NuBusFPGA/nubus-to-ztex-gateware
2024-05-18 10:24:27 +02:00
..
ConsoleTest update to first tested version 2022-04-17 11:25:48 +02:00
hdl-util_hdmi@3200da4fc9 update, including support for ROM-in-builtin-flash 2023-10-14 10:37:15 +02:00
NuBusFPGAHDMIAudio HDMIAudio pick HW info from RSRC 2023-10-12 22:57:02 +02:00
NuBusFPGAInit track HW changes 2022-09-11 14:36:14 +02:00
REF_20240223 updat e REF 2024-02-24 10:25:24 +01:00
VintageBusFPGA_Common@56129b4ddc updat e REF 2024-02-24 10:25:24 +01:00
XiBus@e20f6ca7c4 move to submodules XiBus 2022-10-31 15:28:08 +01:00
.gitignore update, including support for ROM-in-builtin-flash 2023-10-14 10:37:15 +02:00
74fct245.v push to github 2021-12-21 08:26:30 +01:00
do_V1.2 updat e REF 2024-02-24 10:25:24 +01:00
MakeFile push to github 2021-12-21 08:26:30 +01:00
mdio.py 'alt' hdmi from framebuffer, ROM config from gateware, settable pixel clock for non-alt hdmi 2024-02-17 08:38:17 +01:00
nubus_arbiter.v update to first tested version 2022-04-17 11:25:48 +02:00
nubus_cpld.ucf update to first tested version 2022-04-17 11:25:48 +02:00
nubus_cpld.v typo 2022-11-01 11:34:06 +01:00
nubus_cpldinfpga.v typos 2022-11-01 12:41:58 +01:00
nubus_cpu_wb.py Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
nubus_fpga_V1_0_timings.xdc missing entries (???) 2022-09-20 23:11:59 +02:00
nubus_full_unified.py V1.2 bringup 2023-04-17 22:55:22 +02:00
nubus_master_tst.py stat module 2022-06-04 18:56:41 +02:00
nubus_mem_wb.py buffers (fifo) write from NuBus to Wishbone, to improve write BW 2022-05-30 13:15:20 +02:00
nubus_memfifo_wb.py pingmaster sort-of-work 2022-05-30 19:06:33 +02:00
nubus_sampling.v DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
nubus_stat.py stat module 2022-06-04 18:56:41 +02:00
nubus_to_fpga_export.py move SDRAM init from HW to SW 2023-01-27 22:25:12 +01:00
nubus_to_fpga_soc.py board-based name 2024-05-18 10:24:27 +02:00
nubus_V1_0.py support both version for now 2022-11-01 15:42:59 +01:00
nubus_V1_0.v renames 2022-11-01 15:34:02 +01:00
nubus_V1_2.py track V1.2 pcb update 2023-01-14 11:03:01 +01:00
nubus_V1_2.v renames files to V1_2 2022-11-01 15:31:34 +01:00
nubus-to-ztex-io-signal.xdc more stuff thinking about V1.2 2022-11-01 09:29:34 +01:00
nubus-to-ztex-pin-signal.xdc update xdc 2022-11-01 09:45:57 +01:00
post_process_timings.sh update to first tested version 2022-04-17 11:25:48 +02:00
README.md more comments 2023-05-08 15:55:54 +02:00
slave_tb.sv draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel 2022-06-06 23:36:43 +02:00
slave_V1.2_tb.sv fix V1.2 TB 2022-11-01 14:37:20 +01:00
sn74cb3t3125.v fix V1.2 TB 2022-11-01 14:37:20 +01:00
sn74cb3t3245.v fix V1.2 TB 2022-11-01 14:37:20 +01:00
sn74lvt125.v more updates 2022-01-29 11:03:47 +01:00
ztex213_nubus.py move some of board platform stuff to common 2023-11-18 10:06:51 +01:00

Compiling

Rom

Compiling the Declaration Rom (in DeclRom) requires the Retro68 toolchain.

The beginning of the Makefile in DeclROM/ needs to be adapted to point to the toolchain.

Microcode for acceleration

Compiling the acceleration code for the Framebuffer requires a RISC-V toolchain.

The script blit_goblin_nubus.sh in VintageBusFPGA_Common/ needs to be adapted to point to the appropriate toolchain.

Bitstream

Generating the bitstream requires Vivado, 2022 or newer should do. It also requires Litex, see for instance Linux-on-Litex-VexRiscv.

You will need LItex working, and an usable Vivado in yout $PATH.

Known issues

dependencies

There's an interesting issue where you need the DeclRom to generate the bitstream (by defualt the Rom is emebedded in it), but you need CSR headers created during the generation of the bitstream to compile the Declaration Rom. A simple workaround is to create a Rom file with a kilobyte or two of fake data, generate the bitstream, then compile the declaration rom, then re-generate the bitsteam with the proper Rom.

timings

While the main part of the design should be fine in terms of timings, some of the HDMI part isn't. At FullHD resolution (1920x1080 @ 60Hz)), It is 'normal' to have -0.808ns of WPWS, with 9 endpoints failing, in the hdmi5x_clk domain. It doesn't seem to affect the display. This is using the V1.2 54 MHz clock to Bank 34; using the primary 48 MHz clock instead (as in V1.0), the hdmi_clk is a 148.8 MHz instead of 148.5 and the WPPS is -0.811 instead (the 5x clock is at 744 Mhz instead of 742.5 MHz).

physical

The HDMI connector is low-riding on the PCB. The Mac case gets in the the HDMI plug from the cable, thus pushing the NuBusFPGA slightly out of verticality.

Also when plugging a PMod in the PMod connector, the soldered through-hole pins are dangerously close of the Mac shielding. An extra layer of insulation is recommended to avoid short-circuit.