351 lines
10 KiB
C
351 lines
10 KiB
C
#include "NuBusFPGARAMDskDrvr.h"
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/* #include <DriverServices.h> */
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__attribute__ ((section (".text.dskdriver"))) static inline void waitSome(unsigned long bound) {
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unsigned long i;
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for (i = 0 ; i < bound ; i++) {
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asm volatile("nop");
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}
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}
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// CLEANME: use the proper CSR accessor from nubusfpga_csr_exchange_with_mem.h
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#ifdef ENABLE_DMA
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__attribute__ ((section (".text.dskdriver"))) static void startOneOp(struct RAMDrvContext *ctx, const AuxDCEPtr dce) {
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if (ctx->op.blk_todo > 0) {
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ctx->op.blk_doing = ctx->op.blk_todo;
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if (ctx->op.blk_doing > 65535) { // fixme: read HW max
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ctx->op.blk_doing = 32768; // nice Po2
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}
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write_reg(dce, DMA_BLK_ADDR, revb(ctx->dma_blk_base + ctx->op.blk_offset));
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write_reg(dce, DMA_DMA_ADDR, revb((uint32_t)(ctx->op.ioBuffer + (ctx->op.blk_done << ctx->dma_blk_size_shift))));
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ctx->op.blk_done += ctx->op.blk_doing;
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ctx->op.blk_todo -= ctx->op.blk_doing;
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ctx->op.blk_offset += ctx->op.blk_doing;
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write_reg(dce, DMA_BLK_CNT, revb((ctx->op.write ? 0x80000000ul : 0x00000000ul) | ctx->op.blk_doing));
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}
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}
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#endif
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#ifdef ENABLE_DMA
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__attribute__ ((section (".text.dskdriver"))) static OSErr waitForHW(struct RAMDrvContext *ctx, const AuxDCEPtr dce) {
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unsigned long count, max_count, delay;
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unsigned long blk_cnt, status;
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OSErr ret = noErr;
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max_count = 32 * ctx->op.blk_doing;
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delay = (ctx->op.blk_doing >> 4);
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if (delay > 65536)
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delay = 65536;
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waitSome(delay);
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count = 0;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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while (((blk_cnt != 0) ||
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(status != 0)) &&
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(count < max_count)) {
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count ++;
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waitSome(delay);
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if (blk_cnt) blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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if (status) status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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}
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if (blk_cnt || status) {
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ret = ctx->op.write ? writErr : readErr;
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}
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return ret;
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}
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#endif
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#ifdef ENABLE_DMA
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/* see the comment for the FB irq */
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#pragma parameter __D0 dskIrq(__A1)
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__attribute__ ((section (".text.dskdriver"))) short dskIrq(const long sqParameter) {
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register unsigned long p_D1 asm("d1"), p_D2 asm("d2");
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AuxDCEPtr dce;
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struct RAMDrvContext *ctx;
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unsigned int irq;
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short ret;
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asm volatile("" : "+d" (p_D1), "+d" (p_D2));
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dce = (AuxDCEPtr)sqParameter;
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ctx = *(struct RAMDrvContext**)dce->dCtlStorage;
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ret = 0;
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irq = revb(read_reg(dce, DMA_IRQSTATUS));
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if (irq & 1) {
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unsigned int irqctrl = revb(read_reg(dce, DMA_IRQ_CTL));
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irqctrl |= 0x2; // irq clear
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write_reg(dce, DMA_IRQ_CTL, revb(irqctrl));
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if (ctx->op.blk_todo > 0) {
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startOneOp(ctx, dce);
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} else {
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if (ctx->op.blk_doing > 0) {
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ctx->op.blk_doing = 0; // reset just in case
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IODone((DCtlPtr)dce, noErr);
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}
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}
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ret = 1;
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}
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asm volatile("" : : "d" (p_D1), "d" (p_D2));
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return ret;
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}
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#endif
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#ifdef ENABLE_DMA
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__attribute__ ((section (".text.dskdriver"))) static OSErr doAsync(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce, struct RAMDrvContext *ctx) {
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OSErr ret = noErr;
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unsigned char* superslot = (unsigned char*)(((unsigned long)ctx->slot) << 28ul);
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unsigned long abs_offset = 0;
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/* IOParamPtr: Devices 1-53 (p73) */
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/* **** WHERE **** */
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switch(pb->ioPosMode & 0x000F) { // ignore rdVerify
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case fsAtMark:
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abs_offset = dce->dCtlPosition;
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break;
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case fsFromStart:
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abs_offset = pb->ioPosOffset;
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break;
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case fsFromMark:
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abs_offset = dce->dCtlPosition + pb->ioPosOffset;
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break;
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default:
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break;
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}
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/* **** WHAT **** */
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/* Devices 1-33 (p53) */
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if ((pb->ioTrap & 0x00FF) == aRdCmd) {
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if(!(pb->ioPosMode & 0x40)) { // rdVerify, let's ignore it for now
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unsigned long blk_cnt, status;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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if ((blk_cnt == 0) && (status == 0)) {
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ctx->op.blk_todo = pb->ioReqCount >> ctx->dma_blk_size_shift;
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ctx->op.blk_done = 0;
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ctx->op.blk_offset = abs_offset >> ctx->dma_blk_size_shift;
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ctx->op.ioBuffer = pb->ioBuffer;
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ctx->op.write = 0;
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/* should we do it now ? */
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pb->ioActCount = pb->ioReqCount;
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dce->dCtlPosition = abs_offset + pb->ioReqCount;
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pb->ioPosOffset = dce->dCtlPosition;
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if (ctx->op.blk_todo > 0) {
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startOneOp(ctx, dce);
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goto done;
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}
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}
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if (blk_cnt || status) {
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ret = readErr;
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goto done;
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}
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}
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} else if ((pb->ioTrap & 0x00FF) == aWrCmd) {
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unsigned long blk_cnt, status;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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if ((blk_cnt == 0) && (status == 0)) {
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ctx->op.blk_todo = pb->ioReqCount >> ctx->dma_blk_size_shift;
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ctx->op.blk_done = 0;
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ctx->op.blk_offset = abs_offset >> ctx->dma_blk_size_shift;
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ctx->op.ioBuffer = pb->ioBuffer;
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ctx->op.write = 1;
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/* should we do it now ? */
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pb->ioActCount = pb->ioReqCount;
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dce->dCtlPosition = abs_offset + pb->ioReqCount;
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pb->ioPosOffset = dce->dCtlPosition;
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if (ctx->op.blk_todo > 0) {
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startOneOp(ctx, dce);
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goto done;
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}
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}
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if (blk_cnt || status) {
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ret = writErr;
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goto done;
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}
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} else {
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ret = paramErr;
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goto done;
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}
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done:
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return ret;
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}
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#endif // ENABLE_DMA
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__attribute__ ((section (".text.dskdriver"))) static OSErr doSync(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce, struct RAMDrvContext *ctx) {
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OSErr ret = noErr;
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unsigned char* superslot = (unsigned char*)(((unsigned long)ctx->slot) << 28ul);
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unsigned long abs_offset = 0;
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/* IOParamPtr: Devices 1-53 (p73) */
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/* **** WHERE **** */
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switch(pb->ioPosMode & 0x000F) { // ignore rdVerify
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case fsAtMark:
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abs_offset = dce->dCtlPosition;
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break;
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case fsFromStart:
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abs_offset = pb->ioPosOffset;
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break;
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case fsFromMark:
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abs_offset = dce->dCtlPosition + pb->ioPosOffset;
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break;
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default:
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break;
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}
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/* **** WHAT **** */
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/* Devices 1-33 (p53) */
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if ((pb->ioTrap & 0x00FF) == aRdCmd) {
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if(!(pb->ioPosMode & 0x40)) { // rdVerify, let's ignore it for now
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#ifdef ENABLE_DMA
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/* write_reg(dce, GOBOFB_DEBUG, 0xD1580000); */
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/* write_reg(dce, GOBOFB_DEBUG, (unsigned long)pb->ioBuffer); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioReqCount); */
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if ((((unsigned long)pb->ioBuffer & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)pb->ioReqCount & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)abs_offset & ctx->dma_blk_size_mask) == 0)) {
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unsigned long blk_cnt, status;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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if ((blk_cnt == 0) && (status == 0)) {
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ctx->op.blk_todo = pb->ioReqCount >> ctx->dma_blk_size_shift;
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ctx->op.blk_done = 0;
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ctx->op.blk_offset = abs_offset >> ctx->dma_blk_size_shift;
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ctx->op.ioBuffer = pb->ioBuffer;
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ctx->op.write = 0;
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while (ctx->op.blk_todo > 0) {
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startOneOp(ctx, dce);
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ret = waitForHW(ctx, dce);
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if (ret != noErr)
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goto done;
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}
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}
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if (blk_cnt || status) {
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ret = readErr;
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goto done;
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}
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} else
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#endif
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{
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BlockMoveData((superslot + abs_offset), pb->ioBuffer, pb->ioReqCount);
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}
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}
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pb->ioActCount = pb->ioReqCount;
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dce->dCtlPosition = abs_offset + pb->ioReqCount;
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pb->ioPosOffset = dce->dCtlPosition;
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} else if ((pb->ioTrap & 0x00FF) == aWrCmd) {
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#ifdef ENABLE_DMA
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/* write_reg(dce, GOBOFB_DEBUG, 0xD1580001); */
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/* write_reg(dce, GOBOFB_DEBUG, (unsigned long)pb->ioBuffer); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioReqCount); */
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if ((((unsigned long)pb->ioBuffer & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)pb->ioReqCount & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)abs_offset & ctx->dma_blk_size_mask) == 0)) {
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unsigned long blk_cnt, status;
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blk_cnt = revb(read_reg(dce, DMA_BLK_CNT)) & 0xFFFF;
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status = revb(read_reg(dce, DMA_STATUS)) & DMA_STATUS_CHECK_BITS;
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if ((blk_cnt == 0) && (status == 0)) {
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ctx->op.blk_todo = pb->ioReqCount >> ctx->dma_blk_size_shift;
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ctx->op.blk_done = 0;
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ctx->op.blk_offset = abs_offset >> ctx->dma_blk_size_shift;
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ctx->op.ioBuffer = pb->ioBuffer;
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ctx->op.write = 1;
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while (ctx->op.blk_todo > 0) {
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startOneOp(ctx, dce);
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ret = waitForHW(ctx, dce);
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if (ret != noErr)
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goto done;
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}
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}
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if (blk_cnt || status) {
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ret = writErr;
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goto done;
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}
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} else
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#endif
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{
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BlockMoveData(pb->ioBuffer, (superslot + abs_offset), pb->ioReqCount);
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}
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pb->ioActCount = pb->ioReqCount;
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dce->dCtlPosition = abs_offset + pb->ioReqCount;
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pb->ioPosOffset = dce->dCtlPosition;
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} else {
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ret = paramErr;
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goto done;
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}
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done:
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ctx->op.blk_doing = 0;
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return ret;
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}
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/* Devices 1-34 (p54) */
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#pragma parameter __D0 cNuBusFPGARAMDskPrime(__A0, __A1)
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OSErr cNuBusFPGARAMDskPrime(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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{
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OSErr ret = noErr;
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struct RAMDrvContext *ctx;
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unsigned long abs_offset = 0;
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/* IOParamPtr: Devices 1-53 (p73) */
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/* **** WHERE **** */
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switch(pb->ioPosMode & 0x000F) { // ignore rdVerify
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case fsAtMark:
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abs_offset = dce->dCtlPosition;
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break;
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case fsFromStart:
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abs_offset = pb->ioPosOffset;
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break;
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case fsFromMark:
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abs_offset = dce->dCtlPosition + pb->ioPosOffset;
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break;
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default:
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break;
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}
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/* write_reg(dce, GOBOFB_DEBUG, 0xDEAD0003); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioTrap); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioPosMode); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioReqCount); */
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/* write_reg(dce, GOBOFB_DEBUG, pb->ioPosOffset); */
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ctx = *(struct RAMDrvContext**)dce->dCtlStorage;
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if (ctx) {
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#ifdef ENABLE_DMA
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if ((((unsigned long)pb->ioBuffer & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)pb->ioReqCount & ctx->dma_blk_size_mask) == 0) &&
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(((unsigned long)abs_offset & ctx->dma_blk_size_mask) == 0) &&
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(!(pb->ioTrap & (1<<noQueueBit)))) {
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ret = changeRAMDskIRQ(dce, 1, (pb->ioTrap & 0x00FF) == aWrCmd ? writErr : readErr);
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if (ret != noErr) {
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IODone((DCtlPtr)dce, ret);
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goto done;
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}
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// DMA-ifiable & queuable, go async
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ret = doAsync(pb, dce, ctx);
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// no IODone if ongoing, done at interrupt time
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if (ret != noErr)
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IODone((DCtlPtr)dce, ret);
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goto done;
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} else
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#endif
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{
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#ifdef ENABLE_DMA
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ret = changeRAMDskIRQ(dce, 0, (pb->ioTrap & 0x00FF) == aWrCmd ? writErr : readErr);
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#endif
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if (ret)
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goto done;
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ret = doSync(pb, dce, ctx);
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if (!(pb->ioTrap & (1<<noQueueBit))) {
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IODone((DCtlPtr)dce, ret);
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}
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goto done;
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}
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} else {
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ret = offLinErr; /* r/w requested for an off-line drive */
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if (!(pb->ioTrap & (1<<noQueueBit)))
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IODone((DCtlPtr)dce, ret);
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goto done;
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}
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done:
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return ret;
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}
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