NuBusFPGA/nubus-to-ztex-gateware
Romain Dolbeau d52bda7883 fix V1.2 TB
2022-11-01 14:37:20 +01:00
..
ConsoleTest
DeclROM DMA + IRQ for RAM Disk 2022-10-08 18:23:01 +02:00
NuBusFPGAInit track HW changes 2022-09-11 14:36:14 +02:00
VintageBusFPGA_Common@c7d117677e update submodule 2022-11-01 09:08:20 +01:00
XiBus@e20f6ca7c4 move to submodules XiBus 2022-10-31 15:28:08 +01:00
.gitignore LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
74fct245.v
CG6.scala commit current Vex config 2022-06-05 18:04:00 +02:00
DepVideoEqu.a
do DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
GenGoblinAccel.scala LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650 2022-06-24 23:37:18 +02:00
Goblin2c.scala Rounding FMA 2022-08-27 08:30:21 +02:00
Goblin.scala Rounding FMA 2022-08-27 08:30:21 +02:00
MakeFile
nubus_arbiter.v
nubus_cpld.ucf
nubus_cpld.v typo 2022-11-01 11:34:06 +01:00
nubus_cpldinfpga.v typos 2022-11-01 12:41:58 +01:00
nubus_cpu_wb.py Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag) 2022-05-15 14:43:15 +02:00
nubus_fpga_V1_0_timings.xdc missing entries (???) 2022-09-20 23:11:59 +02:00
nubus_full_sampling.py DMA + IRQ for RAM Disk 2022-10-08 18:23:01 +02:00
nubus_full.py DMA + IRQ for RAM Disk 2022-10-08 18:23:01 +02:00
nubus_master_tst.py stat module 2022-06-04 18:56:41 +02:00
nubus_mem_wb.py buffers (fifo) write from NuBus to Wishbone, to improve write BW 2022-05-30 13:15:20 +02:00
nubus_memfifo_wb.py pingmaster sort-of-work 2022-05-30 19:06:33 +02:00
nubus_sampling.v DMA debug with XiBus NuBus & add alternate Migen implementation of NuBus 2022-06-04 09:53:09 +02:00
nubus_stat.py stat module 2022-06-04 18:56:41 +02:00
nubus_to_fpga_export.py
nubus_to_fpga_soc.py typos 2022-11-01 12:41:58 +01:00
nubus-to-ztex-io-signal.xdc more stuff thinking about V1.2 2022-11-01 09:29:34 +01:00
nubus-to-ztex-pin-signal.xdc update xdc 2022-11-01 09:45:57 +01:00
nubus.py typo 2022-11-01 14:36:46 +01:00
nubus.v draft integration of CPLD in FPGA - can't have internal tri-state signals... 2022-11-01 11:36:51 +01:00
NuBusFPGADrvr.a
NuBusFPGAPrimaryInit.a
NuBusFPGASecondaryInit.a
post_process_timings.sh
rom.a
sdram_init.py move wb_master to common 2022-10-31 17:02:21 +01:00
slave_tb.sv draft non-synchronous NuBus (using sampling at sysclk to cut down on latency), minimalist support for 1/2/4 accel 2022-06-06 23:36:43 +02:00
slave_V1.2_tb.sv fix V1.2 TB 2022-11-01 14:37:20 +01:00
sn74cb3t3125.v fix V1.2 TB 2022-11-01 14:37:20 +01:00
sn74cb3t3245.v fix V1.2 TB 2022-11-01 14:37:20 +01:00
sn74lvt125.v
ztex213_nubus.py typos 2022-11-01 12:41:58 +01:00