From 258da24a7a39098eb34a0840a8de19cbb47d2e19 Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Sun, 15 Apr 2018 22:10:01 +1000 Subject: [PATCH] Added V5.1 support, XEBEC support, and fixed some bugs. --- CHANGELOG | 10 + software/SCSI2SD/src/bits.c | 3 - software/SCSI2SD/src/cdrom.c | 3 - software/SCSI2SD/src/config.c | 17 +- software/SCSI2SD/src/diagnostic.c | 4 - software/SCSI2SD/src/disk.c | 5 +- software/SCSI2SD/src/inquiry.c | 5 +- software/SCSI2SD/src/led.c | 5 +- software/SCSI2SD/src/main.c | 6 +- software/SCSI2SD/src/mo.c | 3 - software/SCSI2SD/src/mode.c | 8 +- software/SCSI2SD/src/scsi.c | 89 +- software/SCSI2SD/src/scsiPhy.c | 53 +- software/SCSI2SD/src/scsiPhy.h | 12 +- software/SCSI2SD/src/sd.c | 3 - software/SCSI2SD/src/tape.c | 4 - software/SCSI2SD/src/time.c | 3 - software/SCSI2SD/src/vendor.c | 21 + .../Generated_Source/PSoC5/cyfitter.h | 216 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 3291 ++-- .../Generated_Source/PSoC5/cyfittergnu.inc | 216 +- .../Generated_Source/PSoC5/cyfitteriar.inc | 216 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 216 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx | 18 +- .../SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 241992 -> 241920 bytes software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd | 10 +- .../v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v | 2 - .../Generated_Source/PSoC5/cyfitter.h | 242 +- .../Generated_Source/PSoC5/cyfitter_cfg.c | 3228 ++-- .../Generated_Source/PSoC5/cyfittergnu.inc | 242 +- .../Generated_Source/PSoC5/cyfitteriar.inc | 242 +- .../Generated_Source/PSoC5/cyfitterrv.inc | 242 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx | 20 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 244057 -> 238287 bytes software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd | 12 +- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 252646 -> 252646 bytes .../SCSI2SD/v5.1/SCSI2SD.cydsn/.gitignore | 7 + .../Generated_Source/PSoC5/.USBFS_boot.c.swp | Bin 0 -> 16384 bytes .../Generated_Source/PSoC5/Bootloadable_1.c | 270 + .../Generated_Source/PSoC5/Bootloadable_1.h | 200 + .../Generated_Source/PSoC5/CFG_EEPROM.c | 730 + .../Generated_Source/PSoC5/CFG_EEPROM.h | 79 + .../Generated_Source/PSoC5/Cm3Iar.icf | 160 + .../Generated_Source/PSoC5/Cm3RealView.scat | 228 + .../Generated_Source/PSoC5/Cm3Start.c | 503 + .../Generated_Source/PSoC5/CyBootAsmGnu.s | 161 + .../Generated_Source/PSoC5/CyBootAsmIar.s | 156 + .../Generated_Source/PSoC5/CyBootAsmRv.s | 161 + .../Generated_Source/PSoC5/CyDmac.c | 1039 + .../Generated_Source/PSoC5/CyDmac.h | 228 + .../Generated_Source/PSoC5/CyFlash.c | 684 + .../Generated_Source/PSoC5/CyFlash.h | 322 + .../Generated_Source/PSoC5/CyLib.c | 2928 +++ .../Generated_Source/PSoC5/CyLib.h | 1320 ++ .../Generated_Source/PSoC5/CySpc.c | 693 + .../Generated_Source/PSoC5/CySpc.h | 168 + .../Generated_Source/PSoC5/Debug_Timer.c | 774 + .../Generated_Source/PSoC5/Debug_Timer.h | 434 + .../PSoC5/Debug_Timer_Interrupt.c | 409 + .../PSoC5/Debug_Timer_Interrupt.h | 70 + .../Generated_Source/PSoC5/Debug_Timer_PM.c | 162 + .../Generated_Source/PSoC5/EXTLED.c | 226 + .../Generated_Source/PSoC5/EXTLED.h | 165 + .../Generated_Source/PSoC5/EXTLED_aliases.h | 36 + .../Generated_Source/PSoC5/LED1.c | 231 + .../Generated_Source/PSoC5/LED1.h | 166 + .../Generated_Source/PSoC5/LED1_aliases.h | 39 + .../Generated_Source/PSoC5/SCSI_ATN.c | 137 + .../Generated_Source/PSoC5/SCSI_ATN.h | 130 + .../Generated_Source/PSoC5/SCSI_ATN_aliases.h | 34 + .../Generated_Source/PSoC5/SCSI_CLK.c | 521 + .../Generated_Source/PSoC5/SCSI_CLK.h | 124 + .../Generated_Source/PSoC5/SCSI_CTL_IO.c | 63 + .../Generated_Source/PSoC5/SCSI_CTL_IO.h | 42 + .../Generated_Source/PSoC5/SCSI_CTL_PHASE.c | 65 + .../Generated_Source/PSoC5/SCSI_CTL_PHASE.h | 59 + .../PSoC5/SCSI_CTL_PHASE_PM.c | 109 + .../Generated_Source/PSoC5/SCSI_Filtered.c | 134 + .../Generated_Source/PSoC5/SCSI_Filtered.h | 75 + .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.c | 65 + .../Generated_Source/PSoC5/SCSI_Glitch_Ctl.h | 59 + .../PSoC5/SCSI_Glitch_Ctl_PM.c | 109 + .../Generated_Source/PSoC5/SCSI_In.c | 226 + .../Generated_Source/PSoC5/SCSI_In.h | 165 + .../PSoC5/SCSI_In_DBx_aliases.h | 80 + .../Generated_Source/PSoC5/SCSI_In_aliases.h | 38 + .../PSoC5/SCSI_Noise_aliases.h | 62 + .../Generated_Source/PSoC5/SCSI_Out_Bits.c | 65 + .../Generated_Source/PSoC5/SCSI_Out_Bits.h | 59 + .../Generated_Source/PSoC5/SCSI_Out_Bits_PM.c | 109 + .../Generated_Source/PSoC5/SCSI_Out_Ctl.c | 65 + .../Generated_Source/PSoC5/SCSI_Out_Ctl.h | 59 + .../Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c | 109 + .../PSoC5/SCSI_Out_DBx_aliases.h | 80 + .../Generated_Source/PSoC5/SCSI_Out_aliases.h | 80 + .../PSoC5/SCSI_Parity_Error.c | 134 + .../PSoC5/SCSI_Parity_Error.h | 75 + .../Generated_Source/PSoC5/SCSI_RST.c | 137 + .../Generated_Source/PSoC5/SCSI_RST.h | 130 + .../Generated_Source/PSoC5/SCSI_RST_ISR.c | 409 + .../Generated_Source/PSoC5/SCSI_RST_ISR.h | 70 + .../Generated_Source/PSoC5/SCSI_RST_aliases.h | 34 + .../PSoC5/SCSI_RX_DMA_COMPLETE.c | 409 + .../PSoC5/SCSI_RX_DMA_COMPLETE.h | 70 + .../Generated_Source/PSoC5/SCSI_RX_DMA_dma.c | 141 + .../Generated_Source/PSoC5/SCSI_RX_DMA_dma.h | 35 + .../Generated_Source/PSoC5/SCSI_SEL_ISR.c | 409 + .../Generated_Source/PSoC5/SCSI_SEL_ISR.h | 70 + .../PSoC5/SCSI_TX_DMA_COMPLETE.c | 409 + .../PSoC5/SCSI_TX_DMA_COMPLETE.h | 70 + .../Generated_Source/PSoC5/SCSI_TX_DMA_dma.c | 141 + .../Generated_Source/PSoC5/SCSI_TX_DMA_dma.h | 35 + .../Generated_Source/PSoC5/SDCard.c | 1154 ++ .../Generated_Source/PSoC5/SDCard.h | 373 + .../Generated_Source/PSoC5/SDCard_INT.c | 206 + .../Generated_Source/PSoC5/SDCard_PM.c | 149 + .../Generated_Source/PSoC5/SDCard_PVT.h | 53 + .../Generated_Source/PSoC5/SD_CD.c | 226 + .../Generated_Source/PSoC5/SD_CD.h | 165 + .../Generated_Source/PSoC5/SD_CD_aliases.h | 36 + .../Generated_Source/PSoC5/SD_CS.c | 226 + .../Generated_Source/PSoC5/SD_CS.h | 165 + .../Generated_Source/PSoC5/SD_CS_aliases.h | 36 + .../Generated_Source/PSoC5/SD_Clk_Ctl.c | 63 + .../Generated_Source/PSoC5/SD_Clk_Ctl.h | 42 + .../Generated_Source/PSoC5/SD_Data_Clk.c | 521 + .../Generated_Source/PSoC5/SD_Data_Clk.h | 124 + .../Generated_Source/PSoC5/SD_Init_Clk.c | 521 + .../Generated_Source/PSoC5/SD_Init_Clk.h | 124 + .../Generated_Source/PSoC5/SD_MISO.c | 226 + .../Generated_Source/PSoC5/SD_MISO.h | 165 + .../Generated_Source/PSoC5/SD_MISO_aliases.h | 36 + .../Generated_Source/PSoC5/SD_MOSI.c | 226 + .../Generated_Source/PSoC5/SD_MOSI.h | 165 + .../Generated_Source/PSoC5/SD_MOSI_aliases.h | 36 + .../PSoC5/SD_RX_DMA_COMPLETE.c | 409 + .../PSoC5/SD_RX_DMA_COMPLETE.h | 70 + .../Generated_Source/PSoC5/SD_RX_DMA_dma.c | 141 + .../Generated_Source/PSoC5/SD_RX_DMA_dma.h | 35 + .../Generated_Source/PSoC5/SD_SCK.c | 226 + .../Generated_Source/PSoC5/SD_SCK.h | 165 + .../Generated_Source/PSoC5/SD_SCK_aliases.h | 36 + .../PSoC5/SD_TX_DMA_COMPLETE.c | 409 + .../PSoC5/SD_TX_DMA_COMPLETE.h | 70 + .../Generated_Source/PSoC5/SD_TX_DMA_dma.c | 141 + .../Generated_Source/PSoC5/SD_TX_DMA_dma.h | 35 + .../Generated_Source/PSoC5/TERM_EN.c | 226 + .../Generated_Source/PSoC5/TERM_EN.h | 165 + .../Generated_Source/PSoC5/TERM_EN_aliases.h | 36 + .../Generated_Source/PSoC5/USBFS.c | 2820 +++ .../Generated_Source/PSoC5/USBFS.h | 2081 ++ .../Generated_Source/PSoC5/USBFS_Dm.c | 226 + .../Generated_Source/PSoC5/USBFS_Dm.h | 165 + .../Generated_Source/PSoC5/USBFS_Dm_aliases.h | 36 + .../Generated_Source/PSoC5/USBFS_Dp.c | 226 + .../Generated_Source/PSoC5/USBFS_Dp.h | 165 + .../Generated_Source/PSoC5/USBFS_Dp_aliases.h | 36 + .../Generated_Source/PSoC5/USBFS_audio.c | 380 + .../Generated_Source/PSoC5/USBFS_audio.h | 104 + .../Generated_Source/PSoC5/USBFS_boot.c | 243 + .../Generated_Source/PSoC5/USBFS_cdc.c | 1114 ++ .../Generated_Source/PSoC5/USBFS_cdc.h | 139 + .../Generated_Source/PSoC5/USBFS_cdc.inf | 137 + .../Generated_Source/PSoC5/USBFS_cls.c | 149 + .../Generated_Source/PSoC5/USBFS_cydmac.h | 278 + .../Generated_Source/PSoC5/USBFS_descr.c | 443 + .../Generated_Source/PSoC5/USBFS_drv.c | 796 + .../Generated_Source/PSoC5/USBFS_episr.c | 1354 ++ .../Generated_Source/PSoC5/USBFS_hid.c | 451 + .../Generated_Source/PSoC5/USBFS_hid.h | 71 + .../Generated_Source/PSoC5/USBFS_midi.c | 1391 ++ .../Generated_Source/PSoC5/USBFS_midi.h | 277 + .../Generated_Source/PSoC5/USBFS_msc.c | 150 + .../Generated_Source/PSoC5/USBFS_msc.h | 64 + .../Generated_Source/PSoC5/USBFS_pm.c | 332 + .../Generated_Source/PSoC5/USBFS_pvt.h | 412 + .../Generated_Source/PSoC5/USBFS_std.c | 1262 ++ .../Generated_Source/PSoC5/USBFS_vnd.c | 100 + .../Generated_Source/PSoC5/cm3gcc.ld | 393 + .../Generated_Source/PSoC5/cmsis_armcc.h | 734 + .../Generated_Source/PSoC5/cmsis_gcc.h | 1373 ++ .../Generated_Source/PSoC5/core_cm3.h | 1763 ++ .../Generated_Source/PSoC5/core_cm3_psoc5.h | 52 + .../Generated_Source/PSoC5/core_cmFunc.h | 87 + .../Generated_Source/PSoC5/core_cmInstr.h | 87 + .../Generated_Source/PSoC5/cyPm.c | 1858 ++ .../Generated_Source/PSoC5/cyPm.h | 683 + .../Generated_Source/PSoC5/cybootloader.c | 1241 ++ .../Generated_Source/PSoC5/cybootloader.icf | 3 + .../PSoC5/cycodeshareexport.ld | 0 .../PSoC5/cycodeshareimport.ld | 0 .../PSoC5/cycodeshareimport.scat | 0 .../Generated_Source/PSoC5/cydevice.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevice_trm.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevicegnu.inc | 5357 ++++++ .../PSoC5/cydevicegnu_trm.inc | 5357 ++++++ .../Generated_Source/PSoC5/cydeviceiar.inc | 5356 ++++++ .../PSoC5/cydeviceiar_trm.inc | 5356 ++++++ .../Generated_Source/PSoC5/cydevicerv.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydevicerv_trm.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydisabledsheets.h | 5 + .../Generated_Source/PSoC5/cyfitter.h | 2800 +++ .../Generated_Source/PSoC5/cyfitter_cfg.c | 2178 +++ .../Generated_Source/PSoC5/cyfitter_cfg.h | 30 + .../Generated_Source/PSoC5/cyfittergnu.inc | 2795 +++ .../Generated_Source/PSoC5/cyfitteriar.inc | 2796 +++ .../Generated_Source/PSoC5/cyfitterrv.inc | 2796 +++ .../Generated_Source/PSoC5/cymetadata.c | 54 + .../Generated_Source/PSoC5/cypins.h | 311 + .../Generated_Source/PSoC5/cytypes.h | 1414 ++ .../Generated_Source/PSoC5/cyutils.c | 77 + .../Generated_Source/PSoC5/eeprom.hex | 0 .../PSoC5/exported_symbols.txt | 0 .../Generated_Source/PSoC5/project.h | 87 + .../Generated_Source/PSoC5/protect.hex | 3 + .../PSoC5/renamed_symbols.txt | 0 .../Generated_Source/PSoC5/timer_clock.c | 521 + .../Generated_Source/PSoC5/timer_clock.h | 124 + .../Generated_Source/PSoCCreatorExportIDE.xml | 258 + .../SCSI2SD/v5.1/SCSI2SD.cydsn/OddParityGen | 1 + .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cycdx | 1044 + .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cydwr | 3920 ++++ .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 0 -> 242777 bytes .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj | 2737 +++ .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.svd | 2934 +++ .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 0 -> 319674 bytes software/SCSI2SD/v5.1/SCSI2SD.cydsn/device.h | 18 + .../SCSI2SD/v5.1/SCSI2SD.cydsn/scsiTarget | 1 + .../Generated_Source/PSoC5/.BL.c.swp | Bin 0 -> 16384 bytes .../Generated_Source/PSoC5/BL.c | 1863 ++ .../Generated_Source/PSoC5/BL.h | 355 + .../Generated_Source/PSoC5/BL_PVT.h | 288 + .../Generated_Source/PSoC5/BOOTLDR.c | 226 + .../Generated_Source/PSoC5/BOOTLDR.h | 165 + .../Generated_Source/PSoC5/BOOTLDR_aliases.h | 36 + .../Generated_Source/PSoC5/Cm3Iar.icf | 123 + .../Generated_Source/PSoC5/Cm3RealView.scat | 190 + .../Generated_Source/PSoC5/Cm3Start.c | 539 + .../Generated_Source/PSoC5/CyBootAsmGnu.s | 174 + .../Generated_Source/PSoC5/CyBootAsmIar.s | 156 + .../Generated_Source/PSoC5/CyBootAsmRv.s | 161 + .../Generated_Source/PSoC5/CyDmac.c | 1131 ++ .../Generated_Source/PSoC5/CyDmac.h | 229 + .../Generated_Source/PSoC5/CyFlash.c | 753 + .../Generated_Source/PSoC5/CyFlash.h | 323 + .../Generated_Source/PSoC5/CyLib.c | 3105 +++ .../Generated_Source/PSoC5/CyLib.h | 1361 ++ .../Generated_Source/PSoC5/CySpc.c | 736 + .../Generated_Source/PSoC5/CySpc.h | 168 + .../Generated_Source/PSoC5/LED.c | 147 + .../Generated_Source/PSoC5/LED.h | 130 + .../Generated_Source/PSoC5/LED_aliases.h | 33 + .../PSoC5/SCSI_Out_DBx_aliases.h | 48 + .../Generated_Source/PSoC5/SCSI_Out_aliases.h | 48 + .../Generated_Source/PSoC5/SD_PULLUP.c | 149 + .../Generated_Source/PSoC5/SD_PULLUP.h | 130 + .../PSoC5/SD_PULLUP_aliases.h | 35 + .../Generated_Source/PSoC5/TERM_EN.c | 226 + .../Generated_Source/PSoC5/TERM_EN.h | 165 + .../Generated_Source/PSoC5/TERM_EN_aliases.h | 36 + .../Generated_Source/PSoC5/USBFS.c | 1473 ++ .../Generated_Source/PSoC5/USBFS.h | 1248 ++ .../Generated_Source/PSoC5/USBFS_Dm.c | 146 + .../Generated_Source/PSoC5/USBFS_Dm.h | 130 + .../Generated_Source/PSoC5/USBFS_Dm_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS_Dp.c | 146 + .../Generated_Source/PSoC5/USBFS_Dp.h | 130 + .../Generated_Source/PSoC5/USBFS_Dp_aliases.h | 32 + .../Generated_Source/PSoC5/USBFS_audio.c | 358 + .../Generated_Source/PSoC5/USBFS_audio.h | 98 + .../Generated_Source/PSoC5/USBFS_boot.c | 256 + .../Generated_Source/PSoC5/USBFS_cdc.c | 760 + .../Generated_Source/PSoC5/USBFS_cdc.h | 95 + .../Generated_Source/PSoC5/USBFS_cdc.inf | 122 + .../Generated_Source/PSoC5/USBFS_cls.c | 112 + .../Generated_Source/PSoC5/USBFS_descr.c | 322 + .../Generated_Source/PSoC5/USBFS_drv.c | 788 + .../Generated_Source/PSoC5/USBFS_episr.c | 881 + .../Generated_Source/PSoC5/USBFS_hid.c | 431 + .../Generated_Source/PSoC5/USBFS_hid.h | 67 + .../Generated_Source/PSoC5/USBFS_midi.c | 1382 ++ .../Generated_Source/PSoC5/USBFS_midi.h | 205 + .../Generated_Source/PSoC5/USBFS_pm.c | 285 + .../Generated_Source/PSoC5/USBFS_pvt.h | 218 + .../Generated_Source/PSoC5/USBFS_std.c | 1174 ++ .../Generated_Source/PSoC5/USBFS_vnd.c | 100 + .../Generated_Source/PSoC5/cm3gcc.ld | 295 + .../Generated_Source/PSoC5/core_cm3.h | 1627 ++ .../Generated_Source/PSoC5/core_cm3_psoc5.h | 54 + .../Generated_Source/PSoC5/core_cmFunc.h | 636 + .../Generated_Source/PSoC5/core_cmInstr.h | 688 + .../Generated_Source/PSoC5/cyPm.c | 1873 ++ .../Generated_Source/PSoC5/cyPm.h | 676 + .../PSoC5/cycodeshareexport.ld | 0 .../PSoC5/cycodeshareimport.ld | 0 .../PSoC5/cycodeshareimport.scat | 0 .../Generated_Source/PSoC5/cydevice.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevice_trm.h | 5360 ++++++ .../Generated_Source/PSoC5/cydevicegnu.inc | 5357 ++++++ .../PSoC5/cydevicegnu_trm.inc | 5357 ++++++ .../Generated_Source/PSoC5/cydeviceiar.inc | 5356 ++++++ .../PSoC5/cydeviceiar_trm.inc | 5356 ++++++ .../Generated_Source/PSoC5/cydevicerv.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydevicerv_trm.inc | 16039 ++++++++++++++++ .../Generated_Source/PSoC5/cydisabledsheets.h | 5 + .../Generated_Source/PSoC5/cyfitter.h | 1520 ++ .../Generated_Source/PSoC5/cyfitter_cfg.c | 462 + .../Generated_Source/PSoC5/cyfitter_cfg.h | 30 + .../Generated_Source/PSoC5/cyfittergnu.inc | 1507 ++ .../Generated_Source/PSoC5/cyfitteriar.inc | 1508 ++ .../Generated_Source/PSoC5/cyfitterrv.inc | 1508 ++ .../Generated_Source/PSoC5/cymetadata.c | 126 + .../Generated_Source/PSoC5/cypins.h | 341 + .../Generated_Source/PSoC5/cytypes.h | 560 + .../Generated_Source/PSoC5/cyutils.c | 87 + .../Generated_Source/PSoC5/eeprom.hex | 0 .../PSoC5/exported_symbols.txt | 0 .../Generated_Source/PSoC5/project.h | 57 + .../Generated_Source/PSoC5/protect.hex | 3 + .../PSoC5/renamed_symbols.txt | 0 .../Generated_Source/PSoCCreatorExportIDE.xml | 155 + .../TopDesign/TopDesign.cysch | Bin 0 -> 108779 bytes .../USB_Bootloader.cydsn/USB_Bootloader.cycdx | 105 + .../USB_Bootloader.cydsn/USB_Bootloader.cydwr | 1967 ++ .../USB_Bootloader.cydsn/USB_Bootloader.cyfit | Bin 0 -> 135986 bytes .../USB_Bootloader.cydsn/USB_Bootloader.cyprj | 1206 ++ .../USB_Bootloader.cydsn/USB_Bootloader.rpt | 2866 +++ .../USB_Bootloader.cydsn/USB_Bootloader.svd | 494 + .../USB_Bootloader_timing.html | 644 + .../SCSI2SD/v5.1/USB_Bootloader.cydsn/main.c | 79 + software/include/scsi2sd.h | 24 +- software/scsi2sd-util/BoardPanel.cc | 42 +- software/scsi2sd-util/BoardPanel.hh | 7 +- software/scsi2sd-util/ConfigUtil.cc | 49 +- software/scsi2sd-util/SCSI2SD_Bootloader.cc | 5 + software/scsi2sd-util/TargetPanel.cc | 34 +- software/scsi2sd-util/TargetPanel.hh | 4 +- software/scsi2sd-util/scsi2sd-util.cc | 4 +- 338 files changed, 254348 insertions(+), 4467 deletions(-) mode change 100644 => 100755 software/SCSI2SD/src/mo.c mode change 100644 => 100755 software/SCSI2SD/src/tape.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/.gitignore create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/.USBFS_boot.c.swp create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.h create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/exported_symbols.txt create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/renamed_symbols.txt create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml create mode 120000 software/SCSI2SD/v5.1/SCSI2SD.cydsn/OddParityGen create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cycdx create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cydwr create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.svd create mode 100755 software/SCSI2SD/v5.1/SCSI2SD.cydsn/TopDesign/TopDesign.cysch create mode 100644 software/SCSI2SD/v5.1/SCSI2SD.cydsn/device.h create mode 120000 software/SCSI2SD/v5.1/SCSI2SD.cydsn/scsiTarget create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/.BL.c.swp create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/exported_symbols.txt create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/protect.hex create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoC5/renamed_symbols.txt create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader.cycdx create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader.cydwr create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader.cyfit create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader.cyprj create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader.rpt create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader.svd create mode 100644 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/USB_Bootloader_timing.html create mode 100755 software/SCSI2SD/v5.1/USB_Bootloader.cydsn/main.c diff --git a/CHANGELOG b/CHANGELOG index eab1d80..c9df6b2 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,13 @@ +2018XXXX 4.8 + - Fix Unit Serial Number inquiry page to use return configured serial number + - Apple mode pages now only sent when in Apple mode. + - Added quirks selection to scsi2sd-util. Apple users should manually fix + their settings to use the Apple mode. + - Added specific support for XEBEC controllers. + - Added a speed selection to scsi2sd-util. Users with older SASI or SCSI1 + controllers should select the lower speed for stability. + - Support for v5.1 hardware boards. + 20170501 4.7.1 - Fix scsi2sd-util size and sector-size inputs - Fix crash when configured scsi disk starting sector is less than diff --git a/software/SCSI2SD/src/bits.c b/software/SCSI2SD/src/bits.c index ec8eea7..bec98cf 100755 --- a/software/SCSI2SD/src/bits.c +++ b/software/SCSI2SD/src/bits.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "bits.h" @@ -49,4 +47,3 @@ uint8 countBits(uint8 value) return i; } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/cdrom.c b/software/SCSI2SD/src/cdrom.c index 1c9305f..11f0609 100755 --- a/software/SCSI2SD/src/cdrom.c +++ b/software/SCSI2SD/src/cdrom.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -323,4 +321,3 @@ int scsiCDRomCommand() return commandHandled; } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index 18f476b..c672c31 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "device.h" #include "config.h" @@ -33,7 +31,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0471; +static const uint16_t FIRMWARE_VERSION = 0x0480; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = @@ -142,6 +140,17 @@ writeFlashCommand(const uint8_t* cmd, size_t cmdSize) uint8_t flashArray = cmd[257]; uint8_t flashRow = cmd[258]; + // Be very careful not to overwrite the bootloader or other\r + // code. Bootloader updates no longer supported. Use v5.1 board + // instead. + if ((flashArray != SCSI_CONFIG_ARRAY) || + (flashRow < SCSI_CONFIG_4_ROW) || + (flashRow >= SCSI_CONFIG_3_ROW + SCSI_CONFIG_ROWS)) + { + uint8_t response[] = { CONFIG_STATUS_ERR }; + hidPacket_send(response, sizeof(response)); + } + CySetTemp(); int status = CyWriteRowData(flashArray, flashRow, cmd + 1); @@ -452,5 +461,3 @@ const TargetConfig* getConfigById(int scsiId) return NULL; } - -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/diagnostic.c b/software/SCSI2SD/src/diagnostic.c index c35e6e2..50bdb78 100755 --- a/software/SCSI2SD/src/diagnostic.c +++ b/software/SCSI2SD/src/diagnostic.c @@ -14,9 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") - #include "device.h" #include "scsi.h" #include "diagnostic.h" @@ -218,4 +215,3 @@ void scsiWriteBuffer() } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 7055c34..b825164 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -15,9 +15,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") - #include "device.h" #include "scsi.h" #include "scsiPhy.h" @@ -837,4 +834,4 @@ void scsiDiskInit() #endif } -#pragma GCC pop_options + diff --git a/software/SCSI2SD/src/inquiry.c b/software/SCSI2SD/src/inquiry.c index 9e7c706..5e006ca 100755 --- a/software/SCSI2SD/src/inquiry.c +++ b/software/SCSI2SD/src/inquiry.c @@ -14,9 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") - #include "device.h" #include "scsi.h" #include "config.h" @@ -181,6 +178,7 @@ void scsiInquiry() { memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber)); scsiDev.dataLen = sizeof(UnitSerialNumber); + const TargetConfig* config = scsiDev.target->cfg; memcpy(&scsiDev.data[4], config->serial, sizeof(config->serial)); scsiDev.phase = DATA_IN; } @@ -265,4 +263,3 @@ void scsiInquiry() } } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/led.c b/software/SCSI2SD/src/led.c index 47cc093..4d3b7ee 100755 --- a/software/SCSI2SD/src/led.c +++ b/software/SCSI2SD/src/led.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "led.h" @@ -70,11 +68,10 @@ void ledOn() void ledOff() { - LED1_Write(1); + LED1_Write(0xff); #ifdef HAVE_EXTLED EXTLED_Write(0); #endif } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c index 7678394..e40b2cc 100755 --- a/software/SCSI2SD/src/main.c +++ b/software/SCSI2SD/src/main.c @@ -14,9 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") - #include "device.h" #include "scsi.h" #include "scsiPhy.h" @@ -26,7 +23,7 @@ #include "time.h" #include "trace.h" -const char* Notice = "Copyright (C) 2015 Michael McMaster "; +const char* Notice = "Copyright (C) 2015-2018 Michael McMaster "; int main() { @@ -104,4 +101,3 @@ int main() return 0; } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/mo.c b/software/SCSI2SD/src/mo.c old mode 100644 new mode 100755 index e13acc5..1aa3972 --- a/software/SCSI2SD/src/mo.c +++ b/software/SCSI2SD/src/mo.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -40,4 +38,3 @@ int scsiMOCommand() return commandHandled; } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/mode.c b/software/SCSI2SD/src/mode.c index 112c294..f9d529a 100755 --- a/software/SCSI2SD/src/mode.c +++ b/software/SCSI2SD/src/mode.c @@ -15,9 +15,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") - #include "device.h" #include "scsi.h" #include "mode.h" @@ -476,8 +473,7 @@ static void doModeSense( } if (( - (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) || - (idx + sizeof(AppleVendorPage) <= allocLength) + (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) ) && (pageCode == 0x30 || pageCode == 0x3F)) { @@ -688,5 +684,3 @@ int scsiModeCommand() return commandHandled; } - -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index b3f301b..657868d 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -145,11 +143,13 @@ void process_Status() // OMTI non-standard LINK control if (control & 0x01) { - scsiDev.phase = COMMAND; return; + scsiDev.phase = COMMAND; + return; } } - if ((scsiDev.status == GOOD) && (control & 0x01)) + if ((scsiDev.status == GOOD) && (control & 0x01) && + scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC) { // Linked command. scsiDev.status = INTERMEDIATE; @@ -168,12 +168,31 @@ void process_Status() } - if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI) + if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC) + { + // More non-standardness. Expects 2 status bytes (really status + msg) + // 00 d 000 err 0 + // d == disk number + // ERR = 1 if error. + if (scsiDev.status == GOOD) + { + scsiWriteByte(scsiDev.cdb[1] & 0x20); + } + else + { + scsiWriteByte((scsiDev.cdb[1] & 0x20) | 0x2); + } + CyDelayUs(10); // Seems to need a delay before changing phase bits. + } + else if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI) { scsiDev.status |= (scsiDev.target->targetId & 0x03) << 5; + scsiWriteByte(scsiDev.status); + } + else + { + scsiWriteByte(scsiDev.status); } - - scsiWriteByte(scsiDev.status); scsiDev.lastStatus = scsiDev.status; scsiDev.lastSense = scsiDev.target->sense.code; @@ -279,7 +298,14 @@ static void process_Command() // Prefer LUN's set by IDENTIFY messages for newer hosts. if (scsiDev.lun < 0) { - scsiDev.lun = scsiDev.cdb[1] >> 5; + if (command == 0xE0 || command == 0xE4) // XEBEC s1410 + { + scsiDev.lun = 0; + } + else + { + scsiDev.lun = scsiDev.cdb[1] >> 5; + } } // For Philips P2000C with Xebec S1410 SASI/MFM adapter @@ -319,7 +345,9 @@ static void process_Command() scsiDev.target->sense.asc = SCSI_PARITY_ERROR; enter_Status(CHECK_CONDITION); } - else if ((control & 0x02) && ((control & 0x01) == 0)) + else if ((control & 0x02) && ((control & 0x01) == 0) && + // used for head step options on xebec. + likely(scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC)) { // FLAG set without LINK flag. scsiDev.target->sense.code = ILLEGAL_REQUEST; @@ -335,6 +363,26 @@ static void process_Command() // REQUEST SENSE uint32 allocLength = scsiDev.cdb[4]; + if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC) + { + // Completely non-standard + allocLength = 4; + if (scsiDev.target->sense.code == NO_SENSE) + scsiDev.data[0] = 0; + else if (scsiDev.target->sense.code == ILLEGAL_REQUEST) + scsiDev.data[0] = 0x20; // Illegal command + else if (scsiDev.target->sense.code == NOT_READY) + scsiDev.data[0] = 0x04; // Drive not ready + else + scsiDev.data[0] = 0x11; // Uncorrectable data error + + scsiDev.data[1] = (scsiDev.cdb[1] & 0x20) | ((transfer.lba >> 16) & 0x1F); + scsiDev.data[2] = transfer.lba >> 8; + scsiDev.data[3] = transfer.lba; + + } + else + { // As specified by the SASI and SCSI1 standard. // Newer initiators won't be specifying 0 anyway. if (allocLength == 0) allocLength = 4; @@ -352,6 +400,7 @@ static void process_Command() scsiDev.data[7] = 10; // additional length scsiDev.data[12] = scsiDev.target->sense.asc >> 8; scsiDev.data[13] = scsiDev.target->sense.asc; + } // Silently truncate results. SCSI-2 spec 8.2.14. enter_DataIn(allocLength); @@ -564,7 +613,11 @@ static void process_SelectionPhase() // The Mac Plus boot-time (ie. rom code) selection abort time // is < 1ms and must have no delay (standard suggests 250ms abort time) // Most newer SCSI2 hosts don't care either way. - if (scsiDev.boardCfg.selectionDelay == 255) // auto + if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC) + { + CyDelay(1); // Simply won't work if set to 0. + } + else if (scsiDev.boardCfg.selectionDelay == 255) // auto { if (scsiDev.compatMode < COMPAT_SCSI2) { @@ -580,7 +633,11 @@ static void process_SelectionPhase() int sel = (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL); int bsy = SCSI_ReadFilt(SCSI_Filt_BSY); +#ifdef SCSI_In_IO int io = SCSI_ReadPin(SCSI_In_IO); +#else + int io = 0; +#endif // Only read these pins AFTER SEL and BSY - we don't want to catch them // during a transition period. @@ -601,7 +658,9 @@ static void process_SelectionPhase() } sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL); bsy |= SCSI_ReadFilt(SCSI_Filt_BSY); +#ifdef SCSI_In_IO io |= SCSI_ReadPin(SCSI_In_IO); +#endif if (!bsy && !io && sel && target && (goodParity || !(scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) || !atnFlag) && @@ -663,12 +722,19 @@ static void process_SelectionPhase() } // Wait until the end of the selection phase. + uint32_t selTimerBegin = getTime_ms(); while (likely(!scsiDev.resetFlag)) { if (!SCSI_ReadFilt(SCSI_Filt_SEL)) { break; } + else if (elapsedTime_ms(selTimerBegin) >= 250) + { + SCSI_ClearPin(SCSI_Out_BSY); + scsiDev.resetFlag = 1; + break; + } } scsiDev.phase = COMMAND; @@ -677,7 +743,7 @@ static void process_SelectionPhase() { scsiDev.phase = BUS_BUSY; } - + scsiDev.selFlag = 0; } @@ -1089,4 +1155,3 @@ int scsiReconnect() return reconnected; } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index d9699b3..d0fd43e 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -14,9 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") - #include "device.h" #include "scsi.h" #include "scsiPhy.h" @@ -391,9 +388,8 @@ void scsiEnterPhase(int phase) { // ANSI INCITS 362-2002 SPI-3 10.7.1: // Phase changes are not allowed while REQ or ACK is asserted. - while (likely(!scsiDev.resetFlag) && - (SCSI_ReadPin(SCSI_In_REQ) || SCSI_ReadFilt(SCSI_Filt_ACK)) - ) {} + while (likely(!scsiDev.resetFlag) && SCSI_ReadFilt(SCSI_Filt_ACK)) + {} int newPhase = phase > 0 ? phase : 0; if (newPhase != SCSI_CTL_PHASE_Read()) @@ -403,7 +399,9 @@ void scsiEnterPhase(int phase) if (scsiDev.compatMode < COMPAT_SCSI2) { - CyDelayUs(100); + // XEBEC S1410 manual (old SASI controller) gives 10uSec delay + // between phase bits and REQ. + CyDelayUs(10); } } } @@ -452,9 +450,13 @@ void scsiPhyReset() SCSI_SetPin(SCSI_Out_RST); SCSI_CTL_PHASE_Write(0); + #ifdef SCSI_Out_ATN SCSI_ClearPin(SCSI_Out_ATN); + #endif SCSI_ClearPin(SCSI_Out_BSY); + #ifdef SCSI_Out_ACK SCSI_ClearPin(SCSI_Out_ACK); + #endif SCSI_ClearPin(SCSI_Out_RST); SCSI_ClearPin(SCSI_Out_SEL); SCSI_ClearPin(SCSI_Out_REQ); @@ -512,8 +514,34 @@ void scsiPhyInit() if (scsiDev.boardCfg.flags & CONFIG_DISABLE_GLITCH) { SCSI_Glitch_Ctl_Write(1); + + // Reduce deskew time to 1. (deskew init + 0) CY_SET_REG8(scsiTarget_datapath__D0_REG, 0); } + if ((scsiDev.target->cfg->quirks == CONFIG_QUIRKS_XEBEC) || + (scsiDev.boardCfg.scsiSpeed == CONFIG_SPEED_ASYNC_15)) + { + // 125ns to 250ns deskew time = 3.125 clocks + // - 1 (valid during DESKEW INIT) + // = 2.125. Default is 1. + // Round down because it's going to be doubled anyway due to clock + // divider change below. + CY_SET_REG8(scsiTarget_datapath__D0_REG, 2); + + // Half the SCSI clock as a way to extend the glitch filter. + // This also helps meet the 250ns delays between ACK and reading + // data, or release ack and reassert req. + + // The register contains (divider - 1) + uint16_t clkDiv25MHz = SCSI_CLK_GetDividerRegister(); + SCSI_CLK_SetDivider(((clkDiv25MHz + 1) * 2) - 1); + // Wait for the clock to settle. + CyDelayUs(1); + } + + #ifdef TERM_EN_0 + TERM_EN_Write((scsiDev.boardCfg.flags6 & S2S_CFG_ENABLE_TERMINATOR) ? 0 : 1); + #endif } // 1 = DBx error @@ -546,6 +574,7 @@ int scsiSelfTest() SCSI_Out_Ctl_Write(0); // Write bits normally. // TEST MSG, CD, IO + #ifdef SCSI_In_MSG for (i = 0; i < 8; ++i) { SCSI_CTL_PHASE_Write(i); @@ -564,18 +593,19 @@ int scsiSelfTest() result |= 16; } } + #endif SCSI_CTL_PHASE_Write(0); - uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL }; - uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL }; + uint32_t signalsOut[] = { SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL }; + uint32_t signalsIn[] = { SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL }; - for (i = 0; i < 4; ++i) + for (i = 0; i < 3; ++i) { SCSI_SetPin(signalsOut[i]); scsiDeskewDelay(); int j; - for (j = 0; j < 4; ++j) + for (j = 0; j < 3; ++j) { if (i == j) { @@ -598,4 +628,3 @@ int scsiSelfTest() } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/scsiPhy.h b/software/SCSI2SD/src/scsiPhy.h index 006107b..08676b9 100755 --- a/software/SCSI2SD/src/scsiPhy.h +++ b/software/SCSI2SD/src/scsiPhy.h @@ -37,11 +37,21 @@ typedef enum #define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val)) #define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG) +#ifdef TERM_EN_0 + // V5.1 is active-low +#define SCSI_SetPin(pin) \ + CyPins_ClearPin((pin)); + +#define SCSI_ClearPin(pin) \ + CyPins_SetPin((pin)); +#else + // <= V5.0 is active-high #define SCSI_SetPin(pin) \ CyPins_SetPin((pin)); #define SCSI_ClearPin(pin) \ - CyPins_ClearPin((pin)); + CyPins_ClearPin((pin)); +#endif // Active low: we interpret a 0 as "true", and non-zero as "false" #define SCSI_ReadPin(pin) \ diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index 2755754..6cd9029 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -1018,4 +1016,3 @@ void sdCheckPresent() firstCheck = 0; } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/tape.c b/software/SCSI2SD/src/tape.c old mode 100644 new mode 100755 index 9416a95..522bdd3 --- a/software/SCSI2SD/src/tape.c +++ b/software/SCSI2SD/src/tape.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -29,5 +27,3 @@ int scsiTapeCommand() return 0; } - -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/time.c b/software/SCSI2SD/src/time.c index 3d6b3fe..aad82aa 100755 --- a/software/SCSI2SD/src/time.c +++ b/software/SCSI2SD/src/time.c @@ -14,8 +14,6 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . -#pragma GCC push_options -#pragma GCC optimize("-flto") #include "time.h" #include "limits.h" @@ -70,4 +68,3 @@ uint32_t elapsedTime_ms(uint32_t since) } } -#pragma GCC pop_options diff --git a/software/SCSI2SD/src/vendor.c b/software/SCSI2SD/src/vendor.c index 2fb70b1..eefbaef 100755 --- a/software/SCSI2SD/src/vendor.c +++ b/software/SCSI2SD/src/vendor.c @@ -49,6 +49,27 @@ int scsiVendorCommand() scsiDev.phase = DATA_OUT; scsiDev.postDataOutHook = doAssignDiskParameters; } + else if (command == 0x0C) + { + // Initialize Drive Characteristics + // XEBEC S1410 controller + // http://bitsavers.informatik.uni-stuttgart.de/pdf/xebec/104524C_S1410Man_Aug83.pdf + scsiDev.dataLen = 8; + scsiDev.phase = DATA_OUT; + } + else if (command == 0xE0) + { + // RAM Diagnostic + // XEBEC S1410 controller + // http://bitsavers.informatik.uni-stuttgart.de/pdf/xebec/104524C_S1410Man_Aug83.pdf + // Stub, return success + } + else if (command == 0xE4) + { + // Drive Diagnostic + // XEBEC S1410 controller + // Stub, return success + } else { commandHandled = 0; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 5df9d48..81204e3 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -391,34 +391,34 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -426,13 +426,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB08_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB08_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -450,12 +450,14 @@ #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -463,9 +465,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 @@ -1945,15 +1947,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB08_09_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1966,37 +1968,37 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB08_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB08_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB08_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB08_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB08_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB08_MSK /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -2822,6 +2824,8 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2829,9 +2833,13 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST /* Debug_Timer_Interrupt */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2952,8 +2960,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2961,9 +2969,9 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u @@ -2994,34 +3002,34 @@ /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB07_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB07_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 4fcd68f..3b157aa 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -135,7 +135,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 41u +#define CY_CFG_BASE_ADDR_COUNT 40u CYPACKED typedef struct { uint8 offset; @@ -398,44 +398,43 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010040u, /* Base address: 0x40010000 Count: 64 */ - 0x4001013Bu, /* Base address: 0x40010100 Count: 59 */ - 0x4001024Au, /* Base address: 0x40010200 Count: 74 */ - 0x40010354u, /* Base address: 0x40010300 Count: 84 */ - 0x40010441u, /* Base address: 0x40010400 Count: 65 */ - 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */ - 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ - 0x40010753u, /* Base address: 0x40010700 Count: 83 */ - 0x4001091Du, /* Base address: 0x40010900 Count: 29 */ - 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */ - 0x40010B54u, /* Base address: 0x40010B00 Count: 84 */ - 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ - 0x40010D4Bu, /* Base address: 0x40010D00 Count: 75 */ - 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */ - 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */ - 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */ - 0x40011555u, /* Base address: 0x40011500 Count: 85 */ - 0x40011658u, /* Base address: 0x40011600 Count: 88 */ - 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */ - 0x40011850u, /* Base address: 0x40011800 Count: 80 */ - 0x40011948u, /* Base address: 0x40011900 Count: 72 */ - 0x40011B0Au, /* Base address: 0x40011B00 Count: 10 */ - 0x4001401Au, /* Base address: 0x40014000 Count: 26 */ - 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */ - 0x40014217u, /* Base address: 0x40014200 Count: 23 */ - 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */ - 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */ + 0x4001004Au, /* Base address: 0x40010000 Count: 74 */ + 0x40010142u, /* Base address: 0x40010100 Count: 66 */ + 0x40010248u, /* Base address: 0x40010200 Count: 72 */ + 0x40010355u, /* Base address: 0x40010300 Count: 85 */ + 0x4001045Du, /* Base address: 0x40010400 Count: 93 */ + 0x4001055Au, /* Base address: 0x40010500 Count: 90 */ + 0x40010657u, /* Base address: 0x40010600 Count: 87 */ + 0x4001075Au, /* Base address: 0x40010700 Count: 90 */ + 0x40010851u, /* Base address: 0x40010800 Count: 81 */ + 0x40010953u, /* Base address: 0x40010900 Count: 83 */ + 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */ + 0x40010B45u, /* Base address: 0x40010B00 Count: 69 */ + 0x40010D13u, /* Base address: 0x40010D00 Count: 19 */ + 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */ + 0x4001141Au, /* Base address: 0x40011400 Count: 26 */ + 0x40011550u, /* Base address: 0x40011500 Count: 80 */ + 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */ + 0x40011758u, /* Base address: 0x40011700 Count: 88 */ + 0x40011849u, /* Base address: 0x40011800 Count: 73 */ + 0x40011955u, /* Base address: 0x40011900 Count: 85 */ + 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */ + 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */ + 0x4001411Du, /* Base address: 0x40014100 Count: 29 */ + 0x40014214u, /* Base address: 0x40014200 Count: 20 */ + 0x40014309u, /* Base address: 0x40014300 Count: 9 */ + 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ 0x40014515u, /* Base address: 0x40014500 Count: 21 */ - 0x40014610u, /* Base address: 0x40014600 Count: 16 */ - 0x40014716u, /* Base address: 0x40014700 Count: 22 */ - 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */ - 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ - 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */ - 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */ - 0x40015005u, /* Base address: 0x40015000 Count: 5 */ + 0x40014613u, /* Base address: 0x40014600 Count: 19 */ + 0x40014711u, /* Base address: 0x40014700 Count: 17 */ + 0x40014808u, /* Base address: 0x40014800 Count: 8 */ + 0x4001490Au, /* Base address: 0x40014900 Count: 10 */ + 0x40014C06u, /* Base address: 0x40014C00 Count: 6 */ + 0x40014D06u, /* Base address: 0x40014D00 Count: 6 */ + 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -443,62 +442,55 @@ void cyfitter_cfg(void) {0x7Eu, 0x02u}, {0x01u, 0x20u}, {0x0Au, 0x4Bu}, - {0x00u, 0x12u}, + {0x00u, 0x11u}, {0x01u, 0x03u}, - {0x18u, 0x04u}, + {0x18u, 0x08u}, + {0x19u, 0x04u}, {0x1Cu, 0x71u}, - {0x20u, 0xC0u}, - {0x21u, 0x58u}, + {0x20u, 0xA0u}, + {0x21u, 0x98u}, {0x2Cu, 0x0Eu}, - {0x30u, 0x09u}, - {0x31u, 0x0Au}, + {0x30u, 0x05u}, + {0x31u, 0x09u}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x86u, 0x0Fu}, - {0x01u, 0x33u}, - {0x03u, 0xCCu}, - {0x04u, 0x3Fu}, - {0x08u, 0x04u}, - {0x0Au, 0x08u}, - {0x0Bu, 0xFFu}, - {0x0Eu, 0x3Fu}, + {0x84u, 0x0Fu}, + {0x01u, 0x69u}, + {0x02u, 0x03u}, + {0x03u, 0x96u}, + {0x05u, 0xFFu}, + {0x06u, 0x18u}, + {0x09u, 0x55u}, + {0x0Au, 0x24u}, + {0x0Bu, 0xAAu}, {0x0Fu, 0xFFu}, - {0x10u, 0x10u}, - {0x12u, 0x20u}, - {0x14u, 0x01u}, - {0x15u, 0xFFu}, - {0x16u, 0x02u}, - {0x18u, 0x3Fu}, + {0x10u, 0x24u}, + {0x11u, 0x0Fu}, + {0x12u, 0x09u}, + {0x13u, 0xF0u}, + {0x17u, 0xFFu}, + {0x18u, 0x24u}, {0x19u, 0xFFu}, - {0x1Cu, 0x01u}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0x02u}, - {0x1Fu, 0xF0u}, - {0x20u, 0x10u}, - {0x21u, 0x69u}, + {0x1Au, 0x12u}, {0x22u, 0x20u}, - {0x23u, 0x96u}, - {0x24u, 0x04u}, - {0x25u, 0x55u}, - {0x26u, 0x08u}, - {0x27u, 0xAAu}, - {0x2Au, 0x3Fu}, - {0x2Eu, 0x3Fu}, - {0x2Fu, 0xFFu}, - {0x30u, 0x30u}, - {0x32u, 0x03u}, - {0x34u, 0x0Cu}, - {0x37u, 0xFFu}, - {0x3Au, 0x2Au}, - {0x3Bu, 0x80u}, - {0x40u, 0x52u}, + {0x25u, 0x33u}, + {0x26u, 0x04u}, + {0x27u, 0xCCu}, + {0x2Bu, 0xFFu}, + {0x30u, 0x07u}, + {0x33u, 0xFFu}, + {0x34u, 0x38u}, + {0x39u, 0x80u}, + {0x3Bu, 0x08u}, + {0x3Fu, 0x40u}, + {0x40u, 0x32u}, {0x41u, 0x06u}, - {0x42u, 0x30u}, - {0x45u, 0xDCu}, - {0x46u, 0xE2u}, - {0x47u, 0x0Fu}, - {0x48u, 0x1Fu}, + {0x42u, 0x10u}, + {0x45u, 0x0Du}, + {0x46u, 0x2Eu}, + {0x47u, 0xCFu}, + {0x48u, 0x3Du}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, @@ -517,1422 +509,158 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0xD6u, 0x08u}, - {0xDBu, 0x04u}, - {0xDDu, 0x90u}, - {0x01u, 0x80u}, - {0x02u, 0x08u}, - {0x03u, 0x10u}, - {0x08u, 0x81u}, - {0x0Au, 0x18u}, - {0x10u, 0x40u}, - {0x12u, 0x22u}, - {0x13u, 0x10u}, - {0x19u, 0x04u}, - {0x1Au, 0x90u}, - {0x1Bu, 0x10u}, - {0x20u, 0x02u}, - {0x21u, 0x80u}, - {0x28u, 0x80u}, - {0x29u, 0x80u}, - {0x2Au, 0x04u}, - {0x31u, 0x80u}, - {0x32u, 0x04u}, - {0x33u, 0x10u}, - {0x34u, 0x10u}, - {0x35u, 0x10u}, - {0x39u, 0x80u}, - {0x3Bu, 0x12u}, - {0x43u, 0x14u}, - {0x48u, 0x40u}, - {0x49u, 0x80u}, - {0x4Bu, 0x18u}, - {0x53u, 0x58u}, - {0x58u, 0x40u}, - {0x59u, 0x24u}, - {0x5Au, 0x82u}, - {0x5Fu, 0x80u}, - {0x61u, 0x22u}, - {0x62u, 0x88u}, - {0x63u, 0x20u}, - {0x64u, 0x01u}, - {0x67u, 0x02u}, - {0x68u, 0x94u}, - {0x69u, 0x40u}, - {0x71u, 0x10u}, - {0x72u, 0x82u}, - {0x73u, 0x20u}, - {0x83u, 0x80u}, - {0x85u, 0x04u}, - {0x88u, 0x44u}, - {0x8Du, 0x40u}, - {0xC0u, 0x07u}, - {0xC2u, 0x0Fu}, - {0xC4u, 0x0Fu}, - {0xCAu, 0x0Bu}, - {0xCCu, 0x0Eu}, - {0xCEu, 0x0Du}, - {0xD0u, 0x06u}, - {0xD2u, 0x0Cu}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x1Fu}, - {0xE2u, 0x01u}, - {0xE4u, 0x02u}, - {0xE6u, 0x40u}, - {0x05u, 0x20u}, - {0x07u, 0x40u}, - {0x09u, 0x64u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x02u}, - {0x11u, 0x20u}, - {0x13u, 0x40u}, - {0x15u, 0x03u}, - {0x17u, 0x1Cu}, - {0x19u, 0x69u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x12u}, - {0x23u, 0x01u}, - {0x27u, 0x67u}, - {0x28u, 0x01u}, - {0x29u, 0x08u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x77u}, - {0x2Du, 0x0Bu}, - {0x2Fu, 0x74u}, - {0x31u, 0x60u}, - {0x34u, 0x03u}, - {0x35u, 0x1Fu}, - {0x3Bu, 0x22u}, - {0x3Eu, 0x10u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Fu, 0x01u}, - {0x81u, 0x01u}, - {0x83u, 0x02u}, - {0x84u, 0xFFu}, - {0x85u, 0x3Fu}, - {0x8Bu, 0x3Fu}, - {0x8Eu, 0xFFu}, - {0x8Fu, 0x3Fu}, - {0x90u, 0x0Fu}, - {0x92u, 0xF0u}, - {0x94u, 0x55u}, - {0x95u, 0x3Fu}, - {0x96u, 0xAAu}, - {0x98u, 0xFFu}, - {0x99u, 0x10u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x96u}, - {0x9Du, 0x04u}, - {0x9Eu, 0x69u}, - {0x9Fu, 0x08u}, - {0xA1u, 0x04u}, - {0xA3u, 0x08u}, - {0xA4u, 0x33u}, - {0xA5u, 0x10u}, - {0xA6u, 0xCCu}, - {0xA7u, 0x20u}, - {0xA9u, 0x01u}, - {0xAAu, 0xFFu}, - {0xABu, 0x02u}, - {0xAEu, 0xFFu}, - {0xAFu, 0x3Fu}, - {0xB0u, 0xFFu}, - {0xB1u, 0x03u}, - {0xB5u, 0x30u}, - {0xB7u, 0x0Cu}, - {0xB8u, 0x08u}, - {0xBAu, 0x02u}, - {0xBBu, 0xA2u}, - {0xBEu, 0x04u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x01u, 0x80u}, - {0x03u, 0x10u}, - {0x06u, 0x01u}, - {0x08u, 0x08u}, - {0x09u, 0x80u}, - {0x0Au, 0x88u}, - {0x0Eu, 0x04u}, - {0x12u, 0x22u}, - {0x13u, 0x10u}, - {0x17u, 0x20u}, - {0x18u, 0x20u}, - {0x1Au, 0x80u}, - {0x1Fu, 0x20u}, - {0x21u, 0x21u}, - {0x22u, 0x81u}, - {0x25u, 0x02u}, - {0x26u, 0x01u}, - {0x27u, 0x08u}, - {0x28u, 0x40u}, - {0x29u, 0x90u}, - {0x2Bu, 0x10u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x80u}, - {0x2Eu, 0x20u}, - {0x2Fu, 0x40u}, - {0x31u, 0x20u}, - {0x32u, 0x84u}, - {0x36u, 0x01u}, - {0x37u, 0x18u}, - {0x38u, 0x04u}, - {0x39u, 0x82u}, - {0x3Au, 0x20u}, - {0x3Bu, 0x10u}, - {0x3Cu, 0xA0u}, - {0x3Fu, 0x08u}, - {0x59u, 0x04u}, - {0x5Au, 0x11u}, - {0x5Bu, 0x40u}, - {0x60u, 0x88u}, - {0x61u, 0x80u}, - {0x62u, 0x04u}, - {0x63u, 0x08u}, - {0x80u, 0x10u}, - {0x82u, 0x02u}, - {0x85u, 0x80u}, - {0x89u, 0x04u}, - {0x8Bu, 0x10u}, - {0x8Cu, 0x04u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x10u}, - {0x93u, 0x88u}, - {0x95u, 0x84u}, - {0x96u, 0x0Au}, - {0x97u, 0x10u}, - {0x98u, 0x10u}, - {0x9Au, 0x82u}, - {0x9Cu, 0x80u}, - {0x9Du, 0xA2u}, - {0x9Eu, 0x04u}, - {0x9Fu, 0x14u}, - {0xA0u, 0xC1u}, - {0xA5u, 0x22u}, - {0xA6u, 0xA2u}, - {0xA9u, 0x80u}, - {0xACu, 0x10u}, - {0xAFu, 0x34u}, - {0xB5u, 0x02u}, - {0xB7u, 0x08u}, - {0xC0u, 0x85u}, - {0xC2u, 0x4Fu}, - {0xC4u, 0x47u}, - {0xCAu, 0xFFu}, - {0xCCu, 0xEEu}, - {0xCEu, 0x7Fu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x08u}, - {0xE2u, 0x20u}, - {0xE4u, 0x04u}, - {0xE6u, 0x21u}, - {0xE8u, 0x0Eu}, - {0xEAu, 0x10u}, - {0xECu, 0x0Au}, - {0x02u, 0x1Cu}, - {0x04u, 0x28u}, - {0x05u, 0x10u}, - {0x06u, 0x14u}, - {0x07u, 0x08u}, - {0x0Cu, 0x10u}, - {0x0Du, 0x01u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x02u}, - {0x11u, 0x10u}, - {0x13u, 0x08u}, - {0x19u, 0x08u}, - {0x1Bu, 0x11u}, - {0x1Du, 0x10u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x0Eu}, - {0x22u, 0x20u}, - {0x28u, 0x24u}, - {0x2Au, 0x08u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x08u}, - {0x30u, 0x02u}, - {0x31u, 0x04u}, - {0x33u, 0x03u}, - {0x34u, 0x01u}, - {0x35u, 0x18u}, - {0x36u, 0x3Cu}, - {0x3Bu, 0x20u}, - {0x3Fu, 0x04u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x81u, 0x01u}, - {0x84u, 0x04u}, - {0x86u, 0x43u}, - {0x8Cu, 0x21u}, - {0x8Eu, 0x02u}, - {0x8Fu, 0x01u}, - {0x92u, 0x01u}, - {0x96u, 0xECu}, - {0x98u, 0x88u}, - {0x9Au, 0x03u}, - {0x9Cu, 0xE0u}, - {0x9Du, 0x01u}, - {0xA5u, 0x01u}, - {0xA6u, 0x12u}, - {0xA9u, 0x01u}, - {0xAFu, 0x01u}, - {0xB0u, 0x10u}, - {0xB2u, 0x0Fu}, - {0xB4u, 0xE0u}, - {0xB5u, 0x01u}, - {0xBEu, 0x10u}, - {0xBFu, 0x10u}, - {0xD4u, 0x40u}, - {0xD6u, 0x04u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDFu, 0x01u}, - {0x01u, 0x80u}, - {0x03u, 0x90u}, - {0x04u, 0x44u}, - {0x0Au, 0x02u}, - {0x0Eu, 0xA8u}, - {0x0Fu, 0x01u}, - {0x10u, 0x81u}, - {0x13u, 0x10u}, - {0x15u, 0x08u}, - {0x18u, 0x08u}, - {0x1Bu, 0xC1u}, - {0x1Eu, 0xA0u}, - {0x1Fu, 0x10u}, - {0x20u, 0x20u}, - {0x22u, 0x1Du}, - {0x25u, 0x20u}, - {0x28u, 0x01u}, - {0x2Bu, 0x01u}, - {0x2Cu, 0x08u}, - {0x2Fu, 0x21u}, - {0x32u, 0x91u}, - {0x37u, 0x40u}, - {0x38u, 0x08u}, - {0x39u, 0x40u}, - {0x3Eu, 0x42u}, - {0x45u, 0x20u}, - {0x46u, 0x08u}, - {0x58u, 0x80u}, - {0x5Bu, 0x28u}, - {0x61u, 0x14u}, - {0x62u, 0x80u}, - {0x63u, 0x20u}, - {0x66u, 0x18u}, - {0x67u, 0x42u}, - {0x69u, 0x40u}, - {0x6Du, 0x94u}, - {0x80u, 0x08u}, - {0x85u, 0x50u}, - {0x88u, 0x80u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x41u}, - {0x91u, 0x80u}, - {0x92u, 0x80u}, - {0x93u, 0x88u}, - {0x95u, 0x04u}, - {0x96u, 0x0Cu}, - {0x97u, 0x10u}, - {0x98u, 0x10u}, - {0x9Au, 0x84u}, - {0x9Cu, 0x40u}, - {0x9Du, 0xB2u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0x14u}, - {0xA0u, 0xC1u}, - {0xA1u, 0x01u}, - {0xA4u, 0x10u}, - {0xA6u, 0x20u}, - {0xA7u, 0x10u}, - {0xA8u, 0x20u}, - {0xA9u, 0x40u}, - {0xAAu, 0x02u}, - {0xABu, 0x60u}, - {0xB2u, 0x01u}, - {0xB5u, 0x01u}, - {0xB7u, 0x28u}, - {0xC0u, 0xADu}, - {0xC2u, 0xF1u}, - {0xC4u, 0x2Bu}, - {0xCAu, 0x78u}, - {0xCCu, 0x1Du}, - {0xCEu, 0x9Au}, - {0xD6u, 0x0Eu}, - {0xD8u, 0xFEu}, - {0xE6u, 0x04u}, - {0xEAu, 0x01u}, - {0xEEu, 0x49u}, - {0x02u, 0x10u}, - {0x04u, 0x01u}, - {0x05u, 0x0Au}, - {0x07u, 0x55u}, - {0x08u, 0x01u}, - {0x09u, 0x8Bu}, - {0x0Bu, 0x74u}, - {0x0Cu, 0x01u}, - {0x0Fu, 0x10u}, - {0x12u, 0x01u}, - {0x14u, 0x12u}, - {0x15u, 0x20u}, - {0x16u, 0x04u}, - {0x17u, 0x40u}, - {0x19u, 0x40u}, - {0x1Au, 0x0Eu}, - {0x1Bu, 0x80u}, - {0x1Cu, 0x08u}, - {0x1Eu, 0x10u}, - {0x23u, 0x7Fu}, - {0x25u, 0x01u}, - {0x28u, 0x14u}, - {0x29u, 0x06u}, - {0x2Au, 0x0Au}, - {0x2Cu, 0x01u}, - {0x2Du, 0x91u}, - {0x2Fu, 0x6Cu}, - {0x32u, 0x01u}, - {0x33u, 0x3Fu}, - {0x34u, 0x1Eu}, - {0x35u, 0xC0u}, - {0x36u, 0x01u}, - {0x3Bu, 0x20u}, - {0x3Eu, 0x44u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Fu, 0x01u}, - {0x82u, 0x7Fu}, - {0x84u, 0x78u}, - {0x86u, 0x03u}, - {0x88u, 0x20u}, - {0x8Au, 0x40u}, + {0x81u, 0x33u}, + {0x83u, 0xCCu}, + {0x85u, 0xFFu}, {0x8Bu, 0xFFu}, - {0x8Cu, 0x02u}, - {0x8Fu, 0xFFu}, - {0x91u, 0x0Fu}, - {0x92u, 0x08u}, - {0x93u, 0xF0u}, - {0x94u, 0x01u}, - {0x95u, 0xFFu}, - {0x96u, 0x6Eu}, - {0x98u, 0x64u}, + {0x8Du, 0x0Fu}, + {0x8Fu, 0xF0u}, + {0x91u, 0x55u}, + {0x93u, 0xAAu}, + {0x97u, 0xFFu}, {0x99u, 0xFFu}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x74u}, - {0xA1u, 0x55u}, - {0xA3u, 0xAAu}, - {0xA5u, 0x69u}, - {0xA6u, 0x01u}, - {0xA7u, 0x96u}, - {0xA8u, 0x20u}, - {0xA9u, 0x33u}, - {0xAAu, 0x40u}, - {0xABu, 0xCCu}, - {0xAFu, 0xFFu}, - {0xB1u, 0xFFu}, - {0xB4u, 0x60u}, - {0xB6u, 0x1Fu}, - {0xBAu, 0x20u}, - {0xBBu, 0x02u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x80u}, - {0x01u, 0x20u}, - {0x02u, 0x40u}, - {0x03u, 0x10u}, - {0x04u, 0xA8u}, - {0x06u, 0x80u}, - {0x0Au, 0x09u}, - {0x0Bu, 0x90u}, - {0x0Eu, 0x45u}, - {0x0Fu, 0x10u}, - {0x11u, 0x04u}, - {0x12u, 0x04u}, - {0x16u, 0x02u}, - {0x17u, 0x10u}, - {0x19u, 0xA0u}, - {0x1Au, 0x01u}, - {0x1Eu, 0x06u}, - {0x1Fu, 0x08u}, - {0x22u, 0x02u}, - {0x25u, 0x04u}, - {0x26u, 0x10u}, - {0x27u, 0x14u}, - {0x28u, 0x40u}, - {0x29u, 0x94u}, - {0x2Du, 0x84u}, - {0x2Fu, 0x84u}, - {0x32u, 0x06u}, - {0x33u, 0x10u}, - {0x36u, 0x18u}, - {0x39u, 0x80u}, - {0x3Au, 0x40u}, - {0x3Bu, 0x10u}, - {0x3Cu, 0x80u}, - {0x3Du, 0x08u}, - {0x3Fu, 0x10u}, - {0x41u, 0x40u}, - {0x43u, 0x80u}, - {0x58u, 0x80u}, - {0x5Bu, 0x20u}, - {0x62u, 0x20u}, - {0x63u, 0x02u}, - {0x78u, 0x40u}, - {0x7Bu, 0x01u}, - {0x83u, 0x20u}, - {0x84u, 0x80u}, - {0x8Fu, 0x10u}, - {0x91u, 0x85u}, - {0x92u, 0x88u}, - {0x93u, 0x88u}, - {0x94u, 0x44u}, - {0x95u, 0x08u}, - {0x96u, 0x44u}, - {0x97u, 0x12u}, - {0x98u, 0x18u}, - {0x99u, 0x14u}, - {0x9Au, 0x85u}, - {0x9Cu, 0x40u}, - {0x9Du, 0xA2u}, - {0x9Eu, 0x12u}, - {0x9Fu, 0x54u}, - {0xA0u, 0x41u}, - {0xA1u, 0x01u}, - {0xA2u, 0x08u}, - {0xA4u, 0x08u}, - {0xA6u, 0x24u}, - {0xA7u, 0x20u}, - {0xAAu, 0x01u}, - {0xABu, 0x20u}, - {0xAFu, 0x18u}, - {0xB1u, 0x03u}, - {0xB3u, 0x40u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xFFu}, - {0xC4u, 0xC6u}, - {0xCAu, 0xFFu}, - {0xCCu, 0x67u}, - {0xCEu, 0x7Cu}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x0Cu}, - {0xE2u, 0x01u}, - {0xE6u, 0x06u}, - {0xEAu, 0x2Fu}, - {0xEEu, 0x20u}, - {0x65u, 0x08u}, - {0x66u, 0x08u}, - {0x81u, 0x01u}, - {0x82u, 0x04u}, - {0x89u, 0x40u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x21u}, - {0x91u, 0x60u}, - {0x94u, 0x30u}, - {0x95u, 0x92u}, - {0x98u, 0x0Cu}, - {0x9Au, 0x04u}, - {0x9Bu, 0x42u}, - {0x9Du, 0x48u}, - {0x9Eu, 0x1Au}, - {0xA0u, 0x30u}, - {0xA2u, 0x04u}, - {0xA3u, 0x08u}, - {0xA5u, 0x40u}, - {0xA9u, 0x01u}, - {0xB2u, 0x20u}, - {0xB3u, 0x04u}, - {0xE0u, 0x04u}, - {0xE2u, 0x01u}, - {0xE4u, 0x40u}, - {0xE6u, 0x02u}, - {0xE8u, 0x80u}, - {0xEAu, 0x0Bu}, - {0xEEu, 0xA0u}, - {0x00u, 0xFFu}, - {0x03u, 0x02u}, - {0x04u, 0x03u}, - {0x06u, 0x0Cu}, - {0x07u, 0x04u}, - {0x08u, 0x09u}, - {0x0Au, 0x06u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x04u}, - {0x10u, 0x0Fu}, - {0x12u, 0xF0u}, - {0x16u, 0xFFu}, - {0x18u, 0xFFu}, - {0x20u, 0x05u}, - {0x22u, 0x0Au}, - {0x24u, 0x30u}, - {0x26u, 0xC0u}, - {0x28u, 0x50u}, - {0x2Au, 0xA0u}, - {0x2Cu, 0x90u}, - {0x2Eu, 0x60u}, - {0x2Fu, 0x01u}, - {0x30u, 0xFFu}, - {0x33u, 0x06u}, - {0x35u, 0x01u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x04u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x80u, 0x40u}, - {0x81u, 0x08u}, - {0x82u, 0x20u}, - {0x83u, 0x10u}, - {0x84u, 0x01u}, - {0x86u, 0x02u}, - {0x88u, 0x08u}, - {0x8Au, 0x10u}, - {0x8Bu, 0x10u}, - {0x8Du, 0x01u}, - {0x8Fu, 0x66u}, - {0x91u, 0x04u}, - {0x93u, 0x03u}, - {0x94u, 0x06u}, - {0x97u, 0x20u}, - {0x98u, 0x10u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x18u}, - {0x9Eu, 0x60u}, - {0xA0u, 0x20u}, - {0xA1u, 0xC5u}, - {0xA2u, 0x40u}, - {0xA3u, 0x02u}, - {0xA8u, 0x01u}, - {0xA9u, 0x03u}, - {0xAAu, 0x04u}, - {0xABu, 0xA4u}, - {0xACu, 0x02u}, - {0xAEu, 0x01u}, - {0xB2u, 0x07u}, - {0xB3u, 0xE0u}, - {0xB5u, 0x18u}, - {0xB6u, 0x78u}, - {0xB7u, 0x07u}, - {0xB8u, 0x08u}, + {0xABu, 0xFFu}, + {0xADu, 0x96u}, + {0xAFu, 0x69u}, + {0xB7u, 0xFFu}, {0xBBu, 0x80u}, - {0xBEu, 0x40u}, - {0xBFu, 0x10u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x02u, 0x04u}, - {0x03u, 0x80u}, - {0x04u, 0x20u}, - {0x06u, 0x10u}, - {0x07u, 0x40u}, - {0x0Bu, 0xA8u}, - {0x0Du, 0x70u}, - {0x0Eu, 0x10u}, - {0x0Fu, 0x02u}, - {0x10u, 0x28u}, - {0x11u, 0x41u}, - {0x15u, 0x10u}, - {0x16u, 0x02u}, - {0x17u, 0x02u}, - {0x19u, 0x02u}, - {0x1Eu, 0x10u}, - {0x1Fu, 0x80u}, - {0x23u, 0x14u}, - {0x24u, 0x02u}, - {0x26u, 0x14u}, - {0x27u, 0x01u}, - {0x28u, 0x02u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x02u}, - {0x36u, 0x24u}, - {0x37u, 0x01u}, - {0x38u, 0x08u}, - {0x39u, 0x83u}, - {0x3Bu, 0x80u}, - {0x3Du, 0x80u}, - {0x3Eu, 0x20u}, - {0x3Fu, 0x02u}, - {0x59u, 0x40u}, - {0x60u, 0x02u}, - {0x6Cu, 0x2Cu}, - {0x6Du, 0x40u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x46u}, - {0x74u, 0x10u}, - {0x75u, 0x01u}, - {0x76u, 0x20u}, - {0x77u, 0x02u}, - {0x80u, 0x01u}, - {0x8Bu, 0x10u}, - {0x8Du, 0x20u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x01u}, - {0x93u, 0x20u}, - {0x94u, 0x10u}, - {0x95u, 0x83u}, - {0x96u, 0x40u}, - {0x97u, 0x0Eu}, - {0x98u, 0x0Cu}, - {0x9Au, 0x04u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x0Au}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x04u}, - {0xA2u, 0x20u}, - {0xA3u, 0x08u}, - {0xA4u, 0x28u}, - {0xA6u, 0x10u}, - {0xA7u, 0x82u}, - {0xABu, 0x21u}, - {0xAEu, 0x10u}, - {0xB1u, 0x04u}, - {0xB3u, 0x40u}, - {0xB5u, 0x40u}, - {0xB6u, 0x22u}, - {0xC0u, 0x7Eu}, - {0xC2u, 0xEEu}, - {0xC4u, 0xDFu}, - {0xCAu, 0xA8u}, - {0xCCu, 0xE0u}, - {0xCEu, 0xBBu}, - {0xD6u, 0x08u}, - {0xD8u, 0x08u}, - {0xE0u, 0x40u}, - {0xE2u, 0x20u}, - {0xE4u, 0x40u}, - {0xE6u, 0x10u}, - {0xEAu, 0x10u}, - {0xEEu, 0x91u}, - {0x01u, 0x04u}, - {0x03u, 0x03u}, - {0x07u, 0x38u}, - {0x09u, 0x04u}, - {0x0Bu, 0x02u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x04u}, - {0x10u, 0x02u}, - {0x11u, 0x04u}, - {0x13u, 0x82u}, - {0x15u, 0x20u}, - {0x17u, 0x40u}, - {0x19u, 0x04u}, - {0x1Bu, 0x02u}, - {0x21u, 0x48u}, - {0x23u, 0x10u}, - {0x28u, 0x01u}, - {0x29u, 0x50u}, - {0x2Bu, 0x28u}, - {0x2Fu, 0x40u}, - {0x30u, 0x02u}, - {0x31u, 0x06u}, - {0x33u, 0x80u}, - {0x34u, 0x01u}, - {0x35u, 0x78u}, - {0x37u, 0x01u}, - {0x3Bu, 0x02u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x19u}, - {0x5Fu, 0x01u}, - {0x80u, 0xFFu}, - {0x84u, 0x03u}, - {0x85u, 0x04u}, - {0x86u, 0x0Cu}, - {0x87u, 0x12u}, - {0x88u, 0x50u}, - {0x89u, 0x04u}, - {0x8Au, 0xA0u}, - {0x8Bu, 0x02u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x04u}, - {0x90u, 0x60u}, - {0x92u, 0x90u}, - {0x95u, 0x01u}, - {0x96u, 0xFFu}, - {0x99u, 0x04u}, - {0x9Au, 0xFFu}, - {0x9Bu, 0x0Au}, - {0x9Du, 0x01u}, - {0xA0u, 0x05u}, - {0xA1u, 0x01u}, - {0xA2u, 0x0Au}, - {0xA4u, 0x30u}, - {0xA6u, 0xC0u}, - {0xA8u, 0x06u}, - {0xA9u, 0x01u}, - {0xAAu, 0x09u}, - {0xACu, 0x0Fu}, - {0xADu, 0x04u}, - {0xAEu, 0xF0u}, - {0xAFu, 0x02u}, - {0xB1u, 0x06u}, - {0xB3u, 0x08u}, - {0xB4u, 0xFFu}, - {0xB5u, 0x10u}, - {0xB7u, 0x01u}, - {0xB9u, 0x80u}, - {0xBBu, 0x02u}, - {0xBEu, 0x10u}, - {0xBFu, 0x40u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x10u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x03u, 0x84u}, - {0x0Au, 0x40u}, - {0x0Bu, 0x28u}, - {0x0Fu, 0x40u}, - {0x10u, 0x20u}, - {0x11u, 0x01u}, - {0x12u, 0x06u}, - {0x17u, 0x20u}, - {0x19u, 0x10u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x04u}, - {0x21u, 0xA0u}, - {0x23u, 0x50u}, - {0x24u, 0x44u}, - {0x25u, 0x08u}, - {0x26u, 0x20u}, - {0x27u, 0x11u}, - {0x28u, 0x02u}, - {0x29u, 0x12u}, - {0x2Cu, 0x01u}, - {0x2Eu, 0x21u}, - {0x31u, 0x20u}, - {0x32u, 0x84u}, - {0x36u, 0x08u}, - {0x37u, 0x11u}, - {0x3Bu, 0x54u}, - {0x3Cu, 0x44u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x02u}, - {0x58u, 0x40u}, - {0x5Cu, 0x50u}, - {0x5Du, 0x04u}, - {0x5Fu, 0x01u}, - {0x63u, 0x02u}, - {0x67u, 0x02u}, - {0x80u, 0x08u}, - {0x81u, 0x80u}, - {0x84u, 0x40u}, - {0x86u, 0x08u}, - {0x8Au, 0x05u}, - {0x8Bu, 0x08u}, - {0x8Eu, 0x20u}, - {0x92u, 0x18u}, - {0x93u, 0x20u}, - {0x95u, 0x82u}, - {0x96u, 0x40u}, - {0x98u, 0x05u}, - {0x9Au, 0x04u}, - {0x9Bu, 0x20u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x28u}, - {0x9Fu, 0x0Cu}, - {0xA2u, 0x80u}, - {0xA3u, 0x08u}, - {0xA4u, 0x28u}, - {0xA5u, 0x08u}, - {0xA7u, 0x82u}, - {0xABu, 0x10u}, - {0xACu, 0x4Du}, - {0xAFu, 0x40u}, - {0xB5u, 0x60u}, - {0xB7u, 0x04u}, - {0xC0u, 0x0Eu}, - {0xC2u, 0x1Eu}, - {0xC4u, 0x4Fu}, - {0xCAu, 0xBDu}, - {0xCCu, 0xEEu}, - {0xCEu, 0xFEu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE2u, 0x10u}, - {0xE4u, 0xC0u}, - {0xE6u, 0x38u}, - {0xE8u, 0x50u}, - {0x01u, 0x05u}, - {0x02u, 0xFFu}, - {0x03u, 0x0Au}, - {0x05u, 0x03u}, - {0x07u, 0x0Cu}, - {0x08u, 0x50u}, - {0x0Au, 0xA0u}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0xFFu}, - {0x0Du, 0x0Fu}, - {0x0Fu, 0xF0u}, - {0x10u, 0x60u}, - {0x11u, 0x90u}, - {0x12u, 0x90u}, - {0x13u, 0x60u}, - {0x15u, 0x50u}, - {0x16u, 0xFFu}, - {0x17u, 0xA0u}, - {0x18u, 0x30u}, - {0x19u, 0x30u}, - {0x1Au, 0xC0u}, - {0x1Bu, 0xC0u}, - {0x20u, 0x0Fu}, - {0x22u, 0xF0u}, - {0x23u, 0xFFu}, - {0x24u, 0x03u}, - {0x25u, 0x09u}, - {0x26u, 0x0Cu}, - {0x27u, 0x06u}, - {0x28u, 0x06u}, - {0x2Au, 0x09u}, - {0x2Bu, 0xFFu}, - {0x2Cu, 0x05u}, - {0x2Eu, 0x0Au}, - {0x34u, 0xFFu}, - {0x37u, 0xFFu}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x40u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x81u, 0x02u}, - {0x83u, 0x05u}, - {0x84u, 0x1Au}, - {0x86u, 0x05u}, - {0x89u, 0x02u}, - {0x8Au, 0x08u}, - {0x8Bu, 0x01u}, - {0x8Eu, 0x40u}, - {0x91u, 0x02u}, - {0x93u, 0x01u}, - {0x96u, 0x20u}, - {0x99u, 0x01u}, - {0x9Au, 0x07u}, - {0x9Bu, 0x02u}, - {0x9Eu, 0x10u}, - {0xA1u, 0x02u}, - {0xA3u, 0x09u}, - {0xA4u, 0x19u}, - {0xA6u, 0x02u}, - {0xA8u, 0x14u}, - {0xAAu, 0x08u}, - {0xB0u, 0x10u}, - {0xB2u, 0x20u}, - {0xB3u, 0x03u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0x08u}, - {0xB6u, 0x40u}, - {0xB7u, 0x04u}, - {0xBBu, 0x08u}, - {0xBEu, 0x01u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDFu, 0x01u}, - {0x01u, 0x40u}, - {0x03u, 0x84u}, - {0x05u, 0x10u}, - {0x06u, 0x20u}, - {0x07u, 0x01u}, - {0x08u, 0x10u}, - {0x0Au, 0x40u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x40u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x08u}, - {0x12u, 0x45u}, - {0x13u, 0x04u}, - {0x17u, 0x18u}, - {0x1Au, 0x08u}, - {0x1Eu, 0x18u}, - {0x1Fu, 0x61u}, - {0x22u, 0x80u}, - {0x25u, 0x10u}, - {0x27u, 0x21u}, - {0x2Au, 0x04u}, - {0x2Bu, 0xA4u}, - {0x2Fu, 0x40u}, - {0x30u, 0x38u}, - {0x33u, 0x02u}, - {0x37u, 0x21u}, - {0x39u, 0x82u}, - {0x3Au, 0x49u}, - {0x3Bu, 0x24u}, - {0x3Du, 0x20u}, - {0x3Fu, 0x01u}, - {0x44u, 0x02u}, - {0x45u, 0x40u}, - {0x5Au, 0x80u}, - {0x5Cu, 0x0Au}, - {0x5Du, 0x20u}, - {0x5Fu, 0x40u}, - {0x63u, 0x01u}, - {0x67u, 0x02u}, - {0x82u, 0x40u}, - {0x87u, 0x10u}, - {0x89u, 0x40u}, - {0x8Bu, 0x08u}, - {0x8Du, 0x11u}, - {0xC0u, 0xEBu}, - {0xC2u, 0xEEu}, - {0xC4u, 0x6Fu}, - {0xCAu, 0x87u}, - {0xCCu, 0xA7u}, - {0xCEu, 0xAFu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE0u, 0x60u}, - {0xE2u, 0x01u}, - {0xE4u, 0x20u}, - {0xE6u, 0x41u}, - {0x00u, 0x03u}, - {0x02u, 0x0Cu}, - {0x04u, 0x20u}, - {0x06u, 0x4Fu}, - {0x0Cu, 0x40u}, - {0x0Eu, 0x1Fu}, - {0x10u, 0x06u}, - {0x12u, 0x09u}, - {0x16u, 0x70u}, - {0x1Eu, 0x80u}, - {0x24u, 0x0Fu}, - {0x28u, 0x10u}, - {0x2Au, 0x2Fu}, - {0x2Cu, 0x05u}, - {0x2Eu, 0x0Au}, - {0x30u, 0x80u}, - {0x32u, 0x7Fu}, - {0x40u, 0x26u}, - {0x41u, 0x04u}, - {0x42u, 0x30u}, - {0x44u, 0x05u}, - {0x45u, 0xCEu}, - {0x46u, 0xF0u}, - {0x47u, 0xDBu}, - {0x48u, 0x3Bu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x22u}, - {0x4Eu, 0xF0u}, - {0x4Fu, 0x08u}, - {0x50u, 0x04u}, - {0x58u, 0x04u}, - {0x5Au, 0x04u}, - {0x5Cu, 0x01u}, - {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x64u, 0x40u}, - {0x65u, 0x01u}, - {0x66u, 0x10u}, - {0x67u, 0x11u}, - {0x68u, 0xC0u}, - {0x69u, 0x01u}, - {0x6Bu, 0x11u}, - {0x6Cu, 0x40u}, - {0x6Du, 0x01u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x80u, 0x40u}, - {0x84u, 0x88u}, - {0x86u, 0x21u}, - {0x87u, 0xFFu}, - {0x88u, 0x01u}, - {0x89u, 0x80u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x1Fu}, - {0x8Fu, 0x20u}, - {0x90u, 0x87u}, - {0x91u, 0xC0u}, - {0x92u, 0x18u}, - {0x93u, 0x01u}, - {0x94u, 0x01u}, - {0x97u, 0x9Fu}, - {0x98u, 0xA2u}, - {0x99u, 0x7Fu}, - {0x9Au, 0x08u}, - {0x9Bu, 0x80u}, - {0x9Cu, 0x04u}, - {0x9Du, 0xC0u}, - {0x9Fu, 0x02u}, - {0xA0u, 0x01u}, - {0xA3u, 0x60u}, - {0xA4u, 0x10u}, - {0xA5u, 0xC0u}, - {0xA7u, 0x04u}, - {0xA8u, 0x40u}, - {0xA9u, 0xC0u}, - {0xABu, 0x08u}, - {0xACu, 0x01u}, - {0xADu, 0x90u}, - {0xAFu, 0x40u}, - {0xB0u, 0x3Fu}, - {0xB2u, 0x80u}, - {0xB3u, 0xFFu}, - {0xB6u, 0x40u}, - {0xB8u, 0x82u}, - {0xBEu, 0x05u}, - {0xBFu, 0x04u}, - {0xD4u, 0x09u}, - {0xD6u, 0x04u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x01u, 0x80u}, - {0x03u, 0x10u}, - {0x04u, 0x24u}, - {0x05u, 0x01u}, - {0x07u, 0x01u}, - {0x08u, 0x80u}, - {0x0Au, 0xA0u}, - {0x0Du, 0x0Au}, - {0x0Eu, 0x09u}, - {0x11u, 0x04u}, - {0x12u, 0x02u}, - {0x13u, 0x10u}, - {0x15u, 0x08u}, - {0x17u, 0x62u}, - {0x18u, 0x80u}, - {0x19u, 0x08u}, - {0x1Au, 0x20u}, - {0x1Du, 0x05u}, - {0x1Eu, 0x01u}, - {0x27u, 0x20u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x41u}, - {0x2Fu, 0x20u}, - {0x35u, 0x10u}, - {0x36u, 0x08u}, - {0x37u, 0x42u}, - {0x3Cu, 0xA4u}, - {0x40u, 0x04u}, - {0x41u, 0x02u}, - {0x43u, 0x08u}, - {0x48u, 0x82u}, - {0x49u, 0x12u}, - {0x4Bu, 0x04u}, - {0x51u, 0x04u}, - {0x52u, 0x18u}, - {0x53u, 0x01u}, - {0x5Du, 0x10u}, - {0x5Eu, 0x82u}, - {0x5Fu, 0x04u}, - {0x64u, 0x02u}, - {0x67u, 0x40u}, - {0x80u, 0x40u}, - {0x84u, 0x02u}, - {0x85u, 0x48u}, - {0x89u, 0x12u}, - {0x8Bu, 0x40u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x04u}, - {0x90u, 0x24u}, - {0x91u, 0x04u}, - {0x92u, 0xC0u}, - {0x93u, 0x10u}, - {0x95u, 0x08u}, - {0x97u, 0x02u}, - {0x98u, 0x80u}, - {0x99u, 0x90u}, - {0x9Bu, 0x53u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x10u}, - {0xA0u, 0x59u}, - {0xA1u, 0x0Au}, - {0xA2u, 0x47u}, - {0xA3u, 0x28u}, - {0xA4u, 0x80u}, - {0xA8u, 0x80u}, - {0xABu, 0x01u}, - {0xAEu, 0x10u}, - {0xB3u, 0x10u}, - {0xB5u, 0x10u}, - {0xC0u, 0xFDu}, - {0xC2u, 0xFDu}, - {0xC4u, 0xF7u}, - {0xCAu, 0xF0u}, - {0xCCu, 0xF0u}, - {0xCEu, 0x70u}, - {0xD0u, 0x07u}, - {0xD2u, 0x0Cu}, - {0xD6u, 0xF0u}, - {0xD8u, 0x90u}, - {0xE0u, 0x01u}, - {0xE2u, 0x20u}, - {0xEAu, 0x01u}, - {0xECu, 0x08u}, - {0xEEu, 0x01u}, - {0x00u, 0x6Cu}, - {0x01u, 0xD6u}, - {0x04u, 0x40u}, - {0x05u, 0x29u}, - {0x06u, 0x2Cu}, - {0x07u, 0x46u}, - {0x08u, 0x64u}, - {0x09u, 0x02u}, - {0x0Au, 0x08u}, - {0x0Cu, 0x2Cu}, - {0x0Du, 0xD6u}, - {0x0Eu, 0x40u}, - {0x10u, 0x71u}, - {0x12u, 0x82u}, - {0x14u, 0xA4u}, - {0x15u, 0x21u}, - {0x16u, 0x40u}, - {0x17u, 0x8Eu}, - {0x18u, 0xC0u}, - {0x19u, 0x20u}, - {0x1Au, 0x2Fu}, - {0x1Bu, 0xD0u}, - {0x1Cu, 0x08u}, - {0x1Du, 0xD6u}, - {0x1Eu, 0x10u}, - {0x20u, 0x6Cu}, - {0x21u, 0x04u}, - {0x24u, 0x91u}, - {0x25u, 0xD2u}, - {0x26u, 0x4Eu}, - {0x27u, 0x04u}, - {0x29u, 0xD0u}, - {0x2Bu, 0x06u}, - {0x2Du, 0x17u}, - {0x2Fu, 0x28u}, - {0x30u, 0x0Fu}, - {0x32u, 0xC0u}, - {0x33u, 0xF0u}, - {0x34u, 0x31u}, - {0x35u, 0x0Fu}, - {0x37u, 0x08u}, - {0x39u, 0x20u}, - {0x3Au, 0x38u}, - {0x3Bu, 0x08u}, - {0x3Fu, 0x40u}, - {0x56u, 0x02u}, - {0x57u, 0x24u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Fu, 0x01u}, - {0x80u, 0x06u}, - {0x82u, 0x09u}, - {0x87u, 0x01u}, - {0x88u, 0x60u}, - {0x89u, 0x95u}, - {0x8Au, 0x90u}, - {0x8Bu, 0x28u}, - {0x8Cu, 0x30u}, - {0x8Du, 0x02u}, - {0x8Eu, 0xC0u}, - {0x90u, 0x05u}, - {0x92u, 0x0Au}, - {0x97u, 0x08u}, - {0x98u, 0x03u}, - {0x99u, 0xA4u}, - {0x9Au, 0x0Cu}, - {0x9Bu, 0x58u}, - {0x9Cu, 0x0Fu}, - {0x9Eu, 0xF0u}, - {0x9Fu, 0x70u}, - {0xA0u, 0x50u}, - {0xA2u, 0xA0u}, - {0xA7u, 0x80u}, - {0xADu, 0x41u}, - {0xAFu, 0x88u}, - {0xB0u, 0xFFu}, - {0xB3u, 0x0Fu}, - {0xB7u, 0xF0u}, - {0xB9u, 0x08u}, - {0xBEu, 0x01u}, {0xD4u, 0x01u}, - {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x10u}, {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x02u, 0x89u}, - {0x04u, 0x28u}, - {0x07u, 0x41u}, - {0x09u, 0x01u}, - {0x0Au, 0x04u}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x80u}, - {0x0Du, 0x0Au}, - {0x0Eu, 0x08u}, - {0x11u, 0x01u}, - {0x17u, 0x0Au}, + {0x00u, 0x04u}, + {0x01u, 0x02u}, + {0x03u, 0x04u}, + {0x09u, 0x22u}, + {0x10u, 0x80u}, + {0x13u, 0x08u}, + {0x18u, 0x04u}, {0x19u, 0x02u}, - {0x1Cu, 0xE0u}, - {0x1Du, 0x1Au}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x02u}, - {0x22u, 0x80u}, - {0x23u, 0x10u}, - {0x24u, 0x04u}, - {0x26u, 0x50u}, - {0x27u, 0x28u}, - {0x28u, 0x10u}, - {0x29u, 0x80u}, - {0x2Cu, 0x88u}, - {0x2Fu, 0x22u}, - {0x32u, 0x84u}, - {0x33u, 0x10u}, - {0x36u, 0x04u}, - {0x37u, 0x60u}, - {0x39u, 0x84u}, - {0x3Bu, 0x10u}, - {0x3Cu, 0x24u}, - {0x3Eu, 0x42u}, - {0x59u, 0x40u}, - {0x64u, 0x08u}, - {0x6Cu, 0x5Cu}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x61u}, - {0x76u, 0x02u}, - {0x77u, 0x02u}, - {0x86u, 0x88u}, - {0x88u, 0x40u}, - {0x91u, 0x85u}, - {0x92u, 0x8Cu}, - {0x94u, 0xECu}, - {0x95u, 0x08u}, - {0x96u, 0x40u}, - {0x97u, 0x12u}, - {0x98u, 0x18u}, - {0x99u, 0x80u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x10u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x12u}, - {0x9Fu, 0x40u}, - {0xA0u, 0x01u}, - {0xA1u, 0x01u}, - {0xA2u, 0x03u}, - {0xA3u, 0x08u}, - {0xA4u, 0x08u}, - {0xA6u, 0x04u}, - {0xA7u, 0x20u}, - {0xB1u, 0x80u}, - {0xC0u, 0xFBu}, - {0xC2u, 0xFBu}, - {0xC4u, 0x38u}, - {0xCAu, 0xFAu}, - {0xCCu, 0x7Eu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x08u}, - {0xD8u, 0x20u}, - {0xE2u, 0x8Au}, - {0xE4u, 0x08u}, - {0xEAu, 0x02u}, - {0xEEu, 0x08u}, - {0x02u, 0x08u}, - {0x03u, 0x02u}, - {0x06u, 0x10u}, - {0x08u, 0x01u}, - {0x09u, 0x28u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x14u}, - {0x0Du, 0x01u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x02u}, - {0x10u, 0x14u}, - {0x12u, 0x28u}, - {0x14u, 0x02u}, - {0x16u, 0x01u}, - {0x17u, 0x20u}, - {0x1Bu, 0x1Cu}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x01u}, - {0x1Fu, 0x01u}, - {0x20u, 0x02u}, - {0x21u, 0x10u}, - {0x22u, 0x41u}, - {0x23u, 0x20u}, - {0x24u, 0x02u}, - {0x26u, 0x01u}, + {0x23u, 0x22u}, + {0x25u, 0x40u}, + {0x29u, 0x20u}, {0x2Au, 0x04u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x24u}, - {0x2Fu, 0x08u}, - {0x30u, 0x0Cu}, - {0x32u, 0x03u}, - {0x33u, 0x3Cu}, - {0x34u, 0x30u}, - {0x35u, 0x40u}, - {0x36u, 0x40u}, - {0x37u, 0x03u}, - {0x3Au, 0x08u}, - {0x3Eu, 0x11u}, - {0x3Fu, 0x40u}, + {0x2Du, 0x60u}, + {0x31u, 0x10u}, + {0x33u, 0x05u}, + {0x34u, 0x02u}, + {0x35u, 0x10u}, + {0x37u, 0x04u}, + {0x3Au, 0x99u}, + {0x3Bu, 0x80u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x02u}, + {0x41u, 0x20u}, + {0x42u, 0x08u}, + {0x43u, 0x84u}, + {0x49u, 0x20u}, + {0x4Au, 0x04u}, + {0x4Bu, 0x08u}, + {0x51u, 0x44u}, + {0x52u, 0x02u}, + {0x53u, 0x10u}, + {0x5Au, 0xAAu}, + {0x5Eu, 0x80u}, + {0x61u, 0x08u}, + {0x62u, 0x40u}, + {0x63u, 0x44u}, + {0x69u, 0x24u}, + {0x6Au, 0x40u}, + {0x6Bu, 0x40u}, + {0x70u, 0x8Au}, + {0x73u, 0x08u}, + {0x80u, 0x04u}, + {0x81u, 0x40u}, + {0x83u, 0x40u}, + {0x86u, 0x40u}, + {0x87u, 0x10u}, + {0x88u, 0x10u}, + {0x89u, 0x10u}, + {0x8Bu, 0x40u}, + {0x8Fu, 0x40u}, + {0xC0u, 0x0Eu}, + {0xC2u, 0x0Au}, + {0xC4u, 0x0Cu}, + {0xCAu, 0x36u}, + {0xCCu, 0xE7u}, + {0xCEu, 0xFFu}, + {0xD0u, 0x0Eu}, + {0xD2u, 0x04u}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x04u}, + {0xE2u, 0x10u}, + {0xE4u, 0x01u}, + {0xE6u, 0x44u}, + {0x01u, 0x40u}, + {0x03u, 0x80u}, + {0x05u, 0x01u}, + {0x0Du, 0x0Bu}, + {0x0Fu, 0xF4u}, + {0x11u, 0x06u}, + {0x15u, 0x11u}, + {0x17u, 0xECu}, + {0x19u, 0xE0u}, + {0x21u, 0xCAu}, + {0x22u, 0x01u}, + {0x23u, 0x15u}, + {0x25u, 0x40u}, + {0x27u, 0x80u}, + {0x2Bu, 0x10u}, + {0x2Fu, 0xFFu}, + {0x32u, 0x01u}, + {0x33u, 0xC0u}, + {0x35u, 0x3Fu}, + {0x3Bu, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x81u, 0x0Au}, - {0x83u, 0x05u}, - {0x86u, 0x07u}, - {0x8Cu, 0x09u}, - {0x8Eu, 0x02u}, - {0x8Fu, 0x07u}, - {0x90u, 0x10u}, - {0x92u, 0x20u}, - {0x95u, 0x10u}, - {0x96u, 0x08u}, - {0x97u, 0x20u}, - {0x9Bu, 0x20u}, - {0x9Du, 0x04u}, - {0x9Fu, 0x08u}, - {0xA0u, 0x04u}, - {0xA2u, 0x08u}, - {0xA4u, 0x0Au}, - {0xA6u, 0x05u}, - {0xA7u, 0x10u}, - {0xAAu, 0x10u}, - {0xABu, 0x08u}, - {0xADu, 0x09u}, - {0xAEu, 0x20u}, - {0xAFu, 0x02u}, - {0xB0u, 0x30u}, - {0xB1u, 0x0Fu}, - {0xB2u, 0x0Fu}, - {0xB5u, 0x30u}, - {0xBEu, 0x01u}, - {0xBFu, 0x10u}, + {0x81u, 0x03u}, + {0x82u, 0x02u}, + {0x83u, 0x0Cu}, + {0x85u, 0x02u}, + {0x86u, 0x0Du}, + {0x8Au, 0x90u}, + {0x8Bu, 0x01u}, + {0x8Du, 0xF4u}, + {0x8Eu, 0x60u}, + {0x90u, 0x01u}, + {0x91u, 0x08u}, + {0x92u, 0x02u}, + {0x93u, 0xF7u}, + {0x95u, 0x0Bu}, + {0x97u, 0xF4u}, + {0x98u, 0x90u}, + {0x99u, 0x40u}, + {0x9Au, 0x48u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x90u}, + {0x9Du, 0xFDu}, + {0x9Eu, 0x24u}, + {0x9Fu, 0x02u}, + {0xA1u, 0x10u}, + {0xA3u, 0x20u}, + {0xA5u, 0x10u}, + {0xA7u, 0x20u}, + {0xA9u, 0x40u}, + {0xAAu, 0x80u}, + {0xABu, 0x80u}, + {0xAEu, 0x10u}, + {0xAFu, 0xF7u}, + {0xB0u, 0xE0u}, + {0xB3u, 0x30u}, + {0xB4u, 0x1Cu}, + {0xB5u, 0xC0u}, + {0xB6u, 0x03u}, + {0xB7u, 0x0Fu}, + {0xBBu, 0xA8u}, + {0xBEu, 0x40u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -1940,107 +668,1242 @@ void cyfitter_cfg(void) {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x88u}, - {0x04u, 0x10u}, - {0x07u, 0x62u}, - {0x08u, 0x04u}, - {0x0Au, 0x40u}, - {0x0Eu, 0x52u}, - {0x10u, 0x80u}, - {0x11u, 0x48u}, - {0x12u, 0x04u}, - {0x15u, 0x20u}, + {0x00u, 0x02u}, + {0x03u, 0x26u}, + {0x05u, 0x02u}, + {0x06u, 0x80u}, + {0x08u, 0x81u}, + {0x09u, 0x10u}, + {0x10u, 0x0Au}, {0x16u, 0x40u}, - {0x17u, 0x08u}, - {0x19u, 0x09u}, - {0x1Cu, 0x10u}, - {0x1Eu, 0x06u}, - {0x1Fu, 0x02u}, - {0x20u, 0x40u}, - {0x21u, 0x01u}, - {0x22u, 0x10u}, - {0x24u, 0x20u}, - {0x26u, 0x80u}, - {0x27u, 0x28u}, - {0x29u, 0x88u}, - {0x2Bu, 0x08u}, - {0x2Cu, 0x80u}, - {0x2Du, 0x80u}, - {0x2Eu, 0x10u}, - {0x30u, 0xA0u}, + {0x1Bu, 0x62u}, + {0x1Eu, 0x20u}, + {0x22u, 0x14u}, + {0x23u, 0x01u}, + {0x25u, 0x38u}, + {0x2Au, 0x91u}, + {0x2Bu, 0x10u}, + {0x2Cu, 0x90u}, + {0x2Eu, 0x80u}, + {0x2Fu, 0x04u}, + {0x30u, 0x80u}, + {0x31u, 0x02u}, + {0x32u, 0x10u}, {0x33u, 0x04u}, - {0x34u, 0x08u}, - {0x35u, 0x40u}, - {0x37u, 0x20u}, - {0x38u, 0x40u}, - {0x3Au, 0x01u}, - {0x3Eu, 0x61u}, - {0x5Au, 0x80u}, - {0x62u, 0x40u}, - {0x69u, 0x80u}, - {0x6Au, 0x40u}, - {0x82u, 0x10u}, - {0x84u, 0x10u}, - {0x85u, 0x40u}, - {0x86u, 0x05u}, - {0x89u, 0x40u}, - {0x8Au, 0x90u}, - {0x8Fu, 0x02u}, - {0x91u, 0x60u}, - {0x94u, 0x30u}, - {0x95u, 0x92u}, - {0x98u, 0x0Cu}, - {0x9Au, 0x25u}, - {0x9Bu, 0x42u}, - {0x9Du, 0x09u}, - {0x9Eu, 0x12u}, - {0xA0u, 0xB0u}, - {0xA1u, 0x04u}, - {0xA3u, 0x08u}, - {0xA5u, 0x40u}, - {0xB0u, 0x80u}, - {0xC0u, 0xF5u}, - {0xC2u, 0xBCu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0xBEu}, - {0xCCu, 0x7Eu}, - {0xCEu, 0xB9u}, + {0x35u, 0x10u}, + {0x36u, 0x02u}, + {0x37u, 0x04u}, + {0x38u, 0x80u}, + {0x3Bu, 0x29u}, + {0x3Du, 0x08u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x02u}, + {0x40u, 0x80u}, + {0x41u, 0x02u}, + {0x42u, 0x40u}, + {0x44u, 0x10u}, + {0x45u, 0x08u}, + {0x4Eu, 0x04u}, + {0x4Fu, 0x20u}, + {0x58u, 0x44u}, + {0x5Au, 0x11u}, + {0x5Du, 0x9Au}, + {0x60u, 0x02u}, + {0x61u, 0x80u}, + {0x62u, 0x15u}, + {0x67u, 0x02u}, + {0x81u, 0x08u}, + {0x83u, 0x01u}, + {0x84u, 0x01u}, + {0x85u, 0x80u}, + {0x88u, 0x80u}, + {0x89u, 0x20u}, + {0x8Fu, 0x20u}, + {0x91u, 0x8Cu}, + {0x93u, 0x28u}, + {0x95u, 0x40u}, + {0x96u, 0xAAu}, + {0x97u, 0x54u}, + {0x98u, 0x04u}, + {0x9Au, 0x80u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x15u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x0Au}, + {0xA1u, 0x40u}, + {0xA2u, 0x02u}, + {0xA4u, 0x10u}, + {0xA5u, 0x2Au}, + {0xA6u, 0x44u}, + {0xA7u, 0xC1u}, + {0xADu, 0x04u}, + {0xAFu, 0x23u}, + {0xB0u, 0x04u}, + {0xB5u, 0x02u}, + {0xB6u, 0x40u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x0Bu}, + {0xC4u, 0x13u}, + {0xCAu, 0xFFu}, + {0xCCu, 0xEFu}, + {0xCEu, 0xDFu}, + {0xD6u, 0xFFu}, + {0xD8u, 0x1Fu}, + {0xE2u, 0x08u}, + {0xE6u, 0x0Du}, + {0x00u, 0x04u}, + {0x01u, 0x04u}, + {0x02u, 0x08u}, + {0x03u, 0x08u}, + {0x04u, 0x08u}, + {0x05u, 0x10u}, + {0x06u, 0x37u}, + {0x07u, 0x20u}, + {0x09u, 0x01u}, + {0x0Au, 0x40u}, + {0x0Bu, 0x02u}, + {0x0Du, 0x40u}, + {0x0Fu, 0x3Fu}, + {0x10u, 0x10u}, + {0x12u, 0x20u}, + {0x13u, 0x40u}, + {0x14u, 0x01u}, + {0x15u, 0x40u}, + {0x16u, 0x02u}, + {0x17u, 0x3Fu}, + {0x18u, 0x33u}, + {0x19u, 0x7Fu}, + {0x1Au, 0x04u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x02u}, + {0x20u, 0x33u}, + {0x21u, 0x10u}, + {0x22u, 0x04u}, + {0x23u, 0x20u}, + {0x25u, 0x04u}, + {0x26u, 0x37u}, + {0x27u, 0x08u}, + {0x28u, 0x10u}, + {0x29u, 0x3Fu}, + {0x2Au, 0x20u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x37u}, + {0x2Fu, 0x3Fu}, + {0x30u, 0x30u}, + {0x31u, 0x0Cu}, + {0x32u, 0x03u}, + {0x33u, 0x03u}, + {0x34u, 0x40u}, + {0x35u, 0x30u}, + {0x36u, 0x0Cu}, + {0x37u, 0x40u}, + {0x3Au, 0x8Au}, + {0x3Bu, 0x2Au}, + {0x3Fu, 0x40u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x01u}, + {0x81u, 0x81u}, + {0x82u, 0x02u}, + {0x83u, 0x2Eu}, + {0x87u, 0x80u}, + {0x8Bu, 0x1Fu}, + {0x93u, 0x60u}, + {0x94u, 0x02u}, + {0x95u, 0x03u}, + {0x96u, 0x01u}, + {0x97u, 0x94u}, + {0x98u, 0x02u}, + {0x9Au, 0x11u}, + {0x9Bu, 0x01u}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x09u}, + {0xA0u, 0x02u}, + {0xA1u, 0x98u}, + {0xA2u, 0x05u}, + {0xA3u, 0x43u}, + {0xA7u, 0x08u}, + {0xA9u, 0x02u}, + {0xADu, 0x04u}, + {0xB0u, 0x03u}, + {0xB2u, 0x10u}, + {0xB4u, 0x08u}, + {0xB5u, 0x1Fu}, + {0xB6u, 0x04u}, + {0xB7u, 0xE0u}, + {0xBAu, 0x02u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x02u, 0x28u}, + {0x03u, 0x80u}, + {0x05u, 0x01u}, + {0x09u, 0x80u}, + {0x0Au, 0xA8u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x0Au}, + {0x0Eu, 0x06u}, + {0x10u, 0x82u}, + {0x12u, 0x04u}, + {0x13u, 0x08u}, + {0x14u, 0x20u}, + {0x15u, 0x08u}, + {0x17u, 0x02u}, + {0x1Au, 0xA0u}, + {0x1Bu, 0xA8u}, + {0x1Cu, 0x80u}, + {0x1Du, 0x09u}, + {0x1Eu, 0x06u}, + {0x1Fu, 0x01u}, + {0x21u, 0x01u}, + {0x22u, 0x81u}, + {0x23u, 0x14u}, + {0x26u, 0x20u}, + {0x27u, 0x05u}, + {0x28u, 0x10u}, + {0x29u, 0x92u}, + {0x2Cu, 0x80u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x14u}, + {0x30u, 0x40u}, + {0x31u, 0x20u}, + {0x32u, 0x02u}, + {0x33u, 0x06u}, + {0x37u, 0x15u}, + {0x39u, 0x02u}, + {0x3Au, 0x80u}, + {0x3Bu, 0x14u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x06u}, + {0x45u, 0x01u}, + {0x46u, 0x80u}, + {0x5Bu, 0x40u}, + {0x63u, 0x02u}, + {0x6Cu, 0x09u}, + {0x6Du, 0x08u}, + {0x6Fu, 0x10u}, + {0x81u, 0x02u}, + {0x83u, 0x04u}, + {0x84u, 0x50u}, + {0x88u, 0x08u}, + {0x8Du, 0x40u}, + {0x8Eu, 0x01u}, + {0x91u, 0x8Cu}, + {0x93u, 0x28u}, + {0x94u, 0x80u}, + {0x95u, 0x50u}, + {0x96u, 0x82u}, + {0x97u, 0x16u}, + {0x9Au, 0x04u}, + {0x9Bu, 0x60u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x80u}, + {0xA1u, 0xF0u}, + {0xA2u, 0x12u}, + {0xA4u, 0x10u}, + {0xA5u, 0x06u}, + {0xA6u, 0x44u}, + {0xA7u, 0x89u}, + {0xAAu, 0x10u}, + {0xABu, 0x40u}, + {0xACu, 0x41u}, + {0xAFu, 0x4Au}, + {0xB2u, 0x01u}, + {0xB5u, 0x04u}, + {0xC0u, 0x1Eu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x1Fu}, + {0xCAu, 0xFFu}, + {0xCCu, 0xEFu}, + {0xCEu, 0xEFu}, {0xD6u, 0x08u}, {0xD8u, 0x08u}, - {0xE2u, 0x80u}, - {0xE4u, 0x24u}, - {0xEAu, 0x02u}, - {0xECu, 0x80u}, - {0xEEu, 0x08u}, - {0x82u, 0x10u}, - {0x96u, 0x10u}, - {0xA9u, 0x40u}, - {0xAAu, 0x01u}, - {0xABu, 0x04u}, - {0xADu, 0x10u}, - {0xB1u, 0x80u}, - {0xB6u, 0x42u}, + {0xE0u, 0x01u}, + {0xE6u, 0x6Eu}, + {0xE8u, 0x08u}, + {0xEAu, 0x03u}, + {0xEEu, 0x4Du}, + {0x01u, 0x80u}, + {0x05u, 0x0Fu}, + {0x06u, 0xFFu}, + {0x08u, 0x60u}, + {0x09u, 0x20u}, + {0x0Au, 0x90u}, + {0x0Bu, 0x4Fu}, + {0x0Cu, 0x05u}, + {0x0Du, 0x06u}, + {0x0Eu, 0x0Au}, + {0x0Fu, 0x09u}, + {0x10u, 0x50u}, + {0x11u, 0x80u}, + {0x12u, 0xA0u}, + {0x14u, 0x30u}, + {0x15u, 0x40u}, + {0x16u, 0xC0u}, + {0x17u, 0x1Fu}, + {0x19u, 0x03u}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x0Cu}, + {0x1Cu, 0xFFu}, + {0x1Fu, 0x70u}, + {0x20u, 0x06u}, + {0x21u, 0x80u}, + {0x22u, 0x09u}, + {0x24u, 0x0Fu}, + {0x25u, 0x80u}, + {0x26u, 0xF0u}, + {0x28u, 0x03u}, + {0x29u, 0x05u}, + {0x2Au, 0x0Cu}, + {0x2Bu, 0x0Au}, + {0x2Du, 0x10u}, + {0x2Fu, 0x2Fu}, + {0x33u, 0x80u}, + {0x36u, 0xFFu}, + {0x37u, 0x7Fu}, + {0x39u, 0x08u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x81u, 0xD6u}, + {0x84u, 0x01u}, + {0x85u, 0x17u}, + {0x86u, 0x06u}, + {0x87u, 0x28u}, + {0x89u, 0xD0u}, + {0x8Bu, 0x06u}, + {0x8Eu, 0x08u}, + {0x90u, 0x05u}, + {0x91u, 0xD6u}, + {0x92u, 0x02u}, + {0x95u, 0x20u}, + {0x97u, 0xD0u}, + {0x99u, 0x29u}, + {0x9Bu, 0x46u}, + {0x9Cu, 0x04u}, + {0x9Du, 0xD6u}, + {0x9Eu, 0x03u}, + {0xA1u, 0x21u}, + {0xA2u, 0x10u}, + {0xA3u, 0x8Eu}, + {0xA4u, 0x03u}, + {0xA5u, 0xD2u}, + {0xA6u, 0x04u}, + {0xA7u, 0x04u}, + {0xA9u, 0x02u}, + {0xACu, 0x08u}, + {0xADu, 0x04u}, + {0xAEu, 0x10u}, + {0xB0u, 0x18u}, + {0xB3u, 0xF0u}, + {0xB4u, 0x18u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x07u}, + {0xB9u, 0x20u}, + {0xBAu, 0x80u}, + {0xBBu, 0x08u}, + {0xBEu, 0x11u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x84u}, + {0x05u, 0x40u}, + {0x06u, 0x04u}, + {0x07u, 0x10u}, + {0x0Au, 0x82u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x22u}, + {0x11u, 0x40u}, + {0x12u, 0x20u}, + {0x13u, 0x03u}, + {0x14u, 0x80u}, + {0x15u, 0x20u}, + {0x16u, 0x10u}, + {0x18u, 0x80u}, + {0x19u, 0x10u}, + {0x1Au, 0x4Au}, + {0x1Bu, 0x40u}, + {0x1Fu, 0x40u}, + {0x21u, 0x08u}, + {0x22u, 0x20u}, + {0x24u, 0x10u}, + {0x26u, 0x40u}, + {0x29u, 0x01u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x06u}, + {0x2Cu, 0x20u}, + {0x2Eu, 0xA0u}, + {0x2Fu, 0x40u}, + {0x31u, 0x88u}, + {0x32u, 0x20u}, + {0x33u, 0x01u}, + {0x35u, 0x02u}, + {0x36u, 0x40u}, + {0x37u, 0x24u}, + {0x38u, 0x04u}, + {0x39u, 0x11u}, + {0x3Du, 0xA8u}, + {0x3Eu, 0x05u}, + {0x41u, 0x40u}, + {0x43u, 0x40u}, + {0x58u, 0x26u}, + {0x5Bu, 0x40u}, + {0x62u, 0x80u}, + {0x69u, 0x40u}, + {0x7Fu, 0x0Cu}, + {0x82u, 0x04u}, + {0x83u, 0x10u}, + {0x84u, 0x80u}, + {0x88u, 0x40u}, + {0x8Au, 0x10u}, + {0x8Bu, 0x01u}, + {0x8Cu, 0x10u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x10u}, + {0x91u, 0xA0u}, + {0x93u, 0x08u}, + {0x94u, 0x80u}, + {0x96u, 0x48u}, + {0x98u, 0x24u}, + {0x9Bu, 0x24u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x41u}, + {0x9Fu, 0x0Au}, + {0xA0u, 0xC0u}, + {0xA1u, 0x54u}, + {0xA2u, 0x90u}, + {0xA3u, 0x20u}, + {0xA4u, 0x10u}, + {0xA5u, 0x03u}, + {0xA6u, 0x4Cu}, + {0xA8u, 0x01u}, + {0xADu, 0x90u}, + {0xAFu, 0x09u}, + {0xB0u, 0x04u}, + {0xB1u, 0x10u}, + {0xB3u, 0x02u}, + {0xC0u, 0xE5u}, + {0xC2u, 0xF9u}, + {0xC4u, 0x7Du}, + {0xCAu, 0xFFu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xF7u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, + {0xE2u, 0x11u}, + {0xE6u, 0x03u}, + {0xE8u, 0x02u}, + {0xEAu, 0x20u}, + {0xEEu, 0x01u}, + {0x01u, 0x08u}, + {0x03u, 0x05u}, + {0x04u, 0x55u}, + {0x05u, 0x40u}, + {0x06u, 0xAAu}, + {0x07u, 0x10u}, + {0x0Au, 0xFFu}, + {0x0Bu, 0x30u}, + {0x0Cu, 0xFFu}, + {0x0Fu, 0x40u}, + {0x10u, 0x0Fu}, + {0x11u, 0x08u}, + {0x12u, 0xF0u}, + {0x13u, 0x06u}, + {0x15u, 0x04u}, + {0x16u, 0xFFu}, + {0x17u, 0x08u}, + {0x19u, 0x08u}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x04u}, + {0x1Cu, 0x69u}, + {0x1Eu, 0x96u}, + {0x21u, 0x40u}, + {0x23u, 0x20u}, + {0x24u, 0xFFu}, + {0x25u, 0x08u}, + {0x27u, 0x04u}, + {0x28u, 0x33u}, + {0x2Au, 0xCCu}, + {0x2Bu, 0x40u}, + {0x30u, 0xFFu}, + {0x31u, 0x01u}, + {0x33u, 0x0Cu}, + {0x35u, 0x70u}, + {0x37u, 0x02u}, + {0x3Au, 0x02u}, + {0x3Bu, 0x08u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0xFFu}, + {0x84u, 0x30u}, + {0x86u, 0xC0u}, + {0x87u, 0x01u}, + {0x88u, 0x50u}, + {0x8Au, 0xA0u}, + {0x8Bu, 0x20u}, + {0x8Cu, 0x90u}, + {0x8Eu, 0x60u}, + {0x90u, 0x03u}, + {0x92u, 0x0Cu}, + {0x93u, 0x04u}, + {0x94u, 0xFFu}, + {0x97u, 0x10u}, + {0x98u, 0x05u}, + {0x9Au, 0x0Au}, + {0x9Bu, 0x08u}, + {0xA2u, 0xFFu}, + {0xA3u, 0x02u}, + {0xA8u, 0x09u}, + {0xAAu, 0x06u}, + {0xACu, 0x0Fu}, + {0xADu, 0x15u}, + {0xAEu, 0xF0u}, + {0xAFu, 0x2Au}, + {0xB1u, 0x03u}, + {0xB3u, 0x0Cu}, + {0xB5u, 0x30u}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, + {0xBFu, 0x15u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x10u}, + {0x02u, 0x23u}, + {0x03u, 0x88u}, + {0x05u, 0x80u}, + {0x06u, 0x20u}, + {0x07u, 0x04u}, + {0x08u, 0x01u}, + {0x09u, 0x04u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x68u}, + {0x0Eu, 0x40u}, + {0x0Fu, 0x08u}, + {0x11u, 0xA0u}, + {0x13u, 0x02u}, + {0x16u, 0x08u}, + {0x17u, 0x08u}, + {0x18u, 0x02u}, + {0x1Eu, 0x40u}, + {0x20u, 0x80u}, + {0x21u, 0x08u}, + {0x23u, 0x04u}, + {0x24u, 0x04u}, + {0x25u, 0x10u}, + {0x26u, 0x85u}, + {0x2Au, 0x01u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x08u}, + {0x2Fu, 0x60u}, + {0x30u, 0x01u}, + {0x32u, 0x24u}, + {0x36u, 0x15u}, + {0x38u, 0x04u}, + {0x39u, 0x14u}, + {0x3Du, 0x20u}, + {0x3Fu, 0x8Au}, + {0x5Au, 0x80u}, + {0x5Eu, 0x80u}, + {0x63u, 0x02u}, + {0x64u, 0x02u}, + {0x6Du, 0x80u}, + {0x6Fu, 0x03u}, + {0x82u, 0x22u}, + {0x85u, 0x0Cu}, + {0x8Au, 0x40u}, + {0x8Bu, 0x81u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x04u}, + {0x90u, 0x20u}, + {0x92u, 0x18u}, + {0x93u, 0xA0u}, + {0x95u, 0x01u}, + {0x97u, 0x44u}, + {0x98u, 0x41u}, + {0x9Au, 0x28u}, + {0x9Bu, 0x18u}, + {0x9Du, 0x25u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x08u}, + {0xA2u, 0x10u}, + {0xA3u, 0x40u}, + {0xA4u, 0x65u}, + {0xA6u, 0x84u}, + {0xA8u, 0x40u}, + {0xAAu, 0x40u}, + {0xACu, 0x01u}, + {0xAFu, 0x10u}, + {0xB0u, 0x05u}, + {0xB7u, 0x02u}, + {0xC0u, 0xEFu}, + {0xC2u, 0xFEu}, + {0xC4u, 0x6Bu}, + {0xCAu, 0xE9u}, + {0xCCu, 0xE7u}, + {0xCEu, 0xF6u}, + {0xD6u, 0x18u}, + {0xD8u, 0x18u}, + {0xE0u, 0x02u}, + {0xE2u, 0xC0u}, + {0xE6u, 0x60u}, + {0xEAu, 0xACu}, + {0xEEu, 0x05u}, + {0x01u, 0x02u}, + {0x02u, 0x02u}, + {0x03u, 0x01u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x02u}, + {0x10u, 0x90u}, + {0x12u, 0x48u}, + {0x15u, 0x02u}, + {0x16u, 0x61u}, + {0x17u, 0x09u}, + {0x19u, 0x01u}, + {0x1Au, 0x0Cu}, + {0x1Bu, 0x02u}, + {0x1Du, 0x02u}, + {0x1Eu, 0x10u}, + {0x1Fu, 0x11u}, + {0x22u, 0x80u}, + {0x24u, 0x90u}, + {0x26u, 0x24u}, + {0x2Au, 0x90u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x05u}, + {0x30u, 0x03u}, + {0x31u, 0x10u}, + {0x32u, 0xE0u}, + {0x33u, 0x04u}, + {0x34u, 0x1Cu}, + {0x35u, 0x03u}, + {0x37u, 0x08u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x01u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x30u}, + {0x82u, 0xC0u}, + {0x84u, 0x50u}, + {0x86u, 0xA0u}, + {0x87u, 0x08u}, + {0x88u, 0x60u}, + {0x8Au, 0x90u}, + {0x8Cu, 0x0Fu}, + {0x8Eu, 0xF0u}, + {0x8Fu, 0x01u}, + {0x91u, 0x0Au}, + {0x93u, 0x14u}, + {0x97u, 0x04u}, + {0x98u, 0x06u}, + {0x9Au, 0x09u}, + {0x9Bu, 0x02u}, + {0x9Fu, 0x20u}, + {0xA4u, 0x05u}, + {0xA6u, 0x0Au}, + {0xABu, 0x10u}, + {0xACu, 0x03u}, + {0xAEu, 0x0Cu}, + {0xB1u, 0x06u}, + {0xB3u, 0x01u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x20u}, + {0xB7u, 0x18u}, + {0xBEu, 0x10u}, + {0xBFu, 0x41u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x10u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x01u}, + {0x03u, 0x01u}, + {0x05u, 0x2Bu}, + {0x06u, 0x10u}, + {0x07u, 0x01u}, + {0x09u, 0x40u}, + {0x0Au, 0x14u}, + {0x0Bu, 0x80u}, + {0x0Fu, 0x08u}, + {0x10u, 0x28u}, + {0x11u, 0x02u}, + {0x14u, 0x20u}, + {0x15u, 0x48u}, + {0x1Au, 0x1Cu}, + {0x1Bu, 0x02u}, + {0x1Fu, 0x10u}, + {0x21u, 0x29u}, + {0x22u, 0x40u}, + {0x24u, 0x02u}, + {0x26u, 0x11u}, + {0x27u, 0x10u}, + {0x28u, 0x02u}, + {0x2Du, 0x20u}, + {0x31u, 0x28u}, + {0x32u, 0x40u}, + {0x34u, 0x20u}, + {0x35u, 0x08u}, + {0x36u, 0x80u}, + {0x37u, 0x01u}, + {0x39u, 0x02u}, + {0x3Fu, 0x48u}, + {0x5Au, 0x40u}, + {0x5Cu, 0x44u}, + {0x5Fu, 0x12u}, + {0x60u, 0x02u}, + {0x64u, 0x40u}, + {0x66u, 0x2Au}, + {0x67u, 0x0Au}, + {0x80u, 0x08u}, + {0x82u, 0x02u}, + {0x86u, 0x08u}, + {0x87u, 0x04u}, + {0x8Bu, 0x04u}, + {0x8Fu, 0x03u}, + {0x90u, 0x24u}, + {0x91u, 0x48u}, + {0x93u, 0x80u}, + {0x94u, 0x02u}, + {0x9Bu, 0x08u}, + {0x9Du, 0x06u}, + {0x9Fu, 0x01u}, + {0xA1u, 0x41u}, + {0xA3u, 0x44u}, + {0xA4u, 0x40u}, + {0xA5u, 0x20u}, + {0xA6u, 0x05u}, + {0xADu, 0x04u}, + {0xAFu, 0x01u}, + {0xC0u, 0xF9u}, + {0xC2u, 0x4Fu}, + {0xC4u, 0xAEu}, + {0xCAu, 0x28u}, + {0xCCu, 0xFEu}, + {0xCEu, 0x51u}, + {0xD6u, 0xF8u}, + {0xD8u, 0xF8u}, + {0xE2u, 0x40u}, + {0xEAu, 0x01u}, + {0xEEu, 0x8Du}, + {0x80u, 0x04u}, + {0x81u, 0x04u}, + {0x82u, 0x04u}, + {0x85u, 0x22u}, + {0x88u, 0x40u}, + {0x8Bu, 0x48u}, + {0x8Du, 0x40u}, + {0x90u, 0x20u}, + {0x94u, 0x02u}, + {0xA1u, 0x41u}, + {0xA3u, 0x44u}, + {0xA6u, 0x01u}, + {0xB7u, 0x44u}, + {0xE0u, 0x40u}, + {0xE2u, 0x04u}, + {0xE4u, 0x80u}, {0xE8u, 0x40u}, - {0xECu, 0x80u}, - {0x13u, 0x10u}, + {0xECu, 0x40u}, + {0xEEu, 0x80u}, + {0x80u, 0x11u}, + {0x81u, 0x01u}, + {0x89u, 0x40u}, + {0x8Eu, 0x01u}, + {0xE2u, 0x10u}, + {0xE4u, 0x20u}, + {0x82u, 0x02u}, + {0x83u, 0x07u}, + {0x88u, 0x11u}, + {0x8Au, 0x22u}, + {0x8Cu, 0x28u}, + {0x8Eu, 0x13u}, + {0x91u, 0x34u}, + {0x95u, 0x07u}, + {0x96u, 0x01u}, + {0x98u, 0x60u}, + {0x9Bu, 0x2Au}, + {0x9Eu, 0x0Cu}, + {0x9Fu, 0x08u}, + {0xA4u, 0x14u}, + {0xA6u, 0x43u}, + {0xA9u, 0x01u}, + {0xABu, 0x18u}, + {0xB1u, 0x38u}, + {0xB4u, 0x70u}, + {0xB6u, 0x0Fu}, + {0xB7u, 0x07u}, + {0xB8u, 0x20u}, + {0xBFu, 0x40u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x01u, 0x01u}, + {0x03u, 0x01u}, + {0x04u, 0x40u}, + {0x05u, 0x20u}, + {0x06u, 0x40u}, + {0x09u, 0x80u}, + {0x0Au, 0x94u}, + {0x0Eu, 0x2Au}, + {0x0Fu, 0x01u}, + {0x11u, 0x10u}, + {0x12u, 0x21u}, + {0x13u, 0x08u}, + {0x17u, 0x08u}, + {0x18u, 0x44u}, + {0x19u, 0x29u}, + {0x1Au, 0x90u}, + {0x1Bu, 0x04u}, + {0x1Eu, 0x0Au}, + {0x22u, 0x02u}, + {0x27u, 0x82u}, + {0x29u, 0x29u}, + {0x2Au, 0x40u}, + {0x2Du, 0x20u}, + {0x31u, 0x10u}, + {0x32u, 0x20u}, + {0x33u, 0x49u}, + {0x35u, 0x01u}, + {0x36u, 0x24u}, + {0x37u, 0x80u}, + {0x38u, 0x80u}, + {0x39u, 0x18u}, + {0x3Fu, 0x01u}, + {0x40u, 0x64u}, + {0x49u, 0x14u}, + {0x4Bu, 0x40u}, + {0x50u, 0x20u}, + {0x52u, 0x41u}, + {0x53u, 0x06u}, + {0x63u, 0x80u}, + {0x69u, 0x19u}, + {0x6Au, 0x04u}, + {0x6Bu, 0x61u}, + {0x70u, 0x40u}, + {0x71u, 0x80u}, + {0x80u, 0x20u}, + {0x87u, 0x02u}, + {0x8Bu, 0x80u}, + {0x93u, 0x40u}, + {0x94u, 0x84u}, + {0x95u, 0x19u}, + {0x96u, 0x90u}, + {0x97u, 0x08u}, + {0x9Du, 0x05u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x61u}, + {0xA2u, 0x30u}, + {0xA3u, 0x48u}, + {0xA4u, 0x20u}, + {0xA5u, 0x80u}, + {0xA6u, 0x02u}, + {0xA7u, 0x06u}, + {0xA8u, 0x08u}, + {0xAEu, 0x60u}, + {0xB1u, 0x04u}, + {0xB2u, 0x08u}, + {0xB3u, 0x20u}, + {0xB4u, 0x01u}, + {0xC0u, 0xDDu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x27u}, + {0xCAu, 0x2Fu}, + {0xCCu, 0xFFu}, + {0xCEu, 0x8Eu}, + {0xD0u, 0x07u}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x01u}, + {0xE6u, 0x20u}, + {0xEAu, 0x09u}, + {0xEEu, 0x02u}, + {0x01u, 0x05u}, + {0x03u, 0x08u}, + {0x04u, 0x0Fu}, + {0x06u, 0xF0u}, + {0x07u, 0x01u}, + {0x08u, 0x60u}, + {0x0Au, 0x90u}, + {0x0Cu, 0x05u}, + {0x0Eu, 0x0Au}, + {0x0Fu, 0x08u}, + {0x10u, 0x50u}, + {0x12u, 0xA0u}, + {0x14u, 0x30u}, + {0x15u, 0x01u}, + {0x16u, 0xC0u}, + {0x17u, 0x08u}, + {0x18u, 0x03u}, + {0x1Au, 0x0Cu}, + {0x1Eu, 0xFFu}, + {0x20u, 0x06u}, + {0x21u, 0x04u}, + {0x22u, 0x09u}, + {0x23u, 0x08u}, + {0x26u, 0xFFu}, + {0x28u, 0xFFu}, + {0x2Du, 0x02u}, + {0x31u, 0x0Fu}, + {0x33u, 0x0Fu}, + {0x36u, 0xFFu}, + {0x39u, 0x0Au}, + {0x3Eu, 0x40u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x10u}, + {0x84u, 0x87u}, + {0x85u, 0x03u}, + {0x86u, 0x18u}, + {0x88u, 0x04u}, + {0x89u, 0x03u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x03u}, + {0x90u, 0xA2u}, + {0x92u, 0x08u}, + {0x93u, 0x03u}, + {0x94u, 0x01u}, + {0x97u, 0x04u}, + {0x98u, 0x40u}, + {0x9Bu, 0x01u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x03u}, + {0xA0u, 0x01u}, + {0xA4u, 0x88u}, + {0xA6u, 0x21u}, + {0xA8u, 0x01u}, + {0xABu, 0x08u}, + {0xACu, 0x40u}, + {0xB0u, 0x80u}, + {0xB1u, 0x02u}, + {0xB2u, 0x40u}, + {0xB3u, 0x08u}, + {0xB4u, 0x3Fu}, + {0xB5u, 0x04u}, + {0xB6u, 0x08u}, + {0xB7u, 0x01u}, + {0xB8u, 0x28u}, + {0xBEu, 0x51u}, + {0xBFu, 0x41u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x10u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x02u, 0x40u}, + {0x03u, 0x09u}, + {0x05u, 0x40u}, + {0x06u, 0x14u}, + {0x09u, 0x80u}, + {0x0Au, 0x98u}, + {0x0Cu, 0x40u}, + {0x0Du, 0x11u}, + {0x0Fu, 0x20u}, + {0x11u, 0x01u}, + {0x12u, 0x22u}, + {0x13u, 0x20u}, + {0x14u, 0x80u}, + {0x15u, 0x04u}, + {0x17u, 0x10u}, + {0x19u, 0x80u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x09u}, + {0x1Eu, 0x01u}, + {0x20u, 0x09u}, + {0x22u, 0x09u}, + {0x23u, 0x40u}, + {0x25u, 0x03u}, + {0x26u, 0x04u}, + {0x28u, 0x02u}, + {0x2Au, 0x20u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x82u}, + {0x30u, 0x28u}, + {0x32u, 0x10u}, + {0x33u, 0x41u}, + {0x37u, 0x04u}, + {0x38u, 0x80u}, + {0x39u, 0x18u}, + {0x3Au, 0x08u}, + {0x3Du, 0x0Eu}, + {0x3Eu, 0x40u}, + {0x58u, 0x10u}, + {0x59u, 0x84u}, + {0x5Au, 0x02u}, + {0x5Eu, 0x80u}, + {0x62u, 0x01u}, + {0x63u, 0x02u}, + {0x67u, 0x01u}, + {0x84u, 0x12u}, + {0x88u, 0x16u}, + {0x8Bu, 0x0Cu}, + {0x8Eu, 0x10u}, + {0x91u, 0x22u}, + {0x92u, 0x40u}, + {0x94u, 0x04u}, + {0x95u, 0x11u}, + {0x96u, 0x81u}, + {0x97u, 0x01u}, + {0x98u, 0xC0u}, + {0x99u, 0x40u}, + {0x9Au, 0x14u}, + {0x9Bu, 0x14u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x49u}, + {0x9Fu, 0x09u}, + {0xA0u, 0x80u}, + {0xA1u, 0x04u}, + {0xA2u, 0x30u}, + {0xA3u, 0x70u}, + {0xA4u, 0x10u}, + {0xA5u, 0x83u}, + {0xA6u, 0x0Cu}, + {0xA7u, 0x06u}, + {0xA8u, 0x22u}, + {0xAAu, 0x40u}, + {0xABu, 0x08u}, + {0xB1u, 0x43u}, + {0xB2u, 0x80u}, + {0xB6u, 0x20u}, + {0xC0u, 0xEFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x7Fu}, + {0xCAu, 0x94u}, + {0xCCu, 0x4Fu}, + {0xCEu, 0xDEu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x19u}, + {0xE6u, 0x44u}, + {0xE8u, 0x04u}, + {0xEAu, 0x03u}, + {0xEEu, 0x08u}, + {0x01u, 0x01u}, + {0x03u, 0x02u}, + {0x05u, 0x02u}, + {0x07u, 0x01u}, + {0x08u, 0x08u}, + {0x09u, 0x02u}, + {0x0Au, 0x12u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x1Au}, + {0x0Du, 0x10u}, + {0x0Eu, 0x64u}, + {0x0Fu, 0x08u}, + {0x11u, 0x02u}, + {0x13u, 0x21u}, + {0x14u, 0x10u}, + {0x15u, 0x08u}, + {0x16u, 0x08u}, + {0x17u, 0x10u}, + {0x18u, 0x80u}, + {0x19u, 0x10u}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x20u}, + {0x1Eu, 0x44u}, + {0x20u, 0x40u}, + {0x21u, 0x10u}, + {0x22u, 0x20u}, + {0x23u, 0x0Cu}, + {0x24u, 0x01u}, + {0x25u, 0x10u}, + {0x27u, 0x08u}, + {0x29u, 0x02u}, + {0x2Bu, 0x01u}, + {0x30u, 0x80u}, + {0x31u, 0x03u}, + {0x32u, 0x01u}, + {0x33u, 0x20u}, + {0x34u, 0x06u}, + {0x35u, 0x18u}, + {0x36u, 0x78u}, + {0x37u, 0x04u}, + {0x3Bu, 0x22u}, + {0x3Eu, 0x50u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x19u}, + {0x5Fu, 0x01u}, + {0x82u, 0xFFu}, + {0x84u, 0x09u}, + {0x86u, 0x06u}, + {0x88u, 0x50u}, + {0x8Au, 0xA0u}, + {0x8Cu, 0x0Fu}, + {0x8Eu, 0xF0u}, + {0x90u, 0x03u}, + {0x92u, 0x0Cu}, + {0x96u, 0xFFu}, + {0x98u, 0x05u}, + {0x9Au, 0x0Au}, + {0xA2u, 0xFFu}, + {0xA4u, 0x30u}, + {0xA6u, 0xC0u}, + {0xACu, 0x90u}, + {0xAEu, 0x60u}, + {0xB0u, 0xFFu}, + {0xBEu, 0x01u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x44u}, + {0x01u, 0x10u}, + {0x03u, 0x82u}, + {0x04u, 0x60u}, + {0x08u, 0x01u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x18u}, + {0x11u, 0x84u}, + {0x12u, 0x21u}, + {0x13u, 0x02u}, + {0x15u, 0x01u}, + {0x17u, 0x08u}, + {0x18u, 0x80u}, + {0x1Cu, 0x08u}, + {0x1Du, 0x04u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x80u}, + {0x24u, 0x01u}, + {0x25u, 0x25u}, + {0x26u, 0x08u}, + {0x27u, 0x0Cu}, + {0x2Cu, 0x60u}, + {0x2Fu, 0x04u}, + {0x34u, 0x02u}, + {0x37u, 0x14u}, + {0x3Cu, 0x02u}, + {0x3Du, 0x0Au}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x40u}, + {0x44u, 0x40u}, + {0x46u, 0x40u}, + {0x59u, 0x80u}, + {0x62u, 0x40u}, + {0x64u, 0x08u}, + {0x66u, 0x06u}, + {0x67u, 0x02u}, + {0x6Du, 0x95u}, + {0x74u, 0x80u}, + {0x75u, 0x21u}, + {0x76u, 0x10u}, + {0x82u, 0x02u}, + {0x88u, 0x08u}, + {0x89u, 0x20u}, + {0x8Bu, 0x40u}, + {0x8Eu, 0x40u}, + {0x8Fu, 0x01u}, + {0x90u, 0x24u}, + {0x92u, 0x18u}, + {0x93u, 0x20u}, + {0x94u, 0x80u}, + {0x95u, 0x11u}, + {0x97u, 0x40u}, + {0x98u, 0x03u}, + {0x9Bu, 0x10u}, + {0x9Du, 0x25u}, + {0x9Eu, 0x11u}, + {0x9Fu, 0x06u}, + {0xA2u, 0x04u}, + {0xA3u, 0x02u}, + {0xA4u, 0x05u}, + {0xA6u, 0x20u}, + {0xA7u, 0x80u}, + {0xA8u, 0x40u}, + {0xA9u, 0x80u}, + {0xAAu, 0x40u}, + {0xB0u, 0x20u}, + {0xB2u, 0x04u}, + {0xB3u, 0x08u}, + {0xB6u, 0xC0u}, + {0xB7u, 0x20u}, + {0xC0u, 0xCFu}, + {0xC2u, 0xEEu}, + {0xC4u, 0x3Du}, + {0xCAu, 0xE0u}, + {0xCCu, 0xE0u}, + {0xCEu, 0xF0u}, + {0xD6u, 0x08u}, + {0xD8u, 0xF8u}, + {0xE0u, 0xE0u}, + {0xE6u, 0xC0u}, + {0xEAu, 0xA2u}, + {0xECu, 0x20u}, + {0xEEu, 0x49u}, + {0xA8u, 0x21u}, + {0xAEu, 0x08u}, + {0xB2u, 0x20u}, + {0xB3u, 0x06u}, + {0xB5u, 0x80u}, + {0xB6u, 0x04u}, + {0xE8u, 0xA0u}, + {0xECu, 0x90u}, + {0xEEu, 0x02u}, + {0x12u, 0x08u}, {0x16u, 0x80u}, - {0x17u, 0x20u}, - {0x30u, 0x08u}, + {0x17u, 0x80u}, + {0x33u, 0x08u}, {0x35u, 0x01u}, {0x36u, 0x80u}, - {0x39u, 0x04u}, {0x3Au, 0x80u}, - {0x3Cu, 0x08u}, - {0x3Fu, 0x20u}, - {0x42u, 0x08u}, - {0x49u, 0x10u}, - {0x4Bu, 0x10u}, - {0x5Bu, 0x40u}, - {0x5Eu, 0x04u}, - {0x61u, 0x40u}, - {0x63u, 0x08u}, - {0x64u, 0x40u}, - {0x8Du, 0x01u}, + {0x3Bu, 0x01u}, + {0x3Fu, 0x18u}, + {0x40u, 0x04u}, + {0x59u, 0x08u}, + {0x5Au, 0x80u}, + {0x5Eu, 0x02u}, + {0x61u, 0x20u}, + {0x65u, 0x20u}, + {0x81u, 0x08u}, + {0x83u, 0x01u}, + {0x8Du, 0x20u}, + {0x8Eu, 0x01u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, @@ -2048,187 +1911,171 @@ void cyfitter_cfg(void) {0xD4u, 0x80u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0x31u, 0x10u}, - {0x33u, 0x01u}, - {0x34u, 0x01u}, - {0x37u, 0x20u}, - {0x39u, 0x20u}, - {0x53u, 0x04u}, - {0x57u, 0x02u}, - {0x58u, 0x80u}, - {0x66u, 0x80u}, - {0x81u, 0x01u}, - {0x83u, 0x40u}, - {0x88u, 0x88u}, - {0x96u, 0x04u}, - {0x99u, 0x10u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x40u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x40u}, - {0xA4u, 0x0Cu}, + {0xE2u, 0x80u}, + {0xE6u, 0x20u}, + {0x33u, 0x11u}, + {0x34u, 0x02u}, + {0x37u, 0x80u}, + {0x39u, 0x40u}, + {0x51u, 0x08u}, + {0x52u, 0x02u}, + {0x5Du, 0x02u}, + {0x5Eu, 0x40u}, + {0x82u, 0x02u}, + {0x83u, 0x08u}, + {0x92u, 0x02u}, + {0x94u, 0x04u}, + {0x96u, 0x80u}, + {0x9Bu, 0x90u}, + {0x9Du, 0x21u}, {0xA6u, 0x80u}, - {0xA7u, 0x04u}, - {0xADu, 0x04u}, - {0xB7u, 0x10u}, + {0xA7u, 0x0Cu}, + {0xAAu, 0x08u}, + {0xABu, 0x10u}, + {0xAEu, 0x01u}, + {0xAFu, 0x10u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0xA0u}, {0xD6u, 0xA0u}, - {0xE2u, 0x20u}, + {0xE2u, 0x80u}, {0xE6u, 0x80u}, + {0xEAu, 0x10u}, {0xEEu, 0x40u}, {0x12u, 0x80u}, {0x33u, 0x80u}, - {0x59u, 0x01u}, - {0x86u, 0x80u}, - {0x87u, 0x04u}, - {0x95u, 0x20u}, - {0x96u, 0x04u}, - {0x97u, 0x08u}, - {0x99u, 0x01u}, - {0x9Cu, 0x41u}, - {0x9Eu, 0x88u}, + {0x5Au, 0x02u}, + {0x89u, 0x08u}, + {0x8Cu, 0x04u}, + {0x92u, 0x02u}, + {0x94u, 0x04u}, + {0x96u, 0x80u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x23u}, {0x9Fu, 0x01u}, - {0xA4u, 0x04u}, + {0xA5u, 0x08u}, {0xA6u, 0x80u}, - {0xABu, 0x04u}, - {0xADu, 0x40u}, - {0xB7u, 0x02u}, + {0xA7u, 0x04u}, + {0xA9u, 0x40u}, + {0xB6u, 0x40u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, {0xD6u, 0x40u}, - {0xE2u, 0x40u}, - {0xE6u, 0x10u}, - {0xEEu, 0x30u}, - {0x83u, 0x20u}, - {0x96u, 0x04u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x08u}, + {0xEEu, 0x20u}, + {0x8Eu, 0x40u}, + {0x96u, 0x80u}, + {0x9Du, 0x01u}, {0x9Fu, 0x01u}, - {0xA2u, 0x20u}, - {0xA7u, 0x80u}, - {0xACu, 0x01u}, - {0xAEu, 0x20u}, - {0xB0u, 0x04u}, - {0xB1u, 0x10u}, - {0xE6u, 0x20u}, - {0xEAu, 0x40u}, - {0xEEu, 0x40u}, + {0xA7u, 0x84u}, + {0xA8u, 0x02u}, + {0xA9u, 0x02u}, + {0xB1u, 0x20u}, + {0xEEu, 0xA0u}, {0x08u, 0x02u}, - {0x09u, 0x80u}, + {0x09u, 0x20u}, {0x0Du, 0x01u}, - {0x10u, 0x20u}, - {0x14u, 0x20u}, - {0x51u, 0x04u}, - {0x56u, 0x01u}, - {0x57u, 0x40u}, - {0x59u, 0x10u}, - {0x80u, 0x20u}, - {0x81u, 0x80u}, + {0x10u, 0x80u}, + {0x17u, 0x08u}, + {0x51u, 0x10u}, + {0x54u, 0x40u}, + {0x5Bu, 0x80u}, + {0x5Du, 0x80u}, {0xC2u, 0x0Eu}, {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x02u, 0x04u}, - {0x03u, 0x40u}, - {0x04u, 0x01u}, - {0x07u, 0x08u}, + {0x03u, 0x88u}, + {0x04u, 0x10u}, + {0x05u, 0x02u}, {0x0Au, 0x01u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x08u}, - {0x0Du, 0x80u}, - {0x84u, 0x20u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x80u}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x22u}, + {0x80u, 0x02u}, + {0x8Bu, 0x80u}, {0x91u, 0x02u}, - {0x95u, 0x08u}, - {0x98u, 0x22u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x01u}, - {0xA7u, 0x40u}, + {0x95u, 0x20u}, + {0x98u, 0x02u}, + {0x9Bu, 0x08u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x80u}, + {0xA1u, 0x20u}, + {0xA4u, 0x40u}, + {0xB0u, 0x80u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE2u, 0x08u}, - {0xE6u, 0x08u}, - {0x89u, 0x05u}, + {0xE4u, 0x04u}, + {0xEEu, 0x01u}, + {0x88u, 0x40u}, + {0x8Du, 0x80u}, + {0x90u, 0x10u}, {0x91u, 0x02u}, - {0x93u, 0x20u}, - {0x95u, 0x08u}, + {0x93u, 0x80u}, + {0x95u, 0x20u}, + {0x97u, 0x02u}, {0x98u, 0x02u}, - {0x9Au, 0x04u}, {0x9Bu, 0x08u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x01u}, - {0xA0u, 0x08u}, - {0xA7u, 0x40u}, - {0xABu, 0x40u}, + {0x9Du, 0x80u}, + {0xA1u, 0x20u}, + {0xA3u, 0x80u}, + {0xA4u, 0x40u}, + {0xA8u, 0x20u}, + {0xABu, 0x09u}, + {0xADu, 0x02u}, {0xB2u, 0x01u}, - {0xE2u, 0x04u}, - {0xE4u, 0x01u}, + {0xE4u, 0x06u}, {0xEEu, 0x01u}, {0x09u, 0x08u}, - {0x0Bu, 0x04u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x02u}, - {0x82u, 0x05u}, - {0x87u, 0x10u}, - {0x8Bu, 0x20u}, - {0x93u, 0x20u}, - {0x97u, 0x04u}, + {0x0Bu, 0x02u}, + {0x0Fu, 0x22u}, + {0x85u, 0x10u}, + {0x88u, 0x02u}, + {0x91u, 0x02u}, + {0x95u, 0x20u}, + {0x97u, 0x02u}, {0x98u, 0x02u}, - {0x9Au, 0x04u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x01u}, - {0xA5u, 0x02u}, - {0xA7u, 0x40u}, - {0xA8u, 0x08u}, - {0xADu, 0x02u}, - {0xAFu, 0x08u}, - {0xB3u, 0x04u}, + {0xA1u, 0x20u}, + {0xA7u, 0x10u}, + {0xABu, 0x98u}, + {0xAFu, 0x40u}, + {0xB4u, 0x10u}, {0xC2u, 0x0Fu}, - {0xE2u, 0x01u}, - {0xEEu, 0x04u}, - {0x86u, 0x04u}, - {0x88u, 0x40u}, - {0x96u, 0x04u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x08u}, - {0xA2u, 0x20u}, - {0xA3u, 0x20u}, + {0xE2u, 0x04u}, + {0xEAu, 0x08u}, + {0x83u, 0x04u}, + {0x8Du, 0x01u}, + {0x9Du, 0x01u}, + {0xA7u, 0x04u}, {0xAFu, 0x81u}, - {0xE2u, 0x40u}, + {0xE6u, 0x20u}, {0xEAu, 0x40u}, {0xEEu, 0x10u}, - {0x06u, 0x40u}, - {0x52u, 0x20u}, - {0x57u, 0x20u}, - {0x86u, 0x40u}, - {0x8Au, 0x08u}, - {0x9Eu, 0x08u}, - {0xA2u, 0x20u}, - {0xA3u, 0x20u}, + {0x05u, 0x02u}, + {0x57u, 0x08u}, + {0x5Bu, 0x20u}, + {0x81u, 0x02u}, + {0x87u, 0x08u}, + {0x8Bu, 0x20u}, {0xC0u, 0x20u}, - {0xD4u, 0x60u}, - {0xE0u, 0x10u}, - {0x81u, 0x10u}, - {0x8Fu, 0x40u}, - {0x98u, 0x02u}, - {0x9Du, 0x10u}, - {0xA7u, 0x60u}, + {0xD4u, 0xC0u}, + {0xE4u, 0x20u}, + {0xE6u, 0x40u}, + {0x91u, 0x02u}, + {0x9Fu, 0x40u}, + {0xA1u, 0x20u}, + {0xABu, 0x40u}, {0xADu, 0x08u}, {0xAFu, 0x01u}, - {0xE4u, 0x02u}, - {0x03u, 0x20u}, - {0xA7u, 0x20u}, - {0xB4u, 0x02u}, + {0x03u, 0x40u}, + {0x9Fu, 0x40u}, + {0xADu, 0x01u}, + {0xB5u, 0x20u}, {0xC0u, 0x08u}, - {0xEAu, 0x08u}, + {0xEEu, 0x02u}, {0x10u, 0x03u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, - {0x1Cu, 0x02u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x03u}, {0x1Du, 0x01u}, {0x00u, 0xFDu}, {0x01u, 0xBFu}, @@ -2254,18 +2101,30 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0x6Cu, 0x00u, 0x00u, 0x00u, 0x71u, 0xC0u, 0x82u, 0x04u, 0x00u, 0xC0u, 0x00u, 0x08u, 0x2Cu, 0xC0u, 0x40u, 0x01u, + 0xC0u, 0x90u, 0x2Fu, 0x40u, 0xA4u, 0x00u, 0x40u, 0x60u, 0x64u, 0x00u, 0x08u, 0xFFu, 0x6Cu, 0xC0u, 0x00u, 0x02u, + 0x00u, 0x7Fu, 0x00u, 0x80u, 0x91u, 0x80u, 0x4Eu, 0x00u, 0x40u, 0x1Fu, 0x2Cu, 0x20u, 0x08u, 0x00u, 0x10u, 0x9Fu, + 0x31u, 0xFFu, 0xC0u, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x64u, 0x02u, 0x50u, 0x00u, 0x03u, 0x0Eu, 0xDBu, 0xCFu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 9283e1f..4d4b204 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -391,34 +391,34 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -426,13 +426,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB08_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB08_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -450,12 +450,14 @@ .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -463,9 +465,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 @@ -1945,15 +1947,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB08_09_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1966,37 +1968,37 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB08_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB08_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB08_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB08_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB08_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB08_MSK /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -2822,6 +2824,8 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2829,9 +2833,13 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST /* Debug_Timer_Interrupt */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2952,8 +2960,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2961,9 +2969,9 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 @@ -2994,34 +3002,34 @@ /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB07_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB07_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index d586df1..1dae089 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -426,13 +426,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -450,12 +450,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -463,9 +465,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 @@ -1945,15 +1947,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1966,37 +1968,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2822,6 +2824,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2829,9 +2833,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST /* Debug_Timer_Interrupt */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2952,8 +2960,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2961,9 +2969,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 @@ -2994,34 +3002,34 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 8c27006..05b0356 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -426,13 +426,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB08_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -450,12 +450,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -463,9 +465,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 @@ -1945,15 +1947,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB08_09_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1966,37 +1968,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB08_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB08_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2822,6 +2824,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2829,9 +2833,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST ; Debug_Timer_Interrupt Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2952,8 +2960,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2961,9 +2969,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 @@ -2994,34 +3002,34 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index 7c2a108..510d5c6 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -66,7 +66,7 @@