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Force unit-attention-condition off for pre-SCSI2 hosts

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This commit is contained in:
Michael McMaster 2014-04-16 21:46:01 +10:00
parent 48bfd6f343
commit 36ce697d7a
8 changed files with 48 additions and 35 deletions
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6
CHANGELOG
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@ -1,11 +1,13 @@
20140??? 3.3
20140416 3.3
- Fix to SCSI Reset handling to avoid lockups
- Bug fixes to improve standards compatibility
- Bug fix for Unit Attention Condition, which is now enabled by default.
- scsi2sd-config can be used to disable it for those systems that
scsi2sd-config can be used to disable it for those systems that
truely require it (eg. Mac Plus).
- Added Linked commands support.
- Added support for configurable sector sizes between 64 and 2048 bytes.
The sector size can be set via the MODE SELECT command using a SCSI
format utility, or via scsi2sd-config
- Powerbook firmware added
20140214 3.2

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software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit
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software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit
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4
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
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@ -1663,14 +1663,14 @@
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>
<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>
</warp_dep>
<deps_time v="130400487594237024" />
<deps_time v="130421205782926169" />
<top_block v="TopDesign" />
<last_generation v="0" />
</CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>
</dataGuid>
<dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">
<CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">
<deps_time v="130400487992691193" />
<deps_time v="130421206235126109" />
</CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>
</dataGuid>
<dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">

54
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt
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@ -1,13 +1,13 @@
Loading plugins phase: Elapsed time ==> 0s.499ms
Initializing data phase: Elapsed time ==> 3s.703ms
Loading plugins phase: Elapsed time ==> 0s.481ms
Initializing data phase: Elapsed time ==> 3s.796ms
<CYPRESSTAG name="CyDsfit arguments...">
cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>
<CYPRESSTAG name="Design elaboration results...">
</CYPRESSTAG>
Elaboration phase: Elapsed time ==> 7s.531ms
Elaboration phase: Elapsed time ==> 7s.874ms
<CYPRESSTAG name="HDL generation results...">
</CYPRESSTAG>
HDL generation phase: Elapsed time ==> 0s.109ms
HDL generation phase: Elapsed time ==> 0s.173ms
<CYPRESSTAG name="Synthesis results...">
| | | | | | |
@ -41,7 +41,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof
======================================================================
vlogfe V6.3 IR 41: Verilog parser
Sun Mar 23 21:45:41 2014
Wed Apr 16 21:15:58 2014
======================================================================
@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v
======================================================================
vpp V6.3 IR 41: Verilog Pre-Processor
Sun Mar 23 21:45:41 2014
Wed Apr 16 21:15:59 2014
vpp: No errors.
@ -80,7 +80,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof
======================================================================
tovif V6.3 IR 41: High-level synthesis
Sun Mar 23 21:45:42 2014
Wed Apr 16 21:15:59 2014
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
@ -104,7 +104,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof
======================================================================
topld V6.3 IR 41: Synthesis and optimization
Sun Mar 23 21:45:42 2014
Wed Apr 16 21:16:00 2014
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.
@ -204,10 +204,10 @@ CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\wa
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe
Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog
</CYPRESSTAG>
Warp synthesis phase: Elapsed time ==> 1s.454ms
Warp synthesis phase: Elapsed time ==> 2s.967ms
<CYPRESSTAG name="Fitter results...">
<CYPRESSTAG name="Fitter startup details...">
cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 23 March 2014 21:45:43
cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Wednesday, 16 April 2014 21:16:01
Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog
</CYPRESSTAG>
<CYPRESSTAG name="Design parsing">
@ -1314,7 +1314,7 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00%
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%
SAR Fixed Blocks : 0 : 1 : 1 : 0.00%
</CYPRESSTAG>
Technology Mapping: Elapsed time ==> 0s.031ms
Technology Mapping: Elapsed time ==> 0s.015ms
Tech mapping phase: Elapsed time ==> 0s.281ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Placement">
@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed)
IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)
IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)
USB[0]@[FFB(USB,0)] : \USBFS:USB\
Analog Placement phase: Elapsed time ==> 0s.156ms
Analog Placement phase: Elapsed time ==> 0s.109ms
</CYPRESSTAG>
<CYPRESSTAG name="Analog Routing">
Analog Routing phase: Elapsed time ==> 0s.000ms
@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB
IsVddaHalfUsedForComp = False
IsVddaHalfUsedForSar0 = False
IsVddaHalfUsedForSar1 = False
Analog Code Generation phase: Elapsed time ==> 1s.187ms
Analog Code Generation phase: Elapsed time ==> 1s.031ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Placement">
<CYPRESSTAG name="Detailed placement messages">
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.
I2076: Total run-time: 2.4 sec.
I2076: Total run-time: 1.6 sec.
</CYPRESSTAG>
<CYPRESSTAG name="PLD Packing">
@ -1382,7 +1382,7 @@ PLD Packing: Elapsed time ==> 0s.000ms
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
<CYPRESSTAG name="Final Partitioning Summary">
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>
Partitioning: Elapsed time ==> 0s.078ms
Partitioning: Elapsed time ==> 0s.077ms
</CYPRESSTAG>
<CYPRESSTAG name="Simulated Annealing">
Annealing: Elapsed time ==> 0s.000ms
@ -2664,32 +2664,32 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection
</CYPRESSTAG>
</CYPRESSTAG>
</CYPRESSTAG>
Digital component placer commit/Report: Elapsed time ==> 0s.016ms
Digital Placement phase: Elapsed time ==> 3s.031ms
Digital component placer commit/Report: Elapsed time ==> 0s.017ms
Digital Placement phase: Elapsed time ==> 2s.641ms
</CYPRESSTAG>
<CYPRESSTAG name="Digital Routing">
Routing successful.
Digital Routing phase: Elapsed time ==> 3s.046ms
Digital Routing phase: Elapsed time ==> 3s.404ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream and API generation">
Bitstream and API generation phase: Elapsed time ==> 0s.718ms
Bitstream and API generation phase: Elapsed time ==> 0s.796ms
</CYPRESSTAG>
<CYPRESSTAG name="Bitstream verification">
Bitstream verification phase: Elapsed time ==> 0s.159ms
Bitstream verification phase: Elapsed time ==> 0s.171ms
</CYPRESSTAG>
<CYPRESSTAG name="Static timing analysis">
Timing report is in USB_Bootloader_timing.html.
Static timing analysis phase: Elapsed time ==> 1s.074ms
Static timing analysis phase: Elapsed time ==> 0s.812ms
</CYPRESSTAG>
<CYPRESSTAG name="Data reporting">
Data reporting phase: Elapsed time ==> 0s.000ms
</CYPRESSTAG>
<CYPRESSTAG name="Database update...">
Design database save phase: Elapsed time ==> 0s.374ms
Design database save phase: Elapsed time ==> 0s.406ms
</CYPRESSTAG>
cydsfit: Elapsed time ==> 10s.140ms
cydsfit: Elapsed time ==> 9s.781ms
</CYPRESSTAG>
Fitter phase: Elapsed time ==> 10s.233ms
API generation phase: Elapsed time ==> 4s.062ms
Dependency generation phase: Elapsed time ==> 0s.031ms
Cleanup phase: Elapsed time ==> 0s.046ms
Fitter phase: Elapsed time ==> 9s.859ms
API generation phase: Elapsed time ==> 4s.706ms
Dependency generation phase: Elapsed time ==> 0s.028ms
Cleanup phase: Elapsed time ==> 0s.063ms

2
software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html
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@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className)
<tr> <td class="prop"> Project :</td>
<td class="proptext"> USB_Bootloader</td></tr>
<tr> <td class="prop"> Build Time :</td>
<td class="proptext"> 03/23/14 21:45:52</td></tr>
<td class="proptext"> 04/16/14 21:16:10</td></tr>
<tr> <td class="prop"> Device :</td>
<td class="proptext"> CY8C5267AXI-LP051</td></tr>
<tr> <td class="prop"> Temperature :</td>

15
software/SCSI2SD/src/scsi.c
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@ -48,6 +48,10 @@ static void doReserveRelease(void);
static void enter_BusFree()
{
// This delay probably isn't needed for most SCSI hosts, but it won't
// hurt either. It's possible some of the samplers needed this delay.
CyDelayUs(2);
SCSI_ClearPin(SCSI_Out_BSY);
// We now have a Bus Clear Delay of 800ns to release remaining signals.
SCSI_ClearPin(SCSI_Out_MSG);
@ -492,9 +496,16 @@ static void process_SelectionPhase()
(goodParity || !config->enableParity) && (maskBitCount <= 2))
{
// Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says
// move to MESSAGE OUT if ATN is true before we release BSY.
// The initiate should assert ATN with SEL.
// move to MESSAGE OUT if ATN is true before we assert BSY.
// The initiator should assert ATN with SEL.
scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);
// Unit attention breaks many older SCSI hosts. Disable it completely for
// SCSI-1 (and older) hosts, regardless of our configured setting.
if (!scsiDev.atnFlag)
{
scsiDev.unitAttention = 0;
}
// We've been selected!
// Assert BSY - Selection success!

2
software/SCSI2SD/src/scsi.h
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@ -20,7 +20,7 @@
// Set this to true to log SCSI commands and status information via
// USB HID packets. The can be captured and viewed in wireshark.
// For windows users, capture using USBPcap http://desowin.org/usbpcap/
#define MM_DEBUG 1
#define MM_DEBUG 0
#include "geometry.h"
#include "sense.h"