diff --git a/CHANGELOG b/CHANGELOG index 0102860..eab1d80 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,7 +1,8 @@ -20170429 4.7.1 +20170501 4.7.1 - Fix scsi2sd-util size and sector-size inputs - Fix crash when configured scsi disk starting sector is less than SD card size + - Update to PSoC Creator 4.0 20170312 4.7 - Fix bug in SCSI Inquiry command for SCSI2 hosts diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c old mode 100644 new mode 100755 index 6c7c3fd..28d74fe --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c @@ -1,13 +1,13 @@ -/******************************************************************************* -* File Name: Bootloadable_1.c -* Version 1.30 +/****************************************************************************//** +* \file Bootloadable_1.c +* \version 1.50 * -* Description: -* Provides an API for the Bootloadable application. The API includes a -* single function for starting the bootloader. +* \brief +* Provides an API for the Bootloadable application. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -15,17 +15,25 @@ #include "Bootloadable_1.h" +/** + \defgroup functions_group Functions + @{ +*/ + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + ; +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ /******************************************************************************* * Function Name: Bootloadable_1_Load -******************************************************************************** -* Summary: -* Begins the bootloading algorithm downloading a new ACD image from the host. +****************************************************************************//** * -* Parameters: -* None +* \brief +* Schedules the Bootloader/Launcher to be launched and then performs +* a software reset to launch it * -* Returns: +* \return * This method will never return. It will load a new application and reset * the device. * @@ -33,11 +41,186 @@ void Bootloadable_1_Load(void) { /* Schedule Bootloader to start after reset */ - Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_START_BTLDR); + Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR); CySoftwareReset(); } +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +/******************************************************************************* +* Function Name: Bootloadable_1_GetActiveApplication +****************************************************************************//** +* +* \brief +* Gets the application which will be loaded after a next reset event. +* NOTE Intended for the combination project type ONLY! +* +* \return +* A number of the current active application set in the metadata section. +* \n 0 - app#0 is set as active. +* \n 1 - app#1 is set as active. +* +* \note If neither of the applications is set active, then the API returns 0x02. +* +*******************************************************************************/ +uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \ + +{ + uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE; + + if (0u != Bootloadable_1_GET_CODE_DATA( \ + Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0))) + { + result = Bootloadable_1_MD_BTLDB_ACTIVE_0; + } + else if (0u != Bootloadable_1_GET_CODE_DATA( \ + Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1))) + { + result = Bootloadable_1_MD_BTLDB_ACTIVE_1; + } + else + { + /*Do nothing, result is none*/ + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_1_SetActiveApplication +****************************************************************************//** +* +* \brief +* Sets the application which will be loaded after a next reset event. +* +* \details +* Theory: +* This API sets in the Flash (metadata section) the given active application +* number. +* +* NOTE The active application number is not set directly, but the boolean +* mark instead means that the application is active or not for the relative +* metadata. Both metadata sections are updated. For example, if the second +* application is to be set active, then in the metadata section for the first +* application there will be a "0" written, which means that it is not active, and +* for the second metadata section there will be a "1" written, which means that it is +* active. +* +* NOTE Intended for the combination project type ONLY! +* +* \param appId +* The active application number to be written to flash (metadata section) +* NOTE Possible values are: +* 0 - for the first application +* 1 - for the second application. +* Any other number is considered invalid. +* +* \return +* A status of writing to flash operation. +* \n CYRET_SUCCESS - Returned if appId was successfully changed. +* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the +* same value as the active application ID. +* \note - The other non-zero value is considered as a failure during writing to flash. +* +* \note - This API does not update Bootloader_activeApp variable. +* +*******************************************************************************/ +cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \ + +{ + cystatus result = CYRET_SUCCESS; + + uint8 CYDATA idx; + + /* If invalid application number */ + if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1) + { + result = CYRET_BAD_PARAM; + } + else + { + /* If appID has same value as active application ID */ + if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId))) + { + result = CYRET_BAD_PARAM; + } + else + { + /* Updating metadata section */ + for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++) + { + result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \ + (uint8)(idx == appId)); + } + } + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_1_WriteFlashByte +****************************************************************************//** +* +* \brief +* This API writes to flash the specified data. +* +* \param address +* The address in flash. +* +* \param inputValue +* One-byte data. +* +* \return +* A status of the writing to flash procedure. +* +*******************************************************************************/ +static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + +{ + cystatus result = CYRET_SUCCESS; + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue; + + #if(CY_PSOC4) + result = CySysFlashWriteRow((uint32) rowNum, rowData); + #else + result = CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become stale. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ + return (result); +} +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ +/** @} functions_group */ /******************************************************************************* * The following code is OBSOLETE and must not be used. @@ -75,14 +258,13 @@ void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) #if(CY_PSOC5) /*************************************************************************** - * When writing Flash, data in the instruction cache can become stale. + * When writing to flash, data in the instruction cache can become obsolete. * Therefore, the cache data does not correlate to the data just written to - * Flash. A call to CyFlushCache() is required to invalidate the data in the - * cache and force fresh information to be loaded from Flash. + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. ***************************************************************************/ CyFlushCache(); #endif /* (CY_PSOC5) */ } - /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h old mode 100644 new mode 100755 index 20358af..e06fe4b --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h @@ -1,13 +1,14 @@ -/******************************************************************************* -* File Name: Bootloadable_1.h -* Version 1.30 +/****************************************************************************//** +* \file Bootloadable_1.c +* \version 1.50 * -* Description: +* \brief * Provides an API for the Bootloadable application. The API includes a -* single function for starting bootloader. +* single function for starting the Bootloader. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,7 +25,7 @@ /* Check to see if required defines such as CY_PSOC5LP are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5LP) - #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later + #error Component Bootloadable_v1_50 requires cy_boot v3.0 or later #endif /* !defined (CY_PSOC5LP) */ @@ -41,8 +42,8 @@ /******************************************************************************* -* This variable is used by Bootloader/Bootloadable components to schedule what -* application will be started after software reset. +* This variable is used by the Bootloader/Bootloadable components to schedule which +* application will be started after a software reset. *******************************************************************************/ #if (CY_PSOC4) #if defined(__ARMCC_VERSION) @@ -57,7 +58,7 @@ /******************************************************************************* -* Get the reason of the device reset +* Gets the reason for a device reset *******************************************************************************/ #if(CY_PSOC4) #define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u) @@ -72,7 +73,7 @@ /******************************************************************************* -* Schedule Bootloader/Bootloadable to be run after software reset +* Schedule the Bootloader/Bootloadable to be run after a software reset. *******************************************************************************/ #if(CY_PSOC4) #define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) @@ -89,10 +90,41 @@ extern void Bootloadable_1_Load(void) ; /******************************************************************************* -* The following code is OBSOLETE and must not be used starting from version 1.10 +* The following code is OBSOLETE and must not be used starting from version 1.10. *******************************************************************************/ #define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x) +/******************************************************************************* +* Bootloadable's declarations for in-app bootloading. +*******************************************************************************/ +#define Bootloadable_1_MD_BTLDB_ACTIVE_0 (0x00u) + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x02u) + #define Bootloadable_1_MD_BTLDB_ACTIVE_1 (0x01u) + #define Bootloadable_1_MD_BTLDB_ACTIVE_NONE (0x02u) + #define Bootloadable_1_MD_SIZEOF (64u) + #define Bootloadable_1_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ + Bootloadable_1_MD_SIZEOF)) + #define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u) + +#else + #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x01u) +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/* Mask used to indicate starting application */ +#define Bootloadable_1_SCHEDULE_BTLDB (0x80u) +#define Bootloadable_1_SCHEDULE_BTLDR (0x40u) +#define Bootloadable_1_SCHEDULE_MASK (0xC0u) +/******************************************************************************* +* API prototypes +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \ + ; + cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \ + ; +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ /******************************************************************************* * The following code is OBSOLETE and must not be used starting from version 1.20 @@ -107,7 +139,7 @@ extern void Bootloadable_1_Load(void) ; #define Bootloadable_1_APP_ADDRESS uint16 #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) - /* Offset by 2 from 32 bit start because only need 16 bits */ + /* Offset by 2 from 32 bit start because only 16 bits are needed */ #define Bootloadable_1_META_APP_ADDR_OFFSET (3u) #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u) #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u) @@ -136,18 +168,17 @@ extern void Bootloadable_1_Load(void) ; #define Bootloadable_1_SetFlashRunType(runType) \ Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType)) - /******************************************************************************* * The following code is OBSOLETE and must not be used. * -* If the obsoleted macro definitions intended for use in the application use the +* If the obsoleted macro definitions are intended for the application, use the * following scheme, redefine your own versions of these definitions: * #ifdef * #undef * #define () * #endif * -* Note: Redefine obsoleted macro definitions with caution. They might still be +* NOTE Redefine obsoleted macro definitions with caution. They might still be * used in the application and their modification might lead to unexpected * consequences. *******************************************************************************/ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c index 0668305..a65e927 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c @@ -1,12 +1,12 @@ /******************************************************************************* * File Name: CFG_EEPROM.c -* Version 2.10 +* Version 3.0 * -* Description: -* Provides the source code to the API for the EEPROM component. +* Description: +* Provides the source code to the API for the EEPROM component. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -15,129 +15,129 @@ #include "CFG_EEPROM.h" -#if (CY_PSOC3 || CY_PSOC5LP) - - /******************************************************************************* - * Function Name: CFG_EEPROM_Enable - ******************************************************************************** - * - * Summary: - * Enable the EEPROM. - * - * Parameters: - * None - * - * Return: - * None - * - *******************************************************************************/ - void CFG_EEPROM_Enable(void) - { - CyEEPROM_Start(); - } - - - /******************************************************************************* - * Function Name: CFG_EEPROM_Start - ******************************************************************************** - * - * Summary: - * Starts EEPROM. - * - * Parameters: - * None - * - * Return: - * None - * - *******************************************************************************/ - void CFG_EEPROM_Start(void) - { - /* Enable the EEPROM */ - CFG_EEPROM_Enable(); - } - - - /******************************************************************************* - * Function Name: CFG_EEPROM_Stop - ******************************************************************************** - * - * Summary: - * Stops and powers down EEPROM. - * - * Parameters: - * None - * - * Return: - * None - * - *******************************************************************************/ - void CFG_EEPROM_Stop (void) - { - /* Disable EEPROM */ - CyEEPROM_Stop(); - } - -#endif /* (CY_PSOC3 || CY_PSOC5LP) */ - - /******************************************************************************* -* Function Name: CFG_EEPROM_EraseSector +* Function Name: CFG_EEPROM_Enable ******************************************************************************** * * Summary: -* Erases a sector of memory. This function blocks until the operation is -* complete. +* Enable the EEPROM block. Also reads the temperature and stores it for +* future writes. * * Parameters: -* sectorNumber: Sector number to erase. +* None +* +* Return: +* None +* +*******************************************************************************/ +void CFG_EEPROM_Enable(void) +{ + /* Read temperature value */ + (void)CySetTemp(); + + /* Start EEPROM block */ + CyEEPROM_Start(); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Start +******************************************************************************** +* +* Summary: +* Starts EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CFG_EEPROM_Start(void) +{ + CFG_EEPROM_Enable(); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Stop +******************************************************************************** +* +* Summary: +* Stops and powers down EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CFG_EEPROM_Stop (void) +{ + /* Stop and power down EEPROM block */ + CyEEPROM_Stop(); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_WriteByte +******************************************************************************** +* +* Summary: +* Writes a byte of data to the EEPROM. This function blocks until +* the function is complete. For a reliable write procedure to occur you should +* call CFG_EEPROM_UpdateTemperature() function if the temperature of the +* silicon has been changed for more than 10C since the component was started. +* +* Parameters: +* dataByte: The byte of data to write to the EEPROM +* address: The address of data to be written. The maximum address is dependent +* on the EEPROM size. * * Return: * CYRET_SUCCESS, if the operation was successful. -* CYRET_BAD_PARAM, if the parameter sectorNumber out of range. -* CYRET_LOCKED, if the spc is being used. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. * CYRET_UNKNOWN, if there was an SPC error. * *******************************************************************************/ -cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) +cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) { cystatus status; - - /* Start the SPC */ + uint16 rowNumber; + uint16 byteNumber; + CySpcStart(); - if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS) + if (address < CY_EEPROM_SIZE) { - /* See if we can get the SPC. */ - if(CySpcLock() == CYRET_SUCCESS) + rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW; + byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW)); + if(CYRET_SUCCESS == CySpcLock()) { - #if(CY_PSOC5A) - + status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \ + CFG_EEPROM_SPC_BYTE_WRITE_SIZE); + if (CYRET_STARTED == status) + { /* Plan for failure */ status = CYRET_UNKNOWN; - /* Command to load a row of data */ - if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + while(CY_SPC_BUSY) { - while(CY_SPC_BUSY) - { - /* Wait until SPC becomes idle */ - } - - /* SPC is idle now */ - if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) - { - status = CYRET_SUCCESS; - } + /* Wait until SPC becomes idle */ } - /* Command to erase a sector */ - if(status == CYRET_SUCCESS) + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) { - - #endif /* (CY_PSOC5A) */ - - if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + status = CYRET_SUCCESS; + } + /* Command to erase and program the row. */ + if(CYRET_SUCCESS == status) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) { /* Plan for failure */ status = CYRET_UNKNOWN; @@ -157,19 +157,153 @@ cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) { status = CYRET_UNKNOWN; } - - #if(CY_PSOC5A) - } else { status = CYRET_UNKNOWN; } + } + else + { + if (CYRET_BAD_PARAM != status) + { + status = CYRET_UNKNOWN; + } + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } - #endif /* (CY_PSOC5A) */ - /* Unlock the SPC so someone else can use it. */ - CySpcUnlock(); + return (status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_ReadByte +******************************************************************************** +* +* Summary: +* Reads and returns a byte of data from the on-chip EEPROM memory. Although +* the data is present in the CPU memory space, this function provides an +* intuitive user interface, addressing the EEPROM memory as a separate block with +* the first EERPOM byte address equal to 0x0000. +* +* Parameters: +* address: The address of data to be read. The maximum address is limited by the +* size of the EEPROM array on a specific device. +* +* Return: +* Data located at an address. +* +*******************************************************************************/ +uint8 CFG_EEPROM_ReadByte(uint16 address) +{ + uint8 retByte; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Request access to EEPROM for reading. + This is needed to reserve PHUB for read operation from EEPROM */ + CyEEPROM_ReadReserve(); + + retByte = *((reg8 *) (CYDEV_EE_BASE + address)); + + /* Release EEPROM array */ + CyEEPROM_ReadRelease(); + + CyExitCriticalSection(interruptState); + + return (retByte); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_UpdateTemperature +******************************************************************************** +* +* Summary: +* Updates and stores the temperature value. This function should be called +* before EEPROM writes if the temperature may have been changed by more than +* 10 degrees Celsius. +* +* Parameters: +* None +* +* Return: +* Status of operation, 0 if operation complete, non-zero value if error +* was detected. +* +*******************************************************************************/ +uint8 CFG_EEPROM_UpdateTemperature(void) +{ + return ((uint8)CySetTemp()); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_EraseSector +******************************************************************************** +* +* Summary: +* Erase an EEPROM sector (64 rows). This function blocks until the erase +* operation is complete. Using this API helps to erase the EEPROM sector at +* a time. This is faster than using individual writes but affects a cycle +* recourse of the whole EEPROM row. +* +* Parameters: +* sectorNumber: The sector number to erase. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) +{ + cystatus status; + + CySpcStart(); + + if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); } else { @@ -190,30 +324,33 @@ cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ******************************************************************************** * * Summary: -* Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is -* a blocking call. It will not return until the function succeeds or fails. +* Writes a row (16 bytes) of data to the EEPROM. This function blocks until +* the write operation is complete. Compared to functions that write one byte, +* this function allows writing a whole row (16 bytes) at a time. For +* a reliable write procedure to occur you should call the +* CFG_EEPROM_UpdateTemperature() function if the temperature of the +* silicon has changed for more than 10C since component was started. * * Parameters: -* rowData: Address of the data to write to the EEPROM. -* rowNumber: EEPROM row number to program. +* rowData: The address of the data to write to the EEPROM. +* rowNumber: The row number to write. * * Return: * CYRET_SUCCESS, if the operation was successful. -* CYRET_BAD_PARAM, if the parameter rowNumber out of range. -* CYRET_LOCKED, if the spc is being used. +* CYRET_BAD_PARAM, if the parameter rowNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. * CYRET_UNKNOWN, if there was an SPC error. * *******************************************************************************/ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) { cystatus status; - - /* Start the SPC */ + CySpcStart(); if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) { - /* See if we can get the SPC. */ + /* See if we can get SPC. */ if(CySpcLock() == CYRET_SUCCESS) { /* Plan for failure */ @@ -236,8 +373,8 @@ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) /* Command to erase and program the row. */ if(status == CYRET_SUCCESS) { - if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0], - dieTemperature[1]) == CYRET_STARTED) + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) { /* Plan for failure */ status = CYRET_UNKNOWN; @@ -264,7 +401,7 @@ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) } } - /* Unlock the SPC so someone else can use it. */ + /* Unlock SPC so that someone else can use it. */ CySpcUnlock(); } else @@ -286,31 +423,44 @@ cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ******************************************************************************** * * Summary: -* Starts the SPC write function. This function does not block, it returns -* once the command has begun the SPC write function. This function must be used -* in combination with CFG_EEPROM_QueryWrite(). Once this function has -* been called the SPC will be locked until CFG_EEPROM_QueryWrite() -* returns CYRET_SUCCESS. +* Starts a write of a row (16 bytes) of data to the EEPROM. +* This function does not block. The function returns once the SPC has begun +* writing the data. This function must be used in combination with +* CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called +* until it returns a status other than CYRET_STARTED. That indicates that the +* write has completed. Until CFG_EEPROM_Query() detects that +* the write is complete, the SPC is marked as locked to prevent another +* SPC operation from being performed. For a reliable write procedure to occur +* you should call CFG_EEPROM_UpdateTemperature() API if the temperature +* of the silicon has changed for more than 10C since component was started. * * Parameters: -* rowData: Address of buffer containing a row of data to write to the EEPROM. -* rowNumber: EEPROM row number to program. +* rowData: The address of the data to write to the EEPROM. +* rowNumber: The row number to write. * * Return: -* CYRET_STARTED, if the spc command to write was successfuly started. -* CYRET_BAD_PARAM, if the parameter rowNumber out of range. -* CYRET_LOCKED, if the spc is being used. +* CYRET_STARTED, if the SPC command to write was successfully started. +* CYRET_BAD_PARAM, if the parameter rowNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. * CYRET_UNKNOWN, if there was an SPC error. * +* Side effects: +* After calling this API, the device should not be powered down, reset or switched +* to low power modes until EEPROM operation is complete. +* Ignoring this recommendation may lead to data corruption or silicon +* unexpected behavior. +* *******************************************************************************/ cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ { cystatus status; + + CySpcStart(); if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) { - /* See if we can get the SPC. */ + /* See if we can get SPC. */ if(CySpcLock() == CYRET_SUCCESS) { /* Plan for failure */ @@ -333,8 +483,8 @@ cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ /* Command to erase and program the row. */ if(status == CYRET_SUCCESS) { - if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0], - dieTemperature[1]) == CYRET_STARTED) + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) { status = CYRET_STARTED; } @@ -364,25 +514,94 @@ cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ /******************************************************************************* -* Function Name: CFG_EEPROM_QueryWrite +* Function Name: CFG_EEPROM_StartErase ******************************************************************************** * * Summary: -* Checks the state of write to EEPROM. This function must be called until -* the return value is not CYRET_STARTED. +* Starts the EEPROM sector erase. This function does not block. +* The function returns once the SPC has begun writing the data. This function +* must be used in combination with CFG_EEPROM_Query(). +* CFG_EEPROM_Query() must be called until it returns a status +* other than CYRET_STARTED. That indicates the erase has been completed. +* Until CFG_EEPROM_Query() detects that the erase is +* complete, the SPC is marked as locked to prevent another SPC operation +* from being performed. +* +* Parameters: +* sectorNumber: The sector number to erase. +* +* Return: +* CYRET_STARTED, if the SPC command to erase was successfully started. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +* Side effects: +* After calling this API, the device should not be powered down, reset or switched +* to low power modes until EEPROM operation is complete. +* Ignoring this recommendation may lead to data corruption or silicon +* unexpected behavior. +* +*******************************************************************************/ +cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) +{ + cystatus status; + + CySpcStart(); + + if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Query +******************************************************************************** +* +* Summary: +* Checks the status of an earlier call to CFG_EEPROM_StartWrite() or +* CFG_EEPROM_StartErase(). +* This function must be called until it returns a value other than +* CYRET_STARTED. Once that occurs, the write or erase has been completed and +* the SPC is unlocked. * * Parameters: * None * * Return: -* CYRET_STARTED, if the spc command is still processing. -* CYRET_SUCCESS, if the operation was successful. +* CYRET_STARTED, if the SPC command is still processing. +* CYRET_SUCCESS, if the operation was completed successfully. * CYRET_UNKNOWN, if there was an SPC error. * *******************************************************************************/ -cystatus CFG_EEPROM_QueryWrite(void) +cystatus CFG_EEPROM_Query(void) { cystatus status; + + CySpcStart(); /* Check if SPC is idle */ if(CY_SPC_IDLE) @@ -397,7 +616,7 @@ cystatus CFG_EEPROM_QueryWrite(void) status = CYRET_UNKNOWN; } - /* Unlock the SPC so someone else can use it. */ + /* Unlock SPC so that someone else can use it. */ CySpcUnlock(); } else @@ -410,42 +629,42 @@ cystatus CFG_EEPROM_QueryWrite(void) /******************************************************************************* -* Function Name: CFG_EEPROM_ByteWrite +* Function Name: CFG_EEPROM_ByteWritePos ******************************************************************************** * * Summary: * Writes a byte of data to the EEPROM. This is a blocking call. It will not -* return until the function succeeds or fails. +* return until the write operation succeeds or fails. * * Parameters: -* dataByte: Byte of data to write to the EEPROM. -* rowNumber: EEPROM row number to program. -* byteNumber: Byte number within the row to program. +* dataByte: The byte of data to write to the EEPROM. +* rowNumber: The EEPROM row number to program. +* byteNumber: The byte number within the row to program. * * Return: * CYRET_SUCCESS, if the operation was successful. -* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range. -* CYRET_LOCKED, if the spc is being used. +* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. * CYRET_UNKNOWN, if there was an SPC error. * *******************************************************************************/ -cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ +cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ { cystatus status; - /* Start the SPC */ + /* Start SPC */ CySpcStart(); if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW)) { - /* See if we can get the SPC. */ + /* See if we can get SPC. */ if(CySpcLock() == CYRET_SUCCESS) { /* Plan for failure */ status = CYRET_UNKNOWN; - /* Command to load a byte of data */ + /* Command to load byte of data */ if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\ CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED) { @@ -463,8 +682,8 @@ cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) /* Command to erase and program the row. */ if(status == CYRET_SUCCESS) { - if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0], - dieTemperature[1]) == CYRET_STARTED) + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) { /* Plan for failure */ status = CYRET_UNKNOWN; @@ -491,7 +710,7 @@ cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) } } - /* Unlock the SPC so someone else can use it. */ + /* Unlock SPC so that someone else can use it. */ CySpcUnlock(); } else diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h index e6a5f0f..ad62aa2 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: CFG_EEPROM.h -* Version 2.10 +* Version 3.0 * -* Description: -* Provides the function definitions for the EEPROM APIs. +* Description: +* Provides the function definitions for the EEPROM APIs. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ @@ -19,7 +19,7 @@ #include "CyFlash.h" #if !defined(CY_PSOC5LP) - #error Component EEPROM_v2_10 requires cy_boot v3.0 or later + #error Component EEPROM_v3_0 requires cy_boot v3.0 or later #endif /* (CY_PSOC5LP) */ @@ -27,33 +27,52 @@ * Function Prototypes ***************************************/ -#if (CY_PSOC3 || CY_PSOC5LP) - void CFG_EEPROM_Enable(void) ; - void CFG_EEPROM_Start(void); - void CFG_EEPROM_Stop(void) ; -#endif /* (CY_PSOC3 || CY_PSOC5LP) */ - +void CFG_EEPROM_Enable(void) ; +void CFG_EEPROM_Start(void) ; +void CFG_EEPROM_Stop (void) ; +cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \ + ; +uint8 CFG_EEPROM_ReadByte(uint16 address) ; +uint8 CFG_EEPROM_UpdateTemperature(void) ; cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ; cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ; cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ - ; -cystatus CFG_EEPROM_QueryWrite(void) ; -cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ - ; + ; +cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ; +cystatus CFG_EEPROM_Query(void) ; +cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + ; /**************************************** * API Constants ****************************************/ -#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE +#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE #define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u) +#define CFG_EEPROM_SECTORS_NUMBER (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE) -/******************************************************************************* -* Following code are OBSOLETE and must not be used starting from EEPROM 2.10 -*******************************************************************************/ -#define SPC_BYTE_WRITE_SIZE (CFG_EEPROM_SPC_BYTE_WRITE_SIZE) +#define CFG_EEPROM_AHB_REQ_SHIFT (0x00u) +#define CFG_EEPROM_AHB_REQ ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT)) +#define CFG_EEPROM_AHB_ACK_SHIFT (0x01u) +#define CFG_EEPROM_AHB_ACK_MASK ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT)) + + +/*************************************** +* Registers +***************************************/ +#define CFG_EEPROM_SPC_EE_SCR_REG (*(reg8 *) CYREG_SPC_EE_SCR) +#define CFG_EEPROM_SPC_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* The following code is DEPRECATED and +* should not be used in new projects. +***************************************/ +#define CFG_EEPROM_ByteWrite CFG_EEPROM_ByteWritePos +#define CFG_EEPROM_QueryWrite CFG_EEPROM_Query #endif /* CY_EEPROM_CFG_EEPROM_H */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf old mode 100644 new mode 100755 index 239de62..c83f309 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf @@ -20,6 +20,7 @@ define symbol CY_APPL_LOADER = 0; define symbol CY_APPL_NUM = 1; define symbol CY_APPL_MAX = 1; define symbol CY_METADATA_SIZE = 64; +define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0; define symbol CY_EE_IN_BTLDR = 0x00; define symbol CY_EE_SIZE = 2048; include "cybootloader.icf"; @@ -28,7 +29,7 @@ if (!CY_APPL_LOADABLE) { } define symbol CY_FLASH_SIZE = 131072; -define symbol CY_APPL_ORIGIN = 0; +define symbol CY_APPL_ORIGIN = 0; define symbol CY_FLASH_ROW_SIZE = 256; define symbol CY_ECC_ROW_SIZE = 32; @@ -46,7 +47,7 @@ define block LOADER { readonly section .cybootloader }; } define block APPL with fixed order {readonly section .romvectors, readonly}; -/* The address of Flash row next after Bootloader image */ +/* The address of the Flash row next after the Bootloader image */ define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); @@ -97,21 +98,57 @@ if (CY_APPL_LOADABLE) "readwrite" : place in RAM_region { readwrite }; "HSTACK" : place at end of RAM_region { block HSTACK}; -keep { section .cybootloader, - section .cyloadermeta, +keep { section .cybootloader, + section .cyloadermeta, section .cyloadablemeta, - section .cyconfigecc, - section .cycustnvl, + section .cyconfigecc, + section .cy_checksum_exclude, + section .cycustnvl, section .cywolatch, - section .cyeeprom, + section .cyeeprom, section .cyflashprotect, section .cymeta }; -".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; +".cyloadermeta" : place at address mem : ((CY_APPL_LOADER && !CY_APPL_LOADABLE) ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; if (CY_APPL_LOADABLE) { -".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; +".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; } + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* Align size to the flash row size */ + define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0); + + if (CY_CHECKSUM_EXCLUDE_SIZE != 0) + { + + /* General case */ + if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + else + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + + } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */ +} +else +{ + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; +} + + ".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc }; ".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl }; ".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat old mode 100644 new mode 100755 index 0c25bb2..2f84d01 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -1,31 +1,24 @@ #! armcc -E -; The first line specifies a preprocessor command that the linker invokes +; The first line specifies a preprocessor command that the linker invokes ; to pass a scatter file through a C preprocessor. ;******************************************************************************** -;* File Name: Cm3RealView.scat -;* Version 4.20 +;* \file Cm3RealView.scat +;* \version 5.50 ;* -;* Description: -;* This Linker Descriptor file describes the memory layout of the PSoC5 -;* device. The memory layout of the final binary and hex images as well as -;* the placement in PSoC5 memory is described. -;* -;* -;* Note: +;* \brief +;* This Linker Descriptor file describes the memory layout of the PSoC5 +;* device. The memory layout of the final binary and hex images as well as +;* the placement in PSoC5 memory is described. ;* ;* romvectors: Cypress default Interrupt service routine vector table. -;* ;* This is the ISR vector table at bootup. Used only for the reset vector. ;* -;* ;* ramvectors: Cypress ram interrupt service routine vector table. -;* ;* This is the ISR vector table used by the application. ;* -;* ;******************************************************************************** -;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +;* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. ;* You may use this file only in accordance with the license, terms, conditions, ;* disclaimers, and limitations in the end user license agreement accompanying ;* the software package with which this file was provided. @@ -39,12 +32,16 @@ #define CY_EE_SIZE 2048 #define CY_METADATA_SIZE 64 +#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE) +#define CY_APPL_NUM 1 +#define CY_APPL_MAX 1 + ; Define application base address -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) - #define CY_APPL_NUM 1 - #define CY_APPL_MAX 1 - #define CY_EE_IN_BTLDR 0 +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + #define CY_EE_IN_BTLDR 0 #if CY_APPL_ORIGIN #define APPL1_START CY_APPL_ORIGIN @@ -68,7 +65,8 @@ ; Place Bootloader at the beginning of Flash -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) CYBOOTLOADER 0 { @@ -79,7 +77,7 @@ } #if CY_APPL_ORIGIN - ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER)) + ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER)) #endif #endif @@ -122,26 +120,62 @@ APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) } -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER) +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER) CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) { .cyloadermeta +0 { * (.cyloadermeta) } } -#else +#endif - #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) - CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) - { - .cyloadablemeta +0 { * (.cyloadablemeta) } - } - - #endif +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } #endif + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + + #if (0 != 0) + + #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #else + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + + CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START) + { + .cy_checksum_exclude +0 + { + * (.cy_checksum_exclude) + } + } + + #endif /* (0 != 0) */ + +#endif + + #if (CYDEV_ECC_ENABLE == 0) CYCONFIGECC (0x80000000 + ECC_OFFSET) @@ -180,7 +214,11 @@ CYMETA 0x90500000 .cymeta +0 { * (.cymeta) } } -#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + +/******************************************************************************* +* Bootloader Metadata Section. Must be part of the image, but beyond rom memory. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) CYLOADERMETA +0 { diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c old mode 100644 new mode 100755 index dd1cc0b..d91b39a --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -1,12 +1,13 @@ -/******************************************************************************* -* File Name: Cm3Start.c -* Version 4.20 +/***************************************************************************//** +* \file Cm3Start.c +* \version 5.50 * -* Description: +* \brief * Startup code for the ARM CM3. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -20,6 +21,7 @@ #include "CyDmac.h" #include "cyfitter.h" + #define CY_NUM_INTERRUPTS (32u) #define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) #define CY_NUM_ROM_VECTORS (4u) @@ -29,16 +31,6 @@ #define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ #define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ - -/* Extern functions */ -extern void CyBtldr_CheckLaunch(void); - -/* Function prototypes */ -void initialize_psoc(void); -CY_ISR(IntDefaultHandler); -void Reset(void); -CY_ISR(IntDefaultHandler); - #if defined(__ARMCC_VERSION) #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) #elif defined (__GNUC__) @@ -58,6 +50,14 @@ CY_ISR(IntDefaultHandler); extern int end; #endif /* defined(__GNUC__) */ +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); +CY_ISR(IntDefaultHandler); +void Reset(void); + /* Global variables */ #if !defined (__ICCARM__) CY_NOINIT static uint32 cySysNoInitDataValid; @@ -79,32 +79,48 @@ cyisraddress CyRamVectors[CY_NUM_VECTORS]; /******************************************************************************* * Function Name: IntDefaultHandler -******************************************************************************** +****************************************************************************//** * -* Summary: * This function is called for all interrupts, other than a reset that gets * called before the system is setup. * -* Parameters: -* None -* -* Return: -* None -* * Theory: * Any value other than zero is acceptable. * *******************************************************************************/ CY_ISR(IntDefaultHandler) { + /*************************************************************************** + * We must not get here. If we do, a serious problem occurs, so go into + * an infinite loop. + ***************************************************************************/ - while(1) - { - /*********************************************************************** - * We must not get here. If we do, a serious problem occurs, so go - * into an infinite loop. - ***********************************************************************/ - } + #if defined(__GNUC__) + if (errno == ENOMEM) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + + while(1) + { + /* Out Of Heap Space + * This can be increased in the System tab of the Design Wide Resources. + */ + } + } + else + #endif + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + + } + } } @@ -125,22 +141,15 @@ extern int __main(void); /******************************************************************************* * Function Name: Reset -******************************************************************************** +****************************************************************************//** * -* Summary: * This function handles the reset interrupt for the RVDS/MDK toolchains. * This is the first bit of code that is executed at startup. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void Reset(void) { - #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) /* For PSoC 5LP, debugging is enabled by default */ #if(CYDEV_DEBUGGING_ENABLE == 0) @@ -152,11 +161,11 @@ void Reset(void) */ *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ - #if(CYDEV_BOOTLOADER_ENABLE) + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) CyBtldr_CheckLaunch(); - #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ __main(); } @@ -164,17 +173,10 @@ void Reset(void) /******************************************************************************* * Function Name: $Sub$$main -******************************************************************************** +****************************************************************************//** * -* Summary: * This function is called immediately before the users main * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void $Sub$$main(void) { @@ -224,27 +226,19 @@ extern const char __cy_region_num __attribute__((weak)); /******************************************************************************* * Function Name: _exit -******************************************************************************** +****************************************************************************//** * -* Summary: * Exit a program without cleaning up files. If your system doesn't provide * this, it is best to avoid linking with subroutines that require it (exit, * system). * -* Parameters: -* status: Status caused program exit. -* -* Return: -* None +* \param status: Status caused program exit. * *******************************************************************************/ __attribute__((weak)) void _exit(int status) { - /* Cause divide by 0 exception */ - int x = status / (int) INT_MAX; - x = 4 / x; - + CyHalt((uint8) status); while(1) { @@ -254,22 +248,17 @@ void _exit(int status) /******************************************************************************* * Function Name: _sbrk -******************************************************************************** +****************************************************************************//** * -* Summary: * Increase program data space. As malloc and related functions depend on this, * it is useful to have a working implementation. The following suffices for a * standalone system; it exploits the symbol end automatically defined by the * GNU linker. * -* Parameters: -* nbytes: The number of bytes requested (if the parameter value is positive) +* \param nbytes: The number of bytes requested (if the parameter value is positive) * from the heap or returned back to the heap (if the parameter value is * negative). * -* Return: -* None -* *******************************************************************************/ __attribute__((weak)) void * _sbrk (int nbytes) @@ -297,22 +286,15 @@ void * _sbrk (int nbytes) /******************************************************************************* * Function Name: Reset -******************************************************************************** +****************************************************************************//** * -* Summary: * This function handles the reset interrupt for the GCC toolchain. This is the * first bit of code that is executed at startup. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void Reset(void) { - #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) /* For PSoC 5LP, debugging is enabled by default */ #if(CYDEV_DEBUGGING_ENABLE == 0) @@ -324,11 +306,11 @@ void Reset(void) */ *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ - #if(CYDEV_BOOTLOADER_ENABLE) + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) CyBtldr_CheckLaunch(); - #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ Start_c(); } @@ -336,19 +318,12 @@ void Reset(void) /******************************************************************************* * Function Name: Start_c -******************************************************************************** +****************************************************************************//** * -* Summary: * This function handles initializing the .data and .bss sections in * preparation for running the standard C code. Once initialization is complete * it will call main(). This function will never return. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void Start_c(void) __attribute__ ((noreturn)); void Start_c(void) @@ -395,17 +370,13 @@ void Start_c(void) /******************************************************************************* * Function Name: __low_level_init -******************************************************************************** +****************************************************************************//** * -* Summary: * This function performs early initializations for the IAR Embedded * Workbench IDE. It is executed in the context of a reset interrupt handler * before the data sections are initialized. * -* Parameters: -* None -* -* Return: +* \return * The value that determines whether or not data sections should be initialized * by the system startup code: * 0 - skip data sections initialization; @@ -414,7 +385,7 @@ void Start_c(void) *******************************************************************************/ int __low_level_init(void) { - #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) /* For PSoC 5LP, debugging is enabled by default */ #if(CYDEV_DEBUGGING_ENABLE == 0) @@ -426,11 +397,11 @@ int __low_level_init(void) */ *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); - #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ - #if (CYDEV_BOOTLOADER_ENABLE) + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) CyBtldr_CheckLaunch(); - #endif /* CYDEV_BOOTLOADER_ENABLE */ + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ /* Initialize data sections */ __iar_data_init3(); @@ -478,17 +449,10 @@ int __low_level_init(void) /******************************************************************************* * Function Name: initialize_psoc -******************************************************************************** +****************************************************************************//** * -* Summary: * This function used to initialize the PSoC chip before calling main. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ #if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) __attribute__ ((constructor(101))) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s old mode 100644 new mode 100755 index e8c87a4..4f5f85c --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -1,12 +1,13 @@ -/******************************************************************************* -* File Name: CyBootAsmGnu.s -* Version 4.20 +/***************************************************************************//** +* \file CyBootAsmGnu.s +* \version 5.50 * -* Description: +* \brief * Assembly routines for GNU as. * ******************************************************************************** -* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,16 +22,11 @@ /******************************************************************************* * Function Name: CyDelayCycles -******************************************************************************** +****************************************************************************//** * -* Summary: * Delays for the specified number of cycles. * -* Parameters: -* uint32 cycles: number of cycles to delay. -* -* Return: -* None +* \param uint32 cycles: number of cycles to delay. * *******************************************************************************/ /* void CyDelayCycles(uint32 cycles) */ @@ -107,9 +103,8 @@ cy_flash_cycles: /******************************************************************************* * Function Name: CyEnterCriticalSection -******************************************************************************** +****************************************************************************//** * -* Summary: * CyEnterCriticalSection disables interrupts and returns a value indicating * whether interrupts were previously enabled (the actual value depends on * whether the device is PSoC 3 or PSoC 5). @@ -120,10 +115,7 @@ cy_flash_cycles: * corrupting processor state, it must be the policy that all interrupt routines * restore the interrupt enable bits as they were found on entry. * -* Parameters: -* None -* -* Return: +* \return * uint8 * Returns 0 if interrupts were previously enabled or 1 if interrupts * were previously disabled. @@ -143,20 +135,15 @@ CyEnterCriticalSection: /******************************************************************************* * Function Name: CyExitCriticalSection -******************************************************************************** +****************************************************************************//** * -* Summary: * CyExitCriticalSection re-enables interrupts if they were enabled before * CyEnterCriticalSection was called. The argument should be the value returned * from CyEnterCriticalSection. * -* Parameters: -* uint8 savedIntrStatus: +* \param uint8 savedIntrStatus: * Saved interrupt status returned by the CyEnterCriticalSection function. * -* Return: -* None -* *******************************************************************************/ /* void CyExitCriticalSection(uint8 savedIntrStatus) */ .global CyExitCriticalSection diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s old mode 100644 new mode 100755 index 330202c..3058655 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -1,12 +1,12 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmIar.s -; Version 4.20 +; Version 5.50 ; ; DESCRIPTION: ; Assembly routines for IAR Embedded Workbench IDE. ; ;------------------------------------------------------------------------------- -; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s old mode 100644 new mode 100755 index 8b1cc20..e02cb0f --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -1,12 +1,12 @@ ;------------------------------------------------------------------------------- ; FILENAME: CyBootAsmRv.s -; Version 4.20 +; Version 5.50 ; ; DESCRIPTION: ; Assembly routines for RealView. ; ;------------------------------------------------------------------------------- -; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c old mode 100644 new mode 100755 index 2a1ef96..9e66257 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -1,27 +1,26 @@ -/******************************************************************************* -* File Name: CyDmac.c -* Version 4.20 +/***************************************************************************//** +* \file CyDmac.c +* \version 5.50 * -* Description: -* Provides an API for the DMAC component. The API includes functions for the -* DMA controller, DMA channels and Transfer Descriptors. +* \brief +* Provides an API for the DMAC component. The API includes functions for the +* DMA controller, DMA channels and Transfer Descriptors. This API is the library +* version not the auto generated code that gets generated when the user places a +* DMA component on the schematic. * -* This API is the library version not the auto generated code that gets -* generated when the user places a DMA component on the schematic. +* The auto generated code would use the APi's in this module. * -* The auto generated code would use the APi's in this module. +* \note This code is endian agnostic. * -* Note: -* This code is endian agnostic. +* \note The Transfer Descriptor memory can be used as regular memory if the +* TD's are not being used. * -* The Transfer Descriptor memory can be used as regular memory if the TD's are -* not being used. -* -* This code uses the first byte of each TD to manage the free list of TD's. -* The user can overwrite this once the TD is allocated. +* \note This code uses the first byte of each TD to manage the free list of +* TD's. The user can overwrite this once the TD is allocated. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -44,18 +43,11 @@ static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map /******************************************************************************* * Function Name: CyDmacConfigure -******************************************************************************** +****************************************************************************//** * -* Summary: -* Creates a linked list of all the TDs to be allocated. This function is called -* by the startup code; you do not normally need to call it. You can call this -* function if all of the DMA channels are inactive. -* -* Parameters: -* None -* -* Return: -* None +* Creates a linked list of all the TDs to be allocated. This function is called +* by the startup code; you do not normally need to call it. You can call this +* function if all of the DMA channels are inactive. * *******************************************************************************/ void CyDmacConfigure(void) @@ -79,16 +71,11 @@ void CyDmacConfigure(void) /******************************************************************************* * Function Name: CyDmacError -******************************************************************************** +****************************************************************************//** * -* Summary: * Returns errors of the last failed DMA transaction. * -* Parameters: -* None -* -* Return: -* Errors of the last failed DMA transaction. +* \return Errors of the last failed DMA transaction. * * DMAC_PERIPH_ERR: * Set to 1 when a peripheral responds to a bus transaction with an error @@ -102,43 +89,38 @@ void CyDmacConfigure(void) * are determined by the BUS_TIMEOUT field in the PHUBCFG register. * * Theory: -* Once an error occurs the error bits are sticky and are only cleared by +* Once an error occurs the error bits are sticky and are only cleared by * writing 1 to the error register. * *******************************************************************************/ uint8 CyDmacError(void) { - return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR)); + return((uint8)(((uint32) 0x0Eu) & *CY_DMA_ERR_PTR)); } /******************************************************************************* * Function Name: CyDmacClearError -******************************************************************************** +****************************************************************************//** * -* Summary: * Clears the error bits in the error register of the DMAC. * -* Parameters: -* error: +* \param error: * Clears the error bits in the DMAC error register. * -* DMAC_PERIPH_ERR: +* \param DMAC_PERIPH_ERR: * Set to 1 when a peripheral responds to a bus transaction with an error * response. * -* DMAC_UNPOP_ACC: +* \param DMAC_UNPOP_ACC: * Set to 1 when an access is attempted to an invalid address. * -* DMAC_BUS_TIMEOUT: +* \param DMAC_BUS_TIMEOUT: * Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values * are determined by the BUS_TIMEOUT field in the PHUBCFG register. * -* Return: -* None -* * Theory: -* Once an error occurs the error bits are sticky and are only cleared by +* Once an error occurs the error bits are sticky and are only cleared by * writing 1 to the error register. * *******************************************************************************/ @@ -150,20 +132,15 @@ void CyDmacClearError(uint8 error) /******************************************************************************* * Function Name: CyDmacErrorAddress -******************************************************************************** +****************************************************************************//** * -* Summary: * When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the * address of the error is written to the error address register and can be read * with this function. * * If there are multiple errors, only the address of the first is saved. * -* Parameters: -* None -* -* Return: -* The address that caused the error. +* \return The address that caused the error. * *******************************************************************************/ uint32 CyDmacErrorAddress(void) @@ -174,17 +151,12 @@ uint32 CyDmacErrorAddress(void) /******************************************************************************* * Function Name: CyDmaChAlloc -******************************************************************************** +****************************************************************************//** * -* Summary: * Allocates a channel from the DMAC to be used in all functions that require a * channel handle. * -* Parameters: -* None -* -* Return: -* The allocated channel number. Zero is a valid channel number. +* \return The allocated channel number. Zero is a valid channel number. * DMA_INVALID_CHANNEL is returned if there are no channels available. * *******************************************************************************/ @@ -225,18 +197,15 @@ uint8 CyDmaChAlloc(void) /******************************************************************************* * Function Name: CyDmaChFree -******************************************************************************** +****************************************************************************//** * -* Summary: -* Frees a channel allocated by DmaChAlloc(). +* Frees a channel allocated by \ref DmaChAlloc(). * -* Parameters: -* uint8 chHandle: -* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle The handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChFree(uint8 chHandle) @@ -263,19 +232,16 @@ cystatus CyDmaChFree(uint8 chHandle) /******************************************************************************* * Function Name: CyDmaChEnable -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the DMA channel. A software or hardware request still must happen * before the channel is executed. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* uint8 preserveTds: -* Preserves the original TD state when the TD has completed. This parameter -* applies to all TDs in the channel. +* \param preserveTds Preserves the original TD state when the TD has completed. +* This parameter applies to all TDs in the channel. * * 0 - When TD is completed, the DMAC leaves the TD configuration values in * their current state, and does not restore them to their original state. @@ -288,7 +254,7 @@ cystatus CyDmaChFree(uint8 chHandle) * if you are using CH06 and preserveTds is set, you are not allowed to use TD * slot 6. That is reclaimed by the DMA engine for its private use. * -* Note Do not chain back to a completed TD if the preserveTds for the channel +* \note Do not chain back to a completed TD if the preserveTds for the channel * is set to 0. When a TD has completed preserveTds for the channel set to 0, * the transfer count will be at 0. If a TD with a transfer count of 0 is * started, the TD will transfer an indefinite amount of data. @@ -296,9 +262,8 @@ cystatus CyDmaChFree(uint8 chHandle) * Take extra precautions when using the hardware request (DRQ) option when the * preserveTds is set to 0, as you might be requesting the wrong data. * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) @@ -332,23 +297,20 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) /******************************************************************************* * Function Name: CyDmaChDisable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Disables the DMA channel. Once this function is called, CyDmaChStatus() may -* be called to determine when the channel is disabled and which TDs were being -* executed. +* Disables the DMA channel. Once this function is called, CyDmaChStatus() may +* be called to determine when the channel is disabled and which TDs were being +* executed. * -* If it is currently executing it will allow the current burst to finish -* naturally. +* If it is currently executing it will allow the current burst to finish +* naturally. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChDisable(uint8 chHandle) @@ -376,18 +338,14 @@ cystatus CyDmaChDisable(uint8 chHandle) /******************************************************************************* * Function Name: CyDmaClearPendingDrq -******************************************************************************** +****************************************************************************//** * -* Summary: -* Clears pending the DMA data request. +* Clears pending the DMA data request. * -* Parameters: -* uint8 chHandle: -* Handle to the dma channel. +* \param chHandle Handle to the dma channel. * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaClearPendingDrq(uint8 chHandle) @@ -407,23 +365,19 @@ cystatus CyDmaClearPendingDrq(uint8 chHandle) /******************************************************************************* * Function Name: CyDmaChPriority -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the priority of a DMA channel. You can use this function when you want * to change the priority at run time. If the priority remains the same for a * DMA channel, then you can configure the priority in the .cydwr file. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* uint8 priority: -* Priority to set the channel to, 0 - 7. +* \param priority Priority to set the channel to, 0 - 7. * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) @@ -446,25 +400,20 @@ cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) /******************************************************************************* * Function Name: CyDmaChSetExtendedAddress -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the high 16 bits of the source and destination addresses for the DMA * channel (valid for all TDs in the chain). * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* uint16 source: -* Upper 16 bit address of the DMA transfer source. +* \param source Upper 16 bit address of the DMA transfer source. * -* uint16 destination: -* Upper 16 bit address of the DMA transfer destination. +* \param destination Upper 16 bit address of the DMA transfer destination. * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ @@ -507,23 +456,19 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina /******************************************************************************* * Function Name: CyDmaChSetInitialTd -******************************************************************************** +****************************************************************************//** * -* Summary: -* Sets the initial TD to be executed for the channel when the CyDmaChEnable() -* function is called. +* Sets the initial TD to be executed for the channel when the \ref CyDmaChEnable() +* function is called. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or +* \ref DMA_DmaInitialize(). * -* uint8 startTd: -* Set the TD index as the first TD associated with the channel. Zero is -* a valid TD index. +* \param startTd Set the TD index as the first TD associated with the +* channel. Zero is a valid TD index. * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) @@ -542,26 +487,22 @@ cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) /******************************************************************************* * Function Name: CyDmaChSetRequest -******************************************************************************** +****************************************************************************//** * -* Summary: * Allows the caller to terminate a chain of TDs, terminate one TD, or create a * direct request to start the DMA channel. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). -* -* uint8 request: -* One of the following constants. Each of the constants is a three-bit value. +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * +* \param request One of the following constants. Each of the constants is a +* three-bit value. * CPU_REQ - Create a direct request to start the DMA channel * CPU_TERM_TD - Terminate one TD * CPU_TERM_CHAIN - Terminate a chain of TDs * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) @@ -580,21 +521,18 @@ cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) /******************************************************************************* * Function Name: CyDmaChGetRequest -******************************************************************************** +****************************************************************************//** * -* Summary: -* This function allows the caller of CyDmaChSetRequest() to determine if the -* request was completed. +* This function allows the caller of \ref CyDmaChSetRequest() to determine if the +* request was completed. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* Return: -* Returns a three-bit field, corresponding to the three bits of the request, -* which describes the state of the previously posted request. If the value is -* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is -* invalid. +* \return Returns a three-bit field, corresponding to the three bits of the +* request, which describes the state of the previously posted request. If the +* value is zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle +* is invalid. * *******************************************************************************/ cystatus CyDmaChGetRequest(uint8 chHandle) @@ -613,35 +551,30 @@ cystatus CyDmaChGetRequest(uint8 chHandle) /******************************************************************************* * Function Name: CyDmaChStatus -******************************************************************************** +****************************************************************************//** * -* Summary: * Determines the status of the DMA channel. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). * -* uint8 * currentTd: -* The address to store the index of the current TD. Can be NULL if the value -* is not needed. +* \param currentTd The address to store the index of the current TD. Can be NULL +* if the value is not needed. * -* uint8 * state: -* The address to store the state of the channel. Can be NULL if the value is -* not needed. +* \param state The address to store the state of the channel. Can be NULL if the +* value is not needed. * * STATUS_TD_ACTIVE -* 0: Channel is not currently being serviced by DMAC -* 1: Channel is currently being serviced by DMAC +* \param 0: Channel is not currently being serviced by DMAC +* \param 1: Channel is currently being serviced by DMAC * * STATUS_CHAIN_ACTIVE -* 0: TD chain is inactive; either no DMA requests have triggered a new chain +* \param 0: TD chain is inactive; either no DMA requests have triggered a new chain * or the previous chain has completed. -* 1: TD chain has been triggered by a DMA request +* \param 1: TD chain has been triggered by a DMA request * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. * * Theory: * The caller can check on the activity of the Current TD and the Chain. @@ -672,43 +605,41 @@ cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) /******************************************************************************* * Function Name: CyDmaChSetConfiguration -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets configuration information of the channel. * -* Parameters: -* uint8 chHandle: +* \param uint8 chHandle: * A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). * -* uint8 burstCount: +* \param uint8 burstCount: * Specifies the size of bursts (1 to 127) the data transfer should be divided * into. If this value is zero then the whole transfer is done in one burst. * -* uint8 requestPerBurst: +* \param uint8 requestPerBurst: * The whole of the data can be split into multiple bursts, if this is -* required to complete the transaction: -* 0: All subsequent bursts after the first burst will be automatically +* \param required to complete the transaction: +* \param 0: All subsequent bursts after the first burst will be automatically * requested and carried out -* 1: All subsequent bursts after the first burst must also be individually +* \param 1: All subsequent bursts after the first burst must also be individually * requested. * -* uint8 tdDone0: +* \param uint8 tdDone0: * Selects one of the TERMOUT0 interrupt lines to signal completion. The line * connected to the nrq terminal will determine the TERMOUT0_SEL definition and * should be used as supplied by cyfitter.h * -* uint8 tdDone1: +* \param uint8 tdDone1: * Selects one of the TERMOUT1 interrupt lines to signal completion. The line * connected to the nrq terminal will determine the TERMOUT1_SEL definition and * should be used as supplied by cyfitter.h * -* uint8 tdStop: +* \param uint8 tdStop: * Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD * should terminate. The signal connected to the trq terminal will determine * which TERMIN (termination request) is used. * -* Return: +* \return * CYRET_SUCCESS if successful. * CYRET_BAD_PARAM if chHandle is invalid. * @@ -734,15 +665,11 @@ cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 request /******************************************************************************* * Function Name: CyDmaTdAllocate -******************************************************************************** +****************************************************************************//** * -* Summary: * Allocates a TD for use with an allocated DMA channel. * -* Parameters: -* None -* -* Return: +* \return * Zero-based index of the TD to be used by the caller. Since there are 128 TDs * minus the reserved TDs (0 to 23), the value returned would range from 24 to * 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs @@ -778,18 +705,13 @@ uint8 CyDmaTdAllocate(void) /******************************************************************************* * Function Name: CyDmaTdFree -******************************************************************************** +****************************************************************************//** * -* Summary: * Returns a TD to the free list. * -* Parameters: -* uint8 tdHandle: +* \param uint8 tdHandle: * The TD handle returned by the CyDmaTdAllocate(). * -* Return: -* None -* *******************************************************************************/ void CyDmaTdFree(uint8 tdHandle) { @@ -815,15 +737,11 @@ void CyDmaTdFree(uint8 tdHandle) /******************************************************************************* * Function Name: CyDmaTdFreeCount -******************************************************************************** +****************************************************************************//** * -* Summary: * Returns the number of free TDs available to be allocated. * -* Parameters: -* None -* -* Return: +* \return * The number of free TDs. * *******************************************************************************/ @@ -835,28 +753,26 @@ uint8 CyDmaTdFreeCount(void) /******************************************************************************* * Function Name: CyDmaTdSetConfiguration -******************************************************************************** +****************************************************************************//** * -* Summary: * Configures the TD. * -* Parameters: -* uint8 tdHandle: +* \param uint8 tdHandle: * A handle previously returned by CyDmaTdAlloc(). * -* uint16 transferCount: +* \param uint16 transferCount: * The size of the data transfer (in bytes) for this TD. A size of zero will * cause the transfer to continue indefinitely. This parameter is limited to * 4095 bytes; the TD is not initialized at all when a higher value is passed. * -* uint8 nextTd: +* \param uint8 nextTd: * Zero based index of the next Transfer Descriptor in the TD chain. Zero is a * valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. * DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No * further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and * PSoC 5LP silicons. * -* uint8 configuration: +* \param uint8 configuration: * Stores the Bit field of configuration bits. * * CY_DMA_TD_SWAP_EN - Perform endian swap @@ -883,7 +799,7 @@ uint8 CyDmaTdFreeCount(void) * CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each * data transaction in the burst. * -* Return: +* \return * CYRET_SUCCESS if successful. * CYRET_BAD_PARAM if tdHandle or transferCount is invalid. * @@ -914,34 +830,32 @@ cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nex /******************************************************************************* * Function Name: CyDmaTdGetConfiguration -******************************************************************************** +****************************************************************************//** * -* Summary: * Retrieves the configuration of the TD. If a NULL pointer is passed as a * parameter, that parameter is skipped. You may request only the values you are * interested in. * -* Parameters: -* uint8 tdHandle: +* \param uint8 tdHandle: * A handle previously returned by CyDmaTdAlloc(). * -* uint16 * transferCount: +* \param uint16 * transferCount: * The address to store the size of the data transfer (in bytes) for this TD. * A size of zero could indicate that the TD has completed its transfer, or * that the TD is doing an indefinite transfer. * -* uint8 * nextTd: +* \param uint8 * nextTd: * The address to store the index of the next TD in the TD chain. * -* uint8 * configuration: +* \param uint8 * configuration: * The address to store the Bit field of configuration bits. * See CyDmaTdSetConfiguration() function description. * -* Return: +* \return * CYRET_SUCCESS if successful. * CYRET_BAD_PARAM if tdHandle is invalid. * -* Side Effects: +* \sideeffect * If TD has a transfer count of N and is executed, the transfer count becomes * 0. If it is reexecuted, the Transfer count of zero will be interpreted as a * request for indefinite transfer. Be careful when requesting TD with a @@ -986,23 +900,21 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * /******************************************************************************* * Function Name: CyDmaTdSetAddress -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the lower 16 bits of the source and destination addresses for this TD * only. * -* Parameters: -* uint8 tdHandle: +* \param uint8 tdHandle: * A handle previously returned by CyDmaTdAlloc(). * -* uint16 source: +* \param uint16 source: * The lower 16 address bits of the source of the data transfer. * -* uint16 destination: +* \param uint16 destination: * The lower 16 address bits of the destination of the data transfer. * -* Return: +* \return * CYRET_SUCCESS if successful. * CYRET_BAD_PARAM if tdHandle is invalid. * @@ -1031,26 +943,24 @@ cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) /******************************************************************************* * Function Name: CyDmaTdGetAddress -******************************************************************************** +****************************************************************************//** * -* Summary: * Retrieves the lower 16 bits of the source and/or destination addresses for * this TD only. If NULL is passed for a pointer parameter, that value is * skipped. You may request only the values of interest. * -* Parameters: -* uint8 tdHandle: +* \param uint8 tdHandle: * A handle previously returned by CyDmaTdAlloc(). * -* uint16 * source: +* \param uint16 * source: * The address to store the lower 16 address bits of the source of the data * transfer. * -* uint16 * destination: +* \param uint16 * destination: * The address to store the lower 16 address bits of the destination of the * data transfer. * -* Return: +* \return * CYRET_SUCCESS if successful. * CYRET_BAD_PARAM if tdHandle is invalid. * @@ -1087,23 +997,21 @@ cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination /******************************************************************************* * Function Name: CyDmaChRoundRobin -******************************************************************************** +****************************************************************************//** * -* Summary: -* Either enables or disables the Round-Robin scheduling enforcement algorithm. -* Within a priority level a Round-Robin fairness algorithm is enforced. +* Either enables or disables the Round-Robin scheduling enforcement algorithm. +* Within a priority level a Round-Robin fairness algorithm is enforced. * -* Parameters: -* uint8 chHandle: -* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). +* \param uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). * -* uint8 enableRR: -* 0: Disable Round-Robin fairness algorithm -* 1: Enable Round-Robin fairness algorithm +* \param uint8 enableRR: +* \param 0: Disable Round-Robin fairness algorithm +* \param 1: Enable Round-Robin fairness algorithm * -* Return: -* CYRET_SUCCESS if successful. -* CYRET_BAD_PARAM if chHandle is invalid. +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. * *******************************************************************************/ cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h old mode 100644 new mode 100755 index 8bbb4a7..bbfbf16 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -1,16 +1,15 @@ -/******************************************************************************* -* File Name: CyDmac.h -* Version 4.20 +/***************************************************************************//** +* \file CyDmac.h +* \version 5.50 * -* Description: -* Provides the function definitions for the DMA Controller. +* \brief Provides the function definitions for the DMA Controller. * -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c old mode 100644 new mode 100755 index 38ffe99..8969200 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -1,19 +1,17 @@ -/******************************************************************************* -* File Name: CyFlash.c -* Version 4.20 +/***************************************************************************//** +* \file CyFlash.c +* \version 5.50 * -* Description: -* Provides an API for the FLASH/EEPROM. +* \brief Provides an API for the FLASH/EEPROM. * -* Note: -* This code is endian agnostic. +* \note This code is endian agnostic. * -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -43,17 +41,10 @@ static cystatus CyFlashGetSpcAlgorithm(void); /******************************************************************************* * Function Name: CyFlash_Start -******************************************************************************** +****************************************************************************//** * -* Summary: * Enable the Flash. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyFlash_Start(void) { @@ -104,18 +95,11 @@ void CyFlash_Start(void) /******************************************************************************* * Function Name: CyFlash_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * Disable the Flash. * -* Parameters: -* None -* -* Return: -* None -* -* Side Effects: +* \sideeffect * This setting is ignored as long as the CPU is currently running. This will * only take effect when the CPU is later disabled. * @@ -135,17 +119,13 @@ void CyFlash_Stop(void) /******************************************************************************* * Function Name: CySetTempInt -******************************************************************************** +****************************************************************************//** * -* Summary: * Sends a command to the SPC to read the die temperature. Sets a global value * used by the Write function. This function must be called once before * executing a series of Flash writing functions. * -* Parameters: -* None -* -* Return: +* \return * status: * CYRET_SUCCESS - if successful * CYRET_LOCKED - if Flash writing already in use @@ -197,15 +177,11 @@ static cystatus CySetTempInt(void) /******************************************************************************* * Function Name: CyFlashGetSpcAlgorithm -******************************************************************************** +****************************************************************************//** * -* Summary: * Sends a command to the SPC to download code into RAM. * -* Parameters: -* None -* -* Return: +* \return * status: * CYRET_SUCCESS - if successful * CYRET_LOCKED - if Flash writing already in use @@ -249,16 +225,12 @@ static cystatus CyFlashGetSpcAlgorithm(void) /******************************************************************************* * Function Name: CySetTemp -******************************************************************************** +****************************************************************************//** * -* Summary: * This is a wraparound for CySetTempInt(). It is used to return the second * successful read of the temperature value. * -* Parameters: -* None -* -* Return: +* \return * status: * CYRET_SUCCESS if successful. * CYRET_LOCKED if Flash writing already in use @@ -285,19 +257,17 @@ cystatus CySetTemp(void) /******************************************************************************* * Function Name: CySetFlashEEBuffer -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the user supplied temporary buffer to store SPC data while performing -* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is -* disabled. +* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC +* is disabled. * -* Parameters: -* buffer: -* The address of a block of memory to store temporary memory. The size of the block -* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* \param buffer: +* The address of a block of memory to store temporary memory. The size of the +* block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. * -* Return: +* \return * status: * CYRET_SUCCESS if successful. * CYRET_BAD_PARAM if the buffer is NULL @@ -340,22 +310,20 @@ cystatus CySetFlashEEBuffer(uint8 * buffer) /******************************************************************************* * Function Name: CyWriteRowData -******************************************************************************** +****************************************************************************//** * -* Summary: * Sends a command to the SPC to load and program a row of data in * Flash or EEPROM. * -* Parameters: -* arrayID: ID of the array to write. +* \param arrayID: ID of the array to write. * The type of write, Flash or EEPROM, is determined from the array ID. * The arrays in the part are sequential starting at the first ID for the * specific memory type. The array ID for the Flash memory lasts from 0x00 to * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. -* rowAddress: rowAddress of flash row to program. -* rowData: Array of bytes to write. +* \param rowAddress: rowAddress of flash row to program. +* \param rowData: Array of bytes to write. * -* Return: +* \return * status: * CYRET_SUCCESS if successful. * CYRET_LOCKED if the SPC is already in use. @@ -384,21 +352,19 @@ cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) /******************************************************************************* * Function Name: CyWriteRowConfig - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Sends a command to the SPC to load and program a row of config data in the Flash. - * This function is only valid for Flash array IDs (not for EEPROM). + * Sends a command to the SPC to load and program a row of config data in the + * Flash. This function is only valid for Flash array IDs (not for EEPROM). * - * Parameters: - * arrayId: ID of the array to write + * \param arrayId: ID of the array to write * The arrays in the part are sequential starting at the first ID for the * specific memory type. The array ID for the Flash memory lasts * from 0x00 to 0x3F. - * rowAddress: The address of the sector to erase. - * rowECC: The array of bytes to write. + * \param rowAddress: The address of the sector to erase. + * \param rowECC: The array of bytes to write. * - * Return: + * \return * status: * CYRET_SUCCESS if successful. * CYRET_LOCKED if the SPC is already in use. @@ -422,18 +388,16 @@ cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) /******************************************************************************* * Function Name: CyWriteRowFull -******************************************************************************** -* Summary: +****************************************************************************//** * Sends a command to the SPC to load and program a row of data in the Flash. * rowData array is expected to contain Flash and ECC data if needed. * -* Parameters: -* arrayId: FLASH or EEPROM array id. -* rowData: Pointer to a row of data to write. -* rowNumber: Zero based number of the row. -* rowSize: Size of the row. +* \param arrayId: FLASH or EEPROM array id. +* \param rowData: Pointer to a row of data to write. +* \param rowNumber: Zero based number of the row. +* \param rowSize: Size of the row. * -* Return: +* \return * CYRET_SUCCESS if successful. * CYRET_LOCKED if the SPC is already in use. * CYRET_CANCELED if command not accepted @@ -552,21 +516,16 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, u /******************************************************************************* * Function Name: CyFlash_SetWaitCycles -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the number of clock cycles the cache will wait before it samples data -* coming back from the Flash. This function must be called before increasing the CPU -* clock frequency. It can optionally be called after lowering the CPU clock -* frequency in order to improve the CPU performance. +* coming back from the Flash. This function must be called before increasing +* the CPU clock frequency. It can optionally be called after lowering the CPU +* clock frequency in order to improve the CPU performance. * -* Parameters: -* uint8 freq: +* \param uint8 freq: * Frequency of operation in Megahertz. * -* Return: -* None -* *******************************************************************************/ void CyFlash_SetWaitCycles(uint8 freq) { @@ -621,17 +580,10 @@ void CyFlash_SetWaitCycles(uint8 freq) /******************************************************************************* * Function Name: CyEEPROM_Start -******************************************************************************** +****************************************************************************//** * -* Summary: * Enable the EEPROM. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyEEPROM_Start(void) { @@ -679,17 +631,10 @@ void CyEEPROM_Start(void) /******************************************************************************* * Function Name: CyEEPROM_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * Disable the EEPROM. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyEEPROM_Stop (void) { @@ -706,17 +651,10 @@ void CyEEPROM_Stop (void) /******************************************************************************* * Function Name: CyEEPROM_ReadReserve -******************************************************************************** +****************************************************************************//** * -* Summary: * Request access to the EEPROM for reading and wait until access is available. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyEEPROM_ReadReserve(void) { @@ -732,17 +670,10 @@ void CyEEPROM_ReadReserve(void) /******************************************************************************* * Function Name: CyEEPROM_ReadRelease -******************************************************************************** +****************************************************************************//** * -* Summary: * Release the read reservation of the EEPROM. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyEEPROM_ReadRelease(void) { diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h old mode 100644 new mode 100755 index 119d7fc..6584a19 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -1,16 +1,15 @@ -/******************************************************************************* -* File Name: CyFlash.h -* Version 4.20 +/***************************************************************************//** +* \file CyFlash.h +* \version 5.50 * -* Description: -* Provides the function definitions for the FLASH/EEPROM. +* \brief Provides the function definitions for the FLASH/EEPROM. * -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -48,7 +47,7 @@ extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; #endif /* (CYDEV_ECC_ENABLE == 0) */ #define CY_EEPROM_BASE (CYDEV_EE_BASE) #define CY_EEPROM_SIZE (CYDEV_EE_SIZE) -#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EE_SIZE) /* EEPROM has one array */ #define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) #define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE) #define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) @@ -260,9 +259,9 @@ void CyEEPROM_ReadRelease(void) ; #define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) #define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) #define EEPROM_SIZE (CY_EEPROM_SIZE) -#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) +#define EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE) #define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) -#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_SECTORS) /******************************************************************************* diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c old mode 100644 new mode 100755 index a36bee0..3841b2f --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c @@ -1,16 +1,15 @@ -/******************************************************************************* -* File Name: CyLib.c -* Version 4.20 +/***************************************************************************//** +* \file CyLib.c +* \version 5.50 * -* Description: -* Provides a system API for the clocking, interrupts and watchdog timer. +* \brief Provides a system API for the clocking, interrupts and watchdog timer. * -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -50,26 +49,29 @@ static void CyIMO_SetTrimValue(uint8 freq) ; static void CyBusClk_Internal_SetDivider(uint16 divider); #if(CY_PSOC5) - static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; + static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; static void CySysTickServiceCallbacks(void); uint32 CySysTickInitVar = 0u; #endif /* (CY_PSOC5) */ +#if(CY_PSOC3) + CY_ISR_PROTO(IntDefaultHandler); +#endif /* (CY_PSOC3) */ + + /******************************************************************************* * Function Name: CyPLL_OUT_Start -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the PLL. Optionally waits for it to become stable. * Waits at least 250 us or until it is detected that the PLL is stable. * -* Parameters: -* wait: -* 0: Return immediately after configuration -* 1: Wait for PLL lock or timeout. +* \param wait: +* \param 0: Return immediately after configuration +* \param 1: Wait for PLL lock or timeout. * -* Return: +* \return * Status * CYRET_SUCCESS - Completed successfully * CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. @@ -77,7 +79,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider); * may not occur. However, after the timeout has expired the generated PLL * clock can still be used. * -* Side Effects: +* \sideeffect * If wait is enabled: This function uses the Fast Time Wheel to time the wait. * Any other use of the Fast Time Wheel will be stopped during the period of * this function and then restored. This function also uses the 100 KHz ILO. @@ -144,17 +146,10 @@ cystatus CyPLL_OUT_Start(uint8 wait) /******************************************************************************* * Function Name: CyPLL_OUT_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the PLL. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyPLL_OUT_Stop(void) { @@ -164,34 +159,29 @@ void CyPLL_OUT_Stop(void) /******************************************************************************* * Function Name: CyPLL_OUT_SetPQ -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the P and Q dividers and the charge pump current. * The Frequency Out will be P/Q * Frequency In. * The PLL must be disabled before calling this function. * -* Parameters: -* uint8 pDiv: +* \param uint8 pDiv: * Valid range [8 - 255]. * -* uint8 qDiv: +* \param uint8 qDiv: * Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. -* uint8 current: +* \param uint8 current: * Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and * datasheet for more information. * -* Return: -* None -* -* Side Effects: +* \sideeffect * If this function execution results in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * *******************************************************************************/ void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) @@ -225,28 +215,23 @@ void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) /******************************************************************************* * Function Name: CyPLL_OUT_SetSource -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the input clock source to the PLL. The PLL must be disabled before * calling this function. * -* Parameters: -* source: One of the three available PLL clock sources -* CY_PLL_SOURCE_IMO : IMO -* CY_PLL_SOURCE_XTAL : MHz Crystal -* CY_PLL_SOURCE_DSI : DSI +* \param source: One of the three available PLL clock sources +* \param CY_PLL_SOURCE_IMO : IMO +* \param CY_PLL_SOURCE_XTAL : MHz Crystal +* \param CY_PLL_SOURCE_DSI : DSI * -* Return: -* None -* -* Side Effects: +* \sideeffect * If this function execution results in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the3 Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * *******************************************************************************/ void CyPLL_OUT_SetSource(uint8 source) @@ -271,20 +256,15 @@ void CyPLL_OUT_SetSource(uint8 source) /******************************************************************************* * Function Name: CyIMO_Start -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the IMO. Optionally waits at least 6 us for it to settle. * -* Parameters: -* uint8 wait: -* 0: Return immediately after configuration -* 1: Wait for at least 6 us for the IMO to settle. +* \param uint8 wait: +* \param 0: Return immediately after configuration +* \param 1: Wait for at least 6 us for the IMO to settle. * -* Return: -* None -* -* Side Effects: +* \sideeffect * If wait is enabled: This function uses the Fast Time Wheel to time the wait. * Any other use of the Fast Time Wheel will be stopped during the period of * this function and then restored. This function also uses the 100 KHz ILO. @@ -336,17 +316,10 @@ void CyIMO_Start(uint8 wait) /******************************************************************************* * Function Name: CyIMO_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the IMO. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyIMO_Stop(void) { @@ -357,15 +330,11 @@ void CyIMO_Stop(void) /******************************************************************************* * Function Name: CyUSB_PowerOnCheck -******************************************************************************** +****************************************************************************//** * -* Summary: * Returns the USB power status value. A private function to cy_boot. * -* Parameters: -* None -* -* Return: +* \return * uint8: one if the USB is enabled, 0 if not enabled. * *******************************************************************************/ @@ -373,7 +342,7 @@ static uint8 CyUSB_PowerOnCheck(void) { uint8 poweredOn = 0u; - /* Check whether device is in Active or AltActiv and if USB is powered on */ + /* Check whether device is in Active or AltActive and if USB is powered on */ if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && @@ -388,17 +357,12 @@ static uint8 CyUSB_PowerOnCheck(void) /******************************************************************************* * Function Name: CyIMO_SetTrimValue -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the IMO factory trim values. * -* Parameters: * uint8 freq - frequency for which trims must be set * -* Return: -* None -* *******************************************************************************/ static void CyIMO_SetTrimValue(uint8 freq) { @@ -463,13 +427,11 @@ static void CyIMO_SetTrimValue(uint8 freq) /******************************************************************************* * Function Name: CyIMO_SetFreq -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the frequency of the IMO. Changes may be made while the IMO is running. * -* Parameters: -* freq: Frequency of IMO operation +* \param freq: Frequency of IMO operation * CY_IMO_FREQ_3MHZ to set 3 MHz * CY_IMO_FREQ_6MHZ to set 6 MHz * CY_IMO_FREQ_12MHZ to set 12 MHz @@ -479,16 +441,13 @@ static void CyIMO_SetTrimValue(uint8 freq) * CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) * CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) * -* Return: -* None -* -* Side Effects: +* \sideeffect * If this function execution results in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * * When the USB setting is chosen, the USB clock locking circuit is enabled. * Otherwise this circuit is disabled. The USB block must be powered before @@ -625,29 +584,24 @@ void CyIMO_SetFreq(uint8 freq) /******************************************************************************* * Function Name: CyIMO_SetSource -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the source of the clock output from the IMO block. * * The output from the IMO is by default the IMO itself. Optionally the MHz * Crystal or DSI input can be the source of the IMO output instead. * -* Parameters: -* source: CY_IMO_SOURCE_DSI to set the DSI as source. +* \param source: CY_IMO_SOURCE_DSI to set the DSI as source. * CY_IMO_SOURCE_XTAL to set the MHz as source. * CY_IMO_SOURCE_IMO to set the IMO itself. * -* Return: -* None -* -* Side Effects: +* \sideeffect * If this function execution resulted in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * *******************************************************************************/ void CyIMO_SetSource(uint8 source) @@ -678,18 +632,11 @@ void CyIMO_SetSource(uint8 source) /******************************************************************************* * Function Name: CyIMO_EnableDoubler -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz * input to a 48 MHz output for use by the USB block. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyIMO_EnableDoubler(void) { @@ -700,17 +647,10 @@ void CyIMO_EnableDoubler(void) /******************************************************************************* * Function Name: CyIMO_DisableDoubler -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the IMO doubler. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyIMO_DisableDoubler(void) { @@ -720,31 +660,26 @@ void CyIMO_DisableDoubler(void) /******************************************************************************* * Function Name: CyMasterClk_SetSource -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the source of the master clock. * -* Parameters: -* source: One of the four available Master clock sources. +* \param source: One of the four available Master clock sources. * CY_MASTER_SOURCE_IMO * CY_MASTER_SOURCE_PLL * CY_MASTER_SOURCE_XTAL * CY_MASTER_SOURCE_DSI * -* Return: -* None -* -* Side Effects: +* \sideeffect * The current source and the new source must both be running and stable before * calling this function. * * If this function execution resulted in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * *******************************************************************************/ void CyMasterClk_SetSource(uint8 source) @@ -756,26 +691,21 @@ void CyMasterClk_SetSource(uint8 source) /******************************************************************************* * Function Name: CyMasterClk_SetDivider -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the divider value used to generate Master Clock. * -* Parameters: -* uint8 divider: +* \param uint8 divider: * The valid range is [0-255]. The clock will be divided by this value + 1. * For example to divide this parameter by two should be set to 1. * -* Return: -* None -* -* Side Effects: +* \sideeffect * If this function execution resulted in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * * When changing the Master or Bus clock divider value from div-by-n to div-by-1 * the first clock cycle output after the div-by-1 can be up to 4 ns shorter @@ -790,19 +720,14 @@ void CyMasterClk_SetDivider(uint8 divider) /******************************************************************************* * Function Name: CyBusClk_Internal_SetDivider -******************************************************************************** +****************************************************************************//** * -* Summary: * The function used by CyBusClk_SetDivider(). For internal use only. * -* Parameters: -* divider: Valid range [0-65535]. +* \param divider: Valid range [0-65535]. * The clock will be divided by this value + 1. * For example, to divide this parameter by two should be set to 1. * -* Return: -* None -* *******************************************************************************/ static void CyBusClk_Internal_SetDivider(uint16 divider) { @@ -830,25 +755,20 @@ static void CyBusClk_Internal_SetDivider(uint16 divider) /******************************************************************************* * Function Name: CyBusClk_SetDivider -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the divider value used to generate the Bus Clock. * -* Parameters: -* divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* \param divider: Valid range [0-65535]. The clock will be divided by this value + 1. * For example, to divide this parameter by two should be set to 1. * -* Return: -* None -* -* Side Effects: +* \sideeffect * If this function execution resulted in the CPU clock frequency increasing, * then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. -* See CyFlash_SetWaitCycles() description for more information. +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. * *******************************************************************************/ void CyBusClk_SetDivider(uint16 divider) @@ -902,26 +822,21 @@ void CyBusClk_SetDivider(uint16 divider) /******************************************************************************* * Function Name: CyCpuClk_SetDivider - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets the divider value used to generate the CPU Clock. Only applicable for * PSoC 3 parts. * - * Parameters: - * divider: Valid range [0-15]. The clock will be divided by this value + 1. + * \param divider: Valid range [0-15]. The clock will be divided by this value + 1. * For example, to divide this parameter by two should be set to 1. * - * Return: - * None - * - * Side Effects: + * \sideeffect * If this function execution resulted in the CPU clock frequency increasing, -* then the number of clock cycles the cache will wait before it samples data -* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() -* with an appropriate parameter. It can be optionally called if the CPU clock -* frequency is lowered in order to improve the CPU performance. - * See CyFlash_SetWaitCycles() description for more information. + * then the number of clock cycles the cache will wait before it samples data + * coming back from the Flash must be adjusted by calling + * CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally + * called if the CPU clock frequency is lowered in order to improve the CPU + * performance. See CyFlash_SetWaitCycles() description for more information. * *******************************************************************************/ void CyCpuClk_SetDivider(uint8 divider) @@ -935,21 +850,16 @@ void CyBusClk_SetDivider(uint16 divider) /******************************************************************************* * Function Name: CyUsbClk_SetSource -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the source of the USB clock. * -* Parameters: -* source: One of the four available USB clock sources +* \param source: One of the four available USB clock sources * CY_LIB_USB_CLK_IMO2X - IMO 2x * CY_LIB_USB_CLK_IMO - IMO * CY_LIB_USB_CLK_PLL - PLL * CY_LIB_USB_CLK_DSI - DSI * -* Return: -* None -* *******************************************************************************/ void CyUsbClk_SetSource(uint8 source) { @@ -960,21 +870,14 @@ void CyUsbClk_SetSource(uint8 source) /******************************************************************************* * Function Name: CyILO_Start1K -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the ILO 1 KHz oscillator. * * Note The ILO 1 KHz oscillator is always enabled by default, regardless of the * selection in the Clock Editor. Therefore, this API is only needed if the * oscillator was turned off manually. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyILO_Start1K(void) { @@ -985,22 +888,15 @@ void CyILO_Start1K(void) /******************************************************************************* * Function Name: CyILO_Stop1K -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the ILO 1 KHz oscillator. * -* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power -* mode APIs are expected to be used. For more information, refer to the Power -* Management section of this document. +* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low +* power mode APIs are expected to be used. For more information, refer to the +* Power Management section of this document. * -* Parameters: -* None -* -* Return: -* None -* -* Side Effects: +* \sideeffect * PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. * *******************************************************************************/ @@ -1013,17 +909,10 @@ void CyILO_Stop1K(void) /******************************************************************************* * Function Name: CyILO_Start100K -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the ILO 100 KHz oscillator. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyILO_Start100K(void) { @@ -1033,17 +922,10 @@ void CyILO_Start100K(void) /******************************************************************************* * Function Name: CyILO_Stop100K -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the ILO 100 KHz oscillator. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyILO_Stop100K(void) { @@ -1053,20 +935,13 @@ void CyILO_Stop100K(void) /******************************************************************************* * Function Name: CyILO_Enable33K -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the ILO 33 KHz divider. * * Note that the 33 KHz clock is generated from the 100 KHz oscillator, * so it must also be running in order to generate the 33 KHz output. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyILO_Enable33K(void) { @@ -1077,20 +952,13 @@ void CyILO_Enable33K(void) /******************************************************************************* * Function Name: CyILO_Disable33K -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the ILO 33 KHz divider. * * Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this * API does not disable the 100 KHz clock. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyILO_Disable33K(void) { @@ -1100,21 +968,16 @@ void CyILO_Disable33K(void) /******************************************************************************* * Function Name: CyILO_SetSource -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the source of the clock output from the ILO block. * -* Parameters: -* source: One of the three available ILO output sources +* \param source: One of the three available ILO output sources * Value Define Source * 0 CY_ILO_SOURCE_100K ILO 100 KHz * 1 CY_ILO_SOURCE_33K ILO 33 KHz * 2 CY_ILO_SOURCE_1K ILO 1 KHz * -* Return: -* None -* *******************************************************************************/ void CyILO_SetSource(uint8 source) { @@ -1125,19 +988,16 @@ void CyILO_SetSource(uint8 source) /******************************************************************************* * Function Name: CyILO_SetPowerMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Sets the power mode used by the ILO during power down. Allows for lower power -* down power usage resulting in a slower startup time. +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. * -* Parameters: -* uint8 mode -* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down -* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* \param mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down * -* Return: -* Prevous power mode state. +* \return Prevous power mode state. * *******************************************************************************/ uint8 CyILO_SetPowerMode(uint8 mode) @@ -1164,17 +1024,10 @@ uint8 CyILO_SetPowerMode(uint8 mode) /******************************************************************************* * Function Name: CyXTAL_32KHZ_Start -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the 32 KHz Crystal Oscillator. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_32KHZ_Start(void) { @@ -1208,17 +1061,10 @@ void CyXTAL_32KHZ_Start(void) /******************************************************************************* * Function Name: CyXTAL_32KHZ_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the 32KHz Crystal Oscillator. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_32KHZ_Stop(void) { @@ -1236,15 +1082,11 @@ void CyXTAL_32KHZ_Stop(void) /******************************************************************************* * Function Name: CyXTAL_32KHZ_ReadStatus -******************************************************************************** +****************************************************************************//** * -* Summary: * Returns status of the 32 KHz oscillator. * -* Parameters: -* None -* -* Return: +* \return * Value Define Source * 20 CY_XTAL32K_ANA_STAT Analog measurement * 1: Stable @@ -1259,19 +1101,17 @@ uint8 CyXTAL_32KHZ_ReadStatus(void) /******************************************************************************* * Function Name: CyXTAL_32KHZ_SetPowerMode -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the power mode for the 32 KHz oscillator used during the sleep mode. * Allows for lower power during sleep when there are fewer sources of noise. * During the active mode the oscillator is always run in the high power mode. * -* Parameters: * uint8 mode -* 0: High power mode -* 1: Low power mode during sleep +* \param 0: High power mode +* \param 1: Low power mode during sleep * -* Return: +* \return * Previous power mode. * *******************************************************************************/ @@ -1307,21 +1147,19 @@ uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) /******************************************************************************* * Function Name: CyXTAL_Start -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the megahertz crystal. * * PSoC 3: * Waits until the XERR bit is low (no error) for a millisecond or until the * number of milliseconds specified by the wait parameter has expired. * -* Parameters: -* wait: Valid range [0-255]. +* \param wait: Valid range [0-255]. * This is the timeout value in milliseconds. * The appropriate value is crystal specific. * -* Return: +* \return * CYRET_SUCCESS - Completed successfully * CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. * @@ -1409,17 +1247,10 @@ cystatus CyXTAL_Start(uint8 wait) /******************************************************************************* * Function Name: CyXTAL_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the megahertz crystal oscillator. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_Stop(void) { @@ -1430,18 +1261,11 @@ void CyXTAL_Stop(void) /******************************************************************************* * Function Name: CyXTAL_EnableErrStatus -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the generation of the XERR status bit for the megahertz crystal. * This function is not available for PSoC5. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_EnableErrStatus(void) { @@ -1452,18 +1276,11 @@ void CyXTAL_EnableErrStatus(void) /******************************************************************************* * Function Name: CyXTAL_DisableErrStatus -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the generation of the XERR status bit for the megahertz crystal. * This function is not available for PSoC5. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_DisableErrStatus(void) { @@ -1474,16 +1291,12 @@ void CyXTAL_DisableErrStatus(void) /******************************************************************************* * Function Name: CyXTAL_ReadStatus -******************************************************************************** +****************************************************************************//** * -* Summary: * Reads the XERR status bit for the megahertz crystal. This status bit is a * sticky, clear on read. This function is not available for PSoC5. * -* Parameters: -* None -* -* Return: +* \return * Status * 0: No error * 1: Error @@ -1501,20 +1314,13 @@ uint8 CyXTAL_ReadStatus(void) /******************************************************************************* * Function Name: CyXTAL_EnableFaultRecovery -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the fault recovery circuit which will switch to the IMO in the case * of a fault in the megahertz crystal circuit. The crystal must be up and * running with the XERR bit at 0, before calling this function to prevent * an immediate fault switchover. This function is not available for PSoC5. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_EnableFaultRecovery(void) { @@ -1524,19 +1330,12 @@ void CyXTAL_EnableFaultRecovery(void) /******************************************************************************* * Function Name: CyXTAL_DisableFaultRecovery -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the fault recovery circuit which will switch to the IMO in the case * of a fault in the megahertz crystal circuit. This function is not available * for PSoC5. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyXTAL_DisableFaultRecovery(void) { @@ -1546,22 +1345,17 @@ void CyXTAL_DisableFaultRecovery(void) /******************************************************************************* * Function Name: CyXTAL_SetStartup -******************************************************************************** +****************************************************************************//** * -* Summary: -* Sets the startup settings for the crystal. The logic model outputs a frequency -* (setting + 4) MHz when enabled. +* Sets the startup settings for the crystal. The logic model outputs a +* frequency (setting + 4) MHz when enabled. * * This is artificial as the actual frequency is determined by an attached * external crystal. * -* Parameters: -* setting: Valid range [0-31]. -* The value is dependent on the frequency and quality of the crystal being used. -* Refer to the device TRM and datasheet for more information. -* -* Return: -* None +* \param setting: Valid range [0-31]. +* The value is dependent on the frequency and quality of the crystal being +* used. Refer to the device TRM and datasheet for more information. * *******************************************************************************/ void CyXTAL_SetStartup(uint8 setting) @@ -1574,19 +1368,14 @@ void CyXTAL_SetStartup(uint8 setting) /******************************************************************************* * Function Name: CyXTAL_SetFbVoltage -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the feedback reference voltage to use for the crystal circuit. * This function is only available for PSoC3 and PSoC 5LP. * -* Parameters: -* setting: Valid range [0-15]. +* \param setting: Valid range [0-15]. * Refer to the device TRM and datasheet for more information. * -* Return: -* None -* *******************************************************************************/ void CyXTAL_SetFbVoltage(uint8 setting) { @@ -1597,19 +1386,14 @@ void CyXTAL_SetFbVoltage(uint8 setting) /******************************************************************************* * Function Name: CyXTAL_SetWdVoltage -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the reference voltage used by the watchdog to detect a failure in the * crystal circuit. This function is only available for PSoC3 and PSoC 5LP. * -* Parameters: -* setting: Valid range [0-7]. +* \param setting: Valid range [0-7]. * Refer to the device TRM and datasheet for more information. * -* Return: -* None -* *******************************************************************************/ void CyXTAL_SetWdVoltage(uint8 setting) { @@ -1620,16 +1404,11 @@ void CyXTAL_SetWdVoltage(uint8 setting) /******************************************************************************* * Function Name: CyHalt -******************************************************************************** +****************************************************************************//** * -* Summary: * Halts the CPU. * -* Parameters: -* uint8 reason: Value to be used during debugging. -* -* Return: -* None +* \param uint8 reason: Value to be used during debugging. * *******************************************************************************/ void CyHalt(uint8 reason) CYREENTRANT @@ -1651,17 +1430,10 @@ void CyHalt(uint8 reason) CYREENTRANT /******************************************************************************* * Function Name: CySoftwareReset -******************************************************************************** +****************************************************************************//** * -* Summary: * Forces a device software reset. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CySoftwareReset(void) { @@ -1671,9 +1443,8 @@ void CySoftwareReset(void) /******************************************************************************* * Function Name: CyDelay -******************************************************************************** +****************************************************************************//** * -* Summary: * Blocks for milliseconds. * * Note: @@ -1682,11 +1453,7 @@ void CySoftwareReset(void) * For example, with instruction cache disabled CyDelay(100) would result in * about 200 ms delay instead of 100 ms. * -* Parameters: -* milliseconds: number of milliseconds to delay. -* -* Return: -* None +* \param milliseconds: number of milliseconds to delay. * *******************************************************************************/ void CyDelay(uint32 milliseconds) CYREENTRANT @@ -1711,9 +1478,8 @@ void CyDelay(uint32 milliseconds) CYREENTRANT /******************************************************************************* * Function Name: CyDelayUs - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Blocks for microseconds. * * Note: @@ -1722,13 +1488,9 @@ void CyDelay(uint32 milliseconds) CYREENTRANT * larger. Ex: With instruction cache disabled CyDelayUs(100) would result * in about 200us delay instead of 100us. * - * Parameters: - * uint16 microseconds: number of microseconds to delay. + * \param uint16 microseconds: number of microseconds to delay. * - * Return: - * None - * - * Side Effects: + * \sideeffect * CyDelayUS has been implemented with the instruction cache assumed enabled. * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times * larger. For example, with the instruction cache disabled CyDelayUs(100) would @@ -1748,16 +1510,11 @@ void CyDelay(uint32 milliseconds) CYREENTRANT /******************************************************************************* * Function Name: CyDelayFreq -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the clock frequency for CyDelay. * -* Parameters: -* freq: The frequency of the bus clock in Hertz. -* -* Return: -* None +* \param freq: The frequency of the bus clock in Hertz. * *******************************************************************************/ void CyDelayFreq(uint32 freq) CYREENTRANT @@ -1779,14 +1536,13 @@ void CyDelayFreq(uint32 freq) CYREENTRANT /******************************************************************************* * Function Name: CyWdtStart -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables the watchdog timer. * * The timer is configured for the specified count interval, the central -* timewheel is cleared, the setting for the low power mode is configured and the -* watchdog timer is enabled. +* timewheel is cleared, the setting for the low power mode is configured and +* the watchdog timer is enabled. * * Once enabled the watchdog cannot be disabled. The watchdog counts each time * the Central Time Wheel (CTW) reaches the period specified. The watchdog must @@ -1799,15 +1555,14 @@ void CyDelayFreq(uint32 freq) CYREENTRANT * set to be greater than the sleep wakeup period, then feed the dog on each * wakeup from Sleep. * -* Parameters: -* ticks: One of the four available timer periods. Once WDT enabled, the +* \param ticks: One of the four available timer periods. Once WDT enabled, the interval cannot be changed. * CYWDT_2_TICKS - 4 - 6 ms * CYWDT_16_TICKS - 32 - 48 ms * CYWDT_128_TICKS - 256 - 384 ms * CYWDT_1024_TICKS - 2.048 - 3.072 s * -* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* \param lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. * The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. * * CYWDT_LPMODE_NOCHANGE - No Change @@ -1815,10 +1570,7 @@ void CyDelayFreq(uint32 freq) CYREENTRANT * mode * CYWDT_LPMODE_DISABLED - Disable WDT during low power mode * -* Return: -* None -* -* Side Effects: +* \sideeffect * PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the * ILO 1 kHz could break the active WDT functionality. * @@ -1843,17 +1595,10 @@ void CyWdtStart(uint8 ticks, uint8 lpMode) /******************************************************************************* * Function Name: CyWdtClear -******************************************************************************** +****************************************************************************//** * -* Summary: * Clears (feeds) the watchdog timer. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyWdtClear(void) { @@ -1864,28 +1609,53 @@ void CyWdtClear(void) /******************************************************************************* * Function Name: CyVdLvDigitEnable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Enables the digital low voltage monitors to generate interrupt on Vddd -* archives specified threshold and optionally resets the device. +* Sets the voltage trip level, enables the output of the digital low-voltage +* monitor, and optionally configures voltage monitor to reset device upon the +* low-voltage event instead of generating an interrupt. * -* Parameters: -* reset: The option to reset the device at a specified Vddd threshold: -* 0 - Device is not reset. -* 1 - Device is reset. +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. * -* threshold: Sets the trip level for the voltage monitor. -* Values from 1.70 V to 5.45 V are accepted with an interval of approximately -* 250 mV. +* \param reset: Enables device reset on digital low-voltage event: +* Zero - Interrupt on digital low-voltage event +* Non-zero - Reset on digital low-voltage event * -* Return: -* None +* \param threshold: Sets the trip point of the digital low-voltage monitoring circuit +* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V +* (0x0F). For example, the trip point is set to 1.80 V when the threshold +* parameter value is 0x04. Refer to the device TRM for the exact trip voltage +* values. +* +* Side Effects and Restrictions: +* The voltage resets are momentary. When a voltage reset (analog/digital +* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 +* registers are restored to their default values. This means that the voltage +* monitor circuit is no longer enabled and the device exits reset. If the +* supply is below the trip level and firmware enables the voltage reset +* functionality, the device will reset again. This will continue as long as the +* supply is below the trip level or as long as the user enables the reset +* functionality of the voltage monitor functionality. +* +* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers +* are cleared. This means that analog low-voltage, digital low-voltage and +* analog high-voltage status bits are not persistent across any voltage reset. * *******************************************************************************/ void CyVdLvDigitEnable(uint8 reset, uint8 threshold) { - *CY_INT_CLEAR_PTR = 0x01u; + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); @@ -1893,10 +1663,10 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold) (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; - /* Timeout to eliminate glitches on LVI/HVI when enabling */ + /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */ CyDelayUs(1u); - (void)CY_VD_PERSISTENT_STATUS_REG; + (void) CyVdStickyStatus(CY_VD_LVID); if(0u != reset) { @@ -1907,45 +1677,75 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold) CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); } - *CY_INT_CLR_PEND_PTR = 0x01u; - *CY_INT_ENABLE_PTR = 0x01u; + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); } /******************************************************************************* * Function Name: CyVdLvAnalogEnable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Enables the analog low voltage monitors to generate interrupt on Vdda -* archives specified threshold and optionally resets the device. +* Sets the voltage trip level, enables the output of the analog low-voltage +* monitor, and optionally configures voltage monitor to reset device upon the +* low-voltage event instead of generating an interrupt. * -* Parameters: -* reset: The option to reset the device at a specified Vdda threshold: -* 0 - Device is not reset. -* 1 - Device is reset. +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. * -* threshold: Sets the trip level for the voltage monitor. -* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV -* interval. +* \param reset: Enables device reset on analog low-voltage event: +* Zero - Interrupt on analog low-voltage event +* Non-zero - Reset on analog low-voltage event * -* Return: -* None +* \param threshold: Sets the trip point of the analog low-voltage monitoring circuit +* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V +* (0x0F). For example, the trip point is set to 1.80 V when value of the +* threshold parameter is 0x04. Please refer to the device TRM for the exact +* trip voltage values. +* +* Side Effects and Restrictions: +* The voltage resets are momentary. When a voltage reset (analog/digital +* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 +* registers are restored to their default values. This means that the voltage +* monitor circuit is no longer enabled and the device exits reset. If the +* supply is below the trip level and firmware enables the voltage reset +* functionality, the device will reset again. This will continue as long as +* the supply is below the trip level or as long as the user enables the reset +* functionality of the voltage monitor functionality. +* +* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers +* are cleared. This means that analog low-voltage, digital low-voltage and +* analog high-voltage status bits are not persistent across any voltage reset. * *******************************************************************************/ void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) { - *CY_INT_CLEAR_PTR = 0x01u; + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; - /* Timeout to eliminate glitches on LVI/HVI when enabling */ + /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */ CyDelayUs(1u); - (void)CY_VD_PERSISTENT_STATUS_REG; + (void) CyVdStickyStatus(CY_VD_LVIA); if(0u != reset) { @@ -1956,33 +1756,35 @@ void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); } - *CY_INT_CLR_PEND_PTR = 0x01u; - *CY_INT_ENABLE_PTR = 0x01u; + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); } /******************************************************************************* * Function Name: CyVdLvDigitDisable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Disables the digital low voltage monitor (interrupt and device reset are -* disabled). +* Disables the digital low-voltage monitor, turns off device reset upon the +* digital low-voltage event, and clears the associated persistent status bit. * -* Parameters: -* None -* -* Return: -* None +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. * *******************************************************************************/ void CyVdLvDigitDisable(void) { CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + (void) CyVdStickyStatus(CY_VD_LVID); - while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + while(0u != (CyVdStickyStatus(CY_VD_LVID) & CY_VD_LVID)) { } @@ -1991,26 +1793,21 @@ void CyVdLvDigitDisable(void) /******************************************************************************* * Function Name: CyVdLvAnalogDisable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Disables the analog low voltage monitor (interrupt and device reset are -* disabled). +* Disables the analog low-voltage monitor, turns off device reset upon the +* analog low-voltage event, and clears the associated persistent status bit. * -* Parameters: -* None -* -* Return: -* None +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. * *******************************************************************************/ void CyVdLvAnalogDisable(void) { CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); - CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); - - while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + while(0u != (CyVdStickyStatus(CY_VD_LVIA) & CY_VD_LVIA)) { } @@ -2019,105 +1816,134 @@ void CyVdLvAnalogDisable(void) /******************************************************************************* * Function Name: CyVdHvAnalogEnable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Enables the analog high voltage monitors to generate interrupt on -* Vdda archives 5.75 V threshold and optionally resets device. +* Enables the output of the analog high-voltage monitor and sets 5.75 V +* threshold detection for Vdda. * -* Parameters: -* None -* -* Return: -* None +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. * *******************************************************************************/ void CyVdHvAnalogEnable(void) { - *CY_INT_CLEAR_PTR = 0x01u; + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; - /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + /* Timeout to eliminate glitches on the LVI/HVI when enabling (ID # 127412) */ CyDelayUs(1u); - (void) CY_VD_PERSISTENT_STATUS_REG; + (void) CyVdStickyStatus(CY_VD_HVIA); - *CY_INT_CLR_PEND_PTR = 0x01u; - *CY_INT_ENABLE_PTR = 0x01u; + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); } /******************************************************************************* * Function Name: CyVdHvAnalogDisable -******************************************************************************** +****************************************************************************//** * -* Summary: -* Disables the analog low voltage monitor -* (interrupt and device reset are disabled). +* Disables the analog high-voltage monitor and clears the associated persistent +* status bit. * -* Parameters: -* None -* -* Return: -* None +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. * *******************************************************************************/ void CyVdHvAnalogDisable(void) { CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); + while(0u != (CyVdStickyStatus(CY_VD_HVIA) & CY_VD_HVIA)) + { + + } } /******************************************************************************* * Function Name: CyVdStickyStatus -******************************************************************************** +****************************************************************************//** * -* Summary: -* Manages the Reset and Voltage Detection Status Register 0. -* This register has the interrupt status for the HVIA, LVID and LVIA. -* This hardware register clears on read. +* Reads and clears the voltage detection status bits in the RESET_SR0 register. +* The bits are set to 1 by the voltage monitor circuit when the supply is +* outside the detector trip point. They stay set to 1 until they are read or +* a POR / LVI / PRES reset occurs. This function uses a shadow register, so +* only the bits passed in the parameter will be cleared in the shadow register. * -* Parameters: -* mask: Bits in the shadow register to clear. +* \param mask: Bits in the RESET_SR0 shadow register to clear and return. * Define Definition * CY_VD_LVID Persistent status of digital LVI. * CY_VD_LVIA Persistent status of analog LVI. * CY_VD_HVIA Persistent status of analog HVI. * -* Return: -* Status. Same enumerated bit values as used for the mask parameter. +* \return +* Status. Same enumerated bit values as used for the mask parameter. A zero is +* returned for bits not used in the mask parameter. +* +* Side Effects and Restrictions: +* When an LVI reset occurs, the RESET_SR0 status registers are cleared. This +* means that the voltage detection status bits are not persistent across an LVI +* reset and cannot be used to determine a reset source. * *******************************************************************************/ uint8 CyVdStickyStatus(uint8 mask) { - uint8 status; + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; - status = CY_VD_PERSISTENT_STATUS_REG; - CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); + interruptState = CyEnterCriticalSection(); - return(status); + interruptStatus |= CY_VD_PERSISTENT_STATUS_REG; + tmpStatus = interruptStatus & (uint8)(CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA); + interruptStatus &= ((uint8)(~mask)); + + CyExitCriticalSection(interruptState); + + return(tmpStatus); } /******************************************************************************* * Function Name: CyVdRealTimeStatus -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the real time voltage detection status. +* Reads the real-time voltage detection status bits in the RESET_SR2 register. +* The bits are set to 1 by the voltage monitor circuit when the supply is +* outside the detector’s trip point, and set to 0 when the supply is inside the +* trip point. * -* Parameters: -* None -* -* Return: -* Status: +* \return +* Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register. * Define Definition -* CY_VD_LVID Persistent status of digital LVI. -* CY_VD_LVIA Persistent status of analog LVI. -* CY_VD_HVIA Persistent status of analog HVI. +* CY_VD_LVID Real-time status of digital LVI. +* CY_VD_LVIA Real-time status of analog LVI. +* CY_VD_HVIA Real-time status of analog HVI. +* +* Side Effects and Restrictions: +* When an LVI reset occurs, the RESET_SR2 status registers are cleared. This +* means that the voltage detection status bits are not persistent across an LVI +* reset and cannot be used to determine a reset source. * *******************************************************************************/ uint8 CyVdRealTimeStatus(void) @@ -2126,7 +1952,7 @@ uint8 CyVdRealTimeStatus(void) uint8 vdFlagsState; interruptState = CyEnterCriticalSection(); - vdFlagsState = CY_VD_RT_STATUS_REG; + vdFlagsState = CY_VD_RT_STATUS_REG & (CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA); CyExitCriticalSection(interruptState); return(vdFlagsState); @@ -2135,15 +1961,11 @@ uint8 CyVdRealTimeStatus(void) /******************************************************************************* * Function Name: CyDisableInts -******************************************************************************** +****************************************************************************//** * -* Summary: * Disables the interrupt enable for each interrupt. * -* Parameters: -* None -* -* Return: +* \return * 32 bit mask of previously enabled interrupts. * *******************************************************************************/ @@ -2187,16 +2009,11 @@ uint32 CyDisableInts(void) /******************************************************************************* * Function Name: CyEnableInts -******************************************************************************** +****************************************************************************//** * -* Summary: * Enables interrupts to a given state. * -* Parameters: -* uint32 mask: 32 bit mask of interrupts to enable. -* -* Return: -* None +* \param uint32 mask: 32 bit mask of interrupts to enable. * *******************************************************************************/ void CyEnableInts(uint32 mask) @@ -2228,15 +2045,16 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyFlushCache - ******************************************************************************** - * Summary: - * Flushes the PSoC 5/5LP cache by invalidating all entries. - * - * Parameters: - * None - * - * Return: - * None + ****************************************************************************//** + * Call this API after a flash row erase/write operation to invalidate or flush + * any of that particular flash region content already present in the cache. + * After a cache flush operation, any access to that flash region after the + * erase/write operation would reload the cache with the modified data from the + * flash region. If the flash region update involves multiple flash row write + * operations, then the flushing of the cache can be done once at the end of + * the operation as long as the flash data would not be accessed in the middle + * of the multiple row update process. Else, flush the cache after every flash + * row write. * *******************************************************************************/ void CyFlushCache(void) @@ -2280,14 +2098,12 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntSetSysVector - ******************************************************************************** - * Summary: + ****************************************************************************//** * Sets the interrupt vector of the specified system interrupt number. System * interrupts are present only for the ARM platform. These interrupts are for * SysTick, PendSV and others. * - * Parameters: - * number: System interrupt number: + * \param number: System interrupt number: * CY_INT_NMI_IRQN - Non Maskable Interrupt * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt @@ -2298,9 +2114,9 @@ void CyEnableInts(uint32 mask) * CY_INT_PEND_SV_IRQN - Pend SV Interrupt * CY_INT_SYSTICK_IRQN - System Tick Interrupt * - * address: Pointer to an interrupt service routine. + * \param address: Pointer to an interrupt service routine. * - * Return: + * \return * The old ISR vector at this location. * *******************************************************************************/ @@ -2323,15 +2139,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetSysVector - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the interrupt vector of the specified system interrupt number. System * interrupts are present only for the ARM platform. These interrupts are for * SysTick, PendSV and others. * - * Parameters: - * number: System interrupt number: + * \param number: System interrupt number: * CY_INT_NMI_IRQN - Non Maskable Interrupt * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt @@ -2342,7 +2156,7 @@ void CyEnableInts(uint32 mask) * CY_INT_PEND_SV_IRQN - Pend SV Interrupt * CY_INT_SYSTICK_IRQN - System Tick Interrupt * - * Return: + * \return * Address of the ISR in the interrupt vector table. * *******************************************************************************/ @@ -2357,16 +2171,14 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntSetVector - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets the interrupt vector of the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * address: Pointer to an interrupt service routine + * \param number: Valid range [0-31]. Interrupt number + * \param address: Pointer to an interrupt service routine * - * Return: + * \return * Previous interrupt vector value. * *******************************************************************************/ @@ -2389,15 +2201,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetVector - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the interrupt vector of the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number + * \param number: Valid range [0-31]. Interrupt number * - * Return: + * \return * The address of the ISR in the interrupt vector table. * *******************************************************************************/ @@ -2412,17 +2222,12 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntSetPriority - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets the Priority of the Interrupt. * - * Parameters: - * priority: Priority of the interrupt. 0 - 7, 0 being the highest. - * number: The number of the interrupt, 0 - 31. - * - * Return: - * None + * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * \param number: The number of the interrupt, 0 - 31. * *******************************************************************************/ void CyIntSetPriority(uint8 number, uint8 priority) @@ -2435,15 +2240,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetPriority - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the Priority of the Interrupt. * - * Parameters: - * number: The number of the interrupt, 0 - 31. + * \param number: The number of the interrupt, 0 - 31. * - * Return: + * \return * Priority of the interrupt. 0 - 7, 0 being the highest. * *******************************************************************************/ @@ -2461,15 +2264,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetState - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the enable state of the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. + * \param number: Valid range [0-31]. Interrupt number. * - * Return: + * \return * Enable status: 1 if enabled, 0 if disabled * *******************************************************************************/ @@ -2489,19 +2290,62 @@ void CyEnableInts(uint32 mask) #else /* PSoC3 */ + /******************************************************************************* + * Function Name: IntDefaultHandler + ****************************************************************************//** + * + * This function is called for all interrupts, other than a reset that gets + * called before the system is setup. + * + * Theory: + * Any value other than zero is acceptable. + * + *******************************************************************************/ + CY_ISR(IntDefaultHandler) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + /*********************************************************************** + * We must not get here. If we do, a serious problem occurs, so go + * into an infinite loop. + ***********************************************************************/ + } + } + + + /******************************************************************************* + * Function Name: IntDefaultHandler + ****************************************************************************//** + * + * This function is called during startup to initialize interrupt address vector + * registers with the address of the IntDefaultHandler(). + * + *******************************************************************************/ + void CyIntInitVectors(void) + { + uint8 i; + + for (i = 0; i <= CY_INT_NUMBER_MAX; i++) + { + CY_SET_REG16(&CY_INT_VECT_TABLE[i], (uint16) &IntDefaultHandler); + } + } + /******************************************************************************* * Function Name: CyIntSetVector - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets the interrupt vector of the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * address: Pointer to an interrupt service routine + * \param number: Valid range [0-31]. Interrupt number + * \param address: Pointer to an interrupt service routine * - * Return: + * \return * Previous interrupt vector value. * *******************************************************************************/ @@ -2524,15 +2368,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetVector - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the interrupt vector of the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number + * \param number: Valid range [0-31]. Interrupt number * - * Return: + * \return * Address of the ISR in the interrupt vector table. * *******************************************************************************/ @@ -2547,17 +2389,12 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntSetPriority - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets the Priority of the Interrupt. * - * Parameters: - * priority: Priority of the interrupt. 0 - 7, 0 being the highest. - * number: The number of the interrupt, 0 - 31. - * - * Return: - * None + * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * \param number: The number of the interrupt, 0 - 31. * *******************************************************************************/ void CyIntSetPriority(uint8 number, uint8 priority) @@ -2573,15 +2410,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetPriority - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the Priority of the Interrupt. * - * Parameters: - * number: The number of the interrupt, 0 - 31. + * \param number: The number of the interrupt, 0 - 31. * - * Return: + * \return * Priority of the interrupt. 0 - 7, 0 being the highest. * *******************************************************************************/ @@ -2599,15 +2434,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CyIntGetState - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets the enable state of the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. + * \param number: Valid range [0-31]. Interrupt number. * - * Return: + * \return * Enable status: 1 if enabled, 0 if disabled * *******************************************************************************/ @@ -2624,7 +2457,6 @@ void CyEnableInts(uint32 mask) return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); } - #endif /* (CY_PSOC5) */ @@ -2632,9 +2464,8 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySetScPumps - ******************************************************************************** + ****************************************************************************//** * - * Summary: * If 1 is passed as a parameter: * - if any of the SC blocks are used - enable pumps for the SC blocks and * start boost clock. @@ -2644,20 +2475,17 @@ void CyEnableInts(uint32 mask) * If non-1 value is passed as a parameter: * - If all SC blocks are not used - disable pumps for the SC blocks and * stop the boost clock. - * - For each enabled SC block clear the boost clock index and disable the boost - * clock. + * - For each enabled SC block clear the boost clock index and disable the + * boost clock. * * The global variable CyScPumpEnabled is updated to be equal to passed the * parameter. * - * Parameters: - * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block. + * \param uint8 enable: Enable/disable SC pumps and the boost clock for the enabled + * \param SC block: * 1 - Enable * 0 - Disable * - * Return: - * None - * *******************************************************************************/ void CySetScPumps(uint8 enable) { @@ -2718,20 +2546,13 @@ void CyEnableInts(uint32 mask) #if(CY_PSOC5) /******************************************************************************* * Function Name: CySysTickStart - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Configures the SysTick timer to generate interrupt every 1 ms by call to the * CySysTickInit() function and starts it by calling CySysTickEnable() function. * Refer to the corresponding function description for the details. - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set * *******************************************************************************/ @@ -2749,21 +2570,14 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickInit - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Initializes the callback addresses with pointers to NULL, associates the * SysTick system vector with the function that is responsible for calling * registered callback functions, configures SysTick timer to generate interrupt * every 1 ms. * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set. * * The 1 ms interrupt interval is configured based on the frequency determined @@ -2780,7 +2594,7 @@ void CyEnableInts(uint32 mask) CySysTickCallbacks[i] = (void *) 0; } - (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks); + (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks); CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK); CySysTickSetReload(cydelay_freq_hz/1000u); CySysTickClear(); @@ -2790,18 +2604,11 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickEnable - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Enables the SysTick timer and its interrupt. * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set * *******************************************************************************/ @@ -2814,18 +2621,11 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickStop - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Stops the system timer (SysTick). * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set * *******************************************************************************/ @@ -2837,18 +2637,11 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickEnableInterrupt - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Enables the SysTick interrupt. * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set * *******************************************************************************/ @@ -2860,18 +2653,11 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickDisableInterrupt - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Disables the SysTick interrupt. * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set * *******************************************************************************/ @@ -2883,18 +2669,13 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickSetReload - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets value the counter is set to on startup and after it reaches zero. This * function do not change or reset current sysTick counter value, so it should * be cleared using CySysTickClear() API. * - * Parameters: - * value: Valid range [0x0-0x00FFFFFF]. Counter reset value. - * - * Return: - * None + * \param value: Valid range [0x0-0x00FFFFFF]. Counter reset value. * *******************************************************************************/ void CySysTickSetReload(uint32 value) @@ -2905,15 +2686,11 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickGetReload - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets value the counter is set to on startup and after it reaches zero. * - * Parameters: - * None - * - * Return: + * \return * Counter reset value * *******************************************************************************/ @@ -2925,46 +2702,38 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickGetValue - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Gets current SysTick counter value. * - * Parameters: - * None - * - * Return: + * \return * Current SysTick counter value * *******************************************************************************/ uint32 CySysTickGetValue(void) { - return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG); + return(CY_SYS_SYST_CVR_REG & CY_SYS_SYST_CVR_CNT_MASK); } /******************************************************************************* * Function Name: CySysTickSetClockSource - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Sets the clock source for the SysTick counter. * - * Parameters: - * clockSource: Clock source for SysTick counter + * \param clockSource: Clock source for SysTick counter * Define Clock Source * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock. * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency - * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4). + * clock (ILO 100 KHz for PSoC 5LP, and + * LFCLK for PSoC 4). * - * Return: - * None - * - * Side Effects: + * \sideeffect * Clears SysTick count flag if it was set. If clock source is not ready this - * function call will have no effect. After changing clock source to the low frequency - * clock the counter and reload register values will remain unchanged so time to - * the interrupt will be significantly bigger and vice versa. + * function call will have no effect. After changing clock source to the low + * frequency clock the counter and reload register values will remain unchanged + * so time to the interrupt will be significantly bigger and vice versa. * *******************************************************************************/ void CySysTickSetClockSource(uint32 clockSource) @@ -2975,45 +2744,56 @@ void CyEnableInts(uint32 mask) } else { - CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT)); + CY_SYS_SYST_CSR_REG &= ((uint32) ~((uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT))); } } + + /******************************************************************************* + * Function Name: CySysTickGetClockSource + ****************************************************************************//** + * + * Returns the current clock source of the SysTick counter. + * + * \return + * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock. + * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency + * clock. (ILO 100 KHz for PSoC 5LP, and + * LFCLK for PSoC 4). + *******************************************************************************/ + uint32 CySysTickGetClockSource(void) + { + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ); + } + /******************************************************************************* * Function Name: CySysTickGetCountFlag - ******************************************************************************** + ****************************************************************************//** * - * Summary: * The count flag is set once SysTick counter reaches zero. * The flag cleared on read. * - * Parameters: - * None + * \return + * Returns non-zero value if flag is set, otherwise zero is returned. * - * Return: - * Returns non-zero value if counter is set, otherwise zero is returned. + * + * \sideeffect + * Clears SysTick count flag if it was set. * *******************************************************************************/ uint32 CySysTickGetCountFlag(void) { - return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); } /******************************************************************************* * Function Name: CySysTickClear - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Clears the SysTick counter for well-defined startup. * - * Parameters: - * None - * - * Return: - * None - * *******************************************************************************/ void CySysTickClear(void) { @@ -3023,21 +2803,32 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickSetCallback - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * The function set the pointers to the functions that will be called on - * SysTick interrupt. + * This function allows up to five user-defined interrupt service routine + * functions to be associated with the SysTick interrupt. These are specified + * through the use of pointers to the function. * - * Parameters: - * number: The number of callback function address to be set. - * The valid range is from 0 to 4. - * CallbackFunction: Function address. + * To set a custom callback function without the overhead of the system provided + * one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress
), + * where
is address of the custom defined interrupt service routine. + * Note: a custom callback function overrides the system defined callback + * functions. * - * Return: + * \param number: The number of the callback function addresses to be set. The valid + * range is from 0 to 4. + * + * void(*CallbackFunction(void): A pointer to the function that will be + * associated with the SysTick ISR for the + * specified number. + * + * \return * Returns the address of the previous callback function. * The NULL is returned if the specified address in not set. * + * \sideeffect + * The registered callback functions will be executed in the interrupt. + * *******************************************************************************/ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) { @@ -3051,16 +2842,16 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickGetCallback - ******************************************************************************** + ****************************************************************************//** * - * Summary: * The function get the specified callback pointer. * - * Parameters: - * None + * \param number: The number of callback function address to get. The valid + * range is from 0 to 4. * - * Return: - * None + * \return + * Returns the address of the specified callback function. + * The NULL is returned if the specified address in not initialized. * *******************************************************************************/ cySysTickCallback CySysTickGetCallback(uint32 number) @@ -3071,17 +2862,10 @@ void CyEnableInts(uint32 mask) /******************************************************************************* * Function Name: CySysTickServiceCallbacks - ******************************************************************************** + ****************************************************************************//** * - * Summary: * System Tick timer interrupt routine * - * Parameters: - * None - * - * Return: - * None - * *******************************************************************************/ static void CySysTickServiceCallbacks(void) { @@ -3102,4 +2886,43 @@ void CyEnableInts(uint32 mask) #endif /* (CY_PSOC5) */ +/******************************************************************************* +* Function Name: CyGetUniqueId +****************************************************************************//** +* +* Returns the 64-bit unique ID of the device. The uniqueness of the number is +* guaranteed for 10 years due to the die lot number having a cycle life of 10 +* years and even after 10 years, the probability of getting two identical +* numbers is very small. +* +* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +* the 64-bit unique ID of the device by loading them into the integer array +* pointed to by uniqueId. +* +*******************************************************************************/ +void CyGetUniqueId(uint32* uniqueId) +{ +#if(CY_PSOC4) + uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + + uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); +#else + uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB )); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u); + + uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC )); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u); +#endif /* (CY_PSOC4) */ +} + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h old mode 100644 new mode 100755 index a718ffa..18395d9 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h @@ -1,17 +1,16 @@ -/******************************************************************************* -* File Name: CyLib.h -* Version 4.20 +/***************************************************************************//** +* \file CyLib.h +* \version 5.50 * -* Description: -* Provides the function definitions for the system, clocking, interrupts and -* watchdog timer API. +* \brief Provides the function definitions for the system, clocking, interrupts +* and watchdog timer API. * -* Note: -* Documentation of the API's in this file is located in the System Reference -* Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -169,7 +168,7 @@ void CySetScPumps(uint8 enable) ; #endif /* (CY_PSOC5) */ #if(CY_PSOC5) - /* System tick timer APIs */ + /** System tick timer APIs */ typedef void (*cySysTickCallback)(void); void CySysTickStart(void); @@ -188,6 +187,9 @@ void CySetScPumps(uint8 enable) ; void CySysTickClear(void); #endif /* (CY_PSOC5) */ +void CyGetUniqueId(uint32* uniqueId); + + /*************************************** * API Constants ***************************************/ @@ -290,6 +292,7 @@ void CySetScPumps(uint8 enable) ; #define CY_VD_HVIA (0x04u) #define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) +#define CY_VD_INT_MASK ((uint32) (0x01u)) /******************************************************************************* @@ -435,7 +438,7 @@ void CySetScPumps(uint8 enable) ; #if defined(__ARMCC_VERSION) #define CY_SYS_ISB __isb(0x0f) #else /* ASM for GCC & IAR */ - #define CY_SYS_ISB asm volatile ("isb \n") + #define CY_SYS_ISB __asm volatile ("isb \n") #endif /* (__ARMCC_VERSION) */ #endif /* (CY_PSOC5) */ @@ -805,8 +808,7 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyAssert -******************************************************************************** -* Summary: +****************************************************************************//** * The macro that evaluates the expression and if it is false (evaluates to 0) * then the processor is halted. * @@ -816,11 +818,7 @@ void CySetScPumps(uint8 enable) ; * defined by default for a Release build setting and not defined for a Debug * build setting. * -* Parameters: -* expr: Logical expression. Asserts if false. -* -* Return: -* None +* \param expr: Logical expression. Asserts if false. * *******************************************************************************/ #if !defined(NDEBUG) @@ -907,6 +905,7 @@ void CySetScPumps(uint8 enable) ; #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u)) #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu)) + #define CY_SYS_SYST_CVR_CNT_MASK ((uint32) (0x00FFFFFFu)) #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u)) #endif /* (CY_PSOC5) */ @@ -966,32 +965,22 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntEnable - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Enables the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number * *******************************************************************************/ #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) /******************************************************************************* * Macro Name: CyIntDisable - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Disables the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number. * *******************************************************************************/ #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) @@ -999,16 +988,11 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntSetPending - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Forces the specified interrupt number to be pending. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number. * *******************************************************************************/ #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) @@ -1016,16 +1000,11 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntClearPending - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Clears any pending interrupt for the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number. * *******************************************************************************/ #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) @@ -1036,16 +1015,11 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntEnable - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Enables the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number * *******************************************************************************/ #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ @@ -1054,16 +1028,11 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntDisable - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Disables the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number. * *******************************************************************************/ #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ @@ -1072,16 +1041,11 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntSetPending - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Forces the specified interrupt number to be pending. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number. * *******************************************************************************/ #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ @@ -1090,15 +1054,10 @@ void CySetScPumps(uint8 enable) ; /******************************************************************************* * Macro Name: CyIntClearPending - ******************************************************************************** - * Summary: + ****************************************************************************//** * Clears any pending interrupt for the specified interrupt number. * - * Parameters: - * number: Valid range [0-31]. Interrupt number. - * - * Return: - * None + * \param number: Valid range [0-31]. Interrupt number. * *******************************************************************************/ #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c old mode 100644 new mode 100755 index 2181161..c0a46b1 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c @@ -1,14 +1,14 @@ -/******************************************************************************* -* File Name: CySpc.c -* Version 4.20 +/***************************************************************************//** +* \file CySpc.c +* \version 5.50 * -* Description: -* Provides an API for the System Performance Component. -* The SPC functions are not meant to be called directly by the user -* application. +* \brief Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -64,16 +64,9 @@ uint8 SpcLockState = CY_SPC_UNLOCKED; /******************************************************************************* * Function Name: CySpcStart -******************************************************************************** -* Summary: +****************************************************************************//** * Starts the SPC. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CySpcStart(void) { @@ -90,16 +83,9 @@ void CySpcStart(void) /******************************************************************************* * Function Name: CySpcStop -******************************************************************************** -* Summary: +****************************************************************************//** * Stops the SPC. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CySpcStop(void) { @@ -116,18 +102,16 @@ void CySpcStop(void) /******************************************************************************* * Function Name: CySpcReadData -******************************************************************************** -* Summary: +****************************************************************************//** * Reads data from the SPC. * -* Parameters: -* uint8 buffer: +* \param uint8 buffer: * Address to store data read. * -* uint8 size: +* \param uint8 size: * Number of bytes to read from the SPC. * -* Return: +* \return * uint8: * The number of bytes read from the SPC. * @@ -151,24 +135,22 @@ uint8 CySpcReadData(uint8 buffer[], uint8 size) /******************************************************************************* * Function Name: CySpcLoadMultiByte -******************************************************************************** -* Summary: +****************************************************************************//** * Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. * -* Parameters: -* uint8 array: +* \param uint8 array: * Id of the array. * -* uint16 address: +* \param uint16 address: * Flash/eeprom addrress * -* uint8* buffer: +* \param uint8* buffer: * Data to load to the row latch * -* uint16 number: +* \param uint16 number: * Number bytes to load. * -* Return: +* \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED @@ -227,8 +209,7 @@ cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], u /******************************************************************************* * Function Name: CySpcLoadRow -******************************************************************************** -* Summary: +****************************************************************************//** * Loads a row of data into the row latch of a Flash/EEPROM array. * * The buffer pointer should point to the data that should be written to the @@ -236,20 +217,19 @@ cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], u * responsibility to prepare data: the preserved data are copied from flash into * array with the modified data. * -* Parameters: -* uint8 array: +* \param uint8 array: * Id of the array. * -* uint8* buffer: +* \param uint8* buffer: * Data to be loaded to the row latch * -* uint8 size: +* \param uint8 size: * The number of data bytes that the SPC expects to be written. Depends on the * type of the array and, if the array is Flash, whether ECC is being enabled * or not. There are following values: flash row latch size with ECC enabled, * flash row latch size with ECC disabled and EEPROM row latch size. * -* Return: +* \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED @@ -293,31 +273,29 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) /******************************************************************************* * Function Name: CySpcLoadRowFull -******************************************************************************** -* Summary: +****************************************************************************//** * Loads a row of data into the row latch of a Flash/EEPROM array. * * The only data that are going to be changed should be passed. The function * will handle unmodified data preservation based on DWR settings and input * parameters. * -* Parameters: -* uint8 array: +* \param uint8 array: * Id of the array. * -* uint16 row: +* \param uint16 row: * Flash row number to be loaded. * -* uint8* buffer: +* \param uint8* buffer: * Data to be loaded to the row latch * -* uint8 size: +* \param uint8 size: * The number of data bytes that the SPC expects to be written. Depends on the * type of the array and, if the array is Flash, whether ECC is being enabled * or not. There are following values: flash row latch size with ECC enabled, * flash row latch size with ECC disabled and EEPROM row latch size. * -* Return: +* \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED @@ -436,26 +414,24 @@ cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 /******************************************************************************* * Function Name: CySpcWriteRow -******************************************************************************** -* Summary: +****************************************************************************//** * Erases then programs a row in Flash/EEPROM with data in row latch. * -* Parameters: -* uint8 array: +* \param uint8 array: * Id of the array. * -* uint16 address: +* \param uint16 address: * flash/eeprom addrress * -* uint8 tempPolarity: +* \param uint8 tempPolarity: * temperature polarity. -* 1: the Temp Magnitude is interpreted as a positive value -* 0: the Temp Magnitude is interpreted as a negative value +* \param 1: the Temp Magnitude is interpreted as a positive value +* \param 0: the Temp Magnitude is interpreted as a negative value * -* uint8 tempMagnitude: +* \param uint8 tempMagnitude: * temperature magnitude. * -* Return: +* \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED @@ -498,18 +474,16 @@ cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 te /******************************************************************************* * Function Name: CySpcEraseSector -******************************************************************************** -* Summary: +****************************************************************************//** * Erases all data in the addressed sector (block of 64 rows). * -* Parameters: -* uint8 array: +* \param uint8 array: * Id of the array. * -* uint8 sectorNumber: +* \param uint8 sectorNumber: * Zero based sector number within Flash/EEPROM array * -* Return: +* \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED @@ -548,23 +522,21 @@ cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) /******************************************************************************* * Function Name: CySpcGetTemp -******************************************************************************** -* Summary: +****************************************************************************//** * Returns the internal die temperature * -* Parameters: -* uint8 numSamples: +* \param uint8 numSamples: * Number of samples. Valid values are 1-5, resulting in 2 - 32 samples * respectively. * -* uint16 timerPeriod: +* \param uint16 timerPeriod: * Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits * of 16 bit values are ignored. * -* uint8 clkDivSelect: +* \param uint8 clkDivSelect: * ADC ACLK clock divide value. Valid values are 2 - 225. * -* Return: +* \return * CYRET_STARTED * CYRET_CANCELED * CYRET_LOCKED @@ -602,15 +574,11 @@ cystatus CySpcGetTemp(uint8 numSamples) /******************************************************************************* * Function Name: CySpcLock -******************************************************************************** -* Summary: +****************************************************************************//** * Locks the SPC so it can not be used by someone else: * - Saves wait-pipeline enable state and enable pipeline (PSoC5) * -* Parameters: -* Note -* -* Return: +* \return * CYRET_SUCCESS - if the resource was free. * CYRET_LOCKED - if the SPC is in use. * @@ -655,17 +623,10 @@ cystatus CySpcLock(void) /******************************************************************************* * Function Name: CySpcUnlock -******************************************************************************** -* Summary: +****************************************************************************//** * Unlocks the SPC so it can be used by someone else: * - Restores wait-pipeline enable state (PSoC5) * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CySpcUnlock(void) { @@ -701,14 +662,10 @@ void CySpcUnlock(void) /******************************************************************************* * Function Name: CySpcGetAlgorithm -******************************************************************************** -* Summary: +****************************************************************************//** * Downloads SPC algorithm from SPC SROM into SRAM. * -* Parameters: -* None -* -* Return: +* \return * CYRET_STARTED * CYRET_LOCKED * diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h old mode 100644 new mode 100755 index 36f764e..1979366 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h @@ -1,14 +1,14 @@ -/******************************************************************************* -* File Name: CySpc.c -* Version 4.20 +/***************************************************************************//** +* \file CySpc.c +* \version 5.50 * -* Description: -* Provides definitions for the System Performance Component API. +* \brief Provides definitions for the System Performance Component API. * The SPC functions are not meant to be called directly by the user * application. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c old mode 100644 new mode 100755 index b0b3ba7..575ecee --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LED1.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: LED1_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_Write *******************************************************************************/ -void LED1_Write(uint8 value) +void LED1_Write(uint8 value) { uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK)); LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK); @@ -45,28 +63,31 @@ void LED1_Write(uint8 value) /******************************************************************************* * Function Name: LED1_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* LED1_DM_STRONG Strong Drive -* LED1_DM_OD_HI Open Drain, Drives High -* LED1_DM_OD_LO Open Drain, Drives Low -* LED1_DM_RES_UP Resistive Pull Up -* LED1_DM_RES_DWN Resistive Pull Down -* LED1_DM_RES_UPDWN Resistive Pull Up/Down -* LED1_DM_DIG_HIZ High Impedance Digital -* LED1_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_SetDriveMode *******************************************************************************/ -void LED1_SetDriveMode(uint8 mode) +void LED1_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(LED1_0, mode); } @@ -74,23 +95,22 @@ void LED1_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: LED1_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro LED1_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_Read *******************************************************************************/ -uint8 LED1_Read(void) +uint8 LED1_Read(void) { return (LED1_PS & LED1_MASK) >> LED1_SHIFT; } @@ -98,42 +118,102 @@ uint8 LED1_Read(void) /******************************************************************************* * Function Name: LED1_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED1_Read() API because the +* LED1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_ReadDataReg *******************************************************************************/ -uint8 LED1_ReadDataReg(void) +uint8 LED1_ReadDataReg(void) { return (LED1_DR & LED1_MASK) >> LED1_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(LED1_INTSTAT) /******************************************************************************* - * Function Name: LED1_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: LED1_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use LED1_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - LED1_0_INTR (First pin in the list) + * - LED1_1_INTR (Second pin in the list) + * - ... + * - LED1_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet LED1_SUT.c usage_LED1_SetInterruptMode *******************************************************************************/ - uint8 LED1_ClearInterrupt(void) + void LED1_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & LED1_0_INTR) != 0u) + { + LED1_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: LED1_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet LED1_SUT.c usage_LED1_ClearInterrupt + *******************************************************************************/ + uint8 LED1_ClearInterrupt(void) { return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h old mode 100644 new mode 100755 index 21cf503..df40da1 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: LED1.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "LED1_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void LED1_Write(uint8 value) ; -void LED1_SetDriveMode(uint8 mode) ; -uint8 LED1_ReadDataReg(void) ; -uint8 LED1_Read(void) ; -uint8 LED1_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void LED1_Write(uint8 value); +void LED1_SetDriveMode(uint8 mode); +uint8 LED1_ReadDataReg(void); +uint8 LED1_Read(void); +void LED1_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED1_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define LED1_DM_RES_UP PIN_DM_RES_UP -#define LED1_DM_RES_DWN PIN_DM_RES_DWN -#define LED1_DM_OD_LO PIN_DM_OD_LO -#define LED1_DM_OD_HI PIN_DM_OD_HI -#define LED1_DM_STRONG PIN_DM_STRONG -#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED1_SetDriveMode() function. + * @{ + */ + #define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define LED1_DM_RES_UP PIN_DM_RES_UP + #define LED1_DM_RES_DWN PIN_DM_RES_DWN + #define LED1_DM_OD_LO PIN_DM_OD_LO + #define LED1_DM_OD_HI PIN_DM_OD_HI + #define LED1_DM_STRONG PIN_DM_STRONG + #define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define LED1_MASK LED1__MASK #define LED1_SHIFT LED1__SHIFT #define LED1_WIDTH 1u +/* Interrupt constants */ +#if defined(LED1__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED1_SetInterruptMode() function. + * @{ + */ + #define LED1_INTR_NONE (uint16)(0x0000u) + #define LED1_INTR_RISING (uint16)(0x0001u) + #define LED1_INTR_FALLING (uint16)(0x0002u) + #define LED1_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define LED1_INTR_MASK (0x01u) +#endif /* (LED1__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 LED1_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(LED1__SIO_CFG) + #define LED1_SIO_HYST_EN (* (reg8 *) LED1__SIO_HYST_EN) + #define LED1_SIO_REG_HIFREQ (* (reg8 *) LED1__SIO_REG_HIFREQ) + #define LED1_SIO_CFG (* (reg8 *) LED1__SIO_CFG) + #define LED1_SIO_DIFF (* (reg8 *) LED1__SIO_DIFF) +#endif /* (LED1__SIO_CFG) */ -#if defined(LED1__INTSTAT) /* Interrupt Registers */ - - #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT) - #define LED1_SNAP (* (reg8 *) LED1__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(LED1__INTSTAT) + #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT) + #define LED1_SNAP (* (reg8 *) LED1__SNAP) + + #define LED1_0_INTTYPE_REG (* (reg8 *) LED1__0__INTTYPE) +#endif /* (LED1__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h old mode 100644 new mode 100755 index 3e5d113..f608b21 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: LED1.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define LED1_0 (LED1__0__PC) +#define LED1_0 (LED1__0__PC) +#define LED1_0_INTR ((uint16)((uint16)0x0001u << LED1__0__SHIFT)) + +#define LED1_INTR_ALL ((uint16)(LED1_0_INTR)) #endif /* End Pins LED1_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c old mode 100644 new mode 100755 index eadf7a3..c9d441e --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_CTL_PHASE.c -* Version 1.70 +* Version 1.80 * * Description: * This file contains API to enable firmware control of a Control Register. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -16,8 +16,10 @@ #include "SCSI_CTL_PHASE.h" -#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ +/* Check for removal by optimization */ +#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) + /******************************************************************************* * Function Name: SCSI_CTL_PHASE_Write ******************************************************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h old mode 100644 new mode 100755 index 00cbb37..f974855 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_CTL_PHASE.h -* Version 1.70 +* Version 1.80 * * Description: * This file containts Control Register function prototypes and register defines @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,6 +19,18 @@ #include "cytypes.h" + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_CTL_PHASE_BACKUP_STRUCT; + /*************************************** * Function Prototypes @@ -27,6 +39,11 @@ void SCSI_CTL_PHASE_Write(uint8 control) ; uint8 SCSI_CTL_PHASE_Read(void) ; +void SCSI_CTL_PHASE_SaveConfig(void) ; +void SCSI_CTL_PHASE_RestoreConfig(void) ; +void SCSI_CTL_PHASE_Sleep(void) ; +void SCSI_CTL_PHASE_Wakeup(void) ; + /*************************************** * Registers diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c new file mode 100755 index 0000000..f20c66d --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_CTL_PHASE_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_CTL_PHASE.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) + +static SCSI_CTL_PHASE_BACKUP_STRUCT SCSI_CTL_PHASE_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CTL_PHASE_SaveConfig(void) +{ + SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_CTL_PHASE_RestoreConfig(void) +{ + SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CTL_PHASE_Sleep(void) +{ + SCSI_CTL_PHASE_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CTL_PHASE_Wakeup(void) +{ + SCSI_CTL_PHASE_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c old mode 100644 new mode 100755 index 2fc815b..593f8c3 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Filtered.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware to read the value of a Status @@ -9,7 +9,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -103,7 +103,7 @@ void SCSI_Filtered_InterruptDisable(void) void SCSI_Filtered_WriteMask(uint8 mask) { #if(SCSI_Filtered_INPUTS < 8u) - mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u); + mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u); #endif /* End SCSI_Filtered_INPUTS < 8u */ SCSI_Filtered_Status_Mask = mask; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h old mode 100644 new mode 100755 index 759a85b..87326f5 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Filtered.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Status Register function prototypes and register defines @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -20,6 +20,18 @@ #include "cytypes.h" #include "CyLib.h" + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 statusState; + +} SCSI_Filtered_BACKUP_STRUCT; + /*************************************** * Function Prototypes diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c old mode 100644 new mode 100755 index 8c80437..b447184 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Glitch_Ctl.c -* Version 1.70 +* Version 1.80 * * Description: * This file contains API to enable firmware control of a Control Register. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -16,8 +16,10 @@ #include "SCSI_Glitch_Ctl.h" -#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ +/* Check for removal by optimization */ +#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) + /******************************************************************************* * Function Name: SCSI_Glitch_Ctl_Write ******************************************************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h old mode 100644 new mode 100755 index bcd7650..d6c0d24 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Glitch_Ctl.h -* Version 1.70 +* Version 1.80 * * Description: * This file containts Control Register function prototypes and register defines @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,6 +19,18 @@ #include "cytypes.h" + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_Glitch_Ctl_BACKUP_STRUCT; + /*************************************** * Function Prototypes @@ -27,6 +39,11 @@ void SCSI_Glitch_Ctl_Write(uint8 control) ; uint8 SCSI_Glitch_Ctl_Read(void) ; +void SCSI_Glitch_Ctl_SaveConfig(void) ; +void SCSI_Glitch_Ctl_RestoreConfig(void) ; +void SCSI_Glitch_Ctl_Sleep(void) ; +void SCSI_Glitch_Ctl_Wakeup(void) ; + /*************************************** * Registers diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c new file mode 100755 index 0000000..47fc7c0 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Glitch_Ctl.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) + +static SCSI_Glitch_Ctl_BACKUP_STRUCT SCSI_Glitch_Ctl_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_SaveConfig(void) +{ + SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_RestoreConfig(void) +{ + SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Sleep(void) +{ + SCSI_Glitch_Ctl_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Wakeup(void) +{ + SCSI_Glitch_Ctl_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h old mode 100644 new mode 100755 index 8b2dbe8..47b5520 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_In_DBx.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,28 +22,59 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC) -#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC) -#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC) -#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC) -#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC) -#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC) -#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC) -#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC) +#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC) +#define SCSI_In_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT)) -#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC) -#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC) -#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC) -#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC) -#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC) -#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC) -#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC) -#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC) +#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC) +#define SCSI_In_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT)) + +#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC) +#define SCSI_In_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT)) + +#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC) +#define SCSI_In_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT)) + +#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC) +#define SCSI_In_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT)) + +#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC) +#define SCSI_In_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT)) + +#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC) +#define SCSI_In_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT)) + +#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC) +#define SCSI_In_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT)) + +#define SCSI_In_DBx_INTR_ALL ((uint16)(SCSI_In_DBx_0_INTR| SCSI_In_DBx_1_INTR| SCSI_In_DBx_2_INTR| SCSI_In_DBx_3_INTR| SCSI_In_DBx_4_INTR| SCSI_In_DBx_5_INTR| SCSI_In_DBx_6_INTR| SCSI_In_DBx_7_INTR)) +#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC) +#define SCSI_In_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT)) + +#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC) +#define SCSI_In_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT)) + +#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC) +#define SCSI_In_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT)) + +#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC) +#define SCSI_In_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT)) + +#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC) +#define SCSI_In_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT)) + +#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC) +#define SCSI_In_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT)) + +#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC) +#define SCSI_In_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT)) + +#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC) +#define SCSI_In_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT)) #endif /* End Pins SCSI_In_DBx_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h old mode 100644 new mode 100755 index 7f4d0f7..81fff1b --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_In.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,22 +22,41 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_In_0 (SCSI_In__0__PC) -#define SCSI_In_1 (SCSI_In__1__PC) -#define SCSI_In_2 (SCSI_In__2__PC) -#define SCSI_In_3 (SCSI_In__3__PC) -#define SCSI_In_4 (SCSI_In__4__PC) +#define SCSI_In_0 (SCSI_In__0__PC) +#define SCSI_In_0_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT)) -#define SCSI_In_DBP (SCSI_In__DBP__PC) -#define SCSI_In_MSG (SCSI_In__MSG__PC) -#define SCSI_In_CD (SCSI_In__CD__PC) -#define SCSI_In_REQ (SCSI_In__REQ__PC) -#define SCSI_In_IO (SCSI_In__IO__PC) +#define SCSI_In_1 (SCSI_In__1__PC) +#define SCSI_In_1_INTR ((uint16)((uint16)0x0001u << SCSI_In__1__SHIFT)) + +#define SCSI_In_2 (SCSI_In__2__PC) +#define SCSI_In_2_INTR ((uint16)((uint16)0x0001u << SCSI_In__2__SHIFT)) + +#define SCSI_In_3 (SCSI_In__3__PC) +#define SCSI_In_3_INTR ((uint16)((uint16)0x0001u << SCSI_In__3__SHIFT)) + +#define SCSI_In_4 (SCSI_In__4__PC) +#define SCSI_In_4_INTR ((uint16)((uint16)0x0001u << SCSI_In__4__SHIFT)) + +#define SCSI_In_INTR_ALL ((uint16)(SCSI_In_0_INTR| SCSI_In_1_INTR| SCSI_In_2_INTR| SCSI_In_3_INTR| SCSI_In_4_INTR)) +#define SCSI_In_DBP (SCSI_In__DBP__PC) +#define SCSI_In_DBP_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT)) + +#define SCSI_In_MSG (SCSI_In__MSG__PC) +#define SCSI_In_MSG_INTR ((uint16)((uint16)0x0001u << SCSI_In__1__SHIFT)) + +#define SCSI_In_CD (SCSI_In__CD__PC) +#define SCSI_In_CD_INTR ((uint16)((uint16)0x0001u << SCSI_In__2__SHIFT)) + +#define SCSI_In_REQ (SCSI_In__REQ__PC) +#define SCSI_In_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_In__3__SHIFT)) + +#define SCSI_In_IO (SCSI_In__IO__PC) +#define SCSI_In_IO_INTR ((uint16)((uint16)0x0001u << SCSI_In__4__SHIFT)) #endif /* End Pins SCSI_In_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h old mode 100644 new mode 100755 index 2bf1147..a6c3ff1 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_Noise.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,22 +22,41 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_Noise_0 (SCSI_Noise__0__PC) -#define SCSI_Noise_1 (SCSI_Noise__1__PC) -#define SCSI_Noise_2 (SCSI_Noise__2__PC) -#define SCSI_Noise_3 (SCSI_Noise__3__PC) -#define SCSI_Noise_4 (SCSI_Noise__4__PC) +#define SCSI_Noise_0 (SCSI_Noise__0__PC) +#define SCSI_Noise_0_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT)) -#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC) -#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC) -#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC) -#define SCSI_Noise_RST (SCSI_Noise__RST__PC) -#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC) +#define SCSI_Noise_1 (SCSI_Noise__1__PC) +#define SCSI_Noise_1_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT)) + +#define SCSI_Noise_2 (SCSI_Noise__2__PC) +#define SCSI_Noise_2_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT)) + +#define SCSI_Noise_3 (SCSI_Noise__3__PC) +#define SCSI_Noise_3_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT)) + +#define SCSI_Noise_4 (SCSI_Noise__4__PC) +#define SCSI_Noise_4_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT)) + +#define SCSI_Noise_INTR_ALL ((uint16)(SCSI_Noise_0_INTR| SCSI_Noise_1_INTR| SCSI_Noise_2_INTR| SCSI_Noise_3_INTR| SCSI_Noise_4_INTR)) +#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC) +#define SCSI_Noise_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT)) + +#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC) +#define SCSI_Noise_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT)) + +#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC) +#define SCSI_Noise_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT)) + +#define SCSI_Noise_RST (SCSI_Noise__RST__PC) +#define SCSI_Noise_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT)) + +#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC) +#define SCSI_Noise_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT)) #endif /* End Pins SCSI_Noise_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c old mode 100644 new mode 100755 index 2fa26a4..85a089e --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Out_Bits.c -* Version 1.70 +* Version 1.80 * * Description: * This file contains API to enable firmware control of a Control Register. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -16,8 +16,10 @@ #include "SCSI_Out_Bits.h" -#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) + /******************************************************************************* * Function Name: SCSI_Out_Bits_Write ******************************************************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h old mode 100644 new mode 100755 index 13df446..94ea62a --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Out_Bits.h -* Version 1.70 +* Version 1.80 * * Description: * This file containts Control Register function prototypes and register defines @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,6 +19,18 @@ #include "cytypes.h" + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_Out_Bits_BACKUP_STRUCT; + /*************************************** * Function Prototypes @@ -27,6 +39,11 @@ void SCSI_Out_Bits_Write(uint8 control) ; uint8 SCSI_Out_Bits_Read(void) ; +void SCSI_Out_Bits_SaveConfig(void) ; +void SCSI_Out_Bits_RestoreConfig(void) ; +void SCSI_Out_Bits_Sleep(void) ; +void SCSI_Out_Bits_Wakeup(void) ; + /*************************************** * Registers diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c new file mode 100755 index 0000000..04f06a0 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_Out_Bits_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Out_Bits.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) + +static SCSI_Out_Bits_BACKUP_STRUCT SCSI_Out_Bits_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Bits_SaveConfig(void) +{ + SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_Out_Bits_RestoreConfig(void) +{ + SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Bits_Sleep(void) +{ + SCSI_Out_Bits_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Bits_Wakeup(void) +{ + SCSI_Out_Bits_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c old mode 100644 new mode 100755 index 6191598..ecba124 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Out_Ctl.c -* Version 1.70 +* Version 1.80 * * Description: * This file contains API to enable firmware control of a Control Register. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -16,8 +16,10 @@ #include "SCSI_Out_Ctl.h" -#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) + /******************************************************************************* * Function Name: SCSI_Out_Ctl_Write ******************************************************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h old mode 100644 new mode 100755 index 669ebf5..e473a95 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Out_Ctl.h -* Version 1.70 +* Version 1.80 * * Description: * This file containts Control Register function prototypes and register defines @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,6 +19,18 @@ #include "cytypes.h" + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_Out_Ctl_BACKUP_STRUCT; + /*************************************** * Function Prototypes @@ -27,6 +39,11 @@ void SCSI_Out_Ctl_Write(uint8 control) ; uint8 SCSI_Out_Ctl_Read(void) ; +void SCSI_Out_Ctl_SaveConfig(void) ; +void SCSI_Out_Ctl_RestoreConfig(void) ; +void SCSI_Out_Ctl_Sleep(void) ; +void SCSI_Out_Ctl_Wakeup(void) ; + /*************************************** * Registers diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c new file mode 100755 index 0000000..abc42cf --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_Out_Ctl_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Out_Ctl.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) + +static SCSI_Out_Ctl_BACKUP_STRUCT SCSI_Out_Ctl_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Ctl_SaveConfig(void) +{ + SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_Out_Ctl_RestoreConfig(void) +{ + SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Ctl_Sleep(void) +{ + SCSI_Out_Ctl_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Ctl_Wakeup(void) +{ + SCSI_Out_Ctl_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h old mode 100644 new mode 100755 index 7b23252..74f7c3b --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_Out_DBx.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,28 +22,59 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC) -#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC) -#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC) -#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC) -#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC) -#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC) -#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC) -#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC) +#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC) +#define SCSI_Out_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT)) -#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC) -#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC) -#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC) -#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC) -#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC) -#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC) -#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC) -#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC) +#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC) +#define SCSI_Out_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT)) + +#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC) +#define SCSI_Out_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT)) + +#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC) +#define SCSI_Out_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT)) + +#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC) +#define SCSI_Out_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT)) + +#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC) +#define SCSI_Out_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT)) + +#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC) +#define SCSI_Out_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT)) + +#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC) +#define SCSI_Out_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT)) + +#define SCSI_Out_DBx_INTR_ALL ((uint16)(SCSI_Out_DBx_0_INTR| SCSI_Out_DBx_1_INTR| SCSI_Out_DBx_2_INTR| SCSI_Out_DBx_3_INTR| SCSI_Out_DBx_4_INTR| SCSI_Out_DBx_5_INTR| SCSI_Out_DBx_6_INTR| SCSI_Out_DBx_7_INTR)) +#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC) +#define SCSI_Out_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT)) + +#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC) +#define SCSI_Out_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT)) + +#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC) +#define SCSI_Out_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT)) + +#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC) +#define SCSI_Out_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT)) + +#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC) +#define SCSI_Out_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT)) + +#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC) +#define SCSI_Out_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT)) + +#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC) +#define SCSI_Out_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT)) + +#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC) +#define SCSI_Out_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT)) #endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h old mode 100644 new mode 100755 index f711499..6a1c05a --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_Out.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,32 +22,71 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_Out_0 (SCSI_Out__0__PC) -#define SCSI_Out_1 (SCSI_Out__1__PC) -#define SCSI_Out_2 (SCSI_Out__2__PC) -#define SCSI_Out_3 (SCSI_Out__3__PC) -#define SCSI_Out_4 (SCSI_Out__4__PC) -#define SCSI_Out_5 (SCSI_Out__5__PC) -#define SCSI_Out_6 (SCSI_Out__6__PC) -#define SCSI_Out_7 (SCSI_Out__7__PC) -#define SCSI_Out_8 (SCSI_Out__8__PC) -#define SCSI_Out_9 (SCSI_Out__9__PC) +#define SCSI_Out_0 (SCSI_Out__0__PC) +#define SCSI_Out_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT)) -#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC) -#define SCSI_Out_ATN (SCSI_Out__ATN__PC) -#define SCSI_Out_BSY (SCSI_Out__BSY__PC) -#define SCSI_Out_ACK (SCSI_Out__ACK__PC) -#define SCSI_Out_RST (SCSI_Out__RST__PC) -#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC) -#define SCSI_Out_SEL (SCSI_Out__SEL__PC) -#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC) -#define SCSI_Out_REQ (SCSI_Out__REQ__PC) -#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC) +#define SCSI_Out_1 (SCSI_Out__1__PC) +#define SCSI_Out_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT)) + +#define SCSI_Out_2 (SCSI_Out__2__PC) +#define SCSI_Out_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT)) + +#define SCSI_Out_3 (SCSI_Out__3__PC) +#define SCSI_Out_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT)) + +#define SCSI_Out_4 (SCSI_Out__4__PC) +#define SCSI_Out_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT)) + +#define SCSI_Out_5 (SCSI_Out__5__PC) +#define SCSI_Out_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT)) + +#define SCSI_Out_6 (SCSI_Out__6__PC) +#define SCSI_Out_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT)) + +#define SCSI_Out_7 (SCSI_Out__7__PC) +#define SCSI_Out_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT)) + +#define SCSI_Out_8 (SCSI_Out__8__PC) +#define SCSI_Out_8_INTR ((uint16)((uint16)0x0001u << SCSI_Out__8__SHIFT)) + +#define SCSI_Out_9 (SCSI_Out__9__PC) +#define SCSI_Out_9_INTR ((uint16)((uint16)0x0001u << SCSI_Out__9__SHIFT)) + +#define SCSI_Out_INTR_ALL ((uint16)(SCSI_Out_0_INTR| SCSI_Out_1_INTR| SCSI_Out_2_INTR| SCSI_Out_3_INTR| SCSI_Out_4_INTR| SCSI_Out_5_INTR| SCSI_Out_6_INTR| SCSI_Out_7_INTR| SCSI_Out_8_INTR| SCSI_Out_9_INTR)) +#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC) +#define SCSI_Out_DBP_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT)) + +#define SCSI_Out_ATN (SCSI_Out__ATN__PC) +#define SCSI_Out_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT)) + +#define SCSI_Out_BSY (SCSI_Out__BSY__PC) +#define SCSI_Out_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT)) + +#define SCSI_Out_ACK (SCSI_Out__ACK__PC) +#define SCSI_Out_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT)) + +#define SCSI_Out_RST (SCSI_Out__RST__PC) +#define SCSI_Out_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT)) + +#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC) +#define SCSI_Out_MSG_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT)) + +#define SCSI_Out_SEL (SCSI_Out__SEL__PC) +#define SCSI_Out_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT)) + +#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC) +#define SCSI_Out_CD_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT)) + +#define SCSI_Out_REQ (SCSI_Out__REQ__PC) +#define SCSI_Out_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_Out__8__SHIFT)) + +#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC) +#define SCSI_Out_IO_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__9__SHIFT)) #endif /* End Pins SCSI_Out_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c old mode 100644 new mode 100755 index 8d35a48..de05e37 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Parity_Error.c -* Version 1.80 +* Version 1.90 * * Description: * This file contains API to enable firmware to read the value of a Status @@ -9,7 +9,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -103,7 +103,7 @@ void SCSI_Parity_Error_InterruptDisable(void) void SCSI_Parity_Error_WriteMask(uint8 mask) { #if(SCSI_Parity_Error_INPUTS < 8u) - mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u); + mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u); #endif /* End SCSI_Parity_Error_INPUTS < 8u */ SCSI_Parity_Error_Status_Mask = mask; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h old mode 100644 new mode 100755 index d03aed7..532aff3 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SCSI_Parity_Error.h -* Version 1.80 +* Version 1.90 * * Description: * This file containts Status Register function prototypes and register defines @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -20,6 +20,18 @@ #include "cytypes.h" #include "CyLib.h" + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 statusState; + +} SCSI_Parity_Error_BACKUP_STRUCT; + /*************************************** * Function Prototypes diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c index 3ac6cea..431f527 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SDCard.c -* Version 2.40 +* Version 2.50 * * Description: * This file provides all API functionality of the SPI Master component. @@ -9,7 +9,7 @@ * None. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -18,14 +18,14 @@ #include "SDCard_PVT.h" #if(SDCard_TX_SOFTWARE_BUF_ENABLED) - volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u}; + volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE]; volatile uint8 SDCard_txBufferFull; volatile uint8 SDCard_txBufferRead; volatile uint8 SDCard_txBufferWrite; #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ #if(SDCard_RX_SOFTWARE_BUF_ENABLED) - volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u}; + volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE]; volatile uint8 SDCard_rxBufferFull; volatile uint8 SDCard_rxBufferRead; volatile uint8 SDCard_rxBufferWrite; @@ -523,7 +523,7 @@ void SDCard_WriteTxData(uint8 txData) if((SDCard_txBufferRead == SDCard_txBufferWrite) && (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))) { - /* Add directly to the TX FIFO */ + /* Put data element into the TX FIFO */ CY_SET_REG8(SDCard_TXDATA_PTR, txData); } else @@ -553,13 +553,12 @@ void SDCard_WriteTxData(uint8 txData) SDCard_EnableTxInt(); #else - + /* Wait until TX FIFO has a place */ while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL)) { - ; /* Wait for room in FIFO */ } - /* Put byte in TX FIFO */ + /* Put data element into the TX FIFO */ CY_SET_REG8(SDCard_TXDATA_PTR, txData); #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h old mode 100644 new mode 100755 index adee8b3..6d566df --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SDCard.h -* Version 2.40 +* Version 2.50 * * Description: * Contains the function prototypes, constants and register definition @@ -10,7 +10,7 @@ * None * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -26,7 +26,7 @@ /* Check to see if required defines such as CY_PSOC5A are available */ /* They are defined starting with cy_boot v3.0 */ #if !defined (CY_PSOC5A) - #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later + #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later #endif /* (CY_PSOC5A) */ @@ -71,11 +71,6 @@ typedef struct { uint8 enableState; uint8 cntrPeriod; - #if(CY_UDB_V0) - uint8 saveSrTxIntMask; - uint8 saveSrRxIntMask; - #endif /* (CY_UDB_V0) */ - } SDCard_BACKUP_STRUCT; @@ -123,9 +118,9 @@ CY_ISR_PROTO(SDCard_TX_ISR); CY_ISR_PROTO(SDCard_RX_ISR); -/********************************** +/*************************************** * Variable with external linkage -**********************************/ +***************************************/ extern uint8 SDCard_initVar; @@ -181,7 +176,6 @@ extern uint8 SDCard_initVar; /*************************************** * Registers ***************************************/ - #if(CY_PSOC3 || CY_PSOC5) #define SDCard_TXDATA_REG (* (reg8 *) \ SDCard_BSPIM_sR8_Dp_u0__F0_REG) @@ -199,7 +193,7 @@ extern uint8 SDCard_initVar; SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) #define SDCard_RXDATA_REG (* (reg16 *) \ SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) - #define SDCard_RXDATA_PTR ( (reg16 *) \ + #define SDCard_RXDATA_PTR ( (reg16 *) \ SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) #else #define SDCard_TXDATA_REG (* (reg8 *) \ @@ -236,9 +230,9 @@ extern uint8 SDCard_initVar; #define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) #define SDCard_CONTROL_REG (* (reg8 *) \ - SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) + SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG) #define SDCard_CONTROL_PTR ( (reg8 *) \ - SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG) + SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG) #define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) #define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) @@ -323,14 +317,10 @@ extern uint8 SDCard_initVar; /*************************************** -* Obsolete definitions +* The following code is DEPRECATED and +* should not be used in new projects. ***************************************/ -/* Following definitions are for version compatibility. -* They are obsolete in SPIM v2_30. -* Please do not use it in new projects -*/ - #define SDCard_WriteByte SDCard_WriteTxData #define SDCard_ReadByte SDCard_ReadRxData void SDCard_SetInterruptMode(uint8 intSrc) ; @@ -338,7 +328,6 @@ uint8 SDCard_ReadStatus(void) ; void SDCard_EnableInt(void) ; void SDCard_DisableInt(void) ; -/* Obsolete register names. Not to be used in new designs */ #define SDCard_TXDATA (SDCard_TXDATA_REG) #define SDCard_RXDATA (SDCard_RXDATA_REG) #define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG) @@ -362,11 +351,6 @@ void SDCard_DisableInt(void) ; SDCard_INT_ON_RX_OVER | \ SDCard_INT_ON_BYTE_COMP) -/* Following definitions are for version Compatibility. -* They are obsolete in SPIM v2_40. -* Please do not use it in new projects -*/ - #define SDCard_DataWidth (SDCard_DATA_WIDTH) #define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK) #define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c index d2e68ea..98cfe28 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SDCard_INT.c -* Version 2.40 +* Version 2.50 * * Description: * This file provides all Interrupt Service Routine (ISR) for the SPI Master @@ -10,7 +10,7 @@ * None. * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -18,6 +18,7 @@ #include "SDCard_PVT.h" + /* User code required at start of ISR */ /* `#START SDCard_ISR_START_DEF` */ @@ -54,11 +55,15 @@ CY_ISR(SDCard_TX_ISR) uint8 tmpStatus; #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + #ifdef SDCard_TX_ISR_ENTRY_CALLBACK + SDCard_TX_ISR_EntryCallback(); + #endif /* SDCard_TX_ISR_ENTRY_CALLBACK */ + /* User code required at start of ISR */ /* `#START SDCard_TX_ISR_START` */ /* `#END` */ - + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) /* Check if TX data buffer is not empty and there is space in TX FIFO */ while(SDCard_txBufferRead != SDCard_txBufferWrite) @@ -82,9 +87,9 @@ CY_ISR(SDCard_TX_ISR) SDCard_txBufferFull = 0u; } - /* Move data from the Buffer to the FIFO */ - CY_SET_REG8(SDCard_TXDATA_PTR, - SDCard_txBuffer[SDCard_txBufferRead]); + /* Put data element into the TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, + SDCard_txBuffer[SDCard_txBufferRead]); } else { @@ -104,6 +109,10 @@ CY_ISR(SDCard_TX_ISR) /* `#START SDCard_TX_ISR_END` */ /* `#END` */ + + #ifdef SDCard_TX_ISR_EXIT_CALLBACK + SDCard_TX_ISR_ExitCallback(); + #endif /* SDCard_TX_ISR_EXIT_CALLBACK */ } @@ -138,11 +147,15 @@ CY_ISR(SDCard_RX_ISR) uint8 rxData; #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + #ifdef SDCard_RX_ISR_ENTRY_CALLBACK + SDCard_RX_ISR_EntryCallback(); + #endif /* SDCard_RX_ISR_ENTRY_CALLBACK */ + /* User code required at start of ISR */ /* `#START SDCard_RX_ISR_START` */ /* `#END` */ - + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); @@ -184,6 +197,10 @@ CY_ISR(SDCard_RX_ISR) /* `#START SDCard_RX_ISR_END` */ /* `#END` */ + + #ifdef SDCard_RX_ISR_EXIT_CALLBACK + SDCard_RX_ISR_ExitCallback(); + #endif /* SDCard_RX_ISR_EXIT_CALLBACK */ } /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c index 8819841..86da007 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SDCard_PM.c -* Version 2.40 +* Version 2.50 * * Description: * This file contains the setup, control and status commands to support @@ -9,7 +9,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,10 +21,6 @@ static SDCard_BACKUP_STRUCT SDCard_backup = { SDCard_DISABLED, SDCard_BITCTR_INIT, - #if(CY_UDB_V0) - SDCard_TX_INIT_INTERRUPTS_MASK, - SDCard_RX_INIT_INTERRUPTS_MASK - #endif /* CY_UDB_V0 */ }; @@ -33,7 +29,7 @@ static SDCard_BACKUP_STRUCT SDCard_backup = ******************************************************************************** * * Summary: -* Saves SPIM configuration. +* Empty function. Included for consistency with other components. * * Parameters: * None. @@ -41,21 +37,10 @@ static SDCard_BACKUP_STRUCT SDCard_backup = * Return: * None. * -* Global Variables: -* SDCard_backup - modified when non-retention registers are saved. -* -* Reentrant: -* No. -* *******************************************************************************/ void SDCard_SaveConfig(void) { - /* Store Status Mask registers */ - #if(CY_UDB_V0) - SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG; - SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG; - SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG; - #endif /* (CY_UDB_V0) */ + } @@ -64,7 +49,7 @@ void SDCard_SaveConfig(void) ******************************************************************************** * * Summary: -* Restores SPIM configuration. +* Empty function. Included for consistency with other components. * * Parameters: * None. @@ -72,23 +57,10 @@ void SDCard_SaveConfig(void) * Return: * None. * -* Global Variables: -* SDCard_backup - used when non-retention registers are restored. -* -* Side Effects: -* If this API is called without first calling SaveConfig then in the following -* registers will be default values from Customizer: -* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG. -* *******************************************************************************/ void SDCard_RestoreConfig(void) { - /* Restore the data, saved by SaveConfig() function */ - #if(CY_UDB_V0) - SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod; - SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask); - SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask); - #endif /* (CY_UDB_V0) */ + } @@ -118,7 +90,6 @@ void SDCard_Sleep(void) SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED); SDCard_Stop(); - SDCard_SaveConfig(); } @@ -152,8 +123,6 @@ void SDCard_Sleep(void) *******************************************************************************/ void SDCard_Wakeup(void) { - SDCard_RestoreConfig(); - #if(SDCard_RX_SOFTWARE_BUF_ENABLED) SDCard_rxBufferFull = 0u; SDCard_rxBufferRead = 0u; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h index 7618531..74ab6f0 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: .h -* Version 2.40 +* Version 2.50 * * Description: * This private header file contains internal definitions for the SPIM @@ -9,7 +9,7 @@ * Note: * ******************************************************************************** -* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c old mode 100644 new mode 100755 index c721ce6..7c7c5ce --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_CD.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_CD_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_Write *******************************************************************************/ -void SD_CD_Write(uint8 value) +void SD_CD_Write(uint8 value) { uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK)); SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK); @@ -45,28 +63,31 @@ void SD_CD_Write(uint8 value) /******************************************************************************* * Function Name: SD_CD_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_CD_DM_STRONG Strong Drive -* SD_CD_DM_OD_HI Open Drain, Drives High -* SD_CD_DM_OD_LO Open Drain, Drives Low -* SD_CD_DM_RES_UP Resistive Pull Up -* SD_CD_DM_RES_DWN Resistive Pull Down -* SD_CD_DM_RES_UPDWN Resistive Pull Up/Down -* SD_CD_DM_DIG_HIZ High Impedance Digital -* SD_CD_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_SetDriveMode *******************************************************************************/ -void SD_CD_SetDriveMode(uint8 mode) +void SD_CD_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_CD_0, mode); } @@ -74,23 +95,22 @@ void SD_CD_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_CD_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_CD_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_Read *******************************************************************************/ -uint8 SD_CD_Read(void) +uint8 SD_CD_Read(void) { return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_CD_Read(void) /******************************************************************************* * Function Name: SD_CD_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_CD_Read() API because the +* SD_CD_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_ReadDataReg *******************************************************************************/ -uint8 SD_CD_ReadDataReg(void) +uint8 SD_CD_ReadDataReg(void) { return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_CD_INTSTAT) /******************************************************************************* - * Function Name: SD_CD_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_CD_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_CD_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_CD_0_INTR (First pin in the list) + * - SD_CD_1_INTR (Second pin in the list) + * - ... + * - SD_CD_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_CD_SUT.c usage_SD_CD_SetInterruptMode *******************************************************************************/ - uint8 SD_CD_ClearInterrupt(void) + void SD_CD_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_CD_0_INTR) != 0u) + { + SD_CD_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_CD_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_CD_SUT.c usage_SD_CD_ClearInterrupt + *******************************************************************************/ + uint8 SD_CD_ClearInterrupt(void) { return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h old mode 100644 new mode 100755 index 3ad98a3..7c46ef5 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_CD.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_CD_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_CD_Write(uint8 value) ; -void SD_CD_SetDriveMode(uint8 mode) ; -uint8 SD_CD_ReadDataReg(void) ; -uint8 SD_CD_Read(void) ; -uint8 SD_CD_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_CD_Write(uint8 value); +void SD_CD_SetDriveMode(uint8 mode); +uint8 SD_CD_ReadDataReg(void); +uint8 SD_CD_Read(void); +void SD_CD_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_CD_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_CD_DM_RES_UP PIN_DM_RES_UP -#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN -#define SD_CD_DM_OD_LO PIN_DM_OD_LO -#define SD_CD_DM_OD_HI PIN_DM_OD_HI -#define SD_CD_DM_STRONG PIN_DM_STRONG -#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_CD_SetDriveMode() function. + * @{ + */ + #define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_CD_DM_RES_UP PIN_DM_RES_UP + #define SD_CD_DM_RES_DWN PIN_DM_RES_DWN + #define SD_CD_DM_OD_LO PIN_DM_OD_LO + #define SD_CD_DM_OD_HI PIN_DM_OD_HI + #define SD_CD_DM_STRONG PIN_DM_STRONG + #define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_CD_MASK SD_CD__MASK #define SD_CD_SHIFT SD_CD__SHIFT #define SD_CD_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_CD__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_CD_SetInterruptMode() function. + * @{ + */ + #define SD_CD_INTR_NONE (uint16)(0x0000u) + #define SD_CD_INTR_RISING (uint16)(0x0001u) + #define SD_CD_INTR_FALLING (uint16)(0x0002u) + #define SD_CD_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_CD_INTR_MASK (0x01u) +#endif /* (SD_CD__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_CD_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_CD__SIO_CFG) + #define SD_CD_SIO_HYST_EN (* (reg8 *) SD_CD__SIO_HYST_EN) + #define SD_CD_SIO_REG_HIFREQ (* (reg8 *) SD_CD__SIO_REG_HIFREQ) + #define SD_CD_SIO_CFG (* (reg8 *) SD_CD__SIO_CFG) + #define SD_CD_SIO_DIFF (* (reg8 *) SD_CD__SIO_DIFF) +#endif /* (SD_CD__SIO_CFG) */ -#if defined(SD_CD__INTSTAT) /* Interrupt Registers */ - - #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT) - #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_CD__INTSTAT) + #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT) + #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP) + + #define SD_CD_0_INTTYPE_REG (* (reg8 *) SD_CD__0__INTTYPE) +#endif /* (SD_CD__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h old mode 100644 new mode 100755 index 8237c48..bb11d37 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_CD.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_CD_0 (SD_CD__0__PC) +#define SD_CD_0 (SD_CD__0__PC) +#define SD_CD_0_INTR ((uint16)((uint16)0x0001u << SD_CD__0__SHIFT)) + +#define SD_CD_INTR_ALL ((uint16)(SD_CD_0_INTR)) #endif /* End Pins SD_CD_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c old mode 100644 new mode 100755 index c2189d9..aeefd81 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_CS.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_CS_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_Write *******************************************************************************/ -void SD_CS_Write(uint8 value) +void SD_CS_Write(uint8 value) { uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK)); SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK); @@ -45,28 +63,31 @@ void SD_CS_Write(uint8 value) /******************************************************************************* * Function Name: SD_CS_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_CS_DM_STRONG Strong Drive -* SD_CS_DM_OD_HI Open Drain, Drives High -* SD_CS_DM_OD_LO Open Drain, Drives Low -* SD_CS_DM_RES_UP Resistive Pull Up -* SD_CS_DM_RES_DWN Resistive Pull Down -* SD_CS_DM_RES_UPDWN Resistive Pull Up/Down -* SD_CS_DM_DIG_HIZ High Impedance Digital -* SD_CS_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_SetDriveMode *******************************************************************************/ -void SD_CS_SetDriveMode(uint8 mode) +void SD_CS_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_CS_0, mode); } @@ -74,23 +95,22 @@ void SD_CS_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_CS_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_CS_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_Read *******************************************************************************/ -uint8 SD_CS_Read(void) +uint8 SD_CS_Read(void) { return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_CS_Read(void) /******************************************************************************* * Function Name: SD_CS_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_CS_Read() API because the +* SD_CS_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_ReadDataReg *******************************************************************************/ -uint8 SD_CS_ReadDataReg(void) +uint8 SD_CS_ReadDataReg(void) { return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_CS_INTSTAT) /******************************************************************************* - * Function Name: SD_CS_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_CS_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_CS_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_CS_0_INTR (First pin in the list) + * - SD_CS_1_INTR (Second pin in the list) + * - ... + * - SD_CS_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_CS_SUT.c usage_SD_CS_SetInterruptMode *******************************************************************************/ - uint8 SD_CS_ClearInterrupt(void) + void SD_CS_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_CS_0_INTR) != 0u) + { + SD_CS_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_CS_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_CS_SUT.c usage_SD_CS_ClearInterrupt + *******************************************************************************/ + uint8 SD_CS_ClearInterrupt(void) { return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h old mode 100644 new mode 100755 index e4a4cc7..06fd745 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_CS.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_CS_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_CS_Write(uint8 value) ; -void SD_CS_SetDriveMode(uint8 mode) ; -uint8 SD_CS_ReadDataReg(void) ; -uint8 SD_CS_Read(void) ; -uint8 SD_CS_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_CS_Write(uint8 value); +void SD_CS_SetDriveMode(uint8 mode); +uint8 SD_CS_ReadDataReg(void); +uint8 SD_CS_Read(void); +void SD_CS_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_CS_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_CS_DM_RES_UP PIN_DM_RES_UP -#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN -#define SD_CS_DM_OD_LO PIN_DM_OD_LO -#define SD_CS_DM_OD_HI PIN_DM_OD_HI -#define SD_CS_DM_STRONG PIN_DM_STRONG -#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_CS_SetDriveMode() function. + * @{ + */ + #define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_CS_DM_RES_UP PIN_DM_RES_UP + #define SD_CS_DM_RES_DWN PIN_DM_RES_DWN + #define SD_CS_DM_OD_LO PIN_DM_OD_LO + #define SD_CS_DM_OD_HI PIN_DM_OD_HI + #define SD_CS_DM_STRONG PIN_DM_STRONG + #define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_CS_MASK SD_CS__MASK #define SD_CS_SHIFT SD_CS__SHIFT #define SD_CS_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_CS__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_CS_SetInterruptMode() function. + * @{ + */ + #define SD_CS_INTR_NONE (uint16)(0x0000u) + #define SD_CS_INTR_RISING (uint16)(0x0001u) + #define SD_CS_INTR_FALLING (uint16)(0x0002u) + #define SD_CS_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_CS_INTR_MASK (0x01u) +#endif /* (SD_CS__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_CS_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_CS__SIO_CFG) + #define SD_CS_SIO_HYST_EN (* (reg8 *) SD_CS__SIO_HYST_EN) + #define SD_CS_SIO_REG_HIFREQ (* (reg8 *) SD_CS__SIO_REG_HIFREQ) + #define SD_CS_SIO_CFG (* (reg8 *) SD_CS__SIO_CFG) + #define SD_CS_SIO_DIFF (* (reg8 *) SD_CS__SIO_DIFF) +#endif /* (SD_CS__SIO_CFG) */ -#if defined(SD_CS__INTSTAT) /* Interrupt Registers */ - - #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT) - #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_CS__INTSTAT) + #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT) + #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP) + + #define SD_CS_0_INTTYPE_REG (* (reg8 *) SD_CS__0__INTTYPE) +#endif /* (SD_CS__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h old mode 100644 new mode 100755 index d63225a..630d57d --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_CS.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_CS_0 (SD_CS__0__PC) +#define SD_CS_0 (SD_CS__0__PC) +#define SD_CS_0_INTR ((uint16)((uint16)0x0001u << SD_CS__0__SHIFT)) + +#define SD_CS_INTR_ALL ((uint16)(SD_CS_0_INTR)) #endif /* End Pins SD_CS_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c old mode 100644 new mode 100755 index bc67176..207abd2 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_DAT1.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_DAT1_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_DAT1_SUT.c usage_SD_DAT1_Write *******************************************************************************/ -void SD_DAT1_Write(uint8 value) +void SD_DAT1_Write(uint8 value) { uint8 staticBits = (SD_DAT1_DR & (uint8)(~SD_DAT1_MASK)); SD_DAT1_DR = staticBits | ((uint8)(value << SD_DAT1_SHIFT) & SD_DAT1_MASK); @@ -45,28 +63,31 @@ void SD_DAT1_Write(uint8 value) /******************************************************************************* * Function Name: SD_DAT1_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_DAT1_DM_STRONG Strong Drive -* SD_DAT1_DM_OD_HI Open Drain, Drives High -* SD_DAT1_DM_OD_LO Open Drain, Drives Low -* SD_DAT1_DM_RES_UP Resistive Pull Up -* SD_DAT1_DM_RES_DWN Resistive Pull Down -* SD_DAT1_DM_RES_UPDWN Resistive Pull Up/Down -* SD_DAT1_DM_DIG_HIZ High Impedance Digital -* SD_DAT1_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_DAT1_SUT.c usage_SD_DAT1_SetDriveMode *******************************************************************************/ -void SD_DAT1_SetDriveMode(uint8 mode) +void SD_DAT1_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_DAT1_0, mode); } @@ -74,23 +95,22 @@ void SD_DAT1_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_DAT1_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_DAT1_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_DAT1_SUT.c usage_SD_DAT1_Read *******************************************************************************/ -uint8 SD_DAT1_Read(void) +uint8 SD_DAT1_Read(void) { return (SD_DAT1_PS & SD_DAT1_MASK) >> SD_DAT1_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_DAT1_Read(void) /******************************************************************************* * Function Name: SD_DAT1_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_DAT1_Read() API because the +* SD_DAT1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_DAT1_SUT.c usage_SD_DAT1_ReadDataReg *******************************************************************************/ -uint8 SD_DAT1_ReadDataReg(void) +uint8 SD_DAT1_ReadDataReg(void) { return (SD_DAT1_DR & SD_DAT1_MASK) >> SD_DAT1_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_DAT1_INTSTAT) /******************************************************************************* - * Function Name: SD_DAT1_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_DAT1_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_DAT1_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_DAT1_0_INTR (First pin in the list) + * - SD_DAT1_1_INTR (Second pin in the list) + * - ... + * - SD_DAT1_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_DAT1_SUT.c usage_SD_DAT1_SetInterruptMode *******************************************************************************/ - uint8 SD_DAT1_ClearInterrupt(void) + void SD_DAT1_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_DAT1_0_INTR) != 0u) + { + SD_DAT1_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_DAT1_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_DAT1_SUT.c usage_SD_DAT1_ClearInterrupt + *******************************************************************************/ + uint8 SD_DAT1_ClearInterrupt(void) { return (SD_DAT1_INTSTAT & SD_DAT1_MASK) >> SD_DAT1_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h old mode 100644 new mode 100755 index 1c5c940..2bd6d28 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_DAT1.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_DAT1_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_DAT1_Write(uint8 value) ; -void SD_DAT1_SetDriveMode(uint8 mode) ; -uint8 SD_DAT1_ReadDataReg(void) ; -uint8 SD_DAT1_Read(void) ; -uint8 SD_DAT1_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_DAT1_Write(uint8 value); +void SD_DAT1_SetDriveMode(uint8 mode); +uint8 SD_DAT1_ReadDataReg(void); +uint8 SD_DAT1_Read(void); +void SD_DAT1_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_DAT1_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_DAT1_DM_RES_UP PIN_DM_RES_UP -#define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN -#define SD_DAT1_DM_OD_LO PIN_DM_OD_LO -#define SD_DAT1_DM_OD_HI PIN_DM_OD_HI -#define SD_DAT1_DM_STRONG PIN_DM_STRONG -#define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_DAT1_SetDriveMode() function. + * @{ + */ + #define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_DAT1_DM_RES_UP PIN_DM_RES_UP + #define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN + #define SD_DAT1_DM_OD_LO PIN_DM_OD_LO + #define SD_DAT1_DM_OD_HI PIN_DM_OD_HI + #define SD_DAT1_DM_STRONG PIN_DM_STRONG + #define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_DAT1_MASK SD_DAT1__MASK #define SD_DAT1_SHIFT SD_DAT1__SHIFT #define SD_DAT1_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_DAT1__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_DAT1_SetInterruptMode() function. + * @{ + */ + #define SD_DAT1_INTR_NONE (uint16)(0x0000u) + #define SD_DAT1_INTR_RISING (uint16)(0x0001u) + #define SD_DAT1_INTR_FALLING (uint16)(0x0002u) + #define SD_DAT1_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_DAT1_INTR_MASK (0x01u) +#endif /* (SD_DAT1__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_DAT1_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_DAT1_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT1__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_DAT1__SIO_CFG) + #define SD_DAT1_SIO_HYST_EN (* (reg8 *) SD_DAT1__SIO_HYST_EN) + #define SD_DAT1_SIO_REG_HIFREQ (* (reg8 *) SD_DAT1__SIO_REG_HIFREQ) + #define SD_DAT1_SIO_CFG (* (reg8 *) SD_DAT1__SIO_CFG) + #define SD_DAT1_SIO_DIFF (* (reg8 *) SD_DAT1__SIO_DIFF) +#endif /* (SD_DAT1__SIO_CFG) */ -#if defined(SD_DAT1__INTSTAT) /* Interrupt Registers */ - - #define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT) - #define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_DAT1__INTSTAT) + #define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT) + #define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP) + + #define SD_DAT1_0_INTTYPE_REG (* (reg8 *) SD_DAT1__0__INTTYPE) +#endif /* (SD_DAT1__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h old mode 100644 new mode 100755 index 0a708f8..b355bda --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_DAT1.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_DAT1_0 (SD_DAT1__0__PC) +#define SD_DAT1_0 (SD_DAT1__0__PC) +#define SD_DAT1_0_INTR ((uint16)((uint16)0x0001u << SD_DAT1__0__SHIFT)) + +#define SD_DAT1_INTR_ALL ((uint16)(SD_DAT1_0_INTR)) #endif /* End Pins SD_DAT1_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c old mode 100644 new mode 100755 index ea86b32..27fe1c3 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_DAT2.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_DAT2_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_DAT2_SUT.c usage_SD_DAT2_Write *******************************************************************************/ -void SD_DAT2_Write(uint8 value) +void SD_DAT2_Write(uint8 value) { uint8 staticBits = (SD_DAT2_DR & (uint8)(~SD_DAT2_MASK)); SD_DAT2_DR = staticBits | ((uint8)(value << SD_DAT2_SHIFT) & SD_DAT2_MASK); @@ -45,28 +63,31 @@ void SD_DAT2_Write(uint8 value) /******************************************************************************* * Function Name: SD_DAT2_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_DAT2_DM_STRONG Strong Drive -* SD_DAT2_DM_OD_HI Open Drain, Drives High -* SD_DAT2_DM_OD_LO Open Drain, Drives Low -* SD_DAT2_DM_RES_UP Resistive Pull Up -* SD_DAT2_DM_RES_DWN Resistive Pull Down -* SD_DAT2_DM_RES_UPDWN Resistive Pull Up/Down -* SD_DAT2_DM_DIG_HIZ High Impedance Digital -* SD_DAT2_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_DAT2_SUT.c usage_SD_DAT2_SetDriveMode *******************************************************************************/ -void SD_DAT2_SetDriveMode(uint8 mode) +void SD_DAT2_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_DAT2_0, mode); } @@ -74,23 +95,22 @@ void SD_DAT2_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_DAT2_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_DAT2_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_DAT2_SUT.c usage_SD_DAT2_Read *******************************************************************************/ -uint8 SD_DAT2_Read(void) +uint8 SD_DAT2_Read(void) { return (SD_DAT2_PS & SD_DAT2_MASK) >> SD_DAT2_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_DAT2_Read(void) /******************************************************************************* * Function Name: SD_DAT2_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_DAT2_Read() API because the +* SD_DAT2_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_DAT2_SUT.c usage_SD_DAT2_ReadDataReg *******************************************************************************/ -uint8 SD_DAT2_ReadDataReg(void) +uint8 SD_DAT2_ReadDataReg(void) { return (SD_DAT2_DR & SD_DAT2_MASK) >> SD_DAT2_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_DAT2_INTSTAT) /******************************************************************************* - * Function Name: SD_DAT2_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_DAT2_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_DAT2_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_DAT2_0_INTR (First pin in the list) + * - SD_DAT2_1_INTR (Second pin in the list) + * - ... + * - SD_DAT2_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_DAT2_SUT.c usage_SD_DAT2_SetInterruptMode *******************************************************************************/ - uint8 SD_DAT2_ClearInterrupt(void) + void SD_DAT2_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_DAT2_0_INTR) != 0u) + { + SD_DAT2_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_DAT2_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_DAT2_SUT.c usage_SD_DAT2_ClearInterrupt + *******************************************************************************/ + uint8 SD_DAT2_ClearInterrupt(void) { return (SD_DAT2_INTSTAT & SD_DAT2_MASK) >> SD_DAT2_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h old mode 100644 new mode 100755 index 6f4fd8c..72786a8 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_DAT2.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_DAT2_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_DAT2_Write(uint8 value) ; -void SD_DAT2_SetDriveMode(uint8 mode) ; -uint8 SD_DAT2_ReadDataReg(void) ; -uint8 SD_DAT2_Read(void) ; -uint8 SD_DAT2_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_DAT2_Write(uint8 value); +void SD_DAT2_SetDriveMode(uint8 mode); +uint8 SD_DAT2_ReadDataReg(void); +uint8 SD_DAT2_Read(void); +void SD_DAT2_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_DAT2_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_DAT2_DM_RES_UP PIN_DM_RES_UP -#define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN -#define SD_DAT2_DM_OD_LO PIN_DM_OD_LO -#define SD_DAT2_DM_OD_HI PIN_DM_OD_HI -#define SD_DAT2_DM_STRONG PIN_DM_STRONG -#define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_DAT2_SetDriveMode() function. + * @{ + */ + #define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_DAT2_DM_RES_UP PIN_DM_RES_UP + #define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN + #define SD_DAT2_DM_OD_LO PIN_DM_OD_LO + #define SD_DAT2_DM_OD_HI PIN_DM_OD_HI + #define SD_DAT2_DM_STRONG PIN_DM_STRONG + #define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_DAT2_MASK SD_DAT2__MASK #define SD_DAT2_SHIFT SD_DAT2__SHIFT #define SD_DAT2_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_DAT2__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_DAT2_SetInterruptMode() function. + * @{ + */ + #define SD_DAT2_INTR_NONE (uint16)(0x0000u) + #define SD_DAT2_INTR_RISING (uint16)(0x0001u) + #define SD_DAT2_INTR_FALLING (uint16)(0x0002u) + #define SD_DAT2_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_DAT2_INTR_MASK (0x01u) +#endif /* (SD_DAT2__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_DAT2_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_DAT2_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT2__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_DAT2__SIO_CFG) + #define SD_DAT2_SIO_HYST_EN (* (reg8 *) SD_DAT2__SIO_HYST_EN) + #define SD_DAT2_SIO_REG_HIFREQ (* (reg8 *) SD_DAT2__SIO_REG_HIFREQ) + #define SD_DAT2_SIO_CFG (* (reg8 *) SD_DAT2__SIO_CFG) + #define SD_DAT2_SIO_DIFF (* (reg8 *) SD_DAT2__SIO_DIFF) +#endif /* (SD_DAT2__SIO_CFG) */ -#if defined(SD_DAT2__INTSTAT) /* Interrupt Registers */ - - #define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT) - #define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_DAT2__INTSTAT) + #define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT) + #define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP) + + #define SD_DAT2_0_INTTYPE_REG (* (reg8 *) SD_DAT2__0__INTTYPE) +#endif /* (SD_DAT2__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h old mode 100644 new mode 100755 index 5767bc0..8ab5fae --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_DAT2.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_DAT2_0 (SD_DAT2__0__PC) +#define SD_DAT2_0 (SD_DAT2__0__PC) +#define SD_DAT2_0_INTR ((uint16)((uint16)0x0001u << SD_DAT2__0__SHIFT)) + +#define SD_DAT2_INTR_ALL ((uint16)(SD_DAT2_0_INTR)) #endif /* End Pins SD_DAT2_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c old mode 100644 new mode 100755 index 50dcabf..1854393 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_MISO.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_MISO_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_Write *******************************************************************************/ -void SD_MISO_Write(uint8 value) +void SD_MISO_Write(uint8 value) { uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK)); SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK); @@ -45,28 +63,31 @@ void SD_MISO_Write(uint8 value) /******************************************************************************* * Function Name: SD_MISO_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_MISO_DM_STRONG Strong Drive -* SD_MISO_DM_OD_HI Open Drain, Drives High -* SD_MISO_DM_OD_LO Open Drain, Drives Low -* SD_MISO_DM_RES_UP Resistive Pull Up -* SD_MISO_DM_RES_DWN Resistive Pull Down -* SD_MISO_DM_RES_UPDWN Resistive Pull Up/Down -* SD_MISO_DM_DIG_HIZ High Impedance Digital -* SD_MISO_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_SetDriveMode *******************************************************************************/ -void SD_MISO_SetDriveMode(uint8 mode) +void SD_MISO_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_MISO_0, mode); } @@ -74,23 +95,22 @@ void SD_MISO_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_MISO_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_MISO_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_Read *******************************************************************************/ -uint8 SD_MISO_Read(void) +uint8 SD_MISO_Read(void) { return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_MISO_Read(void) /******************************************************************************* * Function Name: SD_MISO_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_MISO_Read() API because the +* SD_MISO_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_ReadDataReg *******************************************************************************/ -uint8 SD_MISO_ReadDataReg(void) +uint8 SD_MISO_ReadDataReg(void) { return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_MISO_INTSTAT) /******************************************************************************* - * Function Name: SD_MISO_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_MISO_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_MISO_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_MISO_0_INTR (First pin in the list) + * - SD_MISO_1_INTR (Second pin in the list) + * - ... + * - SD_MISO_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_MISO_SUT.c usage_SD_MISO_SetInterruptMode *******************************************************************************/ - uint8 SD_MISO_ClearInterrupt(void) + void SD_MISO_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_MISO_0_INTR) != 0u) + { + SD_MISO_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_MISO_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_MISO_SUT.c usage_SD_MISO_ClearInterrupt + *******************************************************************************/ + uint8 SD_MISO_ClearInterrupt(void) { return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h old mode 100644 new mode 100755 index 7b91202..067667d --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_MISO.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_MISO_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_MISO_Write(uint8 value) ; -void SD_MISO_SetDriveMode(uint8 mode) ; -uint8 SD_MISO_ReadDataReg(void) ; -uint8 SD_MISO_Read(void) ; -uint8 SD_MISO_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_MISO_Write(uint8 value); +void SD_MISO_SetDriveMode(uint8 mode); +uint8 SD_MISO_ReadDataReg(void); +uint8 SD_MISO_Read(void); +void SD_MISO_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_MISO_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_MISO_DM_RES_UP PIN_DM_RES_UP -#define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN -#define SD_MISO_DM_OD_LO PIN_DM_OD_LO -#define SD_MISO_DM_OD_HI PIN_DM_OD_HI -#define SD_MISO_DM_STRONG PIN_DM_STRONG -#define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_MISO_SetDriveMode() function. + * @{ + */ + #define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_MISO_DM_RES_UP PIN_DM_RES_UP + #define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN + #define SD_MISO_DM_OD_LO PIN_DM_OD_LO + #define SD_MISO_DM_OD_HI PIN_DM_OD_HI + #define SD_MISO_DM_STRONG PIN_DM_STRONG + #define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_MISO_MASK SD_MISO__MASK #define SD_MISO_SHIFT SD_MISO__SHIFT #define SD_MISO_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_MISO__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_MISO_SetInterruptMode() function. + * @{ + */ + #define SD_MISO_INTR_NONE (uint16)(0x0000u) + #define SD_MISO_INTR_RISING (uint16)(0x0001u) + #define SD_MISO_INTR_FALLING (uint16)(0x0002u) + #define SD_MISO_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_MISO_INTR_MASK (0x01u) +#endif /* (SD_MISO__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_MISO_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_MISO__SIO_CFG) + #define SD_MISO_SIO_HYST_EN (* (reg8 *) SD_MISO__SIO_HYST_EN) + #define SD_MISO_SIO_REG_HIFREQ (* (reg8 *) SD_MISO__SIO_REG_HIFREQ) + #define SD_MISO_SIO_CFG (* (reg8 *) SD_MISO__SIO_CFG) + #define SD_MISO_SIO_DIFF (* (reg8 *) SD_MISO__SIO_DIFF) +#endif /* (SD_MISO__SIO_CFG) */ -#if defined(SD_MISO__INTSTAT) /* Interrupt Registers */ - - #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT) - #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_MISO__INTSTAT) + #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT) + #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP) + + #define SD_MISO_0_INTTYPE_REG (* (reg8 *) SD_MISO__0__INTTYPE) +#endif /* (SD_MISO__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h old mode 100644 new mode 100755 index a8f41ca..d47930f --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_MISO.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_MISO_0 (SD_MISO__0__PC) +#define SD_MISO_0 (SD_MISO__0__PC) +#define SD_MISO_0_INTR ((uint16)((uint16)0x0001u << SD_MISO__0__SHIFT)) + +#define SD_MISO_INTR_ALL ((uint16)(SD_MISO_0_INTR)) #endif /* End Pins SD_MISO_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c old mode 100644 new mode 100755 index f980ba1..06eaf22 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_MOSI.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_MOSI_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Write *******************************************************************************/ -void SD_MOSI_Write(uint8 value) +void SD_MOSI_Write(uint8 value) { uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK)); SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK); @@ -45,28 +63,31 @@ void SD_MOSI_Write(uint8 value) /******************************************************************************* * Function Name: SD_MOSI_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_MOSI_DM_STRONG Strong Drive -* SD_MOSI_DM_OD_HI Open Drain, Drives High -* SD_MOSI_DM_OD_LO Open Drain, Drives Low -* SD_MOSI_DM_RES_UP Resistive Pull Up -* SD_MOSI_DM_RES_DWN Resistive Pull Down -* SD_MOSI_DM_RES_UPDWN Resistive Pull Up/Down -* SD_MOSI_DM_DIG_HIZ High Impedance Digital -* SD_MOSI_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetDriveMode *******************************************************************************/ -void SD_MOSI_SetDriveMode(uint8 mode) +void SD_MOSI_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_MOSI_0, mode); } @@ -74,23 +95,22 @@ void SD_MOSI_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_MOSI_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_MOSI_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Read *******************************************************************************/ -uint8 SD_MOSI_Read(void) +uint8 SD_MOSI_Read(void) { return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_MOSI_Read(void) /******************************************************************************* * Function Name: SD_MOSI_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_MOSI_Read() API because the +* SD_MOSI_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_ReadDataReg *******************************************************************************/ -uint8 SD_MOSI_ReadDataReg(void) +uint8 SD_MOSI_ReadDataReg(void) { return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_MOSI_INTSTAT) /******************************************************************************* - * Function Name: SD_MOSI_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_MOSI_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_MOSI_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_MOSI_0_INTR (First pin in the list) + * - SD_MOSI_1_INTR (Second pin in the list) + * - ... + * - SD_MOSI_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetInterruptMode *******************************************************************************/ - uint8 SD_MOSI_ClearInterrupt(void) + void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_MOSI_0_INTR) != 0u) + { + SD_MOSI_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_MOSI_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_MOSI_SUT.c usage_SD_MOSI_ClearInterrupt + *******************************************************************************/ + uint8 SD_MOSI_ClearInterrupt(void) { return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h old mode 100644 new mode 100755 index 895fe9e..d39b426 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_MOSI.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_MOSI_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_MOSI_Write(uint8 value) ; -void SD_MOSI_SetDriveMode(uint8 mode) ; -uint8 SD_MOSI_ReadDataReg(void) ; -uint8 SD_MOSI_Read(void) ; -uint8 SD_MOSI_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_MOSI_Write(uint8 value); +void SD_MOSI_SetDriveMode(uint8 mode); +uint8 SD_MOSI_ReadDataReg(void); +uint8 SD_MOSI_Read(void); +void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_MOSI_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_MOSI_DM_RES_UP PIN_DM_RES_UP -#define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN -#define SD_MOSI_DM_OD_LO PIN_DM_OD_LO -#define SD_MOSI_DM_OD_HI PIN_DM_OD_HI -#define SD_MOSI_DM_STRONG PIN_DM_STRONG -#define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_MOSI_SetDriveMode() function. + * @{ + */ + #define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_MOSI_DM_RES_UP PIN_DM_RES_UP + #define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN + #define SD_MOSI_DM_OD_LO PIN_DM_OD_LO + #define SD_MOSI_DM_OD_HI PIN_DM_OD_HI + #define SD_MOSI_DM_STRONG PIN_DM_STRONG + #define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_MOSI_MASK SD_MOSI__MASK #define SD_MOSI_SHIFT SD_MOSI__SHIFT #define SD_MOSI_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_MOSI__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_MOSI_SetInterruptMode() function. + * @{ + */ + #define SD_MOSI_INTR_NONE (uint16)(0x0000u) + #define SD_MOSI_INTR_RISING (uint16)(0x0001u) + #define SD_MOSI_INTR_FALLING (uint16)(0x0002u) + #define SD_MOSI_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_MOSI_INTR_MASK (0x01u) +#endif /* (SD_MOSI__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_MOSI_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_MOSI__SIO_CFG) + #define SD_MOSI_SIO_HYST_EN (* (reg8 *) SD_MOSI__SIO_HYST_EN) + #define SD_MOSI_SIO_REG_HIFREQ (* (reg8 *) SD_MOSI__SIO_REG_HIFREQ) + #define SD_MOSI_SIO_CFG (* (reg8 *) SD_MOSI__SIO_CFG) + #define SD_MOSI_SIO_DIFF (* (reg8 *) SD_MOSI__SIO_DIFF) +#endif /* (SD_MOSI__SIO_CFG) */ -#if defined(SD_MOSI__INTSTAT) /* Interrupt Registers */ - - #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT) - #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_MOSI__INTSTAT) + #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT) + #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP) + + #define SD_MOSI_0_INTTYPE_REG (* (reg8 *) SD_MOSI__0__INTTYPE) +#endif /* (SD_MOSI__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h old mode 100644 new mode 100755 index 5f1a08f..f0d46db --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_MOSI.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_MOSI_0 (SD_MOSI__0__PC) +#define SD_MOSI_0 (SD_MOSI__0__PC) +#define SD_MOSI_0_INTR ((uint16)((uint16)0x0001u << SD_MOSI__0__SHIFT)) + +#define SD_MOSI_INTR_ALL ((uint16)(SD_MOSI_0_INTR)) #endif /* End Pins SD_MOSI_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c old mode 100644 new mode 100755 index fc984f3..8bcf2fd --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_SCK.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_SCK_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_Write *******************************************************************************/ -void SD_SCK_Write(uint8 value) +void SD_SCK_Write(uint8 value) { uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK)); SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK); @@ -45,28 +63,31 @@ void SD_SCK_Write(uint8 value) /******************************************************************************* * Function Name: SD_SCK_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* SD_SCK_DM_STRONG Strong Drive -* SD_SCK_DM_OD_HI Open Drain, Drives High -* SD_SCK_DM_OD_LO Open Drain, Drives Low -* SD_SCK_DM_RES_UP Resistive Pull Up -* SD_SCK_DM_RES_DWN Resistive Pull Down -* SD_SCK_DM_RES_UPDWN Resistive Pull Up/Down -* SD_SCK_DM_DIG_HIZ High Impedance Digital -* SD_SCK_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_SetDriveMode *******************************************************************************/ -void SD_SCK_SetDriveMode(uint8 mode) +void SD_SCK_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_SCK_0, mode); } @@ -74,23 +95,22 @@ void SD_SCK_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_SCK_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_SCK_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_Read *******************************************************************************/ -uint8 SD_SCK_Read(void) +uint8 SD_SCK_Read(void) { return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT; } @@ -98,42 +118,102 @@ uint8 SD_SCK_Read(void) /******************************************************************************* * Function Name: SD_SCK_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_SCK_Read() API because the +* SD_SCK_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_ReadDataReg *******************************************************************************/ -uint8 SD_SCK_ReadDataReg(void) +uint8 SD_SCK_ReadDataReg(void) { return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_SCK_INTSTAT) /******************************************************************************* - * Function Name: SD_SCK_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: SD_SCK_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_SCK_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_SCK_0_INTR (First pin in the list) + * - SD_SCK_1_INTR (Second pin in the list) + * - ... + * - SD_SCK_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_SCK_SUT.c usage_SD_SCK_SetInterruptMode *******************************************************************************/ - uint8 SD_SCK_ClearInterrupt(void) + void SD_SCK_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_SCK_0_INTR) != 0u) + { + SD_SCK_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_SCK_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_SCK_SUT.c usage_SD_SCK_ClearInterrupt + *******************************************************************************/ + uint8 SD_SCK_ClearInterrupt(void) { return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h old mode 100644 new mode 100755 index 8fc2dc5..1f24c4e --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_SCK.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_SCK_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_SCK_Write(uint8 value) ; -void SD_SCK_SetDriveMode(uint8 mode) ; -uint8 SD_SCK_ReadDataReg(void) ; -uint8 SD_SCK_Read(void) ; -uint8 SD_SCK_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_SCK_Write(uint8 value); +void SD_SCK_SetDriveMode(uint8 mode); +uint8 SD_SCK_ReadDataReg(void); +uint8 SD_SCK_Read(void); +void SD_SCK_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_SCK_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_SCK_DM_RES_UP PIN_DM_RES_UP -#define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN -#define SD_SCK_DM_OD_LO PIN_DM_OD_LO -#define SD_SCK_DM_OD_HI PIN_DM_OD_HI -#define SD_SCK_DM_STRONG PIN_DM_STRONG -#define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_SCK_SetDriveMode() function. + * @{ + */ + #define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_SCK_DM_RES_UP PIN_DM_RES_UP + #define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN + #define SD_SCK_DM_OD_LO PIN_DM_OD_LO + #define SD_SCK_DM_OD_HI PIN_DM_OD_HI + #define SD_SCK_DM_STRONG PIN_DM_STRONG + #define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_SCK_MASK SD_SCK__MASK #define SD_SCK_SHIFT SD_SCK__SHIFT #define SD_SCK_WIDTH 1u +/* Interrupt constants */ +#if defined(SD_SCK__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_SCK_SetInterruptMode() function. + * @{ + */ + #define SD_SCK_INTR_NONE (uint16)(0x0000u) + #define SD_SCK_INTR_RISING (uint16)(0x0001u) + #define SD_SCK_INTR_FALLING (uint16)(0x0002u) + #define SD_SCK_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_SCK_INTR_MASK (0x01u) +#endif /* (SD_SCK__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 SD_SCK_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(SD_SCK__SIO_CFG) + #define SD_SCK_SIO_HYST_EN (* (reg8 *) SD_SCK__SIO_HYST_EN) + #define SD_SCK_SIO_REG_HIFREQ (* (reg8 *) SD_SCK__SIO_REG_HIFREQ) + #define SD_SCK_SIO_CFG (* (reg8 *) SD_SCK__SIO_CFG) + #define SD_SCK_SIO_DIFF (* (reg8 *) SD_SCK__SIO_DIFF) +#endif /* (SD_SCK__SIO_CFG) */ -#if defined(SD_SCK__INTSTAT) /* Interrupt Registers */ - - #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT) - #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(SD_SCK__INTSTAT) + #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT) + #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP) + + #define SD_SCK_0_INTTYPE_REG (* (reg8 *) SD_SCK__0__INTTYPE) +#endif /* (SD_SCK__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h old mode 100644 new mode 100755 index 0a09ffd..9659294 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_SCK.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_SCK_0 (SD_SCK__0__PC) +#define SD_SCK_0 (SD_SCK__0__PC) +#define SD_SCK_0_INTR ((uint16)((uint16)0x0001u << SD_SCK__0__SHIFT)) + +#define SD_SCK_INTR_ALL ((uint16)(SD_SCK_0_INTR)) #endif /* End Pins SD_SCK_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c old mode 100644 new mode 100755 index 7ebd294..a8bfd32 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c @@ -1,347 +1,459 @@ -/******************************************************************************* -* File Name: USBFS.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS.c +* \version 3.10 * -* Description: -* API for USBFS Component. +* \brief +* This file contains the global USBFS API functions. * * Note: -* Many of the functions use endpoint number. RAM arrays are sized with 9 -* elements so they are indexed directly by epNumber. The SIE and ARB +* Many of the functions use an endpoint number. SRAM arrays are sized with 9 +* elements, so they are indexed directly by epNumber. The SIE and ARB * registers are indexed by variations of epNumber - 1. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include -#include "USBFS.h" #include "USBFS_pvt.h" +#include "USBFS_cydmac.h" #include "USBFS_hid.h" -#if(USBFS_DMA1_REMOVE == 0u) - #include "USBFS_ep1_dma.h" -#endif /* USBFS_DMA1_REMOVE */ -#if(USBFS_DMA2_REMOVE == 0u) - #include "USBFS_ep2_dma.h" -#endif /* USBFS_DMA2_REMOVE */ -#if(USBFS_DMA3_REMOVE == 0u) - #include "USBFS_ep3_dma.h" -#endif /* USBFS_DMA3_REMOVE */ -#if(USBFS_DMA4_REMOVE == 0u) - #include "USBFS_ep4_dma.h" -#endif /* USBFS_DMA4_REMOVE */ -#if(USBFS_DMA5_REMOVE == 0u) - #include "USBFS_ep5_dma.h" -#endif /* USBFS_DMA5_REMOVE */ -#if(USBFS_DMA6_REMOVE == 0u) - #include "USBFS_ep6_dma.h" -#endif /* USBFS_DMA6_REMOVE */ -#if(USBFS_DMA7_REMOVE == 0u) - #include "USBFS_ep7_dma.h" -#endif /* USBFS_DMA7_REMOVE */ -#if(USBFS_DMA8_REMOVE == 0u) - #include "USBFS_ep8_dma.h" -#endif /* USBFS_DMA8_REMOVE */ -#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - #include "USBFS_EP_DMA_Done_isr.h" - #include "USBFS_EP8_DMA_Done_SR.h" - #include "USBFS_EP17_DMA_Done_SR.h" -#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#include "USBFS_Dp.h" /*************************************** * Global data allocation ***************************************/ +/** Indicates whether the USBFS has been initialized. The variable is +* initialized to 0 after device reset and set to 1 the first time USBFS_Start() +* is called. This allows the Component to restart without reinitialization after +* the first call to the USBFS_Start() routine. +* If re-initialization of the Component is required, the variable should be set +* to 0 before the USBFS_Start() routine is called. Alternatively, the USBFS can +* be reinitialized by calling both USBFS_Init() and USBFS_InitComponent() +* functions. +*/ uint8 USBFS_initVar = 0u; -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - uint8 USBFS_DmaChan[USBFS_MAX_EP]; - uint8 USBFS_DmaTd[USBFS_MAX_EP]; -#endif /* USBFS_EP_MM */ -#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT; - uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; - const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] = - { 0u, - USBFS_ep1_TD_TERMOUT_EN, - USBFS_ep2_TD_TERMOUT_EN, - USBFS_ep3_TD_TERMOUT_EN, - USBFS_ep4_TD_TERMOUT_EN, - USBFS_ep5_TD_TERMOUT_EN, - USBFS_ep6_TD_TERMOUT_EN, - USBFS_ep7_TD_TERMOUT_EN, - USBFS_ep8_TD_TERMOUT_EN + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + static void USBFS_InitEpDma(void); + + /* DMA chanels assigend for endpoints. */ + const uint8 USBFS_DmaChan[USBFS_MAX_EP] = + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + #else + /* DMA chanels assigend for endpoints. */ + uint8 USBFS_DmaChan[USBFS_MAX_EP]; + + /* DMA TDs require for PSoC 3/5LP operation. */ + uint8 USBFS_DmaTd[USBFS_MAX_EP]; + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + /* Number of DMA bursts. */ + uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP]; + + /* Number of bytes to transfer in last DMA burst. */ + uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP]; + + /* Storage for arrays above. */ + uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP]; + uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP]; + + /* DMA trigger mux output for usb.dma_req[0-7]. */ + const uint8 USBFS_DmaReqOut[USBFS_MAX_EP] = + { + 0u, + USBFS_ep1_dma__TR_OUTPUT, + USBFS_ep2_dma__TR_OUTPUT, + USBFS_ep3_dma__TR_OUTPUT, + USBFS_ep4_dma__TR_OUTPUT, + 0u, + 0u, + 0u, + 0u, }; - volatile uint16 USBFS_inLength[USBFS_MAX_EP]; - const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; - volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; -#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + /* DMA trigger mux output for usb.dma_burstend[0-7]. */ + const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP] = + { + 0u, + USBFS_BURSTEND_0_TR_OUTPUT, + USBFS_BURSTEND_1_TR_OUTPUT, + USBFS_BURSTEND_2_TR_OUTPUT, + USBFS_BURSTEND_3_TR_OUTPUT, + USBFS_BURSTEND_4_TR_OUTPUT, + USBFS_BURSTEND_5_TR_OUTPUT, + USBFS_BURSTEND_6_TR_OUTPUT, + USBFS_BURSTEND_7_TR_OUTPUT + }; + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT; + uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] = + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + volatile uint16 USBFS_inLength[USBFS_MAX_EP]; + const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ /******************************************************************************* * Function Name: USBFS_Start -******************************************************************************** +****************************************************************************//** * -* Summary: -* This function initialize the USB SIE, arbiter and the -* endpoint APIs, including setting the D+ Pullup +* This function performs all required initialization for the USBFS component. +* After this function call, the USB device initiates communication with the +* host by pull-up D+ line. This is the preferred method to begin component +* operation. * -* Parameters: -* device: Contains the device number of the desired device descriptor. +* Note that global interrupts have to be enabled because interrupts are +* required for USBFS component operation. +* +* PSoC 4200L devices: when USBFS component configured to DMA with Automatic +* Buffer Management, the DMA interrupt priority is changed to the highest +* (priority 0) inside this function. +* +* PSoC 3/PSoC 5LP devices: when USBFS component configured to DMA with +* Automatic Buffer Management, the Arbiter interrupt priority is changed to +* the highest (priority 0) inside this function. +* +* \param device +* Contains the device number of the desired device descriptor. * The device number can be found in the Device Descriptor Tab of * "Configure" dialog, under the settings of desired Device Descriptor, * in the "Device Number" field. -* mode: The operating voltage. This determines whether the voltage regulator -* is enabled for 5V operation or if pass through mode is used for 3.3V -* operation. Symbolic names and their associated values are given in the -* following table. -* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru -* Vcc for pull-up -* USBFS_5V_OPERATION - Enable voltage regulator and use -* regulator for pull-up -* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage -* regulator depend on Vddd Voltage configuration in DWR. +* \param mode: +* The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following list. * -* Return: -* None. +* *USBFS_3V_OPERATION* - Disable voltage regulator and pass- +* through Vcc for pull-up * -* Global variables: -* The USBFS_intiVar variable is used to indicate initial -* configuration of this component. The variable is initialized to zero (0u) -* and set to one (1u) the first time USBFS_Start() is called. -* This allows for component Re-Start without unnecessary re-initialization -* in all subsequent calls to the USBFS_Start() routine. -* If re-initialization of the component is required the variable should be set -* to zero before call of UART_Start() routine, or the user may call -* USBFS_Init() and USBFS_InitComponent() as done -* in the USBFS_Start() routine. +* *USBFS_5V_OPERATION* - Enable voltage regulator and use +* regulator for pull-up * -* Side Effects: +* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage +* regulator depending on the power supply +* voltage configuration in the DWR tab. +* For PSoC 3/5LP devices, the VDDD supply +* voltage is considered and for PSoC 4A-L, +* the VBUS supply voltage is considered.* +* \globalvars +* \ref USBFS_initVar +* +* \sideeffect * This function will reset all communication states to default. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_Start(uint8 device, uint8 mode) { - /* If not Initialized then initialize all required hardware and software */ - if(USBFS_initVar == 0u) + if (0u == USBFS_initVar) { USBFS_Init(); USBFS_initVar = 1u; } + USBFS_InitComponent(device, mode); } /******************************************************************************* * Function Name: USBFS_Init -******************************************************************************** +****************************************************************************//** * -* Summary: -* Initialize component's hardware. Usually called in USBFS_Start(). +* This function initializes or restores the component according to the +* customizer Configure dialog settings. It is not necessary to call +* USBFS_Init() because the USBFS_Start() routine calls +* this function and is the preferred method to begin component operation. * -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_Init(void) { - uint8 enableInterrupts; - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - uint16 i; - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ +#if (CY_PSOC4) + /* Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN; - enableInterrupts = CyEnterCriticalSection(); + /* The internal regulator (CR1.REG_ENABLE) is enabled in + * USBFS_InitComponent() if it is required. + */ - /* Enable USB block */ + /* Enable USBIO control on drive mode of D+ and D- pins. */ + USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE; + + /* Set number of LF CLK to detect UBS bus reset. */ + USBFS_BUS_RST_CNT_REG = USBFS_DEFUALT_BUS_RST_CNT; + + /* Select VBUS detection source and clear PHY isolate. The application level + * must ensure that VBUS is valid. There is no need to wait 2us before VBUS is valid. + */ + USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS; + + /* Enable PHY detector and single-ended and differential receivers. */ + USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY; + + /* Suspend clear sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + /* Sets IMO lock options and clear all other bits. */ + USBFS_CR1_REG = USBFS_DEFUALT_CR1; + + /* Configure level (hi, lo, med) for each interrupt source. */ + USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL; + + /* Configure interrupt sources from: SOF, Bus Reset and EP0. */ + USBFS_INTR_SIE_MASK_REG = USBFS_DEFAULT_INTR_SIE_MASK; + +#else + uint8 enableInterrupts = CyEnterCriticalSection(); + +#if (USBFS_EP_MANAGEMENT_DMA) + uint16 i; +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Enable USB block. */ USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; - /* Enable USB block for Standby Power Mode */ + /* Enable USB block for Standby Power Mode. */ USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - /* Enable core clock */ + /* Enable core clock. */ USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */ - /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ - USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); - CyDelayUs(0u); /*~50ns delay */ - /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) - * high. This will have been set low by the power manger out of reset. - * Also confirm USBIO pull-up disabled + /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE. */ + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */ + USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */ + /* Disable USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted. + * high. These bits will be set low by the power manager out-of-reset. + * Also confirm USBIO pull-up is disabled. */ - USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | - USBFS_PM_USB_CR0_PD_PULLUP_N))); + USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N); - /* Select iomode to USB mode*/ - USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE)); + /* Select IOMODE to USB mode. */ + USBFS_USBIO_CR1_REG &= (uint8) ~USBFS_USBIO_CR1_IOMODE; - /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + /* Enable USBIO reference by setting PM.USB_CR0.fsusbio_ref_en. */ USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; - /* The reference will be available 1 us after the regulator is enabled */ - CyDelayUs(1u); - /* OR 40us after power restored */ - CyDelayUs(40u); - /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ - USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK)); - USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK)); + /* Reference is available for 1us after regulator is enabled. */ + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); + /* OR 40us after power is restored. */ + CyDelayUs(USBFS_WAIT_VREF_RESTORE); + /* Ensure single-ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ + USBFS_DM_INP_DIS_REG &= (uint8) ~USBFS_DM_MASK; + USBFS_DP_INP_DIS_REG &= (uint8) ~USBFS_DP_MASK; - /* Enable USBIO */ + /* Enable USBIO. */ USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; - CyDelayUs(2u); - /* Set the USBIO pull-up enable */ + CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE); + /* Set USBIO pull-up enable. */ USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; - /* Write WAx */ + /* Reset Arbiter Write Address register for endpoint 1. */ CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */ - for (i = 0u; i < USBFS_MAX_EP; i++) - { - USBFS_DmaTd[i] = DMA_INVALID_TD; - #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - USBFS_DmaNextTd[i] = DMA_INVALID_TD; - #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ - } - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ +#if (USBFS_EP_MANAGEMENT_DMA) + /* Initialize transfer descriptor. This will be used to detect DMA state - initialized or not. */ + for (i = 0u; i < USBFS_MAX_EP; ++i) + { + USBFS_DmaTd[i] = DMA_INVALID_TD; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + } +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ CyExitCriticalSection(enableInterrupts); +#endif /* (CY_PSOC4) */ + /* Configure interrupts from USB block. */ +#if (CY_PSOC4) + /* Configure hi_int: set handler and priority. */ + CyIntSetPriority (USBFS_INTR_HI_VECT_NUM, USBFS_INTR_HI_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_HI_VECT_NUM, &USBFS_INTR_HI_ISR); - /* Set the bus reset Interrupt. */ - (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); + /* Configure lo_int: set handler and priority. */ + CyIntSetPriority (USBFS_INTR_LO_VECT_NUM, USBFS_INTR_LO_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_LO_VECT_NUM, &USBFS_INTR_LO_ISR); + + /* Configure med_int: set handler and priority (routed through DSI). */ + CyIntSetPriority (USBFS_INTR_MED_VECT_NUM, USBFS_INTR_MED_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_MED_VECT_NUM, &USBFS_INTR_MED_ISR); + +#else + /* Set bus reset interrupt. */ CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); + (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); - /* Set the SOF Interrupt. */ - #if(USBFS_SOF_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); - CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); - #endif /* USBFS_SOF_ISR_REMOVE */ - - /* Set the Control Endpoint Interrupt. */ - (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); + /* Set Control Endpoint Interrupt. */ CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); + (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); - /* Set the Data Endpoint 1 Interrupt. */ - #if(USBFS_EP1_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); - CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); - #endif /* USBFS_EP1_ISR_REMOVE */ + /* Set SOF interrupt. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntSetPriority (USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); + (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ - /* Set the Data Endpoint 2 Interrupt. */ - #if(USBFS_EP2_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); - CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); - #endif /* USBFS_EP2_ISR_REMOVE */ + /* Set Data Endpoint 1 Interrupt. */ + #if (USBFS_EP1_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); + (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ - /* Set the Data Endpoint 3 Interrupt. */ - #if(USBFS_EP3_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); - CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); - #endif /* USBFS_EP3_ISR_REMOVE */ + /* Set Data Endpoint 2 Interrupt. */ + #if (USBFS_EP2_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); + (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); + #endif /* (USBFS_EP2_ISR_ACTIVE) */ - /* Set the Data Endpoint 4 Interrupt. */ - #if(USBFS_EP4_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); - CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); - #endif /* USBFS_EP4_ISR_REMOVE */ + /* Set Data Endpoint 3 Interrupt. */ + #if (USBFS_EP3_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); + (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); + #endif /* (USBFS_EP3_ISR_ACTIVE) */ - /* Set the Data Endpoint 5 Interrupt. */ - #if(USBFS_EP5_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); - CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); - #endif /* USBFS_EP5_ISR_REMOVE */ + /* Set Data Endpoint 4 Interrupt. */ + #if (USBFS_EP4_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); + (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); + #endif /* (USBFS_EP4_ISR_ACTIVE) */ - /* Set the Data Endpoint 6 Interrupt. */ - #if(USBFS_EP6_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); - CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); - #endif /* USBFS_EP6_ISR_REMOVE */ + /* Set Data Endpoint 5 Interrupt. */ + #if (USBFS_EP5_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); + (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ - /* Set the Data Endpoint 7 Interrupt. */ - #if(USBFS_EP7_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); - CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); - #endif /* USBFS_EP7_ISR_REMOVE */ + /* Set Data Endpoint 6 Interrupt. */ + #if (USBFS_EP6_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); + (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); + #endif /* (USBFS_EP6_ISR_ACTIVE) */ - /* Set the Data Endpoint 8 Interrupt. */ - #if(USBFS_EP8_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); - CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); - #endif /* USBFS_EP8_ISR_REMOVE */ + /* Set Data Endpoint 7 Interrupt. */ + #if (USBFS_EP7_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); + (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ - #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - /* Set the ARB Interrupt. */ - (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); - CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + /* Set Data Endpoint 8 Interrupt. */ + #if (USBFS_EP8_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); + (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ + /* Set ARB Interrupt. */ + #if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + CyIntSetPriority (USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); + (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); + #endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ + + /* Common: Configure GPIO interrupt for wakeup. */ +#if (USBFS_DP_ISR_ACTIVE) + CyIntSetPriority (USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIORITY); + (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); +#endif /* (USBFS_DP_ISR_ACTIVE) */ + +#if (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) + /* Initialize DMA channels. */ + USBFS_InitEpDma(); +#endif /* (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) */ } /******************************************************************************* * Function Name: USBFS_InitComponent -******************************************************************************** +****************************************************************************//** * -* Summary: -* Initialize the component, except for the HW which is done one time in -* the Start function. This function pulls up D+. +* This function initializes the component’s global variables and initiates +* communication with the host by pull-up D+ line. * -* Parameters: -* device: Contains the device number of the desired device descriptor. -* The device number can be found in the Device Descriptor Tab of -* "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* mode: The operating voltage. This determines whether the voltage regulator -* is enabled for 5V operation or if pass through mode is used for 3.3V -* operation. Symbolic names and their associated values are given in the -* following table. -* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru -* Vcc for pull-up -* USBFS_5V_OPERATION - Enable voltage regulator and use -* regulator for pull-up -* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage -* regulator depend on Vddd Voltage configuration in DWR. +* \param device: +* Contains the device number of the desired device descriptor. The device +* number can be found in the Device Descriptor Tab of "Configure" dialog, +* under the settings of desired Device Descriptor, in the *Device Number* +* field. +* \param mode: +* The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following list. * -* Return: -* None. +* *USBFS_3V_OPERATION* - Disable voltage regulator and pass- +* through Vcc for pull-up * -* Global variables: -* USBFS_device: Contains the device number of the desired device -* descriptor. The device number can be found in the Device Descriptor Tab -* of "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* USBFS_transferState: This variable used by the communication -* functions to handle current transfer state. Initialized to -* TRANS_STATE_IDLE in this API. -* USBFS_configuration: Contains current configuration number -* which is set by the Host using SET_CONFIGURATION request. -* Initialized to zero in this API. -* USBFS_deviceAddress: Contains current device address. This -* variable is initialized to zero in this API. Host starts to communicate -* to device with address 0 and then set it to whatever value using +* *USBFS_5V_OPERATION* - Enable voltage regulator and use +* regulator for pull-up +* +* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage +* regulator depending on the power supply +* voltage configuration in the DWR tab. +* For PSoC 3/5LP devices, the VDDD supply +* voltage is considered and for PSoC 4A-L, +* the VBUS supply voltage is considered. +* +* \globalvars +* \ref USBFS_device +* \ref USBFS_transferState +* \ref USBFS_configuration +* \ref USBFS_deviceStatus +* +* \ref USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using a * SET_ADDRESS request. -* USBFS_deviceStatus: initialized to 0. -* This is two bit variable which contain power status in first bit -* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote -* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. -* USBFS_lastPacketSize initialized to 0; * -* Reentrant: +* \ref USBFS_lastPacketSize - Initialized to 0; +* +* \reentrant * No. * *******************************************************************************/ @@ -351,147 +463,208 @@ void USBFS_InitComponent(uint8 device, uint8 mode) * HID 7.2.6 Set_Protocol Request: * "When initialized, all devices default to report protocol." */ - #if defined(USBFS_ENABLE_HID_CLASS) - uint8 i; +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; - for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - { - USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - } - #endif /* USBFS_ENABLE_HID_CLASS */ + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } +#endif /* USBFS_ENABLE_HID_CLASS */ - /* Enable Interrupts. */ + /* Store device number to access descriptor. */ + USBFS_device = device; + + /* Reset component internal variables. */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_lastPacketSize = 0u; + + /* Enable component interrupts. */ +#if (CY_PSOC4) + CyIntEnable(USBFS_INTR_HI_VECT_NUM); + CyIntEnable(USBFS_INTR_MED_VECT_NUM); + CyIntEnable(USBFS_INTR_LO_VECT_NUM); +#else CyIntEnable(USBFS_BUS_RESET_VECT_NUM); CyIntEnable(USBFS_EP_0_VECT_NUM); - #if(USBFS_EP1_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_1_VECT_NUM); - #endif /* USBFS_EP1_ISR_REMOVE */ - #if(USBFS_EP2_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_2_VECT_NUM); - #endif /* USBFS_EP2_ISR_REMOVE */ - #if(USBFS_EP3_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_3_VECT_NUM); - #endif /* USBFS_EP3_ISR_REMOVE */ - #if(USBFS_EP4_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_4_VECT_NUM); - #endif /* USBFS_EP4_ISR_REMOVE */ - #if(USBFS_EP5_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_5_VECT_NUM); - #endif /* USBFS_EP5_ISR_REMOVE */ - #if(USBFS_EP6_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_6_VECT_NUM); - #endif /* USBFS_EP6_ISR_REMOVE */ - #if(USBFS_EP7_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_7_VECT_NUM); - #endif /* USBFS_EP7_ISR_REMOVE */ - #if(USBFS_EP8_ISR_REMOVE == 0u) - CyIntEnable(USBFS_EP_8_VECT_NUM); - #endif /* USBFS_EP8_ISR_REMOVE */ - #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) - /* usb arb interrupt enable */ - USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; - CyIntEnable(USBFS_ARB_VECT_NUM); - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ - /* Arbiter configuration for DMA transfers */ - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; - #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /*Set cfg cmplt this rises DMA request when the full configuration is done */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - #if(USBFS_EP_DMA_AUTO_OPT == 0u) - /* Init interrupt which handles verification of the successful DMA transaction */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntEnable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + #if (USBFS_EP1_ISR_ACTIVE) + CyIntEnable(USBFS_EP_1_VECT_NUM); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + #if (USBFS_EP2_ISR_ACTIVE) + CyIntEnable(USBFS_EP_2_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP3_ISR_ACTIVE) + CyIntEnable(USBFS_EP_3_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP4_ISR_ACTIVE) + CyIntEnable(USBFS_EP_4_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP5_ISR_ACTIVE) + CyIntEnable(USBFS_EP_5_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP6_ISR_ACTIVE) + CyIntEnable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + + #if (USBFS_EP7_ISR_ACTIVE) + CyIntEnable(USBFS_EP_7_VECT_NUM); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + #if (USBFS_EP8_ISR_ACTIVE) + CyIntEnable(USBFS_EP_8_VECT_NUM); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ + +#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + + #if (CY_PSOC3 || CY_PSOC5) + CyIntEnable(USBFS_ARB_VECT_NUM); + #endif /* (CY_PSOC3 || CY_PSOC5) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */ + +/* Arbiter configuration for DMA transfers. */ +#if (USBFS_EP_MANAGEMENT_DMA) + /* Configure Arbiter for Manual or Auto DMA operation and clear configuration completion. */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + + #if (CY_PSOC4) + /* Enable DMA operation. */ + CyDmaEnable(); + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Change DMA priority to be highest. */ + CyIntSetPriority(CYDMA_INTR_NUMBER, USBFS_DMA_AUTO_INTR_PRIO); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (CY_PSOC4) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + /* Enable DMA interrupt to handle DMA management. */ + CyIntEnable(CYDMA_INTR_NUMBER); + #else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + /* Initialize interrupts which handle verification of successful DMA transaction. */ USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR); USBFS_EP17_DMA_Done_SR_InterruptEnable(); USBFS_EP8_DMA_Done_SR_InterruptEnable(); - #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */ - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + #endif /* (CY_PSOC4) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - - /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/ + /* Enable USB regulator depends on operation voltage. IMO Locking is enabled in Init(). */ switch(mode) { - case USBFS_3V_OPERATION: - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - break; - case USBFS_5V_OPERATION: - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - break; - default: /*USBFS_DWR_VDDD_OPERATION */ - #if(USBFS_VDDD_MV < USBFS_3500MV) - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; - #else - USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; - #endif /* USBFS_VDDD_MV < USBFS_3500MV */ - break; + case USBFS_3V_OPERATION: + /* Disable regulator for 3V operation. */ + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + break; + + case USBFS_5V_OPERATION: + /* Enable regulator for 5V operation. */ + USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE; + break; + + default: /* Check DWR settings of USB power supply. */ + #if (USBFS_VDDD_MV < USBFS_3500MV) + /* Disable regulator for 3V operation. */ + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + #else + /* Enable regulator for 5V operation. */ + USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE; + #endif /* (USBFS_VDDD_MV < USBFS_3500MV) */ + break; } - /* Record the descriptor selection */ - USBFS_device = device; +#if (CY_PSOC4) + /* Clear bus activity. */ + USBFS_CR1_REG &= (uint32) ~USBFS_CR1_BUS_ACTIVITY; - /* Clear all of the component data */ - USBFS_configuration = 0u; - USBFS_interfaceNumber = 0u; - USBFS_configurationChanged = 0u; - USBFS_deviceAddress = 0u; - USBFS_deviceStatus = 0u; + /* Clear EP0 count register. */ + USBFS_EP0_CNT_REG = USBFS_CLEAR_REG; - USBFS_lastPacketSize = 0u; + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; - /* ACK Setup, Stall IN/OUT */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + #if (USBFS_LPM_ACTIVE) + if (NULL != USBFS_GetBOSPtr()) + { + /* Enable LPM and acknowledge LPM packets for active device. + * Reset NYET_EN and SUB_RESP bits in the LPM_CTRL register. + */ + USBFS_LPM_CTRL_REG = (USBFS_LPM_CTRL_LPM_EN | \ + USBFS_LPM_CTRL_LPM_ACK_RESP); + } + else + { + /* Disable LPM for active device. */ + USBFS_LPM_CTRL_REG &= (uint32) ~USBFS_LPM_CTRL_LPM_EN; + } + #endif /* (USBFS_LPM_ACTIVE) */ - /* Enable the SIE with an address 0 */ - CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + /* Enable device to responds to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; - /* Workaround for PSOC5LP */ - CyDelayCycles(1u); +#else + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; - /* Finally, Enable d+ pullup and select iomode to USB mode*/ - CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); + /* Enable device to respond to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; + CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY); +#endif /* (CY_PSOC4) */ + + /* Enable D+ pull-up and keep USB control on IO. */ + USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; } /******************************************************************************* * Function Name: USBFS_ReInitComponent -******************************************************************************** +****************************************************************************//** * -* Summary: * This function reinitialize the component configuration and is * intend to be called from the Reset interrupt. * -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: -* USBFS_device: Contains the device number of the desired device -* descriptor. The device number can be found in the Device Descriptor Tab -* of "Configure" dialog, under the settings of desired Device Descriptor, -* in the "Device Number" field. -* USBFS_transferState: This variable used by the communication -* functions to handle current transfer state. Initialized to +* \globalvars +* USBFS_device - Contains the device number of the desired Device +* Descriptor. The device number can be found in the Device Descriptor tab +* of the Configure dialog, under the settings of the desired Device Descriptor, +* in the Device Number field. +* USBFS_transferState - This variable is used by the communication +* functions to handle the current transfer state. Initialized to * TRANS_STATE_IDLE in this API. -* USBFS_configuration: Contains current configuration number -* which is set by the Host using SET_CONFIGURATION request. +* USBFS_configuration - Contains the current configuration number +* set by the Host using a SET_CONFIGURATION request. * Initialized to zero in this API. -* USBFS_deviceAddress: Contains current device address. This -* variable is initialized to zero in this API. Host starts to communicate -* to device with address 0 and then set it to whatever value using -* SET_ADDRESS request. -* USBFS_deviceStatus: initialized to 0. -* This is two bit variable which contain power status in first bit -* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote -* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. -* USBFS_lastPacketSize initialized to 0; +* USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using +* a SET_ADDRESS request. +* USBFS_deviceStatus - Initialized to 0. +* This is a two-bit variable which contains the power status in the first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and the remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in the second bit. +* USBFS_lastPacketSize - Initialized to 0; * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -500,440 +673,588 @@ void USBFS_ReInitComponent(void) /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol * Request: "When initialized, all devices default to report protocol." */ - #if defined(USBFS_ENABLE_HID_CLASS) - uint8 i; +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; - for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) - { - USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; - } - #endif /* USBFS_ENABLE_HID_CLASS */ + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } +#endif /* USBFS_ENABLE_HID_CLASS */ - USBFS_transferState = USBFS_TRANS_STATE_IDLE; - - /* Clear all of the component data */ - USBFS_configuration = 0u; - USBFS_interfaceNumber = 0u; + /* Reset component internal variables. */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; USBFS_configurationChanged = 0u; - USBFS_deviceAddress = 0u; - USBFS_deviceStatus = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_lastPacketSize = 0u; - USBFS_lastPacketSize = 0u; - - - /* ACK Setup, Stall IN/OUT */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - - /* Enable the SIE with an address 0 */ - CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); +#if (CY_PSOC4) + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; +#else + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; +#endif /* (CY_PSOC4) */ + /* Enable device to respond to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; } /******************************************************************************* * Function Name: USBFS_Stop -******************************************************************************** +****************************************************************************//** * -* Summary: * This function shuts down the USB function including to release -* the D+ Pullup and disabling the SIE. +* the D+ pull-up and disabling the SIE. * -* Parameters: -* None. +* \globalvars +* \ref USBFS_configuration * -* Return: -* None. +* USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using +* a SET_ADDRESS request. * -* Global variables: -* USBFS_configuration: Contains current configuration number -* which is set by the Host using SET_CONFIGURATION request. -* Initialized to zero in this API. -* USBFS_deviceAddress: Contains current device address. This -* variable is initialized to zero in this API. Host starts to communicate -* to device with address 0 and then set it to whatever value using -* SET_ADDRESS request. -* USBFS_deviceStatus: initialized to 0. -* This is two bit variable which contain power status in first bit -* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote -* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. -* USBFS_configurationChanged: This variable is set to one after -* SET_CONFIGURATION request and cleared in this function. -* USBFS_intiVar variable is set to zero +* \ref USBFS_deviceStatus +* +* \ref USBFS_configurationChanged +* +* USBFS_intiVar - This variable is set to zero * *******************************************************************************/ void USBFS_Stop(void) { + uint8 enableInterrupts; - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ +#if (USBFS_EP_MANAGEMENT_DMA) + /* Stop all DMA channels. */ + USBFS_Stop_DMA(USBFS_MAX_EP); +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ - /* Disable the SIE */ - USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE); - /* Disable the d+ pullup */ - USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN); - /* Disable USB in ACT PM */ - USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB); - /* Disable USB block for Standby Power Mode */ - USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); + enableInterrupts = CyEnterCriticalSection(); + + /* Disable USB IP to respond to USB traffic. */ + USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE; + + /* Disable D+ pull-up. */ + USBFS_USBIO_CR1_REG &= (uint8) ~ USBFS_USBIO_CR1_USBPUEN; + +#if (CY_PSOC4) + /* Disable USBFS block. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_ENABLE; +#else + /* Clear power active and standby mode templates. */ + USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB; + + /* Ensure single-ended disable bits are high (PRT15.INP_DIS[7:6]) + * (input receiver disabled). */ + USBFS_DM_INP_DIS_REG |= (uint8) USBFS_DM_MASK; + USBFS_DP_INP_DIS_REG |= (uint8) USBFS_DP_MASK; + +#endif /* (CY_PSOC4) */ + + CyExitCriticalSection(enableInterrupts); + + /* Disable component interrupts. */ +#if (CY_PSOC4) + CyIntDisable(USBFS_INTR_HI_VECT_NUM); + CyIntDisable(USBFS_INTR_LO_VECT_NUM); + CyIntDisable(USBFS_INTR_MED_VECT_NUM); +#else - /* Disable the reset and EP interrupts */ CyIntDisable(USBFS_BUS_RESET_VECT_NUM); CyIntDisable(USBFS_EP_0_VECT_NUM); - #if(USBFS_EP1_ISR_REMOVE == 0u) + + #if (USBFS_SOF_ISR_ACTIVE) + CyIntDisable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + #if (USBFS_EP1_ISR_ACTIVE) CyIntDisable(USBFS_EP_1_VECT_NUM); - #endif /* USBFS_EP1_ISR_REMOVE */ - #if(USBFS_EP2_ISR_REMOVE == 0u) + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + #if (USBFS_EP2_ISR_ACTIVE) CyIntDisable(USBFS_EP_2_VECT_NUM); - #endif /* USBFS_EP2_ISR_REMOVE */ - #if(USBFS_EP3_ISR_REMOVE == 0u) + #endif /* (USBFS_EP2_ISR_ACTIVE) */ + + #if (USBFS_EP3_ISR_ACTIVE) CyIntDisable(USBFS_EP_3_VECT_NUM); - #endif /* USBFS_EP3_ISR_REMOVE */ - #if(USBFS_EP4_ISR_REMOVE == 0u) + #endif /* (USBFS_EP3_ISR_ACTIVE) */ + + #if (USBFS_EP4_ISR_ACTIVE) CyIntDisable(USBFS_EP_4_VECT_NUM); - #endif /* USBFS_EP4_ISR_REMOVE */ - #if(USBFS_EP5_ISR_REMOVE == 0u) + #endif /* (USBFS_EP4_ISR_ACTIVE) */ + + #if (USBFS_EP5_ISR_ACTIVE) CyIntDisable(USBFS_EP_5_VECT_NUM); - #endif /* USBFS_EP5_ISR_REMOVE */ - #if(USBFS_EP6_ISR_REMOVE == 0u) + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP6_ISR_ACTIVE) CyIntDisable(USBFS_EP_6_VECT_NUM); - #endif /* USBFS_EP6_ISR_REMOVE */ - #if(USBFS_EP7_ISR_REMOVE == 0u) + #endif /* USBFS_EP6_ISR_REMOVE */ + + #if (USBFS_EP7_ISR_ACTIVE) CyIntDisable(USBFS_EP_7_VECT_NUM); - #endif /* USBFS_EP7_ISR_REMOVE */ - #if(USBFS_EP8_ISR_REMOVE == 0u) + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + #if (USBFS_EP8_ISR_ACTIVE) CyIntDisable(USBFS_EP_8_VECT_NUM); - #endif /* USBFS_EP8_ISR_REMOVE */ + #endif /* (USBFS_EP8_ISR_ACTIVE) */ - /* Clear all of the component data */ - USBFS_configuration = 0u; - USBFS_interfaceNumber = 0u; + #if (USBFS_DP_ISR_ACTIVE) + /* Clear active mode Dp interrupt source history. */ + (void) USBFS_Dp_ClearInterrupt(); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_ACTIVE). */ + +#endif /* (CY_PSOC4) */ + + /* Reset component internal variables. */ USBFS_configurationChanged = 0u; - USBFS_deviceAddress = 0u; - USBFS_deviceStatus = 0u; - USBFS_initVar = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + /* It is mandatory for correct device startup. */ + USBFS_initVar = 0u; } /******************************************************************************* * Function Name: USBFS_CheckActivity -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the activity status of the bus. Clears the status hardware to -* provide fresh activity status on the next call of this routine. +* This function returns the activity status of the bus. It clears the hardware +* status to provide updated status on the next call of this function. It +* provides a way to determine whether any USB bus activity occurred. The +* application should use this function to determine if the USB suspend +* conditions are met. * -* Parameters: -* None. * -* Return: -* 1 - If bus activity was detected since the last call to this function -* 0 - If bus activity not was detected since the last call to this function +* \return +* cystatus: Status of the bus since the last call of the function. +* Return Value | Description +* -------------|--------------------------------------------------------------- +* 1 |Bus activity was detected since the last call to this function +* 0 |Bus activity was not detected since the last call to this function +* * *******************************************************************************/ uint8 USBFS_CheckActivity(void) { - uint8 r; + uint8 cr1Reg = USBFS_CR1_REG; - r = CY_GET_REG8(USBFS_CR1_PTR); - CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY)))); + /* Clear bus activity. */ + USBFS_CR1_REG = (cr1Reg & (uint8) ~USBFS_CR1_BUS_ACTIVITY); - return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT); + /* Get bus activity. */ + return ((0u != (cr1Reg & USBFS_CR1_BUS_ACTIVITY)) ? (1u) : (0u)); } /******************************************************************************* * Function Name: USBFS_GetConfiguration -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the current configuration setting +* This function gets the current configuration of the USB device. * -* Parameters: -* None. -* -* Return: -* configuration. +* \return +* Returns the currently assigned configuration. Returns 0 if the device +* is not configured * *******************************************************************************/ uint8 USBFS_GetConfiguration(void) { - return(USBFS_configuration); + return (USBFS_configuration); } /******************************************************************************* * Function Name: USBFS_IsConfigurationChanged -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the clear on read configuration state. It is usefull when PC send -* double SET_CONFIGURATION request with same configuration number. +* This function returns the clear-on-read configuration state. It is useful +* when the host sends double SET_CONFIGURATION request with the same +* configuration number or changes alternate settings of the interface. +* After configuration has been changed the OUT endpoints must be enabled and IN +* endpoint must be loaded with data to start communication with the host. * -* Parameters: -* None. -* -* Return: -* Not zero value when new configuration has been changed, otherwise zero is +* \return +* None-zero value when new configuration has been changed, otherwise zero is * returned. * -* Global variables: -* USBFS_configurationChanged: This variable is set to one after -* SET_CONFIGURATION request and cleared in this function. +* \globalvars +* +* \ref USBFS_configurationChanged - This variable is set to 1 after +* a SET_CONFIGURATION request and cleared in this function. * *******************************************************************************/ uint8 USBFS_IsConfigurationChanged(void) { uint8 res = 0u; - if(USBFS_configurationChanged != 0u) + if (USBFS_configurationChanged != 0u) { res = USBFS_configurationChanged; USBFS_configurationChanged = 0u; } - return(res); + return (res); } /******************************************************************************* * Function Name: USBFS_GetInterfaceSetting -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the alternate setting from current interface +* This function gets the current alternate setting for the specified interface. +* It is useful to identify which alternate settings are active in the specified +* interface. * -* Parameters: -* uint8 interfaceNumber, interface number +* \param +* interfaceNumber interface number * -* Return: -* Alternate setting. +* \return +* Returns the current alternate setting for the specified interface. * *******************************************************************************/ uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) { - return(USBFS_interfaceSetting[interfaceNumber]); + return (USBFS_interfaceSetting[interfaceNumber]); } /******************************************************************************* * Function Name: USBFS_GetEPState -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returned the state of the requested endpoint. +* This function returns the state of the requested endpoint. * -* Parameters: -* epNumber: Endpoint Number +* \param epNumber Data endpoint number * -* Return: -* State of the requested endpoint. +* \return +* Returns the current state of the specified USBFS endpoint. Symbolic names and +* their associated values are given in the following table. Use these constants +* whenever you write code to change the state of the endpoints, such as ISR +* code, to handle data sent or received. +* +* Return Value | Description +* -----------------------|----------------------------------------------------- +* USBFS_NO_EVENT_PENDING |The endpoint is awaiting SIE action +* USBFS_EVENT_PENDING |The endpoint is awaiting CPU action +* USBFS_NO_EVENT_ALLOWED |The endpoint is locked from access +* USBFS_IN_BUFFER_FULL |The IN endpoint is loaded and the mode is set to ACK IN +* USBFS_IN_BUFFER_EMPTY |An IN transaction occurred and more data can be loaded +* USBFS_OUT_BUFFER_EMPTY |The OUT endpoint is set to ACK OUT and is waiting for data +* USBFS_OUT_BUFFER_FULL |An OUT transaction has occurred and data can be read * *******************************************************************************/ uint8 USBFS_GetEPState(uint8 epNumber) { - return(USBFS_EP[epNumber].apiEpState); + return (USBFS_EP[epNumber].apiEpState); } /******************************************************************************* * Function Name: USBFS_GetEPCount -******************************************************************************** +****************************************************************************//** * -* Summary: * This function supports Data Endpoints only(EP1-EP8). * Returns the transfer count for the requested endpoint. The value from * the count registers includes 2 counts for the two byte checksum of the * packet. This function subtracts the two counts. * -* Parameters: -* epNumber: Data Endpoint Number. -* Valid values are between 1 and 8. +* \param epNumber Data Endpoint Number. +* Valid values are between 1 and 8. * -* Return: +* \return * Returns the current byte count from the specified endpoint or 0 for an * invalid endpoint. * *******************************************************************************/ uint16 USBFS_GetEPCount(uint8 epNumber) { - uint8 ri; - uint16 result = 0u; + uint16 cntr = 0u; - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - - result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & - USBFS_EPX_CNT0_MASK); - result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri)); - result -= USBFS_EPX_CNTX_CRC_COUNT; + /* Get 11-bits EP counter where epCnt0 - 3 bits MSB and epCnt1 - 8 bits LSB. */ + cntr = ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0) & USBFS_EPX_CNT0_MASK; + cntr = ((uint16) (cntr << 8u)) | ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1); + cntr -= USBFS_EPX_CNTX_CRC_COUNT; } - return(result); + + return (cntr); } -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - - +#if (USBFS_EP_MANAGEMENT_DMA) +#if (CY_PSOC4) /******************************************************************************* - * Function Name: USBFS_InitEP_DMA - ******************************************************************************** + * Function Name: USBFS_InitEpDma + ****************************************************************************//** * - * Summary: - * This function allocates and initializes a DMA channel to be used by the - * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data - * transfer. - * - * Parameters: - * epNumber: Contains the data endpoint number. - * Valid values are between 1 and 8. - * *pData: Pointer to a data array that is related to the EP transfers. - * - * Return: - * None. - * - * Reentrant: - * No. + * This function configures priority for all DMA channels utilized by the + * component. Also sets callbacks for DMA auto mode. * *******************************************************************************/ - void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData) + static void USBFS_InitEpDma(void) + { + #if (USBFS_DMA1_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep1_dma_CHANNEL] = USBFS_ep1_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep2_dma_CHANNEL] = USBFS_ep2_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep3_dma_CHANNEL] = USBFS_ep3_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep4_dma_CHANNEL] = USBFS_ep4_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep5_dma_CHANNEL] = USBFS_ep5_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep6_dma_CHANNEL] = USBFS_ep6_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep7_dma_CHANNEL] = USBFS_ep7_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep8_dma_CHANNEL] = USBFS_ep8_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA8_ACTIVE) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Initialize DMA channel callbacks. */ + #if (USBFS_DMA1_ACTIVE) + (void) USBFS_ep1_dma_SetInterruptCallback(&USBFS_EP1_DMA_DONE_ISR); + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + (void) USBFS_ep2_dma_SetInterruptCallback(&USBFS_EP2_DMA_DONE_ISR); + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + (void) USBFS_ep3_dma_SetInterruptCallback(&USBFS_EP3_DMA_DONE_ISR); + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + (void) USBFS_ep4_dma_SetInterruptCallback(&USBFS_EP4_DMA_DONE_ISR); + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + (void) USBFS_ep5_dma_SetInterruptCallback(&USBFS_EP5_DMA_DONE_ISR); + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + (void) USBFS_ep6_dma_SetInterruptCallback(&USBFS_EP6_DMA_DONE_ISR); + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + (void) USBFS_ep7_dma_SetInterruptCallback(&USBFS_EP7_DMA_DONE_ISR); + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + (void) USBFS_ep8_dma_SetInterruptCallback(&USBFS_EP8_DMA_DONE_ISR); + #endif /* (USBFS_DMA8_ACTIVE) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } +#else + + + /*************************************************************************** + * Function Name: USBFS_InitEP_DMA + ************************************************************************//** + * + * This function allocates and initializes a DMA channel to be used by the + * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data + * transfer. It is available when the Endpoint Memory Management parameter + * is set to DMA. + * + * This function is automatically called from the USBFS_LoadInEP() and USBFS_ReadOutEP() APIs. + * + * \param epNumber Contains the data endpoint number. + * Valid values are between 1 and 8. + * \param *pData Pointer to a data array that is related to the EP transfers. + * + * \reentrant No. + * + ***************************************************************************/ + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) { uint16 src; uint16 dst; - #if (CY_PSOC3) /* PSoC 3 */ - src = HI16(CYDEV_SRAM_BASE); + + #if (CY_PSOC3) + src = HI16(CYDEV_SRAM_BASE); + dst = HI16(CYDEV_PERIPH_BASE); + pData = pData; + #else + if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u) + { + /* IN endpoint: source is memory buffer. */ + src = HI16(pData); dst = HI16(CYDEV_PERIPH_BASE); - pData = pData; - #else /* PSoC 5 */ - if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) - { /* for the IN EP source is the SRAM memory buffer */ - src = HI16(pData); - dst = HI16(CYDEV_PERIPH_BASE); - } - else - { /* for the OUT EP source is the SIE register */ - src = HI16(CYDEV_PERIPH_BASE); - dst = HI16(pData); - } - #endif /* C51 */ + } + else + { + /* OUT endpoint: source is USB IP memory buffer. */ + src = HI16(CYDEV_PERIPH_BASE); + dst = HI16(pData); + } + #endif /* (CY_PSOC3) */ + switch(epNumber) { - case USBFS_EP1: - #if(USBFS_DMA1_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA1_REMOVE */ - break; - case USBFS_EP2: - #if(USBFS_DMA2_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA2_REMOVE */ - break; + #if (USBFS_DMA1_ACTIVE) + case USBFS_EP1: + USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + case USBFS_EP2: + USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) case USBFS_EP3: - #if(USBFS_DMA3_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA3_REMOVE */ - break; + USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) case USBFS_EP4: - #if(USBFS_DMA4_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA4_REMOVE */ - break; + USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) case USBFS_EP5: - #if(USBFS_DMA5_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA5_REMOVE */ - break; - case USBFS_EP6: - #if(USBFS_DMA6_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA6_REMOVE */ - break; - case USBFS_EP7: - #if(USBFS_DMA7_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA7_REMOVE */ - break; - case USBFS_EP8: - #if(USBFS_DMA8_REMOVE == 0u) - USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( - USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); - #endif /* USBFS_DMA8_REMOVE */ - break; - default: - /* Do not support EP0 DMA transfers */ - break; + USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + case USBFS_EP6: + USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + case USBFS_EP7: + USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + case USBFS_EP8: + USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA8_ACTIVE) */ + + default: + /* Do nothing for endpoints other than 1-8. */ + break; } - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); - #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate(); - #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate(); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ } } +#endif /* (CY_PSOC4) */ - - /******************************************************************************* + /*************************************************************************** * Function Name: USBFS_Stop_DMA - ******************************************************************************** + ************************************************************************//** + * + * This function stops DMA channel associated with endpoint. It is available + * when the Endpoint Buffer Management parameter is set to DMA. Call this + * function when endpoint direction is changed from IN to OUT or vice versa + * to trigger DMA re-configuration when USBFS_LoadInEP() or + * USBFS_ReadOutEP() functions are called the first time. + * + * \param epNumber: The data endpoint number for which associated DMA + * channel is stopped. The range of valid values is between 1 and 8. To stop + * all DMAs associated with endpoints call this function with + * USBFS_MAX_EP argument. * - * Summary: Stops and free DMA - * - * Parameters: - * epNumber: Contains the data endpoint number or - * USBFS_MAX_EP to stop all DMAs - * - * Return: - * None. - * - * Reentrant: + * \reentrant * No. * - *******************************************************************************/ + ***************************************************************************/ void USBFS_Stop_DMA(uint8 epNumber) { uint8 i; + i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; + do { + #if (CY_PSOC4) + if (0u != USBFS_DmaChan[i]) + { + USBFS_CyDmaChDisable(USBFS_DmaChan[i]); + } + #else if(USBFS_DmaTd[i] != DMA_INVALID_TD) { (void) CyDmaChDisable(USBFS_DmaChan[i]); CyDmaTdFree(USBFS_DmaTd[i]); USBFS_DmaTd[i] = DMA_INVALID_TD; } - #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) if(USBFS_DmaNextTd[i] != DMA_INVALID_TD) { CyDmaTdFree(USBFS_DmaNextTd[i]); USBFS_DmaNextTd[i] = DMA_INVALID_TD; } - #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + #endif /* (CY_PSOC4) */ i++; - }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); + } + while ((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); } - -#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ -#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - - - /******************************************************************************* +#if (CY_PSOC3 || CY_PSOC5) +#if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /*************************************************************************** * Function Name: USBFS_LoadNextInEP - ******************************************************************************** + ************************************************************************//** * * Summary: * This internal function is used for IN endpoint DMA reconfiguration in @@ -944,22 +1265,19 @@ uint16 USBFS_GetEPCount(uint8 epNumber) * mode: 0 - Configure DMA to send the the rest of data. * 1 - Configure DMA to repeat 2 last bytes of the first burst. * - * Return: - * None. - * - *******************************************************************************/ + ***************************************************************************/ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) { reg16 *convert; - if(mode == 0u) + if (mode == 0u) { - /* Configure DMA to send the the rest of data */ - /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */ + /* Configure DMA to send rest of data. */ + /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; - /* Set transfer length */ + /* Set transfer length. */ CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST); - /* CyDmaTdSetAddress API is optimized to change only source address */ + /* CyDmaTdSetAddress API is optimized to change source address only. */ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + USBFS_DMA_BYTES_PER_BURST)); @@ -968,438 +1286,1110 @@ uint16 USBFS_GetEPCount(uint8 epNumber) else { /* Configure DMA to repeat 2 last bytes of the first burst. */ - /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */ + /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; - /* Set transfer length */ + /* Set transfer length. */ CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT); - /* CyDmaTdSetAddress API is optimized to change only source address */ + /* CyDmaTdSetAddress API is optimized to change source address only. */ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + - USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT)); + (USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT))); } - /* CyDmaChSetInitialTd API is optimised to init TD */ + /* CyDmaChSetInitialTd API is optimized to initialize TD. */ CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber]; } -#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ /******************************************************************************* * Function Name: USBFS_LoadInEP -******************************************************************************** +****************************************************************************//** * -* Summary: -* Loads and enables the specified USB data endpoint for an IN transfer. +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in +* the Descriptor Root in Component Configure window. * -* Parameters: -* epNumber: Contains the data endpoint number. +* *Manual (Static/Dynamic Allocation):* +* This function loads and enables the specified USB data endpoint for an IN +* data transfer. +* +* *DMA with Manual Buffer Management:* +* Configures DMA for a data transfer from system RAM to endpoint buffer. +* Generates request for a transfer. +* +* *DMA with Automatic Buffer Management:* +* Configures DMA. This is required only once, so it is done only when parameter +* pData is not NULL. When the pData pointer is NULL, the function skips this +* task. Sets Data ready status: This generates the first DMA transfer and +* prepares data in endpoint buffer. +* +* \param epNumber Contains the data endpoint number. * Valid values are between 1 and 8. -* *pData: A pointer to a data array from which the data for the endpoint space +* \param *pData A pointer to a data array from which the data for the endpoint space * is loaded. -* length: The number of bytes to transfer from the array and then send as a -* result of an IN request. Valid values are between 0 and 512. +* \param length The number of bytes to transfer from the array and then send as +* a result of an IN request. Valid values are between 0 and 512 +* (1023 for DMA with Automatic Buffer Management mode). The value 512 +* is applicable if only one endpoint is used. * -* Return: -* None. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) { - uint8 ri; - reg8 *p; - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - uint16 i; - #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Limit length to available buffer USB IP buffer size.*/ + if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */ - if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + /* Set count and data toggle. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint8) HI8(length) | USBFS_EP[epNumber].epToggle; + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint8) LO8(length); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + if (NULL != pData) + { + /* Copy data using arbiter data register. */ + uint16 i; + for (i = 0u; i < length; ++i) { - length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr = pData[i]; } - #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + } - /* Set the count and data toggle */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - (length >> 8u) | (USBFS_EP[epNumber].epToggle)); - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu); + /* IN endpoint buffer is full - read to be read. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - if(pData != NULL) - { - /* Copy the data using the arbiter data register */ - for (i = 0u; i < length; i++) - { - CY_SET_REG8(p, pData[i]); - } - } - USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); - #else - /* Init DMA if it was not initialized */ - if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + #else + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Initialize DMA if it was not initialized. */ + if (DMA_INVALID_TD == USBFS_DmaTd[epNumber]) { USBFS_InitEP_DMA(epNumber, pData); } - #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* IN endpoint buffer will be fully loaded by DMA shortly. */ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if ((pData != NULL) && (length > 0u)) { - /* Enable DMA in mode2 for transferring data */ + #if (CY_PSOC4) + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + /* Configure DMA descriptor. */ + --length; + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + #else + /* Configure DMA to transfer data. */ (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, - TD_TERMIN_EN | TD_INC_SRC_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); - /* Enable the DMA */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + + /* Enable DMA channel. */ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - /* Generate DMA request */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); - /* Mode register will be written in arb ISR after DMA transfer complete */ + #endif /* (CY_PSOC4) */ + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ } else { - /* When zero-length packet - write the Mode register directly */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; } - #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) if (pData != NULL) { - /* Enable DMA in mode3 for transferring data */ - (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - #if (USBFS_EP_DMA_AUTO_OPT == 0u) - USBFS_inLength[epNumber] = length; - USBFS_inDataPointer[epNumber] = pData; - /* Configure DMA to send the data only for the first burst */ - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], - (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length, - USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); - /* The second TD will be executed only when the first one fails. - * The intention of this TD is to generate NRQ interrupt - * and repeat 2 last bytes of the first burst. - */ - (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u, - USBFS_DmaNextTd[epNumber], - USBFS_epX_TD_TERMOUT_EN[epNumber]); - /* Configure DmaNextTd to clear Data ready status */ - (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus), - LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri))); - #else /* Configure DMA to send all data*/ - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, - USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); - #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */ + #if (CY_PSOC4) + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; - /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + /* Store address of buffer. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #else + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inDataPointer[epNumber] = pData; + + /* Configure DMA to send data only for first burst */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], + (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + + /* The second TD will be executed only when the first one fails. + * The intention of this TD is to generate NRQ interrupt + * and repeat 2 last bytes of the first burst. + */ + (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u, + USBFS_DmaNextTd[epNumber], + USBFS_epX_TD_TERMOUT_EN[epNumber]); + + /* Configure DmaNextTd to clear Data Ready status. */ + (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32) &clearInDataRdyStatus), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg)); + #else + /* Configure DMA to send all data. */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, + USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + + /* Clear any potential pending DMA requests before starting DMA channel to transfer data. */ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); - /* Enable the DMA */ + /* Enable DMA. */ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ } else { + /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - if(length > 0u) + + if (length > 0u) { - #if (USBFS_EP_DMA_AUTO_OPT == 0u) - USBFS_inLength[epNumber] = length; + #if (CY_PSOC4) + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + (USBFS_DmaEpLastBurstEl[epNumber] - 1u) : + (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + + + /* Mark which descriptor is last one to execute. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Restore DMA settings for current transfer. */ + USBFS_CyDmaChDisable(channelNum); + + /* Restore destination address for input endpoint. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber])); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Set number of elements to transfer. */ + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0); + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1); + + /* Validate descriptor 0 and command to start with it. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Validate descriptor 1. */ + if (USBFS_DmaEpBurstCnt[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #elif (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; USBFS_inBufFull[epNumber] = 0u; + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - /* Configure DMA to send the data only for the first burst */ + /* Configure DMA to send data only for first burst. */ (void) CyDmaTdSetConfiguration( USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length, USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR ); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], - LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p)); - /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) USBFS_inDataPointer[epNumber]), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); - /* Enable the DMA */ + /* Enable DMA. */ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + #endif /* (CY_PSOC4) */ - /* Set Data ready status, This will generate DMA request */ - #ifndef USBFS_MANUAL_IN_EP_ARM - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; - #endif /* USBFS_MANUAL_IN_EP_ARM */ - /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */ + #if !defined (USBFS_MANUAL_IN_EP_ARM) + /* Set IN data ready to generate DMA request to load data into endpoint buffer. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* (USBFS_MANUAL_IN_EP_ARM) */ + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ } else { - /* When zero-length packet - write the Mode register directly */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; } } - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ } } /******************************************************************************* * Function Name: USBFS_ReadOutEP -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read data from an endpoint. The application must call -* USBFS_GetEPState to see if an event is pending. +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in the +* Descriptor Root in Component Configure window. * -* Parameters: -* epNumber: Contains the data endpoint number. +* *Manual (Static/Dynamic Allocation):* +* This function moves the specified number of bytes from endpoint buffer to +* system RAM. The number of bytes actually transferred from endpoint buffer to +* system RAM is the lesser of the actual number of bytes sent by the host or +* the number of bytes requested by the length parameter. +* +* *DMA with Manual Buffer Management:* +* Configure DMA to transfer data from endpoint buffer to system RAM. Generate +* a DMA request. The firmware must wait until the DMA completes the data +* transfer after calling the USBFS_ReadOutEP() API. For example, +* by checking EPstate: +* +* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey +* +* The USBFS_EnableOutEP() has to be called to allow host to write data into +* the endpoint buffer after DMA has completed transfer data from OUT endpoint +* buffer to SRAM. +* +* *DMA with Automatic Buffer Management:* +* Configure DMA. This is required only once and automatically generates DMA +* requests as data arrives +* +* \param epNumber: Contains the data endpoint number. * Valid values are between 1 and 8. -* pData: A pointer to a data array from which the data for the endpoint space -* is loaded. -* length: The number of bytes to transfer from the USB Out endpoint and loads -* it into data array. Valid values are between 0 and 1023. The function -* moves fewer than the requested number of bytes if the host sends -* fewer bytes than requested. +* \param pData: A pointer to a data array from which the data for the endpoint +* space is loaded. +* \param length: The number of bytes to transfer from the USB Out endpoint and +* loads it into data array. Valid values are between 0 and 1023. The +* function moves fewer than the requested number of bytes if the host +* sends fewer bytes than requested. * -* Returns: +* \return * Number of bytes received, 0 for an invalid endpoint. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) { - uint8 ri; - reg8 *p; - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - uint16 i; - #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - uint16 xferCount; - #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) + if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Adjust requested length to available data. */ + length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - /* Determine which is smaller the requested data or the available data */ - xferCount = USBFS_GetEPCount(epNumber); - if (length > xferCount) + #if (USBFS_EP_MANAGEMENT_MANUAL) + { + /* Copy data using arbiter data register. */ + uint16 i; + for (i = 0u; i < length; ++i) { - length = xferCount; + pData[i] = (uint8) USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr; } - #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + } - #if(USBFS_EP_MM == USBFS__EP_MANUAL) - /* Copy the data using the arbiter data register */ - for (i = 0u; i < length; i++) - { - pData[i] = CY_GET_REG8(p); - } + /* Arm OUT endpoint after data has been copied from endpoint buffer. */ + USBFS_EnableOutEP(epNumber); + #else - /* (re)arming of OUT endpoint */ - USBFS_EnableOutEP(epNumber); - #else - /*Init DMA if it was not initialized */ - if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + #if (CY_PSOC3 || CY_PSOC5LP) + /* Initialize DMA if it was not initialized. */ + if (DMA_INVALID_TD == USBFS_DmaTd[epNumber]) { USBFS_InitEP_DMA(epNumber, pData); } + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ - #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + #if (CY_PSOC4) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - /* Enable DMA in mode2 for transferring data */ + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)(length - 1u) | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + #else + /* Configure DMA to transfer data. */ (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, - TD_TERMIN_EN | TD_INC_DST_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); - /* Enable the DMA */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32)pData)); + + /* Enable DMA channel. */ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ - /* Generate DMA request */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); - /* Out EP will be (re)armed in arb ISR after transfer complete */ - #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ; - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* Enable DMA in mode3 for transferring data */ + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + uint32 lengthDescr0, lengthDescr1; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of the data elements transfered in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + (USBFS_DmaEpLastBurstEl[epNumber] - 1u) : + (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Mark if revert number of data elements in descriptor after transfer completion. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u; + + /* Mark last descriptor to be executed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Store address of buffer and burst counter for endpoint. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber]; + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData)); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST)); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Validate DMA descriptor 0 and 1. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + #else (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); - (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], - TD_TERMIN_EN | TD_INC_DST_ADR); - (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32) pData)); - /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); - /* Enable the DMA */ + + /* Enable DMA channel. */ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); - /* Out EP will be (re)armed in arb ISR after transfer complete */ - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* (CY_PSOC4) */ + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ } else { length = 0u; } - return(length); + return (length); +} + + +#if (USBFS_16BITS_EP_ACCESS_ENABLE) +/******************************************************************************* +* Function Name: USBFS_LoadInEP16 +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in +* the Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function loads and enables the specified USB data endpoint for an IN +* data transfer. +* +* *DMA with Manual Buffer Management:* +* Configures DMA for a data transfer from system RAM to endpoint buffer. +* Generates request for a transfer. +* +* *DMA with Automatic Buffer Management:* +* Configures DMA. This is required only once, so it is done only when parameter +* pData is not NULL. When the pData pointer is NULL, the function skips this +* task. Sets Data ready status: This generates the first DMA transfer and +* prepares data in endpoint buffer. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param *pData A pointer to a data array from which the data for the endpoint +* space is loaded. It shall be ensured that this pointer address is even +* to ensure the 16-bit transfer is aligned to even address. Else, a hard +* fault condition can occur. +* \param length The number of bytes to transfer from the array and then send as +* a result of an IN request. Valid values are between 0 and 512 (1023 for +* DMA with Automatic Buffer Management mode). The value 512 is applicable +* if only one endpoint is used. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP16(uint8 epNumber, const uint8 pData[], uint16 length) +{ + /* Check array alignment on half-word boundary. */ + CYASSERT(0u == (((uint32) pData) & 0x01u)); + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Limit length to available buffer USB IP buffer size. */ + if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Set count and data toggle. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint32) HI8(length) | USBFS_EP[epNumber].epToggle; + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint32) LO8(length); + + /* Adjust requested length: 2 bytes are handled at one data register access. */ + length += (length & 0x01u); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + if (NULL != pData) + { + /* Convert uint8 array to uint16. */ + const uint16 *dataBuf = (uint16 *) pData; + + /* Copy data using 16-bits arbiter data register. */ + uint16 i; + for (i = 0u; i < (length >> 1u); ++i) + { + USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16 = dataBuf[i]; + } + } + + /* IN endpoint buffer is full - read to be read. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + #else + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* IN endpoint buffer will be fully loaded by DMA shortly. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if ((pData != NULL) && (length > 0u)) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + /* Configure DMA descriptor. */ + length = (length >> 1u) - 1u; + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + if (pData != NULL) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Store address of buffer. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + else + { + /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if (length > 0u) + { + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) : + (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Mark which descriptor is last one to execute. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Restore DMA settings for current transfer. */ + USBFS_CyDmaChDisable(channelNum); + + /* Restore destination address for input endpoint. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber])); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Set number of elements to transfer. */ + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0); + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1); + + /* Validate descriptor 0 and command to start with it. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Validate descriptor 1. */ + if (USBFS_DmaEpBurstCnt[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #if !defined (USBFS_MANUAL_IN_EP_ARM) + /* Set IN data ready to generate DMA request to load data into endpoint buffer. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* (USBFS_MANUAL_IN_EP_ARM) */ + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } } +/******************************************************************************* +* Function Name: USBFS_ReadOutEP16 +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in the +* Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function moves the specified number of bytes from endpoint buffer to +* system RAM. The number of bytes actually transferred from endpoint buffer to +* system RAM is the lesser of the actual number of bytes sent by the host or +* the number of bytes requested by the length parameter. +* +* *DMA with Manual Buffer Management:* +* Configure DMA to transfer data from endpoint buffer to system RAM. Generate +* a DMA request. The firmware must wait until the DMA completes the data +* transfer after calling the USBFS_ReadOutEP() API. For example, +* by checking EPstate: +* +* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey +* +* The USBFS_EnableOutEP() has to be called to allow host to write data into +* the endpoint buffer after DMA has completed transfer data from OUT endpoint +* buffer to SRAM. +* +* *DMA with Automatic Buffer Management:* +* Configure DMA. This is required only once and automatically generates DMA +* requests as data arrives +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param pData: A pointer to a data array into which the data for the endpoint +* space is copied. It shall be ensured that this pointer address is +* even to ensure the 16-bit transfer is aligned to even address. Else, +* a hard fault condition can occur. +* \param length: The number of bytes to transfer from the USB Out endpoint and +* loads it into data array. Valid values are between 0 and 1023. The +* function moves fewer than the requested number of bytes if the host +* sends fewer bytes than requested. +* +* \return +* Number of bytes received, 0 for an invalid endpoint. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length) +{ + uint32 adjLength; + + /* Check array alignment on half-word boundary */ + CYASSERT(0u == (((uint32) pData) & 0x01u)); + + if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Adjust requested length to available data. */ + length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Adjust requested length: 2 bytes are handled at one data register access. */ + adjLength = length + ((uint32)length & 1u); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + { + /* Convert uint8 array to uint16. */ + uint16 *dataBuf = (uint16 *) pData; + + /* Copy data using 16-bits arbiter data register. */ + uint16 i; + for (i = 0u; i < (adjLength >> 1u); ++i) + { + dataBuf[i] = (uint16) USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16; + } + } + + /* Arm OUT endpoint after data has been read from endpoint buffer. */ + USBFS_EnableOutEP(epNumber); + #else + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)((adjLength >> 1u) - 1u) | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + { + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (adjLength / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (adjLength % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) : + (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Mark last descriptor to be executed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Mark if revert number of data elements in descriptor after transfer completion. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u; + + /* Mark that 16-bits access to data register is performed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= USBFS_DMA_DESCR_16BITS; + + /* Store address of buffer and burst counter for endpoint. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber]; + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData)); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST)); + + /* Configure DMA descriptor 0. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor 1. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Validate DMA descriptor 0 and 1. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } + else + { + length = 0u; + } + + return (length); +} +#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */ + + /******************************************************************************* * Function Name: USBFS_EnableOutEP -******************************************************************************** +****************************************************************************//** * -* Summary: -* This function enables an OUT endpoint. It should not be -* called for an IN endpoint. +* This function enables the specified endpoint for OUT transfers. Do not call +* this function for IN endpoints. * -* Parameters: -* epNumber: Endpoint Number -* Valid values are between 1 and 8. +* \param epNumber: Contains the data endpoint number. Valid values are between +* 1 and 8. * -* Return: -* None. +* \globalvars * -* Global variables: -* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING +* \ref USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_EnableOutEP(uint8 epNumber) { - uint8 ri; - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + + /* Enable OUT endpoint to be written by Host. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } } /******************************************************************************* * Function Name: USBFS_DisableOutEP -******************************************************************************** +****************************************************************************//** * -* Summary: -* This function disables an OUT endpoint. It should not be -* called for an IN endpoint. +* This function disables the specified USBFS OUT endpoint. Do not call this +* function for IN endpoints. * -* Parameters: -* epNumber: Endpoint Number +* \param epNumber: Contains the data endpoint number. * Valid values are between 1 and 8. * -* Return: -* None. -* *******************************************************************************/ void USBFS_DisableOutEP(uint8 epNumber) { - uint8 ri ; - - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + /* Set NAK response for OUT endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT; } } /******************************************************************************* * Function Name: USBFS_Force -******************************************************************************** +****************************************************************************//** * -* Summary: -* Forces the bus state +* This function forces a USB J, K, or SE0 state on the D+/D– lines. It provides +* the necessary mechanism for a USB device application to perform a USB Remote +* Wakeup. For more information, see the USB 2.0 Specification for details on +* Suspend and Resume. * -* Parameters: -* bState -* USBFS_FORCE_J -* USBFS_FORCE_K -* USBFS_FORCE_SE0 -* USBFS_FORCE_NONE +* \param state A byte indicating which of the four bus states to enable. +* Symbolic names and their associated values are listed here: +* State |Description +* ---------------------------|---------------------------------------------- +* USBFS_FORCE_J | Force a J State onto the D+/D– lines +* USBFS_FORCE_K | Force a K State onto the D+/D– lines +* USBFS_FORCE_SE0 | Force a Single Ended 0 onto the D+/D– lines +* USBFS_FORCE_NONE| Return bus to SIE control * -* Return: -* None. * *******************************************************************************/ void USBFS_Force(uint8 bState) { - CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState); + /* This registers is used only for manual control of SIE (no masking is + * needed before write into it). + */ + USBFS_USBIO_CR0_REG = bState; } /******************************************************************************* * Function Name: USBFS_GetEPAckState -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the ACK of the CR0 Register (ACKD) +* This function determines whether an ACK transaction occurred on this endpoint +* by reading the ACK bit in the control register of the endpoint. It does not +* clear the ACK bit. * -* Parameters: -* epNumber: Endpoint Number +* \param epNumber Contains the data endpoint number. * Valid values are between 1 and 8. * -* Returns -* 0 if nothing has been ACKD, non-=zero something has been ACKD +* \return +* If an ACKed transaction occurred, this function returns a non-zero value. +* Otherwise, it returns zero. * *******************************************************************************/ uint8 USBFS_GetEPAckState(uint8 epNumber) { - uint8 ri; uint8 cr = 0u; - if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { - ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD; + cr = USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 & USBFS_MODE_ACKD; } - return(cr); + return ((uint8) cr); } /******************************************************************************* * Function Name: USBFS_SetPowerStatus -******************************************************************************** +****************************************************************************//** * -* Summary: -* Sets the device power status for reporting in the Get Device Status -* request +* This function sets the current power status. The device replies to USB +* GET_STATUS requests based on this value. This allows the device to properly +* report its status for USB Chapter 9 compliance. Devices can change their +* power source from self powered to bus powered at any time and report their +* current power source as part of the device status. You should call this +* function any time your device changes from self powered to bus powered or +* vice versa, and set the status appropriately. * -* Parameters: -* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered, -* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered +* \param powerStatus: Contains the desired power status, one for self powered +* or zero for bus powered. Symbolic names and their associated values are +* given here: +* Power Status |Description +* --------------------------------------------|--------------------------- +* USBFS_DEVICE_STATUS_BUS_POWERED | Set the device to bus powered +* USBFS_DEVICE_STATUS_SELF_POWERED | Set the device to self powered * -* Return: -* None. +* \globalvars * -* Global variables: -* USBFS_deviceStatus - set power status +* \ref USBFS_deviceStatus - set power status * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -1407,67 +2397,424 @@ void USBFS_SetPowerStatus(uint8 powerStatus) { if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) { - USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED; } else { - USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED)); + USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED; } } -#if (USBFS_MON_VBUS == 1u) - - /******************************************************************************* +#if (USBFS_VBUS_MONITORING_ENABLE) + /*************************************************************************** * Function Name: USBFS_VBusPresent - ******************************************************************************** + ************************************************************************//** * - * Summary: - * Determines VBUS presence for Self Powered Devices. + * Determines VBUS presence for self-powered devices. This function is + * available when the VBUS Monitoring option is enabled in the Advanced tab. * - * Parameters: - * None. + * \return + * The return value can be the following: + * Return Value | Description + * -------------|----------------- + * 1 | VBUS is present + * 0 | VBUS is absent * - * Return: - * 1 if VBUS is present, otherwise 0. * - *******************************************************************************/ + ***************************************************************************/ uint8 USBFS_VBusPresent(void) { - return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u); + return ((0u != (USBFS_VBUS_STATUS_REG & USBFS_VBUS_VALID)) ? (uint8) 1u : (uint8) 0u); } - -#endif /* USBFS_MON_VBUS */ +#endif /* (USBFS_VBUS_MONITORING_ENABLE) */ /******************************************************************************* * Function Name: USBFS_RWUEnabled -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE +* This function returns the current remote wakeup status. +* If the device supports remote wakeup, the application should use this +* function to determine if remote wakeup was enabled by the host. When the +* device is suspended and it determines the conditions to initiate a remote +* wakeup are met, the application should use the USBFS_Force() function to +* force the appropriate J and K states onto the USB bus, signaling a remote +* wakeup. * -* Parameters: -* None. * -* Return: -* TRUE - Remote Wake Up Enabled -* FALSE - Remote Wake Up Disabled +* \return +* Returns non-zero value if remote wakeup is enabled and zero otherwise. * -* Global variables: +* \globalvars * USBFS_deviceStatus - checked to determine remote status * *******************************************************************************/ uint8 USBFS_RWUEnabled(void) { uint8 result = USBFS_FALSE; - if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u) + + if (0u != (USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP)) { result = USBFS_TRUE; } - return(result); + return (result); } +/******************************************************************************* +* Function Name: USBFS_GetDeviceAddress +****************************************************************************//** +* +* This function returns the currently assigned address for the USB device. +* +* \return +* Returns the currently assigned address. +* Returns 0 if the device has not yet been assigned an address. +* +*******************************************************************************/ +uint8 USBFS_GetDeviceAddress(void) +{ + return (uint8)(USBFS_CR0_REG & USBFS_CR0_DEVICE_ADDRESS_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_EnableSofInt +****************************************************************************//** +* +* This function enables interrupt generation when a Start-of-Frame (SOF) +* packet is received from the host. +* +*******************************************************************************/ +void USBFS_EnableSofInt(void) +{ +#if (CY_PSOC4) + /* Enable SOF interrupt interrupt source. */ + USBFS_INTR_SIE_MASK_REG |= (uint32) USBFS_INTR_SIE_SOF_INTR; +#else + /* Enable SOF interrupt if it is present. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntEnable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ +} + + +/******************************************************************************* +* Function Name: USBFS_DisableSofInt +****************************************************************************//** +* +* This function disables interrupt generation when a Start-of-Frame (SOF) +* packet is received from the host. +* +*******************************************************************************/ +void USBFS_DisableSofInt(void) +{ +#if (CY_PSOC4) + /* Disable SOF interrupt interrupt source. */ + USBFS_INTR_SIE_MASK_REG &= (uint32) ~USBFS_INTR_SIE_SOF_INTR; +#else + /* Disable SOF interrupt if it is present. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntDisable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ +} + + +#if (USBFS_BATT_CHARG_DET_ENABLE) + /*************************************************************************** + * Function Name: USBFS_DetectPortType + ************************************************************************//** + * + * This function implements the USB Battery Charger Detection (BCD) + * algorithm to determine the type of USB host downstream port. This API + * is available only for PSoC 4 devices, and should be called when the VBUS + * voltage transition (OFF to ON) is detected on the bus. If the USB device + * functionality is enabled, this API first calls USBFS_Stop() API + * internally to disable the USB device functionality, and then proceeds to + * implement the BCD algorithm to detect the USB host port type. + * The USBFS_Start() API should be called after this API if the USB + * communication needs to be initiated with the host. + * *Note* This API is generated only if the “Enable Battery Charging + * Detection” option is enabled in the “Advanced” tab of the component GUI. + * *Note* API implements the steps 2-4 of the BCD algorithm which are + * - Data Contact Detect + * - Primary Detection + * - Secondary Detection + * + * The first step of BCD algorithm, namely, VBUS detection shall be handled + * at the application firmware level. + * + * \return + * The return value can be the following: + * Return Value |Description + * ----------------------------------|------------------------------------- + * USBFS_BCD_PORT_SDP | Standard downstream port detected + * USBFS_BCD_PORT_CDP | Charging downstream port detected + * USBFS_BCD_PORT_DCP | Dedicated charging port detected + * USBFS_BCD_PORT_UNKNOWN | Unable to detect charging port type (proprietary charger type) + * USBFS_BCD_PORT_ERR | Error condition in detection process + * + * + * \sideeffects + * + * USB device functionality is disabled by this API if not already disabled. + * + ***************************************************************************/ + uint8 USBFS_Bcd_DetectPortType(void) + { + uint32 bkPwrCtrl; + uint32 cr1RegVal; + uint32 secondaryDetection = 0u; + uint8 result = USBFS_BCD_PORT_UNKNOWN; + + /*Check USB Started and Stop it*/ + if(0u != USBFS_initVar) + { + USBFS_Stop(); + } + /*Initialize USBFS IP for Charger detection*/ + + /*Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN; + + /* Enable USBIO control on drive mode of D+ and D- pins. */ + USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE; + + /* Select VBUS detection source and clear PHY isolate. The application + * level must ensure that VBUS is valid. There is no need to wait 2us + * before VBUS is valid. + */ + bkPwrCtrl = USBFS_POWER_CTRL_REG; + USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS\ + & (~USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN)\ + & (~USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN); + + + /* Enable PHY detector and single-ended and differential receivers. + * Enable charger detection. */ + USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY\ + | USBFS_POWER_CTRL_ENABLE_CHGDET; + + /* Suspend clear sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + /* Data connection detection + * Realization with delay as Hard IP does not support DCD 300 ms. + */ + #if defined (USBFS_NO_DCD) + CyDelay(USBFS_BCD_TIMEOUT); + #else + /* DCD implementation:*/ + + { + uint16 timeout = USBFS_BCD_TIMEOUT; + uint8 connectionApproved = 0u; + uint8 connected = 0u; + + /* BCD spec 1.2: Turns on Idp_src and D- pull-down resistor */ + USBFS_POWER_CTRL_REG |= USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN; + USBFS_CHGDET_CTRL_REG |= USBFS_CHGDET_CTRL_DCD_SRC_EN; + + /* BCD spec 1.2: Waits for D+ to be low for a time of Tdcd_dbnc*/ + while ((0u != timeout) && (0u == connectionApproved)) + { + if (0u == (USBFS_USBIO_CR1_REG & USBFS_USBIO_CR1_DP0)) + { + connected++; + } + else + { + connected = 0u; + } + connectionApproved = (USBFS_BCD_TDCD_DBNC < connected) ? 1u:0u; + CyDelay(1u); + timeout--; + } + + /* BCD spec 1.2: Turns off Idp_src. */ + USBFS_CHGDET_CTRL_REG &= ~USBFS_CHGDET_CTRL_DCD_SRC_EN; + } + #endif /*(USBFS_NO_DCD)*/ + + /* Primary detection: enable VDP_SRC on D+ and IDM_SINK on D-. */ + USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_PRIMARY; + CyDelay(USBFS_BCD_PRIMARY_WAIT); + cr1RegVal = USBFS_USBIO_CR1_REG; + + /* Check is it SDP or DCP/CDP, read comparator 2 output. */ + if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT)) + { + /* Check status of D- line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DM0)) + { + result = USBFS_BCD_PORT_SDP; + } + else + { + /* ERROR: such combination is impossible. Abort charger + * detection. + */ + result = USBFS_BCD_PORT_ERR; + } + } + else + { + /* Need Secondary detection. Charging port: DCP or proprietary*/ + secondaryDetection = 1u; + } + + /* Secondary detection: Set CHGDET_CTRL register to enable VDM_SRC on D- and IDP_SINK on D+. */ + + if (0u != secondaryDetection) + { + USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_DEFAULT \ + | USBFS_CHGDET_CTRL_SECONDARY; + CyDelay(USBFS_BCD_SECONDARY_WAIT); + cr1RegVal = USBFS_USBIO_CR1_REG; + + /* Check is it SDP or DCP/CDP, read comparator 1 output. */ + if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT)) + { + /* Check status of D+ line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0)) + { + result = USBFS_BCD_PORT_CDP; + } + else + { + /* ERROR: such combination is impossible. Abort charger + * detection. + */ + result = USBFS_BCD_PORT_ERR; + } + } + else + { + /* Check status of D+ line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0)) + { + result = USBFS_BCD_PORT_DCP; + } + else + { + /* It is may be proprietary charger. Proprietary charge is + * not supported byHardware IP block. + */ + result = USBFS_BCD_PORT_UNKNOWN; + } + } + } + + /* Restore CHGDET_CTRL. */ + USBFS_CHGDET_CTRL_REG = 0u; + + /*Revert registers back*/ + USBFS_POWER_CTRL_REG = bkPwrCtrl; + USBFS_USBIO_CR1_REG |= (uint32) USBFS_USBIO_CR1_IOMODE; + USBFS_USB_CLK_EN_REG = ~USBFS_USB_CLK_CSR_CLK_EN; + + return (result); + } +#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */ + + +#if (USBFS_LPM_ACTIVE) + /*************************************************************************** + * Function Name: USBFS_Lpm_GetBeslValue + ************************************************************************//** + * + * This function returns the Best Effort Service Latency (BESL) value + * sent by the host as part of the LPM token transaction. + * + * \return + * 4-bit BESL value received in the LPM token packet from the host + * + * + ***************************************************************************/ + uint32 USBFS_Lpm_GetBeslValue(void) + { + return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_BESL_MASK); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_RemoteWakeUpAllowed + ************************************************************************//** + * + * This function returns the remote wakeup permission set for the device by + * the host as part of the LPM token transaction. + * + * \return + * 0 - remote wakeup not allowed, 1 - remote wakeup allowed + * + * + ***************************************************************************/ + uint32 USBFS_Lpm_RemoteWakeUpAllowed(void) + { + return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_REMOTE_WAKE); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_SetResponse + ************************************************************************//** + * + * This function configures the response in the handshake packet the device + * has to send when an LPM token packet is received. + * + * \param response + * type of response to return for an LPM token packet + * Allowed response values: + * - USBFS_LPM_REQ_ACK - next LPM request will be + * responded with ACK + * - USBFS_LPM_REQ_NACK - next LPM request will be + * responded with NACK + * - USBFS_LPM_REQ_NYET - next LPM request will be + * responded with NYET + * + ***************************************************************************/ + void USBFS_Lpm_SetResponse(uint32 response) + { + uint32 lpmCtrl = USBFS_LPM_CTRL_REG & (uint32) ~USBFS_LPM_CTRL_ACK_NYET_MASK; + + USBFS_LPM_CTRL_REG = lpmCtrl | ((uint32) response & USBFS_LPM_CTRL_ACK_NYET_MASK); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_GetResponse + ************************************************************************//** + * + * This function returns the currently configured response value that the + * device will send as part of the handshake packet when an LPM token + * packet is received. + * + * \return + * type of handshake response that will be returned by the device + * for an LPM token packet + * Possible response values: + * - USBFS_LPM_REQ_ACK - next LPM request will be responded + * with ACK + * - USBFS_LPM_REQ_NACK - next LPM request will be responded + * with NACK + * - USBFS_LPM_REQ_NYET - next LPM request will be responded + * with NYET + * + ***************************************************************************/ + uint32 USBFS_Lpm_GetResponse(void) + { + + return ((uint32) USBFS_LPM_CTRL_REG & (uint32)USBFS_LPM_CTRL_ACK_NYET_MASK); + } + + +#endif /* (USBFS_LPM_ACTIVE) */ + + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h old mode 100644 new mode 100755 index 08a00ea..fc94251 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h @@ -1,12 +1,13 @@ -/******************************************************************************* -* File Name: USBFS.h -* Version 2.80 +/***************************************************************************//** +* \file USBFS.h +* \version 3.10 * -* Description: -* Header File for the USBFS component. Contains prototypes and constant values. +* \brief +* This file provides function prototypes and constants for the USBFS component. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -15,120 +16,139 @@ #if !defined(CY_USBFS_USBFS_H) #define CY_USBFS_USBFS_H -#include "cytypes.h" #include "cydevice_trm.h" #include "cyfitter.h" +#include "cytypes.h" #include "CyLib.h" + /* User supplied definitions. */ /* `#START USER_DEFINITIONS` Place your declaration here */ /* `#END` */ - -/*************************************** -* Conditional Compilation Parameters -***************************************/ - -/* Check to see if required defines such as CY_PSOC5LP are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5LP) - #error Component USBFS_v2_80 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5LP) */ - - -/*************************************** -* Memory Type Definitions -***************************************/ - -/* Renamed Type Definitions for backward compatibility. -* Should not be used in new designs. -*/ -#define USBFS_CODE CYCODE -#define USBFS_FAR CYFAR -#if defined(__C51__) || defined(__CX51__) - #define USBFS_DATA data - #define USBFS_XDATA xdata -#else - #define USBFS_DATA - #define USBFS_XDATA -#endif /* __C51__ */ -#define USBFS_NULL NULL - - /*************************************** * Enumerated Types and Parameters ***************************************/ -#define USBFS__EP_MANUAL 0 -#define USBFS__EP_DMAMANUAL 1 -#define USBFS__EP_DMAAUTO 2 - -#define USBFS__MA_STATIC 0 -#define USBFS__MA_DYNAMIC 1 +/* USB IP memory management options. */ +#define USBFS__EP_MANUAL (0u) +#define USBFS__EP_DMAMANUAL (1u) +#define USBFS__EP_DMAAUTO (2u) +/* USB IP memory allocation options. */ +#define USBFS__MA_STATIC (0u) +#define USBFS__MA_DYNAMIC (1u) /*************************************** * Initial Parameter Constants ***************************************/ -#define USBFS_NUM_DEVICES (1u) -#define USBFS_ENABLE_DESCRIPTOR_STRINGS -#define USBFS_ENABLE_SN_STRING -#define USBFS_ENABLE_STRINGS -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u) -#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u) -#define USBFS_ENABLE_HID_CLASS -#define USBFS_HID_RPT_1_SIZE_LSB (0x25u) -#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) -#define USBFS_HID_RPT_2_SIZE_LSB (0x25u) -#define USBFS_HID_RPT_2_SIZE_MSB (0x00u) -#define USBFS_MAX_REPORTID_NUMBER (0u) +#define USBFS_NUM_DEVICES (1u) +#define USBFS_ENABLE_MIDI_CLASS (0u) +#define USBFS_ENABLE_MSC_CLASS (0u) +#define USBFS_BOS_ENABLE (0u) +#define USBFS_ENABLE_DESCRIPTOR_STRINGS +#define USBFS_ENABLE_SN_STRING +#define USBFS_ENABLE_STRINGS +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u) +#define USBFS_ENABLE_HID_CLASS +#define USBFS_HID_RPT_1_SIZE_LSB (0x25u) +#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) +#define USBFS_HID_RPT_2_SIZE_LSB (0x25u) +#define USBFS_HID_RPT_2_SIZE_MSB (0x00u) +#define USBFS_MAX_REPORTID_NUMBER (0u) -#define USBFS_MON_VBUS (0u) -#define USBFS_EXTERN_VBUS (0u) -#define USBFS_EXTERN_VND (0u) -#define USBFS_EXTERN_CLS (0u) -#define USBFS_MAX_INTERFACES_NUMBER (2u) -#define USBFS_EP0_ISR_REMOVE (0u) -#define USBFS_EP1_ISR_REMOVE (0u) -#define USBFS_EP2_ISR_REMOVE (0u) -#define USBFS_EP3_ISR_REMOVE (0u) -#define USBFS_EP4_ISR_REMOVE (0u) -#define USBFS_EP5_ISR_REMOVE (1u) -#define USBFS_EP6_ISR_REMOVE (1u) -#define USBFS_EP7_ISR_REMOVE (1u) -#define USBFS_EP8_ISR_REMOVE (1u) -#define USBFS_EP_MM (0u) -#define USBFS_EP_MA (0u) -#define USBFS_EP_DMA_AUTO_OPT (0u) -#define USBFS_DMA1_REMOVE (1u) -#define USBFS_DMA2_REMOVE (1u) -#define USBFS_DMA3_REMOVE (1u) -#define USBFS_DMA4_REMOVE (1u) -#define USBFS_DMA5_REMOVE (1u) -#define USBFS_DMA6_REMOVE (1u) -#define USBFS_DMA7_REMOVE (1u) -#define USBFS_DMA8_REMOVE (1u) -#define USBFS_SOF_ISR_REMOVE (0u) -#define USBFS_ARB_ISR_REMOVE (0u) -#define USBFS_DP_ISR_REMOVE (0u) -#define USBFS_ENABLE_CDC_CLASS_API (1u) -#define USBFS_ENABLE_MIDI_API (1u) -#define USBFS_MIDI_EXT_MODE (0u) +#define USBFS_MON_VBUS (0u) +#define USBFS_EXTERN_VBUS (0u) +#define USBFS_POWER_PAD_VBUS (0u) +#define USBFS_EXTERN_VND (0u) +#define USBFS_EXTERN_CLS (0u) +#define USBFS_MAX_INTERFACES_NUMBER (2u) +#define USBFS_EP_MM (0u) +#define USBFS_EP_MA (0u) +#define USBFS_ENABLE_BATT_CHARG_DET (0u) +#define USBFS_GEN_16BITS_EP_ACCESS (0u) + +/* Enable Class APIs: MIDI, CDC, MSC. */ +#define USBFS_ENABLE_CDC_CLASS_API (0u != (1u)) + +/* General parameters */ +#define USBFS_EP_ALLOC_STATIC (USBFS_EP_MA == USBFS__MA_STATIC) +#define USBFS_EP_ALLOC_DYNAMIC (USBFS_EP_MA == USBFS__MA_DYNAMIC) +#define USBFS_EP_MANAGEMENT_MANUAL (USBFS_EP_MM == USBFS__EP_MANUAL) +#define USBFS_EP_MANAGEMENT_DMA (USBFS_EP_MM != USBFS__EP_MANUAL) +#define USBFS_EP_MANAGEMENT_DMA_MANUAL (USBFS_EP_MM == USBFS__EP_DMAMANUAL) +#define USBFS_EP_MANAGEMENT_DMA_AUTO (USBFS_EP_MM == USBFS__EP_DMAAUTO) +#define USBFS_BATT_CHARG_DET_ENABLE (CY_PSOC4 && (0u != USBFS_ENABLE_BATT_CHARG_DET)) +#define USBFS_16BITS_EP_ACCESS_ENABLE (CY_PSOC4 && (0u != USBFS_GEN_16BITS_EP_ACCESS)) +#define USBFS_VBUS_MONITORING_ENABLE (0u != USBFS_MON_VBUS) +#define USBFS_VBUS_MONITORING_INTERNAL (0u == USBFS_EXTERN_VBUS) +#define USBFS_VBUS_POWER_PAD_ENABLE (0u != USBFS_POWER_PAD_VBUS) + +/* Control endpoints availability */ +#define USBFS_SOF_ISR_REMOVE (0u) +#define USBFS_BUS_RESET_ISR_REMOVE (0u) +#define USBFS_EP0_ISR_REMOVE (0u) +#define USBFS_ARB_ISR_REMOVE (0u) +#define USBFS_DP_ISR_REMOVE (0u) +#define USBFS_LPM_REMOVE (1u) +#define USBFS_SOF_ISR_ACTIVE ((0u == USBFS_SOF_ISR_REMOVE) ? 1u: 0u) +#define USBFS_BUS_RESET_ISR_ACTIVE ((0u == USBFS_BUS_RESET_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP0_ISR_ACTIVE ((0u == USBFS_EP0_ISR_REMOVE) ? 1u: 0u) +#define USBFS_ARB_ISR_ACTIVE ((0u == USBFS_ARB_ISR_REMOVE) ? 1u: 0u) +#define USBFS_DP_ISR_ACTIVE ((0u == USBFS_DP_ISR_REMOVE) ? 1u: 0u) +#define USBFS_LPM_ACTIVE ((CY_PSOC4 && (0u == USBFS_LPM_REMOVE)) ? 1u: 0u) + +/* Data endpoints availability */ +#define USBFS_EP1_ISR_REMOVE (0u) +#define USBFS_EP2_ISR_REMOVE (0u) +#define USBFS_EP3_ISR_REMOVE (0u) +#define USBFS_EP4_ISR_REMOVE (0u) +#define USBFS_EP5_ISR_REMOVE (1u) +#define USBFS_EP6_ISR_REMOVE (1u) +#define USBFS_EP7_ISR_REMOVE (1u) +#define USBFS_EP8_ISR_REMOVE (1u) +#define USBFS_EP1_ISR_ACTIVE ((0u == USBFS_EP1_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP2_ISR_ACTIVE ((0u == USBFS_EP2_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP3_ISR_ACTIVE ((0u == USBFS_EP3_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP4_ISR_ACTIVE ((0u == USBFS_EP4_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP5_ISR_ACTIVE ((0u == USBFS_EP5_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP6_ISR_ACTIVE ((0u == USBFS_EP6_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP7_ISR_ACTIVE ((0u == USBFS_EP7_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP8_ISR_ACTIVE ((0u == USBFS_EP8_ISR_REMOVE) ? 1u: 0u) + +#define USBFS_EP_DMA_AUTO_OPT ((CY_PSOC4) ? (1u) : (0u)) +#define USBFS_DMA1_REMOVE (1u) +#define USBFS_DMA2_REMOVE (1u) +#define USBFS_DMA3_REMOVE (1u) +#define USBFS_DMA4_REMOVE (1u) +#define USBFS_DMA5_REMOVE (1u) +#define USBFS_DMA6_REMOVE (1u) +#define USBFS_DMA7_REMOVE (1u) +#define USBFS_DMA8_REMOVE (1u) +#define USBFS_DMA1_ACTIVE ((0u == USBFS_DMA1_REMOVE) ? 1u: 0u) +#define USBFS_DMA2_ACTIVE ((0u == USBFS_DMA2_REMOVE) ? 1u: 0u) +#define USBFS_DMA3_ACTIVE ((0u == USBFS_DMA3_REMOVE) ? 1u: 0u) +#define USBFS_DMA4_ACTIVE ((0u == USBFS_DMA4_REMOVE) ? 1u: 0u) +#define USBFS_DMA5_ACTIVE ((0u == USBFS_DMA5_REMOVE) ? 1u: 0u) +#define USBFS_DMA6_ACTIVE ((0u == USBFS_DMA6_REMOVE) ? 1u: 0u) +#define USBFS_DMA7_ACTIVE ((0u == USBFS_DMA7_REMOVE) ? 1u: 0u) +#define USBFS_DMA8_ACTIVE ((0u == USBFS_DMA8_REMOVE) ? 1u: 0u) /*************************************** -* Data Struct Definition +* Data Structures Definition ***************************************/ typedef struct @@ -167,7 +187,6 @@ typedef struct T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; } T_USBFS_TD; - typedef struct { uint8 c; @@ -179,145 +198,217 @@ typedef struct { uint8 enableState; uint8 mode; +#if (CY_PSOC4) + uint8 intrSeiMask; +#endif /* (CY_PSOC4) */ } USBFS_BACKUP_STRUCT; +/* Number of endpoint 0 data registers. */ +#define USBFS_EP0_DR_MAPPED_REG_CNT (8u) -/* Renamed structure fields for backward compatibility. -* Should not be used in new designs. -*/ -#define wBuffOffset buffOffset -#define wBufferSize bufferSize -#define bStatus status -#define wLength length -#define wCount count +/* Structure to access data registers for EP0. */ +typedef struct +{ + uint8 epData[USBFS_EP0_DR_MAPPED_REG_CNT]; +} USBFS_ep0_data_struct; -/* Renamed global variable for backward compatibility. -* Should not be used in new designs. -*/ -#define CurrentTD USBFS_currentTD +/* Number of SIE endpoint registers group. */ +#define USBFS_SIE_EP_REG_SIZE (USBFS_USB__SIE_EP1_CR0 - \ + USBFS_USB__SIE_EP1_CNT0) + +/* Size of gap between SIE endpoint registers groups. */ +#define USBFS_SIE_GAP_CNT (((USBFS_USB__SIE_EP2_CNT0 - \ + (USBFS_USB__SIE_EP1_CNT0 + \ + USBFS_SIE_EP_REG_SIZE)) / sizeof(reg8)) - 1u) + +/* Structure to access to SIE registers for endpoint. */ +typedef struct +{ + uint8 epCnt0; + uint8 epCnt1; + uint8 epCr0; + uint8 gap[USBFS_SIE_GAP_CNT]; +} USBFS_sie_ep_struct; + +/* Number of ARB endpoint registers group. */ +#define USBFS_ARB_EP_REG_SIZE (USBFS_USB__ARB_RW1_DR - \ + USBFS_USB__ARB_EP1_CFG) + +/* Size of gap between ARB endpoint registers groups. */ +#define USBFS_ARB_GAP_CNT (((USBFS_USB__ARB_EP2_CFG - \ + (USBFS_USB__ARB_EP1_CFG + \ + USBFS_ARB_EP_REG_SIZE)) / sizeof(reg8)) - 1u) + +/* Structure to access to ARB registers for endpoint. */ +typedef struct +{ + uint8 epCfg; + uint8 epIntEn; + uint8 epSr; + uint8 reserved; + uint8 rwWa; + uint8 rwWaMsb; + uint8 rwRa; + uint8 rwRaMsb; + uint8 rwDr; + uint8 gap[USBFS_ARB_GAP_CNT]; +} USBFS_arb_ep_struct; + +#if (CY_PSOC4) + /* Number of ARB endpoint registers group (16-bits access). */ + #define USBFS_ARB_EP_REG16_SIZE (USBFS_USB__ARB_RW1_DR16 - \ + USBFS_USB__ARB_RW1_WA16) + + /* Size of gap between ARB endpoint registers groups (16-bits access). */ + #define USBFS_ARB_EP_REG16_GAP_CNT (((USBFS_USB__ARB_RW2_WA16 - \ + (USBFS_USB__ARB_RW1_WA16 + \ + USBFS_ARB_EP_REG16_SIZE)) / sizeof(reg8)) - 1u) + + /* Structure to access to ARB registers for endpoint (16-bits access). */ + typedef struct + { + uint8 rwWa16; + uint8 reserved0; + uint8 rwRa16; + uint8 reserved1; + uint8 rwDr16; + uint8 gap[USBFS_ARB_EP_REG16_GAP_CNT]; + } USBFS_arb_ep_reg16_struct; +#endif /* (CY_PSOC4) */ + +/* Number of endpoint (takes to account that endpoints numbers are 1-8). */ +#define USBFS_NUMBER_EP (9u) + +/* Consoled SIE register groups for endpoints 1-8. */ +typedef struct +{ + USBFS_sie_ep_struct sieEp[USBFS_NUMBER_EP]; +} USBFS_sie_eps_struct; + +/* Consolidate ARB register groups for endpoints 1-8.*/ +typedef struct +{ + USBFS_arb_ep_struct arbEp[USBFS_NUMBER_EP]; +} USBFS_arb_eps_struct; + +#if (CY_PSOC4) + /* Consolidate ARB register groups for endpoints 1-8 (16-bits access). */ + typedef struct + { + USBFS_arb_ep_reg16_struct arbEp[USBFS_NUMBER_EP]; + } USBFS_arb_eps_reg16_struct; +#endif /* (CY_PSOC4) */ /*************************************** * Function Prototypes ***************************************/ - -void USBFS_Start(uint8 device, uint8 mode) ; -void USBFS_Init(void) ; +/** +* \addtogroup group_general +* @{ +*/ void USBFS_InitComponent(uint8 device, uint8 mode) ; -void USBFS_Stop(void) ; -uint8 USBFS_CheckActivity(void) ; -uint8 USBFS_GetConfiguration(void) ; -uint8 USBFS_IsConfigurationChanged(void) ; -uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) - ; -uint8 USBFS_GetEPState(uint8 epNumber) ; -uint16 USBFS_GetEPCount(uint8 epNumber) ; +void USBFS_Start(uint8 device, uint8 mode) ; +void USBFS_Init(void) ; +void USBFS_Stop(void) ; +uint8 USBFS_GetConfiguration(void) ; +uint8 USBFS_IsConfigurationChanged(void) ; +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) ; +uint8 USBFS_GetEPState(uint8 epNumber) ; +uint16 USBFS_GetEPCount(uint8 epNumber) ; void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) - ; + ; uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) - ; -void USBFS_EnableOutEP(uint8 epNumber) ; -void USBFS_DisableOutEP(uint8 epNumber) ; -void USBFS_Force(uint8 bState) ; -uint8 USBFS_GetEPAckState(uint8 epNumber) ; -void USBFS_SetPowerStatus(uint8 powerStatus) ; -uint8 USBFS_RWUEnabled(void) ; -void USBFS_TerminateEP(uint8 ep) ; + ; +void USBFS_EnableOutEP(uint8 epNumber) ; +void USBFS_DisableOutEP(uint8 epNumber) ; +void USBFS_Force(uint8 bState) ; +uint8 USBFS_GetEPAckState(uint8 epNumber) ; +void USBFS_SetPowerStatus(uint8 powerStatus) ; +void USBFS_TerminateEP(uint8 epNumber) ; + +uint8 USBFS_GetDeviceAddress(void) ; + +void USBFS_EnableSofInt(void) ; +void USBFS_DisableSofInt(void) ; -void USBFS_Suspend(void) ; -void USBFS_Resume(void) ; #if defined(USBFS_ENABLE_FWSN_STRING) void USBFS_SerialNumString(uint8 snString[]) ; #endif /* USBFS_ENABLE_FWSN_STRING */ -#if (USBFS_MON_VBUS == 1u) + +#if (USBFS_VBUS_MONITORING_ENABLE) uint8 USBFS_VBusPresent(void) ; -#endif /* USBFS_MON_VBUS */ +#endif /* (USBFS_VBUS_MONITORING_ENABLE) */ + +#if (USBFS_16BITS_EP_ACCESS_ENABLE) + /* PSoC4 specific functions for 16-bit data register access. */ + void USBFS_LoadInEP16 (uint8 epNumber, const uint8 pData[], uint16 length); + uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length); +#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */ + +#if (USBFS_BATT_CHARG_DET_ENABLE) + uint8 USBFS_Bcd_DetectPortType(void); +#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) ; + void USBFS_Stop_DMA(uint8 epNumber) ; +/** @} general */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +/** +* \addtogroup group_power +* @{ +*/ +uint8 USBFS_CheckActivity(void) ; +void USBFS_Suspend(void) ; +void USBFS_Resume(void) ; +uint8 USBFS_RWUEnabled(void) ; + +#if (USBFS_LPM_ACTIVE) + uint32 USBFS_Lpm_GetBeslValue(void); + uint32 USBFS_Lpm_RemoteWakeUpAllowed(void); + void USBFS_Lpm_SetResponse(uint32 response); + uint32 USBFS_Lpm_GetResponse(void); +#endif /* (USBFS_LPM_ACTIVE) */ + +/** @} power */ + #if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) - - void USBFS_CyBtldrCommStart(void) ; - void USBFS_CyBtldrCommStop(void) ; - void USBFS_CyBtldrCommReset(void) ; +/** +* \addtogroup group_bootloader +* @{ +*/ + void USBFS_CyBtldrCommStart(void) ; + void USBFS_CyBtldrCommStop(void) ; + void USBFS_CyBtldrCommReset(void) ; cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL ; cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL ; +/** @} bootloader */ - #define USBFS_BTLDR_OUT_EP (0x01u) - #define USBFS_BTLDR_IN_EP (0x02u) + #define USBFS_BTLDR_OUT_EP (0x01u) + #define USBFS_BTLDR_IN_EP (0x02u) - #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */ - #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */ + #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* Endpoint 1 (OUT) buffer size. */ + #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* Endpoint 2 (IN) buffer size. */ #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */ - /* These defines active if used USBFS interface as an - * IO Component for bootloading. When Custom_Interface selected - * in Bootloder configuration as the IO Component, user must - * provide these functions. - */ + /* Map-specific USB bootloader communication functions to common bootloader functions */ #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) #define CyBtldrCommStart USBFS_CyBtldrCommStart #define CyBtldrCommStop USBFS_CyBtldrCommStop #define CyBtldrCommReset USBFS_CyBtldrCommReset #define CyBtldrCommWrite USBFS_CyBtldrCommWrite #define CyBtldrCommRead USBFS_CyBtldrCommRead - #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ - -#endif /* CYDEV_BOOTLOADER_IO_COMP */ - -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData) - ; - void USBFS_Stop_DMA(uint8 epNumber) ; -#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */ - -#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) - void USBFS_MIDI_EP_Init(void) ; - - #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - void USBFS_MIDI_IN_Service(void) ; - uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) - ; - #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ - - #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - void USBFS_MIDI_OUT_EP_Service(void) ; - #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ - -#endif /* USBFS_ENABLE_MIDI_API != 0u */ - -/* Renamed Functions for backward compatibility. -* Should not be used in new designs. -*/ - -#define USBFS_bCheckActivity USBFS_CheckActivity -#define USBFS_bGetConfiguration USBFS_GetConfiguration -#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting -#define USBFS_bGetEPState USBFS_GetEPState -#define USBFS_wGetEPCount USBFS_GetEPCount -#define USBFS_bGetEPAckState USBFS_GetEPAckState -#define USBFS_bRWUEnabled USBFS_RWUEnabled -#define USBFS_bVBusPresent USBFS_VBusPresent - -#define USBFS_bConfiguration USBFS_configuration -#define USBFS_bInterfaceSetting USBFS_interfaceSetting -#define USBFS_bDeviceAddress USBFS_deviceAddress -#define USBFS_bDeviceStatus USBFS_deviceStatus -#define USBFS_bDevice USBFS_device -#define USBFS_bTransferState USBFS_transferState -#define USBFS_bLastPacketSize USBFS_lastPacketSize - -#define USBFS_LoadEP USBFS_LoadInEP -#define USBFS_LoadInISOCEP USBFS_LoadInEP -#define USBFS_EnableOutISOCEP USBFS_EnableOutEP - -#define USBFS_SetVector CyIntSetVector -#define USBFS_SetPriority CyIntSetPriority -#define USBFS_EnableInt CyIntEnable + #endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */ +#endif /* CYDEV_BOOTLOADER_IO_COMP */ /*************************************** @@ -361,7 +452,7 @@ void USBFS_Resume(void) ; #define USBFS_3V_OPERATION (0x00u) #define USBFS_5V_OPERATION (0x01u) -#define USBFS_DWR_VDDD_OPERATION (0x02u) +#define USBFS_DWR_POWER_OPERATION (0x02u) #define USBFS_MODE_DISABLE (0x00u) #define USBFS_MODE_NAK_IN_OUT (0x01u) @@ -400,6 +491,12 @@ void USBFS_Resume(void) ; #define USBFS_RQST_RCPT_EP (0x02u) #define USBFS_RQST_RCPT_OTHER (0x03u) +#if (USBFS_LPM_ACTIVE) + #define USBFS_LPM_REQ_ACK (0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_REQ_NACK (0x00u) + #define USBFS_LPM_REQ_NYET (0x01u << USBFS_LPM_CTRL_NYET_EN_POS) +#endif /*(USBFS_LPM_ACTIVE)*/ + /* USB Class Codes */ #define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ #define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ @@ -414,13 +511,12 @@ void USBFS_Resume(void) ; #define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ #define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ #define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ -#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */ +#define USBFS_CLASS_PHD (0x0Fu) /* Personal Health care device */ #define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ #define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ #define USBFS_CLASS_APP (0xEFu) /* Application Specific */ #define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ - /* Standard Request Types (Table 9-4) */ #define USBFS_GET_STATUS (0x00u) #define USBFS_CLEAR_FEATURE (0x01u) @@ -447,7 +543,9 @@ void USBFS_Resume(void) ; #define USBFS_DESCR_DEVICE_QUALIFIER (6u) #define USBFS_DESCR_OTHER_SPEED (7u) #define USBFS_DESCR_INTERFACE_POWER (8u) - +#if (USBFS_BOS_ENABLE) + #define USBFS_DESCR_BOS (15u) +#endif /* (USBFS_BOS_ENABLE) */ /* Device Descriptor Defines */ #define USBFS_DEVICE_DESCR_LENGTH (18u) #define USBFS_DEVICE_DESCR_SN_SHIFT (16u) @@ -464,6 +562,15 @@ void USBFS_Resume(void) ; #define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) #define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) +#if (USBFS_BOS_ENABLE) + /* Config Descriptor BOS */ + #define USBFS_BOS_DESCR_LENGTH (0u) + #define USBFS_BOS_DESCR_TYPE (1u) + #define USBFS_BOS_DESCR_TOTAL_LENGTH_LOW (2u) + #define USBFS_BOS_DESCR_TOTAL_LENGTH_HI (3u) + #define USBFS_BOS_DESCR_NUM_DEV_CAPS (4u) +#endif /* (USBFS_BOS_ENABLE) */ + /* Feature Selectors (Table 9-6) */ #define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) #define USBFS_ENDPOINT_HALT (0x00u) @@ -501,15 +608,16 @@ void USBFS_Resume(void) ; #define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) #define USBFS_EP_USAGE_TYPE_MASK (0x30u) -/* point Status defines */ +/* Point Status defines */ #define USBFS_EP_STATUS_LENGTH (0x02u) -/* point Device defines */ +/* Point Device defines */ #define USBFS_DEVICE_STATUS_LENGTH (0x02u) #define USBFS_STATUS_LENGTH_MAX \ - ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ - USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH ) + ((USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ + USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH) + /* Transfer Completion Notification */ #define USBFS_XFER_IDLE (0x00u) #define USBFS_XFER_STATUS_ACK (0x01u) @@ -527,380 +635,1241 @@ void USBFS_Resume(void) ; #define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) #define USBFS_MSOS_CONF_DESCR_LENGTH (40u) -#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - /* DMA manual mode defines */ - #define USBFS_DMA_BYTES_PER_BURST (0u) - #define USBFS_DMA_REQUEST_PER_BURST (0u) -#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ -#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* DMA automatic mode defines */ - #define USBFS_DMA_BYTES_PER_BURST (32u) - #define USBFS_DMA_BYTES_REPEAT (2u) - /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ - #define USBFS_DMA_BUF_SIZE (0x55u) - #define USBFS_DMA_REQUEST_PER_BURST (1u) +/* Return values */ +#define USBFS_BCD_PORT_SDP (1u) /* Standard downstream port detected */ +#define USBFS_BCD_PORT_CDP (2u) /* Charging downstream port detected */ +#define USBFS_BCD_PORT_DCP (3u) /* Dedicated charging port detected */ +#define USBFS_BCD_PORT_UNKNOWN (0u) /* Unable to detect charging port */ +#define USBFS_BCD_PORT_ERR (4u) /* Error condition in detection process*/ - #if(USBFS_DMA1_REMOVE == 0u) - #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN - #else - #define USBFS_ep1_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA1_REMOVE == 0u */ - #if(USBFS_DMA2_REMOVE == 0u) - #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN - #else - #define USBFS_ep2_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA2_REMOVE == 0u */ - #if(USBFS_DMA3_REMOVE == 0u) - #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN - #else - #define USBFS_ep3_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA3_REMOVE == 0u */ - #if(USBFS_DMA4_REMOVE == 0u) - #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN - #else - #define USBFS_ep4_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA4_REMOVE == 0u */ - #if(USBFS_DMA5_REMOVE == 0u) - #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN - #else - #define USBFS_ep5_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA5_REMOVE == 0u */ - #if(USBFS_DMA6_REMOVE == 0u) - #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN - #else - #define USBFS_ep6_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA6_REMOVE == 0u */ - #if(USBFS_DMA7_REMOVE == 0u) - #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN - #else - #define USBFS_ep7_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA7_REMOVE == 0u */ - #if(USBFS_DMA8_REMOVE == 0u) - #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN - #else - #define USBFS_ep8_TD_TERMOUT_EN (0u) - #endif /* USBFS_DMA8_REMOVE == 0u */ - #define USBFS_EP17_SR_MASK (0x7fu) - #define USBFS_EP8_SR_MASK (0x03u) +/* Timeouts for BCD */ +#define USBFS_BCD_TIMEOUT (400u) /* Copied from PBK#163 TIMEOUT (300 ms) */ +#define USBFS_BCD_TDCD_DBNC (10u) /*BCD v1.2: DCD debounce time 10 ms*/ +#define USBFS_BCD_PRIMARY_WAIT (40u) /* Copied from PBK#163 TIMEOUT (40 ms) */ +#define USBFS_BCD_SECONDARY_WAIT (47u) /* Copied from PBK#163 TIMEOUT (40 ms) */ +#define USBFS_BCD_SUSPEND_DISABLE_WAIT (2u) /* Copied from PBK#163 TIMEOUT (2 us) */ -#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ +/* Wait cycles required before clearing SUSPEND_DEL in POWER_CTRL: 2us */ +#define USBFS_WAIT_SUSPEND_DEL_DISABLE (2u) + +/* Wait cycles required for USB regulator stabilization after it is enabled : 50ns */ +#define USBFS_WAIT_VREF_STABILITY (0u) + +#if (CY_PSOC3 || CY_PSOC5LP) +/* Wait cycles required for USB reference restore: 40us */ +#define USBFS_WAIT_VREF_RESTORE (40u) + +/* Wait cycles required for stabilization after register is written : 50ns */ +#define USBFS_WAIT_REG_STABILITY_50NS (0u) +#define USBFS_WAIT_REG_STABILITY_1US (1u) + +/* Wait cycles required after CR0 register write: 1 cycle */ +#define USBFS_WAIT_CR0_REG_STABILITY (1u) + +/* Wait cycles required after PD_PULLUP_N bit is set in PM_USB_CR0: 2us */ +#define USBFS_WAIT_PD_PULLUP_N_ENABLE (2u) +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#if (CY_PSOC4) + #if (USBFS_EP_MANAGEMENT_DMA) + #define USBFS_DMA_DESCR0 (0u) + #define USBFS_DMA_DESCR1 (1u) + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_HALFWORDS_PER_BURST (16u) + #define USBFS_DMA_BURST_BYTES_MASK (USBFS_DMA_BYTES_PER_BURST - 1u) + + #define USBFS_DMA_DESCR0_MASK (0x00u) + #define USBFS_DMA_DESCR1_MASK (0x80u) + #define USBFS_DMA_DESCR_REVERT (0x40u) + #define USBFS_DMA_DESCR_16BITS (0x20u) + #define USBFS_DMA_DESCR_SHIFT (7u) + + #define USBFS_DMA_GET_DESCR_NUM(desrc) + #define USBFS_DMA_GET_BURST_CNT(dmaBurstCnt) \ + (((dmaBurstCnt) > 2u)? ((dmaBurstCnt) - 2u) : 0u) + + #define USBFS_DMA_GET_MAX_ELEM_PER_BURST(dmaLastBurstEl) \ + ((0u != ((dmaLastBurstEl) & USBFS_DMA_DESCR_16BITS)) ? \ + (USBFS_DMA_HALFWORDS_PER_BURST - 1u) : (USBFS_DMA_BYTES_PER_BURST - 1u)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#else + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + #define USBFS_DMA_BYTES_PER_BURST (0u) + #define USBFS_DMA_REQUEST_PER_BURST (0u) + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_BYTES_REPEAT (2u) + + /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_REQUEST_PER_BURST (1u) + + #define USBFS_EP17_SR_MASK (0x7Fu) + #define USBFS_EP8_SR_MASK (0x03u) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (CY_PSOC4) */ /* DIE ID string descriptor defines */ #if defined(USBFS_ENABLE_IDSN_STRING) - #define USBFS_IDSN_DESCR_LENGTH (0x22u) -#endif /* USBFS_ENABLE_IDSN_STRING */ + #define USBFS_IDSN_DESCR_LENGTH (0x22u) +#endif /* (USBFS_ENABLE_IDSN_STRING) */ /*************************************** -* External data references +* Vars with External Linkage ***************************************/ +/** +* \addtogroup group_globals +* @{ +*/ extern uint8 USBFS_initVar; extern volatile uint8 USBFS_device; extern volatile uint8 USBFS_transferState; extern volatile uint8 USBFS_configuration; extern volatile uint8 USBFS_configurationChanged; extern volatile uint8 USBFS_deviceStatus; +/** @} globals */ +/** +* \addtogroup group_hid +* @{ +*/ /* HID Variables */ #if defined(USBFS_ENABLE_HID_CLASS) - extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; - extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidProtocol [USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleRate [USBFS_MAX_INTERFACES_NUMBER]; extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; -#endif /* USBFS_ENABLE_HID_CLASS */ +#endif /* (USBFS_ENABLE_HID_CLASS) */ +/** @} hid */ /*************************************** * Registers ***************************************/ -#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) -#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG) +/* Common registers for all PSoCs: 3/4/5LP */ +#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) +#define USBFS_ARB_CFG_REG (*(reg8 *) USBFS_USB__ARB_CFG) -#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) -#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_REG (*(reg8 *) USBFS_USB__ARB_EP1_SR) #define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG -#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) -#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN) #define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN -#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) -#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR) #define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR +#define USBFS_ARB_EP_BASE (*(volatile USBFS_arb_eps_struct CYXDATA *) \ + (USBFS_USB__ARB_EP1_CFG - sizeof(USBFS_arb_ep_struct))) -#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) -#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG) -#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) -#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN) -#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) -#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_SR_REG (*(reg8 *) USBFS_USB__ARB_EP2_SR) -#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) -#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG) -#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) -#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN) -#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) -#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_SR_REG (*(reg8 *) USBFS_USB__ARB_EP3_SR) -#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) -#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG) -#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) -#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN) -#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) -#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_SR_REG (*(reg8 *) USBFS_USB__ARB_EP4_SR) -#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) -#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG) -#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) -#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN) -#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) -#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_SR_REG (*(reg8 *) USBFS_USB__ARB_EP5_SR) -#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) -#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG) -#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) -#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN) -#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) -#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_SR_REG (*(reg8 *) USBFS_USB__ARB_EP6_SR) -#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) -#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG) -#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) -#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN) -#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) -#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_SR_REG (*(reg8 *) USBFS_USB__ARB_EP7_SR) -#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) -#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG) -#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) -#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN) -#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) -#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_SR_REG (*(reg8 *) USBFS_USB__ARB_EP8_SR) -#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) -#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN) -#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) -#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_SR_REG (*(reg8 *) USBFS_USB__ARB_INT_SR) -#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA) + +#define USBFS_ARB_RW1_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA_MSB) +#define USBFS_ARB_RW1_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA) +#define USBFS_ARB_RW1_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA_MSB) #define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR -#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA) #define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA -#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB) #define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB -#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA) #define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA -#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB) #define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB -#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR) -#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA) -#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB) -#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA) -#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB) +#define USBFS_ARB_RW2_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW2_DR) +#define USBFS_ARB_RW2_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA) +#define USBFS_ARB_RW2_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA_MSB) +#define USBFS_ARB_RW2_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA) +#define USBFS_ARB_RW2_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA_MSB) -#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR) -#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA) -#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB) -#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA) -#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB) +#define USBFS_ARB_RW3_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW3_DR) +#define USBFS_ARB_RW3_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA) +#define USBFS_ARB_RW3_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA_MSB) +#define USBFS_ARB_RW3_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA) +#define USBFS_ARB_RW3_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA_MSB) -#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR) -#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA) -#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB) -#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA) -#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB) +#define USBFS_ARB_RW4_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW4_DR) +#define USBFS_ARB_RW4_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA) +#define USBFS_ARB_RW4_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA_MSB) +#define USBFS_ARB_RW4_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA) +#define USBFS_ARB_RW4_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA_MSB) -#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR) -#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA) -#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB) -#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA) -#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB) +#define USBFS_ARB_RW5_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW5_DR) +#define USBFS_ARB_RW5_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA) +#define USBFS_ARB_RW5_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA_MSB) +#define USBFS_ARB_RW5_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA) +#define USBFS_ARB_RW5_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA_MSB) -#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR) -#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA) -#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB) -#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA) -#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB) +#define USBFS_ARB_RW6_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW6_DR) +#define USBFS_ARB_RW6_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA) +#define USBFS_ARB_RW6_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA_MSB) +#define USBFS_ARB_RW6_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA) +#define USBFS_ARB_RW6_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA_MSB) -#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR) -#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA) -#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB) -#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA) -#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB) +#define USBFS_ARB_RW7_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW7_DR) +#define USBFS_ARB_RW7_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA) +#define USBFS_ARB_RW7_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA_MSB) +#define USBFS_ARB_RW7_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA) +#define USBFS_ARB_RW7_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA_MSB) -#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR) -#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA) -#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB) -#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA) -#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB) +#define USBFS_ARB_RW8_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW8_DR) +#define USBFS_ARB_RW8_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA) +#define USBFS_ARB_RW8_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA_MSB) +#define USBFS_ARB_RW8_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA) +#define USBFS_ARB_RW8_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA_MSB) -#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) -#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE) -#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) -#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT) -#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) -#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA) -#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) -#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB) -#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) -#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0) -#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) -#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1) +#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUF_SIZE_REG (*(reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_BUS_RST_CNT_REG (*(reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_REG (*(reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CWA_MSB_REG (*(reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) +#define USBFS_CR0_REG (*(reg8 *) USBFS_USB__CR0) +#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) +#define USBFS_CR1_REG (*(reg8 *) USBFS_USB__CR1) -#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) -#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES) -#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) -#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_REG (*(reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_MSB_REG (*(reg8 *) USBFS_USB__DMA_THRES_MSB) -#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) -#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE) -#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) -#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_ACTIVE_REG (*(reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_TYPE_REG (*(reg8 *) USBFS_USB__EP_TYPE) -#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) -#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT) -#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) -#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR) -#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) -#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CNT_REG (*(reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_CR_REG (*(reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_REG (*(reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR1_REG (*(reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR2_REG (*(reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR3_REG (*(reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR4_REG (*(reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR5_REG (*(reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR6_REG (*(reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR7_REG (*(reg8 *) USBFS_USB__EP0_DR7) #define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 -#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) -#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1) -#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) -#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2) -#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) -#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3) -#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) -#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4) -#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) -#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5) -#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) -#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6) -#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) -#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR_BASE (*(volatile USBFS_ep0_data_struct CYXDATA *) USBFS_USB__EP0_DR0) -#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) -#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0) -#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) -#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR0_REG (*(reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR1_REG (*(reg8 *) USBFS_USB__OSCLK_DR1) -#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) -#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG) -#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) -#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG) +#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_EN_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) +#define USBFS_SIE_EP_INT_SR_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_SR) -#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) -#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN) -#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) -#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR) - -#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) -#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0) -#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 -#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) -#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CR0) #define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 -#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) -#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 #define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 +#define USBFS_SIE_EP_BASE (*(volatile USBFS_sie_eps_struct CYXDATA *) \ + (USBFS_USB__SIE_EP1_CNT0 - sizeof(USBFS_sie_ep_struct))) -#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) -#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0) -#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) -#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1) -#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) -#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CR0) -#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) -#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0) -#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) -#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1) -#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) -#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CR0) -#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) -#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0) -#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) -#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1) -#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) -#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CR0) -#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) -#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0) -#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) -#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1) -#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) -#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CR0) -#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) -#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0) -#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) -#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1) -#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) -#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CR0) -#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) -#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0) -#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) -#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1) -#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) -#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CR0) -#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) -#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0) -#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) -#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1) -#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) -#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CR0) -#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) -#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0) -#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) -#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF0_REG (*(reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF1_REG (*(reg8 *) USBFS_USB__SOF1) -#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) -#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_REG (*(reg8 *) USBFS_USB__USB_CLK_EN) -#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) -#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0) -#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) -#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1) -#if(!CY_PSOC5LP) - #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) - #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) -#endif /* CY_PSOC5LP */ +#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR0_REG (*(reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) +#define USBFS_USBIO_CR1_REG (*(reg8 *) USBFS_USB__USBIO_CR1) -#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE +#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) +#define USBFS_DYN_RECONFIG_REG (*(reg8 *) USBFS_USB__DYN_RECONFIG) -#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) -#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0) -#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) -#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG) +#if (CY_PSOC4) + #define USBFS_ARB_RW1_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16) + #define USBFS_ARB_RW1_RA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16) + #define USBFS_ARB_RW1_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16) + #define USBFS_ARB_RW1_WA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16) + #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16) + #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16) + #define USBFS_ARB_EP16_BASE (*(volatile USBFS_arb_eps_reg16_struct CYXDATA *) \ + (USBFS_USB__ARB_RW1_WA16 - sizeof(USBFS_arb_ep_reg16_struct))) -#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) -#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS) -#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) -#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS) -#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) -#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_ARB_RW2_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_DR16) + #define USBFS_ARB_RW2_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_RA16) + #define USBFS_ARB_RW2_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_WA16) -#if (USBFS_MON_VBUS == 1u) - #if (USBFS_EXTERN_VBUS == 0u) - #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) - #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR) - #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) - #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS) - #define USBFS_VBUS_MASK USBFS_VBUS__MASK - #else - #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG ) - #define USBFS_VBUS_MASK (0x01u) - #endif /* USBFS_EXTERN_VBUS == 0u */ -#endif /* USBFS_MON_VBUS */ + #define USBFS_ARB_RW3_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_DR16) + #define USBFS_ARB_RW3_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_RA16) + #define USBFS_ARB_RW3_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_WA16) -/* Renamed Registers for backward compatibility. -* Should not be used in new designs. + #define USBFS_ARB_RW4_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_DR16) + #define USBFS_ARB_RW4_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_RA16) + #define USBFS_ARB_RW4_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_WA16) + + #define USBFS_ARB_RW5_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_DR16) + #define USBFS_ARB_RW5_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_RA16) + #define USBFS_ARB_RW5_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_WA16) + + #define USBFS_ARB_RW6_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_DR16) + #define USBFS_ARB_RW6_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_RA16) + #define USBFS_ARB_RW6_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_WA16) + + #define USBFS_ARB_RW7_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_DR16) + #define USBFS_ARB_RW7_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_RA16) + #define USBFS_ARB_RW7_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_WA16) + + #define USBFS_ARB_RW8_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_DR16) + #define USBFS_ARB_RW8_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_RA16) + #define USBFS_ARB_RW8_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_WA16) + + #define USBFS_OSCLK_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16) + #define USBFS_OSCLK_DR16_REG (*(reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16) + + #define USBFS_SOF16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__SOF16) + #define USBFS_SOF16_REG (*(reg32 *) USBFS_cy_m0s8_usb__SOF16) + + #define USBFS_CWA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__CWA16) + #define USBFS_CWA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__CWA16) + + #define USBFS_DMA_THRES16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16) + #define USBFS_DMA_THRES16_REG (*(reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16) + + #define USBFS_USB_CLK_EN_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN) + #define USBFS_USB_CLK_EN_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN) + + #define USBFS_USBIO_CR2_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (*(reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2) + + #define USBFS_USB_MEM ( (reg32 *) USBFS_cy_m0s8_usb__MEM_DATA0) + + #define USBFS_POWER_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL) + #define USBFS_POWER_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL) + + #define USBFS_CHGDET_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL) + #define USBFS_CHGDET_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL) + + #define USBFS_USBIO_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL) + #define USBFS_USBIO_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL) + + #define USBFS_FLOW_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL) + #define USBFS_FLOW_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL) + + #define USBFS_LPM_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL) + #define USBFS_LPM_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL) + + #define USBFS_LPM_STAT_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT) + #define USBFS_LPM_STAT_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT) + + #define USBFS_PHY_CONTROL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL) + #define USBFS_PHY_CONTROL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL) + + #define USBFS_INTR_SIE_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE) + #define USBFS_INTR_SIE_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE) + + #define USBFS_INTR_SIE_SET_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET) + #define USBFS_INTR_SIE_SET_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET) + + #define USBFS_INTR_SIE_MASK_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK) + #define USBFS_INTR_SIE_MASK_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK) + + #define USBFS_INTR_SIE_MASKED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED) + #define USBFS_INTR_SIE_MASKED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED) + + #define USBFS_INTR_LVL_SEL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL) + #define USBFS_INTR_LVL_SEL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL) + + #define USBFS_INTR_CAUSE_HI_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI) + #define USBFS_INTR_CAUSE_HI_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI) + + #define USBFS_INTR_CAUSE_LO_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO) + #define USBFS_INTR_CAUSE_LO_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO) + + #define USBFS_INTR_CAUSE_MED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED) + #define USBFS_INTR_CAUSE_MED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED) + + #define USBFS_DFT_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL) + #define USBFS_DFT_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL) + + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_POWER_PAD_ENABLE) + /* Vbus power pad pin is hard wired to P13[2] */ + #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT13_PS) + #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT13_PS) + #define USBFS_VBUS_VALID (0x04u) + #else + /* Vbus valid pin is hard wired to P0[0] */ + #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT0_PS) + #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT0_PS) + #define USBFS_VBUS_VALID (0x01u) + #endif + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ + + #define USBFS_BURSTEND_0_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND0_TR_OUTPUT) + #define USBFS_BURSTEND_1_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND1_TR_OUTPUT) + #define USBFS_BURSTEND_2_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND2_TR_OUTPUT) + #define USBFS_BURSTEND_3_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND3_TR_OUTPUT) + #define USBFS_BURSTEND_4_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND4_TR_OUTPUT) + #define USBFS_BURSTEND_5_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND5_TR_OUTPUT) + #define USBFS_BURSTEND_6_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND6_TR_OUTPUT) + #define USBFS_BURSTEND_7_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND7_TR_OUTPUT) + +#else /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* USBFS_PM_USB_CR0 */ + #define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) + #define USBFS_PM_USB_CR0_REG (*(reg8 *) CYREG_PM_USB_CR0) + + /* USBFS_PM_ACT/STBY_CFG */ + #define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) + #define USBFS_PM_ACT_CFG_REG (*(reg8 *) USBFS_USB__PM_ACT_CFG) + #define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) + #define USBFS_PM_STBY_CFG_REG (*(reg8 *) USBFS_USB__PM_STBY_CFG) + + #if (!CY_PSOC5LP) + #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) + #endif /* (!CY_PSOC5LP) */ + + /* USBFS_USB_MEM - USB IP memory buffer */ + #define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) + + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_MONITORING_INTERNAL) + #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_VALID (USBFS_VBUS__MASK) + #else + #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_VALID (USBFS_Vbus_ps_sts_sts_reg__MASK) + #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */ + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Interrupt source constants +***************************************/ + +#define USBFS_DP_INTC_PRIORITY USBFS_dp_int__INTC_PRIOR_NUM +#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER + +#if (CY_PSOC4) + #define USBFS_DMA_AUTO_INTR_PRIO (0u) + + #define USBFS_INTR_HI_PRIORITY USBFS_high_int__INTC_PRIOR_NUM + #define USBFS_INTR_HI_VECT_NUM USBFS_high_int__INTC_NUMBER + + #define USBFS_INTR_MED_PRIORITY USBFS_med_int__INTC_PRIOR_NUM + #define USBFS_INTR_MED_VECT_NUM USBFS_med_int__INTC_NUMBER + + #define USBFS_INTR_LO_PRIORITY USBFS_lo_int__INTC_PRIOR_NUM + #define USBFS_INTR_LO_VECT_NUM USBFS_lo_int__INTC_NUMBER + + /* Interrupt sources in USBFS_isrCallbacks[] table */ + #define USBFS_SOF_INTR_NUM (0u) + #define USBFS_BUS_RESET_INT_NUM (1u) + #define USBFS_EP0_INTR_NUM (2u) + #define USBFS_LPM_INTR_NUM (3u) + #define USBFS_ARB_EP_INTR_NUM (4u) + #define USBFS_EP1_INTR_NUM (5u) + #define USBFS_EP2_INTR_NUM (6u) + #define USBFS_EP3_INTR_NUM (7u) + #define USBFS_EP4_INTR_NUM (8u) + #define USBFS_EP5_INTR_NUM (9u) + #define USBFS_EP6_INTR_NUM (10u) + #define USBFS_EP7_INTR_NUM (11u) + #define USBFS_EP8_INTR_NUM (12u) + +#else + #define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM + #define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK + #define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER + + #define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM + #define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK + #define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER + + #define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM + #define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK + #define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER + + #define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM + #define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK + #define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER + + #define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM + #define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK + #define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER + + #define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM + #define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK + #define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER + + #define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM + #define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK + #define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER + + #define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM + #define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK + #define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER + + #define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM + #define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK + #define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER + + #define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM + #define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK + #define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER + + #define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM + #define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK + #define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER + + /* Set ARB ISR priority 0 to be highest for all EPX ISRs. */ + #define USBFS_ARB_PRIOR (0u) + #define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK + #define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Endpoint 0 offsets (Table 9-2) +***************************************/ +#define USBFS_bmRequestTypeReg USBFS_EP0_DR_BASE.epData[0u] +#define USBFS_bRequestReg USBFS_EP0_DR_BASE.epData[1u] +#define USBFS_wValueLoReg USBFS_EP0_DR_BASE.epData[2u] +#define USBFS_wValueHiReg USBFS_EP0_DR_BASE.epData[3u] +#define USBFS_wIndexLoReg USBFS_EP0_DR_BASE.epData[4u] +#define USBFS_wIndexHiReg USBFS_EP0_DR_BASE.epData[5u] +#define USBFS_wLengthLoReg USBFS_EP0_DR_BASE.epData[6u] +#define USBFS_wLengthHiReg USBFS_EP0_DR_BASE.epData[7u] + +/* Compatibility defines */ +#define USBFS_lengthLoReg USBFS_EP0_DR_BASE.epData[6u] +#define USBFS_lengthHiReg USBFS_EP0_DR_BASE.epData[7u] + + +/*************************************** +* Register Constants +***************************************/ + +#define USBFS_3500MV (3500u) +#if (CY_PSOC4) + #define USBFS_VDDD_MV (CYDEV_VBUS_MV) +#else + #define USBFS_VDDD_MV (CYDEV_VDDD_MV) +#endif /* (CY_PSOC4) */ + + +/* USBFS_USB_CLK */ +#define USBFS_USB_CLK_CSR_CLK_EN_POS (0u) +#define USBFS_USB_CLK_CSR_CLK_EN ((uint8) ((uint8) 0x1u << USBFS_USB_CLK_CSR_CLK_EN_POS)) +#define USBFS_USB_CLK_ENABLE (USBFS_USB_CLK_CSR_CLK_EN) + +/* USBFS_CR0 */ +#define USBFS_CR0_DEVICE_ADDRESS_POS (0u) +#define USBFS_CR0_ENABLE_POS (7u) +#define USBFS_CR0_DEVICE_ADDRESS_MASK ((uint8) ((uint8) 0x7Fu << USBFS_CR0_DEVICE_ADDRESS_POS)) +#define USBFS_CR0_ENABLE ((uint8) ((uint8) 0x01u << USBFS_CR0_ENABLE_POS)) + + +/* USBFS_CR1 */ +#define USBFS_CR1_REG_ENABLE_POS (0u) +#define USBFS_CR1_ENABLE_LOCK_POS (1u) +#define USBFS_CR1_BUS_ACTIVITY_POS (2u) +#define USBFS_CR1_TRIM_OFFSET_MSB_POS (3u) +#define USBFS_CR1_REG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_CR1_REG_ENABLE_POS)) +#define USBFS_CR1_ENABLE_LOCK ((uint8) ((uint8) 0x1u << USBFS_CR1_ENABLE_LOCK_POS)) +#define USBFS_CR1_BUS_ACTIVITY ((uint8) ((uint8) 0x1u << USBFS_CR1_BUS_ACTIVITY_POS)) +#define USBFS_CR1_TRIM_OFFSET_MSB ((uint8) ((uint8) 0x1u << USBFS_CR1_TRIM_OFFSET_MSB_POS)) + +/* USBFS_EPX_CNT */ +#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT0_MASK (0x0Fu) +#define USBFS_EPX_CNTX_MSB_MASK (0x07u) +#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) +#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) +#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) +#define USBFS_EPX_DATA_BUF_MAX (512u) + +/* USBFS_USBIO_CR0 */ + +#define USBFS_USBIO_CR0_TEN (0x80u) +#define USBFS_USBIO_CR0_TSE0 (0x40u) +#define USBFS_USBIO_CR0_TD (0x20u) +#define USBFS_USBIO_CR0_RD (0x01u) + +/* USBFS_USBIO_CR1 */ +#define USBFS_USBIO_CR1_DM0_POS (0u) +#define USBFS_USBIO_CR1_DP0_POS (1u) +#define USBFS_USBIO_CR1_USBPUEN_POS (2u) +#define USBFS_USBIO_CR1_IOMODE_POS (5u) +#define USBFS_USBIO_CR1_DM0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DM0_POS)) +#define USBFS_USBIO_CR1_DP0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DP0_POS)) +#define USBFS_USBIO_CR1_USBPUEN ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_USBPUEN_POS)) +#define USBFS_USBIO_CR1_IOMODE ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_IOMODE_POS)) + +/* USBFS_FASTCLK_IMO_CR */ +#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) +#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) +#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) + +/* USBFS_ARB_EPX_CFG */ +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS (0u) +#define USBFS_ARB_EPX_CFG_DMA_REQ_POS (1u) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS_POS (2u) +#define USBFS_ARB_EPX_CFG_RESET_POS (3u) +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS)) +#define USBFS_ARB_EPX_CFG_DMA_REQ ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_DMA_REQ_POS)) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_CRC_BYPASS_POS)) +#define USBFS_ARB_EPX_CFG_RESET ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_RESET_POS)) + +/* USBFS_ARB_EPX_INT / SR */ +#define USBFS_ARB_EPX_INT_IN_BUF_FULL_POS (0u) +#define USBFS_ARB_EPX_INT_DMA_GNT_POS (1u) +#define USBFS_ARB_EPX_INT_BUF_OVER_POS (2u) +#define USBFS_ARB_EPX_INT_BUF_UNDER_POS (3u) +#define USBFS_ARB_EPX_INT_ERR_INT_POS (4u) +#define USBFS_ARB_EPX_INT_IN_BUF_FULL ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_IN_BUF_FULL_POS)) +#define USBFS_ARB_EPX_INT_DMA_GNT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_GNT_POS)) +#define USBFS_ARB_EPX_INT_BUF_OVER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_OVER_POS)) +#define USBFS_ARB_EPX_INT_BUF_UNDER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_UNDER_POS)) +#define USBFS_ARB_EPX_INT_ERR_INT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_ERR_INT_POS)) + +#if (CY_PSOC4) +#define USBFS_ARB_EPX_INT_DMA_TERMIN_POS (5u) +#define USBFS_ARB_EPX_INT_DMA_TERMIN ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_TERMIN_POS)) +#endif /* (CY_PSOC4) */ + +/* Common arbiter interrupt sources for all PSoC devices. */ +#define USBFS_ARB_EPX_INT_COMMON (USBFS_ARB_EPX_INT_IN_BUF_FULL | \ + USBFS_ARB_EPX_INT_DMA_GNT | \ + USBFS_ARB_EPX_INT_BUF_OVER | \ + USBFS_ARB_EPX_INT_BUF_UNDER | \ + USBFS_ARB_EPX_INT_ERR_INT) + +#if (CY_PSOC4) + #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON | USBFS_ARB_EPX_INT_DMA_TERMIN) +#else + #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON) +#endif /* (CY_PSOC4) */ + +/* USBFS_ARB_CFG */ +#define USBFS_ARB_CFG_AUTO_MEM_POS (4u) +#define USBFS_ARB_CFG_DMA_CFG_POS (5u) +#define USBFS_ARB_CFG_CFG_CMP_POS (7u) +#define USBFS_ARB_CFG_AUTO_MEM ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_AUTO_MEM_POS)) +#define USBFS_ARB_CFG_DMA_CFG_MASK ((uint8) ((uint8) 0x3u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_NONE ((uint8) ((uint8) 0x0u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_MANUAL ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_AUTO ((uint8) ((uint8) 0x2u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_CFG_CMP ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_CFG_CMP_POS)) + +/* USBFS_DYN_RECONFIG */ +#define USBFS_DYN_RECONFIG_EP_SHIFT (1u) +#define USBFS_DYN_RECONFIG_ENABLE_POS (0u) +#define USBFS_DYN_RECONFIG_EPNO_POS (1u) +#define USBFS_DYN_RECONFIG_RDY_STS_POS (4u) +#define USBFS_DYN_RECONFIG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_ENABLE_POS)) +#define USBFS_DYN_RECONFIG_EPNO_MASK ((uint8) ((uint8) 0x7u << USBFS_DYN_RECONFIG_EPNO_POS)) +#define USBFS_DYN_RECONFIG_RDY_STS ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_RDY_STS_POS)) + +/* USBFS_ARB_INT */ +#define USBFS_ARB_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */ +#define USBFS_ARB_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */ +#define USBFS_ARB_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */ +#define USBFS_ARB_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */ +#define USBFS_ARB_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */ +#define USBFS_ARB_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */ +#define USBFS_ARB_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */ +#define USBFS_ARB_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */ +#define USBFS_ARB_INT_EP1_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP1_INTR_POS)) +#define USBFS_ARB_INT_EP2_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP2_INTR_POS)) +#define USBFS_ARB_INT_EP3_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP3_INTR_POS)) +#define USBFS_ARB_INT_EP4_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP4_INTR_POS)) +#define USBFS_ARB_INT_EP5_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP5_INTR_POS)) +#define USBFS_ARB_INT_EP6_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP6_INTR_POS)) +#define USBFS_ARB_INT_EP7_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP7_INTR_POS)) +#define USBFS_ARB_INT_EP8_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP8_INTR_POS)) + +/* USBFS_SIE_INT */ +#define USBFS_SIE_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */ +#define USBFS_SIE_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */ +#define USBFS_SIE_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */ +#define USBFS_SIE_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */ +#define USBFS_SIE_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */ +#define USBFS_SIE_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */ +#define USBFS_SIE_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */ +#define USBFS_SIE_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */ +#define USBFS_SIE_INT_EP1_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP1_INTR_POS)) +#define USBFS_SIE_INT_EP2_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP2_INTR_POS)) +#define USBFS_SIE_INT_EP3_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP3_INTR_POS)) +#define USBFS_SIE_INT_EP4_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP4_INTR_POS)) +#define USBFS_SIE_INT_EP5_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP5_INTR_POS)) +#define USBFS_SIE_INT_EP6_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP6_INTR_POS)) +#define USBFS_SIE_INT_EP7_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP7_INTR_POS)) +#define USBFS_SIE_INT_EP8_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP8_INTR_POS)) + +#if (CY_PSOC4) + /* USBFS_POWER_CTRL_REG */ + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_POS (0u) /* [0] */ + #define USBFS_POWER_CTRL_SUSPEND_POS (2u) /* [1] */ + #define USBFS_POWER_CTRL_SUSPEND_DEL_POS (3u) /* [3] */ + #define USBFS_POWER_CTRL_ISOLATE_POS (4u) /* [4] */ + #define USBFS_POWER_CTRL_CHDET_PWR_CTL_POS (5u) /* [5] */ + #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS (25u) /* [25] */ + #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS (26u) /* [26] */ + #define USBFS_POWER_CTRL_ENABLE_RCVR_POS (27u) /* [27] */ + #define USBFS_POWER_CTRL_ENABLE_DPO_POS (28u) /* [28] */ + #define USBFS_POWER_CTRL_ENABLE_DMO_POS (29u) /* [29] */ + #define USBFS_POWER_CTRL_ENABLE_CHGDET_POS (30u) /* [30] */ + #define USBFS_POWER_CTRL_ENABLE_POS (31u) /* [31] */ + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_0 ((uint32) 0x00u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_1 ((uint32) 0x01u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO ((uint32) 0x02u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_SUSPEND ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_POS) + #define USBFS_POWER_CTRL_SUSPEND_DEL ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_DEL_POS) + #define USBFS_POWER_CTRL_ISOLATE ((uint32) 0x01u << USBFS_POWER_CTRL_ISOLATE_POS) + #define USBFS_POWER_CTRL_CHDET_PWR_CTL_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_CHDET_PWR_CTL_POS) + #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS) + #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS) + #define USBFS_POWER_CTRL_ENABLE_RCVR ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_RCVR_POS) + #define USBFS_POWER_CTRL_ENABLE_DPO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DPO_POS) + #define USBFS_POWER_CTRL_ENABLE_DMO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DMO_POS) + #define USBFS_POWER_CTRL_ENABLE_CHGDET ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_CHGDET_POS) + #define USBFS_POWER_CTRL_ENABLE ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_POS) + + /* USBFS_CHGDET_CTRL_REG */ + #define USBFS_CHGDET_CTRL_COMP_DP_POS (0u) /* [0] */ + #define USBFS_CHGDET_CTRL_COMP_DM_POS (1u) /* [1] */ + #define USBFS_CHGDET_CTRL_COMP_EN_POS (2u) /* [2] */ + #define USBFS_CHGDET_CTRL_REF_DP_POS (3u) /* [3] */ + #define USBFS_CHGDET_CTRL_REF_DM_POS (4u) /* [4] */ + #define USBFS_CHGDET_CTRL_REF_EN_POS (5u) /* [5] */ + #define USBFS_CHGDET_CTRL_DCD_SRC_EN_POS (6u) /* [6] */ + #define USBFS_CHGDET_CTRL_ADFT_CTRL_POS (12u) /* [12] */ + #define USBFS_CHGDET_CTRL_COMP_OUT_POS (31u) /* [31] */ + #define USBFS_CHGDET_CTRL_COMP_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DP_POS) + #define USBFS_CHGDET_CTRL_COMP_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DM_POS) + #define USBFS_CHGDET_CTRL_COMP_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_EN_POS) + #define USBFS_CHGDET_CTRL_REF_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DP_POS) + #define USBFS_CHGDET_CTRL_REF_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DM_POS) + #define USBFS_CHGDET_CTRL_REF_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_EN_POS) + #define USBFS_CHGDET_CTRL_DCD_SRC_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_DCD_SRC_EN_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_MASK ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_NORMAL ((uint32) 0x00u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_VBG ((uint32) 0x01u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_DONTUSE ((uint32) 0x02u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_ADFTIN ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_COMP_OUT ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_OUT_POS) + + /* USBFS_LPM_CTRL */ + #define USBFS_LPM_CTRL_LPM_EN_POS (0u) + #define USBFS_LPM_CTRL_LPM_ACK_RESP_POS (1u) + #define USBFS_LPM_CTRL_NYET_EN_POS (2u) + #define USBFS_LPM_CTRL_SUB_RESP_POS (4u) + #define USBFS_LPM_CTRL_LPM_EN ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_EN_POS) + #define USBFS_LPM_CTRL_LPM_ACK_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_CTRL_NYET_EN ((uint32) 0x01u << USBFS_LPM_CTRL_NYET_EN_POS) + #define USBFS_LPM_CTRL_ACK_NYET_MASK ((uint32) 0x03u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_CTRL_SUB_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_SUB_RESP_POS) + + #define USBFS_LPM_STAT_LPM_BESL_POS (0u) + #define USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS (4u) + #define USBFS_LPM_STAT_LPM_BESL_MASK ((uint32) 0x0Fu << USBFS_LPM_STAT_LPM_BESL_POS) + #define USBFS_LPM_STAT_LPM_REMOTE_WAKE ((uint32) 0x01u << USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS) + + /* USBFS_INTR_SIE */ + #define USBFS_INTR_SIE_SOF_INTR_POS (0u) /* [0] Interrupt for USB SOF */ + #define USBFS_INTR_SIE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt for BUS RESET */ + #define USBFS_INTR_SIE_EP0_INTR_POS (2u) /* [2] Interrupt for EP0 */ + #define USBFS_INTR_SIE_LPM_INTR_POS (3u) /* [3] Interrupt for LPM */ + #define USBFS_INTR_SIE_RESUME_INTR_POS (4u) /* [4] Interrupt for RESUME (not used by component) */ + #define USBFS_INTR_SIE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_SIE_SOF_INTR_POS) + #define USBFS_INTR_SIE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_SIE_BUS_RESET_INTR_POS) + #define USBFS_INTR_SIE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_SIE_EP0_INTR_POS) + #define USBFS_INTR_SIE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_SIE_LPM_INTR_POS) + #define USBFS_INTR_SIE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_SIE_RESUME_INTR_POS) + + /* USBFS_INTR_CAUSE_LO, MED and HI */ + #define USBFS_INTR_CAUSE_SOF_INTR_POS (0u) /* [0] Interrupt status for USB SOF */ + #define USBFS_INTR_CAUSE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt status for USB BUS RSET */ + #define USBFS_INTR_CAUSE_EP0_INTR_POS (2u) /* [2] Interrupt status for USB EP0 */ + #define USBFS_INTR_CAUSE_LPM_INTR_POS (3u) /* [3] Interrupt status for USB LPM */ + #define USBFS_INTR_CAUSE_RESUME_INTR_POS (4u) /* [4] Interrupt status for USB RESUME */ + #define USBFS_INTR_CAUSE_ARB_INTR_POS (7u) /* [7] Interrupt status for USB ARB */ + #define USBFS_INTR_CAUSE_EP1_INTR_POS (8u) /* [8] Interrupt status for USB EP1 */ + #define USBFS_INTR_CAUSE_EP2_INTR_POS (9u) /* [9] Interrupt status for USB EP2 */ + #define USBFS_INTR_CAUSE_EP3_INTR_POS (10u) /* [10] Interrupt status for USB EP3 */ + #define USBFS_INTR_CAUSE_EP4_INTR_POS (11u) /* [11] Interrupt status for USB EP4 */ + #define USBFS_INTR_CAUSE_EP5_INTR_POS (12u) /* [12] Interrupt status for USB EP5 */ + #define USBFS_INTR_CAUSE_EP6_INTR_POS (13u) /* [13] Interrupt status for USB EP6 */ + #define USBFS_INTR_CAUSE_EP7_INTR_POS (14u) /* [14] Interrupt status for USB EP7 */ + #define USBFS_INTR_CAUSE_EP8_INTR_POS (15u) /* [15] Interrupt status for USB EP8 */ + #define USBFS_INTR_CAUSE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_SOF_INTR_POS) + #define USBFS_INTR_CAUSE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_BUS_RESET_INTR_POS) + #define USBFS_INTR_CAUSE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP0_INTR_POS) + #define USBFS_INTR_CAUSE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_LPM_INTR_POS) + #define USBFS_INTR_CAUSE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_RESUME_INTR_POS) + #define USBFS_INTR_CAUSE_ARB_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_ARB_INTR_POS) + #define USBFS_INTR_CAUSE_EP1_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP1_INTR_POS) + #define USBFS_INTR_CAUSE_EP2_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP2_INTR_POS) + #define USBFS_INTR_CAUSE_EP3_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP3_INTR_POS) + #define USBFS_INTR_CAUSE_EP4_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP4_INTR_POS) + #define USBFS_INTR_CAUSE_EP5_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP5_INTR_POS) + #define USBFS_INTR_CAUSE_EP6_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP6_INTR_POS) + #define USBFS_INTR_CAUSE_EP7_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP7_INTR_POS) + #define USBFS_INTR_CAUSE_EP8_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP8_INTR_POS) + + #define USBFS_INTR_CAUSE_CTRL_INTR_MASK (USBFS_INTR_CAUSE_SOF_INTR | \ + USBFS_INTR_CAUSE_BUS_RESET_INTR | \ + USBFS_INTR_CAUSE_EP0_INTR | \ + USBFS_INTR_CAUSE_LPM_INTR) + + #define USBFS_INTR_CAUSE_EP1_8_INTR_MASK (USBFS_INTR_CAUSE_EP1_INTR | \ + USBFS_INTR_CAUSE_EP2_INTR | \ + USBFS_INTR_CAUSE_EP3_INTR | \ + USBFS_INTR_CAUSE_EP4_INTR | \ + USBFS_INTR_CAUSE_EP5_INTR | \ + USBFS_INTR_CAUSE_EP6_INTR | \ + USBFS_INTR_CAUSE_EP7_INTR | \ + USBFS_INTR_CAUSE_EP8_INTR) + + #define USBFS_INTR_CAUSE_EP_INTR_SHIFT (USBFS_INTR_CAUSE_ARB_INTR_POS - \ + (USBFS_INTR_CAUSE_LPM_INTR_POS + 1u)) + #define USBFS_INTR_CAUSE_SRC_COUNT (13u) + + #define USBFS_CHGDET_CTRL_PRIMARY (USBFS_CHGDET_CTRL_COMP_EN | \ + USBFS_CHGDET_CTRL_COMP_DM | \ + USBFS_CHGDET_CTRL_REF_EN | \ + USBFS_CHGDET_CTRL_REF_DP) + + #define USBFS_CHGDET_CTRL_SECONDARY (USBFS_CHGDET_CTRL_COMP_EN | \ + USBFS_CHGDET_CTRL_COMP_DP | \ + USBFS_CHGDET_CTRL_REF_EN | \ + USBFS_CHGDET_CTRL_REF_DM) + + #define USBFS_CHGDET_CTRL_DEFAULT (0x00000900u) + + +#else /* (CY_PSOC3 || CY_PSOC5LP) */ + #define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK + #define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK + #define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) + + #define USBFS_PM_USB_CR0_REF_EN (0x01u) + #define USBFS_PM_USB_CR0_PD_N (0x02u) + #define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Macros Definitions +***************************************/ + +#if (CY_PSOC4) + #define USBFS_ClearSieInterruptSource(intMask) \ + do{ \ + USBFS_INTR_SIE_REG = (uint32) (intMask); \ + }while(0) +#else + #define USBFS_ClearSieInterruptSource(intMask) \ + do{ /* Does nothing. */ }while(0) +#endif /* (CY_PSOC4) */ + +#define USBFS_ClearSieEpInterruptSource(intMask) \ + do{ \ + USBFS_SIE_EP_INT_SR_REG = (uint8) (intMask); \ + }while(0) + +#define USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \ + (USBFS_MODE_ISO_IN) : (USBFS_MODE_ACK_IN)) + +#define USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \ + (USBFS_MODE_ISO_OUT) : (USBFS_MODE_ACK_OUT)) + +#define USBFS_GET_EP_TYPE(epNumber) (USBFS_EP[epNumber].attrib & USBFS_EP_TYPE_MASK) + +#define USBFS_GET_UINT16(hi, low) (((uint16) ((uint16) (hi) << 8u)) | ((uint16) (low) & 0xFFu)) + + +/*************************************** +* Initialization Register Settings +***************************************/ + +/* Clear device address and enable USB IP respond to USB traffic. */ +#define USBFS_DEFUALT_CR0 (USBFS_CR0_ENABLE) + +/* Arbiter configuration depends on memory management mode. */ +#define USBFS_DEFAULT_ARB_CFG ((USBFS_EP_MANAGEMENT_MANUAL) ? (USBFS_ARB_CFG_DMA_CFG_NONE) : \ + ((USBFS_EP_MANAGEMENT_DMA_MANUAL) ? \ + (USBFS_ARB_CFG_DMA_CFG_MANUAL) : \ + (USBFS_ARB_CFG_AUTO_MEM | USBFS_ARB_CFG_DMA_CFG_AUTO))) + +/* Enable arbiter interrupt for active endpoints only */ +#define USBFS_DEFAULT_ARB_INT_EN \ + ((uint8) ((uint8) USBFS_DMA1_ACTIVE << USBFS_ARB_INT_EP1_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA2_ACTIVE << USBFS_ARB_INT_EP2_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA3_ACTIVE << USBFS_ARB_INT_EP3_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA4_ACTIVE << USBFS_ARB_INT_EP4_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA5_ACTIVE << USBFS_ARB_INT_EP5_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA6_ACTIVE << USBFS_ARB_INT_EP6_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA7_ACTIVE << USBFS_ARB_INT_EP7_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA8_ACTIVE << USBFS_ARB_INT_EP8_INTR_POS)) + +/* Enable all SIE endpoints interrupts */ +#define USBFS_DEFAULT_SIE_EP_INT_EN (USBFS_SIE_INT_EP1_INTR | \ + USBFS_SIE_INT_EP2_INTR | \ + USBFS_SIE_INT_EP3_INTR | \ + USBFS_SIE_INT_EP4_INTR | \ + USBFS_SIE_INT_EP5_INTR | \ + USBFS_SIE_INT_EP6_INTR | \ + USBFS_SIE_INT_EP7_INTR | \ + USBFS_SIE_INT_EP8_INTR) + +#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \ + USBFS_ARB_EPX_CFG_CRC_BYPASS) + +/* Default EP arbiter interrupt source register */ +#define USBFS_ARB_EPX_INT_COMMON_MASK (USBFS_ARB_EPX_INT_IN_BUF_FULL | \ + USBFS_ARB_EPX_INT_BUF_OVER | \ + USBFS_ARB_EPX_INT_BUF_UNDER | \ + USBFS_ARB_EPX_INT_ERR_INT | \ + (USBFS_EP_MANAGEMENT_DMA_MANUAL ? USBFS_ARB_EPX_INT_DMA_GNT : 0u)) + +#define USBFS_CLEAR_REG (0u) + +#if (CY_PSOC4) + /* Set USB lock option when IMO is locked to USB traffic. */ + #define USBFS_DEFUALT_CR1 ((0u != CySysClkImoGetUsbLock()) ? (USBFS_CR1_ENABLE_LOCK) : (0u)) + + /* Recommended value is increased from 3 to 10 due to suppress glitch on + * RSE0 with USB2.0 hubs (LF CLK = 32kHz equal to 350us). */ + #define USBFS_DEFUALT_BUS_RST_CNT (10u) + + /* Select VBUS sources as: valid, PHY of GPIO, and clears isolate bit. */ + /* Application level must ensure that VBUS is valid valid to use. */ + #define USBFS_DEFAULT_POWER_CTRL_VBUS (USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN | \ + ((!USBFS_VBUS_MONITORING_ENABLE) ? \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_1) : \ + (USBFS_VBUS_POWER_PAD_ENABLE ? \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY) : \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO)))) + /* Enable USB IP. */ + #define USBFS_DEFAULT_POWER_CTRL_PHY (USBFS_POWER_CTRL_SUSPEND | \ + USBFS_POWER_CTRL_SUSPEND_DEL | \ + USBFS_POWER_CTRL_ENABLE_RCVR | \ + USBFS_POWER_CTRL_ENABLE_DPO | \ + USBFS_POWER_CTRL_ENABLE_DMO | \ + USBFS_POWER_CTRL_ENABLE) + + /* Assign interrupt between levels lo, med, hi. */ + #define USBFS_DEFAULT_INTR_LVL_SEL ((uint32) (USBFS_INTR_LVL_SEL)) + + /* Enable interrupt source in the INTR_SIE. The SOF is always disabled and EP0 is enabled. */ + #define USBFS_DEFAULT_INTR_SIE_MASK \ + ((uint32) ((uint32) USBFS_BUS_RESET_ISR_ACTIVE << USBFS_INTR_SIE_BUS_RESET_INTR_POS) | \ + (uint32) ((uint32) USBFS_SOF_ISR_ACTIVE << USBFS_INTR_SIE_SOF_INTR_POS) | \ + (uint32) ((uint32) USBFS_LPM_ACTIVE << USBFS_INTR_SIE_LPM_INTR_POS) | \ + (uint32) ((uint32) USBFS_INTR_SIE_EP0_INTR)) + + /* Arbiter interrupt sources */ + #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK | \ + (USBFS_EP_MANAGEMENT_DMA_AUTO ? USBFS_ARB_EPX_INT_DMA_TERMIN : 0u)) + + /* Common DMA configuration */ + #define USBFS_DMA_COMMON_CFG (CYDMA_PULSE | CYDMA_ENTIRE_DESCRIPTOR | \ + CYDMA_NON_PREEMPTABLE) + + +#else + #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK) + + #define USBFS_DEFUALT_CR1 (USBFS_CR1_ENABLE_LOCK) + + /* Recommended value is 3 for LF CLK = 100kHz equal to 100us. */ + #define USBFS_DEFUALT_BUS_RST_CNT (10u) +#endif /* (CY_PSOC4) */ + +/* +* \addtogroup group_deprecated +* @{ */ + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Renamed type definitions */ +#define USBFS_CODE CYCODE +#define USBFS_FAR CYFAR +#if defined(__C51__) || defined(__CX51__) + #define USBFS_DATA data + #define USBFS_XDATA xdata +#else + #define USBFS_DATA + #define USBFS_XDATA +#endif /* __C51__ */ +#define USBFS_NULL NULL +/** @} deprecated */ +/* Renamed structure fields */ +#define wBuffOffset buffOffset +#define wBufferSize bufferSize +#define bStatus status +#define wLength length +#define wCount count + +/* Renamed global variable */ +#define CurrentTD USBFS_currentTD +#define USBFS_interfaceSetting_last USBFS_interfaceSettingLast + +/* Renamed global constants */ +#define USBFS_DWR_VDDD_OPERATION (USBFS_DWR_POWER_OPERATION) + +/* Renamed functions */ +#define USBFS_bCheckActivity USBFS_CheckActivity +#define USBFS_bGetConfiguration USBFS_GetConfiguration +#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting +#define USBFS_bGetEPState USBFS_GetEPState +#define USBFS_wGetEPCount USBFS_GetEPCount +#define USBFS_bGetEPAckState USBFS_GetEPAckState +#define USBFS_bRWUEnabled USBFS_RWUEnabled +#define USBFS_bVBusPresent USBFS_VBusPresent + +#define USBFS_bConfiguration USBFS_configuration +#define USBFS_bInterfaceSetting USBFS_interfaceSetting +#define USBFS_bDeviceAddress USBFS_deviceAddress +#define USBFS_bDeviceStatus USBFS_deviceStatus +#define USBFS_bDevice USBFS_device +#define USBFS_bTransferState USBFS_transferState +#define USBFS_bLastPacketSize USBFS_lastPacketSize + +#define USBFS_LoadEP USBFS_LoadInEP +#define USBFS_LoadInISOCEP USBFS_LoadInEP +#define USBFS_EnableOutISOCEP USBFS_EnableOutEP + +#define USBFS_SetVector CyIntSetVector +#define USBFS_SetPriority CyIntSetPriority +#define USBFS_EnableInt CyIntEnable + +/* Replace with register access. */ +#define USBFS_bmRequestType USBFS_EP0_DR0_PTR +#define USBFS_bRequest USBFS_EP0_DR1_PTR +#define USBFS_wValue USBFS_EP0_DR2_PTR +#define USBFS_wValueHi USBFS_EP0_DR3_PTR +#define USBFS_wValueLo USBFS_EP0_DR2_PTR +#define USBFS_wIndex USBFS_EP0_DR4_PTR +#define USBFS_wIndexHi USBFS_EP0_DR5_PTR +#define USBFS_wIndexLo USBFS_EP0_DR4_PTR +#define USBFS_length USBFS_EP0_DR6_PTR +#define USBFS_lengthHi USBFS_EP0_DR7_PTR +#define USBFS_lengthLo USBFS_EP0_DR6_PTR + +/* Rename VBUS monitoring registers. */ +#if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_MONITORING_INTERNAL) + #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_DR_REG (*(reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_PS_REG (*(reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_MASK USBFS_VBUS__MASK + #else + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_MASK (0x01u) + #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */ + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ + + /* Pointer DIE structure in flash (8 bytes): Y and X location, wafer, lot msb, lot lsb, + * work week, fab/year, minor. */ + #define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (USBFS_DMA1_ACTIVE) + #define USBFS_ep1_TD_TERMOUT_EN (USBFS_ep1__TD_TERMOUT_EN) + #else + #define USBFS_ep1_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + #define USBFS_ep2_TD_TERMOUT_EN (USBFS_ep2__TD_TERMOUT_EN) + #else + #define USBFS_ep2_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + #define USBFS_ep3_TD_TERMOUT_EN (USBFS_ep3__TD_TERMOUT_EN) + #else + #define USBFS_ep3_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + #define USBFS_ep4_TD_TERMOUT_EN (USBFS_ep4__TD_TERMOUT_EN) + #else + #define USBFS_ep4_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + #define USBFS_ep5_TD_TERMOUT_EN (USBFS_ep5__TD_TERMOUT_EN) + #else + #define USBFS_ep5_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + #define USBFS_ep6_TD_TERMOUT_EN (USBFS_ep6__TD_TERMOUT_EN) + #else + #define USBFS_ep6_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + #define USBFS_ep7_TD_TERMOUT_EN (USBFS_ep7__TD_TERMOUT_EN) + #else + #define USBFS_ep7_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + #define USBFS_ep8_TD_TERMOUT_EN (USBFS_ep8__TD_TERMOUT_EN) + #else + #define USBFS_ep8_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA8_ACTIVE) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +/* Rename USB IP registers. */ #define USBFS_ARB_CFG USBFS_ARB_CFG_PTR #define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR @@ -1060,167 +2029,14 @@ extern volatile uint8 USBFS_deviceStatus; #define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR #define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR -#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) - -#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) - /* PSoC3 interrupt registers*/ - #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) - #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) - #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) - #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) -#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) - /* PSoC5 interrupt registers*/ - #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) - #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) - #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) - #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) -#endif /* CYDEV_CHIP_DIE_EXPECT */ - - -/*************************************** -* Interrupt vectors, masks and priorities -***************************************/ - -#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM -#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK -#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER - -#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM -#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK -#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER - -#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM -#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK -#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER - -#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM -#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK -#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER - -#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM -#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK -#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER - -#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM -#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK -#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER - -#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM -#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK -#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER - -#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM -#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK -#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER - -#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM -#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK -#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER - -#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM -#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK -#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER - -#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM -#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK -#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER - -#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM -#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK -#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER - -/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */ -#define USBFS_ARB_PRIOR (0u) -#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK -#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER - -/*************************************** - * Endpoint 0 offsets (Table 9-2) - **************************************/ - -#define USBFS_bmRequestType USBFS_EP0_DR0_PTR -#define USBFS_bRequest USBFS_EP0_DR1_PTR -#define USBFS_wValue USBFS_EP0_DR2_PTR -#define USBFS_wValueHi USBFS_EP0_DR3_PTR -#define USBFS_wValueLo USBFS_EP0_DR2_PTR -#define USBFS_wIndex USBFS_EP0_DR4_PTR -#define USBFS_wIndexHi USBFS_EP0_DR5_PTR -#define USBFS_wIndexLo USBFS_EP0_DR4_PTR -#define USBFS_length USBFS_EP0_DR6_PTR -#define USBFS_lengthHi USBFS_EP0_DR7_PTR -#define USBFS_lengthLo USBFS_EP0_DR6_PTR - - -/*************************************** -* Register Constants -***************************************/ -#define USBFS_VDDD_MV CYDEV_VDDD_MV -#define USBFS_3500MV (3500u) - -#define USBFS_CR1_REG_ENABLE (0x01u) -#define USBFS_CR1_ENABLE_LOCK (0x02u) -#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) -#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT)) -#define USBFS_CR1_TRIM_MSB_EN (0x08u) - -#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) -#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) -#define USBFS_EPX_CNT0_MASK (0x0Fu) -#define USBFS_EPX_CNTX_MSB_MASK (0x07u) -#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) -#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) -#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) -#define USBFS_EPX_DATA_BUF_MAX (512u) - -#define USBFS_CR0_ENABLE (0x80u) - -/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */ -#define USBFS_BUS_RST_COUNT (0x0au) - -#define USBFS_USBIO_CR1_IOMODE (0x20u) -#define USBFS_USBIO_CR1_USBPUEN (0x04u) -#define USBFS_USBIO_CR1_DP0 (0x02u) -#define USBFS_USBIO_CR1_DM0 (0x01u) - -#define USBFS_USBIO_CR0_TEN (0x80u) -#define USBFS_USBIO_CR0_TSE0 (0x40u) -#define USBFS_USBIO_CR0_TD (0x20u) -#define USBFS_USBIO_CR0_RD (0x01u) - -#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) -#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) -#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) - -#define USBFS_ARB_EPX_CFG_RESET (0x08u) -#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u) -#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u) -#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u) -#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \ - USBFS_ARB_EPX_CFG_CRC_BYPASS) - -#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) -#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) -#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) -#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) - -#define USBFS_ARB_CFG_AUTO_MEM (0x10u) -#define USBFS_ARB_CFG_MANUAL_DMA (0x20u) -#define USBFS_ARB_CFG_AUTO_DMA (0x40u) -#define USBFS_ARB_CFG_CFG_CPM (0x80u) - -#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - #define USBFS_ARB_EPX_INT_MASK (0x1Du) -#else - #define USBFS_ARB_EPX_INT_MASK (0x1Fu) -#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ -#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \ - (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \ - (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \ - (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \ - (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \ - (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \ - (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \ - (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) ) +#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DM_INP_DIS_REG (*(reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INP_DIS_REG (*(reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DP_INTSTAT_REG (*(reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DM_MASK USBFS_Dm__0__MASK +#define USBFS_DP_MASK USBFS_Dp__0__MASK #define USBFS_SIE_EP_INT_EP1_MASK (0x01u) #define USBFS_SIE_EP_INT_EP2_MASK (0x02u) @@ -1231,25 +2047,35 @@ extern volatile uint8 USBFS_deviceStatus; #define USBFS_SIE_EP_INT_EP7_MASK (0x40u) #define USBFS_SIE_EP_INT_EP8_MASK (0x80u) -#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK -#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK -#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) +#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) +#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) +#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) +#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) -#define USBFS_PM_USB_CR0_REF_EN (0x01u) -#define USBFS_PM_USB_CR0_PD_N (0x02u) -#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) +#define USBFS_ARB_EPX_INT_EN_ALL USBFS_ARB_EPX_INT_ALL -#define USBFS_USB_CLK_ENABLE (0x01u) +#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) -#define USBFS_DM_MASK USBFS_Dm__0__MASK -#define USBFS_DP_MASK USBFS_Dp__0__MASK +#define USBFS_BUS_RST_COUNT USBFS_DEFUALT_BUS_RST_CNT -#define USBFS_DYN_RECONFIG_ENABLE (0x01u) -#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u) -#define USBFS_DYN_RECONFIG_RDY_STS (0x10u) +#define USBFS_ARB_INT_MASK USBFS_DEFAULT_ARB_INT_EN + +#if (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) + /* CY_PSOC3 interrupt registers */ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) +#elif (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) + /* CY_PSOC5LP interrupt registers */ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) +#endif /* CYDEV_CHIP_DIE_EXPECT */ -#endif /* CY_USBFS_USBFS_H */ +#endif /* (CY_USBFS_USBFS_H) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c old mode 100644 new mode 100755 index 6bb45af..66e41ca --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: USBFS_Dm.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: USBFS_Dm_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Write *******************************************************************************/ -void USBFS_Dm_Write(uint8 value) +void USBFS_Dm_Write(uint8 value) { uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); @@ -45,28 +63,31 @@ void USBFS_Dm_Write(uint8 value) /******************************************************************************* * Function Name: USBFS_Dm_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* USBFS_Dm_DM_STRONG Strong Drive -* USBFS_Dm_DM_OD_HI Open Drain, Drives High -* USBFS_Dm_DM_OD_LO Open Drain, Drives Low -* USBFS_Dm_DM_RES_UP Resistive Pull Up -* USBFS_Dm_DM_RES_DWN Resistive Pull Down -* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down -* USBFS_Dm_DM_DIG_HIZ High Impedance Digital -* USBFS_Dm_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetDriveMode *******************************************************************************/ -void USBFS_Dm_SetDriveMode(uint8 mode) +void USBFS_Dm_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(USBFS_Dm_0, mode); } @@ -74,23 +95,22 @@ void USBFS_Dm_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: USBFS_Dm_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro USBFS_Dm_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Read *******************************************************************************/ -uint8 USBFS_Dm_Read(void) +uint8 USBFS_Dm_Read(void) { return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; } @@ -98,42 +118,102 @@ uint8 USBFS_Dm_Read(void) /******************************************************************************* * Function Name: USBFS_Dm_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred USBFS_Dm_Read() API because the +* USBFS_Dm_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ReadDataReg *******************************************************************************/ -uint8 USBFS_Dm_ReadDataReg(void) +uint8 USBFS_Dm_ReadDataReg(void) { return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(USBFS_Dm_INTSTAT) /******************************************************************************* - * Function Name: USBFS_Dm_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: USBFS_Dm_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use USBFS_Dm_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - USBFS_Dm_0_INTR (First pin in the list) + * - USBFS_Dm_1_INTR (Second pin in the list) + * - ... + * - USBFS_Dm_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetInterruptMode *******************************************************************************/ - uint8 USBFS_Dm_ClearInterrupt(void) + void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & USBFS_Dm_0_INTR) != 0u) + { + USBFS_Dm_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: USBFS_Dm_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ClearInterrupt + *******************************************************************************/ + uint8 USBFS_Dm_ClearInterrupt(void) { return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h old mode 100644 new mode 100755 index 5166935..b0c637c --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: USBFS_Dm.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "USBFS_Dm_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void USBFS_Dm_Write(uint8 value) ; -void USBFS_Dm_SetDriveMode(uint8 mode) ; -uint8 USBFS_Dm_ReadDataReg(void) ; -uint8 USBFS_Dm_Read(void) ; -uint8 USBFS_Dm_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_Dm_Write(uint8 value); +void USBFS_Dm_SetDriveMode(uint8 mode); +uint8 USBFS_Dm_ReadDataReg(void); +uint8 USBFS_Dm_Read(void); +void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode); +uint8 USBFS_Dm_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP -#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN -#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO -#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI -#define USBFS_Dm_DM_STRONG PIN_DM_STRONG -#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the USBFS_Dm_SetDriveMode() function. + * @{ + */ + #define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP + #define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN + #define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO + #define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI + #define USBFS_Dm_DM_STRONG PIN_DM_STRONG + #define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define USBFS_Dm_MASK USBFS_Dm__MASK #define USBFS_Dm_SHIFT USBFS_Dm__SHIFT #define USBFS_Dm_WIDTH 1u +/* Interrupt constants */ +#if defined(USBFS_Dm__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in USBFS_Dm_SetInterruptMode() function. + * @{ + */ + #define USBFS_Dm_INTR_NONE (uint16)(0x0000u) + #define USBFS_Dm_INTR_RISING (uint16)(0x0001u) + #define USBFS_Dm_INTR_FALLING (uint16)(0x0002u) + #define USBFS_Dm_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define USBFS_Dm_INTR_MASK (0x01u) +#endif /* (USBFS_Dm__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 USBFS_Dm_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(USBFS_Dm__SIO_CFG) + #define USBFS_Dm_SIO_HYST_EN (* (reg8 *) USBFS_Dm__SIO_HYST_EN) + #define USBFS_Dm_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dm__SIO_REG_HIFREQ) + #define USBFS_Dm_SIO_CFG (* (reg8 *) USBFS_Dm__SIO_CFG) + #define USBFS_Dm_SIO_DIFF (* (reg8 *) USBFS_Dm__SIO_DIFF) +#endif /* (USBFS_Dm__SIO_CFG) */ -#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */ - - #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) - #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(USBFS_Dm__INTSTAT) + #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) + #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) + + #define USBFS_Dm_0_INTTYPE_REG (* (reg8 *) USBFS_Dm__0__INTTYPE) +#endif /* (USBFS_Dm__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h old mode 100644 new mode 100755 index faf0870..1034b60 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: USBFS_Dm.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define USBFS_Dm_0 (USBFS_Dm__0__PC) +#define USBFS_Dm_0 (USBFS_Dm__0__PC) +#define USBFS_Dm_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dm__0__SHIFT)) + +#define USBFS_Dm_INTR_ALL ((uint16)(USBFS_Dm_0_INTR)) #endif /* End Pins USBFS_Dm_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c old mode 100644 new mode 100755 index 7121119..f94a750 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: USBFS_Dp.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: USBFS_Dp_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Write *******************************************************************************/ -void USBFS_Dp_Write(uint8 value) +void USBFS_Dp_Write(uint8 value) { uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); @@ -45,28 +63,31 @@ void USBFS_Dp_Write(uint8 value) /******************************************************************************* * Function Name: USBFS_Dp_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. * -* USBFS_Dp_DM_STRONG Strong Drive -* USBFS_Dp_DM_OD_HI Open Drain, Drives High -* USBFS_Dp_DM_OD_LO Open Drain, Drives Low -* USBFS_Dp_DM_RES_UP Resistive Pull Up -* USBFS_Dp_DM_RES_DWN Resistive Pull Down -* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down -* USBFS_Dp_DM_DIG_HIZ High Impedance Digital -* USBFS_Dp_DM_ALG_HIZ High Impedance Analog +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. * -* Return: +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetDriveMode *******************************************************************************/ -void USBFS_Dp_SetDriveMode(uint8 mode) +void USBFS_Dp_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(USBFS_Dp_0, mode); } @@ -74,23 +95,22 @@ void USBFS_Dp_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: USBFS_Dp_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro USBFS_Dp_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Read *******************************************************************************/ -uint8 USBFS_Dp_Read(void) +uint8 USBFS_Dp_Read(void) { return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; } @@ -98,42 +118,102 @@ uint8 USBFS_Dp_Read(void) /******************************************************************************* * Function Name: USBFS_Dp_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred USBFS_Dp_Read() API because the +* USBFS_Dp_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ReadDataReg *******************************************************************************/ -uint8 USBFS_Dp_ReadDataReg(void) +uint8 USBFS_Dp_ReadDataReg(void) { return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(USBFS_Dp_INTSTAT) /******************************************************************************* - * Function Name: USBFS_Dp_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + * Function Name: USBFS_Dp_SetInterruptMode + ****************************************************************************//** * - * Parameters: - * None + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. * - * Return: - * Returns the value of the interrupt status register + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use USBFS_Dp_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - USBFS_Dp_0_INTR (First pin in the list) + * - USBFS_Dp_1_INTR (Second pin in the list) + * - ... + * - USBFS_Dp_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetInterruptMode *******************************************************************************/ - uint8 USBFS_Dp_ClearInterrupt(void) + void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & USBFS_Dp_0_INTR) != 0u) + { + USBFS_Dp_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: USBFS_Dp_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ClearInterrupt + *******************************************************************************/ + uint8 USBFS_Dp_ClearInterrupt(void) { return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h old mode 100644 new mode 100755 index fb0a19c..1e89e5a --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: USBFS_Dp.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "USBFS_Dp_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void USBFS_Dp_Write(uint8 value) ; -void USBFS_Dp_SetDriveMode(uint8 mode) ; -uint8 USBFS_Dp_ReadDataReg(void) ; -uint8 USBFS_Dp_Read(void) ; -uint8 USBFS_Dp_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_Dp_Write(uint8 value); +void USBFS_Dp_SetDriveMode(uint8 mode); +uint8 USBFS_Dp_ReadDataReg(void); +uint8 USBFS_Dp_Read(void); +void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode); +uint8 USBFS_Dp_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP -#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN -#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO -#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI -#define USBFS_Dp_DM_STRONG PIN_DM_STRONG -#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the USBFS_Dp_SetDriveMode() function. + * @{ + */ + #define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP + #define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN + #define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO + #define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI + #define USBFS_Dp_DM_STRONG PIN_DM_STRONG + #define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define USBFS_Dp_MASK USBFS_Dp__MASK #define USBFS_Dp_SHIFT USBFS_Dp__SHIFT #define USBFS_Dp_WIDTH 1u +/* Interrupt constants */ +#if defined(USBFS_Dp__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in USBFS_Dp_SetInterruptMode() function. + * @{ + */ + #define USBFS_Dp_INTR_NONE (uint16)(0x0000u) + #define USBFS_Dp_INTR_RISING (uint16)(0x0001u) + #define USBFS_Dp_INTR_FALLING (uint16)(0x0002u) + #define USBFS_Dp_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define USBFS_Dp_INTR_MASK (0x01u) +#endif /* (USBFS_Dp__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,21 @@ uint8 USBFS_Dp_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) +/* SIO registers */ +#if defined(USBFS_Dp__SIO_CFG) + #define USBFS_Dp_SIO_HYST_EN (* (reg8 *) USBFS_Dp__SIO_HYST_EN) + #define USBFS_Dp_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dp__SIO_REG_HIFREQ) + #define USBFS_Dp_SIO_CFG (* (reg8 *) USBFS_Dp__SIO_CFG) + #define USBFS_Dp_SIO_DIFF (* (reg8 *) USBFS_Dp__SIO_DIFF) +#endif /* (USBFS_Dp__SIO_CFG) */ -#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */ - - #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) - #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) - -#endif /* Interrupt Registers */ +/* Interrupt Registers */ +#if defined(USBFS_Dp__INTSTAT) + #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) + + #define USBFS_Dp_0_INTTYPE_REG (* (reg8 *) USBFS_Dp__0__INTTYPE) +#endif /* (USBFS_Dp__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h old mode 100644 new mode 100755 index 5268950..ebb6a3c --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: USBFS_Dp.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,12 +22,15 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define USBFS_Dp_0 (USBFS_Dp__0__PC) +#define USBFS_Dp_0 (USBFS_Dp__0__PC) +#define USBFS_Dp_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dp__0__SHIFT)) + +#define USBFS_Dp_INTR_ALL ((uint16)(USBFS_Dp_0_INTR)) #endif /* End Pins USBFS_Dp_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c index 58fa966..b3152a1 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c @@ -1,32 +1,27 @@ -/******************************************************************************* -* File Name: USBFS_audio.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_audio.c +* \version 3.10 * -* Description: -* USB AUDIO Class request handler. +* \brief +* This file contains the USB AUDIO Class request handler. * * Related Document: * Universal Serial Bus Device Class Definition for Audio Devices Release 1.0 * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" +#include "USBFS_audio.h" +#include "USBFS_pvt.h" #if defined(USBFS_ENABLE_AUDIO_CLASS) -#include "USBFS_audio.h" -#include "USBFS_pvt.h" -#if defined(USBFS_ENABLE_MIDI_STREAMING) - #include "USBFS_midi.h" -#endif /* USBFS_ENABLE_MIDI_STREAMING*/ - - /*************************************** * Custom Declarations ***************************************/ @@ -38,15 +33,24 @@ #if !defined(USER_SUPPLIED_AUDIO_HANDLER) - /*************************************** * AUDIO Variables ***************************************/ #if defined(USBFS_ENABLE_AUDIO_STREAMING) + /** Contains the current audio sample frequency. It is set by the host using a SET_CUR request to the endpoint.*/ volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; + /** Used as a flag for the user code, to inform it that the host has been sent a request + * to change the sample frequency. The sample frequency will be sent on the next OUT transaction. + * It contains the endpoint address when set. The following code is recommended for + * detecting new sample frequency in main code: + * \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency + * + * The USBFS_transferState variable is checked to make sure that the transfer completes. */ volatile uint8 USBFS_frequencyChanged; + /** Contains the mute configuration set by the host.*/ volatile uint8 USBFS_currentMute; + /** Contains the volume level set by the host.*/ volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB, USBFS_VOL_MIN_MSB}; @@ -59,18 +63,16 @@ /******************************************************************************* * Function Name: USBFS_DispatchAUDIOClassRqst -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine dispatches class requests * -* Parameters: -* None. +* \return +* Results of Audio Class request handling: +* - USBFS_TRUE - request was handled without errors +* - USBFS_FALSE - error occurs during handling of request * -* Return: -* requestHandled -* -* Global variables: +* \globalvars * USBFS_currentSampleFrequency: Contains the current audio Sample * Frequency. It is set by the Host using SET_CUR request to the endpoint. * USBFS_frequencyChanged: This variable is used as a flag for the @@ -78,99 +80,103 @@ * Sample Frequency. Sample frequency will be sent on the next OUT * transaction. It is contains endpoint address when set. The following * code is recommended for detecting new Sample Frequency in main code: -* if((USBFS_frequencyChanged != 0) && -* (USBFS_transferState == USBFS_TRANS_STATE_IDLE)) -* { -* USBFS_frequencyChanged = 0; -* } -* USBFS_transferState variable is checked to be sure that -* transfer completes. +* +* \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency +* +* USBFS_transferState variable is checked to be sure that transfer +* completes. * USBFS_currentMute: Contains mute configuration set by Host. * USBFS_currentVolume: Contains volume level set by Host. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_DispatchAUDIOClassRqst(void) { uint8 requestHandled = USBFS_FALSE; - uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType); - - #if defined(USBFS_ENABLE_AUDIO_STREAMING) - uint8 epNumber; - epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - #endif /* USBFS_ENABLE_AUDIO_STREAMING */ - - - if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + + uint8 RqstRcpt = (uint8)(USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK); +#if defined(USBFS_ENABLE_AUDIO_STREAMING) + uint8 wValueHi = (uint8) USBFS_wValueHiReg; + uint8 epNumber = (uint8) USBFS_wIndexLoReg & USBFS_DIR_UNUSED; +#endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) { - /* Control Read */ - if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP) + /* Handle direction from device to host. */ + + if (USBFS_RQST_RCPT_EP == RqstRcpt) { - /* Endpoint */ - switch (CY_GET_REG8(USBFS_bRequest)) + /* Request recipient is to endpoint. */ + switch (USBFS_bRequestReg) { case USBFS_GET_CUR: #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL) { /* point Control Selector is Sampling Frequency */ USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlRead(); } - #endif /* USBFS_ENABLE_AUDIO_STREAMING */ - - /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ - - /* `#END` */ + #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK - USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK */ + /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ - break; + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK) */ + break; + default: + /* Do not handle this request unless callback is defined. */ break; } + } - else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC) + else if (USBFS_RQST_RCPT_IFC == RqstRcpt) { - /* Interface or Entity ID */ - switch (CY_GET_REG8(USBFS_bRequest)) + /* Request recipient is interface or entity ID. */ + switch (USBFS_bRequestReg) { case USBFS_GET_CUR: #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + if (wValueHi == USBFS_MUTE_CONTROL) { /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */ /* `#END` */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK - USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK) */ /* Entity ID Control Selector is MUTE */ USBFS_currentTD.wCount = 1u; USBFS_currentTD.pData = &USBFS_currentMute; - requestHandled = USBFS_InitControlRead(); + + requestHandled = USBFS_InitControlRead(); } - else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + else if (wValueHi == USBFS_VOLUME_CONTROL) { /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */ /* `#END` */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK - USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK) */ /* Entity ID Control Selector is VOLUME, */ USBFS_currentTD.wCount = USBFS_VOLUME_LEN; USBFS_currentTD.pData = USBFS_currentVolume; - requestHandled = USBFS_InitControlRead(); + + requestHandled = USBFS_InitControlRead(); } else { @@ -178,134 +184,149 @@ uint8 USBFS_DispatchAUDIOClassRqst(void) /* `#END` */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK - USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK) */ } break; - case USBFS_GET_MIN: /* GET_MIN */ - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + + case USBFS_GET_MIN: + if (wValueHi == USBFS_VOLUME_CONTROL) { /* Entity ID Control Selector is VOLUME, */ USBFS_currentTD.wCount = USBFS_VOLUME_LEN; USBFS_currentTD.pData = &USBFS_minimumVolume[0]; - requestHandled = USBFS_InitControlRead(); + + requestHandled = USBFS_InitControlRead(); } break; - case USBFS_GET_MAX: /* GET_MAX */ - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + + case USBFS_GET_MAX: + if (wValueHi == USBFS_VOLUME_CONTROL) { /* Entity ID Control Selector is VOLUME, */ USBFS_currentTD.wCount = USBFS_VOLUME_LEN; USBFS_currentTD.pData = &USBFS_maximumVolume[0]; - requestHandled = USBFS_InitControlRead(); + + requestHandled = USBFS_InitControlRead(); } break; - case USBFS_GET_RES: /* GET_RES */ - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + + case USBFS_GET_RES: + if (wValueHi == USBFS_VOLUME_CONTROL) { /* Entity ID Control Selector is VOLUME, */ USBFS_currentTD.wCount = USBFS_VOLUME_LEN; USBFS_currentTD.pData = &USBFS_resolutionVolume[0]; + requestHandled = USBFS_InitControlRead(); } break; + /* The contents of the status message is reserved for future use. - * For the time being, a null packet should be returned in the data stage of the - * control transfer, and the received null packet should be ACKed. + * For the time being, a null packet should be returned in the data stage of the + * control transfer, and the received null packet should be ACKed. */ case USBFS_GET_STAT: - USBFS_currentTD.wCount = 0u; - requestHandled = USBFS_InitControlWrite(); + USBFS_currentTD.wCount = 0u; + + requestHandled = USBFS_InitControlWrite(); - #endif /* USBFS_ENABLE_AUDIO_STREAMING */ - - /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ - - /* `#END` */ + #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ + + /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ + /* `#END` */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK */ - + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK) */ break; + default: + /* Do not handle this request. */ break; } } else - { /* USBFS_RQST_RCPT_OTHER */ + { + /* Do not handle other requests recipients. */ } } else { - /* Control Write */ - if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP) + /* Handle direction from host to device. */ + + if (USBFS_RQST_RCPT_EP == RqstRcpt) { - /* point */ - switch (CY_GET_REG8(USBFS_bRequest)) + /* Request recipient is endpoint. */ + switch (USBFS_bRequestReg) { case USBFS_SET_CUR: #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL) { /* point Control Selector is Sampling Frequency */ USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + USBFS_frequencyChanged = (uint8) epNumber; + requestHandled = USBFS_InitControlWrite(); - USBFS_frequencyChanged = epNumber; } - #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ - /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ + /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ - /* `#END` */ + /* `#END` */ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK */ - + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK) */ break; + default: + /* Do not handle this request. */ break; } } - else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC) + else if(USBFS_RQST_RCPT_IFC == RqstRcpt) { - /* Interface or Entity ID */ - switch (CY_GET_REG8(USBFS_bRequest)) + /* Request recipient is interface or entity ID. */ + switch (USBFS_bRequestReg) { case USBFS_SET_CUR: #if defined(USBFS_ENABLE_AUDIO_STREAMING) - if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + if (wValueHi == USBFS_MUTE_CONTROL) { /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */ /* `#END` */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK - USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK) */ /* Entity ID Control Selector is MUTE */ USBFS_currentTD.wCount = 1u; USBFS_currentTD.pData = &USBFS_currentMute; - requestHandled = USBFS_InitControlWrite(); + + requestHandled = USBFS_InitControlWrite(); } - else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + else if (wValueHi == USBFS_VOLUME_CONTROL) { /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */ /* `#END` */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK - USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK) */ /* Entity ID Control Selector is VOLUME */ USBFS_currentTD.wCount = USBFS_VOLUME_LEN; USBFS_currentTD.pData = USBFS_currentVolume; - requestHandled = USBFS_InitControlWrite(); + + requestHandled = USBFS_InitControlWrite(); } else { @@ -313,35 +334,36 @@ uint8 USBFS_DispatchAUDIOClassRqst(void) /* `#END` */ - #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK - USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK) */ } #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + + /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ - /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ - - /* `#END` */ - + /* `#END` */ + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK */ + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK) */ + break; - break; default: - break; + /* Do not handle this request. */ + break; } } else { - /* USBFS_RQST_RCPT_OTHER */ + /* Do not handle other requests recipients. */ } } - return(requestHandled); + return (requestHandled); } - -#endif /* USER_SUPPLIED_AUDIO_HANDLER */ +#endif /* (USER_SUPPLIED_AUDIO_HANDLER) */ /******************************************************************************* @@ -352,7 +374,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void) /* `#END` */ -#endif /* USBFS_ENABLE_AUDIO_CLASS */ +#endif /* (USBFS_ENABLE_AUDIO_CLASS) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h old mode 100644 new mode 100755 index 0cae2dc..1678bd9 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h @@ -1,15 +1,17 @@ -/******************************************************************************* -* File Name: USBFS_audio.h -* Version 2.80 +/***************************************************************************//** +* \file USBFS_audio.h +* \version 3.10 * -* Description: -* Header File for the USBFS component. Contains prototypes and constant values. +* \brief +* This file provides function prototypes and constants for the USBFS component +* Audio class. * * Related Document: * Universal Serial Bus Device Class Definition for Audio Devices Release 1.0 * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -18,7 +20,7 @@ #if !defined(CY_USBFS_USBFS_audio_H) #define CY_USBFS_USBFS_audio_H -#include "cytypes.h" +#include "USBFS.h" /*************************************** @@ -82,12 +84,16 @@ /*************************************** * External data references ***************************************/ - -extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP] - [USBFS_SAMPLE_FREQ_LEN]; +/** +* \addtogroup group_audio +* @{ +*/ +extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; extern volatile uint8 USBFS_frequencyChanged; extern volatile uint8 USBFS_currentMute; extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; +/** @} audio */ + extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN]; extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN]; extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN]; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c old mode 100644 new mode 100755 index 75b9127..1f31349 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c @@ -1,76 +1,67 @@ -/******************************************************************************* -* File Name: USBFS_boot.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_boot.c +* \version 3.10 * -* Description: -* Boot loader API for USBFS Component. -* -* Note: +* \brief +* This file contains the Bootloader API for USBFS Component. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" +#include "USBFS_pvt.h" #if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ - (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) - + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) /*************************************** * Bootloader Variables ***************************************/ + static uint8 USBFS_started = 0u; /******************************************************************************* * Function Name: USBFS_CyBtldrCommStart -******************************************************************************** +****************************************************************************//** * -* Summary: -* Starts the component and enables the interrupt. +* This function performs all required initialization for the USBFS component, +* waits on enumeration, and enables communication. * -* Parameters: -* None. -* -* Return: -* None. -* -* Side Effects: +* \sideeffect * This function starts the USB with 3V or 5V operation. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_CyBtldrCommStart(void) { - CyGlobalIntEnable; /* Enable Global Interrupts */ + /* Enable Global Interrupts. Interrupts are mandatory for USBFS component operation. */ + CyGlobalIntEnable; - /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */ - USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION); + /* Start USBFS Operation: device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR. */ + USBFS_Start(0u, USBFS_DWR_POWER_OPERATION); - /* USB component started, the correct enumeration will be checked in first Read operation */ + /* USB component started, the correct enumeration will be checked in the first Read operation. */ USBFS_started = 1u; } /******************************************************************************* * Function Name: USBFS_CyBtldrCommStop. -******************************************************************************** +****************************************************************************//** * -* Summary: -* Disable the component and disable the interrupt. -* -* Parameters: -* None. -* -* Return: -* None. +* This function performs all necessary shutdown tasks required for the USBFS +* component. +* +* \sideeffect +* Calls the USBFS_Stop() function. * *******************************************************************************/ void USBFS_CyBtldrCommStop(void) @@ -81,47 +72,40 @@ void USBFS_CyBtldrCommStop(void) /******************************************************************************* * Function Name: USBFS_CyBtldrCommReset. -******************************************************************************** +****************************************************************************//** * -* Summary: -* Resets the receive and transmit communication Buffers. +* This function resets receive and transmit communication buffers. * -* Parameters: -* None -* -* Return: -* None -* -* Reentrant: +* \reentrant * No * *******************************************************************************/ void USBFS_CyBtldrCommReset(void) { - USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */ + USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); } /******************************************************************************* * Function Name: USBFS_CyBtldrCommWrite. -******************************************************************************** +****************************************************************************//** * -* Summary: -* Allows the caller to write data to the boot loader host. The function will -* handle polling to allow a block of data to be completely sent to the host +* This function allows the caller to write data to the bootloader host. It +* handles polling to allow a block of data to be completely sent to the host * device. * -* Parameters: -* pData: A pointer to the block of data to send to the device -* size: The number of bytes to write. -* count: Pointer to an unsigned short variable to write the number of -* bytes actually written. -* timeOut: Number of units to wait before returning because of a timeout. +* \param pData A pointer to the block of data to send to the device +* \param size The number of bytes to write. +* \param count Pointer to an unsigned short variable to write the number of +* bytes actually written. +* \param timeOut Number of units to wait before returning because of a timeout. * -* Return: -* Returns the value that best describes the problem. +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value that +* best describes the problem. For more information, see the “Return Codes” +* section of the System Reference Guide. * -* Reentrant: +* \reentrant * No * *******************************************************************************/ @@ -131,12 +115,13 @@ cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, cystatus retCode; uint16 timeoutMs; - timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */ + /* Convert 10mS checks into 1mS checks. */ + timeoutMs = ((uint16) 10u * timeOut); - /* Enable IN transfer */ + /* Load data into IN endpoint to be read by host. */ USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER); - /* Wait for the master to read it. */ + /* Wait unitl host reads data from IN endpoint. */ while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && (0u != timeoutMs)) { @@ -154,32 +139,32 @@ cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, retCode = CYRET_SUCCESS; } - return(retCode); + return (retCode); } /******************************************************************************* * Function Name: USBFS_CyBtldrCommRead. -******************************************************************************** +****************************************************************************//** * -* Summary: -* Allows the caller to read data from the boot loader host. The function will -* handle polling to allow a block of data to be completely received from the +* This function allows the caller to read data from the bootloader host. It +* handles polling to allow a block of data to be completely received from the * host device. * -* Parameters: -* pData: A pointer to the area to store the block of data received -* from the device. -* size: The number of bytes to read. -* count: Pointer to an unsigned short variable to write the number -* of bytes actually read. -* timeOut: Number of units to wait before returning because of a timeOut. -* Timeout is measured in 10s of ms. +* \param pData A pointer to the area to store the block of data received +* from the device. +* \param size The number of bytes to read. +* \param count Pointer to an unsigned short variable to write the number +* of bytes actually read. +* \param timeOut Number of units to wait before returning because of a timeOut. +* Timeout is measured in 10s of ms. * -* Return: -* Returns the value that best describes the problem. +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value that +* best describes the problem. For more information, see the “Return Codes” +* section of the System Reference Guide. * -* Reentrant: +* \reentrant * No * *******************************************************************************/ @@ -189,36 +174,38 @@ cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 cystatus retCode; uint16 timeoutMs; - timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */ + /* Convert 10mS checks into 1mS checks. */ + timeoutMs = ((uint16) 10u * timeOut); if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER) { size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; } - /* Wait on enumeration in first time */ + /* Wait for enumeration first time. */ if (0u != USBFS_started) { - /* Wait for Device to enumerate */ - while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs)) + /* Wait for device enumeration. */ + while ((0u == USBFS_GetConfiguration()) && (0u != timeoutMs)) { CyDelay(USBFS_BTLDR_WAIT_1_MS); timeoutMs--; } - /* Enable first OUT, if enumeration complete */ + /* Enable OUT after enumeration. */ if (0u != USBFS_GetConfiguration()) { - (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */ + (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status. */ USBFS_CyBtldrCommReset(); + USBFS_started = 0u; } } - else /* Check for configuration changes, has been done by Host */ + else /* Check for configuration changes, has been done by Host. */ { - if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */ + if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET. */ { - if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */ + if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured. */ { USBFS_CyBtldrCommReset(); } @@ -227,15 +214,15 @@ cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */ - /* Wait on next packet */ - while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ - (0u != timeoutMs)) + /* Wait unitl host writes data into OUT endpoint. */ + while ((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ + (0u != timeoutMs)) { CyDelay(USBFS_BTLDR_WAIT_1_MS); timeoutMs--; } - /* OUT EP has completed */ + /* Read data from OUT endpoint if host wrote data into it. */ if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) { *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); @@ -247,10 +234,10 @@ cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 retCode = CYRET_TIMEOUT; } - return(retCode); + return (retCode); } -#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ +#endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c index 7b0bb9b..bc8ad27 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c @@ -1,44 +1,98 @@ -/******************************************************************************* -* File Name: USBFS_cdc.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_cdc.c +* \version 3.10 * -* Description: -* USB CDC class request handler. +* \brief +* This file contains the USB CDC class request handler. * * Related Document: * Universal Serial Bus Class Definitions for Communication Devices Version 1.1 * ******************************************************************************** -* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" - -#if defined(USBFS_ENABLE_CDC_CLASS) - #include "USBFS_cdc.h" #include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_CDC_CLASS) -/*************************************** +/******************************************************************************* * CDC Variables -***************************************/ +*******************************************************************************/ -volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] = +/*PUBLIC*/ +/** Contains the current line coding structure. The host sets it using a + * SET_LINE_CODING request and returns it to the user code using the + * USBFS_GetDTERate(), USBFS_GetCharFormat(), + * USBFS_GetParityType(), and USBFS_GetDataBits() APIs. + * It is an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port + * support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE] = { + /*COM Port 1*/ + { 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ 0x00u, /* 1 Stop bit */ 0x00u, /* None parity */ 0x08u /* 8 data bits */ + }, + /*COM Port 2*/ + { + 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ + 0x00u, /* 1 Stop bit */ + 0x00u, /* None parity */ + 0x08u /* 8 data bits */ + } }; -volatile uint8 USBFS_lineChanged; -volatile uint16 USBFS_lineControlBitmap; -volatile uint8 USBFS_cdc_data_in_ep; -volatile uint8 USBFS_cdc_data_out_ep; + +/**Used as a flag for the USBFS_IsLineChanged() API, to inform it that the + * host has been sent a request to change line coding or control bitmap. It is + * an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port + * support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the current control-signal bitmap. The host sets it using a + * SET_CONTROL_LINE request and returns it to the user code using the + * USBFS_GetLineControl() API. It is an array of 2 elements for COM + * port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, data + * is in 0 element.*/ +volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the 16-bit serial state value that was sent using the + * \ref USBFS_SendSerialState() API. . It is an array of 2 elements + * for COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM + * port, data is in 0 element.*/ +volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data IN endpoint number. It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in CDC APIs + * to send data to the PC. It is an array of 2 elements for COM port 1 and COM + * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data OUT endpoint number. It is initialized after a + * SET_CONFIGURATION request based on user descriptor. It is used in CDC APIs to + * receive data from the PC. It is an array of 2 elements for COM port 1 and COM + * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data IN endpoint number for COMMUNICATION interface. It is + * initialized after a SET_CONFIGURATION request based on a user descriptor. It + * is used in CDC APIs to send data to the PC. It is an array of 2 elements for + * COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, + * data is in 0 element.*/ +volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM]; + +/*PRIVATE*/ + +#define USBFS_CDC_IN_EP (0u) +#define USBFS_CDC_OUT_EP (1u) +#define USBFS_CDC_NOTE_EP (2u) + +#define USBFS_CDC_EP_MASK (0x01u) + +#define USBFS_GET_EP_COM_NUM(cdcComNums, epType) (((cdcComNums) >> (epType)) & USBFS_CDC_EP_MASK) /*************************************** @@ -46,6 +100,21 @@ volatile uint8 USBFS_cdc_data_out_ep; ***************************************/ #if (USBFS_ENABLE_CDC_CLASS_API != 0u) static uint16 USBFS_StrLen(const char8 string[]) ; + static t_USBFS_cdc_notification USBFS_serialStateNotification = + { + + USBFS_SERIAL_STATE_REQUEST_TYPE, /* bRequestType */ + USBFS_SERIAL_STATE, /* bNotification */ + 0u, /* wValue */ + 0u, /* wValueMSB */ + 0u, /* wIndex */ + 0u, /* wIndexMSB */ + USBFS_SERIAL_STATE_LENGTH, /* wLength */ + 0u, /* wLengthMSB */ + 0u, /* wSerialState */ + 0u, /* wSerialStateMSB */ + }; + static uint8 USBFS_activeCom = 0u; #endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */ @@ -60,44 +129,46 @@ volatile uint8 USBFS_cdc_data_out_ep; /******************************************************************************* * Function Name: USBFS_DispatchCDCClassRqst -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine dispatches CDC class requests. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled * -* Global variables: -* USBFS_lineCoding: Contains the current line coding structure. +* \globalvars +* USBFS_linesCoding: Contains the current line coding structure. * It is set by the Host using SET_LINE_CODING request and returned to the * user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), * USBFS_GetParityType(), USBFS_GetDataBits() APIs. -* USBFS_lineControlBitmap: Contains the current control signal +* USBFS_linesControlBitmap: Contains the current control signal * bitmap. It is set by the Host using SET_CONTROL_LINE request and returned * to the user code by the USBFS_GetLineControl() API. -* USBFS_lineChanged: This variable is used as a flag for the +* USBFS_linesChanged: This variable is used as a flag for the * USBFS_IsLineChanged() API, to be aware that Host has been sent request * for changing Line Coding or Control Bitmap. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_DispatchCDCClassRqst(void) { uint8 requestHandled = USBFS_FALSE; + uint8 comPort; - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) + comPort = USBFS_GetInterfaceComPort((uint8)USBFS_wIndexLoReg); + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) { case USBFS_CDC_GET_LINE_CODING: USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; - USBFS_currentTD.pData = USBFS_lineCoding; + USBFS_currentTD.pData = USBFS_linesCoding[comPort]; requestHandled = USBFS_InitControlRead(); break; @@ -105,29 +176,32 @@ uint8 USBFS_DispatchCDCClassRqst(void) /* `#END` */ + default: + /* Do not handle this request unless callback is defined. */ #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK - USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK */ - - default: /* requestHandled is initialized as FALSE by default */ + requestHandled = USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK) */ break; } } - else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ - USBFS_RQST_DIR_H2D) - { /* Control Write */ - switch (CY_GET_REG8(USBFS_bRequest)) + else + { + /* Handle direction from host to device. */ + + switch (USBFS_bRequestReg) { case USBFS_CDC_SET_LINE_CODING: - USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; - USBFS_currentTD.pData = USBFS_lineCoding; - USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED; + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_linesCoding[comPort]; + USBFS_linesChanged[comPort] |= USBFS_LINE_CODING_CHANGED; + requestHandled = USBFS_InitControlWrite(); break; case USBFS_CDC_SET_CONTROL_LINE_STATE: - USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo); - USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED; + USBFS_linesControlBitmap[comPort] = (uint8) USBFS_wValueLoReg; + USBFS_linesChanged[comPort] |= USBFS_LINE_CONTROL_CHANGED; + requestHandled = USBFS_InitNoDataControlTransfer(); break; @@ -135,615 +209,895 @@ uint8 USBFS_DispatchCDCClassRqst(void) /* `#END` */ + default: + /* Do not handle this request unless callback is defined. */ #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK - USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback(); - #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK */ - - default: /* requestHandled is initialized as FALSE by default */ + requestHandled = USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK) */ break; } } - else - { /* requestHandled is initialized as FALSE by default */ - } return(requestHandled); } +/*************************************************************************** +* Function Name: USBFS_GetInterfaceComPort +************************************************************************//** +* \internal +* Internal function which gets number of COM port by specified interface +* number. +* +* \param uint8 interface +* Interface number +* +* \return +* COM port number (0 or 1) or error 0xFF +* +***************************************************************************/ +uint8 USBFS_GetInterfaceComPort(uint8 interface) +{ + uint8 comPort = 0u; + uint8 res = 0xFFu; + uint8 notEp; + + while (comPort < USBFS_MAX_MULTI_COM_NUM) + { + notEp = USBFS_cdcCommInInterruptEp[comPort]; + + if (USBFS_EP[notEp].interface == interface) + { + res = comPort; + comPort = USBFS_MAX_MULTI_COM_NUM; + } + + comPort++; + } + return (res); +} + + /*************************************** * Optional CDC APIs ***************************************/ #if (USBFS_ENABLE_CDC_CLASS_API != 0u) +/*************************************************************************** +* Function Name: USBFS_CDC_Init +************************************************************************//** +* +* This function initializes the CDC interface to be ready to receive data +* from the PC. The API set active communication port to 0 in the case of +* multiple communication port support.This API should be called after the +* device has been started and configured using USBUART_Start() API to +* initialize and start the USBFS component operation. Then call the +* USBUART_GetConfiguration() API to wait until the host has enumerated and +* configured the device. For example: +* +* \snippet /USBFS_sut_02.cydsn/main.c wait for enumeration +* +* \return +* cystatus: +* Return Value Description +* USBFS_SUCCESS CDC interface was initialized correctly +* USBFS_FAILURE CDC interface was not initialized +* +* \globalvars +* USBFS_linesChanged: Initialized to zero. +* USBFS_cdcDataOutEp: Used as an OUT endpoint number. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_CDC_Init(void) +{ + uint8 comPort; + uint8 outEp; + uint8 ret = USBFS_SUCCESS; - /******************************************************************************* - * Function Name: USBFS_CDC_Init - ******************************************************************************** - * - * Summary: - * This function initialize the CDC interface to be ready for the receive data - * from the PC. - * - * Parameters: - * None. - * - * Return: - * None. - * - * Global variables: - * USBFS_lineChanged: Initialized to zero. - * USBFS_cdc_data_out_ep: Used as an OUT endpoint number. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_CDC_Init(void) + USBFS_activeCom = 0u; + USBFS_linesChanged[USBFS_COM_PORT1] = 0u; + USBFS_linesChanged[USBFS_COM_PORT2] = 0u; + + for(comPort = 0u; comPort USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) + outEp = USBFS_cdcDataOutEp[comPort]; + if((0u != outEp) && (USBFS_MAX_EP > outEp)) { - /* Caution: Data will be lost if length is greater than Max Packet Length */ - length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize; - /* Halt CPU in debug mode */ - CYASSERT(0u != 0u); - } - USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length); - } - - - /******************************************************************************* - * Function Name: USBFS_StrLen - ******************************************************************************** - * - * Summary: - * Calculates length of a null terminated string. - * - * Parameters: - * string: pointer to the string. - * - * Return: - * Length of the string - * - *******************************************************************************/ - static uint16 USBFS_StrLen(const char8 string[]) - { - uint16 len = 0u; - - while (string[len] != (char8)0) - { - len++; + USBFS_EnableOutEP(outEp); } - return (len); } - - /******************************************************************************* - * Function Name: USBFS_PutString - ******************************************************************************** - * - * Summary: - * This function sends a null terminated string to the PC. This function will - * block if there is not enough memory to place the whole string. It will block - * until the entire string has been written to the transmit buffer. - * The USBUART_CDCIsReady() function should be called before sending data with - * a new call to USBFS_PutString(), to be sure that the previous data - * has finished sending. - * - * Parameters: - * string: pointer to the string to be sent to the PC. - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_PutString(const char8 string[]) + /* COM Port 1 should be correct to proceed. */ + if ((0u == USBFS_cdcDataInEp[USBFS_COM_PORT1]) \ + || (0u == USBFS_cdcDataOutEp[USBFS_COM_PORT1]) \ + || (0u == USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1]) + || (USBFS_cdcDataInEp[USBFS_COM_PORT1] >= USBFS_MAX_EP) + || (USBFS_cdcDataOutEp[USBFS_COM_PORT1] >= USBFS_MAX_EP) + || (USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)) { - uint16 strLength; - uint16 sendLength; - uint16 bufIndex = 0u; + ret = USBFS_FAILURE; + } - /* Get length of the null terminated string */ - strLength = USBFS_StrLen(string); - do + return (ret); +} + + +/******************************************************************************* +* Function Name: USBFS_PutData +****************************************************************************//** +* +* This function sends a specified number of bytes from the location specified +* by a pointer to the PC. The USBFS_CDCIsReady() function should be +* called before sending new data, to be sure that the previous data has +* finished sending. +* If the last sent packet is less than maximum packet size the USB transfer +* of this short packet will identify the end of the segment. If the last sent +* packet is exactly maximum packet size, it shall be followed by a zero-length +* packet (which is a short packet) to assure the end of segment is properly +* identified. To send zero-length packet, use USBFS_PutData() API +* with length parameter set to zero. +* +* \param pData: pointer to the buffer containing data to be sent. +* \param length: Specifies the number of bytes to send from the pData +* buffer. Maximum length will be limited by the maximum packet +* size for the endpoint. Data will be lost if length is greater than Max +* Packet Size. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_PutData(const uint8* pData, uint16 length) +{ + uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom]; + + /* Limit length to maximum packet size for endpoint. */ + if (length > USBFS_EP[epNumber].bufferSize) + { + /* Caution: Data will be lost if length is greater than Max Packet Size. */ + length = USBFS_EP[epNumber].bufferSize; + + /* Halt CPU in debug mode */ + CYASSERT(0u != 0u); + } + + USBFS_LoadInEP(epNumber, pData, length); +} + + +/******************************************************************************* +* Function Name: USBFS_StrLen +****************************************************************************//** +* +* Calculates length of a null terminated string. +* +* \param string: pointer to the string. +* +* \return +* Length of the string +* +*******************************************************************************/ +static uint16 USBFS_StrLen(const char8 string[]) +{ + uint16 len = 0u; + + while (string[len] != (char8)0) + { + len++; + } + + return ((uint16) len); +} + + +/*************************************************************************** +* Function Name: USBFS_PutString +************************************************************************//** +* +* This function sends a null terminated string to the PC. This function will +* block if there is not enough memory to place the whole string. It will block +* until the entire string has been written to the transmit buffer. +* The USBFS_CDCIsReady() function should be called before +* sending data with a new call to USBFS_PutString(), to be sure +* that the previous data has finished sending. This function sends +* zero-length packet automatically, if the length of the last packet, sent +* by this API, is equal to Max Packet Size +* +* \param string: pointer to the string to be sent to the PC. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +***************************************************************************/ +void USBFS_PutString(const char8 string[]) +{ + uint16 strLength; + uint16 sendLength; + uint16 bufIndex = 0u; + + uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom]; + + /* Get length string length (it is terminated with zero). */ + strLength = USBFS_StrLen(string); + + do + { + /* Limit length to maximum packet size of endpoint. */ + sendLength = (strLength > USBFS_EP[epNumber].bufferSize) ? + USBFS_EP[epNumber].bufferSize : strLength; + + /* Load IN endpoint and expose it to host. */ + USBFS_LoadInEP(epNumber, (const uint8 *)&string[bufIndex], sendLength); + strLength -= sendLength; + + /* If more data are present to send or full packet was sent */ + if ((strLength > 0u) || (sendLength == USBFS_EP[epNumber].bufferSize)) { - /* Limits length to maximum packet size for the EP */ - sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ? - USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength; - /* Enable IN transfer */ - USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength); - strLength -= sendLength; + bufIndex += sendLength; - /* If more data are present to send or full packet was sent */ - if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize)) + /* Wait until host read data from IN endpoint buffer. */ + while (USBFS_IN_BUFFER_FULL == USBFS_EP[epNumber].apiEpState) { - bufIndex += sendLength; - /* Wait for the Host to read it. */ - while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState == - USBFS_IN_BUFFER_FULL) - { - ; - } - /* If the last sent packet is exactly maximum packet size, - * it shall be followed by a zero-length packet to assure the - * end of segment is properly identified by the terminal. - */ - if(strLength == 0u) - { - USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u); - } } - }while(strLength > 0u); + + /* If last packet is exactly maximum packet size, it shall be followed + * by a zero-length packet to assure the end of segment is properly + * identified by the terminal. + */ + if (0u == strLength) + { + USBFS_LoadInEP(epNumber, NULL, 0u); + } + } + } + while (strLength > 0u); +} + + +/*************************************************************************** +* Function Name: USBFS_PutChar +************************************************************************//** +* +* This function writes a single character to the PC at a time. This is an +* inefficient way to send large amounts of data. +* +* \param txDataByte: Character to be sent to the PC. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +***************************************************************************/ +void USBFS_PutChar(char8 txDataByte) +{ + uint8 dataByte; + dataByte = (uint8) txDataByte; + + USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], &dataByte, 1u); +} + + +/******************************************************************************* +* Function Name: USBFS_PutCRLF +****************************************************************************//** +* +* This function sends a carriage return (0x0D) and line feed (0x0A) to the +* PC. This APIis provided to mimic API provided by our other UART components +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_PutCRLF(void) +{ + const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; + + USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], (const uint8 *)txData, 2u); +} + + +/******************************************************************************* +* Function Name: USBFS_GetCount +****************************************************************************//** +* +* This function returns the number of bytes that were received from the PC. +* The returned length value should be passed to USBFS_GetData() as +* a parameter to read all received data. If all of the received data is not +* read at one time by the USBFS_GetData() API, the unread data will +* be lost. +* +* \return +* Returns the number of received bytes. The maximum amount of received data at +* a time is limited by the maximum packet size for the endpoint. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +*******************************************************************************/ +uint16 USBFS_GetCount(void) +{ + uint16 bytesCount; + + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + if (USBFS_OUT_BUFFER_FULL == USBFS_EP[epNumber].apiEpState) + { + bytesCount = USBFS_GetEPCount(epNumber); + } + else + { + bytesCount = 0u; } + return (bytesCount); +} - /******************************************************************************* - * Function Name: USBFS_PutChar - ******************************************************************************** - * - * Summary: - * Writes a single character to the PC. - * - * Parameters: - * txDataByte: Character to be sent to the PC. - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_PutChar(char8 txDataByte) + +/******************************************************************************* +* Function Name: USBFS_DataIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the component received data or +* received zero-length packet. The USBFS_GetAll() or +* USBFS_GetData() API should be called to read data from the buffer +* and reinitialize the OUT endpoint even when a zero-length packet is +* received. These APIs will return zero value when zero-length packet is +* received. +* +* \return +* If the OUT packet is received, this function returns a non-zero value. +* Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_DataIsReady(void) +{ + return (USBFS_GetEPState(USBFS_cdcDataOutEp[USBFS_activeCom])); +} + + +/******************************************************************************* +* Function Name: USBFS_CDCIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the component is ready to send more +* data to the PC; otherwise, it returns zero. The function should be called +* before sending new data when using any of the following APIs: +* USBFS_PutData(),USBFS_PutString(), +* USBFS_PutChar or USBFS_PutCRLF(), +* to be sure that the previous data has finished sending. +* +* \return +* If the buffer can accept new data, this function returns a non-zero value. +* Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataInEp: CDC IN endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_CDCIsReady(void) +{ + return (USBFS_GetEPState(USBFS_cdcDataInEp[USBFS_activeCom])); +} + + +/*************************************************************************** +* Function Name: USBFS_GetData +************************************************************************//** +* +* This function gets a specified number of bytes from the input buffer and +* places them in a data array specified by the passed pointer. +* The USBFS_DataIsReady() API should be called first, to be sure +* that data is received from the host. If all received data will not be read at +* once, the unread data will be lost. The USBFS_GetData() API should +* be called to get the number of bytes that were received. +* +* \param pData: Pointer to the data array where data will be placed. +* \param Length: Number of bytes to read into the data array from the RX buffer. +* Maximum length is limited by the the number of received bytes +* or 64 bytes. +* +* \return +* Number of bytes which function moves from endpoint RAM into the +* data array. The function moves fewer than the requested number +* of bytes if the host sends fewer bytes than requested or sends +* zero-length packet. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +* \reentrant +* No. +* +***************************************************************************/ +uint16 USBFS_GetData(uint8* pData, uint16 length) +{ + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + /* Read data from OUT endpoint buffer. */ + length = USBFS_ReadOutEP(epNumber, pData, length); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) { - uint8 dataByte; - dataByte = (uint8)txDataByte; - - USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u); } + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ - /******************************************************************************* - * Function Name: USBFS_PutCRLF - ******************************************************************************** - * - * Summary: - * Sends a carriage return (0x0D) and line feed (0x0A) to the PC - * - * Parameters: - * None. - * - * Return: - * None. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending - * data. - * - * Reentrant: - * No. - * - *******************************************************************************/ - void USBFS_PutCRLF(void) + return (length); +} + + +/******************************************************************************* +* Function Name: USBFS_GetAll +****************************************************************************//** +* +* This function gets all bytes of received data from the input buffer and +* places them into a specified data array. The +* USBFS_DataIsReady() API should be called first, to be sure +* that data is received from the host. +* +* \param pData: Pointer to the data array where data will be placed. +* +* \return +* Number of bytes received. The maximum amount of the received at a time +* data is 64 bytes. +* +* \globalvars +* - \ref USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* - \ref USBFS_EP[].bufferSize: EP max packet size is used as a +* length to read all data from the EP buffer. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_GetAll(uint8* pData) +{ + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + uint16 dataLength; + + /* Read data from OUT endpoint buffer. */ + dataLength = USBFS_ReadOutEP(epNumber, pData, USBFS_EP[epNumber].bufferSize); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) { - const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; - - USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u); } + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ - /******************************************************************************* - * Function Name: USBFS_GetCount - ******************************************************************************** - * - * Summary: - * This function returns the number of bytes that were received from the PC. - * The returned length value should be passed to USBFS_GetData() as - * a parameter to read all received data. If all of the received data is not - * read at one time by the USBFS_GetData() API, the unread data will - * be lost. - * - * Parameters: - * None. - * - * Return: - * Returns the number of received bytes. The maximum amount of received data at - * a time is limited by the maximum packet size for the endpoint. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - *******************************************************************************/ - uint16 USBFS_GetCount(void) + return (dataLength); +} + + +/*************************************************************************** +* Function Name: USBFS_GetChar +************************************************************************//** +* +* This function reads one byte of received data from the buffer. If more than +* one byte has been received from the host, the rest of the data will be lost. +* +* \return +* Received one character. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +* \reentrant +* No. +* +***************************************************************************/ +uint8 USBFS_GetChar(void) +{ + uint8 rxData; + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + (void) USBFS_ReadOutEP(epNumber, &rxData, 1u); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) { - uint16 bytesCount; + } - if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL) + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (rxData); +} + + +/******************************************************************************* +* Function Name: USBFS_IsLineChanged +****************************************************************************//** +* +* This function returns clear on read status of the line. It returns not zero +* value when the host sends updated coding or control information to the +* device. The USBFS_GetDTERate(), USBFS_GetCharFormat() +* or USBFS_GetParityType() or USBFS_GetDataBits() API +* should be called to read data coding information. +* The USBFS_GetLineControl() API should be called to read line +* control information. +* +* \return +* If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it +* returns a non-zero value. Otherwise, it returns zero. +* Return Value | Description +* -----------------------------|-------------------------- +* USBUART_LINE_CODING_CHANGED | Line coding changed +* USBUART_LINE_CONTROL_CHANGED | Line control changed +* +* \globalvars +* - \ref USBFS_transferState: it is checked to be sure then OUT +* data phase has been complete, and data written to the lineCoding or +* Control Bitmap buffer. +* - \ref USBFS_linesChanged: used as a flag to be aware that +* Host has been sent request for changing Line Coding or Control Bitmap. +* +*******************************************************************************/ +uint8 USBFS_IsLineChanged(void) +{ + uint8 state = 0u; + + /* transferState is checked to be sure then OUT data phase has been complete */ + if (USBFS_transferState == USBFS_TRANS_STATE_IDLE) + { + if (USBFS_linesChanged[USBFS_activeCom] != 0u) { - bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep); + state = USBFS_linesChanged[USBFS_activeCom]; + USBFS_linesChanged[USBFS_activeCom] = 0u; + } + } + + return (state); +} + + +/*************************************************************************** +* Function Name: USBFS_GetDTERate +************************************************************************//** +* +* This function returns the data terminal rate set for this port in bits +* per second. +* +* \return +* Returns a uint32 value of the data rate in bits per second. +* +* \globalvars +* USBFS_linesCoding: First four bytes converted to uint32 +* depend on compiler, and returned as a data rate. +* +*******************************************************************************/ +uint32 USBFS_GetDTERate(void) +{ + uint32 rate; + + rate = USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 3u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 2u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 1u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE]; + + return (rate); +} + + +/******************************************************************************* +* Function Name: USBFS_GetCharFormat +****************************************************************************//** +* +* Returns the number of stop bits. +* +* \return +* Returns the number of stop bits. +* Return |Value Description +* ---------------------|------------------- +* USBUART_1_STOPBIT | 1 stop bit +* USBUART_1_5_STOPBITS | 1,5 stop bits +* USBUART_2_STOPBITS | 2 stop bits +* +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetCharFormat(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_STOP_BITS]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetParityType +****************************************************************************//** +* +* This function returns the parity type for the CDC port. +* +* \return +* Returns the parity type. +* Return | Value Description +* ----------------------|------------------- +* USBUART_PARITY_NONE | 1 stop bit +* USBUART_PARITY_ODD | 1,5 stop bits +* USBUART_PARITY_EVEN | 2 stop bits +* USBUART_PARITY_MARK | Mark +* USBUART_PARITY_SPACE | Space +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetParityType(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_PARITY]); +} + + +/*************************************************************************** +* Function Name: USBFS_GetDataBits +************************************************************************//** +* +* This function returns the number of data bits for the CDC port. +* +* \return +* Returns the number of data bits. +* The number of data bits can be 5, 6, 7, 8 or 16. +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetDataBits(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_DATA_BITS]); +} + + +/*************************************************************************** +* Function Name: USBFS_GetLineControl +************************************************************************//** +* +* This function returns Line control bitmap that the host sends to the +* device. +* +* \return +* Returns Line control bitmap. +* Return |Value Notes +* -------------------------|----------------------------------------------- +* USBUART_LINE_CONTROL_DTR |Indicates that a DTR signal is present. This signal corresponds to V.24 signal 108/2 and RS232 signal DTR. +* USBUART_LINE_CONTROL_RTS |Carrier control for half-duplex modems. This signal corresponds to V.24 signal 105 and RS232 signal RTS. +* RESERVED |The rest of the bits are reserved. +* +* *Note* Some terminal emulation programs do not properly handle these +* control signals. They update information about DTR and RTS state only +* when the RTS signal changes the state. +* +* \globalvars +* USBFS_linesControlBitmap: used to get a parameter. +* +*******************************************************************************/ +uint16 USBFS_GetLineControl(void) +{ + return (USBFS_linesControlBitmap[USBFS_activeCom]); +} + + +/******************************************************************************* +* Function Name: USBFS_SendSerialState +****************************************************************************//** +* +* Sends the serial state notification to the host using the interrupt +* endpoint for the COM port selected using the API SetComPort().The +* USBFS_NotificationIsReady() API must be called to check if the +* Component is ready to send more serial state to the host. The API will +* not send the notification data if the interrupt endpoint Max Packet Size +* is less than the required 10 bytes. +* +* \param uint16 serialState +* 16-bit value that will be sent from the device to the +* host as SERIAL_STATE notification using the IN interrupt endpoint. Refer +* to revision 1.2 of the CDC PSTN Subclass specification for bit field +* definitions of the 16-bit serial state value. +* +*******************************************************************************/ +void USBFS_SendSerialState (uint16 serialState) +{ + uint8 epNumber = USBFS_cdcCommInInterruptEp[USBFS_activeCom]; + + if(USBFS_SERIAL_STATE_SIZE <= USBFS_EP[epNumber].bufferSize) + { + /* Save current SERIAL_STATE bitmap. */ + USBFS_serialStateBitmap[USBFS_activeCom] = serialState; + + /* Add interface number */ + USBFS_serialStateNotification.wIndex = USBFS_EP[epNumber].interface; + + /*Form SERIAL_STATE data*/ + USBFS_serialStateNotification.wSerialState = LO8(USBFS_serialStateBitmap[USBFS_activeCom]); + USBFS_serialStateNotification.wSerialStateMSB = HI8(USBFS_serialStateBitmap[USBFS_activeCom]); + + USBFS_LoadInEP(epNumber, (uint8 *) &USBFS_serialStateNotification, sizeof(USBFS_serialStateNotification)); + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetSerialState +****************************************************************************//** +* +* This function returns the current serial state value for the COM port +* selected using the API SetComPort(). +* +* \return +* 16-bit serial state value. Refer to revision 1.2 of the CDC PSTN Subclass +* specification for bit field definitions of the 16-bit serial state value. +* +*******************************************************************************/ +uint16 USBFS_GetSerialState(void) +{ + return USBFS_serialStateBitmap[USBFS_activeCom]; +} + + +/******************************************************************************* +* Function Name: USBFS_NotificationIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the Component is ready to send +* more notifications to the host; otherwise, it returns zero. The function +* should be called before sending new notifications when using +* USBFS_SendSerialState() to ensure that any previous +* notification data has been already sent to the host. +* +* \return +* If the buffer can accept new data(endpoint buffer not full), this +* function returns a non-zero value. Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataInEp: CDC IN endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_NotificationIsReady(void) +{ + return (USBFS_EP[USBFS_cdcCommInInterruptEp[USBFS_activeCom]].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_SetComPort +****************************************************************************//** +* +* This function allows the user to select from one of the two COM ports +* they wish to address in the instance of having multiple COM ports +* instantiated though the use of a composite device. Once set, all future +* function calls related to the USBUART will be affected. This addressed +* COM port can be changed during run time. +* +* \param comNumber +* Contains the COM interface the user wishes to address. Value can either +* be 0 or 1 since a maximum of only 2 COM ports can be supported. Note that +* this COM port number is not the COM port number assigned on the PC side +* for the UART communication. If a value greater than 1 is passed, the +* function returns without performing any action. +* +*******************************************************************************/ +void USBFS_SetComPort(uint8 comNumber) +{ + if ((USBFS_activeCom != comNumber) && \ + (comNumber < USBFS_MAX_MULTI_COM_NUM )) + { + USBFS_activeCom = comNumber; + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetComPort +****************************************************************************//** +* +* This function returns the current selected COM port that the user is +* currently addressing in the instance of having multiple COM ports +* instantiated though the use of a composite device. +* +* \return +* Returns the currently selected COM port. Value can either be 0 or 1 since +* a maximum of only 2 COM ports can be supported. . Note that this COM port +* number is not the COM port number assigned on the PC side for the UART +* communication. +* +*******************************************************************************/ +uint8 USBFS_GetComPort(void) +{ + return (USBFS_activeCom); +} + + +#endif /* (USBFS_ENABLE_CDC_CLASS_API) */ + + +/*************************************************************************** +* Function Name: USBFS_Cdc_EpInit +************************************************************************//** +* +* \internal +* This routine decide type of endpoint (IN, OUT, Notification) and same to +* appropriate global variables according to COM port number. +* USBFS_cdcDataInEp[], USBFS_cdcCommInInterruptEp[], +* USBFS_cdcDataOutEp[] +* +* \param pEP: Pointer to structure with current EP description. +* \param epNum: EP number +* \param cdcComNums: Bit array of current COM ports for CDC IN, OUT, +* and notification EPs(0 - COM port 1, 1- COM port 2) +* +* \return +* Updated cdcComNums +* +* \reentrant +* No. +* +***************************************************************************/ +uint8 USBFS_Cdc_EpInit(const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) +{ + uint8 epType; + + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + if (epType != USBFS_EP_TYPE_INT) + { + USBFS_cdcDataInEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_IN_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_IN_EP); } else { - bytesCount = 0u; + + USBFS_cdcCommInInterruptEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_NOTE_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_NOTE_EP); } - - return(bytesCount); } - - - /******************************************************************************* - * Function Name: USBFS_DataIsReady - ******************************************************************************** - * - * Summary: - * Returns a nonzero value if the component received data or received - * zero-length packet. The USBFS_GetAll() or - * USBFS_GetData() API should be called to read data from the buffer - * and re-init OUT endpoint even when zero-length packet received. - * - * Parameters: - * None. - * - * Return: - * If the OUT packet received this function returns a nonzero value. - * Otherwise zero is returned. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - *******************************************************************************/ - uint8 USBFS_DataIsReady(void) + else { - return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState); - } - - - /******************************************************************************* - * Function Name: USBFS_CDCIsReady - ******************************************************************************** - * - * Summary: - * This function returns a nonzero value if the component is ready to send more - * data to the PC; otherwise, it returns zero. The function should be called - * before sending new data when using any of the following APIs: - * USBFS_PutData(),USBFS_PutString(), - * USBFS_PutChar or USBFS_PutCRLF(), - * to be sure that the previous data has finished sending. - * - * Parameters: - * None. - * - * Return: - * If the buffer can accept new data, this function returns a nonzero value. - * Otherwise, it returns zero. - * - * Global variables: - * USBFS_cdc_data_in_ep: CDC IN endpoint number used. - * - *******************************************************************************/ - uint8 USBFS_CDCIsReady(void) - { - return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState); - } - - - /******************************************************************************* - * Function Name: USBFS_GetData - ******************************************************************************** - * - * Summary: - * This function gets a specified number of bytes from the input buffer and - * places them in a data array specified by the passed pointer. - * The USBFS_DataIsReady() API should be called first, to be sure - * that data is received from the host. If all received data will not be read at - * once, the unread data will be lost. The USBFS_GetData() API should - * be called to get the number of bytes that were received. - * - * Parameters: - * pData: Pointer to the data array where data will be placed. - * Length: Number of bytes to read into the data array from the RX buffer. - * Maximum length is limited by the the number of received bytes. - * - * Return: - * Number of bytes received. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - * Reentrant: - * No. - * - *******************************************************************************/ - uint16 USBFS_GetData(uint8* pData, uint16 length) - { - return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length)); - } - - - /******************************************************************************* - * Function Name: USBFS_GetAll - ******************************************************************************** - * - * Summary: - * Gets all bytes of received data from the input buffer and places it into a - * specified data array. USBFS_DataIsReady() API should be called - * before, to be sure that data is received from the Host. - * - * Parameters: - * pData: Pointer to the data array where data will be placed. - * - * Return: - * Number of bytes received. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * USBFS_EP[].bufferSize: EP max packet size is used as a length - * to read all data from the EP buffer. - * - * Reentrant: - * No. - * - *******************************************************************************/ - uint16 USBFS_GetAll(uint8* pData) - { - return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, - USBFS_EP[USBFS_cdc_data_out_ep].bufferSize)); - } - - - /******************************************************************************* - * Function Name: USBFS_GetChar - ******************************************************************************** - * - * Summary: - * This function reads one byte of received data from the buffer. If more than - * one byte has been received from the host, the rest of the data will be lost. - * - * Parameters: - * None. - * - * Return: - * Received one character. - * - * Global variables: - * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. - * - * Reentrant: - * No. - * - *******************************************************************************/ - uint8 USBFS_GetChar(void) - { - uint8 rxData; - - (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u); - - return(rxData); - } - - /******************************************************************************* - * Function Name: USBFS_IsLineChanged - ******************************************************************************** - * - * Summary: - * This function returns clear on read status of the line. It returns not zero - * value when the host sends updated coding or control information to the - * device. The USBFS_GetDTERate(), USBFS_GetCharFormat() - * or USBFS_GetParityType() or USBFS_GetDataBits() API - * should be called to read data coding information. - * The USBFS_GetLineControl() API should be called to read line - * control information. - * - * Parameters: - * None. - * - * Return: - * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it - * returns a nonzero value. Otherwise, it returns zero. - * - * Global variables: - * USBFS_transferState: it is checked to be sure then OUT data - * phase has been complete, and data written to the lineCoding or Control - * Bitmap buffer. - * USBFS_lineChanged: used as a flag to be aware that Host has been - * sent request for changing Line Coding or Control Bitmap. - * - *******************************************************************************/ - uint8 USBFS_IsLineChanged(void) - { - uint8 state = 0u; - - /* transferState is checked to be sure then OUT data phase has been complete */ - if(USBFS_transferState == USBFS_TRANS_STATE_IDLE) + if (epType != USBFS_EP_TYPE_INT) { - if(USBFS_lineChanged != 0u) - { - state = USBFS_lineChanged; - USBFS_lineChanged = 0u; - } + USBFS_cdcDataOutEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_OUT_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_OUT_EP); } - - return(state); } - - - /******************************************************************************* - * Function Name: USBFS_GetDTERate - ******************************************************************************** - * - * Summary: - * Returns the data terminal rate set for this port in bits per second. - * - * Parameters: - * None. - * - * Return: - * Returns a uint32 value of the data rate in bits per second. - * - * Global variables: - * USBFS_lineCoding: First four bytes converted to uint32 - * depend on compiler, and returned as a data rate. - * - *******************************************************************************/ - uint32 USBFS_GetDTERate(void) - { - uint32 rate; - - rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u]; - rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u]; - rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u]; - rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE]; - - return(rate); - } - - - /******************************************************************************* - * Function Name: USBFS_GetCharFormat - ******************************************************************************** - * - * Summary: - * Returns the number of stop bits. - * - * Parameters: - * None. - * - * Return: - * Returns the number of stop bits. - * - * Global variables: - * USBFS_lineCoding: used to get a parameter. - * - *******************************************************************************/ - uint8 USBFS_GetCharFormat(void) - { - return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]); - } - - - /******************************************************************************* - * Function Name: USBFS_GetParityType - ******************************************************************************** - * - * Summary: - * Returns the parity type for the CDC port. - * - * Parameters: - * None. - * - * Return: - * Returns the parity type. - * - * Global variables: - * USBFS_lineCoding: used to get a parameter. - * - *******************************************************************************/ - uint8 USBFS_GetParityType(void) - { - return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]); - } - - - /******************************************************************************* - * Function Name: USBFS_GetDataBits - ******************************************************************************** - * - * Summary: - * Returns the number of data bits for the CDC port. - * - * Parameters: - * None. - * - * Return: - * Returns the number of data bits. - * The number of data bits can be 5, 6, 7, 8 or 16. - * - * Global variables: - * USBFS_lineCoding: used to get a parameter. - * - *******************************************************************************/ - uint8 USBFS_GetDataBits(void) - { - return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]); - } - - - /******************************************************************************* - * Function Name: USBFS_GetLineControl - ******************************************************************************** - * - * Summary: - * Returns Line control bitmap. - * - * Parameters: - * None. - * - * Return: - * Returns Line control bitmap. - * - * Global variables: - * USBFS_lineControlBitmap: used to get a parameter. - * - *******************************************************************************/ - uint16 USBFS_GetLineControl(void) - { - return(USBFS_lineControlBitmap); - } - -#endif /* USBFS_ENABLE_CDC_CLASS_API*/ + return (cdcComNums); +} /******************************************************************************* @@ -754,7 +1108,7 @@ uint8 USBFS_DispatchCDCClassRqst(void) /* `#END` */ -#endif /* USBFS_ENABLE_CDC_CLASS*/ +#endif /* (USBFS_ENABLE_CDC_CLASS) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h old mode 100644 new mode 100755 index 11c94d0..2aabd0b --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h @@ -1,16 +1,17 @@ -/******************************************************************************* -* File Name: USBFS_cdc.h -* Version 2.80 +/***************************************************************************//** +* \file USBFS_cdc.h +* \version 3.10 * -* Description: -* Header File for the USBFS component. -* Contains CDC class prototypes and constant values. +* \brief +* This file provides function prototypes and constants for the USBFS component +* CDC class. * * Related Document: * Universal Serial Bus Class Definitions for Communication Devices Version 1.1 * ******************************************************************************** -* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,43 +20,55 @@ #if !defined(CY_USBFS_USBFS_cdc_H) #define CY_USBFS_USBFS_cdc_H -#include "cytypes.h" +#include "USBFS.h" -/*************************************** +/******************************************************************************* * Prototypes of the USBFS_cdc API. -***************************************/ - +*******************************************************************************/ +/** +* \addtogroup group_cdc +* @{ +*/ #if (USBFS_ENABLE_CDC_CLASS_API != 0u) - void USBFS_CDC_Init(void) ; + uint8 USBFS_CDC_Init(void) ; void USBFS_PutData(const uint8* pData, uint16 length) ; - void USBFS_PutString(const char8 string[]) ; + void USBFS_PutString(const char8 string[]) ; void USBFS_PutChar(char8 txDataByte) ; - void USBFS_PutCRLF(void) ; - uint16 USBFS_GetCount(void) ; - uint8 USBFS_CDCIsReady(void) ; - uint8 USBFS_DataIsReady(void) ; - uint16 USBFS_GetData(uint8* pData, uint16 length) ; - uint16 USBFS_GetAll(uint8* pData) ; - uint8 USBFS_GetChar(void) ; - uint8 USBFS_IsLineChanged(void) ; - uint32 USBFS_GetDTERate(void) ; - uint8 USBFS_GetCharFormat(void) ; - uint8 USBFS_GetParityType(void) ; - uint8 USBFS_GetDataBits(void) ; - uint16 USBFS_GetLineControl(void) ; -#endif /* USBFS_ENABLE_CDC_CLASS_API */ + void USBFS_PutCRLF(void) ; + uint16 USBFS_GetCount(void) ; + uint8 USBFS_CDCIsReady(void) ; + uint8 USBFS_DataIsReady(void) ; + uint16 USBFS_GetData(uint8* pData, uint16 length) ; + uint16 USBFS_GetAll(uint8* pData) ; + uint8 USBFS_GetChar(void) ; + uint8 USBFS_IsLineChanged(void) ; + uint32 USBFS_GetDTERate(void) ; + uint8 USBFS_GetCharFormat(void) ; + uint8 USBFS_GetParityType(void) ; + uint8 USBFS_GetDataBits(void) ; + uint16 USBFS_GetLineControl(void) ; + void USBFS_SendSerialState (uint16 serialState) ; + uint16 USBFS_GetSerialState (void) ; + void USBFS_SetComPort (uint8 comNumber) ; + uint8 USBFS_GetComPort (void) ; + uint8 USBFS_NotificationIsReady(void) ; +#endif /* (USBFS_ENABLE_CDC_CLASS_API) */ +/** @} cdc */ -/*************************************** +/******************************************************************************* * Constants for USBFS_cdc API. -***************************************/ +*******************************************************************************/ /* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ #define USBFS_CDC_SET_LINE_CODING (0x20u) #define USBFS_CDC_GET_LINE_CODING (0x21u) #define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) +/*PSTN Subclass Specific Notifications (CDC ver 1.2 Table 30)*/ +#define USBFS_SERIAL_STATE (0x20u) + #define USBFS_LINE_CODING_CHANGED (0x01u) #define USBFS_LINE_CONTROL_CHANGED (0x02u) @@ -78,18 +91,49 @@ #define USBFS_LINE_CONTROL_DTR (0x01u) #define USBFS_LINE_CONTROL_RTS (0x02u) +#define USBFS_MAX_MULTI_COM_NUM (2u) -/*************************************** +#define USBFS_COM_PORT1 (0u) +#define USBFS_COM_PORT2 (1u) + +#define USBFS_SUCCESS (0u) +#define USBFS_FAILURE (1u) + +#define USBFS_SERIAL_STATE_SIZE (10u) + +/* SerialState constants*/ +#define USBFS_SERIAL_STATE_REQUEST_TYPE (0xA1u) +#define USBFS_SERIAL_STATE_LENGTH (0x2u) + +/******************************************************************************* * External data references -***************************************/ +*******************************************************************************/ +/** +* \addtogroup group_cdc +* @{ +*/ +extern volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE]; +extern volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM]; +/** @} cdc */ -extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; -extern volatile uint8 USBFS_lineChanged; -extern volatile uint16 USBFS_lineControlBitmap; -extern volatile uint8 USBFS_cdc_data_in_ep; -extern volatile uint8 USBFS_cdc_data_out_ep; +/******************************************************************************* +* The following code is DEPRECATED and +* must not be used. +*******************************************************************************/ -#endif /* CY_USBFS_USBFS_cdc_H */ + +#define USBFS_lineCoding USBFS_linesCoding[0] +#define USBFS_lineChanged USBFS_linesChanged[0] +#define USBFS_lineControlBitmap USBFS_linesControlBitmap[0] +#define USBFS_cdc_data_in_ep USBFS_cdcDataInEp[0] +#define USBFS_cdc_data_out_ep USBFS_cdcDataOutEp[0] + +#endif /* (CY_USBFS_USBFS_cdc_H) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf old mode 100644 new mode 100755 index 9bbefb9..dc7d5f1 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf @@ -1,12 +1,12 @@ ;****************************************************************************** ; File Name: USBFS_cdc.inf -; Version 2.80 +; Version 3.10 ; ; Description: ; Windows USB CDC setup file for USBUART Device. ; ;****************************************************************************** -; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved. +; Copyright 2007-2016, Cypress Semiconductor Corporation. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -32,12 +32,27 @@ DefaultDestDir=12 [DeviceList.NTx86] %DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04 [DeviceList.NTia64] %DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04 [DeviceList.NTamd64] %DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04 ;------------------------------------------------------------------------------ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c index 7ce5887..94b0b35 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c @@ -1,26 +1,22 @@ -/******************************************************************************* -* File Name: USBFS_cls.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_cls.c +* \version 3.10 * -* Description: -* USB Class request handler. -* -* Note: +* \brief +* This file contains the USB Class request handler. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" - -#if(USBFS_EXTERN_CLS == USBFS_FALSE) - #include "USBFS_pvt.h" +#if(USBFS_EXTERN_CLS == USBFS_FALSE) /*************************************** * User Implemented Class Driver Declarations. @@ -32,69 +28,110 @@ /******************************************************************************* * Function Name: USBFS_DispatchClassRqst -******************************************************************************** -* Summary: +****************************************************************************//** * This routine dispatches class specific requests depend on interface class. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_DispatchClassRqst(void) { - uint8 requestHandled = USBFS_FALSE; - uint8 interfaceNumber = 0u; + uint8 requestHandled; + uint8 interfaceNumber; - switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + /* Get interface to which request is intended. */ + switch (USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK) { - case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */ - interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ + case USBFS_RQST_RCPT_IFC: + /* Class-specific request directed to interface: wIndexLoReg + * contains interface number. + */ + interfaceNumber = (uint8) USBFS_wIndexLoReg; break; - case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */ - /* Find related interface to the endpoint, wIndexLo contain EP number */ - interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & - USBFS_DIR_UNUSED].interface; + + case USBFS_RQST_RCPT_EP: + /* Class-specific request directed to endpoint: wIndexLoReg contains + * endpoint number. Find interface related to endpoint, + */ + interfaceNumber = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].interface; break; - default: /* RequestHandled is initialized as FALSE by default */ + + default: + /* Default interface is zero. */ + interfaceNumber = 0u; break; } - /* Handle Class request depend on interface type */ - switch(USBFS_interfaceClass[interfaceNumber]) + +#if (defined(USBFS_ENABLE_HID_CLASS) ||\ + defined(USBFS_ENABLE_AUDIO_CLASS) ||\ + defined(USBFS_ENABLE_CDC_CLASS) ||\ + USBFS_ENABLE_MSC_CLASS) + + /* Handle class request depends on interface type. */ + switch (USBFS_interfaceClass[interfaceNumber]) { + #if defined(USBFS_ENABLE_HID_CLASS) case USBFS_CLASS_HID: - #if defined(USBFS_ENABLE_HID_CLASS) - requestHandled = USBFS_DispatchHIDClassRqst(); - #endif /* USBFS_ENABLE_HID_CLASS */ + requestHandled = USBFS_DispatchHIDClassRqst(); break; + #endif /* (USBFS_ENABLE_HID_CLASS) */ + + #if defined(USBFS_ENABLE_AUDIO_CLASS) case USBFS_CLASS_AUDIO: - #if defined(USBFS_ENABLE_AUDIO_CLASS) - requestHandled = USBFS_DispatchAUDIOClassRqst(); - #endif /* USBFS_CLASS_AUDIO */ + requestHandled = USBFS_DispatchAUDIOClassRqst(); break; + #endif /* (USBFS_CLASS_AUDIO) */ + + #if defined(USBFS_ENABLE_CDC_CLASS) case USBFS_CLASS_CDC: - #if defined(USBFS_ENABLE_CDC_CLASS) - requestHandled = USBFS_DispatchCDCClassRqst(); - #endif /* USBFS_ENABLE_CDC_CLASS */ + requestHandled = USBFS_DispatchCDCClassRqst(); break; - default: /* requestHandled is initialized as FALSE by default */ + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + #if (USBFS_ENABLE_MSC_CLASS) + case USBFS_CLASS_MSD: + #if (USBFS_HANDLE_MSC_REQUESTS) + /* MSC requests are handled by the component. */ + requestHandled = USBFS_DispatchMSCClassRqst(); + #elif defined(USBFS_DISPATCH_MSC_CLASS_RQST_CALLBACK) + /* MSC requests are handled by user defined callbcak. */ + requestHandled = USBFS_DispatchMSCClassRqst_Callback(); + #else + /* MSC requests are not handled. */ + requestHandled = USBFS_FALSE; + #endif /* (USBFS_HANDLE_MSC_REQUESTS) */ + break; + #endif /* (USBFS_ENABLE_MSC_CLASS) */ + + default: + /* Request is not handled: unknown class request type. */ + requestHandled = USBFS_FALSE; break; } +#else /*No class is defined*/ + if (0u != interfaceNumber) + { + /* Suppress warning message */ + } + requestHandled = USBFS_FALSE; +#endif /*HID or AUDIO or MSC or CDC class enabled*/ /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ /* `#END` */ - #ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK - USBFS_DispatchClassRqst_Callback(); - #endif /* USBFS_DISPATCH_CLASS_RQST_CALLBACK */ +#ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK + if (USBFS_FALSE == requestHandled) + { + requestHandled = USBFS_DispatchClassRqst_Callback(interfaceNumber); + } +#endif /* (USBFS_DISPATCH_CLASS_RQST_CALLBACK) */ - return(requestHandled); + return (requestHandled); } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h new file mode 100755 index 0000000..2fd19d6 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h @@ -0,0 +1,278 @@ +/***************************************************************************//** +* \file USBFS_cydmac.h +* \version 3.10 +* +* \brief +* This file provides macros implemenation of DMA_P4 functions. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cydmac_H) +#define CY_USBFS_USBFS_cydmac_H + +#include "USBFS_pvt.h" + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetConfiguration +****************************************************************************//** +* +* Sets configuration information for the specified descriptor. +* +* \param ch: DMA ch modified by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param cfg: Descriptor control register. +* +* \sideeffect +* The status register associated with the specified descriptor is reset to +* zero after this function call. This function should not be called while +* the descriptor is active. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetConfiguration(ch, descr, cfg) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[ch][descr].ctl = (cfg); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetInterruptMask +****************************************************************************//** +* +* Enables the DMA channel interrupt. +* +* \param ch: Channel used by this function. +* +* +*******************************************************************************/ +#define USBFS_CyDmaSetInterruptMask(ch) \ + do{ \ + CYDMA_INTR_MASK_REG |= ((uint32)(1UL << (ch))); \ + }while(0) + + +/******************************************************************************* +* Function Name:USBFS_CyDmaSetDescriptor0Next +****************************************************************************//** +* +* Sets the descriptor 0 that should be run the next time the channel is +* triggered. +* +* \param channel: Channel used by this function. +* +* +*******************************************************************************/ +#define USBFS_CyDmaSetDescriptor0Next(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_DESCRIPTOR; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetNumDataElements +****************************************************************************//** +* +* Sets the number of data elements to transfer for specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param numEl: Total number of data elements this descriptor transfers - 1u. +* Valid ranges are 0 to 65535. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetNumDataElements(ch, descr, numEl) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl = \ + ((CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl & (uint32) ~CYDMA_DATA_NR) | ((uint32) (numEl))); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaGetSrcAddress +****************************************************************************//** +* +* Returns the source address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Specifies descriptor (0 or 1) used by this function. +* +* \return +* Source address written to specified descriptor. +* +*******************************************************************************/ +#define USBFS_CyDmaGetSrcAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetSrcAddress +****************************************************************************//** +* +* Configures the source address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param srcAddress: Address of DMA transfer source. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetSrcAddress(ch, descr, srcAddress) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src = (srcAddress); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaGetDstAddress +****************************************************************************//** +* +* Returns the destination address for the specified descriptor, set by +* CyDmaSetDstAddress(). +* +* \param ch: Channel used by this function. +* \param descr: Specifies descriptor (0 or 1) used by this function. +* +* \return +* Destination address written to specified descriptor. +* +*******************************************************************************/ +#define USBFS_CyDmaGetDstAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetDstAddress +****************************************************************************//** +* +* Configures the destination address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param dstAddress: Address of DMA transfer destination. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetDstAddress(ch, descr, dstAddress) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst = (dstAddress); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaValidateDescriptor +****************************************************************************//** +* +* Validates the specified descriptor after it has been invalidated. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* +* +* \sideeffect +* The status register associated with the specified descriptor is reset to +* zero after this function call. +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaValidateDescriptor(ch, descr) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].status = CYDMA_VALID; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaChEnable +****************************************************************************//** +* +* Enables the DMA ch. +* +* \param ch: Channel used by this function. +* +* +* \sideeffect +* If this function is called before DMA is completely configured the operation +* of the DMA is undefined and could result in system data corruption. +* +*******************************************************************************/ +#define USBFS_CyDmaChEnable(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] |= CYDMA_ENABLED; \ + }while(0) + + +/******************************************************************************* +* Function Name: CyDmaChDisable +****************************************************************************//** +* +* Disables the DMA ch. +* +* \param ch: Channel used by this function. +* +* +* \sideeffect +* If this function is called during a DMA transfer the transfer is aborted. +* +*******************************************************************************/ +#define USBFS_CyDmaChDisable(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_ENABLED; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaTriggerIn +****************************************************************************//** +* +* Triggers the DMA channel to execute a transfer. The tr_in signal is +* triggered. +* +* \param trSel: trigger to be activated. +* +* +*******************************************************************************/ +#define USBFS_DMA_USB_REQ_TR_OUT (0xC0020100U) +#define USBFS_CyDmaTriggerIn(trSel) \ + do{ \ + CYDMA_TR_CTL_REG = USBFS_DMA_USB_REQ_TR_OUT | (uint32)(trSel); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaTriggerOut +****************************************************************************//** +* +* Triggers the DMA channel to generate a transfer completion signal without +* actual transfer executed. The tr_out signal is triggered. +* +* \param trSel: trigger to be activated. +* +* +*******************************************************************************/ +#define USBFS_DMA_USB_BURST_END_TR_OUT (0xC0020300U) +#define USBFS_CyDmaTriggerOut(trSel) \ + do{ \ + CYDMA_TR_CTL_REG = USBFS_DMA_USB_BURST_END_TR_OUT | (uint32)(trSel); \ + }while(0) + + +#endif /* (CY_USBFS_USBFS_cydmac_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c old mode 100644 new mode 100755 index ccd6a78..f72cf9b --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -1,20 +1,18 @@ -/******************************************************************************* -* File Name: USBFS_descr.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_descr.c +* \version 3.10 * -* Description: -* USB descriptors and storage. -* -* Note: +* \brief +* This file contains the USB descriptors and storage. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" #include "USBFS_pvt.h" @@ -384,8 +382,9 @@ const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u] = { * Device Dispatch Table -- Points to the Device Descriptor and each of * and Configuration Tables for this Device *********************************************************************/ -const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = { +const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u] = { {0x01u, &USBFS_DEVICE0_DESCR}, + {0x00u, NULL}, {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} }; /********************************************************************* diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c index 39820f9..c6f57d2 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c @@ -1,20 +1,18 @@ -/******************************************************************************* -* File Name: USBFS_drv.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_drv.c +* \version 3.10 * -* Description: -* Endpoint 0 Driver for the USBFS Component. -* -* Note: +* \brief +* This file contains the Endpoint 0 Driver for the USBFS Component. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" #include "USBFS_pvt.h" @@ -24,15 +22,42 @@ ***************************************/ volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; + +/** Contains the current configuration number, which is set by the host using a + * SET_CONFIGURATION request. This variable is initialized to zero in + * USBFS_InitComponent() API and can be read by the USBFS_GetConfiguration() + * API.*/ volatile uint8 USBFS_configuration; + +/** Contains the current interface number.*/ volatile uint8 USBFS_interfaceNumber; + +/** This variable is set to one after SET_CONFIGURATION and SET_INTERFACE + *requests. It can be read by the USBFS_IsConfigurationChanged() API */ volatile uint8 USBFS_configurationChanged; + +/** Contains the current device address.*/ volatile uint8 USBFS_deviceAddress; + +/** This is a two-bit variable that contains power status in the bit 0 + * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote wakeup + * status (DEVICE_STATUS_REMOTE_WAKEUP) in the bit 1. This variable is + * initialized to zero in USBFS_InitComponent() API, configured by the + * USBFS_SetPowerStatus() API. The remote wakeup status cannot be set using the + * API SetPowerStatus(). */ volatile uint8 USBFS_deviceStatus; + volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; + +/** Contains the started device number. This variable is set by the + * USBFS_Start() or USBFS_InitComponent() APIs.*/ volatile uint8 USBFS_device; + +/** Initialized class array for each interface. It is used for handling Class + * specific requests depend on interface class. Different classes in multiple + * alternate settings are not supported.*/ const uint8 CYCODE *USBFS_interfaceClass; @@ -40,64 +65,68 @@ const uint8 CYCODE *USBFS_interfaceClass; * Local data allocation ***************************************/ -volatile uint8 USBFS_ep0Toggle; -volatile uint8 USBFS_lastPacketSize; -volatile uint8 USBFS_transferState; +volatile uint8 USBFS_ep0Toggle; +volatile uint8 USBFS_lastPacketSize; + +/** This variable is used by the communication functions to handle the current +* transfer state. +* Initialized to TRANS_STATE_IDLE in the USBFS_InitComponent() API and after a +* complete transfer in the status stage. +* Changed to the TRANS_STATE_CONTROL_READ or TRANS_STATE_CONTROL_WRITE in setup +* transaction depending on the request type. +*/ +volatile uint8 USBFS_transferState; volatile T_USBFS_TD USBFS_currentTD; -volatile uint8 USBFS_ep0Mode; -volatile uint8 USBFS_ep0Count; +volatile uint8 USBFS_ep0Mode; +volatile uint8 USBFS_ep0Count; volatile uint16 USBFS_transferByteCount; /******************************************************************************* * Function Name: USBFS_ep_0_Interrupt -******************************************************************************** +****************************************************************************//** * -* Summary: * This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. * It dispatches setup requests and handles the data and status stages. * -* Parameters: -* None. -* -* Return: -* None. * *******************************************************************************/ CY_ISR(USBFS_EP_0_ISR) { - uint8 bRegTemp; + uint8 tempReg; uint8 modifyReg; - #ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK - USBFS_EP_0_ISR_EntryCallback(); - #endif /* USBFS_EP_0_ISR_ENTRY_CALLBACK */ +#ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK + USBFS_EP_0_ISR_EntryCallback(); +#endif /* (USBFS_EP_0_ISR_ENTRY_CALLBACK) */ - bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); - if ((bRegTemp & USBFS_MODE_ACKD) != 0u) + tempReg = USBFS_EP0_CR_REG; + if ((tempReg & USBFS_MODE_ACKD) != 0u) { modifyReg = 1u; - if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) + if ((tempReg & USBFS_MODE_SETUP_RCVD) != 0u) { - if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) + if ((tempReg & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) { - modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */ + /* Mode not equal to NAK_IN_OUT: invalid setup */ + modifyReg = 0u; } else { USBFS_HandleSetup(); - if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) + + if ((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) { - modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */ + /* SETUP bit set: exit without mode modificaiton */ + modifyReg = 0u; } - } } - else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) + else if ((tempReg & USBFS_MODE_IN_RCVD) != 0u) { USBFS_HandleIN(); } - else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) + else if ((tempReg & USBFS_MODE_OUT_RCVD) != 0u) { USBFS_HandleOUT(); } @@ -105,87 +134,109 @@ CY_ISR(USBFS_EP_0_ISR) { modifyReg = 0u; } - if(modifyReg != 0u) + + /* Modify the EP0_CR register */ + if (modifyReg != 0u) { - bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */ + + tempReg = USBFS_EP0_CR_REG; + + /* Make sure that SETUP bit is cleared before modification */ + if ((tempReg & USBFS_MODE_SETUP_RCVD) == 0u) { - /* Update the count register */ - bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; - CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); - if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */ + /* Update count register */ + tempReg = (uint8) USBFS_ep0Toggle | USBFS_ep0Count; + USBFS_EP0_CNT_REG = tempReg; + + /* Make sure that previous write operaiton was successful */ + if (tempReg == USBFS_EP0_CNT_REG) { + /* Repeat until next successful write operation */ do { - modifyReg = USBFS_ep0Mode; /* Init temporary variable */ - /* Unlock registers */ - bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; - if(bRegTemp == 0u) /* Check if SETUP bit is not set */ + /* Init temporary variable */ + modifyReg = USBFS_ep0Mode; + + /* Unlock register */ + tempReg = (uint8) (USBFS_EP0_CR_REG & USBFS_MODE_SETUP_RCVD); + + /* Check if SETUP bit is not set */ + if (0u == tempReg) { /* Set the Mode Register */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); + USBFS_EP0_CR_REG = USBFS_ep0Mode; + /* Writing check */ - modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; + modifyReg = USBFS_EP0_CR_REG & USBFS_MODE_MASK; } - }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ + } + while (modifyReg != USBFS_ep0Mode); } } } } - #ifdef USBFS_EP_0_ISR_EXIT_CALLBACK - USBFS_EP_0_ISR_ExitCallback(); - #endif /* USBFS_EP_0_ISR_EXIT_CALLBACK */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_EP0_INTR); + +#ifdef USBFS_EP_0_ISR_EXIT_CALLBACK + USBFS_EP_0_ISR_ExitCallback(); +#endif /* (USBFS_EP_0_ISR_EXIT_CALLBACK) */ } /******************************************************************************* * Function Name: USBFS_HandleSetup -******************************************************************************** +****************************************************************************//** * -* Summary: * This Routine dispatches requests for the four USB request types * -* Parameters: -* None. * -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_HandleSetup(void) { uint8 requestHandled; + + /* Clear register lock by SIE (read register) and clear setup bit + * (write any value in register). + */ + requestHandled = (uint8) USBFS_EP0_CR_REG; + USBFS_EP0_CR_REG = (uint8) requestHandled; + requestHandled = (uint8) USBFS_EP0_CR_REG; - requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ - CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ - requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ - if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) + if ((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) { - USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */ + /* SETUP bit is set: exit without mode modification. */ + USBFS_ep0Mode = requestHandled; } else { /* In case the previous transfer did not complete, close it out */ USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); - switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) + /* Check request type. */ + switch (USBFS_bmRequestTypeReg & USBFS_RQST_TYPE_MASK) { case USBFS_RQST_TYPE_STD: requestHandled = USBFS_HandleStandardRqst(); break; + case USBFS_RQST_TYPE_CLS: requestHandled = USBFS_DispatchClassRqst(); break; + case USBFS_RQST_TYPE_VND: requestHandled = USBFS_HandleVendorRqst(); break; + default: requestHandled = USBFS_FALSE; break; } + + /* If request is not recognized. Stall endpoint 0 IN and OUT. */ if (requestHandled == USBFS_FALSE) { USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; @@ -196,18 +247,12 @@ void USBFS_HandleSetup(void) /******************************************************************************* * Function Name: USBFS_HandleIN -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine handles EP0 IN transfers. * -* Parameters: -* None. * -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -217,15 +262,19 @@ void USBFS_HandleIN(void) { case USBFS_TRANS_STATE_IDLE: break; + case USBFS_TRANS_STATE_CONTROL_READ: USBFS_ControlReadDataStage(); break; + case USBFS_TRANS_STATE_CONTROL_WRITE: USBFS_ControlWriteStatusStage(); break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: USBFS_NoDataControlStatusStage(); break; + default: /* there are no more states */ break; } @@ -234,18 +283,12 @@ void USBFS_HandleIN(void) /******************************************************************************* * Function Name: USBFS_HandleOUT -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine handles EP0 OUT transfers. * -* Parameters: -* None. * -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -255,19 +298,25 @@ void USBFS_HandleOUT(void) { case USBFS_TRANS_STATE_IDLE: break; + case USBFS_TRANS_STATE_CONTROL_READ: USBFS_ControlReadStatusStage(); break; + case USBFS_TRANS_STATE_CONTROL_WRITE: USBFS_ControlWriteDataStage(); break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: /* Update the completion block */ USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); + /* We expect no more data, so stall INs and OUTs */ USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; break; - default: /* There are no more states */ + + default: + /* There are no more states */ break; } } @@ -275,10 +324,9 @@ void USBFS_HandleOUT(void) /******************************************************************************* * Function Name: USBFS_LoadEP0 -******************************************************************************** +****************************************************************************//** * -* Summary: -* This routine loads the EP0 data registers for OUT transfers. It uses the +* This routine loads the EP0 data registers for OUT transfers. It uses the * currentTD (previously initialized by the _InitControlWrite function and * updated for each OUT transfer, and the bLastPacketSize) to determine how * many uint8s to transfer on the current OUT. @@ -288,13 +336,8 @@ void USBFS_HandleOUT(void) * of the control endpoint size (8) or remaining number of uint8s for the * transaction. * -* Parameters: -* None. * -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_transferByteCount - Update the transfer byte count from the * last transaction. * USBFS_ep0Count - counts the data loaded to the SIE memory in @@ -307,7 +350,7 @@ void USBFS_HandleOUT(void) * USBFS_ep0Mode - prepare for mode register content. * USBFS_transferState - set to TRANS_STATE_CONTROL_READ * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -317,16 +360,18 @@ void USBFS_LoadEP0(void) /* Update the transfer byte count from the last transaction */ USBFS_transferByteCount += USBFS_lastPacketSize; + /* Now load the next transaction */ while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) { - CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData); + USBFS_EP0_DR_BASE.epData[ep0Count] = (uint8) *USBFS_currentTD.pData; USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; ep0Count++; USBFS_currentTD.count--; } - /* Support zero-length packet*/ - if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) ) + + /* Support zero-length packet */ + if ((USBFS_lastPacketSize == 8u) || (ep0Count > 0u)) { /* Update the data toggle */ USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; @@ -344,39 +389,37 @@ void USBFS_LoadEP0(void) } /* Save the packet size for next time */ - USBFS_lastPacketSize = ep0Count; - USBFS_ep0Count = ep0Count; + USBFS_ep0Count = (uint8) ep0Count; + USBFS_lastPacketSize = (uint8) ep0Count; } /******************************************************************************* * Function Name: USBFS_InitControlRead -******************************************************************************** +****************************************************************************//** * -* Summary: -* Initialize a control read transaction, usable to send data to the host. +* Initialize a control read transaction. It is used to send data to the host. * The following global variables should be initialized before this function * called. To send zero length packet use InitZeroLengthControlTransfer * function. * -* Parameters: -* None. * -* Return: +* \return * requestHandled state. * -* Global variables: +* \globalvars * USBFS_currentTD.count - counts of data to be sent. * USBFS_currentTD.pData - data pointer. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_InitControlRead(void) { uint16 xferCount; - if(USBFS_currentTD.count == 0u) + + if (USBFS_currentTD.count == 0u) { (void) USBFS_InitZeroLengthControlTransfer(); } @@ -384,44 +427,44 @@ uint8 USBFS_InitControlRead(void) { /* Set up the state machine */ USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the toggle, it gets updated in LoadEP */ USBFS_ep0Toggle = 0u; + /* Initialize the Status Block */ USBFS_InitializeStatusBlock(); - xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg)); if (USBFS_currentTD.count > xferCount) { USBFS_currentTD.count = xferCount; } + USBFS_LoadEP0(); } - return(USBFS_TRUE); + return (USBFS_TRUE); } /******************************************************************************* * Function Name: USBFS_InitZeroLengthControlTransfer -******************************************************************************** +****************************************************************************//** * -* Summary: * Initialize a zero length data IN transfer. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled state. * -* Global variables: +* \globalvars * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE * USBFS_ep0Mode - prepare for mode register content. * USBFS_transferState - set to TRANS_STATE_CONTROL_READ * USBFS_ep0Count - cleared, means the zero-length packet. * USBFS_lastPacketSize - cleared. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -430,32 +473,30 @@ uint8 USBFS_InitZeroLengthControlTransfer(void) { /* Update the state */ USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the data toggle */ USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Save the packet size for next time */ USBFS_lastPacketSize = 0u; + USBFS_ep0Count = 0u; - return(USBFS_TRUE); + return (USBFS_TRUE); } /******************************************************************************* * Function Name: USBFS_ControlReadDataStage -******************************************************************************** +****************************************************************************//** * -* Summary: * Handle the Data Stage of a control read transfer. * -* Parameters: -* None. * -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -468,23 +509,17 @@ void USBFS_ControlReadDataStage(void) /******************************************************************************* * Function Name: USBFS_ControlReadStatusStage -******************************************************************************** +****************************************************************************//** * -* Summary: * Handle the Status Stage of a control read transfer. * -* Parameters: -* None. * -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_USBFS_transferByteCount - updated with last packet size. * USBFS_transferState - set to TRANS_STATE_IDLE. * USBFS_ep0Mode - set to MODE_STALL_IN_OUT. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -492,34 +527,33 @@ void USBFS_ControlReadStatusStage(void) { /* Update the transfer byte count */ USBFS_transferByteCount += USBFS_lastPacketSize; + /* Go Idle */ USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ - USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; } /******************************************************************************* * Function Name: USBFS_InitControlWrite -******************************************************************************** +****************************************************************************//** * -* Summary: * Initialize a control write transaction * -* Parameters: -* None. -* -* Return: +* \return * requestHandled state. * -* Global variables: +* \globalvars * USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE * USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -529,12 +563,14 @@ uint8 USBFS_InitControlWrite(void) /* Set up the state machine */ USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; + /* This might not be necessary */ USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Initialize the Status Block */ USBFS_InitializeStatusBlock(); - xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg)); if (USBFS_currentTD.count > xferCount) { @@ -550,21 +586,15 @@ uint8 USBFS_InitControlWrite(void) /******************************************************************************* * Function Name: USBFS_ControlWriteDataStage -******************************************************************************** +****************************************************************************//** * -* Summary: * Handle the Data Stage of a control write transfer * 1. Get the data (We assume the destination was validated previously) * 2. Update the count and data toggle * 3. Update the mode register for the next transaction * -* Parameters: -* None. * -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_transferByteCount - Update the transfer byte count from the * last transaction. * USBFS_ep0Count - counts the data loaded from the SIE memory @@ -574,7 +604,7 @@ uint8 USBFS_InitControlWrite(void) * USBFS_ep0Toggle - inverted * USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -583,22 +613,24 @@ void USBFS_ControlWriteDataStage(void) uint8 ep0Count; uint8 regIndex = 0u; - ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - - USBFS_EPX_CNTX_CRC_COUNT; + ep0Count = (USBFS_EP0_CNT_REG & USBFS_EPX_CNT0_MASK) - USBFS_EPX_CNTX_CRC_COUNT; - USBFS_transferByteCount += ep0Count; + USBFS_transferByteCount += (uint8)ep0Count; while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) { - *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); + *USBFS_currentTD.pData = (uint8) USBFS_EP0_DR_BASE.epData[regIndex]; USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; regIndex++; ep0Count--; USBFS_currentTD.count--; } - USBFS_ep0Count = ep0Count; + + USBFS_ep0Count = (uint8)ep0Count; + /* Update the data toggle */ USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Expect Data or Status Stage */ USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; } @@ -606,22 +638,15 @@ void USBFS_ControlWriteDataStage(void) /******************************************************************************* * Function Name: USBFS_ControlWriteStatusStage -******************************************************************************** +****************************************************************************//** * -* Summary: * Handle the Status Stage of a control write transfer * -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_transferState - set to TRANS_STATE_IDLE. * USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -629,8 +654,10 @@ void USBFS_ControlWriteStatusStage(void) { /* Go Idle */ USBFS_transferState = USBFS_TRANS_STATE_IDLE; - /* Update the completion block */ + + /* Update the completion block */ USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; } @@ -638,102 +665,89 @@ void USBFS_ControlWriteStatusStage(void) /******************************************************************************* * Function Name: USBFS_InitNoDataControlTransfer -******************************************************************************** +****************************************************************************//** * -* Summary: * Initialize a no data control transfer * -* Parameters: -* None. -* -* Return: +* \return * requestHandled state. * -* Global variables: +* \globalvars * USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. * USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. * USBFS_ep0Count - cleared. * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_InitNoDataControlTransfer(void) { USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; - USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; - USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; - USBFS_ep0Count = 0u; + USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + USBFS_ep0Count = 0u; - return(USBFS_TRUE); + return (USBFS_TRUE); } /******************************************************************************* * Function Name: USBFS_NoDataControlStatusStage -******************************************************************************** -* Summary: +****************************************************************************//** * Handle the Status Stage of a no data control transfer. * * SET_ADDRESS is special, since we need to receive the status stage with * the old address. * -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_transferState - set to TRANS_STATE_IDLE. * USBFS_ep0Mode - set to MODE_STALL_IN_OUT. * USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE * USBFS_deviceAddress - used to set new address and cleared * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_NoDataControlStatusStage(void) { - /* Change the USB address register if we got a SET_ADDRESS. */ - if (USBFS_deviceAddress != 0u) + if (0u != USBFS_deviceAddress) { - CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); + /* Update device address if we got new address. */ + USBFS_CR0_REG = (uint8) USBFS_deviceAddress | USBFS_CR0_ENABLE; USBFS_deviceAddress = 0u; } - /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; - /* Update the completion block */ + + /* Update the completion block. */ USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); - /* We expect no more data, so stall INs and OUTs */ + + /* Stall IN and OUT, no more data is expected. */ USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; } /******************************************************************************* * Function Name: USBFS_UpdateStatusBlock -******************************************************************************** +****************************************************************************//** * -* Summary: * Update the Completion Status Block for a Request. The block is updated * with the completion code the USBFS_transferByteCount. The * StatusBlock Pointer is set to NULL. * -* Parameters: * completionCode - status. * -* Return: -* None. * -* Global variables: +* \globalvars * USBFS_currentTD.pStatusBlock->status - updated by the * completionCode parameter. * USBFS_currentTD.pStatusBlock->length - updated. * USBFS_currentTD.pStatusBlock - cleared. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -750,34 +764,28 @@ void USBFS_UpdateStatusBlock(uint8 completionCode) /******************************************************************************* * Function Name: USBFS_InitializeStatusBlock -******************************************************************************** +****************************************************************************//** * -* Summary: * Initialize the Completion Status Block for a Request. The completion * code is set to USB_XFER_IDLE. * * Also, initializes USBFS_transferByteCount. Save some space, * this is the only consumer. * -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. * USBFS_currentTD.pStatusBlock->length - cleared. * USBFS_transferByteCount - cleared. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_InitializeStatusBlock(void) { USBFS_transferByteCount = 0u; - if(USBFS_currentTD.pStatusBlock != NULL) + + if (USBFS_currentTD.pStatusBlock != NULL) { USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; USBFS_currentTD.pStatusBlock->length = 0u; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c index 56a4a29..e8804b0 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c @@ -1,29 +1,21 @@ -/******************************************************************************* -* File Name: USBFS_episr.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_episr.c +* \version 3.10 * -* Description: -* Data endpoint Interrupt Service Routines -* -* Note: +* \brief +* This file contains the Data endpoint Interrupt Service Routines. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" #include "USBFS_pvt.h" +#include "USBFS_cydmac.h" -#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) - #include "USBFS_midi.h" -#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */ -#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - #include "USBFS_EP8_DMA_Done_SR.h" - #include "USBFS_EP17_DMA_Done_SR.h" -#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */ /*************************************** @@ -34,702 +26,797 @@ /* `#END` */ -#if(USBFS_EP1_ISR_REMOVE == 0u) - - +#if (USBFS_EP1_ISR_ACTIVE) /****************************************************************************** * Function Name: USBFS_EP_1_ISR - ******************************************************************************* + ***************************************************************************//** * - * Summary: * Endpoint 1 Interrupt Service Routine * - * Parameters: - * None. - * - * Return: - * None. - * ******************************************************************************/ CY_ISR(USBFS_EP_1_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK - USBFS_EP_1_ISR_EntryCallback(); - #endif /* USBFS_EP_1_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK + USBFS_EP_1_ISR_EntryCallback(); + #endif /* (USBFS_EP_1_ISR_ENTRY_CALLBACK) */ /* `#START EP1_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) & - (uint8)~USBFS_SIE_EP_INT_EP1_MASK); - - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP1) + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP1_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP1].addr & USBFS_DIR_IN)) + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP1].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP1) != USBFS_EP_TYPE_ISOC) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP1) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + /* `#START EP1_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK - USBFS_EP_1_ISR_ExitCallback(); - #endif /* USBFS_EP_1_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK + USBFS_EP_1_ISR_ExitCallback(); + #endif /* (USBFS_EP_1_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } -#endif /* USBFS_EP1_ISR_REMOVE */ +#endif /* (USBFS_EP1_ISR_ACTIVE) */ -#if(USBFS_EP2_ISR_REMOVE == 0u) - +#if (USBFS_EP2_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_2_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Endpoint 2 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. + * Endpoint 2 Interrupt Service Routine. * *******************************************************************************/ CY_ISR(USBFS_EP_2_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK - USBFS_EP_2_ISR_EntryCallback(); - #endif /* USBFS_EP_2_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK + USBFS_EP_2_ISR_EntryCallback(); + #endif /* (USBFS_EP_2_ISR_ENTRY_CALLBACK) */ /* `#START EP2_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP2_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP2) + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP2_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP2].addr & USBFS_DIR_IN)) + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP2].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP2) != USBFS_EP_TYPE_ISOC) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP2) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + /* `#START EP2_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK - USBFS_EP_2_ISR_ExitCallback(); - #endif /* USBFS_EP_2_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK + USBFS_EP_2_ISR_ExitCallback(); + #endif /* (USBFS_EP_2_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } - -#endif /* USBFS_EP2_ISR_REMOVE */ +#endif /* (USBFS_EP2_ISR_ACTIVE) */ -#if(USBFS_EP3_ISR_REMOVE == 0u) - +#if (USBFS_EP3_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_3_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Endpoint 3 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. + * Endpoint 3 Interrupt Service Routine. * *******************************************************************************/ CY_ISR(USBFS_EP_3_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ - - #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK - USBFS_EP_3_ISR_EntryCallback(); - #endif /* USBFS_EP_3_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK + USBFS_EP_3_ISR_EntryCallback(); + #endif /* (USBFS_EP_3_ISR_ENTRY_CALLBACK) */ /* `#START EP3_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP3_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP3) + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP3_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP3].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP3].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP3) != USBFS_EP_TYPE_ISOC) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP3) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ /* `#START EP3_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK - USBFS_EP_3_ISR_ExitCallback(); - #endif /* USBFS_EP_3_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK + USBFS_EP_3_ISR_ExitCallback(); + #endif /* (USBFS_EP_3_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } - -#endif /* USBFS_EP3_ISR_REMOVE */ +#endif /* (USBFS_EP3_ISR_ACTIVE) */ -#if(USBFS_EP4_ISR_REMOVE == 0u) - +#if (USBFS_EP4_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_4_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Endpoint 4 Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. + * Endpoint 4 Interrupt Service Routine. * *******************************************************************************/ CY_ISR(USBFS_EP_4_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK - USBFS_EP_4_ISR_EntryCallback(); - #endif /* USBFS_EP_4_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK + USBFS_EP_4_ISR_EntryCallback(); + #endif /* (USBFS_EP_4_ISR_ENTRY_CALLBACK) */ /* `#START EP4_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP4_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP4_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP4].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP4].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP4) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) if(USBFS_midi_out_ep == USBFS_EP4) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_MIDI_OUT_Service(); } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ /* `#START EP4_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK - USBFS_EP_4_ISR_ExitCallback(); - #endif /* USBFS_EP_4_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK + USBFS_EP_4_ISR_ExitCallback(); + #endif /* (USBFS_EP_4_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } - -#endif /* USBFS_EP4_ISR_REMOVE */ +#endif /* (USBFS_EP4_ISR_ACTIVE) */ -#if(USBFS_EP5_ISR_REMOVE == 0u) - +#if (USBFS_EP5_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_5_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Endpoint 5 Interrupt Service Routine * - * Parameters: - * None. - * - * Return: - * None. * *******************************************************************************/ CY_ISR(USBFS_EP_5_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK - USBFS_EP_5_ISR_EntryCallback(); - #endif /* USBFS_EP_5_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK + USBFS_EP_5_ISR_EntryCallback(); + #endif /* (USBFS_EP_5_ISR_ENTRY_CALLBACK) */ /* `#START EP5_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) { - USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP5_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP5) + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP5_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP5].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP5].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP5) != USBFS_EP_TYPE_ISOC) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP5) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ /* `#START EP5_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK - USBFS_EP_5_ISR_ExitCallback(); - #endif /* USBFS_EP_5_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK + USBFS_EP_5_ISR_ExitCallback(); + #endif /* (USBFS_EP_5_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } -#endif /* USBFS_EP5_ISR_REMOVE */ +#endif /* (USBFS_EP5_ISR_ACTIVE) */ -#if(USBFS_EP6_ISR_REMOVE == 0u) - +#if (USBFS_EP6_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_6_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Endpoint 6 Interrupt Service Routine + * Endpoint 6 Interrupt Service Routine. * - * Parameters: - * None. - * - * Return: - * None. * *******************************************************************************/ CY_ISR(USBFS_EP_6_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK - USBFS_EP_6_ISR_EntryCallback(); - #endif /* USBFS_EP_6_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK + USBFS_EP_6_ISR_EntryCallback(); + #endif /* (USBFS_EP_6_ISR_ENTRY_CALLBACK) */ /* `#START EP6_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP6_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP6) + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP6_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP6].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP6].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP6) != USBFS_EP_TYPE_ISOC) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP6) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ /* `#START EP6_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK - USBFS_EP_6_ISR_ExitCallback(); - #endif /* USBFS_EP_6_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK + USBFS_EP_6_ISR_ExitCallback(); + #endif /* (USBFS_EP_6_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } - -#endif /* USBFS_EP6_ISR_REMOVE */ +#endif /* (USBFS_EP6_ISR_ACTIVE) */ -#if(USBFS_EP7_ISR_REMOVE == 0u) - +#if (USBFS_EP7_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_7_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Endpoint 7 Interrupt Service Routine + * Endpoint 7 Interrupt Service Routine. * - * Parameters: - * None. - * - * Return: - * None. * *******************************************************************************/ CY_ISR(USBFS_EP_7_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK - USBFS_EP_7_ISR_EntryCallback(); - #endif /* USBFS_EP_7_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK + USBFS_EP_7_ISR_EntryCallback(); + #endif /* (USBFS_EP_7_ISR_ENTRY_CALLBACK) */ /* `#START EP7_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP7_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP7_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP7].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP7].epCr0; - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP7) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; + } + + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) if(USBFS_midi_out_ep == USBFS_EP7) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_MIDI_OUT_Service(); } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ /* `#START EP7_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK - USBFS_EP_7_ISR_ExitCallback(); - #endif /* USBFS_EP_7_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK + USBFS_EP_7_ISR_ExitCallback(); + #endif /* (USBFS_EP_7_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } - -#endif /* USBFS_EP7_ISR_REMOVE */ +#endif /* (USBFS_EP7_ISR_ACTIVE) */ -#if(USBFS_EP8_ISR_REMOVE == 0u) - +#if (USBFS_EP8_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_EP_8_ISR - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Endpoint 8 Interrupt Service Routine * - * Parameters: - * None. - * - * Return: - * None. * *******************************************************************************/ CY_ISR(USBFS_EP_8_ISR) { - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - uint8 int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK - USBFS_EP_8_ISR_EntryCallback(); - #endif /* USBFS_EP_8_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK + USBFS_EP_8_ISR_EntryCallback(); + #endif /* (USBFS_EP_8_ISR_ENTRY_CALLBACK) */ /* `#START EP8_USER_CODE` Place your code here */ /* `#END` */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - int_en = EA; - CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ - - CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */ - /* Do not toggle ISOC endpoint */ - if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) != - USBFS_EP_TYPE_ISOC) + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) { - USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; - } - USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; - CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) - & (uint8)~USBFS_SIE_EP_INT_EP8_MASK); + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT) - if(USBFS_midi_out_ep == USBFS_EP8) + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP8_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP8].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP8].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP8) != USBFS_EP_TYPE_ISOC) { - USBFS_MIDI_OUT_EP_Service(); + USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; } - #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP8) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ /* `#START EP8_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK - USBFS_EP_8_ISR_ExitCallback(); - #endif /* USBFS_EP_8_ISR_EXIT_CALLBACK */ + #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK + USBFS_EP_8_ISR_ExitCallback(); + #endif /* (USBFS_EP_8_ISR_EXIT_CALLBACK) */ - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ - USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) - EA = int_en; - #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ } - -#endif /* USBFS_EP8_ISR_REMOVE */ +#endif /* (USBFS_EP8_ISR_ACTIVE) */ -/******************************************************************************* -* Function Name: USBFS_SOF_ISR -******************************************************************************** -* -* Summary: -* Start of Frame Interrupt Service Routine -* -* Parameters: -* None. -* -* Return: -* None. -* -*******************************************************************************/ -CY_ISR(USBFS_SOF_ISR) -{ - #ifdef USBFS_SOF_ISR_INTERRUPT_CALLBACK - USBFS_SOF_ISR_InterruptCallback(); - #endif /* USBFS_SOF_ISR_INTERRUPT_CALLBACK */ +#if (USBFS_SOF_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_SOF_ISR + ****************************************************************************//** + * + * Start of Frame Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_SOF_ISR) + { + #ifdef USBFS_SOF_ISR_ENTRY_CALLBACK + USBFS_SOF_ISR_EntryCallback(); + #endif /* (USBFS_SOF_ISR_ENTRY_CALLBACK) */ - /* `#START SOF_USER_CODE` Place your code here */ + /* `#START SOF_USER_CODE` Place your code here */ - /* `#END` */ -} + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_SOF_INTR); + + #ifdef USBFS_SOF_ISR_EXIT_CALLBACK + USBFS_SOF_ISR_ExitCallback(); + #endif /* (USBFS_SOF_ISR_EXIT_CALLBACK) */ + } +#endif /* (USBFS_SOF_ISR_ACTIVE) */ +#if (USBFS_BUS_RESET_ISR_ACTIVE) /******************************************************************************* * Function Name: USBFS_BUS_RESET_ISR -******************************************************************************** +****************************************************************************//** * -* Summary: * USB Bus Reset Interrupt Service Routine. Calls _Start with the same * parameters as the last USER call to _Start * -* Parameters: -* None. -* -* Return: -* None. * *******************************************************************************/ CY_ISR(USBFS_BUS_RESET_ISR) { - #ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK - USBFS_BUS_RESET_ISR_EntryCallback(); - #endif /* USBFS_BUS_RESET_ISR_ENTRY_CALLBACK */ +#ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK + USBFS_BUS_RESET_ISR_EntryCallback(); +#endif /* (USBFS_BUS_RESET_ISR_ENTRY_CALLBACK) */ /* `#START BUS_RESET_USER_CODE` Place your code here */ /* `#END` */ + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_BUS_RESET_INTR); + USBFS_ReInitComponent(); - #ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK - USBFS_BUS_RESET_ISR_ExitCallback(); - #endif /* USBFS_BUS_RESET_ISR_EXIT_CALLBACK */ +#ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK + USBFS_BUS_RESET_ISR_ExitCallback(); +#endif /* (USBFS_BUS_RESET_ISR_EXIT_CALLBACK) */ } +#endif /* (USBFS_BUS_RESET_ISR_ACTIVE) */ -#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) +#if (USBFS_LPM_ACTIVE) +/*************************************************************************** +* Function Name: USBFS_INTR_LPM_ISR +************************************************************************//** +* +* Interrupt Service Routine for LPM of the interrupt sources. +* +* +***************************************************************************/ +CY_ISR(USBFS_LPM_ISR) +{ +#ifdef USBFS_LPM_ISR_ENTRY_CALLBACK + USBFS_LPM_ISR_EntryCallback(); +#endif /* (USBFS_LPM_ISR_ENTRY_CALLBACK) */ + + /* `#START LPM_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_LPM_INTR); + + /* `#START LPM_END_USER_CODE` Place your code here */ + + /* `#END` */ + +#ifdef USBFS_LPM_ISR_EXIT_CALLBACK + USBFS_LPM_ISR_ExitCallback(); +#endif /* (USBFS_LPM_ISR_EXIT_CALLBACK) */ +} +#endif /* (USBFS_LPM_ACTIVE) */ - /******************************************************************************* +#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + /*************************************************************************** * Function Name: USBFS_ARB_ISR - ******************************************************************************** + ************************************************************************//** * - * Summary: - * Arbiter Interrupt Service Routine + * Arbiter Interrupt Service Routine. * - * Parameters: - * None. * - * Return: - * None. - * - * Side effect: - * Search for EP8 int_status will be much slower than search for EP1 int_status. - * - *******************************************************************************/ + ***************************************************************************/ CY_ISR(USBFS_ARB_ISR) { - uint8 int_status; - uint8 ep_status; + uint8 arbIntrStatus; + uint8 epStatus; uint8 ep = USBFS_EP1; - uint8 ptr = 0u; - #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK - USBFS_ARB_ISR_EntryCallback(); - #endif /* USBFS_ARB_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK + USBFS_ARB_ISR_EntryCallback(); + #endif /* (USBFS_ARB_ISR_ENTRY_CALLBACK) */ /* `#START ARB_BEGIN_USER_CODE` Place your code here */ /* `#END` */ - int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */ - USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */ + /* Get pending ARB interrupt sources. */ + arbIntrStatus = USBFS_ARB_INT_SR_REG; - while(int_status != 0u) + while (0u != arbIntrStatus) { - if((int_status & 1u) != 0u) /* If EpX interrupt present */ - { /* read Endpoint Status Register */ - ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); - /* If In Buffer Full */ - if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u) + /* Check which EP is interrupt source. */ + if (0u != (arbIntrStatus & 0x01u)) + { + /* Get endpoint enable interrupt sources. */ + epStatus = (USBFS_ARB_EP_BASE.arbEp[ep].epSr & USBFS_ARB_EP_BASE.arbEp[ep].epIntEn); + + /* Handle IN endpoint buffer full event: happens only once when endpoint buffer is loaded. */ + if (0u != (epStatus & USBFS_ARB_EPX_INT_IN_BUF_FULL)) { - if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) { - /* Clear Data ready status */ - *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &= - (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; - #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - /* Setup common area DMA with rest of the data */ + /* Clear data ready status. */ + USBFS_ARB_EP_BASE.arbEp[ep].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + #if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /* Set up common area DMA with rest of data. */ if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST) { USBFS_LoadNextInEP(ep, 0u); @@ -738,144 +825,530 @@ CY_ISR(USBFS_BUS_RESET_ISR) { USBFS_inBufFull[ep] = 1u; } - #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode); - #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) - if(ep == USBFS_midi_in_ep) - { /* Clear MIDI input pointer */ - USBFS_midiInPointer = 0u; - } - #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_EP[ep].epMode; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) + if (ep == USBFS_midi_in_ep) + { + /* Clear MIDI input pointer. */ + USBFS_midiInPointer = 0u; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ } } - /* (re)arm Out EP only for mode2 */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - /* If DMA Grant */ - if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u) + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Handle DMA completion event for OUT endpoints. */ + if (0u != (epStatus & USBFS_ARB_EPX_SR_DMA_GNT)) + { + if (0u == (USBFS_EP[ep].addr & USBFS_DIR_IN)) { - if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u) - { - USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - /* Write the Mode register */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), - USBFS_EP[ep].epMode); - } + /* Notify user that data has been copied from endpoint buffer. */ + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + + /* DMA done coping data: OUT endpoint has to be re-armed by user. */ } - #endif /* USBFS_EP_MM */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Handle DMA completion event for OUT endpoints. */ + if (0u != (epStatus & USBFS_ARB_EPX_INT_DMA_TERMIN)) + { + uint32 channelNum = USBFS_DmaChan[ep]; + + /* Restore burst counter for endpoint. */ + USBFS_DmaEpBurstCnt[ep] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCntBackup[ep]); + + /* Disable DMA channel to restore descriptor configuration. The on-going transfer is aborted. */ + USBFS_CyDmaChDisable(channelNum); + + /* Generate DMA tr_out signal to notify USB IP that DMA is done. This signal is not generated + * when transfer was aborted (it occurs when host writes less bytes than buffer size). + */ + USBFS_CyDmaTriggerOut(USBFS_DmaBurstEndOut[ep]); + + /* Restore destination address for output endpoint. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep])); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Restore number of data elements to transfer which was adjusted for last burst. */ + if (0u != (USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_DESCR_REVERT)) + { + USBFS_CyDmaSetNumDataElements(channelNum, (USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT), + USBFS_DMA_GET_MAX_ELEM_PER_BURST(USBFS_DmaEpLastBurstEl[ep])); + } + + /* Validate descriptor 0 and 1 (also reset current state). Command to start with descriptor 0. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + if (USBFS_DmaEpBurstCntBackup[ep] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[ep].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(ep) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[ep].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* Notify user that data has been copied from endpoint buffer. */ + USBFS_EP[ep].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == ep) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + } + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ /* `#END` */ - #ifdef USBFS_ARB_ISR_CALLBACK - USBFS_ARB_ISR_Callback(); - #endif /* USBFS_ARB_ISR_CALLBACK */ + #ifdef USBFS_ARB_ISR_CALLBACK + USBFS_ARB_ISR_Callback(ep, epStatus); + #endif /* (USBFS_ARB_ISR_CALLBACK) */ - CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */ + /* Clear serviced endpoint interrupt sources. */ + USBFS_ARB_EP_BASE.arbEp[ep].epSr = epStatus; } - ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ - ep++; - int_status >>= 1u; + + ++ep; + arbIntrStatus >>= 1u; } /* `#START ARB_END_USER_CODE` Place your code here */ /* `#END` */ - #ifdef USBFS_ARB_ISR_EXIT_CALLBACK - USBFS_ARB_ISR_ExitCallback(); - #endif /* USBFS_ARB_ISR_EXIT_CALLBACK */ + #ifdef USBFS_ARB_ISR_EXIT_CALLBACK + USBFS_ARB_ISR_ExitCallback(); + #endif /* (USBFS_ARB_ISR_EXIT_CALLBACK) */ } -#endif /* USBFS_EP_MM */ +#endif /* (USBFS_ARB_ISR_ACTIVE && USBFS_EP_MANAGEMENT_DMA) */ + + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) -#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) /****************************************************************************** - * Function Name: USBFS_EP_DMA_DONE_ISR - ******************************************************************************* + * Function Name: USBFS_EPxDmaDone + ***************************************************************************//** * - * Summary: - * Endpoint 1 DMA Done Interrupt Service Routine - * - * Parameters: - * None. - * - * Return: - * None. + * \internal + * Endpoint DMA Done Interrupt Service Routine basic function . + * + * \param dmaCh + * number of DMA channel + * + * \param ep + * number of USB end point + * + * \param dmaDone + * transfer completion flag + * + * \return + * updated transfer completion flag * ******************************************************************************/ - CY_ISR(USBFS_EP_DMA_DONE_ISR) + CY_INLINE static void USBFS_EPxDmaDone(uint8 dmaCh, uint8 ep) { - uint8 int8Status; - uint8 int17Status; - uint8 ep_status; - uint8 ep = USBFS_EP1; - uint8 ptr = 0u; + uint32 nextAddr; + + /* Manage data elements which remain to transfer. */ + if (0u != USBFS_DmaEpBurstCnt[ep]) + { + if(USBFS_DmaEpBurstCnt[ep] <= 2u) + { + /* Adjust length of last burst. */ + USBFS_CyDmaSetNumDataElements(dmaCh, + ((uint32) USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT), + ((uint32) USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_BURST_BYTES_MASK)); + } + + + /* Advance source for input endpoint or destination for output endpoint. */ + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Change source for descriptor 0. */ + nextAddr = (uint32) USBFS_CyDmaGetSrcAddress(dmaCh, USBFS_DMA_DESCR0); + nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST); + USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr); + + /* Change source for descriptor 1. */ + nextAddr += USBFS_DMA_BYTES_PER_BURST; + USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr); + } + else + { + /* Change destination for descriptor 0. */ + nextAddr = (uint32) USBFS_CyDmaGetDstAddress(dmaCh, USBFS_DMA_DESCR0); + nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST); + USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr); + + /* Change destination for descriptor 1. */ + nextAddr += USBFS_DMA_BYTES_PER_BURST; + USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr); + } + + /* Enable DMA to execute transfer as it was disabled because there were no valid descriptor. */ + USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR0); + + --USBFS_DmaEpBurstCnt[ep]; + if (0u != USBFS_DmaEpBurstCnt[ep]) + { + USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR1); + --USBFS_DmaEpBurstCnt[ep]; + } + + USBFS_CyDmaChEnable (dmaCh); + USBFS_CyDmaTriggerIn(USBFS_DmaReqOut[ep]); + } + else + { + /* No data to transfer. False DMA trig. Ignore. */ + } + + } + + #if (USBFS_DMA1_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP1_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 1 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP1_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP1_DMA_CH, + USBFS_EP1); + + } + #endif /* (USBFS_DMA1_ACTIVE) */ + + + #if (USBFS_DMA2_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP2_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 2 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP2_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP2_DMA_CH, + USBFS_EP2); + } + #endif /* (USBFS_DMA2_ACTIVE) */ + + + #if (USBFS_DMA3_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP3_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 3 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP3_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP3_DMA_CH, + USBFS_EP3); + } + #endif /* (USBFS_DMA3_ACTIVE) */ + + + #if (USBFS_DMA4_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP4_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 4 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP4_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP4_DMA_CH, + USBFS_EP4); + } + #endif /* (USBFS_DMA4_ACTIVE) */ + + + #if (USBFS_DMA5_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP5_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 5 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP5_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP5_DMA_CH, + USBFS_EP5); + } + #endif /* (USBFS_DMA5_ACTIVE) */ + + + #if (USBFS_DMA6_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP6_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 6 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP6_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP6_DMA_CH, + USBFS_EP6); + } + #endif /* (USBFS_DMA6_ACTIVE) */ + + + #if (USBFS_DMA7_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP7_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 7 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP7_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP7_DMA_CH, + USBFS_EP7); + } + #endif /* (USBFS_DMA7_ACTIVE) */ + + + #if (USBFS_DMA8_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP8_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 8 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP8_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP8_DMA_CH, + USBFS_EP8); + } + #endif /* (USBFS_DMA8_ACTIVE) */ + + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + /****************************************************************************** + * Function Name: USBFS_EP_DMA_DONE_ISR + ***************************************************************************//** + * + * DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + CY_ISR(USBFS_EP_DMA_DONE_ISR) + { + uint8 int8Status; + uint8 int17Status; + uint8 ep_status; + uint8 ep = USBFS_EP1; #ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK USBFS_EP_DMA_DONE_ISR_EntryCallback(); - #endif /* USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK */ + #endif /* (USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK) */ - /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */ + /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */ - /* `#END` */ + /* `#END` */ - /* Read clear on read status register with the EP source of interrupt */ - int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK; - int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK; + /* Read clear on read status register with EP source of interrupt. */ + int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK; + int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK; - while(int8Status != 0u) - { - while(int17Status != 0u) + while (int8Status != 0u) { - if((int17Status & 1u) != 0u) /* If EpX interrupt present */ + while (int17Status != 0u) { - /* Read Endpoint Status Register */ - ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); - if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) && - (USBFS_inBufFull[ep] == 0u)) + if ((int17Status & 1u) != 0u) /* If EpX interrupt present. */ { - /* `#START EP_DMA_DONE_USER_CODE` Place your code here */ + /* Read Endpoint Status Register. */ + ep_status = USBFS_ARB_EP_BASE.arbEp[ep].epSr; - /* `#END` */ + if ((0u == (ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL)) && + (0u ==USBFS_inBufFull[ep])) + { + /* `#START EP_DMA_DONE_USER_CODE` Place your code here */ + + /* `#END` */ #ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK USBFS_EP_DMA_DONE_ISR_Callback(); - #endif /* USBFS_EP_DMA_DONE_ISR_CALLBACK */ + #endif /* (USBFS_EP_DMA_DONE_ISR_CALLBACK) */ - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u); - /* repeat 2 last bytes to prefetch endpoint area */ - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr), - USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT); - USBFS_LoadNextInEP(ep, 1); - /* Set Data ready status, This will generate DMA request */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + /* Transfer again 2 last bytes into pre-fetch endpoint area. */ + USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = 0u; + USBFS_ARB_EP_BASE.arbEp[ep].rwWa = (USBFS_DMA_BYTES_PER_BURST * ep) - USBFS_DMA_BYTES_REPEAT; + USBFS_LoadNextInEP(ep, 1u); + + /* Set Data ready status to generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[ep].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + } } + + ep++; + int17Status >>= 1u; + } + + int8Status >>= 1u; + + if (int8Status != 0u) + { + /* Prepare pointer for EP8. */ + ep = USBFS_EP8; + int17Status = int8Status & 0x01u; } - ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ - ep++; - int17Status >>= 1u; - } - int8Status >>= 1u; - if(int8Status != 0u) - { - /* Prepare pointer for EP8 */ - ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - ep = USBFS_EP8; - int17Status = int8Status & 0x01u; } + + /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK + USBFS_EP_DMA_DONE_ISR_ExitCallback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK) */ + } + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +#if (CY_PSOC4) + /*************************************************************************** + * Function Name: USBFS_IntrHandler + ************************************************************************//** + * + * Interrupt handler for Hi/Mid/Low ISRs. + * + * regCause - The cause register of interrupt. One of the three variants: + * USBFS_INTR_CAUSE_LO_REG - Low interrupts. + * USBFS_INTR_CAUSE_MED_REG - Med interrupts. + * USBFS_INTR_CAUSE_HI_REG - - High interrupts. + * + * + ***************************************************************************/ + CY_INLINE static void USBFS_IntrHandler(uint32 intrCause) + { + /* Array of pointers to component interrupt handlers. */ + static const cyisraddress USBFS_isrCallbacks[] = + { + + }; + + uint32 cbIdx = 0u; + + /* Check arbiter interrupt source first. */ + if (0u != (intrCause & USBFS_INTR_CAUSE_ARB_INTR)) + { + USBFS_isrCallbacks[USBFS_ARB_EP_INTR_NUM](); } - /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */ + /* Check all other interrupt sources (except arbiter and resume). */ + intrCause = (intrCause & USBFS_INTR_CAUSE_CTRL_INTR_MASK) | + ((intrCause & USBFS_INTR_CAUSE_EP1_8_INTR_MASK) >> + USBFS_INTR_CAUSE_EP_INTR_SHIFT); - /* `#END` */ + /* Call interrupt handlers for active interrupt sources. */ + while (0u != intrCause) + { + if (0u != (intrCause & 0x1u)) + { + USBFS_isrCallbacks[cbIdx](); + } - #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK - USBFS_EP_DMA_DONE_ISR_ExitCallback(); - #endif /* USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK */ + intrCause >>= 1u; + ++cbIdx; + } } -#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + + /*************************************************************************** + * Function Name: USBFS_INTR_HI_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the high group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_HI_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_HI_REG); + } + + /*************************************************************************** + * Function Name: USBFS_INTR_MED_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the medium group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_MED_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_MED_REG); + } + + /*************************************************************************** + * Function Name: USBFS_INTR_LO_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the low group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_LO_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_LO_REG); + } +#endif /* (CY_PSOC4) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c index dac538b..58b1752 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c @@ -1,37 +1,44 @@ -/******************************************************************************* -* File Name: USBFS_hid.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_hid.c +* \version 3.10 * -* Description: -* USB HID Class request handler. +* \brief +* This file contains the USB HID Class request handler. * * Related Document: * Device Class Definition for Human Interface Devices (HID) Version 1.11 * -* Note: -* ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" +#include "USBFS_hid.h" +#include "USBFS_pvt.h" + + #if defined(USBFS_ENABLE_HID_CLASS) -#include "USBFS_pvt.h" -#include "USBFS_hid.h" - - - /*************************************** * HID Variables ***************************************/ +/** This variable is initialized in the USBFS_InitComponent() API to the + * PROTOCOL_REPORT value. It is controlled by the host using the + * HID_SET_PROTOCOL request. The value is returned to the user code by the + * USBFS_GetProtocol() API.*/ +volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; -volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */ -volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */ +/** This variable controls the HID report rate. It is controlled by the host + * using the HID_SET_IDLE request and used by the USBFS_UpdateHIDTimer() API to + * reload timer.*/ +volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + +/** This variable contains the timer counter, which is decremented and reloaded + * by the USBFS_UpdateHIDTimer() API.*/ volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ @@ -46,18 +53,23 @@ volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device id /******************************************************************************* * Function Name: USBFS_UpdateHIDTimer -******************************************************************************** +****************************************************************************//** * -* Summary: -* Updates the HID report timer and reloads it if expired +* This function updates the HID Report idle timer and returns the status and +* reloads the timer if it expires. * -* Parameters: -* interface: Interface Number. +* \param interface Contains the interface number. * -* Return: -* status. +* \return +* Returns the state of the HID timer. Symbolic names and their associated values are given here: +* Return Value |Notes +* ---------------------------|------------------------------------------------ +* USBFS_IDLE_TIMER_EXPIRED | The timer expired. +* USBFS_IDLE_TIMER_RUNNING | The timer is running. +* USBFS_IDLE_TIMER_IDEFINITE | The report is sent when data or state changes. * -* Reentrant: +* +* \reentrant * No. * *******************************************************************************/ @@ -79,22 +91,20 @@ uint8 USBFS_UpdateHIDTimer(uint8 interface) } } - return(stat); + return((uint8)stat); } /******************************************************************************* * Function Name: USBFS_GetProtocol -******************************************************************************** +****************************************************************************//** * -* Summary: -* Returns the selected protocol value to the application +* This function returns the HID protocol value for the selected interface. * -* Parameters: -* interface: Interface Number. +* \param interface: Contains the interface number. * -* Return: -* Interface protocol. +* \return +* Returns the protocol value. * *******************************************************************************/ uint8 USBFS_GetProtocol(uint8 interface) @@ -105,33 +115,34 @@ uint8 USBFS_GetProtocol(uint8 interface) /******************************************************************************* * Function Name: USBFS_DispatchHIDClassRqst -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine dispatches class requests * -* Parameters: -* None. +* \return +* Results of HID Class request handling: +* - USBFS_TRUE - request was handled without errors +* - USBFS_FALSE - error occurs during handling of request * -* Return: -* requestHandled -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_DispatchHIDClassRqst(void) { uint8 requestHandled = USBFS_FALSE; - uint8 interfaceNumber; - interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) - { /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) + uint8 interfaceNumber = (uint8) USBFS_wIndexLoReg; + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) { case USBFS_GET_DESCRIPTOR: - if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) + if (USBFS_wValueHiReg == USBFS_DESCR_HID_CLASS) { USBFS_FindHidClassDecriptor(); if (USBFS_currentTD.count != 0u) @@ -139,7 +150,7 @@ uint8 USBFS_DispatchHIDClassRqst(void) requestHandled = USBFS_InitControlRead(); } } - else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) + else if (USBFS_wValueHiReg == USBFS_DESCR_HID_REPORT) { USBFS_FindReportDescriptor(); if (USBFS_currentTD.count != 0u) @@ -148,9 +159,11 @@ uint8 USBFS_DispatchHIDClassRqst(void) } } else - { /* requestHandled is initialezed as FALSE by default */ + { + /* Do not handle this request. */ } break; + case USBFS_HID_GET_REPORT: USBFS_FindReport(); if (USBFS_currentTD.count != 0u) @@ -161,15 +174,15 @@ uint8 USBFS_DispatchHIDClassRqst(void) case USBFS_HID_GET_IDLE: /* This function does not support multiple reports per interface*/ - /* Validate interfaceNumber and Report ID (should be 0) */ - if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) { USBFS_currentTD.count = 1u; USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; requestHandled = USBFS_InitControlRead(); } break; + case USBFS_HID_GET_PROTOCOL: /* Validate interfaceNumber */ if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) @@ -179,14 +192,16 @@ uint8 USBFS_DispatchHIDClassRqst(void) requestHandled = USBFS_InitControlRead(); } break; + default: /* requestHandled is initialized as FALSE by default */ break; } } - else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == - USBFS_RQST_DIR_H2D) - { /* Control Write */ - switch (CY_GET_REG8(USBFS_bRequest)) + else + { + /* Handle direction from host to device. */ + + switch (USBFS_bRequestReg) { case USBFS_HID_SET_REPORT: USBFS_FindReport(); @@ -195,13 +210,13 @@ uint8 USBFS_DispatchHIDClassRqst(void) requestHandled = USBFS_InitControlWrite(); } break; + case USBFS_HID_SET_IDLE: /* This function does not support multiple reports per interface */ - /* Validate interfaceNumber and Report ID (should be 0) */ - if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) { - USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); + USBFS_hidIdleRate[interfaceNumber] = (uint8)USBFS_wValueHiReg; /* With regards to HID spec: "7.2.4 Set_Idle Request" * Latency. If the current period has gone past the * newly proscribed time duration, then a report @@ -235,42 +250,36 @@ uint8 USBFS_DispatchHIDClassRqst(void) case USBFS_HID_SET_PROTOCOL: /* Validate interfaceNumber and protocol (must be 0 or 1) */ - if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && - (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg <= 1u)) { - USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); + USBFS_hidProtocol[interfaceNumber] = (uint8)USBFS_wValueLoReg; requestHandled = USBFS_InitNoDataControlTransfer(); } break; - default: /* requestHandled is initialized as FALSE by default */ + + default: + /* Unknown class request is not handled. */ break; } } - else - { /* requestHandled is initialized as FALSE by default */ - } - return(requestHandled); + return (requestHandled); } /******************************************************************************* * Function Name: USB_FindHidClassDescriptor -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine find Hid Class Descriptor pointer based on the Interface number * and Alternate setting then loads the currentTD structure with the address of * the buffer and the size. * The HID Class Descriptor resides inside the config descriptor. * -* Parameters: -* None. -* -* Return: +* \return * currentTD * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -281,19 +290,25 @@ void USBFS_FindHidClassDecriptor(void) uint8 interfaceN; pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - interfaceN = CY_GET_REG8(USBFS_wIndexLo); + + interfaceN = (uint8) USBFS_wIndexLoReg; /* Third entry in the LUT starts the Interface Table pointers */ /* Now use the request interface number*/ pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ pTmp = &pTmp[4u]; pDescr = (volatile uint8 *)pTmp->p_list; + /* The first byte contains the descriptor length */ USBFS_currentTD.count = *pDescr; USBFS_currentTD.pData = pDescr; @@ -302,21 +317,17 @@ void USBFS_FindHidClassDecriptor(void) /******************************************************************************* * Function Name: USB_FindReportDescriptor -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine find Hid Report Descriptor pointer based on the Interface * number, then loads the currentTD structure with the address of the buffer * and the size. * Hid Report Descriptor is located after IN/OUT/FEATURE reports. * -* Parameters: -* void -* -* Return: +* \return * currentTD * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -327,42 +338,44 @@ void USBFS_FindReportDescriptor(void) uint8 interfaceN; pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - interfaceN = CY_GET_REG8(USBFS_wIndexLo); + interfaceN = (uint8) USBFS_wIndexLoReg; + /* Third entry in the LUT starts the Interface Table pointers */ /* Now use the request interface number */ pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fourth entry in the LUT starts the Hid Report Descriptor */ pTmp = &pTmp[3u]; pDescr = (volatile uint8 *)pTmp->p_list; + /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ - USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]); + USBFS_currentTD.count = ((uint16)((uint16) pDescr[1u] << 8u) | pDescr[0u]); USBFS_currentTD.pData = &pDescr[2u]; } /******************************************************************************* * Function Name: USBFS_FindReport -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine sets up a transfer based on the Interface number, Report Type * and Report ID, then loads the currentTD structure with the address of the * buffer and the size. The caller has to decide if it is a control read or * control write. * -* Parameters: -* None. -* -* Return: +* \return * currentTD * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -370,41 +383,48 @@ void USBFS_FindReport(void) { const T_USBFS_LUT CYCODE *pTmp; T_USBFS_TD *pTD; - uint8 interfaceN; uint8 reportType; - + uint8 interfaceN; + /* `#START HID_FINDREPORT` Place custom handling here */ /* `#END` */ - #ifdef USBFS_FIND_REPORT_CALLBACK - USBFS_FindReport_Callback(); - #endif /* USBFS_FIND_REPORT_CALLBACK */ +#ifdef USBFS_FIND_REPORT_CALLBACK + USBFS_FindReport_Callback(); +#endif /* (USBFS_FIND_REPORT_CALLBACK) */ USBFS_currentTD.count = 0u; /* Init not supported condition */ pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - reportType = CY_GET_REG8(USBFS_wValueHi); - interfaceN = CY_GET_REG8(USBFS_wIndexLo); - /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */ + reportType = (uint8) USBFS_wValueHiReg; + interfaceN = (uint8) USBFS_wIndexLoReg; + + /* Third entry in the LUT Configuration Table starts the Interface Table pointers */ /* Now use the request interface number */ pTmp = &pTmp[interfaceN + 2u]; - /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/ + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; - if(interfaceN < USBFS_MAX_INTERFACES_NUMBER) + if (interfaceN < USBFS_MAX_INTERFACES_NUMBER) { /* Now use Alternate setting number */ pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Validate reportType to comply with "7.2.1 Get_Report Request" */ - if((reportType >= USBFS_HID_GET_REPORT_INPUT) && - (reportType <= USBFS_HID_GET_REPORT_FEATURE)) + if ((reportType >= USBFS_HID_GET_REPORT_INPUT) && + (reportType <= USBFS_HID_GET_REPORT_FEATURE)) { /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ pTmp = &pTmp[reportType - 1u]; - reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */ + + /* Get reportID */ + reportType = (uint8) USBFS_wValueLoReg; + /* Validate table support by the HID descriptor, compare table count with reportID */ - if(pTmp->c >= reportType) + if (pTmp->c >= reportType) { pTD = (T_USBFS_TD *) pTmp->p_list; pTD = &pTD[reportType]; /* select entry depend on report ID*/ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h old mode 100644 new mode 100755 index e802023..6b97fbb --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h @@ -1,15 +1,17 @@ -/******************************************************************************* -* File Name: USBFS_hid.h -* Version 2.80 +/***************************************************************************//** +* \file USBFS_hid.h +* \version 3.10 * -* Description: -* Header File for the USBFS component. Contains prototypes and constant values. +* \brief +* This file provides function prototypes and constants for the USBFS component +* HID class. * * Related Document: * Device Class Definition for Human Interface Devices (HID) Version 1.11 * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -18,22 +20,24 @@ #if !defined(CY_USBFS_USBFS_hid_H) #define CY_USBFS_USBFS_hid_H -#include "cytypes.h" - +#include "USBFS.h" /*************************************** * Prototypes of the USBFS_hid API. ***************************************/ - +/** +* \addtogroup group_hid +* @{ +*/ uint8 USBFS_UpdateHIDTimer(uint8 interface) ; -uint8 USBFS_GetProtocol(uint8 interface) ; - +uint8 USBFS_GetProtocol(uint8 interface) ; +/** @} hid */ /*************************************** *Renamed Functions for backward compatible ***************************************/ -#define USBFS_bGetProtocol USBFS_GetProtocol +#define USBFS_bGetProtocol USBFS_GetProtocol /*************************************** diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c index 5ea6b84..fe52d42 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c @@ -1,8 +1,8 @@ -/******************************************************************************* -* File Name: USBFS_midi.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_midi.c +* \version 3.10 * -* Description: +* \brief * MIDI Streaming request handler. * This file contains routines for sending and receiving MIDI * messages, and handles running status in both directions. @@ -12,20 +12,18 @@ * MIDI 1.0 Detailed Specification Document Version 4.2 * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" - -#if defined(USBFS_ENABLE_MIDI_STREAMING) - #include "USBFS_midi.h" #include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) /*************************************** * MIDI Constants @@ -60,29 +58,62 @@ * Global variables ***************************************/ + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + /** Input endpoint buffer pointer. This pointer is used as an index for the + * USBMIDI_midiInBuffer to write data. It is cleared to zero by the + * USBMIDI_MIDI_EP_Init() function.*/ volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ #else volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */ - volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + /** Contains the midi IN endpoint number, It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in MIDI + * APIs to send data to the host.*/ + volatile uint8 USBFS_midi_in_ep; + /** Input endpoint buffer with a length equal to MIDI IN EP Max Packet Size. + * This buffer is used to save and combine the data received from the UARTs, + * generated internally by USBMIDI_PutUsbMidiIn() function messages, or both. + * The USBMIDI_MIDI_IN_Service() function transfers the data from this buffer to the host.*/ uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /** Contains the midi OUT endpoint number. It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in + * MIDI APIs to receive data from the host.*/ volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + /** Output endpoint buffer with a length equal to MIDI OUT EP Max Packet Size. + * This buffer is used by the USBMIDI_MIDI_OUT_EP_Service() function to save + * the data received from the host. The received data is then parsed. The + * parsed data is transferred to the UARTs buffer and also used for internal + * processing by the USBMIDI_callbackLocalMidiEvent() function.*/ uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */ static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */ + /** The USBFS supports a maximum of two external Jacks. The two flag variables + * are used to represent the status of two external Jacks. These optional variables + * are allocated when External Mode is enabled. The following flags help to + * detect and generate responses for SysEx messages. The USBMIDI_MIDI2_InqFlags + * is optional and is not available when only one external Jack is configured. + * Flag | Description + * ------------------------------|--------------------------------------- + * USBMIDI_INQ_SYSEX_FLAG | Non-real-time SysEx message received. + * USBMIDI_INQ_IDENTITY_REQ_FLAG | Identity Request received. You should clear this bit when an Identity Reply message is generated. + * SysEX messages are intended for local device and shouldn't go out on the + * external MIDI jack, this flag indicates when a MIDI SysEx OUT message is + * in progress for the application */ volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */ static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */ + /** See description of \ref USBFS_MIDI1_InqFlags*/ volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ @@ -97,229 +128,206 @@ /* `#END` */ -/*************************************** -* Optional MIDI APIs -***************************************/ #if (USBFS_ENABLE_MIDI_API != 0u) - - /******************************************************************************* -* Function Name: USBFS_MIDI_EP_Init -******************************************************************************** +* Function Name: USBFS_MIDI_Init +****************************************************************************//** * -* Summary: * This function initializes the MIDI interface and UART(s) to be ready to * receive data from the PC and MIDI ports. * -* Parameters: -* None +* \globalvars * -* Return: -* None -* -* Global variables: -* USBFS_midiInBuffer: This buffer is used for saving and combining +* \ref USBFS_midiInBuffer: This buffer is used for saving and combining * the received data from UART(s) and(or) generated internally by * PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service() * function transfers the data from this buffer to the PC. -* USBFS_midiOutBuffer: This buffer is used by the -* USBFS_MIDI_OUT_EP_Service() function for saving the received +* +* \ref USBFS_midiOutBuffer: This buffer is used by the +* USBFS_MIDI_OUT_Service() function for saving the received * from the PC data, then the data are parsed and transferred to UART(s) * buffer and to the internal processing by the -* USBFS_callbackLocalMidiEvent function. -* USBFS_midi_out_ep: Used as an OUT endpoint number. -* USBFS_midi_in_ep: Used as an IN endpoint number. -* USBFS_midiInPointer: Initialized to zero. * -* Reentrant: +* \ref USBFS_callbackLocalMidiEvent function. +* +* \ref USBFS_midi_out_ep: Used as an OUT endpoint number. +* +* \ref USBFS_midi_in_ep: Used as an IN endpoint number. +* +* \ref USBFS_midiInPointer: Initialized to zero. +* +* \sideeffect +* The priority of the UART RX ISR should be higher than UART TX ISR. To do +* that this function changes the priority of the UARTs TX and RX interrupts. +* +* \reentrant * No * *******************************************************************************/ -void USBFS_MIDI_EP_Init(void) +void USBFS_MIDI_Init(void) { +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + USBFS_midiInPointer = 0u; +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - USBFS_midiInPointer = 0u; - #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ - - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - /* Init DMA configurations for IN EP*/ - USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, - USBFS_MIDI_IN_BUFF_SIZE); - - #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ - #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - /* Init DMA configurations for OUT EP*/ - (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, - USBFS_MIDI_OUT_BUFF_SIZE); - #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ - #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */ + /* Provide buffer for IN endpoint. */ + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + USBFS_MIDI_IN_BUFF_SIZE); + #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) - USBFS_EnableOutEP(USBFS_midi_out_ep); + /* Provide buffer for OUT endpoint. */ + (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, + USBFS_MIDI_OUT_BUFF_SIZE); #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ - - /* Initialize the MIDI port(s) */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - USBFS_MIDI_Init(); - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ -} +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + USBFS_EnableOutEP(USBFS_midi_out_ep); +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + + /* Initialize the MIDI port(s) */ +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + USBFS_MIDI_InitInterface(); +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ +} +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) /******************************************************************************* - * Function Name: USBFS_MIDI_OUT_EP_Service - ******************************************************************************** + * Function Name: USBFS_MIDI_OUT_Service + ****************************************************************************//** * - * Summary: - * Services the USB MIDI OUT endpoints. - * This function is called from OUT EP ISR. It transfers the received from PC - * data to the external MIDI port(UART TX buffer) and calls the - * USBFS_callbackLocalMidiEvent() function to internal process - * of the MIDI data. - * This function is blocked by UART, if not enough space is available in UART - * TX buffer. Therefore it is recommended to use large UART TX buffer size. + * This function services the traffic from the USBMIDI OUT endpoint and + * sends the data to the MIDI output ports (TX UARTs). It is blocked by the + * UART when not enough space is available in the UART TX buffer. + * This function is automatically called from OUT EP ISR in DMA with + * Automatic Memory Management mode. In Manual and DMA with Manual EP + * Management modes you must call it from the main foreground task. * - * Parameters: - * None + * \globalvars * - * Return: - * None + * \ref USBFS_midiOutBuffer: Used as temporary buffer between USB + * internal memory and UART TX buffer. * - * Global variables: - * USBFS_midiOutBuffer: Used as temporary buffer between USB internal - * memory and UART TX buffer. - * USBFS_midi_out_ep: Used as an OUT endpoint number. + * \ref USBFS_midi_out_ep: Used as an OUT endpoint number. * - * Reentrant: + * \reentrant * No * *******************************************************************************/ - void USBFS_MIDI_OUT_EP_Service(void) + void USBFS_MIDI_OUT_Service(void) { - #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 - uint16 outLength; - uint16 outPointer; - #else - uint8 outLength; - uint8 outPointer; - #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */ + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + uint16 outLength; + uint16 outPointer; + #else + uint8 outLength; + uint8 outPointer; + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ - uint8 dmaState = 0u; - - /* Service the USB MIDI output endpoint */ - if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL) + /* Service the USB MIDI output endpoint. */ + if (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep)) { - #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256) - outLength = USBFS_GetEPCount(USBFS_midi_out_ep); + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + outLength = USBFS_GetEPCount(USBFS_midi_out_ep); + #else + outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, outLength); #else - outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); + outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, (uint16) outLength); #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) - outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, - USBFS_midiOutBuffer, outLength); - #else - outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, - USBFS_midiOutBuffer, (uint16)outLength); - #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep)) + { + } - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - do /* wait for DMA transfer complete */ - { - (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState); - } - while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u); - #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */ - - #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */ - - if(dmaState != 0u) - { - /* Suppress compiler warning */ - } + /* Enable OUT endpoint for communication with host. */ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ if (outLength >= USBFS_EVENT_LENGTH) { outPointer = 0u; while (outPointer < outLength) { - /* In some OS OUT packet could be appended by nulls which could be skipped */ + /* In some OS OUT packet could be appended by nulls which could be skipped. */ if (USBFS_midiOutBuffer[outPointer] == 0u) { break; } - /* Route USB MIDI to the External connection */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == - USBFS_MIDI_CABLE_00) - { - USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); - } - else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == - USBFS_MIDI_CABLE_01) - { - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); - #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ - } - else - { - /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ - /* `#END` */ + /* Route USB MIDI to the External connection */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_00) + { + USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + } + else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_01) + { + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + } + else + { + /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ - #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK - USBFS_MIDI_OUT_EP_Service_Callback(); - #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */ - } - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + /* `#END` */ + + #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK + USBFS_MIDI_OUT_EP_Service_Callback(); + #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */ + } + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ /* Process any local MIDI output functions */ - USBFS_callbackLocalMidiEvent( - USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, - &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); + USBFS_callbackLocalMidiEvent(USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, + &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); outPointer += USBFS_EVENT_LENGTH; } } - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* Enable Out EP*/ - USBFS_EnableOutEP(USBFS_midi_out_ep); - #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Enable OUT endpoint for communiation. */ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ } } +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ -#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ #if (USBFS_MIDI_IN_BUFF_SIZE > 0) - - /******************************************************************************* * Function Name: USBFS_MIDI_IN_EP_Service - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Services the USB MIDI IN endpoint. Non-blocking. * Checks that previous packet was processed by HOST, otherwise service the * input endpoint on the subsequent call. It is called from the * USBFS_MIDI_IN_Service() and from the * USBFS_PutUsbMidiIn() function. * - * Parameters: - * None - * - * Return: - * None - * - * Global variables: + * \globalvars * USBFS_midi_in_ep: Used as an IN endpoint number. * USBFS_midiInBuffer: Function loads the data from this buffer to * the USB IN endpoint. * USBFS_midiInPointer: Cleared to zero when data are sent. * - * Reentrant: + * \reentrant * No * *******************************************************************************/ @@ -331,18 +339,17 @@ void USBFS_MIDI_EP_Init(void) { if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING) { - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, - (uint16)USBFS_midiInPointer); - #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ - /* rearm IN EP */ + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer); - #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */ + #else + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + (uint16) USBFS_midiInPointer); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */ - #if(USBFS_EP_MM == USBFS__EP_MANUAL) + #if (USBFS_EP_MANAGEMENT_MANUAL) USBFS_midiInPointer = 0u; - #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ } } } @@ -350,28 +357,26 @@ void USBFS_MIDI_EP_Init(void) /******************************************************************************* * Function Name: USBFS_MIDI_IN_Service - ******************************************************************************** + ****************************************************************************//** * - * Summary: - * Services the traffic from the MIDI input ports (RX UART) and prepare data - * in USB MIDI IN endpoint buffer. + * This function services the traffic from the MIDI input ports (RX UART) + * and prepare data in USB MIDI IN endpoint buffer. * Calls the USBFS_MIDI_IN_EP_Service() function to sent the * data from buffer to PC. Non-blocking. Should be called from main foreground * task. * This function is not protected from the reentrant calls. When it is required * to use this function in UART RX ISR to guaranty low latency, care should be * taken to protect from reentrant calls. + * In PSoC 3, if this function is called from an ISR, you must declare this + * function as re-entrant so that different variable storage space is + * created by the compiler. This is automatically taken care for PSoC 4 and + * PSoC 5LP devices by the compiler. * - * Parameters: - * None + * \globalvars * - * Return: - * None - * - * Global variables: * USBFS_midiInPointer: Cleared to zero when data are sent. * - * Reentrant: + * \reentrant * No * *******************************************************************************/ @@ -380,86 +385,92 @@ void USBFS_MIDI_EP_Init(void) /* Service the MIDI UART inputs until either both receivers have no more * events or until the input endpoint buffer fills up. */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) uint8 m1 = 0u; uint8 m2 = 0u; + + if (0u == USBFS_midiInPointer) + { do { - if (USBFS_midiInPointer <= - (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) { /* Check MIDI1 input port for a complete event */ m1 = USBFS_MIDI1_GetEvent(); if (m1 != 0u) { USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0], - USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); + USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); } } #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - if (USBFS_midiInPointer <= - (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) { /* Check MIDI2 input port for a complete event */ m2 = USBFS_MIDI2_GetEvent(); if (m2 != 0u) { USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0], - USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); + USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); } } #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ - - }while( (USBFS_midiInPointer <= - (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) && - ((m1 != 0u) || (m2 != 0u)) ); - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + } + while((USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) && + ((m1 != 0u) || (m2 != 0u))); + } + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ /* Service the USB MIDI input endpoint */ USBFS_MIDI_IN_EP_Service(); } - /******************************************************************************* + /*************************************************************************** * Function Name: USBFS_PutUsbMidiIn - ******************************************************************************** + ************************************************************************//** * - * Summary: - * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are - * MIDI input messages to the host. This function is only used if the device - * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function - * should additionally be called to send the message from local buffer to - * IN endpoint. + * This function puts one MIDI message into the USB MIDI In endpoint buffer. + * This is a MIDI input message to the host. This function is used only if + * the device has internal MIDI input functionality. + * The USBFS_MIDI_IN_Service() function should also be called to + * send the message from local buffer to the IN endpoint. * - * Parameters: - * ic: 0 = No message (should never happen) - * 1 - 3 = Complete MIDI message in midiMsg - * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in - * midiMsg. The length is limited by the max BULK EP size(64) - * MIDI_SYSEX = Start or continuation of SysEx message - * (put event bytes in midiMsg buffer) - * MIDI_EOSEX = End of SysEx message - * (put event bytes in midiMsg buffer) - * MIDI_TUNEREQ = Tune Request message (single byte system common msg) - * 0xf8 - 0xff = Single byte real-time message - * midiMsg: pointer to MIDI message. - * cable: cable number. + * \param ic: The length of the MIDI message or command is described on the + * following table. + * Value | Description + * ---------------|--------------------------------------------------------- + * 0 | No message (should never happen) + * 1 - 3 | Complete MIDI message in midiMsg + * 3 IN EP LENGTH | Complete SySEx message(without EOSEX byte) in midiMsg. The length is limited by the max BULK EP size(64) + * MIDI_SYSEX | Start or continuation of SysEx message (put event bytes in midiMsg buffer) + * MIDI_EOSEX | End of SysEx message (put event bytes in midiMsg buffer) + * MIDI_TUNEREQ | Tune Request message (single byte system common msg) + * 0xF8 - 0xFF | Single byte real-time message * - * Return: - * USBFS_TRUE if error. - * USBFS_FALSE if success. + * \param midiMsg: pointer to MIDI message. + * \param cable: cable number. * - * Global variables: - * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data. - * USBFS_midiInPointer: Checked this variable to see if there is - * enough free space in the IN endpoint buffer. If buffer is full, initiate - * sending to PC. + * \return + * Return Value | Description + * ----------------------|----------------------------------------- + * USBFS_TRUE | Host is not ready to receive this message + * USBFS_FALSE | Success transfer * - * Reentrant: + * \globalvars + * + * \ref USBFS_midi_in_ep: MIDI IN endpoint number used for + * sending data. + * + * \ref USBFS_midiInPointer: Checked this variable to see if + * there is enough free space in the IN endpoint buffer. If buffer is + * full, initiate sending to PC. + * + * \reentrant * No * - *******************************************************************************/ + ***************************************************************************/ uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) { @@ -467,18 +478,19 @@ void USBFS_MIDI_EP_Init(void) uint8 msgIndex; /* Protect PrepareInBuffer() function from concurrent calls */ - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - MIDI1_UART_DisableRxInt(); - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - MIDI2_UART_DisableRxInt(); - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_DisableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_DisableRxInt(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ if (USBFS_midiInPointer > (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) { USBFS_MIDI_IN_EP_Service(); } + if (USBFS_midiInPointer <= (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) { @@ -487,20 +499,25 @@ void USBFS_MIDI_EP_Init(void) USBFS_PrepareInBuffer(ic, midiMsg, ic, cable); } else - { /* Only SysEx message is greater than 4 bytes */ + { + /* Only SysEx message is greater than 4 bytes */ msgIndex = 0u; + do { USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex], USBFS_EVENT_BYTE3, cable); + ic -= USBFS_EVENT_BYTE3; msgIndex += USBFS_EVENT_BYTE3; + if (USBFS_midiInPointer > (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) { USBFS_MIDI_IN_EP_Service(); - if(USBFS_midiInPointer > - (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) { /* Error condition. HOST is not ready to receive this packet. */ retError = USBFS_TRUE; @@ -508,9 +525,9 @@ void USBFS_MIDI_EP_Init(void) } } } - while(ic > USBFS_EVENT_BYTE3); + while (ic > USBFS_EVENT_BYTE3); - if(retError == USBFS_FALSE) + if (retError == USBFS_FALSE) { USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable); } @@ -522,12 +539,12 @@ void USBFS_MIDI_EP_Init(void) retError = USBFS_TRUE; } - #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - MIDI1_UART_EnableRxInt(); - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - MIDI2_UART_EnableRxInt(); - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ - #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_EnableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_EnableRxInt(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ return (retError); } @@ -535,14 +552,12 @@ void USBFS_MIDI_EP_Init(void) /******************************************************************************* * Function Name: USBFS_PrepareInBuffer - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Builds a USB MIDI event in the input endpoint buffer at the current pointer. * Puts one MIDI message into the USB MIDI In endpoint buffer. * - * Parameters: - * ic: 0 = No message (should never happen) + * \param ic: 0 = No message (should never happen) * 1 - 3 = Complete MIDI message at pMdat[0] * MIDI_SYSEX = Start or continuation of SysEx message * (put eventLen bytes in buffer) @@ -552,21 +567,18 @@ void USBFS_MIDI_EP_Init(void) * MIDI_TUNEREQ = Tune Request message (single byte system common msg) * 0xf8 - 0xff = Single byte real-time message * - * srcBuff: pointer to MIDI data - * eventLen: number of bytes in MIDI event - * cable: MIDI source port number + * \param srcBuff: pointer to MIDI data + * \param eventLen: number of bytes in MIDI event + * \param cable: MIDI source port number * - * Return: - * None - * - * Global variables: + * \globalvars * USBFS_midiInBuffer: This buffer is used for saving and combine the * received from UART(s) and(or) generated internally by * USBFS_PutUsbMidiIn() function messages. * USBFS_midiInPointer: Used as an index for midiInBuffer to * write data. * - * Reentrant: + * \reentrant * No * *******************************************************************************/ @@ -674,87 +686,80 @@ void USBFS_MIDI_EP_Init(void) } } -#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */ +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ /* The implementation for external serial input and output connections * to route USB MIDI data to and from those connections. */ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - - /******************************************************************************* - * Function Name: USBFS_MIDI_Init - ******************************************************************************** + * Function Name: USBFS_MIDI_InitInterface + ****************************************************************************//** * - * Summary: * Initializes MIDI variables and starts the UART(s) hardware block(s). * - * Parameters: - * None - * - * Return: - * None - * - * Side Effects: + * \sideeffect * Change the priority of the UART(s) TX interrupts to be higher than the * default EP ISR priority. * - * Global variables: + * \globalvars * USBFS_MIDI_Event: initialized to zero. * USBFS_MIDI_TxRunStat: initialized to zero. * *******************************************************************************/ - void USBFS_MIDI_Init(void) + void USBFS_MIDI_InitInterface(void) { - USBFS_MIDI1_Event.length = 0u; - USBFS_MIDI1_Event.count = 0u; - USBFS_MIDI1_Event.size = 0u; + USBFS_MIDI1_Event.length = 0u; + USBFS_MIDI1_Event.count = 0u; + USBFS_MIDI1_Event.size = 0u; USBFS_MIDI1_Event.runstat = 0u; - USBFS_MIDI1_TxRunStat = 0u; - USBFS_MIDI1_InqFlags = 0u; + USBFS_MIDI1_TxRunStat = 0u; + USBFS_MIDI1_InqFlags = 0u; + /* Start UART block */ MIDI1_UART_Start(); + /* Change the priority of the UART TX and RX interrupt */ CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); - #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - USBFS_MIDI2_Event.length = 0u; - USBFS_MIDI2_Event.count = 0u; - USBFS_MIDI2_Event.size = 0u; - USBFS_MIDI2_Event.runstat = 0u; - USBFS_MIDI2_TxRunStat = 0u; - USBFS_MIDI2_InqFlags = 0u; - /* Start second UART block */ - MIDI2_UART_Start(); - /* Change the priority of the UART TX interrupt */ - CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); - CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); - #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/ + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_Event.length = 0u; + USBFS_MIDI2_Event.count = 0u; + USBFS_MIDI2_Event.size = 0u; + USBFS_MIDI2_Event.runstat = 0u; + USBFS_MIDI2_TxRunStat = 0u; + USBFS_MIDI2_InqFlags = 0u; + + /* Start second UART block */ + MIDI2_UART_Start(); + + /* Change the priority of the UART TX interrupt */ + CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */ /* `#END` */ - #ifdef USBFS_MIDI_INIT_CALLBACK - USBFS_MIDI_Init_Callback(); - #endif /* USBFS_MIDI_INIT_CALLBACK */ + #ifdef USBFS_MIDI_INIT_CALLBACK + USBFS_MIDI_Init_Callback(); + #endif /* (USBFS_MIDI_INIT_CALLBACK) */ } /******************************************************************************* * Function Name: USBFS_ProcessMidiIn - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Processes one byte of incoming MIDI data. * - * Parameters: * mData = current MIDI input data byte * *rxStat = pointer to a MIDI_RX_STATUS structure * - * Return: + * \return * 0, if no complete message * 1 - 4, if message complete * MIDI_SYSEX, if start or continuation of system exclusive @@ -891,7 +896,7 @@ void USBFS_MIDI_EP_Init(void) break; case USBFS_MIDI_PROGRAM_CHANGE: case USBFS_MIDI_CHANNEL_PRESSURE: - rxStat->size =rxStat->count; + rxStat->size = rxStat->count; rxStat->count = 0u; midiReturn = rxStat->size; break; @@ -910,23 +915,19 @@ void USBFS_MIDI_EP_Init(void) /******************************************************************************* * Function Name: USBFS_MIDI1_GetEvent - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Checks for incoming MIDI data, calls the MIDI event builder if so. * Returns either empty or with a complete event. * - * Parameters: - * None - * - * Return: + * \return * 0, if no complete message * 1 - 4, if message complete * MIDI_SYSEX, if start or continuation of system exclusive * MIDI_EOSEX, if end of system exclusive * 0xf8 - 0xff, if single byte real time message * - * Global variables: + * \globalvars * USBFS_MIDI1_Event: RX status structure used to parse received * data. * @@ -948,12 +949,13 @@ void USBFS_MIDI_EP_Init(void) /* Read buffer loop condition to the local variable */ rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; - if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + if ((MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) { /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) CyIntDisable(MIDI1_UART_RX_VECT_NUM); #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + rxBufferRead = MIDI1_UART_rxBufferRead; #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) rxBufferWrite = MIDI1_UART_rxBufferWrite; @@ -976,23 +978,25 @@ void USBFS_MIDI_EP_Init(void) rxData = MIDI1_UART_rxBuffer[rxBufferRead]; /* Increment pointer with a wrap */ rxBufferRead++; - if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) + if (rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) { rxBufferRead = 0u; } + /* If loop condition was set - update real read buffer pointer * to avoid overflow status */ - if(rxBufferLoopDetect != 0u ) + if (rxBufferLoopDetect != 0u ) { MIDI1_UART_rxBufferLoopDetect = 0u; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI1_UART_RX_VECT_NUM); - #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + MIDI1_UART_rxBufferRead = rxBufferRead; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI1_UART_RX_VECT_NUM); - #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ } msgRtn = USBFS_ProcessMidiIn(rxData, @@ -1005,13 +1009,14 @@ void USBFS_MIDI_EP_Init(void) /* Finally, update the real output pointer, then return with * an indication as to whether there's a complete message in the buffer. */ - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI1_UART_RX_VECT_NUM); - #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ - MIDI1_UART_rxBufferRead = rxBufferRead; - #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI1_UART_RX_VECT_NUM); - #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ } return (msgRtn); @@ -1020,19 +1025,14 @@ void USBFS_MIDI_EP_Init(void) /******************************************************************************* * Function Name: USBFS_MIDI1_ProcessUsbOut - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Process a USB MIDI output event. * Puts data into the MIDI TX output buffer. * - * Parameters: - * *epBuf: pointer on MIDI event. + * \param *epBuf: pointer on MIDI event. * - * Return: - * None - * - * Global variables: + * \globalvars * USBFS_MIDI1_TxRunStat: This variable used to save the MIDI * status byte and skip to send the repeated status byte in subsequent event. * USBFS_MIDI1_InqFlags: The following flags are set when SysEx @@ -1054,21 +1054,23 @@ void USBFS_MIDI_EP_Init(void) /* `#END` */ - #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK - USBFS_MIDI1_ProcessUsbOut_EntryCallback(); - #endif /* USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK */ + #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK + USBFS_MIDI1_ProcessUsbOut_EntryCallback(); + #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK) */ cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; - if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + + if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) { len = USBFS_MIDI_SIZE[cmd]; i = USBFS_EVENT_BYTE1; /* Universal System Exclusive message parsing */ - if(cmd == USBFS_SYSEX) + if (cmd == USBFS_SYSEX) { - if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && - (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) - { /* Non-Real Time SySEx starts */ + if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { + /* Non-Real Time SySEx starts */ USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG; } else @@ -1076,23 +1078,24 @@ void USBFS_MIDI_EP_Init(void) USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; } } - else if(cmd == USBFS_SYSEX_ENDS_WITH1) + else if (cmd == USBFS_SYSEX_ENDS_WITH1) { USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; } - else if(cmd == USBFS_SYSEX_ENDS_WITH2) + else if (cmd == USBFS_SYSEX_ENDS_WITH2) { USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; } - else if(cmd == USBFS_SYSEX_ENDS_WITH3) + else if (cmd == USBFS_SYSEX_ENDS_WITH3) { /* Identify Request support */ - if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + if ((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) { USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; - if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && - (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) - { /* Set the flag about received the Identity Request. + if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { + /* Set the flag about received the Identity Request. * The Identity Reply message may be send by user code. */ USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; @@ -1102,28 +1105,34 @@ void USBFS_MIDI_EP_Init(void) else /* Do nothing for other command */ { } + /* Running Status for Voice and Mode messages only. */ - if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + if ((cmd >= USBFS_NOTE_OFF) && (cmd <= USBFS_PITCH_BEND_CHANGE)) { - if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) - { /* Skip the repeated Status byte */ + if (USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { + /* Skip the repeated Status byte */ i++; } else - { /* Save Status byte for next event */ + { + /* Save Status byte for next event */ USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; } } else - { /* Clear Running Status */ + { + /* Clear Running Status */ USBFS_MIDI1_TxRunStat = 0u; } + /* Puts data into the MIDI TX output buffer.*/ do { MIDI1_UART_PutChar(epBuf[i]); i++; - } while (i <= len); + } + while (i <= len); } /* User code is required at the end of the procedure */ @@ -1131,34 +1140,28 @@ void USBFS_MIDI_EP_Init(void) /* `#END` */ - #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK - USBFS_MIDI1_ProcessUsbOut_ExitCallback(); - #endif /* USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK */ + #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK + USBFS_MIDI1_ProcessUsbOut_ExitCallback(); + #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK) */ } #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - - /******************************************************************************* * Function Name: USBFS_MIDI2_GetEvent - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Checks for incoming MIDI data, calls the MIDI event builder if so. * Returns either empty or with a complete event. * - * Parameters: - * None - * - * Return: + * \return * 0, if no complete message * 1 - 4, if message complete * MIDI_SYSEX, if start or continuation of system exclusive * MIDI_EOSEX, if end of system exclusive * 0xf8 - 0xff, if single byte real time message * - * Global variables: + * \globalvars * USBFS_MIDI2_Event: RX status structure used to parse received * data. * @@ -1167,6 +1170,7 @@ void USBFS_MIDI_EP_Init(void) { uint8 msgRtn = 0u; uint8 rxData; + #if (MIDI2_UART_RXBUFFERSIZE >= 256u) uint16 rxBufferRead; #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */ @@ -1211,19 +1215,21 @@ void USBFS_MIDI_EP_Init(void) { rxBufferRead = 0u; } + /* If loop condition was set - update real read buffer pointer * to avoid overflow status */ - if(rxBufferLoopDetect != 0u ) + if (rxBufferLoopDetect != 0u) { MIDI2_UART_rxBufferLoopDetect = 0u; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI2_UART_RX_VECT_NUM); - #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + MIDI2_UART_rxBufferRead = rxBufferRead; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI2_UART_RX_VECT_NUM); - #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ } msgRtn = USBFS_ProcessMidiIn(rxData, @@ -1236,13 +1242,14 @@ void USBFS_MIDI_EP_Init(void) /* Finally, update the real output pointer, then return with * an indication as to whether there's a complete message in the buffer. */ - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntDisable(MIDI2_UART_RX_VECT_NUM); - #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + MIDI2_UART_rxBufferRead = rxBufferRead; - #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) - CyIntEnable(MIDI2_UART_RX_VECT_NUM); - #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ } return (msgRtn); @@ -1251,19 +1258,14 @@ void USBFS_MIDI_EP_Init(void) /******************************************************************************* * Function Name: USBFS_MIDI2_ProcessUsbOut - ******************************************************************************** + ****************************************************************************//** * - * Summary: * Process a USB MIDI output event. * Puts data into the MIDI TX output buffer. * - * Parameters: - * *epBuf: pointer on MIDI event. + * \param *epBuf: pointer on MIDI event. * - * Return: - * None - * - * Global variables: + * \globalvars * USBFS_MIDI2_TxRunStat: This variable used to save the MIDI * status byte and skip to send the repeated status byte in subsequent event. * USBFS_MIDI2_InqFlags: The following flags are set when SysEx @@ -1285,21 +1287,24 @@ void USBFS_MIDI_EP_Init(void) /* `#END` */ - #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK - USBFS_MIDI2_ProcessUsbOut_EntryCallback(); - #endif /* USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK */ + #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK + USBFS_MIDI2_ProcessUsbOut_EntryCallback(); + #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK) */ cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; - if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + + if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) { len = USBFS_MIDI_SIZE[cmd]; i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ if(cmd == USBFS_SYSEX) { if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) - { /* SySEx starts */ + { + /* SySEx starts */ USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG; } else @@ -1318,9 +1323,10 @@ void USBFS_MIDI_EP_Init(void) else if(cmd == USBFS_SYSEX_ENDS_WITH3) { /* Identify Request support */ - if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + if ((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) { USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) { /* Set the flag about received the Identity Request. @@ -1333,10 +1339,11 @@ void USBFS_MIDI_EP_Init(void) else /* Do nothing for other command */ { } + /* Running Status for Voice and Mode messages only. */ - if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + if ((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) { - if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + if (USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) { /* Skip the repeated Status byte */ i++; } @@ -1349,12 +1356,14 @@ void USBFS_MIDI_EP_Init(void) { /* Clear Running Status */ USBFS_MIDI2_TxRunStat = 0u; } + /* Puts data into the MIDI TX output buffer.*/ do { MIDI2_UART_PutChar(epBuf[i]); i++; - } while (i <= len); + } + while (i <= len); } /* User code is required at the end of the procedure */ @@ -1362,9 +1371,9 @@ void USBFS_MIDI_EP_Init(void) /* `#END` */ - #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK - USBFS_MIDI2_ProcessUsbOut_ExitCallback(); - #endif /* USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK */ + #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK + USBFS_MIDI2_ProcessUsbOut_ExitCallback(); + #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK) */ } #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ @@ -1376,7 +1385,7 @@ void USBFS_MIDI_EP_Init(void) /* `#END` */ -#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */ +#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h old mode 100644 new mode 100755 index ad6e5d7..34ed83d --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h @@ -1,17 +1,18 @@ -/******************************************************************************* -* File Name: USBFS_midi.h -* Version 2.80 +/***************************************************************************//** +* \file USBFS_midi.h +* \version 3.10 * -* Description: -* Header File for the USBFS MIDI module. -* Contains prototypes and constant values. +* \brief +* This file provides function prototypes and constants for the USBFS component +* MIDI class support. * * Related Document: * Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0 * MIDI 1.0 Detailed Specification Document Version 4.2 * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -20,33 +21,106 @@ #if !defined(CY_USBFS_USBFS_midi_H) #define CY_USBFS_USBFS_midi_H -#include "cytypes.h" #include "USBFS.h" +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_ENABLE_MIDI_API (0u != (1u)) +#define USBFS_MIDI_EXT_MODE (0u) + + +/* Number of external interfaces (UARTs). */ +#define USBFS_ONE_EXT_INTRF (0x01u) +#define USBFS_TWO_EXT_INTRF (0x02u) + +#define USBFS_ISR_SERVICE_MIDI_OUT \ + ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_OUT_BUFF_SIZE > 0) && \ + (USBFS_EP_MANAGEMENT_DMA_AUTO)) + +#define USBFS_ISR_SERVICE_MIDI_IN \ + ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + + +/*************************************** +* External References +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + #include "MIDI1_UART.h" +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + #include "MIDI2_UART.h" +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + /*************************************** * Data Structure Definition ***************************************/ /* The following structure is used to hold status information for - building and parsing incoming MIDI messages. */ +* building and parsing incoming MIDI messages. +*/ typedef struct { uint8 length; /* expected length */ uint8 count; /* current byte count */ uint8 size; /* complete size */ uint8 runstat; /* running status */ - uint8 msgBuff[4]; /* message buffer */ + uint8 msgBuff[4u]; /* message buffer */ } USBFS_MIDI_RX_STATUS; +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_midi +* @{ +*/ +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + void USBFS_MIDI_Init(void) ; + + #if (USBFS_MIDI_IN_BUFF_SIZE > 0u) + void USBFS_MIDI_IN_Service(void) ; + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) ; + #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0u) */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0u) + void USBFS_MIDI_OUT_Service(void) ; + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0u) */ +#endif /* (USBFS_ENABLE_MIDI_API != 0u) */ + + +/******************************************************************************* +* Callback Function Prototypes +*******************************************************************************/ + +/******************************************************************************* +* Function Name: USBFS_callbackLocalMidiEvent +****************************************************************************//** +* +* This is a callback function that locally processes data received from the PC +* in main.c. You should implement this function if you want to use it. It is +* called from the USB output processing routine for each MIDI output event +* processed (decoded) from the output endpoint buffer. +* +* \param cable: Cable number +* +* \param midiMsg: Pointer to the 3-byte MIDI message +* +* +***************************************************************************/ +void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) + ; +/** @} midi */ + /*************************************** * MIDI Constants. ***************************************/ -#define USBFS_ONE_EXT_INTRF (0x01u) -#define USBFS_TWO_EXT_INTRF (0x02u) - /* Flag definitions for use with MIDI device inquiry */ #define USBFS_INQ_SYSEX_FLAG (0x01u) #define USBFS_INQ_IDENTITY_REQ_FLAG (0x02u) @@ -102,104 +176,102 @@ typedef struct /* MIDI Universal System Exclusive defines */ #define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu) #define USBFS_MIDI_SYSEX_REALTIME (0x7Fu) + /* ID of target device */ #define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu) + /* Sub-ID#1*/ #define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u) #define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u) + /* Sub-ID#2*/ #define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u) #define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u) #define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u) #define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u) -#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) -#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) - -#define USBFS_ISR_SERVICE_MIDI_OUT \ - ( (USBFS_ENABLE_MIDI_API != 0u) && \ - (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO)) -#define USBFS_ISR_SERVICE_MIDI_IN \ - ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) ) +/* UART TX and RX interrupt priority. */ +#if (CY_PSOC4) + #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x01u) + #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x02u) +#else + #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) + #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) +#endif /* (CYPSOC4) */ /*************************************** -* External function references -***************************************/ - -void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) - ; - - -/*************************************** -* External references -***************************************/ - -#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - #include "MIDI1_UART.h" -#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ -#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - #include "MIDI2_UART.h" -#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - #include -#endif /* USBFS_EP_MM */ - - -/*************************************** -* Private function prototypes +* Private Function Prototypes ***************************************/ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) - ; + ; #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - void USBFS_MIDI_Init(void) ; + void USBFS_MIDI_InitInterface(void) ; uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) ; - uint8 USBFS_MIDI1_GetEvent(void) ; - void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) - ; + uint8 USBFS_MIDI1_GetEvent(void) ; + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + ; #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - uint8 USBFS_MIDI2_GetEvent(void) ; - void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) - ; - #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + uint8 USBFS_MIDI2_GetEvent(void) ; + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + ; + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ /*************************************** -* External data references +* Vars with External Linkage ***************************************/ #if defined(USBFS_ENABLE_MIDI_STREAMING) #if (USBFS_MIDI_IN_BUFF_SIZE > 0) #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) +/** +* \addtogroup group_midi +* @{ +*/ extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ +/** @} midi*/ #else extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ - #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */ + #endif /* (USBFS_MIDI_IN_BUFF_SIZE >=256) */ +/** +* \addtogroup group_midi +* @{ +*/ extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ -#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ -#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) - extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) - extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ - #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ -#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ - -#endif /* USBFS_ENABLE_MIDI_STREAMING */ + extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ +/** @} midi */ +#endif /* (USBFS_ENABLE_MIDI_STREAMING) */ -#endif /* CY_USBFS_USBFS_midi_H */ +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +#define USBFS_MIDI_EP_Init USBFS_MIDI_Init +#define USBFS_MIDI_OUT_EP_Service USBFS_MIDI_OUT_Service + +#endif /* (CY_USBFS_USBFS_midi_H) */ /* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c new file mode 100755 index 0000000..20a9a86 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c @@ -0,0 +1,150 @@ +/***************************************************************************//** +* \file USBFS_cdc.c +* \version 3.10 +* +* \brief +* This file contains the USB MSC Class request handler and global API for MSC +* class. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* \copyright +* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_msc.h" +#include "USBFS_pvt.h" + + +#if (USBFS_HANDLE_MSC_REQUESTS) + +/*************************************** +* Internal variables +***************************************/ + +static uint8 USBFS_lunCount = USBFS_MSC_LUN_NUMBER; + + +/******************************************************************************* +* Function Name: USBFS_DispatchMSCClassRqst +****************************************************************************//** +* +* \internal +* This routine dispatches MSC class requests. +* +* \return +* Status of request processing: handled or not handled. +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchMSCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + /* Get request data. */ + uint16 value = USBFS_GET_UINT16(USBFS_wValueHiReg, USBFS_wValueLoReg); + uint16 dataLength = USBFS_GET_UINT16(USBFS_wLengthHiReg, USBFS_wLengthLoReg); + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + if (USBFS_MSC_GET_MAX_LUN == USBFS_bRequestReg) + { + /* Check request fields. */ + if ((value == USBFS_MSC_GET_MAX_LUN_WVALUE) && + (dataLength == USBFS_MSC_GET_MAX_LUN_WLENGTH)) + { + /* Reply to Get Max LUN request: setup control read. */ + USBFS_currentTD.pData = &USBFS_lunCount; + USBFS_currentTD.count = USBFS_MSC_GET_MAX_LUN_WLENGTH; + + requestHandled = USBFS_InitControlRead(); + } + } + } + else + { + /* Handle direction from host to device. */ + + if (USBFS_MSC_RESET == USBFS_bRequestReg) + { + /* Check request fields. */ + if ((value == USBFS_MSC_RESET_WVALUE) && + (dataLength == USBFS_MSC_RESET_WLENGTH)) + { + /* Handle to Bulk-Only Reset request: no data control transfer. */ + USBFS_currentTD.count = USBFS_MSC_RESET_WLENGTH; + + #ifdef USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK + USBFS_DispatchMSCClass_MSC_RESET_RQST_Callback(); + #endif /* (USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK) */ + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + } + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_MSC_SetLunCount +****************************************************************************//** +* +* This function sets the number of logical units supported in the application. +* The default number of logical units is set in the component customizer. +* +* \param lunCount: Count of the logical units. Valid range is between 1 and 16. +* +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_MSC_SetLunCount(uint8 lunCount) +{ + USBFS_lunCount = (lunCount - 1u); +} + + +/******************************************************************************* +* Function Name: USBFS_MSC_GetLunCount +****************************************************************************//** +* +* This function returns the number of logical units. +* +* \return +* Number of the logical units. +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_MSC_GetLunCount(void) +{ + return (USBFS_lunCount + 1u); +} + +#endif /* (USBFS_HANDLE_MSC_REQUESTS) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h new file mode 100755 index 0000000..551900f --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h @@ -0,0 +1,64 @@ +/***************************************************************************//** +* \file USBFS_msc.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* MSC class support. +* +* Related Document: +* Device Class Definition for Mass Storage (MSC) Version TDB +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_msc_H) +#define CY_USBFS_USBFS_msc_H + +#include "USBFS.h" + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_HANDLE_MSC_REQUESTS (0u != (1u)) +#define USBFS_MSC_LUN_NUMBER (1u - 1u) + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_msc +* @{ +*/ +#if (USBFS_HANDLE_MSC_REQUESTS) + void USBFS_MSC_SetLunCount(uint8 lunCount) ; + uint8 USBFS_MSC_GetLunCount(void) ; +#endif /* (USBFS_HANDLE_MSC_REQUESTS) */ +/** @} msc */ + +/*************************************** +* Constants +***************************************/ + +/* MSC Class-Specific requests */ +#define USBFS_MSC_RESET (0xFFu) +#define USBFS_MSC_GET_MAX_LUN (0xFEu) + +/* MSC Class-Specific requests constant fields. */ +#define USBFS_MSC_RESET_WVALUE (0u) +#define USBFS_MSC_RESET_WLENGTH (0u) + +#define USBFS_MSC_GET_MAX_LUN_WVALUE (0u) +#define USBFS_MSC_GET_MAX_LUN_WLENGTH (1u) + +#endif /* CY_USBFS_USBFS_msc_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c index bcf7525..776ffb9 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c @@ -1,23 +1,20 @@ -/******************************************************************************* -* File Name: USBFS_pm.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_pm.c +* \version 3.10 * -* Description: -* This file provides Suspend/Resume APIs functionality. -* -* Note: +* \brief +* This file provides Suspend/Resume APIs implementation. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "project.h" -#include "USBFS.h" #include "USBFS_pvt.h" - +#include "USBFS_Dp.h" /*************************************** @@ -34,156 +31,154 @@ static USBFS_BACKUP_STRUCT USBFS_backup; - -#if(USBFS_DP_ISR_REMOVE == 0u) - +#if (USBFS_DP_ISR_ACTIVE) /******************************************************************************* - * Function Name: USBFS_DP_Interrupt - ******************************************************************************** + * Function Name: USBFS_DP_ISR + ****************************************************************************//** * - * Summary: * This Interrupt Service Routine handles DP pin changes for wake-up from * the sleep mode. * - * Parameters: - * None. - * - * Return: - * None. - * *******************************************************************************/ CY_ISR(USBFS_DP_ISR) { - #ifdef USBFS_DP_ISR_ENTRY_CALLBACK - USBFS_DP_ISR_EntryCallback(); - #endif /* USBFS_DP_ISR_ENTRY_CALLBACK */ + #ifdef USBFS_DP_ISR_ENTRY_CALLBACK + USBFS_DP_ISR_EntryCallback(); + #endif /* (USBFS_DP_ISR_ENTRY_CALLBACK) */ /* `#START DP_USER_CODE` Place your code here */ /* `#END` */ - /* Clears active interrupt */ - CY_GET_REG8(USBFS_DP_INTSTAT_PTR); - - #ifdef USBFS_DP_ISR_EXIT_CALLBACK - USBFS_DP_ISR_ExitCallback(); - #endif /* USBFS_DP_ISR_EXIT_CALLBACK */ + (void) USBFS_Dp_ClearInterrupt(); + + #ifdef USBFS_DP_ISR_EXIT_CALLBACK + USBFS_DP_ISR_ExitCallback(); + #endif /* (USBFS_DP_ISR_EXIT_CALLBACK) */ } - -#endif /* (USBFS_DP_ISR_REMOVE == 0u) */ +#endif /* (USBFS_DP_ISR_ACTIVE) */ /******************************************************************************* * Function Name: USBFS_SaveConfig -******************************************************************************** +****************************************************************************//** * -* Summary: * Saves the current user configuration. * -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_SaveConfig(void) { - + /* Empty function added for the compatibility purpose. */ } /******************************************************************************* * Function Name: USBFS_RestoreConfig -******************************************************************************** +****************************************************************************//** * -* Summary: * Restores the current user configuration. * -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_RestoreConfig(void) { - if(USBFS_configuration != 0u) + if (USBFS_configuration != 0u) { USBFS_ConfigReg(); + USBFS_EpStateInit(); } } /******************************************************************************* * Function Name: USBFS_Suspend -******************************************************************************** +****************************************************************************//** * -* Summary: -* This function disables the USBFS block and prepares for power down mode. +* This function prepares the USBFS component to enter low power mode. The +* interrupt on falling edge on Dp pin is configured to wakeup device when the +* host drives resume condition. The pull-up is enabled on the Dp line while +* device is in low power mode. The supported low power modes are Deep Sleep +* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP). +* +* *Note* For PSoC 4200L devices, this function should not be called before +* entering Sleep. +* +* *Note* After enter low power mode, the data which is left in the IN or OUT +* endpoint buffers is not restored after wakeup and lost. Therefore it should +* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint +* before enter low power mode. * -* Parameters: -* None. -* -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_backup.enable: modified. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_Suspend(void) { uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); - if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u) - { /* USB block is enabled */ + if (0u != (USBFS_CR0_REG & USBFS_CR0_ENABLE)) + { + /* USB block is enabled. */ USBFS_backup.enableState = 1u; - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + #if (USBFS_EP_MANAGEMENT_DMA) + USBFS_Stop_DMA(USBFS_MAX_EP); + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ - /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ - USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN; - CyDelayUs(0u); /*~50ns delay */ + #if (CY_PSOC4) + /* Suspend enter sequence. */ + USBFS_POWER_CTRL_REG |= (USBFS_POWER_CTRL_SUSPEND | + USBFS_POWER_CTRL_SUSPEND_DEL); + + /* Store state of USB regulator and disable it. */ + USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE); + USBFS_CR1_REG &= (uint32) ~USBFS_CR1_REG_ENABLE; + + /* Store SIE interrupt sources. Valid bits are 0 - 4. */ + USBFS_backup.intrSeiMask = (uint8) USBFS_INTR_SIE_MASK_REG; + + #else + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */ + USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /*~50ns delay. */ /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ - USBFS_PM_USB_CR0_REG &= - (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N); + USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N); - /* Disable the SIE */ - USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE; + /* Disable the SIE. */ + USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE; - CyDelayUs(0u); /* ~50ns delay */ - /* Store mode and Disable VRegulator*/ - USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE; - USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */ + /* Store mode and disable VRegulator. */ + USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE); + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */ - CyDelayUs(1u); /* 0.5 us min delay */ /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ - USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN; + USBFS_PM_USB_CR0_REG &= (uint8) ~USBFS_PM_USB_CR0_REF_EN; - /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/ + /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */ USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; - /* Disable USB in ACT PM */ - USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB; - /* Disable USB block for Standby Power Mode */ - USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB; - CyDelayUs(1u); /* min 0.5us delay required */ + /* Disable USBFS block. */ + /* Clear power active and standby mode templates: disable USB block. */ + USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB; + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */ + #endif /* (CY_PSOC4) */ } else { @@ -192,90 +187,142 @@ void USBFS_Suspend(void) CyExitCriticalSection(enableInterrupts); - /* Set the DP Interrupt for wake-up from sleep mode. */ - #if(USBFS_DP_ISR_REMOVE == 0u) - (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); - CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR); - CyIntClearPending(USBFS_DP_INTC_VECT_NUM); - CyIntEnable(USBFS_DP_INTC_VECT_NUM); - #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ +#if (USBFS_DP_ISR_ACTIVE) + /* Clear active mode Dp interrupt source history. */ + (void) USBFS_Dp_ClearInterrupt(); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + + CyIntEnable (USBFS_DP_INTC_VECT_NUM); +#endif /* (USBFS_DP_ISR_ACTIVE). */ } /******************************************************************************* * Function Name: USBFS_Resume -******************************************************************************** +****************************************************************************//** * -* Summary: -* This function enables the USBFS block after power down mode. +* This function prepares the USBFS component for active mode operation after +* exit low power mode. It restores the component active mode configuration such +* as device address assigned previously by the host, endpoints buffer and disables +* interrupt on Dp pin. +* The supported low power modes are Deep Sleep (PSoC 4200L) and Sleep +* (PSoC 3/ PSoC 5LP). +* +* *Note* For PSoC 4200L devices, this function should not be called after +* exiting Sleep. +* +* *Note* To resume communication with the host, the data endpoints must be +* managed: the OUT endpoints must be enabled and IN endpoints must be loaded +* with data. For DMA with Automatic Buffer Management, all endpoints buffers +* must be initialized again before making them available to the host. * -* Parameters: -* None. * -* Return: -* None. -* -* Global variables: +* \globalvars * USBFS_backup - checked. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_Resume(void) { uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); - if(USBFS_backup.enableState != 0u) + if (0u != USBFS_backup.enableState) { - #if(USBFS_DP_ISR_REMOVE == 0u) - CyIntDisable(USBFS_DP_INTC_VECT_NUM); - #endif /* USBFS_DP_ISR_REMOVE */ + #if (USBFS_DP_ISR_ACTIVE) + CyIntDisable(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_ACTIVE) */ - /* Enable USB block */ - USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; - /* Enable USB block for Standby Power Mode */ + #if (CY_PSOC4) + /* Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_CSR_CLK_EN; + + /* Restore arbiter configuration for DMA transfers. */ + #if (USBFS_EP_MANAGEMENT_DMA) + #if (USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Configure arbiter for Manual or Auto DMA operation and clear + * configuration completion. + */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Restore level (hi, lo, med) for each interrupt source. */ + USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL; + + /* Store SIE interrupt sources. */ + USBFS_INTR_SIE_MASK_REG = (uint32) USBFS_backup.intrSeiMask; + + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; + + /* Restore data EP1-8 configuration. */ + USBFS_RestoreConfig(); + + /* Restore state of USB regulator and wait until it supples stable power. */ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(USBFS_WAIT_VREF_STABILITY); + + /* Suspend exit sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + #else + /* Set power active and standby mode templates: enable USB block. */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; - /* Enable core clock */ + + /* Enable core clock. */ USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; - /* The reference will be available ~40us after power restored */ - CyDelayUs(40u); - /* Return VRegulator*/ + + /* The reference is available ~40us after power restored. */ + CyDelayUs(USBFS_WAIT_VREF_RESTORE); + /* Restore state of USB regulator and wait until it supples stable power. */ USBFS_CR1_REG |= USBFS_backup.mode; - CyDelayUs(0u); /*~50ns delay */ - /* Enable USBIO */ + CyDelayUs(USBFS_WAIT_VREF_STABILITY); /*~50ns delay. */ + + /* Enable USBIO. */ USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; - CyDelayUs(2u); - /* Set the USBIO pull-up enable */ + CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE); + /* Set the USBIO pull-up enable. */ USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; - /* Re-init Arbiter configuration for DMA transfers */ - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - /* Usb arb interrupt enable */ - USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; - #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; - #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /*Set cfg cmplt this rises DMA request when the full configuration is done */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + /* Restore arbiter configuration for DMA transfers. */ + #if (USBFS_EP_MANAGEMENT_DMA) + #if (USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ - /* STALL_IN_OUT */ - CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); - /* Enable the SIE with a last address */ + /* Configure arbiter for Manual or Auto DMA operation and clear + * configuration completion. + */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; + + /* Enable the USB IP to respond to USB traffic with the last address. */ USBFS_CR0_REG |= USBFS_CR0_ENABLE; - CyDelayCycles(1u); - /* Finally, Enable d+ pullup and select iomode to USB mode*/ - CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); + CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY); - /* Restore USB register settings */ + /* Enable D+ pull-up and keep USB control on IO. */ + USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; + + /* Restore data EP1-8 configuration. */ USBFS_RestoreConfig(); + #endif /* (CY_PSOC4) */ } CyExitCriticalSection(enableInterrupts); diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h old mode 100644 new mode 100755 index 08bf742..957e823 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h @@ -1,16 +1,14 @@ -/******************************************************************************* -* File Name: .h -* Version 2.80 +/***************************************************************************//** +* \file .h +* \version 3.10 * -* Description: -* This private file provides constants and parameter values for the -* USBFS Component. -* Please do not use this file or its content in your project. -* -* Note: +* \brief +* This file provides private function prototypes and constants for the +* USBFS component. It is not intended to be used in the user project. * ******************************************************************************** -* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2013-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,12 +17,83 @@ #if !defined(CY_USBFS_USBFS_pvt_H) #define CY_USBFS_USBFS_pvt_H +#include "USBFS.h" + +#ifdef USBFS_ENABLE_AUDIO_CLASS + #include "USBFS_audio.h" +#endif /* USBFS_ENABLE_AUDIO_CLASS */ + +#ifdef USBFS_ENABLE_CDC_CLASS + #include "USBFS_cdc.h" +#endif /* USBFS_ENABLE_CDC_CLASS */ + +#if (USBFS_ENABLE_MIDI_CLASS) + #include "USBFS_midi.h" +#endif /* (USBFS_ENABLE_MIDI_CLASS) */ + +#if (USBFS_ENABLE_MSC_CLASS) + #include "USBFS_msc.h" +#endif /* (USBFS_ENABLE_MSC_CLASS) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + #include + #else + #include + #if ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + #include "USBFS_EP_DMA_Done_isr.h" + #include "USBFS_EP8_DMA_Done_SR.h" + #include "USBFS_EP17_DMA_Done_SR.h" + #endif /* ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_DMA1_ACTIVE) + #include "USBFS_ep1_dma.h" + #define USBFS_EP1_DMA_CH (USBFS_ep1_dma_CHANNEL) +#endif /* (USBFS_DMA1_ACTIVE) */ + +#if (USBFS_DMA2_ACTIVE) + #include "USBFS_ep2_dma.h" + #define USBFS_EP2_DMA_CH (USBFS_ep2_dma_CHANNEL) +#endif /* (USBFS_DMA2_ACTIVE) */ + +#if (USBFS_DMA3_ACTIVE) + #include "USBFS_ep3_dma.h" + #define USBFS_EP3_DMA_CH (USBFS_ep3_dma_CHANNEL) +#endif /* (USBFS_DMA3_ACTIVE) */ + +#if (USBFS_DMA4_ACTIVE) + #include "USBFS_ep4_dma.h" + #define USBFS_EP4_DMA_CH (USBFS_ep4_dma_CHANNEL) +#endif /* (USBFS_DMA4_ACTIVE) */ + +#if (USBFS_DMA5_ACTIVE) + #include "USBFS_ep5_dma.h" + #define USBFS_EP5_DMA_CH (USBFS_ep5_dma_CHANNEL) +#endif /* (USBFS_DMA5_ACTIVE) */ + +#if (USBFS_DMA6_ACTIVE) + #include "USBFS_ep6_dma.h" + #define USBFS_EP6_DMA_CH (USBFS_ep6_dma_CHANNEL) +#endif /* (USBFS_DMA6_ACTIVE) */ + +#if (USBFS_DMA7_ACTIVE) + #include "USBFS_ep7_dma.h" + #define USBFS_EP7_DMA_CH (USBFS_ep7_dma_CHANNEL) +#endif /* (USBFS_DMA7_ACTIVE) */ + +#if (USBFS_DMA8_ACTIVE) + #include "USBFS_ep8_dma.h" + #define USBFS_EP8_DMA_CH (USBFS_ep8_dma_CHANNEL) +#endif /* (USBFS_DMA8_ACTIVE) */ + /*************************************** * Private Variables ***************************************/ -/* Generated external references for descriptors*/ +/* Generated external references for descriptors. */ extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u]; extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u]; @@ -32,7 +101,7 @@ extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u]; extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u]; extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u]; -extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u]; extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10]; extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u]; @@ -62,11 +131,11 @@ extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; #if defined(USBFS_ENABLE_IDSN_STRING) extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; -#endif /* USBFS_ENABLE_IDSN_STRING */ +#endif /* (USBFS_ENABLE_IDSN_STRING) */ extern volatile uint8 USBFS_interfaceNumber; extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; -extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_interfaceSettingLast[USBFS_MAX_INTERFACES_NUMBER]; extern volatile uint8 USBFS_deviceAddress; extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; extern const uint8 CYCODE *USBFS_interfaceClass; @@ -74,17 +143,35 @@ extern const uint8 CYCODE *USBFS_interfaceClass; extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; extern volatile T_USBFS_TD USBFS_currentTD; -#if(USBFS_EP_MM != USBFS__EP_MANUAL) - extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; - extern uint8 USBFS_DmaTd[USBFS_MAX_EP]; -#endif /* USBFS_EP_MM */ -#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; - extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP]; - extern volatile uint16 USBFS_inLength[USBFS_MAX_EP]; - extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; - extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; -#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + extern const uint8 USBFS_DmaChan[USBFS_MAX_EP]; + #else + extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; + extern uint8 USBFS_DmaTd [USBFS_MAX_EP]; + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + extern uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP]; + extern uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP]; + + extern uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP]; + extern uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP]; + + extern const uint8 USBFS_DmaReqOut [USBFS_MAX_EP]; + extern const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP]; +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + extern volatile uint16 USBFS_inLength [USBFS_MAX_EP]; + extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; + extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP]; + extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* CY_PSOC4 */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ extern volatile uint8 USBFS_ep0Toggle; extern volatile uint8 USBFS_lastPacketSize; @@ -96,111 +183,178 @@ extern volatile uint16 USBFS_transferByteCount; /*************************************** * Private Function Prototypes ***************************************/ -void USBFS_ReInitComponent(void) ; -void USBFS_HandleSetup(void) ; -void USBFS_HandleIN(void) ; -void USBFS_HandleOUT(void) ; -void USBFS_LoadEP0(void) ; -uint8 USBFS_InitControlRead(void) ; -uint8 USBFS_InitControlWrite(void) ; -void USBFS_ControlReadDataStage(void) ; -void USBFS_ControlReadStatusStage(void) ; -void USBFS_ControlReadPrematureStatus(void) - ; -uint8 USBFS_InitControlWrite(void) ; -uint8 USBFS_InitZeroLengthControlTransfer(void) - ; -void USBFS_ControlWriteDataStage(void) ; -void USBFS_ControlWriteStatusStage(void) ; -void USBFS_ControlWritePrematureStatus(void) - ; -uint8 USBFS_InitNoDataControlTransfer(void) ; -void USBFS_NoDataControlStatusStage(void) ; -void USBFS_InitializeStatusBlock(void) ; +void USBFS_ReInitComponent(void) ; +void USBFS_HandleSetup(void) ; +void USBFS_HandleIN(void) ; +void USBFS_HandleOUT(void) ; +void USBFS_LoadEP0(void) ; +uint8 USBFS_InitControlRead(void) ; +uint8 USBFS_InitControlWrite(void) ; +void USBFS_ControlReadDataStage(void) ; +void USBFS_ControlReadStatusStage(void) ; +void USBFS_ControlReadPrematureStatus(void) ; +uint8 USBFS_InitControlWrite(void) ; +uint8 USBFS_InitZeroLengthControlTransfer(void) ; +void USBFS_ControlWriteDataStage(void) ; +void USBFS_ControlWriteStatusStage(void) ; +void USBFS_ControlWritePrematureStatus(void); +uint8 USBFS_InitNoDataControlTransfer(void) ; +void USBFS_NoDataControlStatusStage(void) ; +void USBFS_InitializeStatusBlock(void) ; void USBFS_UpdateStatusBlock(uint8 completionCode) ; -uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; void USBFS_Config(uint8 clearAltSetting) ; -void USBFS_ConfigAltChanged(void) ; -void USBFS_ConfigReg(void) ; +void USBFS_ConfigAltChanged(void) ; +void USBFS_ConfigReg(void) ; +void USBFS_EpStateInit(void) ; -const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) - ; -const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) - ; -const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) - ; -uint8 USBFS_ClearEndpointHalt(void) ; -uint8 USBFS_SetEndpointHalt(void) ; -uint8 USBFS_ValidateAlternateSetting(void) ; -void USBFS_SaveConfig(void) ; -void USBFS_RestoreConfig(void) ; +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex); +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) ; +#if (USBFS_BOS_ENABLE) + const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) ; +#endif /* (USBFS_BOS_ENABLE) */ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) ;uint8 USBFS_ClearEndpointHalt(void) ; +uint8 USBFS_SetEndpointHalt(void) ; +uint8 USBFS_ValidateAlternateSetting(void) ; -#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ; -#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */ +void USBFS_SaveConfig(void) ; +void USBFS_RestoreConfig(void) ; + +#if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ #if defined(USBFS_ENABLE_IDSN_STRING) - void USBFS_ReadDieID(uint8 descr[]) ; + void USBFS_ReadDieID(uint8 descr[]) ; #endif /* USBFS_ENABLE_IDSN_STRING */ #if defined(USBFS_ENABLE_HID_CLASS) - uint8 USBFS_DispatchHIDClassRqst(void); -#endif /* USBFS_ENABLE_HID_CLASS */ + uint8 USBFS_DispatchHIDClassRqst(void) ; +#endif /* (USBFS_ENABLE_HID_CLASS) */ + #if defined(USBFS_ENABLE_AUDIO_CLASS) - uint8 USBFS_DispatchAUDIOClassRqst(void); -#endif /* USBFS_ENABLE_HID_CLASS */ + uint8 USBFS_DispatchAUDIOClassRqst(void) ; +#endif /* (USBFS_ENABLE_AUDIO_CLASS) */ + #if defined(USBFS_ENABLE_CDC_CLASS) - uint8 USBFS_DispatchCDCClassRqst(void); -#endif /* USBFS_ENABLE_CDC_CLASS */ + uint8 USBFS_DispatchCDCClassRqst(void) ; +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + +#if (USBFS_ENABLE_MSC_CLASS) + #if (USBFS_HANDLE_MSC_REQUESTS) + uint8 USBFS_DispatchMSCClassRqst(void) ; + #endif /* (USBFS_HANDLE_MSC_REQUESTS) */ +#endif /* (USBFS_ENABLE_MSC_CLASS */ CY_ISR_PROTO(USBFS_EP_0_ISR); -#if(USBFS_EP1_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_1_ISR); -#endif /* USBFS_EP1_ISR_REMOVE */ -#if(USBFS_EP2_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_2_ISR); -#endif /* USBFS_EP2_ISR_REMOVE */ -#if(USBFS_EP3_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_3_ISR); -#endif /* USBFS_EP3_ISR_REMOVE */ -#if(USBFS_EP4_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_4_ISR); -#endif /* USBFS_EP4_ISR_REMOVE */ -#if(USBFS_EP5_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_5_ISR); -#endif /* USBFS_EP5_ISR_REMOVE */ -#if(USBFS_EP6_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_6_ISR); -#endif /* USBFS_EP6_ISR_REMOVE */ -#if(USBFS_EP7_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_7_ISR); -#endif /* USBFS_EP7_ISR_REMOVE */ -#if(USBFS_EP8_ISR_REMOVE == 0u) - CY_ISR_PROTO(USBFS_EP_8_ISR); -#endif /* USBFS_EP8_ISR_REMOVE */ CY_ISR_PROTO(USBFS_BUS_RESET_ISR); -#if(USBFS_SOF_ISR_REMOVE == 0u) + +#if (USBFS_SOF_ISR_ACTIVE) CY_ISR_PROTO(USBFS_SOF_ISR); -#endif /* USBFS_SOF_ISR_REMOVE */ -#if(USBFS_EP_MM != USBFS__EP_MANUAL) +#endif /* (USBFS_SOF_ISR_ACTIVE) */ + +#if (USBFS_EP1_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_1_ISR); +#endif /* (USBFS_EP1_ISR_ACTIVE) */ + +#if (USBFS_EP2_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_2_ISR); +#endif /* (USBFS_EP2_ISR_ACTIVE) */ + +#if (USBFS_EP3_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_3_ISR); +#endif /* (USBFS_EP3_ISR_ACTIVE) */ + +#if (USBFS_EP4_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_4_ISR); +#endif /* (USBFS_EP4_ISR_ACTIVE) */ + +#if (USBFS_EP5_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_5_ISR); +#endif /* (USBFS_EP5_ISR_ACTIVE) */ + +#if (USBFS_EP6_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_6_ISR); +#endif /* (USBFS_EP6_ISR_ACTIVE) */ + +#if (USBFS_EP7_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_7_ISR); +#endif /* (USBFS_EP7_ISR_ACTIVE) */ + +#if (USBFS_EP8_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_8_ISR); +#endif /* (USBFS_EP8_ISR_ACTIVE) */ + +#if (USBFS_EP_MANAGEMENT_DMA) CY_ISR_PROTO(USBFS_ARB_ISR); -#endif /* USBFS_EP_MM */ -#if(USBFS_DP_ISR_REMOVE == 0u) +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_DP_ISR_ACTIVE) CY_ISR_PROTO(USBFS_DP_ISR); -#endif /* USBFS_DP_ISR_REMOVE */ -#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) - CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR); -#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (USBFS_DP_ISR_ACTIVE) */ + +#if (CY_PSOC4) + CY_ISR_PROTO(USBFS_INTR_HI_ISR); + CY_ISR_PROTO(USBFS_INTR_MED_ISR); + CY_ISR_PROTO(USBFS_INTR_LO_ISR); + #if (USBFS_LPM_ACTIVE) + CY_ISR_PROTO(USBFS_LPM_ISR); + #endif /* (USBFS_LPM_ACTIVE) */ +#endif /* (CY_PSOC4) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + #if (USBFS_DMA1_ACTIVE) + void USBFS_EP1_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + void USBFS_EP2_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + void USBFS_EP3_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + void USBFS_EP4_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + void USBFS_EP5_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + void USBFS_EP6_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + void USBFS_EP7_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + void USBFS_EP8_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA8_ACTIVE) */ + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + /*************************************** -* Request Handlers +* Request Handlers ***************************************/ uint8 USBFS_HandleStandardRqst(void) ; -uint8 USBFS_DispatchClassRqst(void) ; -uint8 USBFS_HandleVendorRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_HandleVendorRqst(void) ; /*************************************** @@ -208,8 +362,8 @@ uint8 USBFS_HandleVendorRqst(void) ; ***************************************/ #if defined(USBFS_ENABLE_HID_CLASS) - void USBFS_FindReport(void) ; - void USBFS_FindReportDescriptor(void) ; + void USBFS_FindReport(void) ; + void USBFS_FindReportDescriptor(void) ; void USBFS_FindHidClassDecriptor(void) ; #endif /* USBFS_ENABLE_HID_CLASS */ @@ -219,8 +373,37 @@ uint8 USBFS_HandleVendorRqst(void) ; ***************************************/ #if defined(USBFS_ENABLE_MIDI_STREAMING) - void USBFS_MIDI_IN_EP_Service(void) ; -#endif /* USBFS_ENABLE_MIDI_STREAMING */ + void USBFS_MIDI_IN_EP_Service(void) ; +#endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + + +/*************************************** +* CDC Internal references +***************************************/ + +#if defined(USBFS_ENABLE_CDC_CLASS) + + typedef struct + { + uint8 bRequestType; + uint8 bNotification; + uint8 wValue; + uint8 wValueMSB; + uint8 wIndex; + uint8 wIndexMSB; + uint8 wLength; + uint8 wLengthMSB; + uint8 wSerialState; + uint8 wSerialStateMSB; + } t_USBFS_cdc_notification; + + uint8 USBFS_GetInterfaceComPort(uint8 interface) ; + uint8 USBFS_Cdc_EpInit( const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) ; + + extern volatile uint8 USBFS_cdc_dataInEpList[USBFS_MAX_MULTI_COM_NUM]; + extern volatile uint8 USBFS_cdc_dataOutEpList[USBFS_MAX_MULTI_COM_NUM]; + extern volatile uint8 USBFS_cdc_commInEpList[USBFS_MAX_MULTI_COM_NUM]; +#endif /* (USBFS_ENABLE_CDC_CLASS) */ #endif /* CY_USBFS_USBFS_pvt_H */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c old mode 100644 new mode 100755 index b047b37..836cd73 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c @@ -1,87 +1,83 @@ -/******************************************************************************* -* File Name: USBFS_std.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_std.c +* \version 3.10 * -* Description: -* USB Standard request handler. -* -* Note: +* \brief +* This file contains the USB Standard request handler. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" -#include "USBFS_cdc.h" #include "USBFS_pvt.h" -#if defined(USBFS_ENABLE_MIDI_STREAMING) - #include "USBFS_midi.h" -#endif /* USBFS_ENABLE_MIDI_STREAMING*/ - /*************************************** * Static data allocation ***************************************/ #if defined(USBFS_ENABLE_FWSN_STRING) - static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; - static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; -#endif /* USBFS_ENABLE_FWSN_STRING */ + static volatile uint8* USBFS_fwSerialNumberStringDescriptor; + static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; +#endif /* (USBFS_ENABLE_FWSN_STRING) */ #if defined(USBFS_ENABLE_FWSN_STRING) - - /******************************************************************************* + /*************************************************************************** * Function Name: USBFS_SerialNumString - ******************************************************************************** + ************************************************************************//** * - * Summary: - * Application firmware may supply the source of the USB device descriptors - * serial number string during runtime. + * This function is available only when the User Call Back option in the + * Serial Number String descriptor properties is selected. Application + * firmware can provide the source of the USB device serial number string + * descriptor during run time. The default string is used if the application + * firmware does not use this function or sets the wrong string descriptor. * - * Parameters: - * snString: pointer to string. + * \param snString: Pointer to the user-defined string descriptor. The + * string descriptor should meet the Universal Serial Bus Specification + * revision 2.0 chapter 9.6.7 + * Offset|Size|Value|Description + * ------|----|------|--------------------------------- + * 0 |1 |N |Size of this descriptor in bytes + * 1 |1 |0x03 |STRING Descriptor Type + * 2 |N-2 |Number|UNICODE encoded string + * + * *For example:* uint8 snString[16]={0x0E,0x03,'F',0,'W',0,'S',0,'N',0,'0',0,'1',0}; * - * Return: - * None. - * - * Reentrant: + * \reentrant * No. * - *******************************************************************************/ + ***************************************************************************/ void USBFS_SerialNumString(uint8 snString[]) { USBFS_snStringConfirm = USBFS_FALSE; - if(snString != NULL) + + if (snString != NULL) { /* Check descriptor validation */ - if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) ) + if ((snString[0u] > 1u) && (snString[1u] == USBFS_DESCR_STRING)) { USBFS_fwSerialNumberStringDescriptor = snString; USBFS_snStringConfirm = USBFS_TRUE; } } } - #endif /* USBFS_ENABLE_FWSN_STRING */ /******************************************************************************* * Function Name: USBFS_HandleStandardRqst -******************************************************************************** +****************************************************************************//** * -* Summary: * This Routine dispatches standard requests * -* Parameters: -* None. * -* Return: +* \return * TRUE if request handled. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -90,90 +86,116 @@ uint8 USBFS_HandleStandardRqst(void) uint8 requestHandled = USBFS_FALSE; uint8 interfaceNumber; uint8 configurationN; - #if defined(USBFS_ENABLE_STRINGS) - volatile uint8 *pStr = 0u; - #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) - uint8 nStr; - uint8 descrLength; - #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ - #endif /* USBFS_ENABLE_STRINGS */ + uint8 bmRequestType = USBFS_bmRequestTypeReg; + +#if defined(USBFS_ENABLE_STRINGS) + volatile uint8 *pStr = 0u; + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + uint8 nStr; + uint8 descrLength; + #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */ +#endif /* (USBFS_ENABLE_STRINGS) */ + static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; const T_USBFS_LUT CYCODE *pTmp; + USBFS_currentTD.count = 0u; - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + if (USBFS_RQST_DIR_D2H == (bmRequestType & USBFS_RQST_DIR_MASK)) { /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) + switch (USBFS_bRequestReg) { case USBFS_GET_DESCRIPTOR: - if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) + if (USBFS_DESCR_DEVICE ==USBFS_wValueHiReg) { pTmp = USBFS_GetDeviceTablePtr(); USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; + requestHandled = USBFS_InitControlRead(); } - else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) + else if (USBFS_DESCR_CONFIG == USBFS_wValueHiReg) { - pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); - if( pTmp != NULL ) /* Verify that requested descriptor exists */ + pTmp = USBFS_GetConfigTablePtr((uint8) USBFS_wValueLoReg); + + /* Verify that requested descriptor exists */ + if (pTmp != NULL) { USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; - USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ - USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ - (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; + USBFS_currentTD.count = (uint16)((uint16)(USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ + (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; requestHandled = USBFS_InitControlRead(); } } - #if defined(USBFS_ENABLE_STRINGS) - else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) + + #if(USBFS_BOS_ENABLE) + else if (USBFS_DESCR_BOS == USBFS_wValueHiReg) { - /* Descriptor Strings*/ - #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) - nStr = 0u; - pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u]; - while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) + pTmp = USBFS_GetBOSPtr(); + + /* Verify that requested descriptor exists */ + if (pTmp != NULL) + { + USBFS_currentTD.pData = (volatile uint8 *)pTmp; + USBFS_currentTD.count = ((uint16)((uint16)(USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_HI] << 8u)) | \ + (USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /*(USBFS_BOS_ENABLE)*/ + + #if defined(USBFS_ENABLE_STRINGS) + else if (USBFS_DESCR_STRING == USBFS_wValueHiReg) + { + /* Descriptor Strings */ + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + nStr = 0u; + pStr = (volatile uint8 *) &USBFS_STRING_DESCRIPTORS[0u]; + + while ((USBFS_wValueLoReg > nStr) && (*pStr != 0u)) + { + /* Read descriptor length from 1st byte */ + descrLength = *pStr; + /* Move to next string descriptor */ + pStr = &pStr[descrLength]; + nStr++; + } + #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */ + + /* Microsoft OS String */ + #if defined(USBFS_ENABLE_MSOS_STRING) + if (USBFS_STRING_MSOS == USBFS_wValueLoReg) + { + pStr = (volatile uint8 *)& USBFS_MSOS_DESCRIPTOR[0u]; + } + #endif /* (USBFS_ENABLE_MSOS_STRING) */ + + /* SN string */ + #if defined(USBFS_ENABLE_SN_STRING) + if ((USBFS_wValueLoReg != 0u) && + (USBFS_wValueLoReg == USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT])) + { + #if defined(USBFS_ENABLE_IDSN_STRING) + /* Read DIE ID and generate string descriptor in RAM */ + USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); + pStr = USBFS_idSerialNumberStringDescriptor; + #elif defined(USBFS_ENABLE_FWSN_STRING) + + if(USBFS_snStringConfirm != USBFS_FALSE) { - /* Read descriptor length from 1st byte */ - descrLength = *pStr; - /* Move to next string descriptor */ - pStr = &pStr[descrLength]; - nStr++; + pStr = USBFS_fwSerialNumberStringDescriptor; } - #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ - /* Microsoft OS String*/ - #if defined(USBFS_ENABLE_MSOS_STRING) - if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) + else { - pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; } - #endif /* USBFS_ENABLE_MSOS_STRING*/ - /* SN string */ - #if defined(USBFS_ENABLE_SN_STRING) - if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && - (CY_GET_REG8(USBFS_wValueLo) == - USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) ) - { - - #if defined(USBFS_ENABLE_IDSN_STRING) - /* Read DIE ID and generate string descriptor in RAM */ - USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); - pStr = USBFS_idSerialNumberStringDescriptor; - #elif defined(USBFS_ENABLE_FWSN_STRING) - if(USBFS_snStringConfirm != USBFS_FALSE) - { - pStr = USBFS_fwSerialNumberStringDescriptor; - } - else - { - pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; - } - #else - pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; - #endif /* defined(USBFS_ENABLE_IDSN_STRING) */ - } - #endif /* USBFS_ENABLE_SN_STRING */ + #else + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + #endif /* (USBFS_ENABLE_IDSN_STRING) */ + } + #endif /* (USBFS_ENABLE_SN_STRING) */ + if (*pStr != 0u) { USBFS_currentTD.count = *pStr; @@ -181,106 +203,123 @@ uint8 USBFS_HandleStandardRqst(void) requestHandled = USBFS_InitControlRead(); } } - #endif /* USBFS_ENABLE_STRINGS */ + #endif /* USBFS_ENABLE_STRINGS */ else { requestHandled = USBFS_DispatchClassRqst(); } break; + case USBFS_GET_STATUS: - switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) + switch (bmRequestType & USBFS_RQST_RCPT_MASK) { case USBFS_RQST_RCPT_EP: USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; - USBFS_tBuffer[0u] = USBFS_EP[ \ - CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; - USBFS_tBuffer[1u] = 0u; + USBFS_tBuffer[0u] = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].hwEpState; + USBFS_tBuffer[1u] = 0u; USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); break; case USBFS_RQST_RCPT_DEV: USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; - USBFS_tBuffer[0u] = USBFS_deviceStatus; - USBFS_tBuffer[1u] = 0u; + USBFS_tBuffer[0u] = USBFS_deviceStatus; + USBFS_tBuffer[1u] = 0u; USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); break; default: /* requestHandled is initialized as FALSE by default */ break; } break; + case USBFS_GET_CONFIGURATION: USBFS_currentTD.count = 1u; - USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_configuration; requestHandled = USBFS_InitControlRead(); break; + case USBFS_GET_INTERFACE: USBFS_currentTD.count = 1u; - USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ - CY_GET_REG8(USBFS_wIndexLo)]; + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_interfaceSetting[USBFS_wIndexLoReg]; requestHandled = USBFS_InitControlRead(); break; + default: /* requestHandled is initialized as FALSE by default */ break; } } - else { + else + { /* Control Write */ - switch (CY_GET_REG8(USBFS_bRequest)) + switch (USBFS_bRequestReg) { case USBFS_SET_ADDRESS: - USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); + /* Store address to be set in USBFS_NoDataControlStatusStage(). */ + USBFS_deviceAddress = (uint8) USBFS_wValueLoReg; requestHandled = USBFS_InitNoDataControlTransfer(); break; + case USBFS_SET_CONFIGURATION: - configurationN = CY_GET_REG8(USBFS_wValueLo); + configurationN = USBFS_wValueLoReg; + + /* Verify that configuration descriptor exists */ if(configurationN > 0u) - { /* Verify that configuration descriptor exists */ - pTmp = USBFS_GetConfigTablePtr(configurationN - 1u); + { + pTmp = USBFS_GetConfigTablePtr((uint8) configurationN - 1u); } + /* Responds with a Request Error when configuration number is invalid */ if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u)) { /* Set new configuration if it has been changed */ if(configurationN != USBFS_configuration) { - USBFS_configuration = configurationN; + USBFS_configuration = (uint8) configurationN; USBFS_configurationChanged = USBFS_TRUE; USBFS_Config(USBFS_TRUE); } requestHandled = USBFS_InitNoDataControlTransfer(); } break; + case USBFS_SET_INTERFACE: - if (USBFS_ValidateAlternateSetting() != 0u) + if (0u != USBFS_ValidateAlternateSetting()) { - interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); - USBFS_interfaceNumber = interfaceNumber; - USBFS_configurationChanged = USBFS_TRUE; - #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ - (USBFS_EP_MM == USBFS__EP_MANUAL) ) + /* Get interface number from the request. */ + interfaceNumber = USBFS_wIndexLoReg; + USBFS_interfaceNumber = (uint8) USBFS_wIndexLoReg; + + /* Check if alternate settings is changed for interface. */ + if (USBFS_interfaceSettingLast[interfaceNumber] != USBFS_interfaceSetting[interfaceNumber]) + { + USBFS_configurationChanged = USBFS_TRUE; + + /* Change alternate setting for the endpoints. */ + #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) USBFS_Config(USBFS_FALSE); #else USBFS_ConfigAltChanged(); - #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ - /* Update handled Alt setting changes status */ - USBFS_interfaceSetting_last[interfaceNumber] = - USBFS_interfaceSetting[interfaceNumber]; + #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */ + } + requestHandled = USBFS_InitNoDataControlTransfer(); } break; + case USBFS_CLEAR_FEATURE: - switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + switch (bmRequestType & USBFS_RQST_RCPT_MASK) { case USBFS_RQST_RCPT_EP: - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT) { requestHandled = USBFS_ClearEndpointHalt(); } break; case USBFS_RQST_RCPT_DEV: /* Clear device REMOTE_WAKEUP */ - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP) { USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; requestHandled = USBFS_InitNoDataControlTransfer(); @@ -288,10 +327,9 @@ uint8 USBFS_HandleStandardRqst(void) break; case USBFS_RQST_RCPT_IFC: /* Validate interfaceNumber */ - if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER) { - USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg; requestHandled = USBFS_InitNoDataControlTransfer(); } break; @@ -299,396 +337,422 @@ uint8 USBFS_HandleStandardRqst(void) break; } break; + case USBFS_SET_FEATURE: - switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + switch (bmRequestType & USBFS_RQST_RCPT_MASK) { case USBFS_RQST_RCPT_EP: - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT) { requestHandled = USBFS_SetEndpointHalt(); } break; + case USBFS_RQST_RCPT_DEV: /* Set device REMOTE_WAKEUP */ - if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP) { USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; requestHandled = USBFS_InitNoDataControlTransfer(); } break; + case USBFS_RQST_RCPT_IFC: /* Validate interfaceNumber */ - if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER) { - USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= - (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg; requestHandled = USBFS_InitNoDataControlTransfer(); } break; + default: /* requestHandled is initialized as FALSE by default */ break; } break; + default: /* requestHandled is initialized as FALSE by default */ break; } } - return(requestHandled); + + return (requestHandled); } #if defined(USBFS_ENABLE_IDSN_STRING) - /*************************************************************************** * Function Name: USBFS_ReadDieID - **************************************************************************** + ************************************************************************//** * - * Summary: * This routine read Die ID and generate Serial Number string descriptor. * - * Parameters: - * descr: pointer on string descriptor. + * \param descr: pointer on string descriptor. This string size has to be equal or + * greater than USBFS_IDSN_DESCR_LENGTH. * - * Return: - * None. * - * Reentrant: + * \reentrant * No. * ***************************************************************************/ void USBFS_ReadDieID(uint8 descr[]) { + const char8 CYCODE hex[] = "0123456789ABCDEF"; uint8 i; uint8 j = 0u; - uint8 value; - const char8 CYCODE hex[16u] = "0123456789ABCDEF"; + uint8 uniqueId[8u]; - /* Check descriptor validation */ - if( descr != NULL) + if (NULL != descr) { + /* Initialize descriptor header. */ descr[0u] = USBFS_IDSN_DESCR_LENGTH; descr[1u] = USBFS_DESCR_STRING; + + /* Unique ID size is 8 bytes. */ + CyGetUniqueId((uint32 *) uniqueId); - /* fill descriptor */ - for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) + /* Fill descriptor with unique device ID. */ + for (i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) { - value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j)); - j++; - descr[i] = (uint8)hex[value >> 4u]; - descr[i + 2u] = (uint8)hex[value & 0x0Fu]; + descr[i] = (uint8) hex[(uniqueId[j] >> 4u)]; + descr[i + 1u] = 0u; + descr[i + 2u] = (uint8) hex[(uniqueId[j] & 0x0Fu)]; + descr[i + 3u] = 0u; + ++j; } } } - -#endif /* USBFS_ENABLE_IDSN_STRING */ +#endif /* (USBFS_ENABLE_IDSN_STRING) */ /******************************************************************************* * Function Name: USBFS_ConfigReg -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine configures hardware registers from the variables. * It is called from USBFS_Config() function and from RestoreConfig * after Wakeup. * -* Parameters: -* None. -* -* Return: -* None. -* *******************************************************************************/ void USBFS_ConfigReg(void) { uint8 ep; - uint8 i; - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - uint8 epType = 0u; - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ - /* Set the endpoint buffer addresses */ - ep = USBFS_EP1; - for (i = 0u; i < 0x80u; i+= 0x10u) +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + uint8 epType = 0u; +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Go thought all endpoints and set hardware configuration */ + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep) { - CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT); - #if(USBFS_EP_MM != USBFS__EP_MANUAL) - /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */ - CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK); - #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ - - if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) + USBFS_ARB_EP_BASE.arbEp[ep].epCfg = USBFS_ARB_EPX_CFG_DEFAULT; + + #if (USBFS_EP_MANAGEMENT_DMA) + /* Enable arbiter endpoint interrupt sources */ + USBFS_ARB_EP_BASE.arbEp[ep].epIntEn = USBFS_ARB_EPX_INT_MASK; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + if (USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) { - if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u ) + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN); + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) + /* Clear DMA_TERMIN for IN endpoint. */ + USBFS_ARB_EP_BASE.arbEp[ep].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) */ } else { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT); - /* Prepare EP type mask for automatic memory allocation */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - epType |= (uint8)(0x01u << (ep - USBFS_EP1)); - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* (CY_PSOC4): DMA_TERMIN for OUT endpoint is set above. */ + + /* Prepare endpoint type mask. */ + epType |= (uint8) (0x01u << (ep - USBFS_EP1)); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ } } else { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP); + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_STALL_DATA_EP; } - - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); - - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); - #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ - - ep++; + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + USBFS_ARB_EP16_BASE.arbEp[ep].rwRa16 = (uint32) USBFS_EP[ep].buffOffset; + USBFS_ARB_EP16_BASE.arbEp[ep].rwWa16 = (uint32) USBFS_EP[ep].buffOffset; + #else + USBFS_ARB_EP_BASE.arbEp[ep].rwRa = LO8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwRaMsb = HI8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwWa = LO8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = HI8(USBFS_EP[ep].buffOffset); + #endif /* (CY_PSOC4) */ + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ } - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ - USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; - USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */ - USBFS_DMA_THRES_MSB_REG = 0u; - USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK; - USBFS_EP_TYPE_REG = epType; - /* Cfg_cmp bit set to 1 once configuration is complete. */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM | - USBFS_ARB_CFG_CFG_CPM; - /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ - USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* BUF_SIZE depend on DMA_THRESS value:0x55-32 bytes 0x44-16 bytes 0x33-8 bytes 0x22-4 bytes 0x11-2 bytes */ + USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; - CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu); + /* Configure DMA burst threshold */ +#if (CY_PSOC4) + USBFS_DMA_THRES16_REG = USBFS_DMA_BYTES_PER_BURST; +#else + USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; + USBFS_DMA_THRES_MSB_REG = 0u; +#endif /* (CY_PSOC4) */ + USBFS_EP_ACTIVE_REG = USBFS_DEFAULT_ARB_INT_EN; + USBFS_EP_TYPE_REG = epType; + + /* Cfg_cmp bit set to 1 once configuration is complete. */ + /* Lock arbiter configtuation */ + USBFS_ARB_CFG_REG |= (uint8) USBFS_ARB_CFG_CFG_CMP; + /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ + USBFS_ARB_CFG_REG &= (uint8) ~USBFS_ARB_CFG_CFG_CMP; + +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Enable interrupt SIE interurpt source from EP0-EP1 */ + USBFS_SIE_EP_INT_EN_REG = (uint8) USBFS_DEFAULT_SIE_EP_INT_EN; +} + + +/******************************************************************************* +* Function Name: USBFS_EpStateInit +****************************************************************************//** +* +* This routine initialize state of Data end points based of its type: +* IN - USBFS_IN_BUFFER_EMPTY (USBFS_EVENT_PENDING) +* OUT - USBFS_OUT_BUFFER_EMPTY (USBFS_NO_EVENT_PENDING) +* +*******************************************************************************/ +void USBFS_EpStateInit(void) +{ + uint8 i; + + for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + { + if (0u != (USBFS_EP[i].addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + } + } + } /******************************************************************************* * Function Name: USBFS_Config -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine configures endpoints for the entire configuration by scanning * the configuration descriptor. * -* Parameters: -* clearAltSetting: It configures the bAlternateSetting 0 for each interface. -* -* Return: -* None. +* \param clearAltSetting: It configures the bAlternateSetting 0 for each interface. * * USBFS_interfaceClass - Initialized class array for each interface. * It is used for handling Class specific requests depend on interface class. * Different classes in multiple Alternate settings does not supported. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_Config(uint8 clearAltSetting) { uint8 ep; - uint8 cur_ep; + uint8 curEp; uint8 i; uint8 epType; const uint8 *pDescr; - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) uint16 buffCount = 0u; - #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ const T_USBFS_LUT CYCODE *pTmp; const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; - /* Clear all of the endpoints */ - for (ep = 0u; ep < USBFS_MAX_EP; ep++) + /* Clear endpoints settings */ + for (ep = 0u; ep < USBFS_MAX_EP; ++ep) { - USBFS_EP[ep].attrib = 0u; - USBFS_EP[ep].hwEpState = 0u; - USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[ep].epToggle = 0u; - USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; + USBFS_EP[ep].attrib = 0u; + USBFS_EP[ep].hwEpState = 0u; + USBFS_EP[ep].epToggle = 0u; USBFS_EP[ep].bufferSize = 0u; - USBFS_EP[ep].interface = 0u; - + USBFS_EP[ep].interface = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; } - /* Clear Alternate settings for all interfaces */ - if(clearAltSetting != 0u) + /* Clear Alternate settings for all interfaces. */ + if (0u != clearAltSetting) { - for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; ++i) { - USBFS_interfaceSetting[i] = 0x00u; - USBFS_interfaceSetting_last[i] = 0x00u; + USBFS_interfaceSetting[i] = 0u; + USBFS_interfaceSettingLast[i] = 0u; } } /* Init Endpoints and Device Status if configured */ - if(USBFS_configuration > 0u) + if (USBFS_configuration > 0u) { + #if defined(USBFS_ENABLE_CDC_CLASS) + uint8 cdcComNums = 0u; + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + /* Set Power status for current configuration */ pDescr = (const uint8 *)pTmp->p_list; - if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) + if ((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) { - USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED; } else { - USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; + USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED; } + /* Move to next element */ pTmp = &pTmp[1u]; ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ - #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ - (USBFS_EP_MM == USBFS__EP_MANUAL) ) + #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) /* Configure for dynamic EP memory allocation */ /* p_list points the endpoint setting table. */ pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; + for (i = 0u; i < ep; i++) - { + { /* Compare current Alternate setting with EP Alt */ - if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - { - cur_ep = pEP->addr & USBFS_DIR_UNUSED; + if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + curEp = pEP->addr & USBFS_DIR_UNUSED; epType = pEP->attributes & USBFS_EP_TYPE_MASK; - if (pEP->addr & USBFS_DIR_IN) + + USBFS_EP[curEp].addr = pEP->addr; + USBFS_EP[curEp].attrib = pEP->attributes; + USBFS_EP[curEp].bufferSize = pEP->bufferSize; + + if (0u != (pEP->addr & USBFS_DIR_IN)) { /* IN Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (epType != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_in_ep = cur_ep; - } - #endif /* USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (epType == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_in_ep = cur_ep; - } - #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = curEp; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ } else { /* OUT Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (epType != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_out_ep = cur_ep; - } - #endif /* USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (epType == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_out_ep = cur_ep; - } - #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = curEp; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ } - USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - USBFS_EP[cur_ep].addr = pEP->addr; - USBFS_EP[cur_ep].attrib = pEP->attributes; + + #if(defined (USBFS_ENABLE_CDC_CLASS)) + if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC)) + { + cdcComNums = USBFS_Cdc_EpInit(pEP, curEp, cdcComNums); + } + #endif /* (USBFS_ENABLE_CDC_CLASS) */ } + pEP = &pEP[1u]; } - #else /* Configure for static EP memory allocation */ - for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + + #else + for (i = USBFS_EP1; i < USBFS_MAX_EP; ++i) { /* p_list points the endpoint setting table. */ pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; /* Find max length for each EP and select it (length could be different in different Alt settings) */ /* but other settings should be correct with regards to Interface alt Setting */ - for (cur_ep = 0u; cur_ep < ep; cur_ep++) + + for (curEp = 0u; curEp < ep; ++curEp) { - /* EP count is equal to EP # in table and we found larger EP length than have before*/ - if(i == (pEP->addr & USBFS_DIR_UNUSED)) + if (i == (pEP->addr & USBFS_DIR_UNUSED)) { - if(USBFS_EP[i].bufferSize < pEP->bufferSize) + /* Compare endpoint buffers size with current size to find greater. */ + if (USBFS_EP[i].bufferSize < pEP->bufferSize) { USBFS_EP[i].bufferSize = pEP->bufferSize; } - /* Compare current Alternate setting with EP Alt*/ - if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) - { + + /* Compare current Alternate setting with EP Alt */ + if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + USBFS_EP[i].addr = pEP->addr; + USBFS_EP[i].attrib = pEP->attributes; + epType = pEP->attributes & USBFS_EP_TYPE_MASK; - if ((pEP->addr & USBFS_DIR_IN) != 0u) + + if (0u != (pEP->addr & USBFS_DIR_IN)) { /* IN Endpoint */ + USBFS_EP[i].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; - USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; - /* Find and initialize CDC IN endpoint number */ - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (epType != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_in_ep = i; - } - #endif /* USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_IN_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (epType == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_in_ep = i; - } - #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = i; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ } else { /* OUT Endpoint */ + USBFS_EP[i].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; - /* Find and initialize CDC IN endpoint number */ - #if defined(USBFS_ENABLE_CDC_CLASS) - if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || - (pEP->bMisc == USBFS_CLASS_CDC)) && - (epType != USBFS_EP_TYPE_INT)) - { - USBFS_cdc_data_out_ep = i; - } - #endif /* USBFS_ENABLE_CDC_CLASS*/ - #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ - (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) - if((pEP->bMisc == USBFS_CLASS_AUDIO) && - (epType == USBFS_EP_TYPE_BULK)) - { - USBFS_midi_out_ep = i; - } - #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = i; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ } - USBFS_EP[i].addr = pEP->addr; - USBFS_EP[i].attrib = pEP->attributes; - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - break; /* use first EP setting in Auto memory managment */ - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #if (defined(USBFS_ENABLE_CDC_CLASS)) + if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC)) + { + cdcComNums = USBFS_Cdc_EpInit(pEP, i, cdcComNums); + } + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + break; /* Use first EP setting in Auto memory management */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ } } + pEP = &pEP[1u]; } } - #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */ /* Init class array for each interface and interface number for each EP. * It is used for handling Class specific requests directed to either an @@ -698,170 +762,181 @@ void USBFS_Config(uint8 clearAltSetting) pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; for (i = 0u; i < ep; i++) { - /* Configure interface number for each EP*/ + /* Configure interface number for each EP */ USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; pEP = &pEP[1u]; } - /* Init pointer on interface class table*/ + + /* Init pointer on interface class table */ USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); - /* Set the endpoint buffer addresses */ - - #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) - for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) - { - USBFS_EP[ep].buffOffset = buffCount; - buffCount += USBFS_EP[ep].bufferSize; - } - #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Set the endpoint buffer addresses */ + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + buffCount = 0u; + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep) + { + USBFS_EP[ep].buffOffset = buffCount; + buffCount += USBFS_EP[ep].bufferSize; + + #if (USBFS_GEN_16BITS_EP_ACCESS) + /* Align EP buffers to be event size to access 16-bits DR register. */ + buffCount += (0u != (buffCount & 0x01u)) ? 1u : 0u; + #endif /* (USBFS_GEN_16BITS_EP_ACCESS) */ + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ /* Configure hardware registers */ USBFS_ConfigReg(); - } /* USBFS_configuration > 0 */ + } } /******************************************************************************* * Function Name: USBFS_ConfigAltChanged -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine update configuration for the required endpoints only. * It is called after SET_INTERFACE request when Static memory allocation used. * -* Parameters: -* None. -* -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * *******************************************************************************/ void USBFS_ConfigAltChanged(void) { uint8 ep; - uint8 cur_ep; - uint8 i; + uint8 curEp; uint8 epType; - uint8 ri; + uint8 i; + uint8 interfaceNum; const T_USBFS_LUT CYCODE *pTmp; const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; - /* Init Endpoints and Device Status if configured */ - if(USBFS_configuration > 0u) + if (USBFS_configuration > 0u) { + /* Get number of endpoints configurations (ep). */ pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); pTmp = &pTmp[1u]; - ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + ep = pTmp->c; - /* Do not touch EP which doesn't need reconfiguration */ - /* When Alt setting changed, the only required endpoints need to be reconfigured */ - /* p_list points the endpoint setting table. */ + /* Get pointer to endpoints setting table (pEP). */ pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + + /* Look through all possible endpoint configurations. Find endpoints + * which belong to current interface and alternate settings for + * re-configuration. + */ + interfaceNum = USBFS_interfaceNumber; for (i = 0u; i < ep; i++) { - /*If Alt setting changed and new is same with EP Alt */ - if((USBFS_interfaceSetting[pEP->interface] != - USBFS_interfaceSetting_last[pEP->interface] ) && - (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && - (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) + /* Find endpoints which belong to current interface and alternate settings. */ + if ((interfaceNum == pEP->interface) && + (USBFS_interfaceSetting[interfaceNum] == pEP->altSetting)) { - cur_ep = pEP->addr & USBFS_DIR_UNUSED; - ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - epType = pEP->attributes & USBFS_EP_TYPE_MASK; - if ((pEP->addr & USBFS_DIR_IN) != 0u) + curEp = ((uint8) pEP->addr & USBFS_DIR_UNUSED); + epType = ((uint8) pEP->attributes & USBFS_EP_TYPE_MASK); + + /* Change the SIE mode for the selected EP to NAK ALL */ + USBFS_EP[curEp].epToggle = 0u; + USBFS_EP[curEp].addr = pEP->addr; + USBFS_EP[curEp].attrib = pEP->attributes; + USBFS_EP[curEp].bufferSize = pEP->bufferSize; + + if (0u != (pEP->addr & USBFS_DIR_IN)) { /* IN Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING; } else { /* OUT Endpoint */ - USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; - USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? - USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING; } - /* Change the SIE mode for the selected EP to NAK ALL */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); - USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; - USBFS_EP[cur_ep].addr = pEP->addr; - USBFS_EP[cur_ep].attrib = pEP->attributes; + + /* Make SIE to NAK any endpoint requests */ + USBFS_SIE_EP_BASE.sieEp[curEp].epCr0 = USBFS_MODE_NAK_IN_OUT; - /* Clear the data toggle */ - USBFS_EP[cur_ep].epToggle = 0u; + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Clear IN data ready. */ + USBFS_ARB_EP_BASE.arbEp[curEp].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY; - /* Dynamic reconfiguration for mode 3 transfer */ - #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) - /* In_data_rdy for selected EP should be set to 0 */ - * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; - - /* write the EP number for which reconfiguration is required */ - USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) << - USBFS_DYN_RECONFIG_EP_SHIFT; - /* Set the dyn_config_en bit in dynamic reconfiguration register */ + /* Select endpoint number of reconfiguration */ + USBFS_DYN_RECONFIG_REG = (uint8) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT); + + /* Request for dynamic re-configuration of endpoint. */ USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; - /* wait for the dyn_config_rdy bit to set by the block, - * this bit will be set to 1 when block is ready for reconfiguration. - */ - while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u) + + /* Wait until block is ready for re-configuration */ + while (0u == (USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS)) { - ; } - /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ + + /* Once DYN_RECONFIG_RDY_STS bit is set, FW can change the EP configuration. */ /* Change EP Type with new direction */ - if((pEP->addr & USBFS_DIR_IN) == 0u) + if (0u != (pEP->addr & USBFS_DIR_IN)) { - USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1)); + /* Set endpoint type: 0 - IN and 1 - OUT. */ + USBFS_EP_TYPE_REG &= (uint8) ~(uint8)((uint8) 0x01u << (curEp - 1u)); + + #if (CY_PSOC4) + /* Clear DMA_TERMIN for IN endpoint */ + USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (CY_PSOC4) */ } else { - USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1)); + /* Set endpoint type: 0 - IN and 1- OUT. */ + USBFS_EP_TYPE_REG |= (uint8) ((uint8) 0x01u << (curEp - 1u)); + + #if (CY_PSOC4) + /* Set DMA_TERMIN for OUT endpoint */ + USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn |= (uint32) USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (CY_PSOC4) */ } - /* dynamic reconfiguration enable bit cleared, pointers and control/status - * signals for the selected EP is cleared/re-initialized on negative edge - * of dynamic reconfiguration enable bit). + + /* Complete dynamic re-configuration: all endpoint related status and signals + * are set into the default state. */ - USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE; - /* The main loop has to re-enable DMA and OUT endpoint*/ + USBFS_DYN_RECONFIG_REG &= (uint8) ~USBFS_DYN_RECONFIG_ENABLE; + #else - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), - USBFS_EP[cur_ep].bufferSize >> 8u); - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), - USBFS_EP[cur_ep].bufferSize & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), - USBFS_EP[cur_ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), - USBFS_EP[cur_ep].buffOffset >> 8u); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), - USBFS_EP[cur_ep].buffOffset & 0xFFu); - CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), - USBFS_EP[cur_ep].buffOffset >> 8u); - #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + USBFS_SIE_EP_BASE.sieEp[curEp].epCnt0 = HI8(USBFS_EP[curEp].bufferSize); + USBFS_SIE_EP_BASE.sieEp[curEp].epCnt1 = LO8(USBFS_EP[curEp].bufferSize); + + #if (CY_PSOC4) + USBFS_ARB_EP16_BASE.arbEp[curEp].rwRa16 = (uint32) USBFS_EP[curEp].buffOffset; + USBFS_ARB_EP16_BASE.arbEp[curEp].rwWa16 = (uint32) USBFS_EP[curEp].buffOffset; + #else + USBFS_ARB_EP_BASE.arbEp[curEp].rwRa = LO8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwRaMsb = HI8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwWa = LO8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwWaMsb = HI8(USBFS_EP[curEp].buffOffset); + #endif /* (CY_PSOC4) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ } - /* Get next EP element */ - pEP = &pEP[1u]; + + pEP = &pEP[1u]; /* Get next EP element */ } - } /* USBFS_configuration > 0 */ + + /* The main loop has to re-enable DMA and OUT endpoint */ + } } /******************************************************************************* * Function Name: USBFS_GetConfigTablePtr -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine returns a pointer a configuration table entry * -* Parameters: -* confIndex: Configuration Index +* \param confIndex: Configuration Index * -* Return: -* Device Descriptor pointer or NULL when descriptor isn't exists. +* \return +* Device Descriptor pointer or NULL when descriptor does not exist. * *******************************************************************************/ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) @@ -873,10 +948,11 @@ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; /* The first entry points to the Device Descriptor, + * the second entry point to the BOS Descriptor * the rest configuration entries. * Set pointer to the first Configuration Descriptor */ - pTmp = &pTmp[1u]; + pTmp = &pTmp[2u]; /* For this table, c is the number of configuration descriptors */ if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */ { @@ -887,21 +963,48 @@ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list; } - return( pTmp ); + return (pTmp); } +#if (USBFS_BOS_ENABLE) + /******************************************************************************* + * Function Name: USBFS_GetBOSPtr + ****************************************************************************//** + * + * This routine returns a pointer a BOS table entry + * + * + * + * \return + * BOS Descriptor pointer or NULL when descriptor does not exist. + * + *******************************************************************************/ + const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) + + { + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the second entry points to the BOS Descriptor + */ + pTmp = &pTmp[1u]; + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + return (pTmp); + } +#endif /* (USBFS_BOS_ENABLE) */ + + /******************************************************************************* * Function Name: USBFS_GetDeviceTablePtr -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine returns a pointer to the Device table * -* Parameters: -* None. -* -* Return: +* \return * Device Table pointer * *******************************************************************************/ @@ -915,16 +1018,12 @@ const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) /******************************************************************************* * Function Name: USB_GetInterfaceClassTablePtr -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine returns Interface Class table pointer, which contains * the relation between interface number and interface class. * -* Parameters: -* None. -* -* Return: +* \return * Interface Class table pointer. * *******************************************************************************/ @@ -936,7 +1035,7 @@ const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) uint8 currentInterfacesNum; pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - if( pTmp != NULL ) + if (pTmp != NULL) { currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; /* Third entry in the LUT starts the Interface Table pointers */ @@ -949,53 +1048,50 @@ const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) pInterfaceClass = (const uint8 CYCODE *) NULL; } - return( pInterfaceClass ); + return (pInterfaceClass); } /******************************************************************************* * Function Name: USBFS_TerminateEP -******************************************************************************** +****************************************************************************//** * -* Summary: * This function terminates the specified USBFS endpoint. * This function should be used before endpoint reconfiguration. * -* Parameters: -* Endpoint number. +* \param ep Contains the data endpoint number. * -* Return: -* None. -* -* Reentrant: +* \reentrant * No. * +* \sideeffect +* +* The device responds with a NAK for any transactions on the selected endpoint. +* *******************************************************************************/ -void USBFS_TerminateEP(uint8 ep) +void USBFS_TerminateEP(uint8 epNumber) { - uint8 ri; + /* Get endpoint number */ + epNumber &= USBFS_DIR_UNUSED; - ep &= USBFS_DIR_UNUSED; - ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); - - if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) { /* Set the endpoint Halt */ - USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + USBFS_EP[epNumber].hwEpState |= USBFS_ENDPOINT_STATUS_HALT; /* Clear the data toggle */ - USBFS_EP[ep].epToggle = 0u; - USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED; + USBFS_EP[epNumber].epToggle = 0u; + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_ALLOWED; - if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) - { + if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u) + { /* IN Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_IN; } else { /* OUT Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT; } } } @@ -1003,30 +1099,24 @@ void USBFS_TerminateEP(uint8 ep) /******************************************************************************* * Function Name: USBFS_SetEndpointHalt -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine handles set endpoint halt. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_SetEndpointHalt(void) { - uint8 ep; - uint8 ri; uint8 requestHandled = USBFS_FALSE; - + uint8 ep; + /* Set endpoint halt */ - ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED; if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) { @@ -1040,86 +1130,84 @@ uint8 USBFS_SetEndpointHalt(void) if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) { /* IN Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | - USBFS_MODE_ACK_IN); + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_IN); } else { /* OUT Endpoint */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | - USBFS_MODE_ACK_OUT); + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_OUT); } requestHandled = USBFS_InitNoDataControlTransfer(); } - return(requestHandled); + return (requestHandled); } /******************************************************************************* * Function Name: USBFS_ClearEndpointHalt -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine handles clear endpoint halt. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_ClearEndpointHalt(void) { - uint8 ep; - uint8 ri; uint8 requestHandled = USBFS_FALSE; + uint8 ep; /* Clear endpoint halt */ - ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; - ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED; if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) { /* Clear the endpoint Halt */ - USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT); + USBFS_EP[ep].hwEpState &= (uint8) ~USBFS_ENDPOINT_STATUS_HALT; /* Clear the data toggle */ USBFS_EP[ep].epToggle = 0u; + /* Clear toggle bit for already armed packet */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8( - (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); + USBFS_SIE_EP_BASE.sieEp[ep].epCnt0 = (uint8) ~(uint8)USBFS_EPX_CNT_DATA_TOGGLE; + /* Return API State as it was defined before */ - USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED; + USBFS_EP[ep].apiEpState &= (uint8) ~USBFS_NO_EVENT_ALLOWED; if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) { /* IN Endpoint */ if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) - { /* Wait for next packet from application */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + { + /* Wait for next packet from application */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN; } else /* Continue armed transfer */ { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN); + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_IN; } } else { /* OUT Endpoint */ - if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) - { /* Allow application to read full buffer */ - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + if (USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { + /* Allow application to read full buffer */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT; } else /* Mark endpoint as empty, so it will be reloaded */ { - CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_OUT; } } + requestHandled = USBFS_InitNoDataControlTransfer(); } @@ -1129,42 +1217,42 @@ uint8 USBFS_ClearEndpointHalt(void) /******************************************************************************* * Function Name: USBFS_ValidateAlternateSetting -******************************************************************************** +****************************************************************************//** * -* Summary: * Validates (and records) a SET INTERFACE request. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ uint8 USBFS_ValidateAlternateSetting(void) { - uint8 requestHandled = USBFS_TRUE; + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNum; + uint8 curInterfacesNum; const T_USBFS_LUT CYCODE *pTmp; - uint8 currentInterfacesNum; - - interfaceNum = CY_GET_REG8(USBFS_wIndexLo); - /* Validate interface setting, stall if invalid. */ + + /* Get interface number from the request. */ + interfaceNum = (uint8) USBFS_wIndexLoReg; + + /* Get number of interfaces for current configuration. */ pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); - currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + curInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; - if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER)) - { /* Wrong interface number */ - requestHandled = USBFS_FALSE; - } - else + /* Validate that interface number is within range. */ + if ((interfaceNum <= curInterfacesNum) || (interfaceNum <= USBFS_MAX_INTERFACES_NUMBER)) { - /* Save current Alt setting to find out the difference in Config() function */ - USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; - USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo); + /* Save current and new alternate settings (come with request) to make + * desicion about following endpoint re-configuration. + */ + USBFS_interfaceSettingLast[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; + USBFS_interfaceSetting[interfaceNum] = (uint8) USBFS_wValueLoReg; + + requestHandled = USBFS_TRUE; } return (requestHandled); diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c index 78e95ad..e509cfd 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c @@ -1,26 +1,23 @@ -/******************************************************************************* -* File Name: USBFS_vnd.c -* Version 2.80 +/***************************************************************************//** +* \file USBFS_vnd.c +* \version 3.10 * -* Description: -* USB vendor request handler. -* -* Note: +* \brief +* This file contains the USB vendor request handler. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ -#include "USBFS.h" #include "USBFS_pvt.h" #if(USBFS_EXTERN_VND == USBFS_FALSE) - /*************************************** * Vendor Specific Declarations ***************************************/ @@ -32,9 +29,8 @@ /******************************************************************************* * Function Name: USBFS_HandleVendorRqst -******************************************************************************** +****************************************************************************//** * -* Summary: * This routine provide users with a method to implement vendor specific * requests. * @@ -43,13 +39,10 @@ * must set the variable "requestHandled" to TRUE, indicating that the * request has been handled. * -* Parameters: -* None. -* -* Return: +* \return * requestHandled. * -* Reentrant: +* \reentrant * No. * *******************************************************************************/ @@ -57,18 +50,21 @@ uint8 USBFS_HandleVendorRqst(void) { uint8 requestHandled = USBFS_FALSE; - if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) { - /* Control Read */ - switch (CY_GET_REG8(USBFS_bRequest)) + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) { case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: - #if defined(USBFS_ENABLE_MSOS_STRING) - USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u]; - USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; - requestHandled = USBFS_InitControlRead(); - #endif /* USBFS_ENABLE_MSOS_STRING */ + #if defined(USBFS_ENABLE_MSOS_STRING) + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_MSOS_CONFIGURATION_DESCR[0u]; + USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; + requestHandled = USBFS_InitControlRead(); + #endif /* (USBFS_ENABLE_MSOS_STRING) */ break; + default: break; } @@ -78,11 +74,14 @@ uint8 USBFS_HandleVendorRqst(void) /* `#END` */ - #ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK - USBFS_HandleVendorRqst_Callback(); - #endif /* USBFS_HANDLE_VENDOR_RQST_CALLBACK */ +#ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK + if (USBFS_FALSE == requestHandled) + { + requestHandled = USBFS_HandleVendorRqst_Callback(); + } +#endif /* (USBFS_HANDLE_VENDOR_RQST_CALLBACK) */ - return(requestHandled); + return (requestHandled); } @@ -94,6 +93,7 @@ uint8 USBFS_HandleVendorRqst(void) /* `#END` */ + #endif /* USBFS_EXTERN_VND */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld old mode 100644 new mode 100755 index 3504994..13b5097 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -20,15 +20,19 @@ ENTRY(__cy_reset) SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) +/* Code sharing support */ +INCLUDE cycodeshareexport.ld +INCLUDE cycodeshareimport.ld + MEMORY { - rom (rx) : ORIGIN = 0x0, LENGTH = 131072 - ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 } -CY_APPL_ORIGIN = 0; +CY_APPL_ORIGIN = 0; CY_FLASH_ROW_SIZE = 256; CY_ECC_ROW_SIZE = 32; CY_EE_IN_BTLDR = 0x00; @@ -37,6 +41,8 @@ CY_EE_SIZE = 2048; CY_APPL_NUM = 1; CY_APPL_MAX = 1; CY_METADATA_SIZE = 64; +CY_APPL_LOADABLE = 1; +CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE); /* These force the linker to search for particular symbols from @@ -61,235 +67,327 @@ PROVIDE(__cy_heap_end = __cy_stack - 0x1000); SECTIONS { - /* The bootloader location */ - .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom - /* Calculate where the loadables should start */ - appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); - appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); - appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; - ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; - ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; - ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; - PROVIDE(CY_ECC_OFFSET = ecc_offset); - - .text appl_start : - { - CREATE_OBJECT_SYMBOLS - PROVIDE(__cy_interrupt_vector = RomVectors); + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; + ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + PROVIDE(CY_ECC_OFFSET = ecc_offset); - *(.romvectors) + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); - /* Make sure we pulled in an interrupt vector. */ - ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + *(.romvectors) - ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); - PROVIDE(__cy_reset = Reset); - *(.text.Reset) - /* Make sure we pulled in some reset code. */ - ASSERT (. != __cy_reset, "No reset code"); + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); - /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */ - *(.dma_init) - ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); - - *(.text .text.* .gnu.linkonce.t.*) - *(.plt) - *(.gnu.warning) - *(.glue_7t) *(.glue_7) *(.vfp11_veneer) - - KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + PROVIDE(__cy_reset = Reset); + *(.text.Reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); - *(.ARM.extab* .gnu.linkonce.armextab.*) - *(.gcc_except_table) - } >rom - .eh_frame_hdr : ALIGN (4) - { - KEEP (*(.eh_frame_hdr)) - } >rom - .eh_frame : ALIGN (4) - { - KEEP (*(.eh_frame)) - } >rom - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } >rom - __exidx_end = .; - .rodata : ALIGN (4) - { - *(.rodata .rodata.* .gnu.linkonce.r.*) + /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */ + *(.dma_init) + ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); - . = ALIGN(4); - KEEP(*(.init)) + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - __cy_regions = .; - LONG (__cy_region_init_ram) - LONG (__cy_region_start_data) - LONG (__cy_region_init_size_ram) - LONG (__cy_region_zero_size_ram) - __cy_regions_end = .; - - . = ALIGN (8); - _etext = .; + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) } >rom - .ramvectors (NOLOAD) : ALIGN(8) - { - __cy_region_start_ram = .; - KEEP(*(.ramvectors)) - } - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom - .data : ALIGN(8) - { - __cy_region_start_data = .; - KEEP(*(.jcr)) - *(.got.plt) *(.got) - *(.shdata) - *(.data .data.* .gnu.linkonce.d.*) - . = ALIGN (8); - *(.ram) - _edata = .; - } >ram AT>rom - .bss : ALIGN(8) - { - PROVIDE(__bss_start__ = .); - *(.shbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - *(.ram.b) - _end = .; - __end = .; - } >ram AT>rom - PROVIDE(end = .); - PROVIDE(__bss_end__ = .); - - __cy_region_init_ram = LOADADDR (.data); - __cy_region_init_size_ram = _edata - ADDR (.data); - __cy_region_zero_size_ram = _end - _edata; - - /* The .stack and .heap sections don't contain any symbols. - * They are only used for linker to calculate RAM utilization. - */ - .heap (NOLOAD) : - { - . = _end; - . += 0x0400; - __cy_heap_limit = .; - } >ram + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom - .stack (__cy_stack - 0x1000) (NOLOAD) : - { - __cy_stack_limit = .; - . += 0x1000; - } >ram - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") - .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : - { - KEEP(*(.cyloadermeta)) - } :NONE + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; - .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : - { - KEEP(*(.cyloadablemeta)) - } >rom - .cyconfigecc (0x80000000 + ecc_offset) : - { - KEEP(*(.cyconfigecc)) - } :NONE + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) - .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE - .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE + . = ALIGN(4); + KEEP(*(.init)) - .cyeeprom (0x90200000 + ee_offset) : - { - KEEP(*(.cyeeprom)) - ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); - } :NONE + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; - .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; - .stab 0 (NOLOAD) : { *(.stab) } - .stabstr 0 (NOLOAD) : { *(.stabstr) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. - */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* DWARF 2.1 */ - .debug_ranges 0 : { *(.debug_ranges) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } + . = ALIGN(4); + KEEP(*(.fini)) - .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } - .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } - /DISCARD/ : { *(.note.GNU-stack) } + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + + /*************************************************************************** + * Checksum Exclude Section for non-bootloadable projects. See below. + ***************************************************************************/ + + + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + + + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + + + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x0400; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x1000) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x1000; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + + /*************************************************************************** + * Checksum Exclude Section + *************************************************************************** + * + * For the normal and bootloader projects this section is placed at any + * place. For the Bootloadable applications, it is placed at the specific + * address. + * + * Case # 1. Bootloadable application + * + * _______________________________ + * | Metadata (BTLDBL) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | | + * | | + * | BTLDBL | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDR | + * |_______________________________| + * + * + * Case # 2. Bootloadable application for Dual-Application Bootloader + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 2 | + * |_______________________________|____BTLDBL # 2 Start address___ + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + */ + .cy_checksum_exclude ((LENGTH(rom) - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE): { KEEP(*(.cy_checksum_exclude)) } + + + /* Bootloadable applications only: verify that size of the data in the section is within the specified limit. */ + cy_checksum_exclude_size = (CY_APPL_LOADABLE == 1) ? SIZEOF(.cy_checksum_exclude) : 0; + ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.") + + + .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : + { + KEEP(*(.cyloadermeta)) + } :NONE + + .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + + .cyconfigecc (0x80000000 + ecc_offset) : + { + KEEP(*(.cyconfigecc)) + } :NONE + + .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE + .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE + + .cyeeprom (0x90200000 + ee_offset) : + { + KEEP(*(.cyeeprom)) + ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); + } :NONE + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } } diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h new file mode 100755 index 0000000..74c49c6 --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h new file mode 100755 index 0000000..bb89fbb --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h index 0e215fc..34ed84c 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h @@ -1,13 +1,10 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * + * @version V4.30 + * @date 20. October 2015 ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,18 +32,23 @@ ---------------------------------------------------------------------------*/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
@@ -63,78 +65,107 @@ /******************************************************************************* * CMSIS definitions ******************************************************************************/ -/** \ingroup Cortex_M3 +/** + \ingroup Cortex_M3 @{ */ /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler #endif -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all */ -#define __FPU_USED 0 +#define __FPU_USED 0U #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + #endif -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif #endif /* __CORE_CM3_H_GENERIC */ @@ -143,25 +174,29 @@ #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT +#ifdef __cplusplus + extern "C" { +#endif + /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV - #define __CM3_REV 0x0200 + #define __CM3_REV 0x0200U #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 + #define __MPU_PRESENT 0U #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 + #define __NVIC_PRIO_BITS 4U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 + #define __Vendor_SysTickConfig 0U #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif @@ -175,12 +210,17 @@ \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ + #define __I volatile /*!< Defines 'read only' permissions */ #else - #define __I volatile const /*!< Defines 'read only' permissions */ + #define __I volatile const /*!< Defines 'read only' permissions */ #endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ /*@} end of group Cortex_M3 */ @@ -196,1062 +236,1152 @@ - Core Debug Register - Core MPU Register ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. @{ */ -/** \brief Union type to access the Application Program Status Register (APSR). +/** + \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ -/** \brief Union type to access the Interrupt Program Status Register (IPSR). +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ -/** \brief Union type to access the Control Registers (CONTROL). +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers @{ */ -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers @{ */ -/** \brief Structure type to access the System Control Block (SCB). +/** + \brief Structure type to access the System Control Block (SCB). */ typedef struct { - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB @{ */ -/** \brief Structure type to access the System Control and ID Register not in the SCB. +/** + \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else - uint32_t RESERVED1[1]; + uint32_t RESERVED1[1U]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. @{ */ -/** \brief Structure type to access the System Timer (SysTick). +/** + \brief Structure type to access the System Timer (SysTick). */ typedef struct { - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { - __O union + __OM union { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) @{ */ -/** \brief Structure type to access the Trace Port Interface Register (TPI). +/** + \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) @{ */ -/** \brief Structure type to access the Memory Protection Unit (MPU). +/** + \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers @{ */ -/** \brief Structure type to access the Core Debug Register (CoreDebug). +/** + \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ @@ -1266,239 +1396,236 @@ typedef struct - Core Debug Functions - Core Register Access Functions ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ */ -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } } -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1506,40 +1633,40 @@ __STATIC_INLINE void NVIC_SystemReset(void) /* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. @{ */ -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. +#if (__Vendor_SysTickConfig == 0U) +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1549,49 +1676,52 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) /* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. @{ */ -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; } return (ch); } -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ int32_t ch = -1; /* no character available */ - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } @@ -1600,28 +1730,34 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { } -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ -#endif /* __CORE_CM3_H_DEPENDANT */ -#endif /* __CMSIS_GENERIC */ + #ifdef __cplusplus } #endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h old mode 100644 new mode 100755 index 959fde9..9815c07 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -1,17 +1,15 @@ /******************************************************************************* -* File Name: core_cm3_psoc5.h -* Version 4.20 +* \file core_cm3_psoc5.h +* \version 5.50 * -* Description: -* Provides important type information for the PSoC5. This includes types -* necessary for core_cm3.h. +* \brief Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. * -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h index 139bc3c..ca319a5 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h @@ -1,13 +1,10 @@ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * + * @version V4.30 + * @date 20. October 2015 ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,6 +32,12 @@ ---------------------------------------------------------------------------*/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H @@ -43,594 +46,42 @@ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include #endif /*@} end of CMSIS_Core_RegAccFunctions */ - #endif /* __CORE_CMFUNC_H */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h index 0d75f40..a0a5064 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h @@ -1,13 +1,10 @@ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.20 - * @date 05. March 2013 - * - * @note - * + * @version V4.30 + * @date 20. October 2015 ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -35,6 +32,12 @@ ---------------------------------------------------------------------------*/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H @@ -45,641 +48,37 @@ @{ */ -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include #endif diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c old mode 100644 new mode 100755 index 33ecdf4..b56dccd --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c @@ -1,16 +1,15 @@ -/******************************************************************************* -* File Name: cyPm.c -* Version 4.20 +/***************************************************************************//** +* \file cyPm.c +* \version 5.50 * -* Description: -* Provides an API for the power management. +* \brief Provides an API for the power management. * -* Note: -* Documentation of the API's in this file is located in the +* \note Documentation of the API's in this file is located in the * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,6 +18,7 @@ #include "cyPm.h" + /******************************************************************* * Place your includes, defines, and code here. Do not use the merge * region below unless any component datasheet suggests doing so. @@ -47,9 +47,8 @@ static void CyPmHviLviRestore(void) ; /******************************************************************************* * Function Name: CyPmSaveClocks -******************************************************************************** +****************************************************************************//** * -* Summary: * This function is called in preparation for entering sleep or hibernate low * power modes. Saves all the states of the clocking system that do not persist * during sleep/hibernate or that need to be altered in preparation for @@ -67,13 +66,7 @@ static void CyPmHviLviRestore(void) ; * must be set manually to another source before using the * CyPmSaveClocks()/CyPmRestoreClocks() functions. * -* Parameters: -* None -* -* Return: -* None -* -* Side Effects: +* \sideeffect * All peripheral clocks are going to be off after this API method call. * *******************************************************************************/ @@ -254,9 +247,8 @@ void CyPmSaveClocks(void) /******************************************************************************* * Function Name: CyPmRestoreClocks -******************************************************************************** +****************************************************************************//** * -* Summary: * Restores any state that was preserved by the last call to CyPmSaveClocks(). * The Flash wait state setting is also restored. * @@ -272,12 +264,6 @@ void CyPmSaveClocks(void) * The 130 ms is given for the megahertz crystal to stabilize. Its readiness is * not verified after a hold-off timeout. * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyPmRestoreClocks(void) { @@ -340,11 +326,15 @@ void CyPmRestoreClocks(void) /* `#START_MHZ_ECO_TIMEOUT` */ /* `#END` */ + + #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK + CyBoot_CyPmRestoreClocks_EcoTimeout_Callback(); + #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK */ } } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ - /* Temprorary set maximum flash wait cycles */ + /* Temporary set maximum flash wait cycles */ CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); /* XTAL and DSI clocks are ready to be source for Master clock. */ @@ -449,6 +439,10 @@ void CyPmRestoreClocks(void) /* `#START_PLL_TIMEOUT` */ /* `#END` */ + + #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK + CyBoot_CyPmRestoreClocks_PllTimeout_Callback(); + #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK */ } } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ @@ -494,9 +488,8 @@ void CyPmRestoreClocks(void) /******************************************************************************* * Function Name: CyPmAltAct -******************************************************************************** +****************************************************************************//** * -* Summary: * Puts the part into the Alternate Active (Standby) state. The Alternate Active * state can allow for any of the capabilities of the device to be active, but * the operation of this function is dependent on the CPU being disabled during @@ -561,34 +554,33 @@ void CyPmRestoreClocks(void) * PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be * started while device remains in Alternate Active mode. * -* Parameters: -* wakeupTime: Specifies a timer wakeup source and the frequency of that +* \param wakeupTime: Specifies a timer wakeup source and the frequency of that * source. For PSoC 5LP this parameter is ignored. * * Define Time * PM_ALT_ACT_TIME_NONE None -* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second -* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms -* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms -* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms -* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms -* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms -* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms -* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms -* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms -* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms -* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms -* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms -* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* \param PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* \param PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* \param PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* \param PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* \param PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* \param PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* \param PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* \param PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* \param PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* \param PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* \param PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* \param PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* \param PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms * PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms * -* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* \param *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that * specifies how many increments of 10 us to delay. For PSoC 3 silicon the valid range of values is 1 to 256. * -* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if -* a wakeupTime has been specified, the associated timer will be -* included as a wakeup source. +* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified, the associated timer will +* be included as a wakeup source. * * Define Source * PM_ALT_ACT_SRC_NONE None @@ -606,26 +598,23 @@ void CyPmRestoreClocks(void) * PM_ALT_ACT_SRC_ONE_PPS One PPS** * PM_ALT_ACT_SRC_LCD LCD * -* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. -* **Note: CTW and One PPS wakeup signals are in the same mask bit. +* \param *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* \param **Note: CTW and One PPS wakeup signals are in the same mask bit. * * When specifying a Comparator as the wakeupSource, an instance specific define * that will track with the specific comparator that the instance -* is placed into should be used. As an example, for a Comparator instance named MyComp the -* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* is placed into should be used. As an example, for a Comparator instance named +* \param MyComp the value to OR into the mask is: MyComp_ctComp__CMP_MASK. * * When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() * function must be called upon wakeup with a corresponding parameter. Please * refer to the CyPmReadStatus() API in the System Reference Guide for more * information. * -* Return: -* None -* * Reentrant: * No * -* Side Effects: +* \sideeffect * If a wakeupTime other than NONE is specified, then upon exit the state of the * specified timer will be left as specified by wakeupTime with the timer * enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is @@ -721,9 +710,8 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) /******************************************************************************* * Function Name: CyPmSleep -******************************************************************************** +****************************************************************************//** * -* Summary: * Puts the part into the Sleep state. * * Note Before calling this function, you must manually configure the power @@ -761,27 +749,26 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) * intervals and RTC for 1PPS interval. The component must be configured to * generate interrupt. * -* Parameters: -* wakeupTime: Specifies a timer wakeup source and the frequency of that +* \param wakeupTime: Specifies a timer wakeup source and the frequency of that * source. For PSoC 5LP, this parameter is ignored. * * Define Time * PM_SLEEP_TIME_NONE None -* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second -* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms -* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms -* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms -* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms -* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms -* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms -* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms -* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms -* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms -* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms -* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms -* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* \param PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* \param PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* \param PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* \param PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* \param PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* \param PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* \param PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* \param PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* \param PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* \param PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* \param PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* \param PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* \param PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms * -* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if * a wakeupTime has been specified the associated timer will be * included as a wakeup source. * @@ -799,21 +786,18 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) * PM_SLEEP_SRC_ONE_PPS One PPS* * PM_SLEEP_SRC_LCD LCD * -* *Note: CTW and One PPS wakeup signals are in the same mask bit. +* \param *Note: CTW and One PPS wakeup signals are in the same mask bit. * * When specifying a Comparator as the wakeupSource an instance specific define * should be used that will track with the specific comparator that the instance * is placed into. As an example for a Comparator instance named MyComp the -* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* \param value to OR into the mask is: MyComp_ctComp__CMP_MASK. * * When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() * function must be called upon wakeup with corresponding parameter. Please * refer to the CyPmReadStatus() API in the System Reference Guide for more * information. * -* Return: -* None -* * Reentrant: * No * @@ -984,6 +968,9 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) /* `#END` */ + #ifdef CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK + CyBoot_CyPmSleep_BeforeSleep_Callback(); + #endif /* CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK */ /* Last moment IMO frequency change */ if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) @@ -1034,6 +1021,9 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) /* `#END` */ + #ifdef CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK + CyBoot_CyPmSleep_AfterSleep_Callback(); + #endif /* CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK */ /* Restore hardware configuration */ CyPmHibSlpRestore(); @@ -1069,12 +1059,10 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) /******************************************************************************* * Function Name: CyPmHibernate -******************************************************************************** +****************************************************************************//** * -* Summary: * Puts the part into the Hibernate state. * -* PSoC 3 and PSoC 5LP: * Before switching to Hibernate, the current status of the PICU wakeup source * bit is saved and then set. This configures the device to wake up from the * PICU. Make sure you have at least one pin configured to generate PICU @@ -1084,24 +1072,18 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) * option. Once the wakeup occurs, the PICU wakeup source bit is restored and * the PSoC returns to the Active state. * -* Parameters: -* None -* -* Return: -* None -* * Reentrant: * No * -* Side Effects: +* \sideeffect * Applications must wait 20 us before re-entering hibernate or sleep after * waking up from hibernate. The 20 us allows the sleep regulator time to * stabilize before the next hibernate / sleep event occurs. The 20 us * requirement begins when the device wakes up. There is no hardware check that * this requirement is met. The specified delay should be done on ISR entry. * -* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is -* instance name of the Pins component) function must be called to clear the +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin +* is instance name of the Pins component) function must be called to clear the * latched pin events to allow the proper Hibernate mode entry and to enable * detection of future events. * @@ -1111,6 +1093,67 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) * *******************************************************************************/ void CyPmHibernate(void) +{ + CyPmHibernateEx(CY_PM_HIB_SRC_PICU); +} + + +/******************************************************************************* +* Function Name: CyPmHibernateEx +****************************************************************************//** +* +* Puts the part into the Hibernate state. +* +* The following wake up sources can be configured: PICU interrupt, Comparator0, +* Comparator1, Comparator2, and Comparator3 output. +* +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. +* +* If using PICU as the wake up source, make sure you have at least one pin +* configured to generate a PICU interrupt. For pin Px.y, the register +* "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this +* register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet, +* this register is referred to as the IRQ option. Once the wakeup occurs, the +* PICU wakeup source bit is restored and the PSoC returns to the Active state. +* +* If using a comparator as the wake up source, make sure you call this function +* with the 'wakeupSource' parameter set to the appropriate comparator. The part +* is configured for the requested wakeup source by setting the corresponding +* bits in PM_WAKEUP_CFG1 register. +* +* Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as +* CyPmHibernate(). +* +* \param wakeupSource: +* Parameter Value Description +* CY_PM_HIB_SRC_PICU PICU interrupt is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR0 Comparator 0 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR1 Comparator 1 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR2 Comparator 2 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR3 Comparator 3 is set as the wake up source. +* +* Reentrant: +* No +* +* \sideeffect +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin +* is instance name of the Pins component) function must be called to clear the +* latched pin events to allow the proper Hibernate mode entry and to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using the rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernateEx(uint16 wakeupSource) { uint8 interruptState; @@ -1141,12 +1184,15 @@ void CyPmHibernate(void) CyPmHibSaveSet(); + /* Save and set new wake up configuration */ + /* Save and enable only wakeup on PICU */ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; - CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; + CY_PM_WAKEUP_CFG0_REG = ((uint8) (wakeupSource >> 4u) & CY_PM_WAKEUP_PICU); + /* Comparators */ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; - CY_PM_WAKEUP_CFG1_REG = 0x00u; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; CY_PM_WAKEUP_CFG2_REG = 0x00u; @@ -1211,9 +1257,8 @@ void CyPmHibernate(void) /******************************************************************************* * Function Name: CyPmReadStatus -******************************************************************************** +****************************************************************************//** * -* Summary: * Manages the Power Manager Interrupt Status Register. This register has the * interrupt status for the one pulse per second, central timewheel and fast * timewheel timers. This hardware register clears on read. To allow for only @@ -1226,15 +1271,14 @@ void CyPmHibernate(void) * Note You must call this function within 1 ms (1 clock cycle of the ILO) * after a CTW event has occurred. * -* Parameters: -* mask: Bits in the shadow register to clear. +* \param mask: Bits in the shadow register to clear. * * Define Source * CY_PM_FTW_INT Fast Timewheel * CY_PM_CTW_INT Central Timewheel * CY_PM_ONEPPS_INT One Pulse Per Second * -* Return: +* \return * Status. Same bits values as the mask parameter. * *******************************************************************************/ @@ -1249,7 +1293,7 @@ uint8 CyPmReadStatus(uint8 mask) /* Save value of register, copy it and clear desired bit */ interruptStatus |= CY_PM_INT_SR_REG; - tmpStatus = interruptStatus; + tmpStatus = interruptStatus & (CY_PM_FTW_INT | CY_PM_CTW_INT | CY_PM_ONEPPS_INT); interruptStatus &= ((uint8)(~mask)); /* Exit critical section */ @@ -1261,9 +1305,8 @@ uint8 CyPmReadStatus(uint8 mask) /******************************************************************************* * Function Name: CyPmHibSaveSet -******************************************************************************** +****************************************************************************//** * -* Summary: * Prepare device for proper Hibernate low power mode entry: * - Disables I2C backup regulator * - Saves ILO power down mode state and enable it @@ -1272,12 +1315,6 @@ uint8 CyPmReadStatus(uint8 mask) * - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() * - CyPmHibSlpSaveSet() function is called * -* Parameters: -* None -* -* Return: -* None -* * Reentrant: * No * @@ -1355,9 +1392,8 @@ static void CyPmHibSaveSet(void) /******************************************************************************* * Function Name: CyPmHibRestore -******************************************************************************** +****************************************************************************//** * -* Summary: * Restores the device for the proper Hibernate mode exit: * - Restores LVI/HVI configuration - calsl CyPmHviLviRestore() * - CyPmHibSlpSaveRestore() function is called @@ -1365,12 +1401,6 @@ static void CyPmHibSaveSet(void) * - Restores the state of 1 kHz and 100 kHz ILO and disables them * - Restores the sleep regulator settings * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ static void CyPmHibRestore(void) { @@ -1415,21 +1445,16 @@ static void CyPmHibRestore(void) /******************************************************************************* * Function Name: CyPmCtwSetInterval -******************************************************************************** +****************************************************************************//** * -* Summary: * Performs the CTW configuration: * - Disables the CTW interrupt * - Enables 1 kHz ILO * - Sets a new CTW interval * -* Parameters: -* ctwInterval: the CTW interval to be set. +* \param ctwInterval: the CTW interval to be set. * -* Return: -* None -* -* Side Effects: +* \sideeffect * Enables ILO 1 KHz clock and leaves it enabled. * *******************************************************************************/ @@ -1470,20 +1495,13 @@ void CyPmCtwSetInterval(uint8 ctwInterval) /******************************************************************************* * Function Name: CyPmOppsSet -******************************************************************************** +****************************************************************************//** * -* Summary: * Performs 1PPS configuration: * - Starts 32 KHz XTAL * - Disables 1PPS interrupts * - Enables 1PPS * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ void CyPmOppsSet(void) { @@ -1504,21 +1522,16 @@ void CyPmOppsSet(void) /******************************************************************************* * Function Name: CyPmFtwSetInterval -******************************************************************************** +****************************************************************************//** * -* Summary: * Performs the FTW configuration: * - Disables the FTW interrupt * - Enables 100 kHz ILO * - Sets a new FTW interval. * -* Parameters: -* ftwInterval - FTW counter interval. +* \param ftwInterval The FTW counter interval. * -* Return: -* None -* -* Side Effects: +* \sideeffect * Enables the ILO 100 KHz clock and leaves it enabled. * *******************************************************************************/ @@ -1559,22 +1572,15 @@ void CyPmFtwSetInterval(uint8 ftwInterval) /******************************************************************************* * Function Name: CyPmHibSlpSaveSet -******************************************************************************** +****************************************************************************//** * -* Summary: -* This API is used for preparing the device for the Sleep and Hibernate low power -* modes entry: +* This API is used for preparing the device for the Sleep and Hibernate low +* power modes entry: * - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5) * - Saves the SC/CT routing connections (PSoC 3/5/5LP) * - Disables the Serial Wire Viewer (SWV) (PSoC 3) * - Saves the boost reference selection and sets it to internal * -* Parameters: -* None -* -* Return: -* None -* * Reentrant: * No * @@ -1694,21 +1700,14 @@ static void CyPmHibSlpSaveSet(void) /******************************************************************************* * Function Name: CyPmHibSlpRestore -******************************************************************************** +****************************************************************************//** * -* Summary: -* This API is used for restoring the device configurations after wakeup from the Sleep -* and Hibernate low power modes: +* This API is used for restoring the device configurations after wakeup from +* the Sleep and Hibernate low power modes: * - Restores the SC/CT routing connections * - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3) * - Restores the boost reference selection * -* Parameters: -* None -* -* Return: -* None -* *******************************************************************************/ static void CyPmHibSlpRestore(void) { @@ -1772,17 +1771,10 @@ static void CyPmHibSlpRestore(void) /******************************************************************************* * Function Name: CyPmHviLviSaveDisable -******************************************************************************** +****************************************************************************//** * -* Summary: * Saves analog and digital LVI and HVI configuration and disables them. * -* Parameters: -* None -* -* Return: -* None -* * Reentrant: * No * @@ -1835,17 +1827,10 @@ static void CyPmHviLviSaveDisable(void) /******************************************************************************* * Function Name: CyPmHviLviRestore -******************************************************************************** +****************************************************************************//** * -* Summary: * Restores the analog and digital LVI and HVI configuration. * -* Parameters: -* None -* -* Return: -* None -* * Reentrant: * No * diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h old mode 100644 new mode 100755 index 0110c37..44013bf --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h @@ -1,16 +1,15 @@ -/******************************************************************************* -* File Name: cyPm.h -* Version 4.20 +/***************************************************************************//** +* \file cyPm.h +* \version 5.50 * -* Description: -* Provides the function definitions for the power management API. +* \brief Provides the function definitions for the power management API. * -* Note: -* Documentation of the API's in this file is located in the +* \note Documentation of the API's in this file is located in the * System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -34,6 +33,7 @@ void CyPmRestoreClocks(void) ; void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; void CyPmHibernate(void) ; +void CyPmHibernateEx(uint16 wakeupSource) ; uint8 CyPmReadStatus(uint8 mask) ; @@ -104,6 +104,13 @@ void CyPmOppsSet(void) ; #define PM_SLEEP_SRC_ONE_PPS (0x0800u) #define PM_SLEEP_SRC_LCD (0x1000u) +/* Wake up sources for Hibernate mode */ +#define CY_PM_HIB_SRC_PICU (0x0040u) +#define CY_PM_HIB_SRC_COMPARATOR0 (0x0001u) +#define CY_PM_HIB_SRC_COMPARATOR1 (0x0002u) +#define CY_PM_HIB_SRC_COMPARATOR2 (0x0004u) +#define CY_PM_HIB_SRC_COMPARATOR3 (0x0008u) + /* Wake up sources for Alternate Active mode */ #define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) #define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) @@ -195,7 +202,7 @@ void CyPmOppsSet(void) ; #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ #define CY_PM_WFI __wfi() #else /* ASM for GCC & IAR */ - #define CY_PM_WFI asm volatile ("WFI \n") + #define CY_PM_WFI __asm volatile ("WFI \n") #endif /* (__ARMCC_VERSION) */ #else diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index f98fb50..e9a0eaf 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index 02dbced..b7f270a 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index e550a13..bacd4b7 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index 78bb577..22e5061 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 45156fe..019dd7c 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.3 +; PSoC Creator 4.0 Update 1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index 17aba9b..0e2c8a3 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 3.3 +; PSoC Creator 4.0 Update 1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index 67890e8..228aba9 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 3.3 +; PSoC Creator 4.0 Update 1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 0175ff3..473b655 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 3.3 +; PSoC Creator 4.0 Update 1 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 2a56837..5df9d48 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -8,7 +8,7 @@ #define LED1__0__MASK 0x08u #define LED1__0__PC CYREG_PRT12_PC3 #define LED1__0__PORT 12u -#define LED1__0__SHIFT 3 +#define LED1__0__SHIFT 3u #define LED1__AG CYREG_PRT12_AG #define LED1__BIE CYREG_PRT12_BIE #define LED1__BIT_MASK CYREG_PRT12_BIT_MASK @@ -29,7 +29,7 @@ #define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 #define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT #define LED1__PS CYREG_PRT12_PS -#define LED1__SHIFT 3 +#define LED1__SHIFT 3u #define LED1__SIO_CFG CYREG_PRT12_SIO_CFG #define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF #define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN @@ -41,7 +41,7 @@ #define SD_CD__0__MASK 0x40u #define SD_CD__0__PC CYREG_PRT3_PC6 #define SD_CD__0__PORT 3u -#define SD_CD__0__SHIFT 6 +#define SD_CD__0__SHIFT 6u #define SD_CD__AG CYREG_PRT3_AG #define SD_CD__AMUX CYREG_PRT3_AMUX #define SD_CD__BIE CYREG_PRT3_BIE @@ -67,7 +67,7 @@ #define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_CD__PS CYREG_PRT3_PS -#define SD_CD__SHIFT 6 +#define SD_CD__SHIFT 6u #define SD_CD__SLW CYREG_PRT3_SLW /* SD_CS */ @@ -75,7 +75,7 @@ #define SD_CS__0__MASK 0x10u #define SD_CS__0__PC CYREG_PRT3_PC4 #define SD_CS__0__PORT 3u -#define SD_CS__0__SHIFT 4 +#define SD_CS__0__SHIFT 4u #define SD_CS__AG CYREG_PRT3_AG #define SD_CS__AMUX CYREG_PRT3_AMUX #define SD_CS__BIE CYREG_PRT3_BIE @@ -101,7 +101,7 @@ #define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_CS__PS CYREG_PRT3_PS -#define SD_CS__SHIFT 4 +#define SD_CS__SHIFT 4u #define SD_CS__SLW CYREG_PRT3_SLW /* USBFS_arb_int */ @@ -129,7 +129,7 @@ #define USBFS_Dm__0__MASK 0x80u #define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 #define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7 +#define USBFS_Dm__0__SHIFT 7u #define USBFS_Dm__AG CYREG_PRT15_AG #define USBFS_Dm__AMUX CYREG_PRT15_AMUX #define USBFS_Dm__BIE CYREG_PRT15_BIE @@ -155,7 +155,7 @@ #define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 #define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT #define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7 +#define USBFS_Dm__SHIFT 7u #define USBFS_Dm__SLW CYREG_PRT15_SLW /* USBFS_Dp */ @@ -163,7 +163,7 @@ #define USBFS_Dp__0__MASK 0x40u #define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 #define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6 +#define USBFS_Dp__0__SHIFT 6u #define USBFS_Dp__AG CYREG_PRT15_AG #define USBFS_Dp__AMUX CYREG_PRT15_AMUX #define USBFS_Dp__BIE CYREG_PRT15_BIE @@ -190,7 +190,7 @@ #define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 #define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT #define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6 +#define USBFS_Dp__SHIFT 6u #define USBFS_Dp__SLW CYREG_PRT15_SLW #define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 @@ -391,34 +391,34 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -426,9 +426,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -450,8 +454,8 @@ #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -459,20 +463,16 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 #define SD_SCK__0__MASK 0x04u #define SD_SCK__0__PC CYREG_PRT3_PC2 #define SD_SCK__0__PORT 3u -#define SD_SCK__0__SHIFT 2 +#define SD_SCK__0__SHIFT 2u #define SD_SCK__AG CYREG_PRT3_AG #define SD_SCK__AMUX CYREG_PRT3_AMUX #define SD_SCK__BIE CYREG_PRT3_BIE @@ -498,7 +498,7 @@ #define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_SCK__PS CYREG_PRT3_PS -#define SD_SCK__SHIFT 2 +#define SD_SCK__SHIFT 2u #define SD_SCK__SLW CYREG_PRT3_SLW /* SCSI_In */ @@ -528,7 +528,7 @@ #define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In__0__PS CYREG_PRT2_PS -#define SCSI_In__0__SHIFT 0 +#define SCSI_In__0__SHIFT 0u #define SCSI_In__0__SLW CYREG_PRT2_SLW #define SCSI_In__1__AG CYREG_PRT6_AG #define SCSI_In__1__AMUX CYREG_PRT6_AMUX @@ -556,7 +556,7 @@ #define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_In__1__PS CYREG_PRT6_PS -#define SCSI_In__1__SHIFT 7 +#define SCSI_In__1__SHIFT 7u #define SCSI_In__1__SLW CYREG_PRT6_SLW #define SCSI_In__2__AG CYREG_PRT5_AG #define SCSI_In__2__AMUX CYREG_PRT5_AMUX @@ -584,7 +584,7 @@ #define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__2__PS CYREG_PRT5_PS -#define SCSI_In__2__SHIFT 1 +#define SCSI_In__2__SHIFT 1u #define SCSI_In__2__SLW CYREG_PRT5_SLW #define SCSI_In__3__AG CYREG_PRT5_AG #define SCSI_In__3__AMUX CYREG_PRT5_AMUX @@ -612,7 +612,7 @@ #define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__3__PS CYREG_PRT5_PS -#define SCSI_In__3__SHIFT 2 +#define SCSI_In__3__SHIFT 2u #define SCSI_In__3__SLW CYREG_PRT5_SLW #define SCSI_In__4__AG CYREG_PRT5_AG #define SCSI_In__4__AMUX CYREG_PRT5_AMUX @@ -640,7 +640,7 @@ #define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__4__PS CYREG_PRT5_PS -#define SCSI_In__4__SHIFT 3 +#define SCSI_In__4__SHIFT 3u #define SCSI_In__4__SLW CYREG_PRT5_SLW #define SCSI_In__CD__AG CYREG_PRT5_AG #define SCSI_In__CD__AMUX CYREG_PRT5_AMUX @@ -668,7 +668,7 @@ #define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__CD__PS CYREG_PRT5_PS -#define SCSI_In__CD__SHIFT 1 +#define SCSI_In__CD__SHIFT 1u #define SCSI_In__CD__SLW CYREG_PRT5_SLW #define SCSI_In__DBP__AG CYREG_PRT2_AG #define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX @@ -696,7 +696,7 @@ #define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In__DBP__PS CYREG_PRT2_PS -#define SCSI_In__DBP__SHIFT 0 +#define SCSI_In__DBP__SHIFT 0u #define SCSI_In__DBP__SLW CYREG_PRT2_SLW #define SCSI_In__IO__AG CYREG_PRT5_AG #define SCSI_In__IO__AMUX CYREG_PRT5_AMUX @@ -724,7 +724,7 @@ #define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__IO__PS CYREG_PRT5_PS -#define SCSI_In__IO__SHIFT 3 +#define SCSI_In__IO__SHIFT 3u #define SCSI_In__IO__SLW CYREG_PRT5_SLW #define SCSI_In__MSG__AG CYREG_PRT6_AG #define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX @@ -752,7 +752,7 @@ #define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_In__MSG__PS CYREG_PRT6_PS -#define SCSI_In__MSG__SHIFT 7 +#define SCSI_In__MSG__SHIFT 7u #define SCSI_In__MSG__SLW CYREG_PRT6_SLW #define SCSI_In__REQ__AG CYREG_PRT5_AG #define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX @@ -780,7 +780,7 @@ #define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__REQ__PS CYREG_PRT5_PS -#define SCSI_In__REQ__SHIFT 2 +#define SCSI_In__REQ__SHIFT 2u #define SCSI_In__REQ__SLW CYREG_PRT5_SLW /* SCSI_In_DBx */ @@ -805,7 +805,7 @@ #define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 #define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT #define SCSI_In_DBx__0__PS CYREG_PRT12_PS -#define SCSI_In_DBx__0__SHIFT 4 +#define SCSI_In_DBx__0__SHIFT 4u #define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG #define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF #define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN @@ -837,7 +837,7 @@ #define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__1__PS CYREG_PRT2_PS -#define SCSI_In_DBx__1__SHIFT 7 +#define SCSI_In_DBx__1__SHIFT 7u #define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__2__AG CYREG_PRT2_AG #define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX @@ -865,7 +865,7 @@ #define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__2__PS CYREG_PRT2_PS -#define SCSI_In_DBx__2__SHIFT 6 +#define SCSI_In_DBx__2__SHIFT 6u #define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__3__AG CYREG_PRT2_AG #define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX @@ -893,7 +893,7 @@ #define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__3__PS CYREG_PRT2_PS -#define SCSI_In_DBx__3__SHIFT 5 +#define SCSI_In_DBx__3__SHIFT 5u #define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__4__AG CYREG_PRT2_AG #define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX @@ -921,7 +921,7 @@ #define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__4__PS CYREG_PRT2_PS -#define SCSI_In_DBx__4__SHIFT 4 +#define SCSI_In_DBx__4__SHIFT 4u #define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__5__AG CYREG_PRT2_AG #define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX @@ -949,7 +949,7 @@ #define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__5__PS CYREG_PRT2_PS -#define SCSI_In_DBx__5__SHIFT 3 +#define SCSI_In_DBx__5__SHIFT 3u #define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__6__AG CYREG_PRT2_AG #define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX @@ -977,7 +977,7 @@ #define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__6__PS CYREG_PRT2_PS -#define SCSI_In_DBx__6__SHIFT 2 +#define SCSI_In_DBx__6__SHIFT 2u #define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__7__AG CYREG_PRT2_AG #define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX @@ -1005,7 +1005,7 @@ #define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__7__PS CYREG_PRT2_PS -#define SCSI_In_DBx__7__SHIFT 1 +#define SCSI_In_DBx__7__SHIFT 1u #define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG #define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE @@ -1028,7 +1028,7 @@ #define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 #define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT #define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS -#define SCSI_In_DBx__DB0__SHIFT 4 +#define SCSI_In_DBx__DB0__SHIFT 4u #define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG #define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF #define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN @@ -1060,7 +1060,7 @@ #define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB1__SHIFT 7 +#define SCSI_In_DBx__DB1__SHIFT 7u #define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG #define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX @@ -1088,7 +1088,7 @@ #define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB2__SHIFT 6 +#define SCSI_In_DBx__DB2__SHIFT 6u #define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG #define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX @@ -1116,7 +1116,7 @@ #define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB3__SHIFT 5 +#define SCSI_In_DBx__DB3__SHIFT 5u #define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG #define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX @@ -1144,7 +1144,7 @@ #define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB4__SHIFT 4 +#define SCSI_In_DBx__DB4__SHIFT 4u #define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG #define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX @@ -1172,7 +1172,7 @@ #define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB5__SHIFT 3 +#define SCSI_In_DBx__DB5__SHIFT 3u #define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG #define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX @@ -1200,7 +1200,7 @@ #define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB6__SHIFT 2 +#define SCSI_In_DBx__DB6__SHIFT 2u #define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW #define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG #define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX @@ -1228,7 +1228,7 @@ #define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 #define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT #define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS -#define SCSI_In_DBx__DB7__SHIFT 1 +#define SCSI_In_DBx__DB7__SHIFT 1u #define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW /* SD_DAT1 */ @@ -1236,7 +1236,7 @@ #define SD_DAT1__0__MASK 0x01u #define SD_DAT1__0__PC CYREG_PRT3_PC0 #define SD_DAT1__0__PORT 3u -#define SD_DAT1__0__SHIFT 0 +#define SD_DAT1__0__SHIFT 0u #define SD_DAT1__AG CYREG_PRT3_AG #define SD_DAT1__AMUX CYREG_PRT3_AMUX #define SD_DAT1__BIE CYREG_PRT3_BIE @@ -1262,7 +1262,7 @@ #define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_DAT1__PS CYREG_PRT3_PS -#define SD_DAT1__SHIFT 0 +#define SD_DAT1__SHIFT 0u #define SD_DAT1__SLW CYREG_PRT3_SLW /* SD_DAT2 */ @@ -1270,7 +1270,7 @@ #define SD_DAT2__0__MASK 0x20u #define SD_DAT2__0__PC CYREG_PRT3_PC5 #define SD_DAT2__0__PORT 3u -#define SD_DAT2__0__SHIFT 5 +#define SD_DAT2__0__SHIFT 5u #define SD_DAT2__AG CYREG_PRT3_AG #define SD_DAT2__AMUX CYREG_PRT3_AMUX #define SD_DAT2__BIE CYREG_PRT3_BIE @@ -1296,7 +1296,7 @@ #define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_DAT2__PS CYREG_PRT3_PS -#define SD_DAT2__SHIFT 5 +#define SD_DAT2__SHIFT 5u #define SD_DAT2__SLW CYREG_PRT3_SLW /* SD_MISO */ @@ -1304,7 +1304,7 @@ #define SD_MISO__0__MASK 0x02u #define SD_MISO__0__PC CYREG_PRT3_PC1 #define SD_MISO__0__PORT 3u -#define SD_MISO__0__SHIFT 1 +#define SD_MISO__0__SHIFT 1u #define SD_MISO__AG CYREG_PRT3_AG #define SD_MISO__AMUX CYREG_PRT3_AMUX #define SD_MISO__BIE CYREG_PRT3_BIE @@ -1330,7 +1330,7 @@ #define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_MISO__PS CYREG_PRT3_PS -#define SD_MISO__SHIFT 1 +#define SD_MISO__SHIFT 1u #define SD_MISO__SLW CYREG_PRT3_SLW /* SD_MOSI */ @@ -1338,7 +1338,7 @@ #define SD_MOSI__0__MASK 0x08u #define SD_MOSI__0__PC CYREG_PRT3_PC3 #define SD_MOSI__0__PORT 3u -#define SD_MOSI__0__SHIFT 3 +#define SD_MOSI__0__SHIFT 3u #define SD_MOSI__AG CYREG_PRT3_AG #define SD_MOSI__AMUX CYREG_PRT3_AMUX #define SD_MOSI__BIE CYREG_PRT3_BIE @@ -1364,7 +1364,7 @@ #define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 #define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT #define SD_MOSI__PS CYREG_PRT3_PS -#define SD_MOSI__SHIFT 3 +#define SD_MOSI__SHIFT 3u #define SD_MOSI__SLW CYREG_PRT3_SLW /* SCSI_CLK */ @@ -1405,7 +1405,7 @@ #define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out__0__PS CYREG_PRT4_PS -#define SCSI_Out__0__SHIFT 3 +#define SCSI_Out__0__SHIFT 3u #define SCSI_Out__0__SLW CYREG_PRT4_SLW #define SCSI_Out__1__AG CYREG_PRT4_AG #define SCSI_Out__1__AMUX CYREG_PRT4_AMUX @@ -1433,7 +1433,7 @@ #define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out__1__PS CYREG_PRT4_PS -#define SCSI_Out__1__SHIFT 2 +#define SCSI_Out__1__SHIFT 2u #define SCSI_Out__1__SLW CYREG_PRT4_SLW #define SCSI_Out__2__AG CYREG_PRT0_AG #define SCSI_Out__2__AMUX CYREG_PRT0_AMUX @@ -1461,7 +1461,7 @@ #define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__2__PS CYREG_PRT0_PS -#define SCSI_Out__2__SHIFT 7 +#define SCSI_Out__2__SHIFT 7u #define SCSI_Out__2__SLW CYREG_PRT0_SLW #define SCSI_Out__3__AG CYREG_PRT0_AG #define SCSI_Out__3__AMUX CYREG_PRT0_AMUX @@ -1489,7 +1489,7 @@ #define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__3__PS CYREG_PRT0_PS -#define SCSI_Out__3__SHIFT 6 +#define SCSI_Out__3__SHIFT 6u #define SCSI_Out__3__SLW CYREG_PRT0_SLW #define SCSI_Out__4__AG CYREG_PRT0_AG #define SCSI_Out__4__AMUX CYREG_PRT0_AMUX @@ -1517,7 +1517,7 @@ #define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__4__PS CYREG_PRT0_PS -#define SCSI_Out__4__SHIFT 5 +#define SCSI_Out__4__SHIFT 5u #define SCSI_Out__4__SLW CYREG_PRT0_SLW #define SCSI_Out__5__AG CYREG_PRT0_AG #define SCSI_Out__5__AMUX CYREG_PRT0_AMUX @@ -1545,7 +1545,7 @@ #define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__5__PS CYREG_PRT0_PS -#define SCSI_Out__5__SHIFT 4 +#define SCSI_Out__5__SHIFT 4u #define SCSI_Out__5__SLW CYREG_PRT0_SLW #define SCSI_Out__6__AG CYREG_PRT0_AG #define SCSI_Out__6__AMUX CYREG_PRT0_AMUX @@ -1573,7 +1573,7 @@ #define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__6__PS CYREG_PRT0_PS -#define SCSI_Out__6__SHIFT 3 +#define SCSI_Out__6__SHIFT 3u #define SCSI_Out__6__SLW CYREG_PRT0_SLW #define SCSI_Out__7__AG CYREG_PRT0_AG #define SCSI_Out__7__AMUX CYREG_PRT0_AMUX @@ -1601,7 +1601,7 @@ #define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__7__PS CYREG_PRT0_PS -#define SCSI_Out__7__SHIFT 2 +#define SCSI_Out__7__SHIFT 2u #define SCSI_Out__7__SLW CYREG_PRT0_SLW #define SCSI_Out__8__AG CYREG_PRT0_AG #define SCSI_Out__8__AMUX CYREG_PRT0_AMUX @@ -1629,7 +1629,7 @@ #define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__8__PS CYREG_PRT0_PS -#define SCSI_Out__8__SHIFT 1 +#define SCSI_Out__8__SHIFT 1u #define SCSI_Out__8__SLW CYREG_PRT0_SLW #define SCSI_Out__9__AG CYREG_PRT0_AG #define SCSI_Out__9__AMUX CYREG_PRT0_AMUX @@ -1657,7 +1657,7 @@ #define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__9__PS CYREG_PRT0_PS -#define SCSI_Out__9__SHIFT 0 +#define SCSI_Out__9__SHIFT 0u #define SCSI_Out__9__SLW CYREG_PRT0_SLW #define SCSI_Out__ACK__AG CYREG_PRT0_AG #define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX @@ -1685,7 +1685,7 @@ #define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__ACK__PS CYREG_PRT0_PS -#define SCSI_Out__ACK__SHIFT 6 +#define SCSI_Out__ACK__SHIFT 6u #define SCSI_Out__ACK__SLW CYREG_PRT0_SLW #define SCSI_Out__ATN__AG CYREG_PRT4_AG #define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX @@ -1713,7 +1713,7 @@ #define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out__ATN__PS CYREG_PRT4_PS -#define SCSI_Out__ATN__SHIFT 2 +#define SCSI_Out__ATN__SHIFT 2u #define SCSI_Out__ATN__SLW CYREG_PRT4_SLW #define SCSI_Out__BSY__AG CYREG_PRT0_AG #define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX @@ -1741,7 +1741,7 @@ #define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__BSY__PS CYREG_PRT0_PS -#define SCSI_Out__BSY__SHIFT 7 +#define SCSI_Out__BSY__SHIFT 7u #define SCSI_Out__BSY__SLW CYREG_PRT0_SLW #define SCSI_Out__CD_raw__AG CYREG_PRT0_AG #define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX @@ -1769,7 +1769,7 @@ #define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__CD_raw__PS CYREG_PRT0_PS -#define SCSI_Out__CD_raw__SHIFT 2 +#define SCSI_Out__CD_raw__SHIFT 2u #define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW #define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG #define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX @@ -1797,7 +1797,7 @@ #define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS -#define SCSI_Out__DBP_raw__SHIFT 3 +#define SCSI_Out__DBP_raw__SHIFT 3u #define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW #define SCSI_Out__IO_raw__AG CYREG_PRT0_AG #define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX @@ -1825,7 +1825,7 @@ #define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__IO_raw__PS CYREG_PRT0_PS -#define SCSI_Out__IO_raw__SHIFT 0 +#define SCSI_Out__IO_raw__SHIFT 0u #define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW #define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG #define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX @@ -1853,7 +1853,7 @@ #define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS -#define SCSI_Out__MSG_raw__SHIFT 4 +#define SCSI_Out__MSG_raw__SHIFT 4u #define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW #define SCSI_Out__REQ__AG CYREG_PRT0_AG #define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX @@ -1881,7 +1881,7 @@ #define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__REQ__PS CYREG_PRT0_PS -#define SCSI_Out__REQ__SHIFT 1 +#define SCSI_Out__REQ__SHIFT 1u #define SCSI_Out__REQ__SLW CYREG_PRT0_SLW #define SCSI_Out__RST__AG CYREG_PRT0_AG #define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX @@ -1909,7 +1909,7 @@ #define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__RST__PS CYREG_PRT0_PS -#define SCSI_Out__RST__SHIFT 5 +#define SCSI_Out__RST__SHIFT 5u #define SCSI_Out__RST__SLW CYREG_PRT0_SLW #define SCSI_Out__SEL__AG CYREG_PRT0_AG #define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX @@ -1937,7 +1937,7 @@ #define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 #define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT #define SCSI_Out__SEL__PS CYREG_PRT0_PS -#define SCSI_Out__SEL__SHIFT 3 +#define SCSI_Out__SEL__SHIFT 3u #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW /* SCSI_Out_Bits */ @@ -1945,15 +1945,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1966,37 +1966,37 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -2025,7 +2025,7 @@ #define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__0__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__0__SHIFT 3 +#define SCSI_Out_DBx__0__SHIFT 3u #define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__1__AG CYREG_PRT6_AG #define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX @@ -2053,7 +2053,7 @@ #define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__1__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__1__SHIFT 2 +#define SCSI_Out_DBx__1__SHIFT 2u #define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__2__AG CYREG_PRT6_AG #define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX @@ -2081,7 +2081,7 @@ #define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__2__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__2__SHIFT 1 +#define SCSI_Out_DBx__2__SHIFT 1u #define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__3__AG CYREG_PRT6_AG #define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX @@ -2109,7 +2109,7 @@ #define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__3__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__3__SHIFT 0 +#define SCSI_Out_DBx__3__SHIFT 0u #define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__4__AG CYREG_PRT4_AG #define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX @@ -2137,7 +2137,7 @@ #define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__4__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__4__SHIFT 7 +#define SCSI_Out_DBx__4__SHIFT 7u #define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__5__AG CYREG_PRT4_AG #define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX @@ -2165,7 +2165,7 @@ #define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__5__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__5__SHIFT 6 +#define SCSI_Out_DBx__5__SHIFT 6u #define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__6__AG CYREG_PRT4_AG #define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX @@ -2193,7 +2193,7 @@ #define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__6__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__6__SHIFT 5 +#define SCSI_Out_DBx__6__SHIFT 5u #define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__7__AG CYREG_PRT4_AG #define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX @@ -2221,7 +2221,7 @@ #define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__7__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__7__SHIFT 4 +#define SCSI_Out_DBx__7__SHIFT 4u #define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX @@ -2249,7 +2249,7 @@ #define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB0__SHIFT 3 +#define SCSI_Out_DBx__DB0__SHIFT 3u #define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG #define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX @@ -2277,7 +2277,7 @@ #define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB1__SHIFT 2 +#define SCSI_Out_DBx__DB1__SHIFT 2u #define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG #define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX @@ -2305,7 +2305,7 @@ #define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB2__SHIFT 1 +#define SCSI_Out_DBx__DB2__SHIFT 1u #define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG #define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX @@ -2333,7 +2333,7 @@ #define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS -#define SCSI_Out_DBx__DB3__SHIFT 0 +#define SCSI_Out_DBx__DB3__SHIFT 0u #define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW #define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG #define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX @@ -2361,7 +2361,7 @@ #define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB4__SHIFT 7 +#define SCSI_Out_DBx__DB4__SHIFT 7u #define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG #define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX @@ -2389,7 +2389,7 @@ #define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB5__SHIFT 6 +#define SCSI_Out_DBx__DB5__SHIFT 6u #define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG #define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX @@ -2417,7 +2417,7 @@ #define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB6__SHIFT 5 +#define SCSI_Out_DBx__DB6__SHIFT 5u #define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW #define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG #define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX @@ -2445,7 +2445,7 @@ #define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 #define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT #define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS -#define SCSI_Out_DBx__DB7__SHIFT 4 +#define SCSI_Out_DBx__DB7__SHIFT 4u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW /* SD_RX_DMA */ @@ -2514,7 +2514,7 @@ #define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 #define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT #define SCSI_Noise__0__PS CYREG_PRT12_PS -#define SCSI_Noise__0__SHIFT 5 +#define SCSI_Noise__0__SHIFT 5u #define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG #define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF #define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN @@ -2546,7 +2546,7 @@ #define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Noise__1__PS CYREG_PRT6_PS -#define SCSI_Noise__1__SHIFT 4 +#define SCSI_Noise__1__SHIFT 4u #define SCSI_Noise__1__SLW CYREG_PRT6_SLW #define SCSI_Noise__2__AG CYREG_PRT5_AG #define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX @@ -2574,7 +2574,7 @@ #define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_Noise__2__PS CYREG_PRT5_PS -#define SCSI_Noise__2__SHIFT 0 +#define SCSI_Noise__2__SHIFT 0u #define SCSI_Noise__2__SLW CYREG_PRT5_SLW #define SCSI_Noise__3__AG CYREG_PRT6_AG #define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX @@ -2602,7 +2602,7 @@ #define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Noise__3__PS CYREG_PRT6_PS -#define SCSI_Noise__3__SHIFT 6 +#define SCSI_Noise__3__SHIFT 6u #define SCSI_Noise__3__SLW CYREG_PRT6_SLW #define SCSI_Noise__4__AG CYREG_PRT6_AG #define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX @@ -2630,7 +2630,7 @@ #define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Noise__4__PS CYREG_PRT6_PS -#define SCSI_Noise__4__SHIFT 5 +#define SCSI_Noise__4__SHIFT 5u #define SCSI_Noise__4__SLW CYREG_PRT6_SLW #define SCSI_Noise__ACK__AG CYREG_PRT6_AG #define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX @@ -2658,7 +2658,7 @@ #define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Noise__ACK__PS CYREG_PRT6_PS -#define SCSI_Noise__ACK__SHIFT 5 +#define SCSI_Noise__ACK__SHIFT 5u #define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW #define SCSI_Noise__ATN__AG CYREG_PRT12_AG #define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE @@ -2681,7 +2681,7 @@ #define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 #define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT #define SCSI_Noise__ATN__PS CYREG_PRT12_PS -#define SCSI_Noise__ATN__SHIFT 5 +#define SCSI_Noise__ATN__SHIFT 5u #define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG #define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF #define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN @@ -2713,7 +2713,7 @@ #define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Noise__BSY__PS CYREG_PRT6_PS -#define SCSI_Noise__BSY__SHIFT 4 +#define SCSI_Noise__BSY__SHIFT 4u #define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW #define SCSI_Noise__RST__AG CYREG_PRT6_AG #define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX @@ -2741,7 +2741,7 @@ #define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_Noise__RST__PS CYREG_PRT6_PS -#define SCSI_Noise__RST__SHIFT 6 +#define SCSI_Noise__RST__SHIFT 6u #define SCSI_Noise__RST__SLW CYREG_PRT6_SLW #define SCSI_Noise__SEL__AG CYREG_PRT5_AG #define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX @@ -2769,7 +2769,7 @@ #define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_Noise__SEL__PS CYREG_PRT5_PS -#define SCSI_Noise__SEL__SHIFT 0 +#define SCSI_Noise__SEL__SHIFT 0u #define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW /* scsiTarget */ @@ -2952,8 +2952,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2961,80 +2961,83 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB07_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB07_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 3.3" +#define CY_VERSION "PSoC Creator 4.0 Update 1" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PANTHER 18u -#define CYDEV_CHIP_DIE_PSOC4A 10u -#define CYDEV_CHIP_DIE_PSOC5LP 17u +#define CYDEV_CHIP_DIE_PSOC4A 12u +#define CYDEV_CHIP_DIE_PSOC5LP 19u +#define CYDEV_CHIP_DIE_PSOC5TM 20u #define CYDEV_CHIP_DIE_TMA4 2u #define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 4u +#define CYDEV_CHIP_FAMILY_FM3 5u +#define CYDEV_CHIP_FAMILY_FM4 6u #define CYDEV_CHIP_FAMILY_PSOC3 1u #define CYDEV_CHIP_FAMILY_PSOC4 2u #define CYDEV_CHIP_FAMILY_PSOC5 3u @@ -3042,22 +3045,30 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 10u -#define CYDEV_CHIP_MEMBER_4C 15u -#define CYDEV_CHIP_MEMBER_4D 6u +#define CYDEV_CHIP_MEMBER_4A 12u +#define CYDEV_CHIP_MEMBER_4C 18u +#define CYDEV_CHIP_MEMBER_4D 8u #define CYDEV_CHIP_MEMBER_4E 4u -#define CYDEV_CHIP_MEMBER_4F 11u +#define CYDEV_CHIP_MEMBER_4F 13u #define CYDEV_CHIP_MEMBER_4G 2u -#define CYDEV_CHIP_MEMBER_4H 9u -#define CYDEV_CHIP_MEMBER_4I 14u -#define CYDEV_CHIP_MEMBER_4J 7u -#define CYDEV_CHIP_MEMBER_4K 8u -#define CYDEV_CHIP_MEMBER_4L 13u -#define CYDEV_CHIP_MEMBER_4M 12u -#define CYDEV_CHIP_MEMBER_4N 5u +#define CYDEV_CHIP_MEMBER_4H 11u +#define CYDEV_CHIP_MEMBER_4I 17u +#define CYDEV_CHIP_MEMBER_4J 9u +#define CYDEV_CHIP_MEMBER_4K 10u +#define CYDEV_CHIP_MEMBER_4L 16u +#define CYDEV_CHIP_MEMBER_4M 15u +#define CYDEV_CHIP_MEMBER_4N 6u +#define CYDEV_CHIP_MEMBER_4O 5u +#define CYDEV_CHIP_MEMBER_4P 14u +#define CYDEV_CHIP_MEMBER_4Q 7u #define CYDEV_CHIP_MEMBER_4U 3u -#define CYDEV_CHIP_MEMBER_5A 17u -#define CYDEV_CHIP_MEMBER_5B 16u +#define CYDEV_CHIP_MEMBER_5A 20u +#define CYDEV_CHIP_MEMBER_5B 19u +#define CYDEV_CHIP_MEMBER_FM3 24u +#define CYDEV_CHIP_MEMBER_FM4 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -3066,13 +3077,13 @@ #define CYDEV_CHIP_REV_LEOPARD_ES2 1u #define CYDEV_CHIP_REV_LEOPARD_ES3 3u #define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u -#define CYDEV_CHIP_REV_PANTHER_ES0 0u -#define CYDEV_CHIP_REV_PANTHER_ES1 1u -#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u #define CYDEV_CHIP_REV_PSOC4A_ES0 17u #define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u #define CYDEV_CHIP_REV_PSOC5LP_ES0 0u #define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u #define CYDEV_CHIP_REV_TMA4_ES 17u #define CYDEV_CHIP_REV_TMA4_ES2 33u #define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u @@ -3098,12 +3109,20 @@ #define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u #define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION #define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED #define CYDEV_CONFIG_FASTBOOT_ENABLED 1 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 78594ac..4fcd68f 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -1,7 +1,7 @@ /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file contains device initialization code. @@ -9,7 +9,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -30,7 +30,9 @@ #define CYPACKED_ATTR __attribute__ ((packed)) #define CYALIGNED __attribute__ ((aligned)) #define CY_CFG_UNUSED __attribute__ ((unused)) - #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif #if defined(__ARMCC_VERSION) #define CY_CFG_MEMORY_BARRIER() __memory_changed() @@ -78,12 +80,14 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) + /* Clock startup error codes */ #define CYCLOCKSTART_NO_ERROR 0u #define CYCLOCKSTART_XTAL_ERROR 1u #define CYCLOCKSTART_32KHZ_ERROR 2u #define CYCLOCKSTART_PLL_ERROR 3u + #ifdef CY_NEED_CYCLOCKSTARTUPERROR /******************************************************************************* * Function Name: CyClockStartupError @@ -108,6 +112,14 @@ static void CyClockStartupError(uint8 errorCode) /* To remove the compiler warning if errorCode not used. */ errorCode = errorCode; + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ /* `#START CyClockStartupError` */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ @@ -119,10 +131,11 @@ static void CyClockStartupError(uint8 errorCode) /* If nothing else, stop here since the clocks have not started */ /* correctly. */ while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ } #endif -#define CY_CFG_BASE_ADDR_COUNT 40u +#define CY_CFG_BASE_ADDR_COUNT 41u CYPACKED typedef struct { uint8 offset; @@ -328,7 +341,11 @@ void cyfitter_cfg(void) /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; + 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; + + /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_1_VAL[] = { + 0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { @@ -384,81 +401,103 @@ void cyfitter_cfg(void) 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010054u, /* Base address: 0x40010000 Count: 84 */ - 0x40010141u, /* Base address: 0x40010100 Count: 65 */ - 0x40010243u, /* Base address: 0x40010200 Count: 67 */ - 0x40010350u, /* Base address: 0x40010300 Count: 80 */ - 0x40010454u, /* Base address: 0x40010400 Count: 84 */ - 0x40010553u, /* Base address: 0x40010500 Count: 83 */ - 0x40010651u, /* Base address: 0x40010600 Count: 81 */ - 0x40010755u, /* Base address: 0x40010700 Count: 85 */ - 0x40010916u, /* Base address: 0x40010900 Count: 22 */ - 0x40010A56u, /* Base address: 0x40010A00 Count: 86 */ - 0x40010B4Du, /* Base address: 0x40010B00 Count: 77 */ - 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */ - 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */ - 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */ - 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ - 0x40011421u, /* Base address: 0x40011400 Count: 33 */ - 0x40011551u, /* Base address: 0x40011500 Count: 81 */ - 0x4001165Bu, /* Base address: 0x40011600 Count: 91 */ - 0x40011747u, /* Base address: 0x40011700 Count: 71 */ - 0x40011907u, /* Base address: 0x40011900 Count: 7 */ - 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */ - 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ - 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */ - 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ - 0x40014310u, /* Base address: 0x40014300 Count: 16 */ - 0x40014412u, /* Base address: 0x40014400 Count: 18 */ - 0x40014516u, /* Base address: 0x40014500 Count: 22 */ - 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ - 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */ - 0x40014806u, /* Base address: 0x40014800 Count: 6 */ - 0x40014909u, /* Base address: 0x40014900 Count: 9 */ - 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */ - 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */ - 0x40015004u, /* Base address: 0x40015000 Count: 4 */ + 0x40010040u, /* Base address: 0x40010000 Count: 64 */ + 0x4001013Bu, /* Base address: 0x40010100 Count: 59 */ + 0x4001024Au, /* Base address: 0x40010200 Count: 74 */ + 0x40010354u, /* Base address: 0x40010300 Count: 84 */ + 0x40010441u, /* Base address: 0x40010400 Count: 65 */ + 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */ + 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ + 0x40010753u, /* Base address: 0x40010700 Count: 83 */ + 0x4001091Du, /* Base address: 0x40010900 Count: 29 */ + 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */ + 0x40010B54u, /* Base address: 0x40010B00 Count: 84 */ + 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ + 0x40010D4Bu, /* Base address: 0x40010D00 Count: 75 */ + 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */ + 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */ + 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */ + 0x40011555u, /* Base address: 0x40011500 Count: 85 */ + 0x40011658u, /* Base address: 0x40011600 Count: 88 */ + 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */ + 0x40011850u, /* Base address: 0x40011800 Count: 80 */ + 0x40011948u, /* Base address: 0x40011900 Count: 72 */ + 0x40011B0Au, /* Base address: 0x40011B00 Count: 10 */ + 0x4001401Au, /* Base address: 0x40014000 Count: 26 */ + 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */ + 0x40014217u, /* Base address: 0x40014200 Count: 23 */ + 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */ + 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */ + 0x40014515u, /* Base address: 0x40014500 Count: 21 */ + 0x40014610u, /* Base address: 0x40014600 Count: 16 */ + 0x40014716u, /* Base address: 0x40014700 Count: 22 */ + 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */ + 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */ + 0x40015005u, /* Base address: 0x40015000 Count: 5 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x1Bu}, - {0x00u, 0x11u}, - {0x01u, 0x02u}, + {0x0Au, 0x4Bu}, + {0x00u, 0x12u}, + {0x01u, 0x03u}, {0x18u, 0x04u}, {0x1Cu, 0x71u}, - {0x20u, 0x38u}, - {0x21u, 0x60u}, + {0x20u, 0xC0u}, + {0x21u, 0x58u}, {0x2Cu, 0x0Eu}, - {0x30u, 0x0Cu}, + {0x30u, 0x09u}, {0x31u, 0x0Au}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x85u, 0x0Fu}, - {0x00u, 0x20u}, - {0x04u, 0x01u}, - {0x08u, 0x51u}, - {0x0Au, 0x2Cu}, + {0x86u, 0x0Fu}, + {0x01u, 0x33u}, + {0x03u, 0xCCu}, + {0x04u, 0x3Fu}, + {0x08u, 0x04u}, + {0x0Au, 0x08u}, + {0x0Bu, 0xFFu}, {0x0Eu, 0x3Fu}, - {0x10u, 0x4Au}, - {0x12u, 0x15u}, - {0x1Cu, 0x4Bu}, - {0x1Eu, 0x34u}, - {0x20u, 0x06u}, - {0x22u, 0x40u}, - {0x26u, 0x10u}, - {0x30u, 0x3Fu}, - {0x32u, 0x40u}, - {0x3Eu, 0x04u}, - {0x40u, 0x34u}, - {0x41u, 0x05u}, - {0x42u, 0x20u}, - {0x45u, 0xCFu}, - {0x46u, 0xD2u}, - {0x47u, 0x0Eu}, + {0x0Fu, 0xFFu}, + {0x10u, 0x10u}, + {0x12u, 0x20u}, + {0x14u, 0x01u}, + {0x15u, 0xFFu}, + {0x16u, 0x02u}, + {0x18u, 0x3Fu}, + {0x19u, 0xFFu}, + {0x1Cu, 0x01u}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x02u}, + {0x1Fu, 0xF0u}, + {0x20u, 0x10u}, + {0x21u, 0x69u}, + {0x22u, 0x20u}, + {0x23u, 0x96u}, + {0x24u, 0x04u}, + {0x25u, 0x55u}, + {0x26u, 0x08u}, + {0x27u, 0xAAu}, + {0x2Au, 0x3Fu}, + {0x2Eu, 0x3Fu}, + {0x2Fu, 0xFFu}, + {0x30u, 0x30u}, + {0x32u, 0x03u}, + {0x34u, 0x0Cu}, + {0x37u, 0xFFu}, + {0x3Au, 0x2Au}, + {0x3Bu, 0x80u}, + {0x40u, 0x52u}, + {0x41u, 0x06u}, + {0x42u, 0x30u}, + {0x45u, 0xDCu}, + {0x46u, 0xE2u}, + {0x47u, 0x0Fu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -466,9 +505,10 @@ void cyfitter_cfg(void) {0x4Fu, 0x2Cu}, {0x56u, 0x01u}, {0x58u, 0x04u}, + {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x11u}, {0x5Du, 0x01u}, {0x5Fu, 0x01u}, {0x60u, 0x08u}, @@ -477,305 +517,256 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x80u, 0xC0u}, - {0x81u, 0x69u}, - {0x82u, 0x18u}, - {0x83u, 0x12u}, - {0x84u, 0x40u}, - {0x86u, 0x80u}, - {0x8Cu, 0x25u}, - {0x8Du, 0x20u}, - {0x8Eu, 0xD8u}, - {0x8Fu, 0x40u}, - {0x93u, 0x67u}, - {0x94u, 0x10u}, - {0x95u, 0x03u}, - {0x96u, 0x20u}, - {0x97u, 0x1Cu}, - {0x9Bu, 0x01u}, - {0x9Cu, 0xC4u}, - {0x9Du, 0x64u}, - {0x9Eu, 0x18u}, - {0xA0u, 0x02u}, - {0xA1u, 0x08u}, - {0xA2u, 0xD0u}, - {0xA3u, 0x77u}, - {0xA4u, 0x21u}, - {0xA5u, 0x02u}, - {0xA6u, 0xD8u}, - {0xA9u, 0x0Bu}, - {0xAAu, 0x01u}, - {0xABu, 0x74u}, - {0xACu, 0x40u}, - {0xADu, 0x20u}, - {0xAEu, 0x80u}, - {0xAFu, 0x40u}, - {0xB1u, 0x60u}, - {0xB2u, 0x30u}, - {0xB4u, 0xC0u}, - {0xB5u, 0x1Fu}, - {0xB6u, 0x0Fu}, - {0xB8u, 0x80u}, - {0xBAu, 0x28u}, - {0xBBu, 0x22u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDCu, 0x11u}, - {0xDFu, 0x01u}, - {0x03u, 0x59u}, - {0x05u, 0x44u}, - {0x07u, 0x40u}, - {0x0Au, 0x41u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x02u}, - {0x12u, 0x90u}, - {0x14u, 0x02u}, - {0x15u, 0x08u}, - {0x17u, 0x11u}, - {0x1Au, 0xD0u}, - {0x1Bu, 0x01u}, - {0x1Du, 0x40u}, - {0x1Eu, 0x27u}, - {0x1Fu, 0x40u}, - {0x24u, 0x40u}, - {0x27u, 0x88u}, - {0x2Du, 0x08u}, - {0x2Fu, 0x69u}, - {0x36u, 0x20u}, - {0x37u, 0x49u}, - {0x3Cu, 0x40u}, - {0x3Fu, 0x02u}, - {0x40u, 0x08u}, - {0x41u, 0x04u}, - {0x42u, 0x40u}, - {0x43u, 0x08u}, - {0x48u, 0x10u}, - {0x4Au, 0x81u}, - {0x51u, 0x80u}, - {0x52u, 0x18u}, - {0x53u, 0x20u}, - {0x59u, 0x06u}, - {0x5Au, 0x24u}, - {0x5Bu, 0x80u}, - {0x61u, 0x10u}, - {0x63u, 0x91u}, - {0x68u, 0x24u}, + {0xD6u, 0x08u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0x01u, 0x80u}, + {0x02u, 0x08u}, + {0x03u, 0x10u}, + {0x08u, 0x81u}, + {0x0Au, 0x18u}, + {0x10u, 0x40u}, + {0x12u, 0x22u}, + {0x13u, 0x10u}, + {0x19u, 0x04u}, + {0x1Au, 0x90u}, + {0x1Bu, 0x10u}, + {0x20u, 0x02u}, + {0x21u, 0x80u}, + {0x28u, 0x80u}, + {0x29u, 0x80u}, + {0x2Au, 0x04u}, + {0x31u, 0x80u}, + {0x32u, 0x04u}, + {0x33u, 0x10u}, + {0x34u, 0x10u}, + {0x35u, 0x10u}, + {0x39u, 0x80u}, + {0x3Bu, 0x12u}, + {0x43u, 0x14u}, + {0x48u, 0x40u}, + {0x49u, 0x80u}, + {0x4Bu, 0x18u}, + {0x53u, 0x58u}, + {0x58u, 0x40u}, + {0x59u, 0x24u}, + {0x5Au, 0x82u}, + {0x5Fu, 0x80u}, + {0x61u, 0x22u}, + {0x62u, 0x88u}, + {0x63u, 0x20u}, + {0x64u, 0x01u}, + {0x67u, 0x02u}, + {0x68u, 0x94u}, {0x69u, 0x40u}, - {0x6Au, 0x02u}, - {0x70u, 0x80u}, - {0x72u, 0xA8u}, - {0x78u, 0x08u}, - {0x7Au, 0x10u}, - {0x82u, 0x50u}, - {0x83u, 0x08u}, - {0x86u, 0x01u}, - {0x88u, 0x14u}, + {0x71u, 0x10u}, + {0x72u, 0x82u}, + {0x73u, 0x20u}, + {0x83u, 0x80u}, + {0x85u, 0x04u}, + {0x88u, 0x44u}, {0x8Du, 0x40u}, - {0x8Eu, 0x08u}, - {0x8Fu, 0x08u}, - {0xC0u, 0xBFu}, - {0xC2u, 0xA9u}, - {0xC4u, 0xFCu}, - {0xCAu, 0xF0u}, - {0xCCu, 0xF0u}, - {0xCEu, 0x90u}, - {0xD0u, 0x07u}, - {0xD2u, 0x08u}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x05u}, - {0xE2u, 0x08u}, - {0xE4u, 0x03u}, - {0xE6u, 0xC0u}, + {0xC0u, 0x07u}, + {0xC2u, 0x0Fu}, + {0xC4u, 0x0Fu}, + {0xCAu, 0x0Bu}, + {0xCCu, 0x0Eu}, + {0xCEu, 0x0Du}, + {0xD0u, 0x06u}, + {0xD2u, 0x0Cu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE2u, 0x01u}, + {0xE4u, 0x02u}, + {0xE6u, 0x40u}, + {0x05u, 0x20u}, + {0x07u, 0x40u}, + {0x09u, 0x64u}, {0x0Du, 0x02u}, - {0x0Fu, 0x01u}, - {0x10u, 0x0Au}, - {0x11u, 0x04u}, - {0x12u, 0x05u}, - {0x13u, 0x08u}, - {0x15u, 0x02u}, - {0x16u, 0x07u}, - {0x17u, 0x11u}, - {0x19u, 0x01u}, - {0x1Bu, 0x06u}, - {0x1Cu, 0x09u}, - {0x1Du, 0x02u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x09u}, - {0x22u, 0x08u}, - {0x24u, 0x04u}, - {0x25u, 0x02u}, - {0x26u, 0x08u}, - {0x27u, 0x21u}, - {0x31u, 0x0Cu}, - {0x32u, 0x0Fu}, - {0x33u, 0x03u}, - {0x35u, 0x20u}, - {0x37u, 0x10u}, - {0x3Bu, 0x08u}, - {0x3Fu, 0x01u}, - {0x56u, 0x08u}, + {0x0Eu, 0x02u}, + {0x11u, 0x20u}, + {0x13u, 0x40u}, + {0x15u, 0x03u}, + {0x17u, 0x1Cu}, + {0x19u, 0x69u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x12u}, + {0x23u, 0x01u}, + {0x27u, 0x67u}, + {0x28u, 0x01u}, + {0x29u, 0x08u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x77u}, + {0x2Du, 0x0Bu}, + {0x2Fu, 0x74u}, + {0x31u, 0x60u}, + {0x34u, 0x03u}, + {0x35u, 0x1Fu}, + {0x3Bu, 0x22u}, + {0x3Eu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x90u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x83u, 0x70u}, - {0x86u, 0x01u}, - {0x87u, 0x07u}, - {0x88u, 0x40u}, - {0x8Bu, 0x80u}, - {0x8Eu, 0x10u}, - {0x95u, 0x99u}, - {0x96u, 0x04u}, - {0x97u, 0x22u}, - {0x9Bu, 0x08u}, - {0x9Du, 0xAAu}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x55u}, - {0xA6u, 0x20u}, - {0xA9u, 0x44u}, - {0xAAu, 0x08u}, - {0xABu, 0x88u}, - {0xACu, 0x15u}, - {0xAEu, 0x2Au}, - {0xB0u, 0x40u}, - {0xB1u, 0xF0u}, - {0xB2u, 0x30u}, - {0xB3u, 0x0Fu}, - {0xB4u, 0x03u}, - {0xB6u, 0x0Cu}, - {0xBEu, 0x54u}, + {0x81u, 0x01u}, + {0x83u, 0x02u}, + {0x84u, 0xFFu}, + {0x85u, 0x3Fu}, + {0x8Bu, 0x3Fu}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0x3Fu}, + {0x90u, 0x0Fu}, + {0x92u, 0xF0u}, + {0x94u, 0x55u}, + {0x95u, 0x3Fu}, + {0x96u, 0xAAu}, + {0x98u, 0xFFu}, + {0x99u, 0x10u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x96u}, + {0x9Du, 0x04u}, + {0x9Eu, 0x69u}, + {0x9Fu, 0x08u}, + {0xA1u, 0x04u}, + {0xA3u, 0x08u}, + {0xA4u, 0x33u}, + {0xA5u, 0x10u}, + {0xA6u, 0xCCu}, + {0xA7u, 0x20u}, + {0xA9u, 0x01u}, + {0xAAu, 0xFFu}, + {0xABu, 0x02u}, + {0xAEu, 0xFFu}, + {0xAFu, 0x3Fu}, + {0xB0u, 0xFFu}, + {0xB1u, 0x03u}, + {0xB5u, 0x30u}, + {0xB7u, 0x0Cu}, + {0xB8u, 0x08u}, + {0xBAu, 0x02u}, + {0xBBu, 0xA2u}, + {0xBEu, 0x04u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x19u}, + {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x24u}, - {0x02u, 0x02u}, - {0x08u, 0x80u}, - {0x0Au, 0x10u}, - {0x0Eu, 0x62u}, - {0x0Fu, 0x20u}, - {0x10u, 0x06u}, - {0x12u, 0x20u}, - {0x14u, 0x10u}, - {0x16u, 0x80u}, + {0x01u, 0x80u}, + {0x03u, 0x10u}, + {0x06u, 0x01u}, + {0x08u, 0x08u}, + {0x09u, 0x80u}, + {0x0Au, 0x88u}, + {0x0Eu, 0x04u}, + {0x12u, 0x22u}, + {0x13u, 0x10u}, + {0x17u, 0x20u}, {0x18u, 0x20u}, - {0x19u, 0x80u}, - {0x1Bu, 0x22u}, - {0x1Eu, 0x30u}, - {0x21u, 0x05u}, - {0x22u, 0x02u}, - {0x24u, 0x80u}, - {0x25u, 0x41u}, - {0x27u, 0x68u}, - {0x2Bu, 0x08u}, - {0x2Fu, 0x10u}, - {0x30u, 0x20u}, - {0x31u, 0x04u}, - {0x32u, 0x40u}, - {0x36u, 0x80u}, - {0x37u, 0x2Au}, + {0x1Au, 0x80u}, + {0x1Fu, 0x20u}, + {0x21u, 0x21u}, + {0x22u, 0x81u}, + {0x25u, 0x02u}, + {0x26u, 0x01u}, + {0x27u, 0x08u}, + {0x28u, 0x40u}, + {0x29u, 0x90u}, + {0x2Bu, 0x10u}, + {0x2Cu, 0x20u}, + {0x2Du, 0x80u}, + {0x2Eu, 0x20u}, + {0x2Fu, 0x40u}, + {0x31u, 0x20u}, + {0x32u, 0x84u}, + {0x36u, 0x01u}, + {0x37u, 0x18u}, {0x38u, 0x04u}, - {0x39u, 0x0Au}, - {0x3Au, 0x2Au}, - {0x3Du, 0x80u}, - {0x58u, 0x60u}, - {0x5Au, 0x04u}, - {0x5Du, 0x20u}, - {0x5Fu, 0x40u}, - {0x60u, 0x0Au}, - {0x62u, 0x08u}, - {0x67u, 0x0Au}, - {0x6Bu, 0x02u}, - {0x6Cu, 0x04u}, - {0x6Du, 0x40u}, - {0x6Fu, 0x10u}, - {0x80u, 0x04u}, - {0x81u, 0x40u}, - {0x84u, 0xA0u}, - {0x88u, 0x18u}, - {0x8Bu, 0x0Au}, - {0x8Du, 0x0Cu}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x30u}, - {0x92u, 0xC0u}, - {0x93u, 0x40u}, - {0x96u, 0x20u}, - {0x97u, 0x13u}, - {0x99u, 0x20u}, - {0x9Au, 0xB0u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x12u}, - {0x9Fu, 0x50u}, - {0xA0u, 0xA0u}, - {0xA1u, 0x80u}, - {0xA2u, 0x01u}, - {0xA7u, 0x48u}, - {0xA9u, 0x28u}, - {0xAFu, 0x01u}, - {0xB2u, 0x08u}, - {0xB3u, 0x40u}, - {0xB5u, 0x80u}, - {0xB6u, 0xA0u}, - {0xC0u, 0x07u}, - {0xC2u, 0xB5u}, - {0xC4u, 0x37u}, - {0xCAu, 0x44u}, - {0xCCu, 0xFEu}, - {0xCEu, 0x17u}, - {0xD6u, 0x3Eu}, - {0xD8u, 0x3Eu}, - {0xE6u, 0xCAu}, - {0xEAu, 0x02u}, - {0xECu, 0x04u}, - {0xEEu, 0x81u}, - {0x00u, 0x3Fu}, - {0x01u, 0x01u}, - {0x03u, 0x02u}, - {0x04u, 0x04u}, - {0x06u, 0x08u}, - {0x08u, 0x01u}, - {0x09u, 0x10u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x20u}, + {0x39u, 0x82u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0xA0u}, + {0x3Fu, 0x08u}, + {0x59u, 0x04u}, + {0x5Au, 0x11u}, + {0x5Bu, 0x40u}, + {0x60u, 0x88u}, + {0x61u, 0x80u}, + {0x62u, 0x04u}, + {0x63u, 0x08u}, + {0x80u, 0x10u}, + {0x82u, 0x02u}, + {0x85u, 0x80u}, + {0x89u, 0x04u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x04u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x10u}, + {0x93u, 0x88u}, + {0x95u, 0x84u}, + {0x96u, 0x0Au}, + {0x97u, 0x10u}, + {0x98u, 0x10u}, + {0x9Au, 0x82u}, + {0x9Cu, 0x80u}, + {0x9Du, 0xA2u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x14u}, + {0xA0u, 0xC1u}, + {0xA5u, 0x22u}, + {0xA6u, 0xA2u}, + {0xA9u, 0x80u}, + {0xACu, 0x10u}, + {0xAFu, 0x34u}, + {0xB5u, 0x02u}, + {0xB7u, 0x08u}, + {0xC0u, 0x85u}, + {0xC2u, 0x4Fu}, + {0xC4u, 0x47u}, + {0xCAu, 0xFFu}, + {0xCCu, 0xEEu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x08u}, + {0xE2u, 0x20u}, + {0xE4u, 0x04u}, + {0xE6u, 0x21u}, + {0xE8u, 0x0Eu}, + {0xEAu, 0x10u}, + {0xECu, 0x0Au}, + {0x02u, 0x1Cu}, + {0x04u, 0x28u}, + {0x05u, 0x10u}, + {0x06u, 0x14u}, + {0x07u, 0x08u}, {0x0Cu, 0x10u}, - {0x0Du, 0x10u}, + {0x0Du, 0x01u}, {0x0Eu, 0x20u}, - {0x0Fu, 0x20u}, - {0x10u, 0x3Fu}, - {0x13u, 0x3Fu}, - {0x14u, 0x04u}, - {0x15u, 0x04u}, - {0x16u, 0x08u}, - {0x17u, 0x08u}, - {0x19u, 0x04u}, - {0x1Au, 0x3Fu}, - {0x1Bu, 0x08u}, - {0x1Cu, 0x10u}, - {0x1Du, 0x3Fu}, - {0x1Eu, 0x20u}, - {0x22u, 0x3Fu}, - {0x23u, 0x3Fu}, - {0x25u, 0x01u}, - {0x27u, 0x02u}, - {0x28u, 0x01u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x3Fu}, - {0x2Du, 0x3Fu}, - {0x2Eu, 0x3Fu}, - {0x30u, 0x03u}, - {0x33u, 0x30u}, - {0x34u, 0x0Cu}, - {0x35u, 0x0Cu}, - {0x36u, 0x30u}, - {0x37u, 0x03u}, - {0x3Au, 0xA2u}, - {0x3Bu, 0xA8u}, + {0x0Fu, 0x02u}, + {0x11u, 0x10u}, + {0x13u, 0x08u}, + {0x19u, 0x08u}, + {0x1Bu, 0x11u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x0Eu}, + {0x22u, 0x20u}, + {0x28u, 0x24u}, + {0x2Au, 0x08u}, + {0x2Du, 0x10u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x08u}, + {0x30u, 0x02u}, + {0x31u, 0x04u}, + {0x33u, 0x03u}, + {0x34u, 0x01u}, + {0x35u, 0x18u}, + {0x36u, 0x3Cu}, + {0x3Bu, 0x20u}, + {0x3Fu, 0x04u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -783,1237 +774,1462 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x82u, 0x70u}, - {0x84u, 0x0Fu}, - {0x8Du, 0x02u}, + {0x81u, 0x01u}, + {0x84u, 0x04u}, + {0x86u, 0x43u}, + {0x8Cu, 0x21u}, + {0x8Eu, 0x02u}, {0x8Fu, 0x01u}, - {0x90u, 0x40u}, - {0x91u, 0x01u}, - {0x92u, 0x1Fu}, - {0x93u, 0x02u}, - {0x94u, 0x06u}, - {0x95u, 0x02u}, - {0x96u, 0x09u}, - {0x97u, 0x05u}, - {0x98u, 0x05u}, - {0x99u, 0x02u}, - {0x9Au, 0x0Au}, - {0x9Bu, 0x09u}, - {0x9Cu, 0x10u}, - {0x9Eu, 0x2Fu}, - {0xA4u, 0x03u}, - {0xA6u, 0x0Cu}, - {0xA9u, 0x02u}, - {0xABu, 0x11u}, - {0xACu, 0x20u}, - {0xAEu, 0x4Fu}, - {0xB0u, 0x7Fu}, - {0xB1u, 0x03u}, - {0xB3u, 0x08u}, - {0xB5u, 0x10u}, - {0xB7u, 0x04u}, - {0xBBu, 0x02u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x60u}, - {0x03u, 0x40u}, - {0x05u, 0x01u}, - {0x07u, 0x13u}, - {0x08u, 0x08u}, - {0x0Au, 0x46u}, - {0x0Cu, 0x60u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x02u}, - {0x0Fu, 0x40u}, - {0x10u, 0x40u}, - {0x11u, 0x10u}, - {0x13u, 0x40u}, - {0x14u, 0x01u}, - {0x17u, 0x04u}, - {0x18u, 0x04u}, - {0x19u, 0x12u}, - {0x1Au, 0x02u}, - {0x1Bu, 0x40u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x80u}, - {0x22u, 0x10u}, - {0x23u, 0x11u}, - {0x24u, 0x40u}, - {0x25u, 0x40u}, - {0x26u, 0x16u}, - {0x28u, 0x51u}, - {0x2Bu, 0x08u}, - {0x2Cu, 0x01u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x04u}, - {0x32u, 0x18u}, - {0x33u, 0x41u}, - {0x36u, 0x16u}, - {0x39u, 0x80u}, - {0x3Bu, 0x11u}, - {0x3Du, 0x80u}, - {0x5Au, 0x80u}, - {0x5Cu, 0x60u}, - {0x5Fu, 0x0Au}, - {0x62u, 0xC0u}, - {0x66u, 0x80u}, - {0x84u, 0x30u}, - {0x85u, 0x12u}, - {0x8Au, 0x08u}, - {0x8Du, 0x40u}, - {0x8Eu, 0x40u}, - {0x90u, 0x80u}, - {0x91u, 0x80u}, - {0x92u, 0x40u}, - {0x93u, 0x0Au}, - {0x96u, 0x20u}, - {0x97u, 0x31u}, - {0x98u, 0x0Au}, - {0x9Au, 0x1Au}, - {0x9Bu, 0x70u}, - {0x9Cu, 0x04u}, - {0x9Du, 0x12u}, - {0xA0u, 0x80u}, - {0xA1u, 0x89u}, - {0xA2u, 0x09u}, - {0xA3u, 0x10u}, - {0xA4u, 0x12u}, - {0xA6u, 0xA0u}, - {0xA7u, 0x48u}, - {0xA9u, 0x40u}, - {0xACu, 0x40u}, - {0xB1u, 0x80u}, - {0xB2u, 0x04u}, - {0xB4u, 0x50u}, - {0xC0u, 0x3Fu}, - {0xC2u, 0xFFu}, - {0xC4u, 0xABu}, - {0xCAu, 0x2Fu}, - {0xCCu, 0xEFu}, - {0xCEu, 0x1Du}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE2u, 0x02u}, - {0xE6u, 0x02u}, - {0xEAu, 0x03u}, - {0xEEu, 0xC8u}, - {0x00u, 0x01u}, - {0x01u, 0xFFu}, - {0x02u, 0x0Eu}, - {0x04u, 0x02u}, - {0x07u, 0xFFu}, - {0x09u, 0x0Fu}, - {0x0Bu, 0xF0u}, - {0x0Cu, 0x04u}, - {0x0Du, 0xFFu}, - {0x10u, 0x18u}, - {0x11u, 0x69u}, - {0x12u, 0x03u}, - {0x13u, 0x96u}, - {0x14u, 0x03u}, - {0x15u, 0x55u}, - {0x16u, 0x14u}, - {0x17u, 0xAAu}, - {0x1Au, 0x1Fu}, - {0x1Eu, 0x08u}, - {0x22u, 0x20u}, - {0x23u, 0xFFu}, - {0x2Au, 0x01u}, - {0x2Bu, 0xFFu}, - {0x2Du, 0x33u}, - {0x2Fu, 0xCCu}, - {0x32u, 0x1Fu}, - {0x34u, 0x20u}, - {0x35u, 0xFFu}, - {0x3Bu, 0x20u}, - {0x54u, 0x01u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x10u}, - {0x5Fu, 0x01u}, - {0x81u, 0x04u}, - {0x82u, 0x10u}, - {0x83u, 0x20u}, - {0x85u, 0x01u}, - {0x87u, 0x5Eu}, - {0x88u, 0x04u}, - {0x89u, 0x39u}, - {0x8Au, 0x08u}, - {0x8Bu, 0x06u}, - {0x8Du, 0x46u}, - {0x8Eu, 0x07u}, - {0x90u, 0x0Au}, - {0x91u, 0x46u}, - {0x92u, 0x05u}, - {0x97u, 0x46u}, - {0x99u, 0x42u}, - {0x9Bu, 0x04u}, - {0x9Cu, 0x09u}, - {0x9Du, 0x46u}, - {0x9Eu, 0x02u}, - {0xA1u, 0x42u}, - {0xA2u, 0x08u}, - {0xA4u, 0x10u}, - {0xA6u, 0x20u}, - {0xAAu, 0x20u}, - {0xADu, 0x77u}, - {0xAFu, 0x08u}, - {0xB0u, 0x0Fu}, - {0xB1u, 0x08u}, - {0xB2u, 0x30u}, - {0xB3u, 0x70u}, - {0xB5u, 0x0Fu}, - {0xB7u, 0x01u}, - {0xB8u, 0x80u}, - {0xB9u, 0x20u}, - {0xBBu, 0x0Cu}, - {0xBEu, 0x44u}, - {0xBFu, 0x41u}, - {0xD4u, 0x09u}, + {0x92u, 0x01u}, + {0x96u, 0xECu}, + {0x98u, 0x88u}, + {0x9Au, 0x03u}, + {0x9Cu, 0xE0u}, + {0x9Du, 0x01u}, + {0xA5u, 0x01u}, + {0xA6u, 0x12u}, + {0xA9u, 0x01u}, + {0xAFu, 0x01u}, + {0xB0u, 0x10u}, + {0xB2u, 0x0Fu}, + {0xB4u, 0xE0u}, + {0xB5u, 0x01u}, + {0xBEu, 0x10u}, + {0xBFu, 0x10u}, + {0xD4u, 0x40u}, {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x02u, 0x80u}, - {0x03u, 0x08u}, - {0x04u, 0x80u}, - {0x05u, 0x02u}, - {0x06u, 0x10u}, - {0x0Au, 0x41u}, - {0x0Du, 0x80u}, - {0x0Eu, 0x64u}, - {0x10u, 0x80u}, - {0x13u, 0x28u}, - {0x16u, 0x40u}, - {0x17u, 0x10u}, - {0x18u, 0x40u}, - {0x1Au, 0x20u}, - {0x1Bu, 0x40u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x18u}, - {0x20u, 0x08u}, - {0x21u, 0x14u}, - {0x23u, 0x95u}, - {0x25u, 0x10u}, - {0x27u, 0x04u}, - {0x29u, 0x41u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x09u}, - {0x30u, 0x28u}, - {0x33u, 0x41u}, - {0x34u, 0x02u}, - {0x36u, 0x08u}, - {0x38u, 0x02u}, - {0x39u, 0x6Au}, - {0x3Du, 0x22u}, - {0x3Eu, 0x44u}, - {0x58u, 0x20u}, - {0x59u, 0x04u}, - {0x5Au, 0x02u}, - {0x5Bu, 0x80u}, - {0x5Du, 0x02u}, - {0x5Eu, 0x83u}, - {0x62u, 0x01u}, - {0x63u, 0x01u}, - {0x68u, 0x02u}, - {0x80u, 0x21u}, - {0x83u, 0x40u}, - {0x8Au, 0xA0u}, - {0x8Cu, 0x40u}, - {0x90u, 0x80u}, - {0x92u, 0x44u}, - {0x93u, 0x02u}, - {0x97u, 0x20u}, - {0x98u, 0x06u}, - {0x9Au, 0x52u}, - {0x9Bu, 0x10u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x80u}, - {0xA1u, 0x81u}, - {0xA2u, 0x49u}, - {0xA3u, 0x10u}, - {0xA4u, 0x12u}, + {0x01u, 0x80u}, + {0x03u, 0x90u}, + {0x04u, 0x44u}, + {0x0Au, 0x02u}, + {0x0Eu, 0xA8u}, + {0x0Fu, 0x01u}, + {0x10u, 0x81u}, + {0x13u, 0x10u}, + {0x15u, 0x08u}, + {0x18u, 0x08u}, + {0x1Bu, 0xC1u}, + {0x1Eu, 0xA0u}, + {0x1Fu, 0x10u}, + {0x20u, 0x20u}, + {0x22u, 0x1Du}, + {0x25u, 0x20u}, + {0x28u, 0x01u}, + {0x2Bu, 0x01u}, + {0x2Cu, 0x08u}, + {0x2Fu, 0x21u}, + {0x32u, 0x91u}, + {0x37u, 0x40u}, + {0x38u, 0x08u}, + {0x39u, 0x40u}, + {0x3Eu, 0x42u}, + {0x45u, 0x20u}, + {0x46u, 0x08u}, + {0x58u, 0x80u}, + {0x5Bu, 0x28u}, + {0x61u, 0x14u}, + {0x62u, 0x80u}, + {0x63u, 0x20u}, + {0x66u, 0x18u}, + {0x67u, 0x42u}, + {0x69u, 0x40u}, + {0x6Du, 0x94u}, + {0x80u, 0x08u}, + {0x85u, 0x50u}, + {0x88u, 0x80u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x41u}, + {0x91u, 0x80u}, + {0x92u, 0x80u}, + {0x93u, 0x88u}, + {0x95u, 0x04u}, + {0x96u, 0x0Cu}, + {0x97u, 0x10u}, + {0x98u, 0x10u}, + {0x9Au, 0x84u}, + {0x9Cu, 0x40u}, + {0x9Du, 0xB2u}, + {0x9Eu, 0x01u}, + {0x9Fu, 0x14u}, + {0xA0u, 0xC1u}, + {0xA1u, 0x01u}, + {0xA4u, 0x10u}, {0xA6u, 0x20u}, - {0xA7u, 0x08u}, + {0xA7u, 0x10u}, {0xA8u, 0x20u}, - {0xA9u, 0x20u}, - {0xAAu, 0x80u}, - {0xABu, 0x20u}, - {0xACu, 0x10u}, - {0xAEu, 0x04u}, - {0xAFu, 0x09u}, - {0xB0u, 0x04u}, - {0xB3u, 0x48u}, - {0xB6u, 0x01u}, - {0xB7u, 0x10u}, - {0xC0u, 0xBBu}, - {0xC2u, 0xF9u}, - {0xC4u, 0x5Eu}, - {0xCAu, 0xB9u}, - {0xCCu, 0xCFu}, - {0xCEu, 0xFFu}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x09u}, - {0xE2u, 0x09u}, - {0xE6u, 0x02u}, - {0xEAu, 0x02u}, - {0xEEu, 0x07u}, - {0x88u, 0x04u}, - {0x89u, 0x40u}, - {0x8Fu, 0x04u}, - {0x99u, 0x40u}, - {0x9Cu, 0x84u}, - {0xA0u, 0x24u}, - {0xA7u, 0x04u}, - {0xA8u, 0x02u}, - {0xA9u, 0x10u}, - {0xAAu, 0x40u}, - {0xAEu, 0x20u}, - {0xAFu, 0x04u}, - {0xB0u, 0x42u}, - {0xB6u, 0x08u}, - {0xB7u, 0x08u}, - {0xE0u, 0x40u}, - {0xE2u, 0xA9u}, - {0xE6u, 0x02u}, - {0xE8u, 0x10u}, - {0xEAu, 0x04u}, - {0xECu, 0x40u}, - {0xEEu, 0x80u}, - {0x02u, 0xFFu}, - {0x05u, 0x10u}, - {0x06u, 0xFFu}, - {0x08u, 0x50u}, - {0x0Au, 0xA0u}, - {0x0Bu, 0x08u}, - {0x0Fu, 0x04u}, - {0x10u, 0x05u}, - {0x12u, 0x0Au}, - {0x13u, 0x02u}, - {0x14u, 0x0Fu}, - {0x15u, 0x05u}, - {0x16u, 0xF0u}, - {0x17u, 0x0Au}, - {0x18u, 0x03u}, - {0x1Au, 0x0Cu}, - {0x1Cu, 0x06u}, - {0x1Eu, 0x09u}, - {0x20u, 0xFFu}, - {0x23u, 0x01u}, - {0x24u, 0x30u}, - {0x26u, 0xC0u}, - {0x2Cu, 0x60u}, - {0x2Eu, 0x90u}, - {0x31u, 0x0Cu}, - {0x33u, 0x03u}, - {0x35u, 0x10u}, - {0x36u, 0xFFu}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x05u}, - {0x56u, 0x08u}, + {0xA9u, 0x40u}, + {0xAAu, 0x02u}, + {0xABu, 0x60u}, + {0xB2u, 0x01u}, + {0xB5u, 0x01u}, + {0xB7u, 0x28u}, + {0xC0u, 0xADu}, + {0xC2u, 0xF1u}, + {0xC4u, 0x2Bu}, + {0xCAu, 0x78u}, + {0xCCu, 0x1Du}, + {0xCEu, 0x9Au}, + {0xD6u, 0x0Eu}, + {0xD8u, 0xFEu}, + {0xE6u, 0x04u}, + {0xEAu, 0x01u}, + {0xEEu, 0x49u}, + {0x02u, 0x10u}, + {0x04u, 0x01u}, + {0x05u, 0x0Au}, + {0x07u, 0x55u}, + {0x08u, 0x01u}, + {0x09u, 0x8Bu}, + {0x0Bu, 0x74u}, + {0x0Cu, 0x01u}, + {0x0Fu, 0x10u}, + {0x12u, 0x01u}, + {0x14u, 0x12u}, + {0x15u, 0x20u}, + {0x16u, 0x04u}, + {0x17u, 0x40u}, + {0x19u, 0x40u}, + {0x1Au, 0x0Eu}, + {0x1Bu, 0x80u}, + {0x1Cu, 0x08u}, + {0x1Eu, 0x10u}, + {0x23u, 0x7Fu}, + {0x25u, 0x01u}, + {0x28u, 0x14u}, + {0x29u, 0x06u}, + {0x2Au, 0x0Au}, + {0x2Cu, 0x01u}, + {0x2Du, 0x91u}, + {0x2Fu, 0x6Cu}, + {0x32u, 0x01u}, + {0x33u, 0x3Fu}, + {0x34u, 0x1Eu}, + {0x35u, 0xC0u}, + {0x36u, 0x01u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x44u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x90u}, - {0x5Du, 0x90u}, + {0x5Cu, 0x11u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, - {0x81u, 0x09u}, - {0x82u, 0x01u}, - {0x83u, 0x06u}, - {0x85u, 0x30u}, - {0x86u, 0x80u}, - {0x87u, 0xC0u}, - {0x88u, 0x01u}, - {0x89u, 0x50u}, - {0x8Au, 0x02u}, - {0x8Bu, 0xA0u}, - {0x8Du, 0x03u}, - {0x8Eu, 0x70u}, - {0x8Fu, 0x0Cu}, - {0x93u, 0xFFu}, - {0x94u, 0x02u}, - {0x96u, 0x05u}, - {0x97u, 0xFFu}, - {0x9Cu, 0x02u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0xFFu}, - {0xA0u, 0x40u}, - {0xA1u, 0x05u}, - {0xA2u, 0x80u}, - {0xA3u, 0x0Au}, - {0xA4u, 0xA0u}, - {0xA6u, 0x50u}, - {0xA8u, 0x90u}, - {0xA9u, 0x0Fu}, - {0xAAu, 0x20u}, - {0xABu, 0xF0u}, - {0xACu, 0x02u}, - {0xADu, 0x90u}, - {0xAEu, 0x09u}, - {0xAFu, 0x60u}, - {0xB0u, 0x04u}, - {0xB2u, 0x08u}, - {0xB4u, 0x03u}, - {0xB5u, 0xFFu}, - {0xB6u, 0xF0u}, + {0x82u, 0x7Fu}, + {0x84u, 0x78u}, + {0x86u, 0x03u}, + {0x88u, 0x20u}, + {0x8Au, 0x40u}, + {0x8Bu, 0xFFu}, + {0x8Cu, 0x02u}, + {0x8Fu, 0xFFu}, + {0x91u, 0x0Fu}, + {0x92u, 0x08u}, + {0x93u, 0xF0u}, + {0x94u, 0x01u}, + {0x95u, 0xFFu}, + {0x96u, 0x6Eu}, + {0x98u, 0x64u}, + {0x99u, 0xFFu}, + {0x9Cu, 0x03u}, + {0x9Eu, 0x74u}, + {0xA1u, 0x55u}, + {0xA3u, 0xAAu}, + {0xA5u, 0x69u}, + {0xA6u, 0x01u}, + {0xA7u, 0x96u}, + {0xA8u, 0x20u}, + {0xA9u, 0x33u}, + {0xAAu, 0x40u}, + {0xABu, 0xCCu}, + {0xAFu, 0xFFu}, + {0xB1u, 0xFFu}, + {0xB4u, 0x60u}, + {0xB6u, 0x1Fu}, {0xBAu, 0x20u}, - {0xBFu, 0x10u}, + {0xBBu, 0x02u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x18u}, - {0x03u, 0x40u}, - {0x05u, 0x55u}, - {0x08u, 0x14u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x80u}, - {0x0Du, 0x80u}, - {0x0Eu, 0x20u}, - {0x11u, 0x44u}, - {0x13u, 0x02u}, - {0x15u, 0x82u}, - {0x16u, 0x28u}, - {0x18u, 0x02u}, - {0x1Du, 0x51u}, - {0x1Eu, 0x20u}, - {0x20u, 0x80u}, - {0x22u, 0x28u}, - {0x27u, 0x04u}, - {0x2Au, 0x02u}, - {0x2Cu, 0x04u}, - {0x2Fu, 0x42u}, - {0x30u, 0x04u}, - {0x33u, 0x02u}, - {0x34u, 0x80u}, - {0x35u, 0x08u}, - {0x37u, 0x49u}, - {0x39u, 0x10u}, - {0x3Bu, 0x84u}, - {0x3Du, 0x14u}, - {0x3Eu, 0x03u}, - {0x3Fu, 0x40u}, - {0x58u, 0x40u}, - {0x5Eu, 0x40u}, - {0x5Fu, 0x10u}, - {0x60u, 0x02u}, + {0x00u, 0x80u}, + {0x01u, 0x20u}, + {0x02u, 0x40u}, + {0x03u, 0x10u}, + {0x04u, 0xA8u}, + {0x06u, 0x80u}, + {0x0Au, 0x09u}, + {0x0Bu, 0x90u}, + {0x0Eu, 0x45u}, + {0x0Fu, 0x10u}, + {0x11u, 0x04u}, + {0x12u, 0x04u}, + {0x16u, 0x02u}, + {0x17u, 0x10u}, + {0x19u, 0xA0u}, + {0x1Au, 0x01u}, + {0x1Eu, 0x06u}, + {0x1Fu, 0x08u}, + {0x22u, 0x02u}, + {0x25u, 0x04u}, + {0x26u, 0x10u}, + {0x27u, 0x14u}, + {0x28u, 0x40u}, + {0x29u, 0x94u}, + {0x2Du, 0x84u}, + {0x2Fu, 0x84u}, + {0x32u, 0x06u}, + {0x33u, 0x10u}, + {0x36u, 0x18u}, + {0x39u, 0x80u}, + {0x3Au, 0x40u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x08u}, + {0x3Fu, 0x10u}, + {0x41u, 0x40u}, + {0x43u, 0x80u}, + {0x58u, 0x80u}, + {0x5Bu, 0x20u}, + {0x62u, 0x20u}, {0x63u, 0x02u}, - {0x65u, 0x20u}, - {0x66u, 0x80u}, - {0x67u, 0x02u}, - {0x85u, 0x20u}, - {0x86u, 0x04u}, - {0x88u, 0x50u}, - {0x8Bu, 0x48u}, - {0x8Eu, 0x08u}, - {0x8Fu, 0x01u}, - {0x91u, 0xD6u}, - {0x92u, 0x05u}, - {0x93u, 0x94u}, - {0x94u, 0x02u}, - {0x99u, 0x04u}, - {0x9Au, 0x20u}, - {0x9Bu, 0x03u}, - {0x9Cu, 0x14u}, - {0x9Du, 0x28u}, - {0x9Eu, 0x82u}, - {0x9Fu, 0x44u}, - {0xA0u, 0x26u}, - {0xA1u, 0x80u}, - {0xA3u, 0x02u}, - {0xA7u, 0x0Du}, - {0xABu, 0x01u}, - {0xAEu, 0x40u}, - {0xAFu, 0x20u}, - {0xB3u, 0x10u}, - {0xB7u, 0x80u}, - {0xC0u, 0xFEu}, - {0xC2u, 0xAFu}, - {0xC4u, 0xFDu}, - {0xCAu, 0xB1u}, - {0xCCu, 0xD3u}, - {0xCEu, 0xFEu}, - {0xD6u, 0x38u}, - {0xD8u, 0x38u}, - {0xE0u, 0x20u}, - {0xE2u, 0x50u}, - {0xECu, 0x10u}, - {0xEEu, 0x2Au}, - {0x04u, 0xFFu}, - {0x05u, 0x01u}, - {0x07u, 0x12u}, - {0x08u, 0x55u}, - {0x0Au, 0xAAu}, - {0x0Du, 0x04u}, - {0x0Fu, 0x28u}, - {0x15u, 0x53u}, + {0x78u, 0x40u}, + {0x7Bu, 0x01u}, + {0x83u, 0x20u}, + {0x84u, 0x80u}, + {0x8Fu, 0x10u}, + {0x91u, 0x85u}, + {0x92u, 0x88u}, + {0x93u, 0x88u}, + {0x94u, 0x44u}, + {0x95u, 0x08u}, + {0x96u, 0x44u}, + {0x97u, 0x12u}, + {0x98u, 0x18u}, + {0x99u, 0x14u}, + {0x9Au, 0x85u}, + {0x9Cu, 0x40u}, + {0x9Du, 0xA2u}, + {0x9Eu, 0x12u}, + {0x9Fu, 0x54u}, + {0xA0u, 0x41u}, + {0xA1u, 0x01u}, + {0xA2u, 0x08u}, + {0xA4u, 0x08u}, + {0xA6u, 0x24u}, + {0xA7u, 0x20u}, + {0xAAu, 0x01u}, + {0xABu, 0x20u}, + {0xAFu, 0x18u}, + {0xB1u, 0x03u}, + {0xB3u, 0x40u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xC6u}, + {0xCAu, 0xFFu}, + {0xCCu, 0x67u}, + {0xCEu, 0x7Cu}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x0Cu}, + {0xE2u, 0x01u}, + {0xE6u, 0x06u}, + {0xEAu, 0x2Fu}, + {0xEEu, 0x20u}, + {0x65u, 0x08u}, + {0x66u, 0x08u}, + {0x81u, 0x01u}, + {0x82u, 0x04u}, + {0x89u, 0x40u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x21u}, + {0x91u, 0x60u}, + {0x94u, 0x30u}, + {0x95u, 0x92u}, + {0x98u, 0x0Cu}, + {0x9Au, 0x04u}, + {0x9Bu, 0x42u}, + {0x9Du, 0x48u}, + {0x9Eu, 0x1Au}, + {0xA0u, 0x30u}, + {0xA2u, 0x04u}, + {0xA3u, 0x08u}, + {0xA5u, 0x40u}, + {0xA9u, 0x01u}, + {0xB2u, 0x20u}, + {0xB3u, 0x04u}, + {0xE0u, 0x04u}, + {0xE2u, 0x01u}, + {0xE4u, 0x40u}, + {0xE6u, 0x02u}, + {0xE8u, 0x80u}, + {0xEAu, 0x0Bu}, + {0xEEu, 0xA0u}, + {0x00u, 0xFFu}, + {0x03u, 0x02u}, + {0x04u, 0x03u}, + {0x06u, 0x0Cu}, + {0x07u, 0x04u}, + {0x08u, 0x09u}, + {0x0Au, 0x06u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x04u}, + {0x10u, 0x0Fu}, + {0x12u, 0xF0u}, {0x16u, 0xFFu}, - {0x17u, 0xACu}, - {0x18u, 0x0Fu}, - {0x19u, 0x02u}, - {0x1Au, 0xF0u}, - {0x1Bu, 0x41u}, - {0x1Cu, 0x33u}, - {0x1Eu, 0xCCu}, - {0x21u, 0x08u}, - {0x22u, 0xFFu}, - {0x23u, 0x84u}, - {0x24u, 0x69u}, - {0x26u, 0x96u}, - {0x2Au, 0xFFu}, - {0x2Cu, 0xFFu}, - {0x31u, 0xC0u}, - {0x33u, 0x30u}, - {0x34u, 0xFFu}, - {0x37u, 0x0Fu}, - {0x3Au, 0x20u}, - {0x3Fu, 0x45u}, + {0x18u, 0xFFu}, + {0x20u, 0x05u}, + {0x22u, 0x0Au}, + {0x24u, 0x30u}, + {0x26u, 0xC0u}, + {0x28u, 0x50u}, + {0x2Au, 0xA0u}, + {0x2Cu, 0x90u}, + {0x2Eu, 0x60u}, + {0x2Fu, 0x01u}, + {0x30u, 0xFFu}, + {0x33u, 0x06u}, + {0x35u, 0x01u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x04u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x10u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, + {0x80u, 0x40u}, + {0x81u, 0x08u}, + {0x82u, 0x20u}, + {0x83u, 0x10u}, + {0x84u, 0x01u}, + {0x86u, 0x02u}, + {0x88u, 0x08u}, + {0x8Au, 0x10u}, + {0x8Bu, 0x10u}, + {0x8Du, 0x01u}, + {0x8Fu, 0x66u}, + {0x91u, 0x04u}, + {0x93u, 0x03u}, + {0x94u, 0x06u}, + {0x97u, 0x20u}, + {0x98u, 0x10u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x18u}, + {0x9Eu, 0x60u}, + {0xA0u, 0x20u}, + {0xA1u, 0xC5u}, + {0xA2u, 0x40u}, + {0xA3u, 0x02u}, + {0xA8u, 0x01u}, + {0xA9u, 0x03u}, + {0xAAu, 0x04u}, + {0xABu, 0xA4u}, + {0xACu, 0x02u}, + {0xAEu, 0x01u}, + {0xB2u, 0x07u}, + {0xB3u, 0xE0u}, + {0xB5u, 0x18u}, + {0xB6u, 0x78u}, + {0xB7u, 0x07u}, + {0xB8u, 0x08u}, + {0xBBu, 0x80u}, + {0xBEu, 0x40u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x08u}, + {0x02u, 0x04u}, + {0x03u, 0x80u}, + {0x04u, 0x20u}, + {0x06u, 0x10u}, + {0x07u, 0x40u}, + {0x0Bu, 0xA8u}, + {0x0Du, 0x70u}, + {0x0Eu, 0x10u}, + {0x0Fu, 0x02u}, + {0x10u, 0x28u}, + {0x11u, 0x41u}, + {0x15u, 0x10u}, + {0x16u, 0x02u}, + {0x17u, 0x02u}, + {0x19u, 0x02u}, + {0x1Eu, 0x10u}, + {0x1Fu, 0x80u}, + {0x23u, 0x14u}, + {0x24u, 0x02u}, + {0x26u, 0x14u}, + {0x27u, 0x01u}, + {0x28u, 0x02u}, + {0x2Du, 0x10u}, + {0x2Eu, 0x02u}, + {0x36u, 0x24u}, + {0x37u, 0x01u}, + {0x38u, 0x08u}, + {0x39u, 0x83u}, + {0x3Bu, 0x80u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x02u}, + {0x59u, 0x40u}, + {0x60u, 0x02u}, + {0x6Cu, 0x2Cu}, + {0x6Du, 0x40u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x46u}, + {0x74u, 0x10u}, + {0x75u, 0x01u}, + {0x76u, 0x20u}, + {0x77u, 0x02u}, + {0x80u, 0x01u}, + {0x8Bu, 0x10u}, + {0x8Du, 0x20u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x01u}, + {0x93u, 0x20u}, + {0x94u, 0x10u}, + {0x95u, 0x83u}, + {0x96u, 0x40u}, + {0x97u, 0x0Eu}, + {0x98u, 0x0Cu}, + {0x9Au, 0x04u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x0Au}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x04u}, + {0xA2u, 0x20u}, + {0xA3u, 0x08u}, + {0xA4u, 0x28u}, + {0xA6u, 0x10u}, + {0xA7u, 0x82u}, + {0xABu, 0x21u}, + {0xAEu, 0x10u}, + {0xB1u, 0x04u}, + {0xB3u, 0x40u}, + {0xB5u, 0x40u}, + {0xB6u, 0x22u}, + {0xC0u, 0x7Eu}, + {0xC2u, 0xEEu}, + {0xC4u, 0xDFu}, + {0xCAu, 0xA8u}, + {0xCCu, 0xE0u}, + {0xCEu, 0xBBu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE0u, 0x40u}, + {0xE2u, 0x20u}, + {0xE4u, 0x40u}, + {0xE6u, 0x10u}, + {0xEAu, 0x10u}, + {0xEEu, 0x91u}, + {0x01u, 0x04u}, + {0x03u, 0x03u}, + {0x07u, 0x38u}, + {0x09u, 0x04u}, + {0x0Bu, 0x02u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x04u}, + {0x10u, 0x02u}, + {0x11u, 0x04u}, + {0x13u, 0x82u}, + {0x15u, 0x20u}, + {0x17u, 0x40u}, + {0x19u, 0x04u}, + {0x1Bu, 0x02u}, + {0x21u, 0x48u}, + {0x23u, 0x10u}, + {0x28u, 0x01u}, + {0x29u, 0x50u}, + {0x2Bu, 0x28u}, + {0x2Fu, 0x40u}, + {0x30u, 0x02u}, + {0x31u, 0x06u}, + {0x33u, 0x80u}, + {0x34u, 0x01u}, + {0x35u, 0x78u}, + {0x37u, 0x01u}, + {0x3Bu, 0x02u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x19u}, + {0x5Fu, 0x01u}, {0x80u, 0xFFu}, - {0x81u, 0xFFu}, - {0x85u, 0x30u}, - {0x86u, 0xFFu}, - {0x87u, 0xC0u}, - {0x88u, 0x03u}, - {0x89u, 0x50u}, - {0x8Au, 0x0Cu}, - {0x8Bu, 0xA0u}, - {0x8Du, 0x05u}, - {0x8Fu, 0x0Au}, - {0x90u, 0x05u}, - {0x91u, 0x60u}, - {0x92u, 0x0Au}, - {0x93u, 0x90u}, - {0x94u, 0x0Fu}, - {0x96u, 0xF0u}, - {0x99u, 0x03u}, - {0x9Bu, 0x0Cu}, - {0x9Cu, 0x09u}, - {0x9Eu, 0x06u}, - {0x9Fu, 0xFFu}, - {0xA0u, 0xFFu}, - {0xA1u, 0x06u}, - {0xA3u, 0x09u}, + {0x84u, 0x03u}, + {0x85u, 0x04u}, + {0x86u, 0x0Cu}, + {0x87u, 0x12u}, + {0x88u, 0x50u}, + {0x89u, 0x04u}, + {0x8Au, 0xA0u}, + {0x8Bu, 0x02u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x04u}, + {0x90u, 0x60u}, + {0x92u, 0x90u}, + {0x95u, 0x01u}, + {0x96u, 0xFFu}, + {0x99u, 0x04u}, + {0x9Au, 0xFFu}, + {0x9Bu, 0x0Au}, + {0x9Du, 0x01u}, + {0xA0u, 0x05u}, + {0xA1u, 0x01u}, + {0xA2u, 0x0Au}, {0xA4u, 0x30u}, {0xA6u, 0xC0u}, - {0xA7u, 0xFFu}, - {0xA8u, 0x50u}, - {0xA9u, 0x0Fu}, - {0xAAu, 0xA0u}, - {0xABu, 0xF0u}, - {0xACu, 0x90u}, - {0xAEu, 0x60u}, - {0xB2u, 0xFFu}, - {0xB7u, 0xFFu}, - {0xBEu, 0x04u}, + {0xA8u, 0x06u}, + {0xA9u, 0x01u}, + {0xAAu, 0x09u}, + {0xACu, 0x0Fu}, + {0xADu, 0x04u}, + {0xAEu, 0xF0u}, + {0xAFu, 0x02u}, + {0xB1u, 0x06u}, + {0xB3u, 0x08u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x10u}, + {0xB7u, 0x01u}, + {0xB9u, 0x80u}, + {0xBBu, 0x02u}, + {0xBEu, 0x10u}, {0xBFu, 0x40u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x10u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x09u}, - {0x03u, 0x48u}, - {0x05u, 0x20u}, - {0x06u, 0x20u}, - {0x08u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x80u}, - {0x0Cu, 0x08u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x22u}, - {0x11u, 0x54u}, - {0x13u, 0x02u}, - {0x14u, 0x20u}, - {0x15u, 0x22u}, - {0x17u, 0x80u}, - {0x18u, 0x20u}, + {0x01u, 0x08u}, + {0x03u, 0x84u}, + {0x0Au, 0x40u}, + {0x0Bu, 0x28u}, + {0x0Fu, 0x40u}, + {0x10u, 0x20u}, + {0x11u, 0x01u}, + {0x12u, 0x06u}, + {0x17u, 0x20u}, + {0x19u, 0x10u}, + {0x1Du, 0x01u}, {0x1Eu, 0x04u}, - {0x22u, 0x40u}, - {0x25u, 0x02u}, - {0x26u, 0x80u}, - {0x27u, 0x23u}, - {0x28u, 0x04u}, - {0x29u, 0x08u}, - {0x2Au, 0x02u}, - {0x2Cu, 0x80u}, - {0x30u, 0x10u}, - {0x32u, 0x80u}, - {0x33u, 0x02u}, - {0x34u, 0x04u}, - {0x36u, 0x10u}, - {0x39u, 0x15u}, - {0x3Bu, 0x80u}, - {0x3Cu, 0x80u}, - {0x3Fu, 0x08u}, - {0x5Au, 0x40u}, - {0x5Eu, 0x80u}, - {0x61u, 0xC0u}, - {0x64u, 0x01u}, - {0x67u, 0x01u}, - {0x6Cu, 0x80u}, - {0x6Du, 0x54u}, - {0x6Fu, 0x02u}, - {0x74u, 0x66u}, - {0x85u, 0x04u}, - {0x88u, 0x20u}, - {0x89u, 0x03u}, - {0x8Cu, 0x80u}, - {0x8Du, 0x10u}, - {0x8Fu, 0x10u}, - {0x91u, 0xA0u}, - {0x92u, 0x41u}, - {0x93u, 0x84u}, - {0x94u, 0x22u}, - {0x96u, 0x80u}, - {0x99u, 0x04u}, - {0x9Au, 0x20u}, - {0x9Cu, 0x81u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x84u}, - {0xA1u, 0x10u}, - {0xA2u, 0x10u}, - {0xA4u, 0x08u}, - {0xA9u, 0x02u}, - {0xAFu, 0x04u}, - {0xB1u, 0x80u}, - {0xB5u, 0x08u}, - {0xC0u, 0x6Eu}, - {0xC2u, 0xEDu}, - {0xC4u, 0xFFu}, - {0xCAu, 0x87u}, - {0xCCu, 0x6Du}, - {0xCEu, 0x5Fu}, - {0xD6u, 0x18u}, + {0x21u, 0xA0u}, + {0x23u, 0x50u}, + {0x24u, 0x44u}, + {0x25u, 0x08u}, + {0x26u, 0x20u}, + {0x27u, 0x11u}, + {0x28u, 0x02u}, + {0x29u, 0x12u}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x21u}, + {0x31u, 0x20u}, + {0x32u, 0x84u}, + {0x36u, 0x08u}, + {0x37u, 0x11u}, + {0x3Bu, 0x54u}, + {0x3Cu, 0x44u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x02u}, + {0x58u, 0x40u}, + {0x5Cu, 0x50u}, + {0x5Du, 0x04u}, + {0x5Fu, 0x01u}, + {0x63u, 0x02u}, + {0x67u, 0x02u}, + {0x80u, 0x08u}, + {0x81u, 0x80u}, + {0x84u, 0x40u}, + {0x86u, 0x08u}, + {0x8Au, 0x05u}, + {0x8Bu, 0x08u}, + {0x8Eu, 0x20u}, + {0x92u, 0x18u}, + {0x93u, 0x20u}, + {0x95u, 0x82u}, + {0x96u, 0x40u}, + {0x98u, 0x05u}, + {0x9Au, 0x04u}, + {0x9Bu, 0x20u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x28u}, + {0x9Fu, 0x0Cu}, + {0xA2u, 0x80u}, + {0xA3u, 0x08u}, + {0xA4u, 0x28u}, + {0xA5u, 0x08u}, + {0xA7u, 0x82u}, + {0xABu, 0x10u}, + {0xACu, 0x4Du}, + {0xAFu, 0x40u}, + {0xB5u, 0x60u}, + {0xB7u, 0x04u}, + {0xC0u, 0x0Eu}, + {0xC2u, 0x1Eu}, + {0xC4u, 0x4Fu}, + {0xCAu, 0xBDu}, + {0xCCu, 0xEEu}, + {0xCEu, 0xFEu}, + {0xD6u, 0xF8u}, {0xD8u, 0x18u}, - {0xE0u, 0xF0u}, - {0xE6u, 0x18u}, - {0xE8u, 0x40u}, - {0xEAu, 0x20u}, - {0xECu, 0x80u}, - {0xEEu, 0x01u}, - {0x01u, 0x10u}, - {0x02u, 0x07u}, - {0x05u, 0x08u}, - {0x07u, 0x06u}, - {0x09u, 0x10u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x10u}, - {0x0Fu, 0x04u}, - {0x10u, 0x04u}, - {0x12u, 0x08u}, - {0x15u, 0x10u}, - {0x19u, 0x04u}, - {0x1Bu, 0x08u}, - {0x1Du, 0x10u}, - {0x1Eu, 0x20u}, - {0x21u, 0x08u}, - {0x22u, 0x08u}, - {0x23u, 0x04u}, - {0x28u, 0x09u}, - {0x29u, 0x08u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x04u}, - {0x2Cu, 0x0Au}, - {0x2Eu, 0x05u}, - {0x2Fu, 0x01u}, - {0x30u, 0x20u}, - {0x31u, 0x02u}, - {0x33u, 0x10u}, - {0x34u, 0x10u}, - {0x35u, 0x0Cu}, - {0x36u, 0x0Fu}, - {0x37u, 0x01u}, - {0x39u, 0x08u}, - {0x3Bu, 0x20u}, - {0x3Fu, 0x04u}, + {0xE2u, 0x10u}, + {0xE4u, 0xC0u}, + {0xE6u, 0x38u}, + {0xE8u, 0x50u}, + {0x01u, 0x05u}, + {0x02u, 0xFFu}, + {0x03u, 0x0Au}, + {0x05u, 0x03u}, + {0x07u, 0x0Cu}, + {0x08u, 0x50u}, + {0x0Au, 0xA0u}, + {0x0Bu, 0xFFu}, + {0x0Cu, 0xFFu}, + {0x0Du, 0x0Fu}, + {0x0Fu, 0xF0u}, + {0x10u, 0x60u}, + {0x11u, 0x90u}, + {0x12u, 0x90u}, + {0x13u, 0x60u}, + {0x15u, 0x50u}, + {0x16u, 0xFFu}, + {0x17u, 0xA0u}, + {0x18u, 0x30u}, + {0x19u, 0x30u}, + {0x1Au, 0xC0u}, + {0x1Bu, 0xC0u}, + {0x20u, 0x0Fu}, + {0x22u, 0xF0u}, + {0x23u, 0xFFu}, + {0x24u, 0x03u}, + {0x25u, 0x09u}, + {0x26u, 0x0Cu}, + {0x27u, 0x06u}, + {0x28u, 0x06u}, + {0x2Au, 0x09u}, + {0x2Bu, 0xFFu}, + {0x2Cu, 0x05u}, + {0x2Eu, 0x0Au}, + {0x34u, 0xFFu}, + {0x37u, 0xFFu}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x96u}, - {0x83u, 0x69u}, - {0x84u, 0xAAu}, - {0x86u, 0x55u}, - {0x87u, 0xFFu}, - {0x89u, 0xFFu}, - {0x8Au, 0x80u}, - {0x8Du, 0x55u}, - {0x8Fu, 0xAAu}, - {0x91u, 0x33u}, - {0x93u, 0xCCu}, - {0x95u, 0x0Fu}, - {0x96u, 0x70u}, - {0x97u, 0xF0u}, - {0x9Bu, 0xFFu}, - {0x9Du, 0xFFu}, - {0x9Eu, 0x07u}, - {0xA0u, 0x99u}, - {0xA2u, 0x22u}, - {0xA6u, 0x08u}, - {0xA8u, 0x44u}, - {0xAAu, 0x88u}, - {0xABu, 0xFFu}, - {0xB2u, 0xF0u}, - {0xB5u, 0xFFu}, - {0xB6u, 0x0Fu}, - {0xBBu, 0x20u}, + {0x81u, 0x02u}, + {0x83u, 0x05u}, + {0x84u, 0x1Au}, + {0x86u, 0x05u}, + {0x89u, 0x02u}, + {0x8Au, 0x08u}, + {0x8Bu, 0x01u}, + {0x8Eu, 0x40u}, + {0x91u, 0x02u}, + {0x93u, 0x01u}, + {0x96u, 0x20u}, + {0x99u, 0x01u}, + {0x9Au, 0x07u}, + {0x9Bu, 0x02u}, + {0x9Eu, 0x10u}, + {0xA1u, 0x02u}, + {0xA3u, 0x09u}, + {0xA4u, 0x19u}, + {0xA6u, 0x02u}, + {0xA8u, 0x14u}, + {0xAAu, 0x08u}, + {0xB0u, 0x10u}, + {0xB2u, 0x20u}, + {0xB3u, 0x03u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0x08u}, + {0xB6u, 0x40u}, + {0xB7u, 0x04u}, + {0xBBu, 0x08u}, + {0xBEu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x03u, 0x82u}, - {0x05u, 0x20u}, + {0x01u, 0x40u}, + {0x03u, 0x84u}, + {0x05u, 0x10u}, {0x06u, 0x20u}, - {0x09u, 0x01u}, - {0x0Au, 0x02u}, - {0x0Eu, 0x22u}, - {0x10u, 0x0Au}, - {0x12u, 0x80u}, - {0x14u, 0x80u}, - {0x15u, 0x04u}, - {0x16u, 0x08u}, - {0x19u, 0x11u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x82u}, - {0x1Eu, 0x22u}, - {0x1Fu, 0x40u}, - {0x20u, 0x60u}, - {0x21u, 0x50u}, - {0x22u, 0x31u}, - {0x23u, 0x04u}, + {0x07u, 0x01u}, + {0x08u, 0x10u}, + {0x0Au, 0x40u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x40u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x08u}, + {0x12u, 0x45u}, + {0x13u, 0x04u}, + {0x17u, 0x18u}, + {0x1Au, 0x08u}, + {0x1Eu, 0x18u}, + {0x1Fu, 0x61u}, + {0x22u, 0x80u}, {0x25u, 0x10u}, - {0x27u, 0x08u}, - {0x29u, 0x51u}, - {0x2Cu, 0x08u}, - {0x32u, 0x50u}, - {0x33u, 0x04u}, - {0x34u, 0x01u}, - {0x36u, 0x20u}, - {0x37u, 0x88u}, - {0x38u, 0x66u}, - {0x3Eu, 0xA8u}, - {0x3Fu, 0x02u}, - {0x58u, 0x60u}, - {0x5Du, 0x8Au}, - {0x5Fu, 0x10u}, - {0x60u, 0x04u}, - {0x63u, 0x02u}, - {0x67u, 0x01u}, - {0x80u, 0x02u}, - {0x81u, 0x01u}, - {0x82u, 0x28u}, - {0x83u, 0x01u}, - {0x84u, 0x30u}, - {0x85u, 0x20u}, - {0x88u, 0x40u}, - {0x89u, 0x04u}, - {0x8Bu, 0x10u}, - {0x8Du, 0x04u}, - {0x8Eu, 0xC0u}, - {0xC0u, 0x69u}, - {0xC2u, 0xA9u}, - {0xC4u, 0x7Bu}, - {0xCAu, 0x2Du}, - {0xCCu, 0xFEu}, - {0xCEu, 0xFFu}, - {0xD6u, 0xFCu}, - {0xD8u, 0x1Cu}, - {0xE0u, 0x70u}, - {0xE4u, 0x80u}, - {0xE6u, 0x08u}, - {0x85u, 0x0Bu}, - {0x86u, 0x82u}, - {0x87u, 0x24u}, - {0x88u, 0x04u}, - {0x89u, 0x15u}, - {0x8Au, 0x23u}, - {0x8Bu, 0x0Au}, - {0x8Cu, 0x70u}, - {0x91u, 0x30u}, - {0x95u, 0x04u}, - {0x96u, 0x7Cu}, - {0x97u, 0x03u}, - {0x9Au, 0x01u}, - {0x9Cu, 0x11u}, - {0x9Eu, 0x02u}, - {0xA1u, 0x09u}, - {0xA3u, 0x16u}, - {0xA4u, 0x48u}, - {0xA6u, 0x03u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x07u}, - {0xB4u, 0x80u}, - {0xB6u, 0x70u}, - {0xB7u, 0x38u}, - {0xB9u, 0x80u}, - {0xBBu, 0x08u}, - {0xBEu, 0x40u}, - {0xD6u, 0x02u}, - {0xD7u, 0x28u}, + {0x27u, 0x21u}, + {0x2Au, 0x04u}, + {0x2Bu, 0xA4u}, + {0x2Fu, 0x40u}, + {0x30u, 0x38u}, + {0x33u, 0x02u}, + {0x37u, 0x21u}, + {0x39u, 0x82u}, + {0x3Au, 0x49u}, + {0x3Bu, 0x24u}, + {0x3Du, 0x20u}, + {0x3Fu, 0x01u}, + {0x44u, 0x02u}, + {0x45u, 0x40u}, + {0x5Au, 0x80u}, + {0x5Cu, 0x0Au}, + {0x5Du, 0x20u}, + {0x5Fu, 0x40u}, + {0x63u, 0x01u}, + {0x67u, 0x02u}, + {0x82u, 0x40u}, + {0x87u, 0x10u}, + {0x89u, 0x40u}, + {0x8Bu, 0x08u}, + {0x8Du, 0x11u}, + {0xC0u, 0xEBu}, + {0xC2u, 0xEEu}, + {0xC4u, 0x6Fu}, + {0xCAu, 0x87u}, + {0xCCu, 0xA7u}, + {0xCEu, 0xAFu}, + {0xD6u, 0xF8u}, + {0xD8u, 0x18u}, + {0xE0u, 0x60u}, + {0xE2u, 0x01u}, + {0xE4u, 0x20u}, + {0xE6u, 0x41u}, + {0x00u, 0x03u}, + {0x02u, 0x0Cu}, + {0x04u, 0x20u}, + {0x06u, 0x4Fu}, + {0x0Cu, 0x40u}, + {0x0Eu, 0x1Fu}, + {0x10u, 0x06u}, + {0x12u, 0x09u}, + {0x16u, 0x70u}, + {0x1Eu, 0x80u}, + {0x24u, 0x0Fu}, + {0x28u, 0x10u}, + {0x2Au, 0x2Fu}, + {0x2Cu, 0x05u}, + {0x2Eu, 0x0Au}, + {0x30u, 0x80u}, + {0x32u, 0x7Fu}, + {0x40u, 0x26u}, + {0x41u, 0x04u}, + {0x42u, 0x30u}, + {0x44u, 0x05u}, + {0x45u, 0xCEu}, + {0x46u, 0xF0u}, + {0x47u, 0xDBu}, + {0x48u, 0x3Bu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x22u}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x08u}, + {0x50u, 0x04u}, + {0x58u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Cu, 0x01u}, + {0x5Fu, 0x01u}, + {0x62u, 0xC0u}, + {0x64u, 0x40u}, + {0x65u, 0x01u}, + {0x66u, 0x10u}, + {0x67u, 0x11u}, + {0x68u, 0xC0u}, + {0x69u, 0x01u}, + {0x6Bu, 0x11u}, + {0x6Cu, 0x40u}, + {0x6Du, 0x01u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x80u, 0x40u}, + {0x84u, 0x88u}, + {0x86u, 0x21u}, + {0x87u, 0xFFu}, + {0x88u, 0x01u}, + {0x89u, 0x80u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x1Fu}, + {0x8Fu, 0x20u}, + {0x90u, 0x87u}, + {0x91u, 0xC0u}, + {0x92u, 0x18u}, + {0x93u, 0x01u}, + {0x94u, 0x01u}, + {0x97u, 0x9Fu}, + {0x98u, 0xA2u}, + {0x99u, 0x7Fu}, + {0x9Au, 0x08u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x04u}, + {0x9Du, 0xC0u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x01u}, + {0xA3u, 0x60u}, + {0xA4u, 0x10u}, + {0xA5u, 0xC0u}, + {0xA7u, 0x04u}, + {0xA8u, 0x40u}, + {0xA9u, 0xC0u}, + {0xABu, 0x08u}, + {0xACu, 0x01u}, + {0xADu, 0x90u}, + {0xAFu, 0x40u}, + {0xB0u, 0x3Fu}, + {0xB2u, 0x80u}, + {0xB3u, 0xFFu}, + {0xB6u, 0x40u}, + {0xB8u, 0x82u}, + {0xBEu, 0x05u}, + {0xBFu, 0x04u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0x48u}, - {0x03u, 0x40u}, - {0x05u, 0x20u}, - {0x06u, 0x10u}, + {0x00u, 0x02u}, + {0x01u, 0x80u}, + {0x03u, 0x10u}, + {0x04u, 0x24u}, + {0x05u, 0x01u}, {0x07u, 0x01u}, - {0x0Au, 0x41u}, - {0x0Bu, 0x14u}, - {0x0Eu, 0x19u}, - {0x10u, 0x28u}, - {0x13u, 0x02u}, + {0x08u, 0x80u}, + {0x0Au, 0xA0u}, + {0x0Du, 0x0Au}, + {0x0Eu, 0x09u}, + {0x11u, 0x04u}, + {0x12u, 0x02u}, + {0x13u, 0x10u}, {0x15u, 0x08u}, - {0x18u, 0x04u}, + {0x17u, 0x62u}, + {0x18u, 0x80u}, {0x19u, 0x08u}, - {0x1Au, 0x42u}, - {0x1Eu, 0x18u}, - {0x1Fu, 0x80u}, - {0x21u, 0x80u}, - {0x26u, 0x08u}, - {0x27u, 0x11u}, - {0x2Au, 0x82u}, - {0x2Bu, 0x10u}, - {0x2Eu, 0x01u}, - {0x30u, 0x06u}, - {0x32u, 0xA0u}, + {0x1Au, 0x20u}, + {0x1Du, 0x05u}, + {0x1Eu, 0x01u}, + {0x27u, 0x20u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x41u}, + {0x2Fu, 0x20u}, + {0x35u, 0x10u}, {0x36u, 0x08u}, - {0x37u, 0x01u}, - {0x3Fu, 0x14u}, - {0x40u, 0x06u}, - {0x41u, 0x04u}, - {0x46u, 0x08u}, - {0x47u, 0x10u}, - {0x48u, 0x04u}, - {0x49u, 0x64u}, - {0x4Bu, 0x02u}, - {0x51u, 0x01u}, - {0x52u, 0x11u}, - {0x53u, 0x48u}, - {0x66u, 0x08u}, - {0x6Cu, 0x38u}, - {0x6Du, 0x44u}, - {0x6Eu, 0x20u}, - {0x6Fu, 0x60u}, - {0x77u, 0x02u}, - {0x82u, 0x80u}, - {0x83u, 0x80u}, - {0x89u, 0x80u}, + {0x37u, 0x42u}, + {0x3Cu, 0xA4u}, + {0x40u, 0x04u}, + {0x41u, 0x02u}, + {0x43u, 0x08u}, + {0x48u, 0x82u}, + {0x49u, 0x12u}, + {0x4Bu, 0x04u}, + {0x51u, 0x04u}, + {0x52u, 0x18u}, + {0x53u, 0x01u}, + {0x5Du, 0x10u}, + {0x5Eu, 0x82u}, + {0x5Fu, 0x04u}, + {0x64u, 0x02u}, + {0x67u, 0x40u}, + {0x80u, 0x40u}, + {0x84u, 0x02u}, + {0x85u, 0x48u}, + {0x89u, 0x12u}, + {0x8Bu, 0x40u}, {0x8Cu, 0x02u}, - {0x8Du, 0x10u}, - {0x8Eu, 0x40u}, - {0x8Fu, 0x01u}, - {0x91u, 0x08u}, - {0x92u, 0x01u}, - {0x93u, 0x14u}, - {0x94u, 0x20u}, - {0x95u, 0x46u}, - {0x96u, 0x02u}, - {0x97u, 0x80u}, - {0x98u, 0x04u}, - {0x99u, 0x40u}, - {0x9Au, 0x02u}, - {0x9Du, 0x14u}, - {0x9Eu, 0x11u}, - {0x9Fu, 0x42u}, - {0xA0u, 0x06u}, - {0xA2u, 0xA0u}, - {0xA3u, 0x10u}, - {0xA4u, 0x28u}, - {0xA6u, 0x10u}, - {0xA7u, 0x28u}, - {0xC0u, 0xEDu}, - {0xC2u, 0xEFu}, - {0xC4u, 0x2Eu}, - {0xCAu, 0x8Bu}, - {0xCCu, 0xCFu}, - {0xCEu, 0x60u}, - {0xD0u, 0x0Eu}, + {0x8Du, 0x04u}, + {0x90u, 0x24u}, + {0x91u, 0x04u}, + {0x92u, 0xC0u}, + {0x93u, 0x10u}, + {0x95u, 0x08u}, + {0x97u, 0x02u}, + {0x98u, 0x80u}, + {0x99u, 0x90u}, + {0x9Bu, 0x53u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x59u}, + {0xA1u, 0x0Au}, + {0xA2u, 0x47u}, + {0xA3u, 0x28u}, + {0xA4u, 0x80u}, + {0xA8u, 0x80u}, + {0xABu, 0x01u}, + {0xAEu, 0x10u}, + {0xB3u, 0x10u}, + {0xB5u, 0x10u}, + {0xC0u, 0xFDu}, + {0xC2u, 0xFDu}, + {0xC4u, 0xF7u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0x70u}, + {0xD0u, 0x07u}, {0xD2u, 0x0Cu}, - {0xD8u, 0x40u}, - {0xE0u, 0x10u}, - {0xE2u, 0x01u}, - {0xE6u, 0x40u}, - {0x00u, 0xC0u}, - {0x01u, 0x01u}, - {0x02u, 0x02u}, - {0x05u, 0x08u}, - {0x06u, 0x9Fu}, - {0x07u, 0x21u}, - {0x08u, 0xC0u}, - {0x09u, 0x22u}, - {0x0Au, 0x04u}, - {0x0Bu, 0x08u}, - {0x0Cu, 0x1Fu}, - {0x0Du, 0x04u}, - {0x0Eu, 0x20u}, - {0x11u, 0x01u}, - {0x12u, 0x60u}, - {0x14u, 0xC0u}, - {0x15u, 0x40u}, - {0x16u, 0x08u}, - {0x19u, 0x40u}, - {0x1Au, 0xFFu}, - {0x1Cu, 0x80u}, - {0x1Du, 0x01u}, - {0x20u, 0xC0u}, - {0x21u, 0x07u}, - {0x22u, 0x01u}, - {0x23u, 0x18u}, - {0x24u, 0x7Fu}, - {0x25u, 0x01u}, - {0x26u, 0x80u}, - {0x29u, 0x10u}, - {0x2Cu, 0x90u}, - {0x2Du, 0x01u}, - {0x2Eu, 0x40u}, - {0x33u, 0x3Fu}, - {0x34u, 0xFFu}, - {0x37u, 0x40u}, - {0x39u, 0x88u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x04u}, - {0x56u, 0x08u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x90u}, + {0xE0u, 0x01u}, + {0xE2u, 0x20u}, + {0xEAu, 0x01u}, + {0xECu, 0x08u}, + {0xEEu, 0x01u}, + {0x00u, 0x6Cu}, + {0x01u, 0xD6u}, + {0x04u, 0x40u}, + {0x05u, 0x29u}, + {0x06u, 0x2Cu}, + {0x07u, 0x46u}, + {0x08u, 0x64u}, + {0x09u, 0x02u}, + {0x0Au, 0x08u}, + {0x0Cu, 0x2Cu}, + {0x0Du, 0xD6u}, + {0x0Eu, 0x40u}, + {0x10u, 0x71u}, + {0x12u, 0x82u}, + {0x14u, 0xA4u}, + {0x15u, 0x21u}, + {0x16u, 0x40u}, + {0x17u, 0x8Eu}, + {0x18u, 0xC0u}, + {0x19u, 0x20u}, + {0x1Au, 0x2Fu}, + {0x1Bu, 0xD0u}, + {0x1Cu, 0x08u}, + {0x1Du, 0xD6u}, + {0x1Eu, 0x10u}, + {0x20u, 0x6Cu}, + {0x21u, 0x04u}, + {0x24u, 0x91u}, + {0x25u, 0xD2u}, + {0x26u, 0x4Eu}, + {0x27u, 0x04u}, + {0x29u, 0xD0u}, + {0x2Bu, 0x06u}, + {0x2Du, 0x17u}, + {0x2Fu, 0x28u}, + {0x30u, 0x0Fu}, + {0x32u, 0xC0u}, + {0x33u, 0xF0u}, + {0x34u, 0x31u}, + {0x35u, 0x0Fu}, + {0x37u, 0x08u}, + {0x39u, 0x20u}, + {0x3Au, 0x38u}, + {0x3Bu, 0x08u}, + {0x3Fu, 0x40u}, + {0x56u, 0x02u}, + {0x57u, 0x24u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x65u}, - {0x81u, 0x04u}, - {0x83u, 0x12u}, - {0x84u, 0x25u}, - {0x86u, 0x40u}, - {0x88u, 0x22u}, - {0x8Au, 0x01u}, - {0x8Cu, 0x60u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x05u}, - {0x8Fu, 0x0Au}, - {0x92u, 0x04u}, - {0x94u, 0x03u}, - {0x95u, 0x02u}, - {0x96u, 0x78u}, - {0x97u, 0x04u}, - {0x98u, 0x0Au}, - {0x99u, 0x04u}, - {0x9Au, 0x71u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x09u}, - {0x9Du, 0x04u}, - {0x9Eu, 0x12u}, - {0x9Fu, 0x03u}, - {0xA0u, 0x65u}, - {0xA8u, 0x05u}, - {0xAAu, 0x60u}, - {0xACu, 0x40u}, - {0xB0u, 0x03u}, - {0xB1u, 0x10u}, - {0xB2u, 0x04u}, - {0xB3u, 0x06u}, - {0xB4u, 0x03u}, - {0xB5u, 0x01u}, - {0xB6u, 0x78u}, - {0xB7u, 0x08u}, - {0xBAu, 0x22u}, - {0xBBu, 0x08u}, - {0xBEu, 0x04u}, - {0xD4u, 0x40u}, - {0xD6u, 0x04u}, + {0x80u, 0x06u}, + {0x82u, 0x09u}, + {0x87u, 0x01u}, + {0x88u, 0x60u}, + {0x89u, 0x95u}, + {0x8Au, 0x90u}, + {0x8Bu, 0x28u}, + {0x8Cu, 0x30u}, + {0x8Du, 0x02u}, + {0x8Eu, 0xC0u}, + {0x90u, 0x05u}, + {0x92u, 0x0Au}, + {0x97u, 0x08u}, + {0x98u, 0x03u}, + {0x99u, 0xA4u}, + {0x9Au, 0x0Cu}, + {0x9Bu, 0x58u}, + {0x9Cu, 0x0Fu}, + {0x9Eu, 0xF0u}, + {0x9Fu, 0x70u}, + {0xA0u, 0x50u}, + {0xA2u, 0xA0u}, + {0xA7u, 0x80u}, + {0xADu, 0x41u}, + {0xAFu, 0x88u}, + {0xB0u, 0xFFu}, + {0xB3u, 0x0Fu}, + {0xB7u, 0xF0u}, + {0xB9u, 0x08u}, + {0xBEu, 0x01u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x10u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x01u, 0x64u}, - {0x03u, 0x40u}, - {0x04u, 0x20u}, - {0x05u, 0x40u}, - {0x06u, 0x10u}, - {0x07u, 0x40u}, - {0x08u, 0x02u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x94u}, - {0x0Eu, 0xA0u}, - {0x0Fu, 0x06u}, - {0x10u, 0x08u}, - {0x12u, 0x01u}, - {0x13u, 0x02u}, - {0x15u, 0x48u}, - {0x17u, 0x03u}, - {0x18u, 0x10u}, - {0x19u, 0x61u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x81u}, + {0x02u, 0x89u}, + {0x04u, 0x28u}, + {0x07u, 0x41u}, + {0x09u, 0x01u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x80u}, + {0x0Du, 0x0Au}, + {0x0Eu, 0x08u}, + {0x11u, 0x01u}, + {0x17u, 0x0Au}, + {0x19u, 0x02u}, + {0x1Cu, 0xE0u}, + {0x1Du, 0x1Au}, {0x1Eu, 0x08u}, - {0x20u, 0x60u}, - {0x21u, 0x08u}, - {0x22u, 0x50u}, - {0x25u, 0x40u}, - {0x26u, 0x40u}, - {0x27u, 0x20u}, - {0x2Du, 0x40u}, - {0x2Fu, 0xA8u}, - {0x31u, 0x08u}, - {0x32u, 0x50u}, + {0x1Fu, 0x02u}, + {0x22u, 0x80u}, + {0x23u, 0x10u}, + {0x24u, 0x04u}, + {0x26u, 0x50u}, + {0x27u, 0x28u}, + {0x28u, 0x10u}, + {0x29u, 0x80u}, + {0x2Cu, 0x88u}, + {0x2Fu, 0x22u}, + {0x32u, 0x84u}, + {0x33u, 0x10u}, {0x36u, 0x04u}, - {0x37u, 0x62u}, + {0x37u, 0x60u}, + {0x39u, 0x84u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x24u}, + {0x3Eu, 0x42u}, + {0x59u, 0x40u}, + {0x64u, 0x08u}, + {0x6Cu, 0x5Cu}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x61u}, + {0x76u, 0x02u}, + {0x77u, 0x02u}, + {0x86u, 0x88u}, + {0x88u, 0x40u}, + {0x91u, 0x85u}, + {0x92u, 0x8Cu}, + {0x94u, 0xECu}, + {0x95u, 0x08u}, + {0x96u, 0x40u}, + {0x97u, 0x12u}, + {0x98u, 0x18u}, + {0x99u, 0x80u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x10u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x12u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x01u}, + {0xA1u, 0x01u}, + {0xA2u, 0x03u}, + {0xA3u, 0x08u}, + {0xA4u, 0x08u}, + {0xA6u, 0x04u}, + {0xA7u, 0x20u}, + {0xB1u, 0x80u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xFBu}, + {0xC4u, 0x38u}, + {0xCAu, 0xFAu}, + {0xCCu, 0x7Eu}, + {0xCEu, 0xFEu}, + {0xD6u, 0x08u}, + {0xD8u, 0x20u}, + {0xE2u, 0x8Au}, + {0xE4u, 0x08u}, + {0xEAu, 0x02u}, + {0xEEu, 0x08u}, + {0x02u, 0x08u}, + {0x03u, 0x02u}, + {0x06u, 0x10u}, + {0x08u, 0x01u}, + {0x09u, 0x28u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x14u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x02u}, + {0x10u, 0x14u}, + {0x12u, 0x28u}, + {0x14u, 0x02u}, + {0x16u, 0x01u}, + {0x17u, 0x20u}, + {0x1Bu, 0x1Cu}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x01u}, + {0x1Fu, 0x01u}, + {0x20u, 0x02u}, + {0x21u, 0x10u}, + {0x22u, 0x41u}, + {0x23u, 0x20u}, + {0x24u, 0x02u}, + {0x26u, 0x01u}, + {0x2Au, 0x04u}, + {0x2Bu, 0x40u}, + {0x2Du, 0x24u}, + {0x2Fu, 0x08u}, + {0x30u, 0x0Cu}, + {0x32u, 0x03u}, + {0x33u, 0x3Cu}, + {0x34u, 0x30u}, + {0x35u, 0x40u}, + {0x36u, 0x40u}, + {0x37u, 0x03u}, + {0x3Au, 0x08u}, + {0x3Eu, 0x11u}, + {0x3Fu, 0x40u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Fu, 0x01u}, + {0x81u, 0x0Au}, + {0x83u, 0x05u}, + {0x86u, 0x07u}, + {0x8Cu, 0x09u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x07u}, + {0x90u, 0x10u}, + {0x92u, 0x20u}, + {0x95u, 0x10u}, + {0x96u, 0x08u}, + {0x97u, 0x20u}, + {0x9Bu, 0x20u}, + {0x9Du, 0x04u}, + {0x9Fu, 0x08u}, + {0xA0u, 0x04u}, + {0xA2u, 0x08u}, + {0xA4u, 0x0Au}, + {0xA6u, 0x05u}, + {0xA7u, 0x10u}, + {0xAAu, 0x10u}, + {0xABu, 0x08u}, + {0xADu, 0x09u}, + {0xAEu, 0x20u}, + {0xAFu, 0x02u}, + {0xB0u, 0x30u}, + {0xB1u, 0x0Fu}, + {0xB2u, 0x0Fu}, + {0xB5u, 0x30u}, + {0xBEu, 0x01u}, + {0xBFu, 0x10u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x88u}, + {0x04u, 0x10u}, + {0x07u, 0x62u}, + {0x08u, 0x04u}, + {0x0Au, 0x40u}, + {0x0Eu, 0x52u}, + {0x10u, 0x80u}, + {0x11u, 0x48u}, + {0x12u, 0x04u}, + {0x15u, 0x20u}, + {0x16u, 0x40u}, + {0x17u, 0x08u}, + {0x19u, 0x09u}, + {0x1Cu, 0x10u}, + {0x1Eu, 0x06u}, + {0x1Fu, 0x02u}, + {0x20u, 0x40u}, + {0x21u, 0x01u}, + {0x22u, 0x10u}, + {0x24u, 0x20u}, + {0x26u, 0x80u}, + {0x27u, 0x28u}, + {0x29u, 0x88u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x80u}, + {0x2Du, 0x80u}, + {0x2Eu, 0x10u}, + {0x30u, 0xA0u}, + {0x33u, 0x04u}, + {0x34u, 0x08u}, + {0x35u, 0x40u}, + {0x37u, 0x20u}, {0x38u, 0x40u}, - {0x3Bu, 0x02u}, - {0x3Du, 0x80u}, - {0x3Fu, 0x16u}, - {0x5Cu, 0x80u}, - {0x60u, 0x12u}, - {0x61u, 0x10u}, - {0x63u, 0x80u}, - {0x67u, 0x02u}, - {0x88u, 0x80u}, - {0x8Fu, 0x40u}, - {0x91u, 0x08u}, - {0x93u, 0x14u}, - {0x95u, 0x42u}, - {0x96u, 0x02u}, - {0x98u, 0x04u}, - {0x9Au, 0x02u}, - {0x9Du, 0x45u}, - {0x9Fu, 0x41u}, - {0xA0u, 0x06u}, - {0xA2u, 0xA0u}, - {0xA3u, 0x10u}, - {0xA4u, 0x38u}, - {0xB0u, 0x02u}, - {0xB3u, 0x08u}, - {0xB6u, 0x11u}, - {0xB7u, 0x20u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xFFu}, - {0xC4u, 0xBBu}, - {0xCAu, 0xF0u}, - {0xCCu, 0xFEu}, - {0xCEu, 0xF9u}, - {0xD6u, 0x10u}, - {0xD8u, 0x1Fu}, - {0xE6u, 0x40u}, - {0xEAu, 0x40u}, - {0xEEu, 0x48u}, - {0x9Cu, 0x80u}, - {0xA0u, 0x20u}, - {0xB0u, 0x04u}, - {0xB4u, 0x20u}, - {0xE2u, 0x20u}, + {0x3Au, 0x01u}, + {0x3Eu, 0x61u}, + {0x5Au, 0x80u}, + {0x62u, 0x40u}, + {0x69u, 0x80u}, + {0x6Au, 0x40u}, + {0x82u, 0x10u}, + {0x84u, 0x10u}, + {0x85u, 0x40u}, + {0x86u, 0x05u}, + {0x89u, 0x40u}, + {0x8Au, 0x90u}, + {0x8Fu, 0x02u}, + {0x91u, 0x60u}, + {0x94u, 0x30u}, + {0x95u, 0x92u}, + {0x98u, 0x0Cu}, + {0x9Au, 0x25u}, + {0x9Bu, 0x42u}, + {0x9Du, 0x09u}, + {0x9Eu, 0x12u}, + {0xA0u, 0xB0u}, + {0xA1u, 0x04u}, + {0xA3u, 0x08u}, + {0xA5u, 0x40u}, + {0xB0u, 0x80u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xBCu}, + {0xC4u, 0x7Fu}, + {0xCAu, 0xBEu}, + {0xCCu, 0x7Eu}, + {0xCEu, 0xB9u}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE2u, 0x80u}, + {0xE4u, 0x24u}, + {0xEAu, 0x02u}, {0xECu, 0x80u}, - {0xEEu, 0x18u}, - {0x80u, 0x20u}, - {0x88u, 0x80u}, - {0x9Cu, 0x80u}, - {0xA0u, 0x20u}, - {0xE0u, 0x20u}, - {0x13u, 0x20u}, + {0xEEu, 0x08u}, + {0x82u, 0x10u}, + {0x96u, 0x10u}, + {0xA9u, 0x40u}, + {0xAAu, 0x01u}, + {0xABu, 0x04u}, + {0xADu, 0x10u}, + {0xB1u, 0x80u}, + {0xB6u, 0x42u}, + {0xE8u, 0x40u}, + {0xECu, 0x80u}, + {0x13u, 0x10u}, {0x16u, 0x80u}, - {0x17u, 0x40u}, - {0x33u, 0x08u}, + {0x17u, 0x20u}, + {0x30u, 0x08u}, + {0x35u, 0x01u}, {0x36u, 0x80u}, - {0x37u, 0x08u}, - {0x39u, 0x08u}, + {0x39u, 0x04u}, {0x3Au, 0x80u}, - {0x3Cu, 0x04u}, - {0x3Fu, 0x10u}, - {0x41u, 0x20u}, - {0x56u, 0x20u}, - {0x5Au, 0x04u}, - {0x60u, 0x40u}, - {0x65u, 0x01u}, - {0x66u, 0x40u}, - {0x86u, 0x20u}, - {0x8Bu, 0x10u}, - {0x8Eu, 0x40u}, + {0x3Cu, 0x08u}, + {0x3Fu, 0x20u}, + {0x42u, 0x08u}, + {0x49u, 0x10u}, + {0x4Bu, 0x10u}, + {0x5Bu, 0x40u}, + {0x5Eu, 0x04u}, + {0x61u, 0x40u}, + {0x63u, 0x08u}, + {0x64u, 0x40u}, + {0x8Du, 0x01u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x40u}, + {0xD4u, 0x80u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x10u}, - {0x30u, 0x20u}, - {0x32u, 0x01u}, - {0x37u, 0x44u}, - {0x3Bu, 0x10u}, - {0x52u, 0x20u}, - {0x56u, 0x20u}, - {0x5Au, 0x40u}, - {0x5Du, 0x02u}, - {0x68u, 0x20u}, - {0x6Bu, 0x20u}, - {0x81u, 0x02u}, - {0x82u, 0x20u}, - {0x8Bu, 0x08u}, - {0x8Eu, 0x20u}, - {0x92u, 0x40u}, - {0x94u, 0x44u}, + {0x31u, 0x10u}, + {0x33u, 0x01u}, + {0x34u, 0x01u}, + {0x37u, 0x20u}, + {0x39u, 0x20u}, + {0x53u, 0x04u}, + {0x57u, 0x02u}, + {0x58u, 0x80u}, + {0x66u, 0x80u}, + {0x81u, 0x01u}, + {0x83u, 0x40u}, + {0x88u, 0x88u}, {0x96u, 0x04u}, - {0x9Bu, 0x60u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x08u}, - {0xA5u, 0x20u}, + {0x99u, 0x10u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x40u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x40u}, + {0xA4u, 0x0Cu}, {0xA6u, 0x80u}, - {0xA7u, 0x08u}, - {0xB1u, 0x04u}, + {0xA7u, 0x04u}, + {0xADu, 0x04u}, + {0xB7u, 0x10u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, - {0xD4u, 0xE0u}, - {0xD6u, 0x80u}, - {0xE6u, 0xA0u}, + {0xD4u, 0xA0u}, + {0xD6u, 0xA0u}, + {0xE2u, 0x20u}, + {0xE6u, 0x80u}, + {0xEEu, 0x40u}, {0x12u, 0x80u}, {0x33u, 0x80u}, - {0x94u, 0x44u}, - {0x96u, 0x02u}, - {0x97u, 0x10u}, - {0x9Fu, 0x04u}, - {0xA5u, 0x20u}, + {0x59u, 0x01u}, + {0x86u, 0x80u}, + {0x87u, 0x04u}, + {0x95u, 0x20u}, + {0x96u, 0x04u}, + {0x97u, 0x08u}, + {0x99u, 0x01u}, + {0x9Cu, 0x41u}, + {0x9Eu, 0x88u}, + {0x9Fu, 0x01u}, + {0xA4u, 0x04u}, {0xA6u, 0x80u}, - {0xA7u, 0x08u}, - {0xAEu, 0x04u}, - {0xB2u, 0x40u}, - {0xB5u, 0x01u}, + {0xABu, 0x04u}, + {0xADu, 0x40u}, + {0xB7u, 0x02u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0xEAu, 0x40u}, - {0x61u, 0x01u}, - {0x81u, 0x01u}, - {0x83u, 0x04u}, - {0x86u, 0x01u}, - {0x87u, 0x10u}, - {0x94u, 0x44u}, - {0x96u, 0x02u}, - {0x97u, 0x10u}, - {0x9Fu, 0x04u}, - {0xA5u, 0x20u}, + {0xD6u, 0x40u}, + {0xE2u, 0x40u}, + {0xE6u, 0x10u}, + {0xEEu, 0x30u}, + {0x83u, 0x20u}, + {0x96u, 0x04u}, + {0x9Cu, 0x40u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x01u}, + {0xA2u, 0x20u}, {0xA7u, 0x80u}, - {0xAFu, 0x08u}, - {0xD8u, 0x40u}, - {0xE2u, 0xB0u}, - {0xE6u, 0x40u}, + {0xACu, 0x01u}, + {0xAEu, 0x20u}, + {0xB0u, 0x04u}, + {0xB1u, 0x10u}, + {0xE6u, 0x20u}, + {0xEAu, 0x40u}, {0xEEu, 0x40u}, - {0x09u, 0x04u}, - {0x0Au, 0x08u}, - {0x0Fu, 0x20u}, - {0x10u, 0x10u}, - {0x14u, 0x80u}, - {0x51u, 0x08u}, - {0x53u, 0x01u}, - {0x55u, 0x40u}, - {0x5Du, 0x80u}, - {0x86u, 0x04u}, - {0x8Bu, 0x80u}, - {0x8Du, 0x04u}, + {0x08u, 0x02u}, + {0x09u, 0x80u}, + {0x0Du, 0x01u}, + {0x10u, 0x20u}, + {0x14u, 0x20u}, + {0x51u, 0x04u}, + {0x56u, 0x01u}, + {0x57u, 0x40u}, + {0x59u, 0x10u}, + {0x80u, 0x20u}, + {0x81u, 0x80u}, {0xC2u, 0x0Eu}, {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0xE2u, 0x01u}, - {0xE6u, 0x02u}, - {0x03u, 0x88u}, - {0x05u, 0x40u}, - {0x06u, 0x20u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x80u}, - {0x0Du, 0x10u}, - {0x0Eu, 0x20u}, - {0x85u, 0x40u}, - {0x89u, 0x08u}, - {0x8Fu, 0x01u}, - {0x97u, 0x02u}, - {0x9Du, 0x80u}, - {0xA3u, 0x10u}, - {0xA5u, 0x48u}, - {0xA7u, 0x80u}, - {0xA8u, 0x80u}, - {0xB0u, 0x10u}, - {0xC0u, 0x0Fu}, - {0xC2u, 0x0Fu}, - {0xE0u, 0x02u}, - {0xE4u, 0x04u}, - {0xEAu, 0x04u}, - {0x8Au, 0x10u}, - {0x8Du, 0x80u}, - {0x8Fu, 0x10u}, - {0x9Au, 0x20u}, - {0x9Du, 0x80u}, - {0xA2u, 0x10u}, - {0xA3u, 0x10u}, - {0xA5u, 0x40u}, - {0xAEu, 0x04u}, - {0xAFu, 0x08u}, - {0xB1u, 0x10u}, - {0xB3u, 0x40u}, - {0xE2u, 0x09u}, - {0xE4u, 0x02u}, - {0xEEu, 0x05u}, + {0x02u, 0x04u}, + {0x03u, 0x40u}, + {0x04u, 0x01u}, + {0x07u, 0x08u}, {0x0Au, 0x01u}, {0x0Bu, 0x20u}, + {0x0Cu, 0x08u}, + {0x0Du, 0x80u}, + {0x84u, 0x20u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x80u}, + {0x91u, 0x02u}, + {0x95u, 0x08u}, + {0x98u, 0x22u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x01u}, + {0xA7u, 0x40u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x0Fu}, + {0xE2u, 0x08u}, + {0xE6u, 0x08u}, + {0x89u, 0x05u}, + {0x91u, 0x02u}, + {0x93u, 0x20u}, + {0x95u, 0x08u}, + {0x98u, 0x02u}, + {0x9Au, 0x04u}, + {0x9Bu, 0x08u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x01u}, + {0xA0u, 0x08u}, + {0xA7u, 0x40u}, + {0xABu, 0x40u}, + {0xB2u, 0x01u}, + {0xE2u, 0x04u}, + {0xE4u, 0x01u}, + {0xEEu, 0x01u}, + {0x09u, 0x08u}, + {0x0Bu, 0x04u}, {0x0Du, 0x02u}, {0x0Fu, 0x02u}, - {0x81u, 0x02u}, - {0x86u, 0x01u}, + {0x82u, 0x05u}, {0x87u, 0x10u}, - {0xAAu, 0x20u}, - {0xB1u, 0x40u}, + {0x8Bu, 0x20u}, + {0x93u, 0x20u}, + {0x97u, 0x04u}, + {0x98u, 0x02u}, + {0x9Au, 0x04u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x01u}, + {0xA5u, 0x02u}, + {0xA7u, 0x40u}, + {0xA8u, 0x08u}, + {0xADu, 0x02u}, + {0xAFu, 0x08u}, + {0xB3u, 0x04u}, {0xC2u, 0x0Fu}, - {0xECu, 0x04u}, - {0x8Cu, 0x04u}, - {0x94u, 0x04u}, - {0xAFu, 0x80u}, - {0xB4u, 0x40u}, - {0xB5u, 0x20u}, + {0xE2u, 0x01u}, + {0xEEu, 0x04u}, + {0x86u, 0x04u}, + {0x88u, 0x40u}, + {0x96u, 0x04u}, + {0x9Cu, 0x40u}, + {0x9Eu, 0x08u}, + {0xA2u, 0x20u}, + {0xA3u, 0x20u}, + {0xAFu, 0x81u}, + {0xE2u, 0x40u}, + {0xEAu, 0x40u}, {0xEEu, 0x10u}, - {0x04u, 0x08u}, - {0x52u, 0x80u}, - {0x56u, 0x20u}, - {0x82u, 0x80u}, - {0x8Cu, 0x04u}, - {0x8Eu, 0x20u}, + {0x06u, 0x40u}, + {0x52u, 0x20u}, + {0x57u, 0x20u}, + {0x86u, 0x40u}, + {0x8Au, 0x08u}, + {0x9Eu, 0x08u}, + {0xA2u, 0x20u}, + {0xA3u, 0x20u}, {0xC0u, 0x20u}, {0xD4u, 0x60u}, - {0xE6u, 0x20u}, - {0x88u, 0x04u}, + {0xE0u, 0x10u}, + {0x81u, 0x10u}, + {0x8Fu, 0x40u}, + {0x98u, 0x02u}, + {0x9Du, 0x10u}, + {0xA7u, 0x60u}, + {0xADu, 0x08u}, {0xAFu, 0x01u}, - {0xE2u, 0x04u}, - {0x00u, 0x08u}, - {0xA4u, 0x04u}, + {0xE4u, 0x02u}, + {0x03u, 0x20u}, + {0xA7u, 0x20u}, + {0xB4u, 0x02u}, {0xC0u, 0x08u}, + {0xEAu, 0x08u}, {0x10u, 0x03u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, - {0x1Bu, 0x01u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x01u}, {0x00u, 0xFDu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, @@ -2037,32 +2253,19 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, - {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x8Du, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Du, 0x00u, 0x80u, 0x00u, - 0x00u, 0x0Fu, 0x10u, 0xF0u, 0x62u, 0x30u, 0x08u, 0xC0u, 0x02u, 0x50u, 0x54u, 0xA0u, 0x01u, 0x06u, 0x32u, 0x09u, - 0x8Du, 0x05u, 0x00u, 0x0Au, 0x8Du, 0x03u, 0x00u, 0x0Cu, 0x8Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x00u, 0x90u, - 0x70u, 0x00u, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x80u, 0xFFu, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x50u, 0x40u, - 0x63u, 0x05u, 0x20u, 0x00u, 0x01u, 0xFEu, 0xBDu, 0xCBu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; @@ -2108,6 +2311,7 @@ void cyfitter_cfg(void) CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index 03118c3..7252135 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file provides basic startup and mux configration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 2a57e06..9283e1f 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -391,34 +391,34 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -426,9 +426,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -450,8 +454,8 @@ .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -459,13 +463,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 @@ -1945,15 +1945,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1966,37 +1966,37 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -2952,8 +2952,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2961,78 +2961,81 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB07_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB07_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PANTHER, 18 -.set CYDEV_CHIP_DIE_PSOC4A, 10 -.set CYDEV_CHIP_DIE_PSOC5LP, 17 +.set CYDEV_CHIP_DIE_PSOC4A, 12 +.set CYDEV_CHIP_DIE_PSOC5LP, 19 +.set CYDEV_CHIP_DIE_PSOC5TM, 20 .set CYDEV_CHIP_DIE_TMA4, 2 .set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_FM0P, 4 +.set CYDEV_CHIP_FAMILY_FM3, 5 +.set CYDEV_CHIP_FAMILY_FM4, 6 .set CYDEV_CHIP_FAMILY_PSOC3, 1 .set CYDEV_CHIP_FAMILY_PSOC4, 2 .set CYDEV_CHIP_FAMILY_PSOC5, 3 @@ -3040,22 +3043,30 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 10 -.set CYDEV_CHIP_MEMBER_4C, 15 -.set CYDEV_CHIP_MEMBER_4D, 6 +.set CYDEV_CHIP_MEMBER_4A, 12 +.set CYDEV_CHIP_MEMBER_4C, 18 +.set CYDEV_CHIP_MEMBER_4D, 8 .set CYDEV_CHIP_MEMBER_4E, 4 -.set CYDEV_CHIP_MEMBER_4F, 11 +.set CYDEV_CHIP_MEMBER_4F, 13 .set CYDEV_CHIP_MEMBER_4G, 2 -.set CYDEV_CHIP_MEMBER_4H, 9 -.set CYDEV_CHIP_MEMBER_4I, 14 -.set CYDEV_CHIP_MEMBER_4J, 7 -.set CYDEV_CHIP_MEMBER_4K, 8 -.set CYDEV_CHIP_MEMBER_4L, 13 -.set CYDEV_CHIP_MEMBER_4M, 12 -.set CYDEV_CHIP_MEMBER_4N, 5 +.set CYDEV_CHIP_MEMBER_4H, 11 +.set CYDEV_CHIP_MEMBER_4I, 17 +.set CYDEV_CHIP_MEMBER_4J, 9 +.set CYDEV_CHIP_MEMBER_4K, 10 +.set CYDEV_CHIP_MEMBER_4L, 16 +.set CYDEV_CHIP_MEMBER_4M, 15 +.set CYDEV_CHIP_MEMBER_4N, 6 +.set CYDEV_CHIP_MEMBER_4O, 5 +.set CYDEV_CHIP_MEMBER_4P, 14 +.set CYDEV_CHIP_MEMBER_4Q, 7 .set CYDEV_CHIP_MEMBER_4U, 3 -.set CYDEV_CHIP_MEMBER_5A, 17 -.set CYDEV_CHIP_MEMBER_5B, 16 +.set CYDEV_CHIP_MEMBER_5A, 20 +.set CYDEV_CHIP_MEMBER_5B, 19 +.set CYDEV_CHIP_MEMBER_FM3, 24 +.set CYDEV_CHIP_MEMBER_FM4, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -3064,13 +3075,13 @@ .set CYDEV_CHIP_REV_LEOPARD_ES2, 1 .set CYDEV_CHIP_REV_LEOPARD_ES3, 3 .set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 -.set CYDEV_CHIP_REV_PANTHER_ES0, 0 -.set CYDEV_CHIP_REV_PANTHER_ES1, 1 -.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1 .set CYDEV_CHIP_REV_PSOC4A_ES0, 17 .set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 .set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 .set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 +.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 .set CYDEV_CHIP_REV_TMA4_ES, 17 .set CYDEV_CHIP_REV_TMA4_ES2, 33 .set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 @@ -3096,12 +3107,20 @@ .set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION .set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED .set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 48927dd..d586df1 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -426,9 +426,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -450,8 +454,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -459,13 +463,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 @@ -1945,15 +1945,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1966,37 +1966,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2952,8 +2952,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2961,78 +2961,81 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PANTHER EQU 18 -CYDEV_CHIP_DIE_PSOC4A EQU 10 -CYDEV_CHIP_DIE_PSOC5LP EQU 17 +CYDEV_CHIP_DIE_PSOC4A EQU 12 +CYDEV_CHIP_DIE_PSOC5LP EQU 19 +CYDEV_CHIP_DIE_PSOC5TM EQU 20 CYDEV_CHIP_DIE_TMA4 EQU 2 CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 4 +CYDEV_CHIP_FAMILY_FM3 EQU 5 +CYDEV_CHIP_FAMILY_FM4 EQU 6 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 @@ -3040,22 +3043,30 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 10 -CYDEV_CHIP_MEMBER_4C EQU 15 -CYDEV_CHIP_MEMBER_4D EQU 6 +CYDEV_CHIP_MEMBER_4A EQU 12 +CYDEV_CHIP_MEMBER_4C EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 8 CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 11 +CYDEV_CHIP_MEMBER_4F EQU 13 CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 9 -CYDEV_CHIP_MEMBER_4I EQU 14 -CYDEV_CHIP_MEMBER_4J EQU 7 -CYDEV_CHIP_MEMBER_4K EQU 8 -CYDEV_CHIP_MEMBER_4L EQU 13 -CYDEV_CHIP_MEMBER_4M EQU 12 -CYDEV_CHIP_MEMBER_4N EQU 5 +CYDEV_CHIP_MEMBER_4H EQU 11 +CYDEV_CHIP_MEMBER_4I EQU 17 +CYDEV_CHIP_MEMBER_4J EQU 9 +CYDEV_CHIP_MEMBER_4K EQU 10 +CYDEV_CHIP_MEMBER_4L EQU 16 +CYDEV_CHIP_MEMBER_4M EQU 15 +CYDEV_CHIP_MEMBER_4N EQU 6 +CYDEV_CHIP_MEMBER_4O EQU 5 +CYDEV_CHIP_MEMBER_4P EQU 14 +CYDEV_CHIP_MEMBER_4Q EQU 7 CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 17 -CYDEV_CHIP_MEMBER_5B EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 20 +CYDEV_CHIP_MEMBER_5B EQU 19 +CYDEV_CHIP_MEMBER_FM3 EQU 24 +CYDEV_CHIP_MEMBER_FM4 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3064,13 +3075,13 @@ CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 -CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 -CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 -CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 CYDEV_CHIP_REV_TMA4_ES EQU 17 CYDEV_CHIP_REV_TMA4_ES2 EQU 33 CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 @@ -3096,12 +3107,20 @@ CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index b4a739d..8c27006 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -426,9 +426,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -450,8 +454,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -459,13 +463,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 @@ -1945,15 +1945,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1966,37 +1966,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2952,8 +2952,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2961,78 +2961,81 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PANTHER EQU 18 -CYDEV_CHIP_DIE_PSOC4A EQU 10 -CYDEV_CHIP_DIE_PSOC5LP EQU 17 +CYDEV_CHIP_DIE_PSOC4A EQU 12 +CYDEV_CHIP_DIE_PSOC5LP EQU 19 +CYDEV_CHIP_DIE_PSOC5TM EQU 20 CYDEV_CHIP_DIE_TMA4 EQU 2 CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 4 +CYDEV_CHIP_FAMILY_FM3 EQU 5 +CYDEV_CHIP_FAMILY_FM4 EQU 6 CYDEV_CHIP_FAMILY_PSOC3 EQU 1 CYDEV_CHIP_FAMILY_PSOC4 EQU 2 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 @@ -3040,22 +3043,30 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 10 -CYDEV_CHIP_MEMBER_4C EQU 15 -CYDEV_CHIP_MEMBER_4D EQU 6 +CYDEV_CHIP_MEMBER_4A EQU 12 +CYDEV_CHIP_MEMBER_4C EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 8 CYDEV_CHIP_MEMBER_4E EQU 4 -CYDEV_CHIP_MEMBER_4F EQU 11 +CYDEV_CHIP_MEMBER_4F EQU 13 CYDEV_CHIP_MEMBER_4G EQU 2 -CYDEV_CHIP_MEMBER_4H EQU 9 -CYDEV_CHIP_MEMBER_4I EQU 14 -CYDEV_CHIP_MEMBER_4J EQU 7 -CYDEV_CHIP_MEMBER_4K EQU 8 -CYDEV_CHIP_MEMBER_4L EQU 13 -CYDEV_CHIP_MEMBER_4M EQU 12 -CYDEV_CHIP_MEMBER_4N EQU 5 +CYDEV_CHIP_MEMBER_4H EQU 11 +CYDEV_CHIP_MEMBER_4I EQU 17 +CYDEV_CHIP_MEMBER_4J EQU 9 +CYDEV_CHIP_MEMBER_4K EQU 10 +CYDEV_CHIP_MEMBER_4L EQU 16 +CYDEV_CHIP_MEMBER_4M EQU 15 +CYDEV_CHIP_MEMBER_4N EQU 6 +CYDEV_CHIP_MEMBER_4O EQU 5 +CYDEV_CHIP_MEMBER_4P EQU 14 +CYDEV_CHIP_MEMBER_4Q EQU 7 CYDEV_CHIP_MEMBER_4U EQU 3 -CYDEV_CHIP_MEMBER_5A EQU 17 -CYDEV_CHIP_MEMBER_5B EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 20 +CYDEV_CHIP_MEMBER_5B EQU 19 +CYDEV_CHIP_MEMBER_FM3 EQU 24 +CYDEV_CHIP_MEMBER_FM4 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3064,13 +3075,13 @@ CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 -CYDEV_CHIP_REV_PANTHER_ES0 EQU 0 -CYDEV_CHIP_REV_PANTHER_ES1 EQU 1 -CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1 CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 CYDEV_CHIP_REV_TMA4_ES EQU 17 CYDEV_CHIP_REV_TMA4_ES2 EQU 33 CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 @@ -3096,12 +3107,20 @@ CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 140a2c9..8638ffb 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,7 +19,10 @@ #if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cyloadablemeta"), used)) +#ifndef CY_LOADABLE_META_SECTION +#define CY_LOADABLE_META_SECTION __attribute__ ((__section__(".cyloadablemeta"), used)) +#endif +CY_LOADABLE_META_SECTION #elif defined(__ICCARM__) #pragma location=".cyloadablemeta" #else @@ -28,7 +31,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used)) const uint8 cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, @@ -37,7 +40,10 @@ const uint8 cy_meta_loadable[] = { }; #if defined(__GNUC__) || defined(__ARMCC_VERSION) -__attribute__ ((__section__(".cyconfigecc"), used)) +#ifndef CY_CONFIG_ECC_SECTION +#define CY_CONFIG_ECC_SECTION __attribute__ ((__section__(".cyconfigecc"), used)) +#endif +CY_CONFIG_ECC_SECTION #elif defined(__ICCARM__) #pragma location=".cyconfigecc" #else diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h old mode 100644 new mode 100755 index a1a727b..9f733f7 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h @@ -1,17 +1,16 @@ -/******************************************************************************* -* File Name: cypins.h -* Version 4.20 +/***************************************************************************//** +* \file cypins.h +* \version 5.50 * -* Description: -* This file contains the function prototypes and constants used for a port/pin -* in access and control. +* \brief This file contains the function prototypes and constants used for a +* port/pin in access and control. * -* Note: -* Documentation of the API's in this file is located in the -* System Reference Guide provided with PSoC Creator. +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -71,20 +70,18 @@ /******************************************************************************* * Macro Name: CyPins_ReadPin -******************************************************************************** +****************************************************************************//** * -* Summary: * Reads the current value on the pin (pin state, PS). * -* Parameters: -* pinPC: Port pin configuration register (uint16). +* \param pinPC: Port pin configuration register (uint16). * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * -* Return: +* \return * Pin state * 0: Logic low value * Non-0: Logic high value @@ -95,9 +92,8 @@ /******************************************************************************* * Macro Name: CyPins_SetPin -******************************************************************************** +****************************************************************************//** * -* Summary: * Set the output value for the pin (data register, DR) to a logic high. * * Note that this only has an effect for pins configured as software pins that @@ -110,26 +106,21 @@ * interrupt is disabled or within critical section (all interrupts are * disabled). * -* Parameters: -* pinPC: Port pin configuration register (uint16). +* \param pinPC: Port pin configuration register (uint16). * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * -* Return: -* None -* *******************************************************************************/ #define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) /******************************************************************************* * Macro Name: CyPins_ClearPin -******************************************************************************** +****************************************************************************//** * -* Summary: * This macro sets the state of the specified pin to 0. * * The macro operation is not atomic. It is not guaranteed that shared register @@ -139,26 +130,21 @@ * interrupt is disabled or within critical section (all interrupts are * disabled). * -* Parameters: -* pinPC: address of a Pin Configuration register. +* \param pinPC: address of a Pin Configuration register. * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * -* Return: -* None -* *******************************************************************************/ #define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) /******************************************************************************* * Macro Name: CyPins_SetPinDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: * Sets the drive mode for the pin (DM). * * The macro operation is not atomic. It is not guaranteed that shared register @@ -168,15 +154,14 @@ * interrupt is disabled or within critical section (all interrupts are * disabled). * -* Parameters: -* pinPC: Port pin configuration register (uint16) +* \param pinPC: Port pin configuration register (uint16) * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * -* mode: Desired drive mode +* \param mode: Desired drive mode * * Define Source * PIN_DM_ALG_HIZ Analog HiZ @@ -188,9 +173,6 @@ * PIN_DM_STRONG Strong CMOS Output * PIN_DM_RES_UPDWN Resistive pull up/down * -* Return: -* None -* *******************************************************************************/ #define CyPins_SetPinDriveMode(pinPC, mode) \ ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ @@ -199,21 +181,19 @@ /******************************************************************************* * Macro Name: CyPins_ReadPinDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: * Reads the drive mode for the pin (DM). * -* Parameters: -* pinPC: Port pin configuration register (uint16) +* \param pinPC: Port pin configuration register (uint16) * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * * -* Return: +* \return * mode: The current drive mode for the pin * * Define Source @@ -232,9 +212,8 @@ /******************************************************************************* * Macro Name: CyPins_FastSlew -******************************************************************************** +****************************************************************************//** * -* Summary: * Set the slew rate for the pin to fast the edge rate. * Note that this only applies for pins in strong output drive modes, * not to resistive drive modes. @@ -246,27 +225,22 @@ * interrupt is disabled or within critical section (all interrupts are * disabled). * -* Parameters: -* pinPC: address of a Pin Configuration register. +* \param pinPC: address of a Pin Configuration register. * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * * -* Return: -* None -* *******************************************************************************/ #define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) /******************************************************************************* * Macro Name: CyPins_SlowSlew -******************************************************************************** +****************************************************************************//** * -* Summary: * Set the slew rate for the pin to slow the edge rate. * Note that this only applies for pins in strong output drive modes, * not to resistive drive modes. @@ -278,17 +252,13 @@ * interrupt is disabled or within critical section (all interrupts are * disabled). * -* Parameters: -* pinPC: address of a Pin Configuration register. +* \param pinPC: address of a Pin Configuration register. * #defines for each pin on a chip are provided in the cydevice_trm.h file -* in the form: +* \param in the form: * CYREG_PRTx_PCy * * where x is a port number 0 - 15 and y is a pin number 0 - 7 * -* Return: -* None -* *******************************************************************************/ #define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h old mode 100644 new mode 100755 index d48f29a..cbaebbc --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h @@ -1,23 +1,22 @@ -/******************************************************************************* -* FILENAME: cytypes.h -* Version 4.20 +/***************************************************************************//** +* \file cytypes.h +* \version 5.50 * -* Description: -* CyTypes provides register access macros and approved types for use in -* firmware. +* \brief CyTypes provides register access macros and approved types for use in +* firmware. * -* Note: -* Due to endiannesses of the hardware and some compilers, the register -* access macros for big endian compilers use some library calls to arrange -* data the correct way. +* \note Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. * -* Register Access macros and functions perform their operations on an -* input of the type pointer to void. The arguments passed to it should be -* pointers to the type associated with the register size. -* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -78,6 +77,47 @@ #define CY_PSOC4_4200BL (0u != 0u) #endif /* CYDEV_CHIP_MEMBER_4F */ +#ifdef CYDEV_CHIP_MEMBER_4M + #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) + #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) +#else + #define CY_PSOC4_4100M (0u != 0u) + #define CY_PSOC4_4200M (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4M */ + +#ifdef CYDEV_CHIP_MEMBER_4H + #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H) +#else + #define CY_PSOC4_4200D (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4H */ + +#ifdef CYDEV_CHIP_MEMBER_4L + #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L) +#else + #define CY_PSOC4_4200L (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4L */ + +#ifdef CYDEV_CHIP_MEMBER_4U + #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U) +#else + #define CY_PSOC4_4000U (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4U */ + +#ifdef CYDEV_CHIP_MEMBER_4J + #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J) +#else + #define CY_PSOC4_4000S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4J */ + +#ifdef CYDEV_CHIP_MEMBER_4K + #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K) +#else + #define CY_PSOC4_4100S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4K */ + + +#define CY_IP_HOBTO_DEVICE (!(0 == 1)) + /******************************************************************************* * IP blocks @@ -85,63 +125,259 @@ #if (CY_PSOC4) /* Using SRSSv2 or SRS-Lite */ - #if (CY_PSOC4_4100 || CY_PSOC4_4200) - #define CY_IP_SRSSV2 (0u == 0u) + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_SRSSV2 (0 != 0) #define CY_IP_SRSSLT (!CY_IP_SRSSV2) #else - #define CY_IP_SRSSV2 (0u != 0u) + #define CY_IP_SRSSV2 (0 == 0) #define CY_IP_SRSSLT (!CY_IP_SRSSV2) - #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + #endif /* (CY_IP_HOBTO_DEVICE) */ - #if (CY_PSOC4_4100 || CY_PSOC4_4200) - #define CY_IP_CPUSSV2 (0u != 0u) - #define CY_IP_CPUSS (0u == 0u) + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSSV3 (0 == 1) + #define CY_IP_CPUSSV2 (0 == 1) + #define CY_IP_CPUSS (0 == 1) #else - #define CY_IP_CPUSSV2 (0u != 0u) - #define CY_IP_CPUSS (!CY_IP_CPUSSV2) - #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + #define CY_IP_CPUSSV3 (0 != 0) + #define CY_IP_CPUSSV2 (0 != 0) + #define CY_IP_CPUSS (0 == 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_CPUSS_CM0 (0 == 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_CPUSS_CM0 (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0) + #else + #define CY_IP_CPUSS_CM0 (0 == 0) + #define CY_IP_CPUSS_CM0PLUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash memory present or not (1=Flash present, 0=Flash not present) */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0) + #else + #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + /* Product uses FLASH-Lite or regular FLASH */ - #if (CY_PSOC4_4100 || CY_PSOC4_4200) - #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */ - #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #endif /* (CY_IP_CPUSSV2) */ #else - #define CY_IP_FMLT (-1u != 0u) - #define CY_IP_FM (!CY_IP_FMLT) - #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */ + #define CY_IP_FS (0 != 0) /* FS */ + #define CY_IP_FSLT (0 != 0) /* FSLT */ + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Enable simultaneous execution/programming in multi-macro devices */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_MACROS (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_MACROS (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_HOBTO_DEVICE) */ /* Number of interrupt request inputs to CM0 */ - #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_INT_NR (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_INT_NR (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else #define CY_IP_INT_NR (32u) - #else - #define CY_IP_INT_NR (-1u) - #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ - - /* Number of Flash macros used in the device (0, 1 or 2) */ - #if (CY_PSOC4_4100 || CY_PSOC4_4200) - #define CY_IP_FLASH_MACROS (1u) - #else - #define CY_IP_FLASH_MACROS (-1u) - #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + #endif /* (CY_IP_HOBTO_DEVICE) */ - /* Number of Flash macros used in the device (0, 1 or 2) */ - #if (CY_PSOC4_4100 || CY_PSOC4_4200) - #define CY_IP_BLESS (0u != 0u) + /* Presence of the BLESS IP block */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_BLESS (0 != 0) #else - #define CY_IP_BLESS (0u != 0u) - #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + #define CY_IP_BLESS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_USBDEV (0 != 0) + #else + #define CY_IP_USBDEV (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /*************************************************************************** + * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use + * the 36MHz Oscillator for Flash operation. Instead, flash write function + * ensures that the charge pump clock and the higher frequency clock (HFCLK) + * are set to the IMO at 48MHz prior to writing the flash. + ***************************************************************************/ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ /* Watch Crystal Oscillator (WCO) is present (32kHz) */ - #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) - #define CY_IP_WCO (0u != 0u) - #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION) - #define CY_IP_WCO (0u == 0u) - #elif (CY_IP_SRSSV2) - #define CY_IP_WCO (-1u) + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_WCO_BLESS (0 == 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 == 1) + #define CY_IP_WCO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ #else - #define CY_IP_WCO (0u != 0u) - #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */ + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + + + /* PLL is present */ + #if (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2) + #define CY_IP_PLL ((-1 != 0) || \ + (-1 != 0)) + + #define CY_IP_PLL_NR (-1u + \ + -1u) + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2) */ + + + /* External Crystal Oscillator is present (high frequency) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_ECO_BLESS (0 == 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2) + + + /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash Macro 0 has extra rows */ + #if (CY_IP_HOBTO_DEVICE) + #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0 + #define CY_SFLASH_XTRA_ROWS (0 == 0) + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */ + + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_USBDEV) + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0) + #endif /* (CY_IP_USBDEV) */ + + + #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0) + #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */ + + + /* DW/DMA Controller present (0=No, 1=Yes) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_DMAC_PRESENT (-1 == 1) + #else + #define CY_IP_DMAC_PRESENT (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_DMAC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_PASS (0 == 1) + #else + #define CY_IP_PASS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + + /* Number of external slave ports on System Interconnect */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SL_NR (-1) + #else + #define CY_IP_SL_NR (-1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + +#else + + #if (CY_PSOC3) + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #else /* PSoC 5LP */ + #define CY_SYSTICK_LFCLK_SOURCE (0 == 0) + #endif /* (CY_PSOC3) */ #endif /* (CY_PSOC4) */ @@ -152,7 +388,12 @@ * (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) *******************************************************************************/ #define CY_BOOT_4_20 (420u) -#define CY_BOOT_VERSION (CY_BOOT_4_20) +#define CY_BOOT_5_0 (500u) +#define CY_BOOT_5_10 (510u) +#define CY_BOOT_5_20 (520u) +#define CY_BOOT_5_30 (530u) +#define CY_BOOT_5_40 (540u) +#define CY_BOOT_VERSION (CY_BOOT_5_40) /******************************************************************************* @@ -355,49 +596,278 @@ typedef volatile uint32 CYXDATA reg32; #endif /* (CY_PSOC3) */ -/******************************************************************************* -* Register Access -*******************************************************************************/ +#define CY_M_PI (3.14159265358979323846264338327) + + +/** +* \addtogroup group_register_access +A library of macros provides read and write access to the registers of the device. These macros are used with the +defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made +using these macros and not the functions that are used to implement the macros. This allows for device independent code +generation. + +The PSoC 4 processor architecture use little endian ordering. + +SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, +the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this +little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider +the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, +as well as function calls that are passed an array of bytes in memory. + +The PSoC 4 requires these accesses to be aligned to the width of the transaction. + +The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might +ignore the transfer and Hard Fault exception will be generated. + +*/ + +/** @} group_register_access */ + + +/** +* \addtogroup group_register_access_macros Register Access +* \ingroup group_register_access +* @{ +*/ + #if(CY_PSOC3) + /******************************************************************************* + * Macro Name: CY_GET_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) /******************************************************************************* - * KEIL for the 8051 is a big endian compiler This causes problems as the on chip - * registers are little endian. Byte swapping for two and four byte registers is - * implemented in the functions below. This will require conditional compilation - * of function prototypes in the code. + * Macro Name: CY_SET_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * + * \param reg Register address. + * \param value Value to write. + * *******************************************************************************/ - - /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */ - - #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + /******************************************************************************* + * Macro Name: CY_GET_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + /******************************************************************************* + * Macro Name: CY_GET_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + /******************************************************************************* + * Macro Name: CY_GET_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) - /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * Identical to \ref CY_GET_REG8 for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * Identical to \ref CY_SET_REG8 for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) #else - /* 8, 16, 24 and 32-bit register access macros */ #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) @@ -416,7 +886,6 @@ typedef volatile uint32 CYXDATA reg32; #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) - /* To allow code to be 8051-ARM agnostic. */ #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) @@ -431,8 +900,387 @@ typedef volatile uint32 CYXDATA reg32; #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) #endif /* (CY_PSOC3) */ +/** @} group_register_access_macros */ +/** +* \addtogroup group_register_access_bits Bit Manipulation +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC4) + + /******************************************************************************* + * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName) + ****************************************************************************//** + * + * Returns the bit field mask for the specified register size and bit field + * name. + * + * \param regSize Size of the register in bits. + * \param bitFieldName Fully qualified name of the bit field. The biFieldName + * is automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * \return Returns the bit mask. + * + *******************************************************************************/ + #define CY_GET_FIELD_MASK(regSize, bitFieldName) \ + ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\ + ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET) + + + /******************************************************************************* + * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register will remain uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on 32-bit and 16-bit width registers will generate a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG8_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 8-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers, generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG8((registerName), \ + ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \ + (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \ + (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hardfault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG16_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 16-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerNam The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG16((registerName), \ + ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \ + (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\ + (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The Fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields, please, refer to + * a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, otherwise. + * The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG32_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 32-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG32((registerName), \ + ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \ + (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \ + (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_FIELD(regValue, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_FIELD(regValue, bitFieldName) \ + (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value within a given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads and \ref CY_SET_REG32 for atomic writes. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to the respective PSoC family register TRM. + * + *******************************************************************************/ + #define CY_SET_FIELD(regValue, bitFieldName, value) \ + ((regValue) = \ + ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \ + ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET))) + +#endif /* (CY_PSOC4) */ + +/** @} group_register_access_bits */ + /******************************************************************************* * Data manipulation defines @@ -448,10 +1296,10 @@ typedef volatile uint32 CYXDATA reg32; /* Swap the byte ordering of 32 bit value */ #define CYSWAP_ENDIAN32(x) \ - ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) /* Swap the byte ordering of 16 bit value */ -#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8))) +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu))) /******************************************************************************* @@ -504,7 +1352,7 @@ typedef volatile uint32 CYXDATA reg32; /******************************************************************************* -* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +* The following code is OBSOLETE and must not be used starting from cy_boot 5.10 * * If the obsoleted macro definitions intended for use in the application use the * following scheme, redefine your own versions of these definitions: @@ -517,6 +1365,12 @@ typedef volatile uint32 CYXDATA reg32; * used in the application and their modification might lead to unexpected * consequences. *******************************************************************************/ +#define CY_IP_S8FS CY_IP_FS + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ #define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) #define CY_UDB_V1 (!CY_UDB_V0) #define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c old mode 100644 new mode 100755 index 4d2b71a..7f9c5f9 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c @@ -1,12 +1,12 @@ -/******************************************************************************* -* FILENAME: cyutils.c -* Version 4.20 +/***************************************************************************//** +* \file cyutils.c +* \version 5.50 * -* Description: -* CyUtils provides a function to handle 24-bit value writes. +* \brief Provides a function to handle 24-bit value writes. * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -18,17 +18,12 @@ /*************************************************************************** * Function Name: CySetReg24 - **************************************************************************** + ************************************************************************//** * - * Summary: - * Writes a 24-bit value to the specified register. + * Writes a 24-bit value to the specified register. * - * Parameters: - * addr : the address where data must be written. - * value: the data that must be written. - * - * Return: - * None + * \param add The address where data must be written. + * \param value The data that must be written. * * Reentrant: * No @@ -50,16 +45,11 @@ /*************************************************************************** * Function Name: CyGetReg24 - **************************************************************************** + ************************************************************************//** * - * Summary: * Reads the 24-bit value from the specified register. * - * Parameters: - * addr : the address where data must be read. - * - * Return: - * None + * \param addr : the address where data must be read. * * Reentrant: * No diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 3e44573..83e11bd 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 3.3 +* PSoC Creator 4.0 Update 1 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -53,6 +53,8 @@ #include "USBFS_hid.h" #include "USBFS_midi.h" #include "USBFS_pvt.h" +#include "USBFS_cydmac.h" +#include "USBFS_msc.h" #include "Bootloadable_1.h" #include "SCSI_Out_Bits.h" #include "SCSI_Out_Ctl.h" @@ -76,7 +78,6 @@ #include "USBFS_Dp_aliases.h" #include "USBFS_Dp.h" #include "core_cm3_psoc5.h" -#include "core_cm3.h" #include "CyDmac.h" #include "CyFlash.h" #include "CyLib.h" @@ -84,8 +85,6 @@ #include "cyPm.h" #include "CySpc.h" #include "cytypes.h" -#include "core_cmFunc.h" -#include "core_cmInstr.h" /*[]*/ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c old mode 100644 new mode 100755 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index 555f967..7c2a108 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -16,57 +16,57 @@