From 561f2903e943cffde438affd15d48fe2192854a1 Mon Sep 17 00:00:00 2001 From: Michael McMaster Date: Wed, 22 May 2019 20:06:49 +1000 Subject: [PATCH] Update IDE files --- software/SCSI2SD/src/config.c | 2 +- .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 4 +- .../PSoC5/cydeviceiar_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 2142 +++++------ .../Generated_Source/PSoC5/cyfitter_cfg.c | 3249 +++++++++-------- .../Generated_Source/PSoC5/cyfitter_cfg.h | 4 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 2140 +++++------ .../Generated_Source/PSoC5/cyfitteriar.inc | 2140 +++++------ .../Generated_Source/PSoC5/cyfitterrv.inc | 2140 +++++------ .../Generated_Source/PSoC5/cymetadata.c | 4 +- .../Generated_Source/PSoC5/project.h | 5 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx | 207 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr | 9 +- .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 251892 -> 259636 bytes .../SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj | 30 +- software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd | 632 ++-- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 252646 -> 253892 bytes .../Generated_Source/PSoC5/cydevice.h | 4 +- .../Generated_Source/PSoC5/cydevice_trm.h | 4 +- .../Generated_Source/PSoC5/cydevicegnu.inc | 4 +- .../PSoC5/cydevicegnu_trm.inc | 4 +- .../Generated_Source/PSoC5/cydeviceiar.inc | 4 +- .../PSoC5/cydeviceiar_trm.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv.inc | 4 +- .../Generated_Source/PSoC5/cydevicerv_trm.inc | 4 +- .../Generated_Source/PSoC5/cyfitter.h | 2020 +++++----- .../Generated_Source/PSoC5/cyfitter_cfg.c | 13 +- .../Generated_Source/PSoC5/cyfitter_cfg.h | 4 +- .../Generated_Source/PSoC5/cyfittergnu.inc | 2018 +++++----- .../Generated_Source/PSoC5/cyfitteriar.inc | 2018 +++++----- .../Generated_Source/PSoC5/cyfitterrv.inc | 2018 +++++----- .../Generated_Source/PSoC5/cymetadata.c | 4 +- .../Generated_Source/PSoC5/project.h | 5 +- .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cycdx | 25 +- .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cydwr | 9 +- .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyfit | Bin 255983 -> 257227 bytes .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.cyprj | 30 +- .../SCSI2SD/v5.1/SCSI2SD.cydsn/SCSI2SD.svd | 32 +- .../SCSI2SD.cydsn/TopDesign/TopDesign.cysch | Bin 319674 -> 321028 bytes 45 files changed, 10652 insertions(+), 10312 deletions(-) diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index ce84013..f1367d9 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -31,7 +31,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0481; +static const uint16_t FIRMWARE_VERSION = 0x0482; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index 160bd6a..87d9c0b 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index bff26ed..9ac643d 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index 5db8be3..0a6e4e6 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index e0ed758..529602b 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 6b49c48..33f3ab7 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index c7c07d0..e128fd3 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index e9f2b78..dcd9ce1 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index 4a32cab..56680bb 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index a11569b..3154230 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,68 +19,6 @@ #include "cydevice.h" #include "cydevice_trm.h" -/* Debug_Timer_Interrupt */ -#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define Debug_Timer_Interrupt__INTC_MASK 0x01u -#define Debug_Timer_Interrupt__INTC_NUMBER 0u -#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u -#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 -#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 -#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 -#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 -#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 -#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 -#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 -#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 -#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 -#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 -#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 -#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u -#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 -#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u -#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 -#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 -#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 - -/* EXTLED */ -#define EXTLED__0__INTTYPE CYREG_PICU0_INTTYPE0 -#define EXTLED__0__MASK 0x01u -#define EXTLED__0__PC CYREG_PRT0_PC0 -#define EXTLED__0__PORT 0u -#define EXTLED__0__SHIFT 0u -#define EXTLED__AG CYREG_PRT0_AG -#define EXTLED__AMUX CYREG_PRT0_AMUX -#define EXTLED__BIE CYREG_PRT0_BIE -#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK -#define EXTLED__BYP CYREG_PRT0_BYP -#define EXTLED__CTL CYREG_PRT0_CTL -#define EXTLED__DM0 CYREG_PRT0_DM0 -#define EXTLED__DM1 CYREG_PRT0_DM1 -#define EXTLED__DM2 CYREG_PRT0_DM2 -#define EXTLED__DR CYREG_PRT0_DR -#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS -#define EXTLED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE -#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN -#define EXTLED__MASK 0x01u -#define EXTLED__PORT 0u -#define EXTLED__PRT CYREG_PRT0_PRT -#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define EXTLED__PS CYREG_PRT0_PS -#define EXTLED__SHIFT 0u -#define EXTLED__SLW CYREG_PRT0_SLW - /* LED1 */ #define LED1__0__INTTYPE CYREG_PICU0_INTTYPE1 #define LED1__0__MASK 0x02u @@ -115,82 +53,478 @@ #define LED1__SHIFT 1u #define LED1__SLW CYREG_PRT0_SLW -/* SCSI_CLK */ -#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 -#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u -#define SCSI_CLK__INDEX 0x01u -#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SCSI_CLK__PM_ACT_MSK 0x02u -#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SCSI_CLK__PM_STBY_MSK 0x02u +/* SD_CD */ +#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE5 +#define SD_CD__0__MASK 0x20u +#define SD_CD__0__PC CYREG_PRT3_PC5 +#define SD_CD__0__PORT 3u +#define SD_CD__0__SHIFT 5u +#define SD_CD__AG CYREG_PRT3_AG +#define SD_CD__AMUX CYREG_PRT3_AMUX +#define SD_CD__BIE CYREG_PRT3_BIE +#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CD__BYP CYREG_PRT3_BYP +#define SD_CD__CTL CYREG_PRT3_CTL +#define SD_CD__DM0 CYREG_PRT3_DM0 +#define SD_CD__DM1 CYREG_PRT3_DM1 +#define SD_CD__DM2 CYREG_PRT3_DM2 +#define SD_CD__DR CYREG_PRT3_DR +#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CD__MASK 0x20u +#define SD_CD__PORT 3u +#define SD_CD__PRT CYREG_PRT3_PRT +#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CD__PS CYREG_PRT3_PS +#define SD_CD__SHIFT 5u +#define SD_CD__SLW CYREG_PRT3_SLW -/* SCSI_CTL_PHASE */ -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK +/* SD_CS */ +#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SD_CS__0__MASK 0x10u +#define SD_CS__0__PC CYREG_PRT3_PC4 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 4u +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x10u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 4u +#define SD_CS__SLW CYREG_PRT3_SLW -/* SCSI_Filtered */ -#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u -#define SCSI_Filtered_sts_sts_reg__0__POS 0 -#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u -#define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST -#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u -#define SCSI_Filtered_sts_sts_reg__2__POS 2 -#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u -#define SCSI_Filtered_sts_sts_reg__3__POS 3 -#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u -#define SCSI_Filtered_sts_sts_reg__4__POS 4 -#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_PRIOR_NUM 7u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_PRIOR_NUM 7u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 -/* SCSI_Glitch_Ctl */ -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK +/* EXTLED */ +#define EXTLED__0__INTTYPE CYREG_PICU0_INTTYPE0 +#define EXTLED__0__MASK 0x01u +#define EXTLED__0__PC CYREG_PRT0_PC0 +#define EXTLED__0__PORT 0u +#define EXTLED__0__SHIFT 0u +#define EXTLED__AG CYREG_PRT0_AG +#define EXTLED__AMUX CYREG_PRT0_AMUX +#define EXTLED__BIE CYREG_PRT0_BIE +#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK +#define EXTLED__BYP CYREG_PRT0_BYP +#define EXTLED__CTL CYREG_PRT0_CTL +#define EXTLED__DM0 CYREG_PRT0_DM0 +#define EXTLED__DM1 CYREG_PRT0_DM1 +#define EXTLED__DM2 CYREG_PRT0_DM2 +#define EXTLED__DR CYREG_PRT0_DR +#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS +#define EXTLED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN +#define EXTLED__MASK 0x01u +#define EXTLED__PORT 0u +#define EXTLED__PRT CYREG_PRT0_PRT +#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define EXTLED__PS CYREG_PRT0_PS +#define EXTLED__SHIFT 0u +#define EXTLED__SLW CYREG_PRT0_SLW + +/* SDCard */ +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST + +/* SD_SCK */ +#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_SCK__0__MASK 0x04u +#define SD_SCK__0__PC CYREG_PRT3_PC2 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 2u +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x04u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 2u +#define SD_SCK__SLW CYREG_PRT3_SLW /* SCSI_In */ #define SCSI_In__0__AG CYREG_PRT2_AG @@ -918,287 +1252,84 @@ #define SCSI_In_DBx__DB7__SHIFT 4u #define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW -/* SCSI_Noise */ -#define SCSI_Noise__0__AG CYREG_PRT2_AG -#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX -#define SCSI_Noise__0__BIE CYREG_PRT2_BIE -#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK -#define SCSI_Noise__0__BYP CYREG_PRT2_BYP -#define SCSI_Noise__0__CTL CYREG_PRT2_CTL -#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0 -#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1 -#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2 -#define SCSI_Noise__0__DR CYREG_PRT2_DR -#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS -#define SCSI_Noise__0__INTTYPE CYREG_PICU2_INTTYPE0 -#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG -#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN -#define SCSI_Noise__0__MASK 0x01u -#define SCSI_Noise__0__PC CYREG_PRT2_PC0 -#define SCSI_Noise__0__PORT 2u -#define SCSI_Noise__0__PRT CYREG_PRT2_PRT -#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL -#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN -#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 -#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 -#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 -#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 -#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT -#define SCSI_Noise__0__PS CYREG_PRT2_PS -#define SCSI_Noise__0__SHIFT 0u -#define SCSI_Noise__0__SLW CYREG_PRT2_SLW -#define SCSI_Noise__1__AG CYREG_PRT6_AG -#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__1__BIE CYREG_PRT6_BIE -#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__1__BYP CYREG_PRT6_BYP -#define SCSI_Noise__1__CTL CYREG_PRT6_CTL -#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__1__DR CYREG_PRT6_DR -#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE3 -#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__1__MASK 0x08u -#define SCSI_Noise__1__PC CYREG_PRT6_PC3 -#define SCSI_Noise__1__PORT 6u -#define SCSI_Noise__1__PRT CYREG_PRT6_PRT -#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__1__PS CYREG_PRT6_PS -#define SCSI_Noise__1__SHIFT 3u -#define SCSI_Noise__1__SLW CYREG_PRT6_SLW -#define SCSI_Noise__2__AG CYREG_PRT4_AG -#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__2__BIE CYREG_PRT4_BIE -#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__2__BYP CYREG_PRT4_BYP -#define SCSI_Noise__2__CTL CYREG_PRT4_CTL -#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__2__DR CYREG_PRT4_DR -#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__2__INTTYPE CYREG_PICU4_INTTYPE3 -#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__2__MASK 0x08u -#define SCSI_Noise__2__PC CYREG_PRT4_PC3 -#define SCSI_Noise__2__PORT 4u -#define SCSI_Noise__2__PRT CYREG_PRT4_PRT -#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__2__PS CYREG_PRT4_PS -#define SCSI_Noise__2__SHIFT 3u -#define SCSI_Noise__2__SLW CYREG_PRT4_SLW -#define SCSI_Noise__3__AG CYREG_PRT4_AG -#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__3__BIE CYREG_PRT4_BIE -#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__3__BYP CYREG_PRT4_BYP -#define SCSI_Noise__3__CTL CYREG_PRT4_CTL -#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__3__DR CYREG_PRT4_DR -#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__3__INTTYPE CYREG_PICU4_INTTYPE7 -#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__3__MASK 0x80u -#define SCSI_Noise__3__PC CYREG_PRT4_PC7 -#define SCSI_Noise__3__PORT 4u -#define SCSI_Noise__3__PRT CYREG_PRT4_PRT -#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__3__PS CYREG_PRT4_PS -#define SCSI_Noise__3__SHIFT 7u -#define SCSI_Noise__3__SLW CYREG_PRT4_SLW -#define SCSI_Noise__4__AG CYREG_PRT6_AG -#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__4__BIE CYREG_PRT6_BIE -#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__4__BYP CYREG_PRT6_BYP -#define SCSI_Noise__4__CTL CYREG_PRT6_CTL -#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__4__DR CYREG_PRT6_DR -#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE2 -#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__4__MASK 0x04u -#define SCSI_Noise__4__PC CYREG_PRT6_PC2 -#define SCSI_Noise__4__PORT 6u -#define SCSI_Noise__4__PRT CYREG_PRT6_PRT -#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__4__PS CYREG_PRT6_PS -#define SCSI_Noise__4__SHIFT 2u -#define SCSI_Noise__4__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ACK__AG CYREG_PRT6_AG -#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE -#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP -#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL -#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__ACK__DR CYREG_PRT6_DR -#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE2 -#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__ACK__MASK 0x04u -#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2 -#define SCSI_Noise__ACK__PORT 6u -#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT -#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__ACK__PS CYREG_PRT6_PS -#define SCSI_Noise__ACK__SHIFT 2u -#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW -#define SCSI_Noise__ATN__AG CYREG_PRT2_AG -#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX -#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE -#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK -#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP -#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL -#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0 -#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1 -#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2 -#define SCSI_Noise__ATN__DR CYREG_PRT2_DR -#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS -#define SCSI_Noise__ATN__INTTYPE CYREG_PICU2_INTTYPE0 -#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG -#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN -#define SCSI_Noise__ATN__MASK 0x01u -#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0 -#define SCSI_Noise__ATN__PORT 2u -#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT -#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL -#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN -#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 -#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 -#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT -#define SCSI_Noise__ATN__PS CYREG_PRT2_PS -#define SCSI_Noise__ATN__SHIFT 0u -#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW -#define SCSI_Noise__BSY__AG CYREG_PRT6_AG -#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX -#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE -#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP -#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL -#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 -#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 -#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 -#define SCSI_Noise__BSY__DR CYREG_PRT6_DR -#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE3 -#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_Noise__BSY__MASK 0x08u -#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3 -#define SCSI_Noise__BSY__PORT 6u -#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT -#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_Noise__BSY__PS CYREG_PRT6_PS -#define SCSI_Noise__BSY__SHIFT 3u -#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW -#define SCSI_Noise__RST__AG CYREG_PRT4_AG -#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE -#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP -#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL -#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__RST__DR CYREG_PRT4_DR -#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__RST__INTTYPE CYREG_PICU4_INTTYPE7 -#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__RST__MASK 0x80u -#define SCSI_Noise__RST__PC CYREG_PRT4_PC7 -#define SCSI_Noise__RST__PORT 4u -#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT -#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__RST__PS CYREG_PRT4_PS -#define SCSI_Noise__RST__SHIFT 7u -#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW -#define SCSI_Noise__SEL__AG CYREG_PRT4_AG -#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX -#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE -#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP -#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL -#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0 -#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1 -#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2 -#define SCSI_Noise__SEL__DR CYREG_PRT4_DR -#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_Noise__SEL__INTTYPE CYREG_PICU4_INTTYPE3 -#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_Noise__SEL__MASK 0x08u -#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3 -#define SCSI_Noise__SEL__PORT 4u -#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT -#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_Noise__SEL__PS CYREG_PRT4_PS -#define SCSI_Noise__SEL__SHIFT 3u -#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW +/* SD_MISO */ +#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 +#define SD_MISO__0__MASK 0x02u +#define SD_MISO__0__PC CYREG_PRT3_PC1 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 1u +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x02u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 1u +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_MOSI__0__MASK 0x08u +#define SD_MOSI__0__PC CYREG_PRT3_PC3 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 3u +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x08u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 3u +#define SD_MOSI__SLW CYREG_PRT3_SLW + +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT15_AG @@ -1765,15 +1896,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1786,35 +1917,35 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK #define SCSI_Out_DBx__0__AG CYREG_PRT5_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE @@ -2264,296 +2395,6 @@ #define SCSI_Out_DBx__DB7__SHIFT 2u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW -/* SCSI_Parity_Error */ -#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST -#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST - -/* SCSI_RST_ISR */ -#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x02u -#define SCSI_RST_ISR__INTC_NUMBER 1u -#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 -#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_RX_DMA */ -#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u -#define SCSI_RX_DMA__NUMBEROF_TDS 0u -#define SCSI_RX_DMA__PRIORITY 2u -#define SCSI_RX_DMA__TERMIN_EN 0u -#define SCSI_RX_DMA__TERMIN_SEL 0u -#define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u -#define SCSI_RX_DMA__TERMOUT1_EN 0u -#define SCSI_RX_DMA__TERMOUT1_SEL 0u -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u -#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 -#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u -#define SCSI_TX_DMA__NUMBEROF_TDS 0u -#define SCSI_TX_DMA__PRIORITY 2u -#define SCSI_TX_DMA__TERMIN_EN 0u -#define SCSI_TX_DMA__TERMIN_SEL 0u -#define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u -#define SCSI_TX_DMA__TERMOUT1_EN 0u -#define SCSI_TX_DMA__TERMOUT1_SEL 0u -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - -/* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_RxStsReg__4__POS 4 -#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u -#define SDCard_BSPIM_RxStsReg__5__POS 5 -#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u -#define SDCard_BSPIM_RxStsReg__6__POS 6 -#define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u -#define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u -#define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST -#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u -#define SDCard_BSPIM_TxStsReg__2__POS 2 -#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u -#define SDCard_BSPIM_TxStsReg__3__POS 3 -#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u -#define SDCard_BSPIM_TxStsReg__4__POS 4 -#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST - -/* SD_CD */ -#define SD_CD__0__INTTYPE CYREG_PICU3_INTTYPE5 -#define SD_CD__0__MASK 0x20u -#define SD_CD__0__PC CYREG_PRT3_PC5 -#define SD_CD__0__PORT 3u -#define SD_CD__0__SHIFT 5u -#define SD_CD__AG CYREG_PRT3_AG -#define SD_CD__AMUX CYREG_PRT3_AMUX -#define SD_CD__BIE CYREG_PRT3_BIE -#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CD__BYP CYREG_PRT3_BYP -#define SD_CD__CTL CYREG_PRT3_CTL -#define SD_CD__DM0 CYREG_PRT3_DM0 -#define SD_CD__DM1 CYREG_PRT3_DM1 -#define SD_CD__DM2 CYREG_PRT3_DM2 -#define SD_CD__DR CYREG_PRT3_DR -#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CD__MASK 0x20u -#define SD_CD__PORT 3u -#define SD_CD__PRT CYREG_PRT3_PRT -#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CD__PS CYREG_PRT3_PS -#define SD_CD__SHIFT 5u -#define SD_CD__SLW CYREG_PRT3_SLW - -/* SD_CS */ -#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 -#define SD_CS__0__MASK 0x10u -#define SD_CS__0__PC CYREG_PRT3_PC4 -#define SD_CS__0__PORT 3u -#define SD_CS__0__SHIFT 4u -#define SD_CS__AG CYREG_PRT3_AG -#define SD_CS__AMUX CYREG_PRT3_AMUX -#define SD_CS__BIE CYREG_PRT3_BIE -#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_CS__BYP CYREG_PRT3_BYP -#define SD_CS__CTL CYREG_PRT3_CTL -#define SD_CS__DM0 CYREG_PRT3_DM0 -#define SD_CS__DM1 CYREG_PRT3_DM1 -#define SD_CS__DM2 CYREG_PRT3_DM2 -#define SD_CS__DR CYREG_PRT3_DR -#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS -#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN -#define SD_CS__MASK 0x10u -#define SD_CS__PORT 3u -#define SD_CS__PRT CYREG_PRT3_PRT -#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_CS__PS CYREG_PRT3_PS -#define SD_CS__SHIFT 4u -#define SD_CS__SLW CYREG_PRT3_SLW - -/* SD_Data_Clk */ -#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 -#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 -#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 -#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Data_Clk__INDEX 0x00u -#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Data_Clk__PM_ACT_MSK 0x01u -#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Data_Clk__PM_STBY_MSK 0x01u - -/* SD_MISO */ -#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE1 -#define SD_MISO__0__MASK 0x02u -#define SD_MISO__0__PC CYREG_PRT3_PC1 -#define SD_MISO__0__PORT 3u -#define SD_MISO__0__SHIFT 1u -#define SD_MISO__AG CYREG_PRT3_AG -#define SD_MISO__AMUX CYREG_PRT3_AMUX -#define SD_MISO__BIE CYREG_PRT3_BIE -#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MISO__BYP CYREG_PRT3_BYP -#define SD_MISO__CTL CYREG_PRT3_CTL -#define SD_MISO__DM0 CYREG_PRT3_DM0 -#define SD_MISO__DM1 CYREG_PRT3_DM1 -#define SD_MISO__DM2 CYREG_PRT3_DM2 -#define SD_MISO__DR CYREG_PRT3_DR -#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MISO__MASK 0x02u -#define SD_MISO__PORT 3u -#define SD_MISO__PRT CYREG_PRT3_PRT -#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MISO__PS CYREG_PRT3_PS -#define SD_MISO__SHIFT 1u -#define SD_MISO__SLW CYREG_PRT3_SLW - -/* SD_MOSI */ -#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE3 -#define SD_MOSI__0__MASK 0x08u -#define SD_MOSI__0__PC CYREG_PRT3_PC3 -#define SD_MOSI__0__PORT 3u -#define SD_MOSI__0__SHIFT 3u -#define SD_MOSI__AG CYREG_PRT3_AG -#define SD_MOSI__AMUX CYREG_PRT3_AMUX -#define SD_MOSI__BIE CYREG_PRT3_BIE -#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_MOSI__BYP CYREG_PRT3_BYP -#define SD_MOSI__CTL CYREG_PRT3_CTL -#define SD_MOSI__DM0 CYREG_PRT3_DM0 -#define SD_MOSI__DM1 CYREG_PRT3_DM1 -#define SD_MOSI__DM2 CYREG_PRT3_DM2 -#define SD_MOSI__DR CYREG_PRT3_DR -#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS -#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN -#define SD_MOSI__MASK 0x08u -#define SD_MOSI__PORT 3u -#define SD_MOSI__PRT CYREG_PRT3_PRT -#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_MOSI__PS CYREG_PRT3_PS -#define SD_MOSI__SHIFT 3u -#define SD_MOSI__SLW CYREG_PRT3_SLW - /* SD_RX_DMA */ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u @@ -2574,40 +2415,6 @@ #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SD_SCK */ -#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 -#define SD_SCK__0__MASK 0x04u -#define SD_SCK__0__PC CYREG_PRT3_PC2 -#define SD_SCK__0__PORT 3u -#define SD_SCK__0__SHIFT 2u -#define SD_SCK__AG CYREG_PRT3_AG -#define SD_SCK__AMUX CYREG_PRT3_AMUX -#define SD_SCK__BIE CYREG_PRT3_BIE -#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK -#define SD_SCK__BYP CYREG_PRT3_BYP -#define SD_SCK__CTL CYREG_PRT3_CTL -#define SD_SCK__DM0 CYREG_PRT3_DM0 -#define SD_SCK__DM1 CYREG_PRT3_DM1 -#define SD_SCK__DM2 CYREG_PRT3_DM2 -#define SD_SCK__DR CYREG_PRT3_DR -#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS -#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN -#define SD_SCK__MASK 0x04u -#define SD_SCK__PORT 3u -#define SD_SCK__PRT CYREG_PRT3_PRT -#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SD_SCK__PS CYREG_PRT3_PS -#define SD_SCK__SHIFT 2u -#define SD_SCK__SLW CYREG_PRT3_SLW - /* SD_TX_DMA */ #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_TX_DMA__DRQ_NUMBER 3u @@ -2628,269 +2435,287 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* USBFS */ -#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_arb_int__INTC_MASK 0x400000u -#define USBFS_arb_int__INTC_NUMBER 22u -#define USBFS_arb_int__INTC_PRIOR_NUM 6u -#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 -#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_bus_reset__INTC_MASK 0x800000u -#define USBFS_bus_reset__INTC_NUMBER 23u -#define USBFS_bus_reset__INTC_PRIOR_NUM 7u -#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 -#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 -#define USBFS_Dm__0__MASK 0x80u -#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 -#define USBFS_Dm__0__PORT 15u -#define USBFS_Dm__0__SHIFT 7u -#define USBFS_Dm__AG CYREG_PRT15_AG -#define USBFS_Dm__AMUX CYREG_PRT15_AMUX -#define USBFS_Dm__BIE CYREG_PRT15_BIE -#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dm__BYP CYREG_PRT15_BYP -#define USBFS_Dm__CTL CYREG_PRT15_CTL -#define USBFS_Dm__DM0 CYREG_PRT15_DM0 -#define USBFS_Dm__DM1 CYREG_PRT15_DM1 -#define USBFS_Dm__DM2 CYREG_PRT15_DM2 -#define USBFS_Dm__DR CYREG_PRT15_DR -#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dm__MASK 0x80u -#define USBFS_Dm__PORT 15u -#define USBFS_Dm__PRT CYREG_PRT15_PRT -#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dm__PS CYREG_PRT15_PS -#define USBFS_Dm__SHIFT 7u -#define USBFS_Dm__SLW CYREG_PRT15_SLW -#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 -#define USBFS_Dp__0__MASK 0x40u -#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 -#define USBFS_Dp__0__PORT 15u -#define USBFS_Dp__0__SHIFT 6u -#define USBFS_Dp__AG CYREG_PRT15_AG -#define USBFS_Dp__AMUX CYREG_PRT15_AMUX -#define USBFS_Dp__BIE CYREG_PRT15_BIE -#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK -#define USBFS_Dp__BYP CYREG_PRT15_BYP -#define USBFS_Dp__CTL CYREG_PRT15_CTL -#define USBFS_Dp__DM0 CYREG_PRT15_DM0 -#define USBFS_Dp__DM1 CYREG_PRT15_DM1 -#define USBFS_Dp__DM2 CYREG_PRT15_DM2 -#define USBFS_Dp__DR CYREG_PRT15_DR -#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS -#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT -#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE -#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG -#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN -#define USBFS_Dp__MASK 0x40u -#define USBFS_Dp__PORT 15u -#define USBFS_Dp__PRT CYREG_PRT15_PRT -#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL -#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN -#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 -#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 -#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 -#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 -#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT -#define USBFS_Dp__PS CYREG_PRT15_PS -#define USBFS_Dp__SHIFT 6u -#define USBFS_Dp__SLW CYREG_PRT15_SLW -#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 -#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_dp_int__INTC_MASK 0x1000u -#define USBFS_dp_int__INTC_NUMBER 12u -#define USBFS_dp_int__INTC_PRIOR_NUM 7u -#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 -#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_0__INTC_MASK 0x1000000u -#define USBFS_ep_0__INTC_NUMBER 24u -#define USBFS_ep_0__INTC_PRIOR_NUM 7u -#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 -#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u -#define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 -#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u -#define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 -#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u -#define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 -#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u -#define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 -#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_sof_int__INTC_MASK 0x200000u -#define USBFS_sof_int__INTC_NUMBER 21u -#define USBFS_sof_int__INTC_PRIOR_NUM 7u -#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 -#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG -#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG -#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN -#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR -#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG -#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN -#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR -#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG -#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN -#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR -#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG -#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN -#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR -#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG -#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN -#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR -#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG -#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN -#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR -#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG -#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN -#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR -#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG -#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN -#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR -#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN -#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR -#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR -#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA -#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB -#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA -#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB -#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR -#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA -#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB -#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA -#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB -#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR -#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA -#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB -#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA -#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB -#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR -#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA -#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB -#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA -#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB -#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR -#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA -#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB -#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA -#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB -#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR -#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA -#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB -#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA -#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB -#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR -#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA -#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB -#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA -#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB -#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR -#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA -#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB -#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA -#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB -#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE -#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT -#define USBFS_USB__CR0 CYREG_USB_CR0 -#define USBFS_USB__CR1 CYREG_USB_CR1 -#define USBFS_USB__CWA CYREG_USB_CWA -#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB -#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES -#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB -#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG -#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE -#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE -#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT -#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR -#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 -#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 -#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 -#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 -#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 -#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 -#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 -#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 -#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE -#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 -#define USBFS_USB__PM_ACT_MSK 0x01u -#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 -#define USBFS_USB__PM_STBY_MSK 0x01u -#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN -#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR -#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 -#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 -#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 -#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 -#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 -#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 -#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 -#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 -#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 -#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 -#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 -#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 -#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 -#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 -#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 -#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 -#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 -#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 -#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 -#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 -#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 -#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 -#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 -#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 -#define USBFS_USB__SOF0 CYREG_USB_SOF0 -#define USBFS_USB__SOF1 CYREG_USB_SOF1 -#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 -#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT2_AG +#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX +#define SCSI_Noise__0__BIE CYREG_PRT2_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT2_BYP +#define SCSI_Noise__0__CTL CYREG_PRT2_CTL +#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2 +#define SCSI_Noise__0__DR CYREG_PRT2_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Noise__0__INTTYPE CYREG_PICU2_INTTYPE0 +#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Noise__0__MASK 0x01u +#define SCSI_Noise__0__PC CYREG_PRT2_PC0 +#define SCSI_Noise__0__PORT 2u +#define SCSI_Noise__0__PRT CYREG_PRT2_PRT +#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT2_PS +#define SCSI_Noise__0__SHIFT 0u +#define SCSI_Noise__0__SLW CYREG_PRT2_SLW +#define SCSI_Noise__1__AG CYREG_PRT6_AG +#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT6_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT6_BYP +#define SCSI_Noise__1__CTL CYREG_PRT6_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__1__DR CYREG_PRT6_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__1__INTTYPE CYREG_PICU6_INTTYPE3 +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__1__MASK 0x08u +#define SCSI_Noise__1__PC CYREG_PRT6_PC3 +#define SCSI_Noise__1__PORT 6u +#define SCSI_Noise__1__PRT CYREG_PRT6_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT6_PS +#define SCSI_Noise__1__SHIFT 3u +#define SCSI_Noise__1__SLW CYREG_PRT6_SLW +#define SCSI_Noise__2__AG CYREG_PRT4_AG +#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT4_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT4_BYP +#define SCSI_Noise__2__CTL CYREG_PRT4_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__2__DR CYREG_PRT4_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__2__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__2__MASK 0x08u +#define SCSI_Noise__2__PC CYREG_PRT4_PC3 +#define SCSI_Noise__2__PORT 4u +#define SCSI_Noise__2__PRT CYREG_PRT4_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT4_PS +#define SCSI_Noise__2__SHIFT 3u +#define SCSI_Noise__2__SLW CYREG_PRT4_SLW +#define SCSI_Noise__3__AG CYREG_PRT4_AG +#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT4_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT4_BYP +#define SCSI_Noise__3__CTL CYREG_PRT4_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__3__DR CYREG_PRT4_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__3__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__3__MASK 0x80u +#define SCSI_Noise__3__PC CYREG_PRT4_PC7 +#define SCSI_Noise__3__PORT 4u +#define SCSI_Noise__3__PRT CYREG_PRT4_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT4_PS +#define SCSI_Noise__3__SHIFT 7u +#define SCSI_Noise__3__SLW CYREG_PRT4_SLW +#define SCSI_Noise__4__AG CYREG_PRT6_AG +#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT6_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT6_BYP +#define SCSI_Noise__4__CTL CYREG_PRT6_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__4__DR CYREG_PRT6_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__4__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__4__MASK 0x04u +#define SCSI_Noise__4__PC CYREG_PRT6_PC2 +#define SCSI_Noise__4__PORT 6u +#define SCSI_Noise__4__PRT CYREG_PRT6_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT6_PS +#define SCSI_Noise__4__SHIFT 2u +#define SCSI_Noise__4__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT6_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT6_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__ACK__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__ACK__MASK 0x04u +#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2 +#define SCSI_Noise__ACK__PORT 6u +#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT6_PS +#define SCSI_Noise__ACK__SHIFT 2u +#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT2_AG +#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX +#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP +#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL +#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT2_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Noise__ATN__INTTYPE CYREG_PICU2_INTTYPE0 +#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Noise__ATN__MASK 0x01u +#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0 +#define SCSI_Noise__ATN__PORT 2u +#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT +#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT2_PS +#define SCSI_Noise__ATN__SHIFT 0u +#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT6_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT6_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__BSY__INTTYPE CYREG_PICU6_INTTYPE3 +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__BSY__MASK 0x08u +#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3 +#define SCSI_Noise__BSY__PORT 6u +#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT6_PS +#define SCSI_Noise__BSY__SHIFT 3u +#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Noise__RST__AG CYREG_PRT4_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT4_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__RST__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__RST__MASK 0x80u +#define SCSI_Noise__RST__PC CYREG_PRT4_PC7 +#define SCSI_Noise__RST__PORT 4u +#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT4_PS +#define SCSI_Noise__RST__SHIFT 7u +#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT4_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT4_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__SEL__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__SEL__MASK 0x08u +#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3 +#define SCSI_Noise__SEL__PORT 4u +#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT4_PS +#define SCSI_Noise__SEL__SHIFT 3u +#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW /* scsiTarget */ #define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 @@ -2942,8 +2767,8 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2951,9 +2776,90 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST + +/* Debug_Timer */ +#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define Debug_Timer_Interrupt__INTC_MASK 0x01u +#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 +#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 +#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u +#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u +#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 +#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 +#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u /* timer_clock */ #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 @@ -2966,14 +2872,110 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x02u +#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST + +/* SCSI_CTL_PHASE */ +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK + +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK + +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST + /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 4.1" +#define CY_VERSION "PSoC Creator 4.2" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 16u +#define CYDEV_CHIP_DIE_PSOC4A 18u #define CYDEV_CHIP_DIE_PSOC5LP 2u #define CYDEV_CHIP_DIE_PSOC5TM 3u #define CYDEV_CHIP_DIE_TMA4 4u @@ -2989,32 +2991,34 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 16u -#define CYDEV_CHIP_MEMBER_4D 12u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u #define CYDEV_CHIP_MEMBER_4E 6u -#define CYDEV_CHIP_MEMBER_4F 17u +#define CYDEV_CHIP_MEMBER_4F 19u #define CYDEV_CHIP_MEMBER_4G 4u -#define CYDEV_CHIP_MEMBER_4H 15u -#define CYDEV_CHIP_MEMBER_4I 21u -#define CYDEV_CHIP_MEMBER_4J 13u -#define CYDEV_CHIP_MEMBER_4K 14u -#define CYDEV_CHIP_MEMBER_4L 20u -#define CYDEV_CHIP_MEMBER_4M 19u -#define CYDEV_CHIP_MEMBER_4N 9u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u #define CYDEV_CHIP_MEMBER_4O 7u -#define CYDEV_CHIP_MEMBER_4P 18u -#define CYDEV_CHIP_MEMBER_4Q 11u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u #define CYDEV_CHIP_MEMBER_4R 8u -#define CYDEV_CHIP_MEMBER_4S 10u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u #define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u #define CYDEV_CHIP_MEMBER_5A 3u #define CYDEV_CHIP_MEMBER_5B 2u -#define CYDEV_CHIP_MEMBER_6A 22u -#define CYDEV_CHIP_MEMBER_FM3 26u -#define CYDEV_CHIP_MEMBER_FM4 27u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 23u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 24u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 25u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -3040,6 +3044,7 @@ #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u @@ -3059,14 +3064,17 @@ #define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u #define CYDEV_CHIP_REVISION_5B_ES0 0u #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u -#define CYDEV_CHIP_REVISION_6A_NO_UDB 0u -#define CYDEV_CHIP_REVISION_6A_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u #define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u #define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u #define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 2e1f70d..6982fca 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -2,7 +2,7 @@ /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file contains device initialization code. @@ -10,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -101,6 +101,7 @@ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) #define CYCLOCKSTART_32KHZ_ERROR 2u #define CYCLOCKSTART_PLL_ERROR 3u #define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u #ifdef CY_NEED_CYCLOCKSTARTUPERROR @@ -124,12 +125,8 @@ static void CyClockStartupError(uint8 errorCode); CY_CFG_UNUSED static void CyClockStartupError(uint8 errorCode) { - /* To remove the compiler warning if errorCode not used. */ -#if defined(CY_PSOC3) && (CY_PSOC3) + /* To remove the compiler warning if errorCode not used. */ errorCode = errorCode; -#else - (void)errorCode; -#endif /* CY_PSOC3 */ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ /* we will end up here to allow the customer to implement something to */ @@ -403,7 +400,7 @@ void cyfitter_cfg(void) /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u)); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */ @@ -415,97 +412,113 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */ + 0x40005211u, /* Base address: 0x40005200 Count: 17 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010045u, /* Base address: 0x40010000 Count: 69 */ - 0x4001013Du, /* Base address: 0x40010100 Count: 61 */ - 0x40010247u, /* Base address: 0x40010200 Count: 71 */ - 0x4001035Fu, /* Base address: 0x40010300 Count: 95 */ - 0x4001045Fu, /* Base address: 0x40010400 Count: 95 */ - 0x40010560u, /* Base address: 0x40010500 Count: 96 */ - 0x40010650u, /* Base address: 0x40010600 Count: 80 */ - 0x40010755u, /* Base address: 0x40010700 Count: 85 */ - 0x40010912u, /* Base address: 0x40010900 Count: 18 */ - 0x40010A46u, /* Base address: 0x40010A00 Count: 70 */ - 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */ - 0x40010C56u, /* Base address: 0x40010C00 Count: 86 */ - 0x40010D58u, /* Base address: 0x40010D00 Count: 88 */ - 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */ - 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */ - 0x4001141Fu, /* Base address: 0x40011400 Count: 31 */ - 0x40011554u, /* Base address: 0x40011500 Count: 84 */ - 0x40011656u, /* Base address: 0x40011600 Count: 86 */ - 0x40011744u, /* Base address: 0x40011700 Count: 68 */ - 0x40011804u, /* Base address: 0x40011800 Count: 4 */ - 0x40011905u, /* Base address: 0x40011900 Count: 5 */ - 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ - 0x40014019u, /* Base address: 0x40014000 Count: 25 */ - 0x40014118u, /* Base address: 0x40014100 Count: 24 */ - 0x4001420Du, /* Base address: 0x40014200 Count: 13 */ - 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ - 0x40014411u, /* Base address: 0x40014400 Count: 17 */ - 0x40014518u, /* Base address: 0x40014500 Count: 24 */ - 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */ - 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */ + 0x40010047u, /* Base address: 0x40010000 Count: 71 */ + 0x40010142u, /* Base address: 0x40010100 Count: 66 */ + 0x40010254u, /* Base address: 0x40010200 Count: 84 */ + 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */ + 0x4001044Fu, /* Base address: 0x40010400 Count: 79 */ + 0x4001055Au, /* Base address: 0x40010500 Count: 90 */ + 0x40010653u, /* Base address: 0x40010600 Count: 83 */ + 0x40010752u, /* Base address: 0x40010700 Count: 82 */ + 0x4001091Cu, /* Base address: 0x40010900 Count: 28 */ + 0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */ + 0x40010B4Fu, /* Base address: 0x40010B00 Count: 79 */ + 0x40010C4Cu, /* Base address: 0x40010C00 Count: 76 */ + 0x40010D50u, /* Base address: 0x40010D00 Count: 80 */ + 0x40010E51u, /* Base address: 0x40010E00 Count: 81 */ + 0x40010F3Au, /* Base address: 0x40010F00 Count: 58 */ + 0x40011460u, /* Base address: 0x40011400 Count: 96 */ + 0x4001154Du, /* Base address: 0x40011500 Count: 77 */ + 0x40011646u, /* Base address: 0x40011600 Count: 70 */ + 0x40011752u, /* Base address: 0x40011700 Count: 82 */ + 0x40011854u, /* Base address: 0x40011800 Count: 84 */ + 0x40011954u, /* Base address: 0x40011900 Count: 84 */ + 0x40011B0Eu, /* Base address: 0x40011B00 Count: 14 */ + 0x40014016u, /* Base address: 0x40014000 Count: 22 */ + 0x4001411Du, /* Base address: 0x40014100 Count: 29 */ + 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ + 0x4001430Fu, /* Base address: 0x40014300 Count: 15 */ + 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */ + 0x4001451Du, /* Base address: 0x40014500 Count: 29 */ + 0x4001460Au, /* Base address: 0x40014600 Count: 10 */ + 0x40014712u, /* Base address: 0x40014700 Count: 18 */ 0x40014809u, /* Base address: 0x40014800 Count: 9 */ - 0x4001490Du, /* Base address: 0x40014900 Count: 13 */ - 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */ - 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */ - 0x40015004u, /* Base address: 0x40015000 Count: 4 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C0Cu, /* Base address: 0x40014C00 Count: 12 */ + 0x40014D0Cu, /* Base address: 0x40014D00 Count: 12 */ + 0x40015005u, /* Base address: 0x40015000 Count: 5 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x36u}, - {0x00u, 0x04u}, - {0x01u, 0x0Cu}, + {0x0Au, 0x27u}, + {0x00u, 0x48u}, + {0x01u, 0x4Cu}, {0x04u, 0x31u}, {0x10u, 0xC4u}, - {0x11u, 0x44u}, - {0x18u, 0x04u}, + {0x11u, 0x40u}, + {0x19u, 0x08u}, {0x1Cu, 0x30u}, + {0x20u, 0x10u}, + {0x21u, 0x10u}, {0x24u, 0x44u}, - {0x28u, 0x02u}, - {0x30u, 0x20u}, - {0x31u, 0x30u}, + {0x28u, 0x01u}, + {0x29u, 0x01u}, + {0x30u, 0x30u}, + {0x31u, 0x20u}, {0x78u, 0x20u}, {0x79u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x85u, 0x0Fu}, - {0x02u, 0xFFu}, - {0x04u, 0x0Fu}, - {0x06u, 0xF0u}, - {0x0Au, 0xFFu}, - {0x0Eu, 0xFFu}, - {0x10u, 0x69u}, - {0x12u, 0x96u}, - {0x14u, 0xFFu}, - {0x18u, 0x55u}, - {0x19u, 0x04u}, - {0x1Au, 0xAAu}, - {0x1Cu, 0xFFu}, + {0x87u, 0x0Fu}, + {0x00u, 0xE0u}, + {0x01u, 0x03u}, + {0x03u, 0x74u}, + {0x04u, 0x40u}, + {0x05u, 0x20u}, + {0x06u, 0x80u}, + {0x07u, 0x40u}, + {0x08u, 0x0Bu}, + {0x09u, 0x02u}, + {0x0Au, 0xF4u}, + {0x0Cu, 0x11u}, + {0x0Du, 0x64u}, + {0x0Eu, 0xECu}, + {0x16u, 0xFFu}, + {0x17u, 0x08u}, + {0x18u, 0xCAu}, + {0x1Au, 0x15u}, + {0x1Bu, 0x01u}, {0x1Du, 0x01u}, - {0x1Fu, 0x02u}, - {0x23u, 0x01u}, - {0x28u, 0x33u}, - {0x2Au, 0xCCu}, - {0x2Bu, 0x02u}, - {0x31u, 0x04u}, - {0x32u, 0xFFu}, - {0x35u, 0x03u}, + {0x1Fu, 0x6Eu}, + {0x20u, 0x06u}, + {0x26u, 0x10u}, + {0x27u, 0x7Fu}, + {0x28u, 0x40u}, + {0x29u, 0x78u}, + {0x2Au, 0x80u}, + {0x2Bu, 0x03u}, + {0x2Cu, 0x01u}, + {0x2Du, 0x20u}, + {0x2Fu, 0x40u}, + {0x32u, 0xC0u}, + {0x34u, 0x3Fu}, + {0x35u, 0x60u}, + {0x37u, 0x1Fu}, {0x3Au, 0x08u}, - {0x3Fu, 0x10u}, - {0x40u, 0x53u}, - {0x41u, 0x06u}, - {0x42u, 0x40u}, - {0x45u, 0xEFu}, + {0x3Bu, 0x20u}, + {0x40u, 0x52u}, + {0x41u, 0x03u}, + {0x42u, 0x60u}, + {0x45u, 0xE2u}, {0x46u, 0xDCu}, - {0x47u, 0x20u}, - {0x48u, 0x2Fu}, + {0x47u, 0x0Fu}, + {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, {0x4Bu, 0xFFu}, @@ -515,7 +528,7 @@ void cyfitter_cfg(void) {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x91u}, + {0x5Cu, 0x11u}, {0x5Du, 0x01u}, {0x5Fu, 0x01u}, {0x60u, 0x08u}, @@ -524,299 +537,296 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x81u, 0x02u}, - {0x83u, 0x01u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x05u}, - {0x91u, 0x02u}, - {0x93u, 0x11u}, - {0x95u, 0x02u}, - {0x97u, 0x09u}, - {0x99u, 0x01u}, - {0x9Bu, 0x02u}, - {0xB1u, 0x04u}, - {0xB3u, 0x03u}, - {0xB5u, 0x10u}, - {0xB7u, 0x08u}, - {0xBBu, 0x08u}, - {0xD6u, 0x08u}, + {0x8Bu, 0x01u}, + {0xA6u, 0x01u}, + {0xABu, 0x02u}, + {0xB2u, 0x01u}, + {0xB5u, 0x01u}, + {0xB7u, 0x02u}, + {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x10u}, - {0xDDu, 0x90u}, + {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0xA8u}, - {0x03u, 0x40u}, - {0x09u, 0x08u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x44u}, - {0x12u, 0x04u}, - {0x19u, 0x08u}, - {0x1Au, 0x10u}, - {0x21u, 0x02u}, - {0x22u, 0x10u}, - {0x25u, 0x41u}, - {0x27u, 0x18u}, - {0x2Au, 0x10u}, - {0x2Bu, 0xC0u}, - {0x32u, 0x80u}, - {0x33u, 0x10u}, - {0x34u, 0x02u}, - {0x37u, 0x18u}, - {0x3Du, 0x82u}, - {0x41u, 0x09u}, - {0x48u, 0x01u}, - {0x49u, 0xA0u}, - {0x4Au, 0x50u}, - {0x51u, 0x50u}, - {0x52u, 0x21u}, - {0x59u, 0x10u}, - {0x5Au, 0x84u}, - {0x5Bu, 0x01u}, - {0x5Cu, 0x40u}, - {0x60u, 0x80u}, + {0x01u, 0x8Au}, + {0x03u, 0x08u}, + {0x08u, 0x80u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x22u}, + {0x10u, 0x80u}, + {0x11u, 0x80u}, + {0x12u, 0x14u}, + {0x17u, 0x08u}, + {0x19u, 0x28u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x10u}, + {0x20u, 0x02u}, + {0x21u, 0x20u}, + {0x27u, 0x0Au}, + {0x29u, 0x20u}, + {0x2Bu, 0x22u}, + {0x2Eu, 0x10u}, + {0x30u, 0x20u}, + {0x31u, 0x84u}, + {0x38u, 0xA0u}, + {0x39u, 0x01u}, + {0x3Bu, 0x04u}, + {0x3Cu, 0x22u}, + {0x3Du, 0x01u}, + {0x42u, 0x0Cu}, + {0x43u, 0x08u}, + {0x44u, 0x20u}, + {0x45u, 0x08u}, + {0x48u, 0x05u}, + {0x49u, 0x84u}, + {0x4Bu, 0x0Au}, + {0x50u, 0x90u}, + {0x51u, 0x08u}, + {0x52u, 0x10u}, + {0x59u, 0x08u}, + {0x5Au, 0x22u}, + {0x5Bu, 0x80u}, {0x61u, 0x20u}, - {0x62u, 0x08u}, - {0x63u, 0x02u}, - {0x64u, 0x02u}, - {0x68u, 0x04u}, - {0x69u, 0x45u}, - {0x70u, 0x94u}, - {0x72u, 0x80u}, - {0x81u, 0x04u}, - {0x82u, 0x80u}, - {0x83u, 0x01u}, - {0x85u, 0x04u}, - {0x86u, 0x10u}, - {0x88u, 0x04u}, - {0x8Au, 0x10u}, - {0x8Cu, 0x10u}, - {0x8Du, 0x20u}, - {0x8Eu, 0x90u}, + {0x62u, 0x01u}, + {0x63u, 0x21u}, + {0x68u, 0x48u}, + {0x69u, 0x84u}, + {0x71u, 0x10u}, + {0x72u, 0x81u}, + {0x73u, 0x10u}, + {0x81u, 0xB0u}, + {0x83u, 0x0Au}, + {0x84u, 0x80u}, + {0x87u, 0x40u}, + {0x88u, 0x01u}, + {0x8Au, 0x05u}, + {0x8Eu, 0x02u}, {0xC0u, 0x0Fu}, - {0xC2u, 0x0Fu}, - {0xC4u, 0x02u}, - {0xCAu, 0x05u}, - {0xCCu, 0xECu}, - {0xCEu, 0x90u}, - {0xD0u, 0x03u}, + {0xC2u, 0x06u}, + {0xC4u, 0x2Fu}, + {0xCAu, 0x2Eu}, + {0xCCu, 0x0Eu}, + {0xCEu, 0x2Fu}, + {0xD0u, 0x06u}, {0xD2u, 0x0Cu}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x1Fu}, - {0xE2u, 0x82u}, - {0xE4u, 0x02u}, - {0xE6u, 0x05u}, - {0x02u, 0xFFu}, - {0x08u, 0x0Bu}, - {0x0Au, 0xF4u}, - {0x10u, 0xE0u}, - {0x14u, 0xCAu}, - {0x16u, 0x15u}, - {0x18u, 0x40u}, - {0x1Au, 0x80u}, - {0x1Cu, 0x11u}, - {0x1Eu, 0xECu}, - {0x20u, 0x40u}, - {0x22u, 0x80u}, - {0x24u, 0x01u}, - {0x2Au, 0x10u}, - {0x2Cu, 0x06u}, - {0x32u, 0x3Fu}, - {0x34u, 0xC0u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x08u}, + {0xE4u, 0x05u}, + {0xE6u, 0x02u}, + {0x00u, 0x02u}, + {0x02u, 0x05u}, + {0x04u, 0x02u}, + {0x06u, 0x01u}, + {0x0Cu, 0x02u}, + {0x0Eu, 0x01u}, + {0x14u, 0x02u}, + {0x16u, 0x01u}, + {0x18u, 0x01u}, + {0x1Au, 0x02u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x09u}, + {0x20u, 0x02u}, + {0x22u, 0x11u}, + {0x24u, 0x02u}, + {0x25u, 0x01u}, + {0x26u, 0x01u}, + {0x30u, 0x08u}, + {0x32u, 0x04u}, + {0x34u, 0x03u}, + {0x35u, 0x01u}, + {0x36u, 0x10u}, {0x3Au, 0x20u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, + {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x91u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x03u}, - {0x81u, 0x08u}, - {0x82u, 0x0Cu}, - {0x83u, 0x10u}, - {0x86u, 0xFFu}, - {0x87u, 0x80u}, - {0x88u, 0x05u}, - {0x8Au, 0x0Au}, - {0x8Bu, 0x04u}, - {0x8Fu, 0x9Bu}, - {0x90u, 0x06u}, - {0x92u, 0x09u}, - {0x93u, 0x60u}, - {0x95u, 0x01u}, - {0x97u, 0x02u}, - {0x98u, 0x60u}, - {0x99u, 0x9Bu}, - {0x9Au, 0x90u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x0Fu}, - {0x9Du, 0x08u}, - {0x9Eu, 0xF0u}, - {0x9Fu, 0x10u}, - {0xA1u, 0x1Bu}, - {0xA2u, 0xFFu}, - {0xA4u, 0x30u}, - {0xA5u, 0x01u}, - {0xA6u, 0xC0u}, - {0xA7u, 0x02u}, - {0xA8u, 0xFFu}, - {0xA9u, 0x80u}, - {0xABu, 0x3Bu}, - {0xACu, 0x50u}, - {0xAEu, 0xA0u}, - {0xAFu, 0x1Bu}, - {0xB1u, 0xE0u}, - {0xB3u, 0x03u}, - {0xB4u, 0xFFu}, - {0xB5u, 0x04u}, - {0xB7u, 0x18u}, - {0xBBu, 0x88u}, - {0xBEu, 0x10u}, + {0x80u, 0x02u}, + {0x81u, 0x8Bu}, + {0x82u, 0x21u}, + {0x83u, 0x74u}, + {0x84u, 0x02u}, + {0x86u, 0x01u}, + {0x87u, 0x01u}, + {0x89u, 0x02u}, + {0x8Cu, 0x02u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x20u}, + {0x90u, 0x02u}, + {0x92u, 0x05u}, + {0x94u, 0x02u}, + {0x95u, 0x88u}, + {0x96u, 0x09u}, + {0x97u, 0x77u}, + {0x98u, 0x01u}, + {0x99u, 0x40u}, + {0x9Au, 0x12u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x03u}, + {0x9Eu, 0x01u}, + {0x9Fu, 0x0Cu}, + {0xA1u, 0x34u}, + {0xA3u, 0x40u}, + {0xA4u, 0x02u}, + {0xA6u, 0x01u}, + {0xA7u, 0x77u}, + {0xA9u, 0x3Du}, + {0xABu, 0x42u}, + {0xACu, 0x10u}, + {0xADu, 0x10u}, + {0xAEu, 0x20u}, + {0xAFu, 0x20u}, + {0xB0u, 0x30u}, + {0xB1u, 0x30u}, + {0xB2u, 0x04u}, + {0xB4u, 0x03u}, + {0xB5u, 0xC0u}, + {0xB6u, 0x08u}, + {0xB7u, 0x0Fu}, + {0xBAu, 0x20u}, + {0xBBu, 0xA2u}, + {0xBEu, 0x01u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x10u}, + {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x04u}, - {0x03u, 0x84u}, - {0x05u, 0x20u}, - {0x07u, 0x40u}, - {0x0Au, 0x48u}, - {0x0Bu, 0x02u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x05u}, - {0x0Fu, 0x80u}, - {0x11u, 0x02u}, - {0x12u, 0x10u}, - {0x13u, 0x90u}, - {0x15u, 0xA4u}, + {0x00u, 0x81u}, + {0x01u, 0x08u}, + {0x05u, 0x05u}, + {0x07u, 0x02u}, + {0x09u, 0x08u}, + {0x0Au, 0x05u}, + {0x0Bu, 0x40u}, + {0x0Eu, 0x1Au}, + {0x10u, 0x02u}, + {0x11u, 0x08u}, {0x16u, 0x40u}, - {0x1Bu, 0x20u}, - {0x1Du, 0x08u}, - {0x1Eu, 0x04u}, - {0x22u, 0x9Au}, - {0x28u, 0x22u}, - {0x29u, 0x20u}, - {0x2Bu, 0x40u}, - {0x2Cu, 0x20u}, - {0x2Fu, 0x20u}, - {0x30u, 0x10u}, - {0x32u, 0x8Au}, - {0x34u, 0x80u}, - {0x36u, 0x80u}, - {0x38u, 0x28u}, - {0x3Au, 0x02u}, - {0x3Bu, 0x80u}, - {0x44u, 0x10u}, - {0x45u, 0x08u}, - {0x58u, 0x01u}, - {0x59u, 0x84u}, - {0x5Bu, 0x20u}, - {0x5Cu, 0x04u}, - {0x5Eu, 0xA2u}, - {0x60u, 0x08u}, - {0x62u, 0x04u}, - {0x63u, 0x45u}, - {0x66u, 0x80u}, - {0x79u, 0x80u}, - {0x7Bu, 0x02u}, - {0x81u, 0x81u}, - {0x82u, 0x02u}, - {0x84u, 0x20u}, - {0x88u, 0x40u}, - {0x89u, 0x44u}, - {0x8Bu, 0x10u}, - {0x8Cu, 0x04u}, - {0x8Eu, 0x21u}, - {0x8Fu, 0x02u}, - {0x90u, 0x08u}, - {0x91u, 0xE1u}, - {0x92u, 0x10u}, - {0x93u, 0x02u}, - {0x95u, 0x02u}, - {0x96u, 0x86u}, - {0x97u, 0x44u}, - {0x98u, 0x01u}, - {0x99u, 0x04u}, - {0x9Au, 0x11u}, - {0x9Bu, 0x30u}, - {0x9Cu, 0x80u}, - {0x9Du, 0x30u}, - {0x9Eu, 0x04u}, - {0x9Fu, 0x41u}, - {0xA0u, 0x80u}, - {0xA2u, 0x70u}, - {0xA3u, 0x80u}, - {0xA4u, 0x01u}, - {0xA5u, 0x28u}, - {0xA6u, 0x08u}, - {0xA7u, 0x01u}, - {0xA9u, 0x02u}, - {0xABu, 0x40u}, - {0xACu, 0x01u}, - {0xAEu, 0x40u}, - {0xAFu, 0x20u}, - {0xB0u, 0x01u}, - {0xB4u, 0x40u}, - {0xB5u, 0x08u}, - {0xC0u, 0x5Eu}, - {0xC2u, 0xFBu}, - {0xC4u, 0xFFu}, - {0xCAu, 0x0Fu}, - {0xCCu, 0x0Fu}, - {0xCEu, 0x0Fu}, - {0xD6u, 0xFFu}, - {0xD8u, 0x1Fu}, - {0xE2u, 0x24u}, - {0xE6u, 0x0Du}, - {0xE8u, 0x40u}, - {0xEAu, 0x06u}, - {0xECu, 0x08u}, - {0x01u, 0x40u}, - {0x02u, 0x24u}, - {0x03u, 0x80u}, - {0x05u, 0x04u}, - {0x06u, 0x40u}, - {0x07u, 0x08u}, - {0x08u, 0x24u}, - {0x09u, 0x04u}, - {0x0Au, 0x09u}, - {0x0Bu, 0x08u}, - {0x0Du, 0x01u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x02u}, - {0x11u, 0x3Fu}, - {0x12u, 0x18u}, - {0x13u, 0x40u}, - {0x14u, 0x24u}, - {0x15u, 0x3Fu}, - {0x16u, 0x12u}, - {0x17u, 0x40u}, - {0x19u, 0x01u}, - {0x1Au, 0x03u}, - {0x1Bu, 0x02u}, - {0x1Eu, 0x80u}, - {0x1Fu, 0x7Fu}, - {0x21u, 0x10u}, - {0x22u, 0x04u}, - {0x23u, 0x20u}, - {0x25u, 0x80u}, - {0x27u, 0x7Fu}, - {0x29u, 0x10u}, + {0x17u, 0x08u}, + {0x18u, 0x88u}, + {0x19u, 0x0Au}, + {0x1Au, 0x45u}, + {0x1Bu, 0x40u}, + {0x1Cu, 0x20u}, + {0x1Du, 0x05u}, + {0x1Eu, 0x0Au}, + {0x1Fu, 0x30u}, + {0x20u, 0x48u}, + {0x21u, 0x20u}, + {0x22u, 0x40u}, + {0x23u, 0x80u}, + {0x25u, 0x10u}, + {0x28u, 0x02u}, + {0x29u, 0x22u}, {0x2Bu, 0x20u}, - {0x2Cu, 0x40u}, - {0x2Du, 0x80u}, - {0x2Eu, 0x80u}, - {0x2Fu, 0x7Fu}, - {0x30u, 0x38u}, - {0x31u, 0xC0u}, - {0x33u, 0x0Cu}, - {0x34u, 0x07u}, - {0x35u, 0x03u}, - {0x36u, 0xC0u}, - {0x37u, 0x30u}, - {0x3Bu, 0xAAu}, - {0x3Eu, 0x40u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x21u}, + {0x31u, 0x20u}, + {0x32u, 0x40u}, + {0x33u, 0x08u}, + {0x38u, 0x60u}, + {0x39u, 0x01u}, + {0x3Bu, 0x08u}, + {0x58u, 0x14u}, + {0x5Bu, 0x40u}, + {0x5Du, 0x40u}, + {0x60u, 0x08u}, + {0x62u, 0x84u}, + {0x63u, 0x04u}, + {0x66u, 0x40u}, + {0x68u, 0x02u}, + {0x6Cu, 0x20u}, + {0x6Du, 0x10u}, + {0x6Fu, 0x02u}, + {0x80u, 0x04u}, + {0x81u, 0x40u}, + {0x82u, 0x01u}, + {0x88u, 0x01u}, + {0x8Au, 0x10u}, + {0x8Bu, 0x22u}, + {0x8Eu, 0x02u}, + {0x90u, 0x20u}, + {0x91u, 0x05u}, + {0x92u, 0x10u}, + {0x93u, 0x58u}, + {0x94u, 0x80u}, + {0x96u, 0x22u}, + {0x97u, 0x25u}, + {0x98u, 0xA4u}, + {0x99u, 0xA0u}, + {0x9Au, 0x9Au}, + {0x9Bu, 0x4Au}, + {0x9Du, 0x02u}, + {0x9Eu, 0x05u}, + {0x9Fu, 0x80u}, + {0xA0u, 0x88u}, + {0xA4u, 0x34u}, + {0xA5u, 0x50u}, + {0xA7u, 0x38u}, + {0xA9u, 0x10u}, + {0xACu, 0x40u}, + {0xB0u, 0x04u}, + {0xB1u, 0x08u}, + {0xB5u, 0x40u}, + {0xB7u, 0x41u}, + {0xC0u, 0xBDu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x35u}, + {0xCAu, 0x4Fu}, + {0xCCu, 0x0Eu}, + {0xCEu, 0x0Fu}, + {0xD6u, 0x1Eu}, + {0xD8u, 0x1Eu}, + {0xE2u, 0x04u}, + {0xE4u, 0x01u}, + {0xE6u, 0x80u}, + {0xE8u, 0x02u}, + {0xEAu, 0x40u}, + {0xEEu, 0x20u}, + {0x00u, 0xFFu}, + {0x01u, 0x1Bu}, + {0x05u, 0x9Bu}, + {0x06u, 0xFFu}, + {0x07u, 0x40u}, + {0x08u, 0xFFu}, + {0x09u, 0x08u}, + {0x0Bu, 0x10u}, + {0x0Cu, 0x0Fu}, + {0x0Eu, 0xF0u}, + {0x0Fu, 0x9Bu}, + {0x13u, 0x60u}, + {0x14u, 0x69u}, + {0x15u, 0x80u}, + {0x16u, 0x96u}, + {0x17u, 0x3Bu}, + {0x19u, 0x08u}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x10u}, + {0x1Du, 0x01u}, + {0x1Fu, 0x02u}, + {0x20u, 0x33u}, + {0x22u, 0xCCu}, + {0x23u, 0x04u}, + {0x24u, 0x55u}, + {0x26u, 0xAAu}, + {0x27u, 0x1Bu}, + {0x29u, 0x01u}, + {0x2Bu, 0x02u}, + {0x2Eu, 0xFFu}, + {0x2Fu, 0x80u}, + {0x30u, 0xFFu}, + {0x31u, 0xE0u}, + {0x33u, 0x04u}, + {0x35u, 0x18u}, + {0x37u, 0x03u}, + {0x3Au, 0x02u}, + {0x3Bu, 0xA0u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -824,357 +834,673 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x82u, 0x7Fu}, - {0x85u, 0x0Fu}, - {0x88u, 0x20u}, - {0x89u, 0x05u}, - {0x8Au, 0x40u}, - {0x8Bu, 0x0Au}, - {0x8Eu, 0x08u}, - {0x90u, 0x64u}, - {0x94u, 0x78u}, - {0x95u, 0x06u}, - {0x96u, 0x03u}, - {0x97u, 0x09u}, - {0x98u, 0x02u}, - {0x99u, 0x90u}, - {0x9Bu, 0x2Fu}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x74u}, - {0x9Fu, 0x70u}, - {0xA1u, 0xC0u}, - {0xA3u, 0x1Fu}, - {0xA5u, 0x03u}, - {0xA6u, 0x01u}, - {0xA7u, 0x0Cu}, - {0xA8u, 0x01u}, - {0xA9u, 0xA0u}, - {0xAAu, 0x6Eu}, + {0x80u, 0xFFu}, + {0x84u, 0x55u}, + {0x85u, 0x06u}, + {0x86u, 0xAAu}, + {0x87u, 0x09u}, + {0x88u, 0xFFu}, + {0x89u, 0x03u}, + {0x8Bu, 0x0Cu}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0x70u}, + {0x94u, 0x0Fu}, + {0x95u, 0x10u}, + {0x96u, 0xF0u}, + {0x97u, 0x2Fu}, + {0x9Au, 0xFFu}, + {0x9Du, 0x40u}, + {0x9Fu, 0x1Fu}, + {0xA5u, 0x0Fu}, + {0xA6u, 0xFFu}, + {0xA8u, 0x69u}, + {0xA9u, 0x20u}, + {0xAAu, 0x96u}, {0xABu, 0x4Fu}, - {0xACu, 0x20u}, - {0xAEu, 0x40u}, - {0xAFu, 0x80u}, - {0xB1u, 0x7Fu}, - {0xB4u, 0x60u}, - {0xB5u, 0x80u}, - {0xB6u, 0x1Fu}, - {0xBAu, 0x20u}, + {0xACu, 0x33u}, + {0xADu, 0x05u}, + {0xAEu, 0xCCu}, + {0xAFu, 0x0Au}, + {0xB2u, 0xFFu}, + {0xB7u, 0x7Fu}, + {0xBAu, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x00u, 0x40u}, + {0x01u, 0x22u}, + {0x03u, 0x20u}, + {0x04u, 0x80u}, + {0x05u, 0xA6u}, + {0x06u, 0x08u}, + {0x08u, 0x08u}, + {0x09u, 0x10u}, + {0x0Eu, 0x18u}, + {0x12u, 0xA0u}, + {0x13u, 0x80u}, + {0x14u, 0x02u}, + {0x16u, 0x04u}, + {0x17u, 0x04u}, + {0x18u, 0x40u}, + {0x1Bu, 0x02u}, + {0x1Eu, 0x10u}, + {0x20u, 0x20u}, + {0x22u, 0x52u}, + {0x23u, 0x41u}, + {0x25u, 0x40u}, + {0x27u, 0x02u}, + {0x2Au, 0x82u}, + {0x2Bu, 0x24u}, + {0x2Cu, 0x20u}, + {0x2Du, 0x20u}, + {0x2Fu, 0x02u}, + {0x32u, 0x52u}, + {0x33u, 0x08u}, + {0x35u, 0x80u}, + {0x37u, 0x84u}, + {0x38u, 0x80u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x12u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x10u}, + {0x43u, 0x0Cu}, + {0x58u, 0x10u}, + {0x59u, 0x08u}, + {0x5Bu, 0x41u}, + {0x60u, 0x01u}, + {0x61u, 0x46u}, + {0x62u, 0x20u}, + {0x63u, 0x18u}, + {0x7Du, 0x20u}, + {0x7Fu, 0x08u}, + {0x81u, 0x20u}, + {0x83u, 0x40u}, + {0x84u, 0x20u}, + {0x88u, 0x10u}, + {0x8Bu, 0x02u}, + {0x91u, 0x04u}, + {0x93u, 0x22u}, + {0x94u, 0x01u}, + {0x96u, 0x22u}, + {0x97u, 0x01u}, + {0x98u, 0xA9u}, + {0x99u, 0x82u}, + {0x9Au, 0x8Eu}, + {0x9Cu, 0x02u}, + {0xA0u, 0xA8u}, + {0xA2u, 0x84u}, + {0xA3u, 0x60u}, + {0xA4u, 0x40u}, + {0xA5u, 0x08u}, + {0xA6u, 0x02u}, + {0xA7u, 0x18u}, + {0xABu, 0x08u}, + {0xACu, 0x30u}, + {0xADu, 0x50u}, + {0xAFu, 0x10u}, + {0xB4u, 0x40u}, + {0xB5u, 0x04u}, + {0xB6u, 0x40u}, + {0xC0u, 0xFFu}, + {0xC2u, 0x66u}, + {0xC4u, 0xEDu}, + {0xCAu, 0x7Fu}, + {0xCCu, 0x5Fu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x02u}, + {0xE2u, 0x04u}, + {0xE6u, 0x11u}, + {0xE8u, 0x0Au}, + {0xEAu, 0x10u}, + {0xECu, 0x01u}, + {0xEEu, 0x02u}, + {0x00u, 0x1Fu}, + {0x01u, 0xE0u}, + {0x02u, 0x20u}, + {0x06u, 0x60u}, + {0x07u, 0x01u}, + {0x0Au, 0x9Fu}, + {0x0Fu, 0xECu}, + {0x10u, 0x90u}, + {0x11u, 0x21u}, + {0x12u, 0x40u}, + {0x13u, 0x02u}, + {0x14u, 0xC0u}, + {0x15u, 0x04u}, + {0x16u, 0x08u}, + {0x17u, 0x43u}, + {0x18u, 0xC0u}, + {0x19u, 0x88u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x03u}, + {0x1Cu, 0xC0u}, + {0x1Eu, 0x01u}, + {0x20u, 0xC0u}, + {0x22u, 0x02u}, + {0x25u, 0x10u}, + {0x26u, 0xFFu}, + {0x28u, 0x7Fu}, + {0x2Au, 0x80u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x80u}, + {0x2Du, 0x10u}, + {0x33u, 0x10u}, + {0x34u, 0xFFu}, + {0x35u, 0xE0u}, + {0x37u, 0x0Fu}, + {0x39u, 0x08u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x10u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x0Fu}, + {0x82u, 0x80u}, + {0x84u, 0x50u}, + {0x86u, 0x8Fu}, + {0x8Fu, 0x04u}, + {0x90u, 0x04u}, + {0x91u, 0x04u}, + {0x92u, 0x08u}, + {0x93u, 0x08u}, + {0x94u, 0x20u}, + {0x96u, 0x0Fu}, + {0x98u, 0x4Fu}, + {0x9Au, 0x80u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x01u}, + {0x9Eu, 0x02u}, + {0xA0u, 0x01u}, + {0xA2u, 0x02u}, + {0xA3u, 0x01u}, + {0xA6u, 0x10u}, + {0xA8u, 0x04u}, + {0xAAu, 0x08u}, + {0xACu, 0x10u}, + {0xAEu, 0x8Fu}, + {0xAFu, 0x02u}, + {0xB1u, 0x01u}, + {0xB2u, 0xF0u}, + {0xB3u, 0x02u}, + {0xB4u, 0x0Cu}, + {0xB5u, 0x0Cu}, + {0xB6u, 0x03u}, + {0xB8u, 0x0Au}, + {0xBAu, 0xA0u}, + {0xBEu, 0x01u}, {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x01u, 0x0Au}, + {0x04u, 0x02u}, + {0x06u, 0x04u}, + {0x07u, 0x20u}, + {0x08u, 0x10u}, + {0x09u, 0x02u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x20u}, + {0x0Eu, 0x54u}, + {0x0Fu, 0x01u}, + {0x10u, 0x20u}, + {0x11u, 0x20u}, + {0x12u, 0x82u}, + {0x15u, 0x01u}, + {0x17u, 0x58u}, + {0x18u, 0x20u}, + {0x19u, 0x08u}, + {0x1Au, 0x82u}, + {0x1Bu, 0x1Cu}, + {0x1Fu, 0x20u}, + {0x20u, 0x80u}, + {0x21u, 0x08u}, + {0x23u, 0x04u}, + {0x25u, 0x40u}, + {0x27u, 0x24u}, + {0x28u, 0x10u}, + {0x29u, 0x40u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x40u}, + {0x2Fu, 0x25u}, + {0x30u, 0x02u}, + {0x31u, 0x20u}, + {0x37u, 0x19u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x60u}, + {0x3Cu, 0x08u}, + {0x3Du, 0xA0u}, + {0x3Eu, 0x02u}, + {0x3Fu, 0x20u}, + {0x49u, 0x80u}, + {0x4Au, 0x02u}, + {0x58u, 0xA5u}, + {0x5Cu, 0x40u}, + {0x62u, 0x40u}, + {0x64u, 0x02u}, + {0x68u, 0x02u}, + {0x69u, 0x40u}, + {0x81u, 0x40u}, + {0x82u, 0x40u}, + {0x8Au, 0x40u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x40u}, + {0x91u, 0x04u}, + {0x93u, 0x60u}, + {0x94u, 0x04u}, + {0x96u, 0x02u}, + {0x98u, 0xA5u}, + {0x99u, 0xC2u}, + {0x9Au, 0x08u}, + {0x9Cu, 0x02u}, + {0xA0u, 0x28u}, + {0xA1u, 0x22u}, + {0xA2u, 0x80u}, + {0xA3u, 0x40u}, + {0xA4u, 0x40u}, + {0xA5u, 0x08u}, + {0xA7u, 0x18u}, + {0xA9u, 0x08u}, + {0xAFu, 0x01u}, + {0xB0u, 0x94u}, + {0xC0u, 0x7Cu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x79u}, + {0xCCu, 0xE5u}, + {0xCEu, 0xD8u}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x18u}, + {0xE2u, 0x04u}, + {0xE4u, 0x14u}, + {0xEAu, 0x03u}, + {0xEEu, 0x04u}, + {0x80u, 0x08u}, + {0x82u, 0x40u}, + {0x8Bu, 0x40u}, + {0x8Fu, 0x20u}, + {0x91u, 0x10u}, + {0x92u, 0x0Au}, + {0x93u, 0x90u}, + {0x95u, 0x48u}, + {0x96u, 0x20u}, + {0x97u, 0x02u}, + {0x98u, 0x20u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x60u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x04u}, + {0xA1u, 0x40u}, + {0xA2u, 0x02u}, + {0xA3u, 0xA4u}, + {0xA7u, 0x12u}, + {0xACu, 0x04u}, + {0xAFu, 0x02u}, + {0xB7u, 0x10u}, + {0xE2u, 0x40u}, + {0xE4u, 0x30u}, + {0xE6u, 0x80u}, + {0xEAu, 0x23u}, + {0xEEu, 0x04u}, + {0x04u, 0x30u}, + {0x06u, 0xC0u}, + {0x07u, 0x01u}, + {0x0Au, 0xFFu}, + {0x0Bu, 0x02u}, + {0x0Eu, 0xFFu}, + {0x10u, 0x60u}, + {0x12u, 0x90u}, + {0x13u, 0x08u}, + {0x14u, 0x0Fu}, + {0x16u, 0xF0u}, + {0x18u, 0x06u}, + {0x1Au, 0x09u}, + {0x1Bu, 0x04u}, + {0x1Cu, 0x05u}, + {0x1Eu, 0x0Au}, + {0x20u, 0xFFu}, + {0x28u, 0x50u}, + {0x29u, 0x04u}, + {0x2Au, 0xA0u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x03u}, + {0x2Eu, 0x0Cu}, + {0x31u, 0x0Cu}, + {0x33u, 0x02u}, + {0x35u, 0x01u}, + {0x36u, 0xFFu}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x84u, 0x50u}, + {0x85u, 0x30u}, + {0x86u, 0xA0u}, + {0x87u, 0xC0u}, + {0x88u, 0xFFu}, + {0x8Bu, 0xFFu}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0xFFu}, + {0x90u, 0x03u}, + {0x91u, 0x90u}, + {0x92u, 0x0Cu}, + {0x93u, 0x60u}, + {0x94u, 0x06u}, + {0x95u, 0x0Fu}, + {0x96u, 0x09u}, + {0x97u, 0xF0u}, + {0x98u, 0x30u}, + {0x99u, 0x09u}, + {0x9Au, 0xC0u}, + {0x9Bu, 0x06u}, + {0x9Cu, 0x60u}, + {0x9Du, 0x05u}, + {0x9Eu, 0x90u}, + {0x9Fu, 0x0Au}, + {0xA0u, 0x05u}, + {0xA2u, 0x0Au}, + {0xA3u, 0xFFu}, + {0xA8u, 0x0Fu}, + {0xA9u, 0x50u}, + {0xAAu, 0xF0u}, + {0xABu, 0xA0u}, + {0xADu, 0x03u}, + {0xAEu, 0xFFu}, + {0xAFu, 0x0Cu}, + {0xB1u, 0xFFu}, + {0xB4u, 0xFFu}, + {0xBEu, 0x10u}, + {0xBFu, 0x01u}, {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x01u, 0x60u}, - {0x03u, 0x20u}, - {0x04u, 0x80u}, - {0x05u, 0x10u}, - {0x06u, 0x01u}, - {0x07u, 0x40u}, - {0x09u, 0x08u}, - {0x0Au, 0x48u}, - {0x0Bu, 0x01u}, - {0x0Du, 0x18u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x80u}, - {0x10u, 0x82u}, - {0x14u, 0x02u}, - {0x15u, 0x04u}, - {0x16u, 0x08u}, - {0x18u, 0x09u}, - {0x1Au, 0x4Au}, - {0x1Bu, 0x40u}, - {0x1Cu, 0x02u}, - {0x1Du, 0x50u}, - {0x1Eu, 0x01u}, - {0x1Fu, 0x40u}, - {0x21u, 0x21u}, - {0x22u, 0x40u}, - {0x23u, 0x30u}, - {0x25u, 0x10u}, - {0x27u, 0x80u}, - {0x28u, 0x80u}, - {0x29u, 0x40u}, - {0x2Au, 0x18u}, - {0x2Eu, 0x04u}, - {0x2Fu, 0x4Au}, - {0x31u, 0x28u}, - {0x32u, 0x01u}, - {0x33u, 0x48u}, - {0x35u, 0x20u}, - {0x37u, 0x88u}, - {0x39u, 0x02u}, - {0x3Au, 0x04u}, - {0x3Bu, 0x50u}, + {0x00u, 0x90u}, + {0x01u, 0x84u}, + {0x04u, 0x10u}, + {0x05u, 0x80u}, + {0x06u, 0x20u}, + {0x08u, 0x98u}, + {0x0Au, 0x80u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x22u}, + {0x0Fu, 0x04u}, + {0x10u, 0x01u}, + {0x11u, 0x51u}, + {0x14u, 0x88u}, + {0x16u, 0x02u}, + {0x1Bu, 0x80u}, + {0x1Fu, 0x20u}, + {0x20u, 0x04u}, + {0x21u, 0x10u}, + {0x22u, 0x05u}, + {0x26u, 0x02u}, + {0x28u, 0x08u}, + {0x2Du, 0x51u}, + {0x2Eu, 0x22u}, + {0x30u, 0x10u}, + {0x33u, 0x01u}, + {0x34u, 0x98u}, + {0x35u, 0x40u}, + {0x36u, 0x11u}, + {0x37u, 0x01u}, + {0x39u, 0x28u}, + {0x3Cu, 0x90u}, {0x3Du, 0x04u}, - {0x3Eu, 0x10u}, - {0x58u, 0x40u}, - {0x5Fu, 0x80u}, - {0x62u, 0x40u}, - {0x68u, 0x02u}, - {0x83u, 0x14u}, - {0x87u, 0x20u}, - {0x88u, 0x01u}, - {0x89u, 0x20u}, - {0x8Au, 0x08u}, - {0x8Cu, 0x24u}, - {0x91u, 0x61u}, - {0x92u, 0x30u}, - {0x93u, 0x41u}, - {0x94u, 0x20u}, - {0x95u, 0x06u}, - {0x96u, 0xC3u}, - {0x97u, 0x80u}, - {0x98u, 0x48u}, - {0x9Au, 0x05u}, - {0x9Bu, 0x50u}, - {0x9Du, 0x30u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x05u}, - {0xA0u, 0xA0u}, - {0xA1u, 0x48u}, - {0xA2u, 0x20u}, - {0xA3u, 0x02u}, - {0xA4u, 0x01u}, - {0xA5u, 0x30u}, - {0xA7u, 0x41u}, - {0xA8u, 0x02u}, - {0xAAu, 0x42u}, - {0xABu, 0x40u}, - {0xAEu, 0x04u}, - {0xAFu, 0x80u}, - {0xB5u, 0x10u}, - {0xB6u, 0x80u}, - {0xC0u, 0xDFu}, + {0x3Fu, 0x04u}, + {0x5Fu, 0x40u}, + {0x60u, 0x04u}, + {0x63u, 0x08u}, + {0x69u, 0x16u}, + {0x6Au, 0x80u}, + {0x6Bu, 0x01u}, + {0x70u, 0xA2u}, + {0x73u, 0x10u}, + {0x80u, 0x02u}, + {0x84u, 0x40u}, + {0x8Au, 0x40u}, + {0x8Bu, 0x40u}, + {0x90u, 0x10u}, + {0x93u, 0x80u}, + {0x95u, 0x52u}, + {0x96u, 0x20u}, + {0x97u, 0x16u}, + {0x98u, 0x20u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x8Cu}, + {0x9Du, 0x20u}, + {0x9Eu, 0x50u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x04u}, + {0xA1u, 0x40u}, + {0xA2u, 0x10u}, + {0xA4u, 0xA2u}, + {0xAAu, 0x08u}, + {0xACu, 0x01u}, + {0xAEu, 0x22u}, + {0xAFu, 0x20u}, + {0xB4u, 0x04u}, + {0xB7u, 0x80u}, + {0xC0u, 0xE7u}, {0xC2u, 0xFFu}, - {0xC4u, 0xE9u}, - {0xCAu, 0xFFu}, - {0xCCu, 0x7Fu}, - {0xCEu, 0x6Fu}, - {0xD6u, 0x18u}, - {0xD8u, 0x08u}, - {0xE0u, 0x04u}, - {0xE2u, 0x01u}, - {0xE4u, 0x08u}, - {0xE8u, 0x05u}, - {0xEAu, 0x12u}, - {0xECu, 0x80u}, - {0xEEu, 0x09u}, - {0x00u, 0x55u}, - {0x02u, 0xAAu}, - {0x0Au, 0xFFu}, - {0x0Eu, 0xFFu}, - {0x0Fu, 0x12u}, - {0x10u, 0xFFu}, - {0x13u, 0x01u}, - {0x14u, 0xFFu}, - {0x17u, 0x0Cu}, - {0x18u, 0x0Fu}, - {0x19u, 0x24u}, - {0x1Au, 0xF0u}, - {0x1Bu, 0x03u}, - {0x20u, 0x69u}, - {0x22u, 0x96u}, - {0x24u, 0x33u}, - {0x25u, 0x28u}, - {0x26u, 0xCCu}, - {0x27u, 0x03u}, - {0x29u, 0x21u}, - {0x2Bu, 0x02u}, - {0x2Eu, 0xFFu}, - {0x31u, 0x10u}, + {0xC4u, 0xDBu}, + {0xCAu, 0xB4u}, + {0xCCu, 0xF5u}, + {0xCEu, 0x76u}, + {0xD6u, 0x10u}, + {0xE0u, 0x20u}, + {0xE4u, 0x80u}, + {0xE6u, 0x11u}, + {0xECu, 0x10u}, + {0xEEu, 0x42u}, + {0x03u, 0x13u}, + {0x06u, 0xFFu}, + {0x08u, 0xFFu}, + {0x0Bu, 0x10u}, + {0x0Cu, 0x90u}, + {0x0Eu, 0x60u}, + {0x0Fu, 0x0Cu}, + {0x11u, 0x13u}, + {0x13u, 0x08u}, + {0x14u, 0x09u}, + {0x16u, 0x06u}, + {0x18u, 0x30u}, + {0x19u, 0x01u}, + {0x1Au, 0xC0u}, + {0x1Bu, 0x02u}, + {0x1Cu, 0x03u}, + {0x1Du, 0x03u}, + {0x1Eu, 0x0Cu}, + {0x20u, 0x05u}, + {0x22u, 0x0Au}, + {0x23u, 0x03u}, + {0x24u, 0x0Fu}, + {0x25u, 0x10u}, + {0x26u, 0xF0u}, + {0x27u, 0x07u}, + {0x28u, 0x50u}, + {0x2Au, 0xA0u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0xFFu}, + {0x2Du, 0x01u}, + {0x2Fu, 0x02u}, {0x33u, 0x20u}, {0x34u, 0xFFu}, - {0x35u, 0x0Fu}, - {0x3Au, 0x20u}, - {0x3Fu, 0x04u}, + {0x35u, 0x03u}, + {0x37u, 0x1Cu}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, - {0x82u, 0x09u}, - {0x83u, 0x40u}, - {0x84u, 0x01u}, - {0x86u, 0x02u}, - {0x8Bu, 0x80u}, - {0x8Cu, 0x02u}, - {0x8Eu, 0x01u}, + {0x87u, 0x02u}, + {0x88u, 0x03u}, + {0x8Au, 0x0Cu}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x06u}, + {0x8Eu, 0x09u}, {0x8Fu, 0x01u}, - {0x91u, 0x03u}, - {0x93u, 0x0Cu}, - {0x94u, 0x02u}, - {0x96u, 0x01u}, - {0x97u, 0x30u}, - {0x98u, 0x10u}, - {0x99u, 0x02u}, - {0x9Cu, 0x10u}, - {0x9Fu, 0x07u}, - {0xA0u, 0x02u}, - {0xA1u, 0x04u}, - {0xA2u, 0x05u}, - {0xA4u, 0x10u}, - {0xA5u, 0x4Du}, - {0xA7u, 0x22u}, - {0xA9u, 0x48u}, - {0xABu, 0x17u}, - {0xACu, 0x10u}, - {0xADu, 0x0Bu}, - {0xAFu, 0x44u}, - {0xB0u, 0x04u}, - {0xB1u, 0x0Fu}, - {0xB2u, 0x08u}, - {0xB3u, 0x70u}, - {0xB4u, 0x03u}, - {0xB5u, 0x80u}, - {0xB6u, 0x10u}, - {0xB8u, 0x80u}, - {0xBAu, 0x20u}, - {0xBBu, 0x02u}, - {0xBEu, 0x40u}, - {0xD6u, 0x08u}, + {0x93u, 0x04u}, + {0x94u, 0x0Fu}, + {0x96u, 0xF0u}, + {0x97u, 0x20u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x05u}, + {0x9Eu, 0x0Au}, + {0x9Fu, 0x40u}, + {0xA4u, 0x60u}, + {0xA6u, 0x90u}, + {0xA8u, 0x50u}, + {0xA9u, 0x25u}, + {0xAAu, 0xA0u}, + {0xABu, 0x4Au}, + {0xACu, 0x30u}, + {0xAEu, 0xC0u}, + {0xB1u, 0x03u}, + {0xB2u, 0xFFu}, + {0xB3u, 0x60u}, + {0xB5u, 0x10u}, + {0xB7u, 0x0Cu}, + {0xBEu, 0x04u}, + {0xBFu, 0x45u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x90u}, + {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x01u, 0x82u}, - {0x03u, 0x20u}, - {0x04u, 0x01u}, - {0x05u, 0x60u}, - {0x08u, 0x20u}, - {0x09u, 0x40u}, - {0x0Au, 0x20u}, - {0x0Cu, 0x04u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0xA0u}, - {0x10u, 0x20u}, - {0x11u, 0x40u}, - {0x13u, 0x01u}, - {0x16u, 0x50u}, - {0x17u, 0x40u}, - {0x18u, 0x20u}, - {0x19u, 0x02u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x20u}, - {0x1Eu, 0x04u}, - {0x20u, 0x08u}, - {0x21u, 0x02u}, - {0x22u, 0x04u}, - {0x26u, 0x02u}, - {0x27u, 0x28u}, - {0x29u, 0x60u}, - {0x2Bu, 0x50u}, - {0x2Fu, 0x18u}, - {0x31u, 0x02u}, - {0x32u, 0x24u}, - {0x33u, 0x40u}, - {0x35u, 0x08u}, - {0x36u, 0x02u}, - {0x37u, 0x18u}, - {0x38u, 0x80u}, - {0x39u, 0x11u}, - {0x3Cu, 0x80u}, - {0x49u, 0x40u}, - {0x4Bu, 0x80u}, - {0x58u, 0x40u}, - {0x59u, 0x10u}, - {0x60u, 0x03u}, - {0x62u, 0x10u}, - {0x6Du, 0x04u}, - {0x6Eu, 0x60u}, - {0x80u, 0x10u}, - {0x81u, 0xC2u}, - {0x86u, 0x11u}, - {0x8Au, 0x04u}, - {0x8Du, 0x10u}, - {0x90u, 0x80u}, - {0x91u, 0x11u}, - {0x92u, 0x22u}, - {0x93u, 0x81u}, - {0x94u, 0x20u}, - {0x95u, 0x04u}, - {0x96u, 0x04u}, - {0x98u, 0x28u}, - {0x9Au, 0x40u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x20u}, - {0x9Eu, 0x10u}, - {0xA0u, 0x20u}, - {0xA1u, 0x48u}, - {0xA2u, 0x20u}, - {0xA3u, 0x40u}, - {0xA7u, 0x21u}, - {0xA8u, 0x80u}, - {0xAAu, 0x40u}, - {0xAFu, 0x29u}, - {0xB1u, 0x18u}, - {0xB4u, 0x01u}, - {0xC0u, 0xDDu}, - {0xC2u, 0x77u}, - {0xC4u, 0xBDu}, - {0xCAu, 0x6Fu}, - {0xCCu, 0xEFu}, - {0xCEu, 0x1Du}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x0Cu}, - {0xE0u, 0x08u}, - {0xE6u, 0x05u}, - {0xEAu, 0x09u}, - {0x82u, 0x80u}, - {0x89u, 0x08u}, - {0x9Du, 0x08u}, - {0xA2u, 0x80u}, - {0xA7u, 0x08u}, - {0xADu, 0x08u}, - {0xAEu, 0x04u}, - {0xAFu, 0x92u}, - {0xB1u, 0x20u}, - {0xB2u, 0x14u}, - {0xB3u, 0x02u}, - {0xB4u, 0x80u}, - {0xB7u, 0x20u}, - {0xE0u, 0x88u}, - {0xE2u, 0x40u}, - {0xE6u, 0x01u}, - {0xEAu, 0x81u}, - {0xECu, 0x38u}, + {0x00u, 0x80u}, {0x02u, 0x04u}, - {0x05u, 0x08u}, - {0x06u, 0x08u}, - {0x07u, 0x05u}, - {0x0Cu, 0x2Au}, - {0x0Du, 0x08u}, - {0x0Eu, 0x54u}, + {0x03u, 0x02u}, + {0x04u, 0x10u}, + {0x07u, 0x21u}, + {0x08u, 0x08u}, + {0x09u, 0x40u}, + {0x0Du, 0x40u}, + {0x0Eu, 0x20u}, {0x0Fu, 0x04u}, - {0x12u, 0x01u}, - {0x15u, 0x04u}, + {0x10u, 0x22u}, + {0x13u, 0x10u}, + {0x14u, 0x80u}, + {0x15u, 0x10u}, {0x16u, 0x02u}, {0x17u, 0x08u}, - {0x19u, 0x08u}, - {0x1Au, 0x40u}, - {0x1Bu, 0x06u}, - {0x1Du, 0x08u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x14u}, - {0x22u, 0x10u}, - {0x30u, 0x06u}, - {0x31u, 0x02u}, - {0x32u, 0x01u}, - {0x33u, 0x0Cu}, - {0x34u, 0x18u}, - {0x35u, 0x10u}, - {0x36u, 0x60u}, - {0x37u, 0x01u}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x51u}, + {0x18u, 0x10u}, + {0x1Cu, 0x08u}, + {0x20u, 0x24u}, + {0x23u, 0x42u}, + {0x25u, 0x60u}, + {0x26u, 0x20u}, + {0x27u, 0x10u}, + {0x28u, 0x08u}, + {0x2Du, 0x20u}, + {0x2Eu, 0x09u}, + {0x2Fu, 0x81u}, + {0x30u, 0xA0u}, + {0x31u, 0x08u}, + {0x33u, 0x02u}, + {0x34u, 0x01u}, + {0x36u, 0x20u}, + {0x37u, 0x80u}, + {0x39u, 0xC0u}, + {0x3Au, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x02u}, + {0x58u, 0x04u}, + {0x59u, 0x80u}, + {0x5Au, 0x21u}, + {0x5Cu, 0x08u}, + {0x5Fu, 0x08u}, + {0x60u, 0x02u}, + {0x80u, 0x02u}, + {0x81u, 0x20u}, + {0x87u, 0x40u}, + {0x88u, 0x10u}, + {0x8Bu, 0x82u}, + {0x8Eu, 0x44u}, + {0x93u, 0x80u}, + {0x94u, 0x04u}, + {0x95u, 0x02u}, + {0x96u, 0x80u}, + {0x98u, 0x21u}, + {0x99u, 0x80u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0x40u}, + {0xA0u, 0x41u}, + {0xA1u, 0x08u}, + {0xA2u, 0x10u}, + {0xA3u, 0x01u}, + {0xA4u, 0x80u}, + {0xACu, 0x20u}, + {0xB4u, 0x20u}, + {0xB6u, 0x04u}, + {0xC0u, 0xE3u}, + {0xC2u, 0xE5u}, + {0xC4u, 0xF7u}, + {0xCAu, 0xF4u}, + {0xCCu, 0xBFu}, + {0xCEu, 0xBEu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, + {0xE0u, 0x80u}, + {0xE4u, 0x12u}, + {0xEAu, 0x10u}, + {0xECu, 0x10u}, + {0xEEu, 0x80u}, + {0x00u, 0x02u}, + {0x01u, 0x08u}, + {0x02u, 0x11u}, + {0x03u, 0x04u}, + {0x04u, 0x02u}, + {0x05u, 0x02u}, + {0x06u, 0x01u}, + {0x07u, 0x01u}, + {0x10u, 0x02u}, + {0x12u, 0x01u}, + {0x14u, 0x02u}, + {0x15u, 0x01u}, + {0x16u, 0x01u}, + {0x17u, 0x02u}, + {0x18u, 0x02u}, + {0x1Au, 0x05u}, + {0x1Bu, 0x20u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x04u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x08u}, + {0x20u, 0x02u}, + {0x22u, 0x01u}, + {0x23u, 0x10u}, + {0x29u, 0x03u}, + {0x2Bu, 0x0Cu}, + {0x2Cu, 0x02u}, + {0x2Eu, 0x09u}, + {0x30u, 0x10u}, + {0x31u, 0x10u}, + {0x32u, 0x08u}, + {0x33u, 0x20u}, + {0x34u, 0x04u}, + {0x36u, 0x03u}, + {0x37u, 0x0Fu}, + {0x3Au, 0x80u}, + {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -1182,899 +1508,810 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0xFFu}, - {0x89u, 0x04u}, - {0x8Au, 0xFFu}, - {0x8Bu, 0x03u}, - {0x91u, 0x04u}, - {0x93u, 0x0Au}, - {0x94u, 0x0Fu}, - {0x95u, 0x02u}, - {0x96u, 0xF0u}, - {0x97u, 0x04u}, - {0x98u, 0xFFu}, - {0x99u, 0x04u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x33u}, - {0x9Eu, 0xCCu}, - {0xA0u, 0x96u}, - {0xA2u, 0x69u}, - {0xA6u, 0xFFu}, - {0xA9u, 0x04u}, - {0xAAu, 0xFFu}, - {0xABu, 0x02u}, - {0xACu, 0x55u}, - {0xAEu, 0xAAu}, - {0xB0u, 0xFFu}, - {0xB3u, 0x06u}, - {0xB5u, 0x08u}, - {0xB7u, 0x01u}, - {0xBAu, 0x02u}, - {0xBBu, 0x08u}, + {0x83u, 0x80u}, + {0x86u, 0x01u}, + {0x8Au, 0x80u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x98u}, + {0x8Eu, 0x22u}, + {0x91u, 0x24u}, + {0x92u, 0x06u}, + {0x93u, 0x09u}, + {0x96u, 0x60u}, + {0x97u, 0x58u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x03u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x10u}, + {0xA2u, 0x88u}, + {0xA3u, 0x24u}, + {0xA7u, 0x20u}, + {0xA9u, 0x40u}, + {0xABu, 0x80u}, + {0xACu, 0x98u}, + {0xADu, 0x24u}, + {0xAEu, 0x44u}, + {0xAFu, 0x12u}, + {0xB0u, 0x0Eu}, + {0xB1u, 0xC0u}, + {0xB2u, 0xE0u}, + {0xB3u, 0x07u}, + {0xB4u, 0x01u}, + {0xB5u, 0x38u}, + {0xB6u, 0x10u}, + {0xBEu, 0x40u}, + {0xBFu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x01u, 0x48u}, - {0x05u, 0x20u}, - {0x07u, 0x20u}, - {0x09u, 0x04u}, - {0x0Au, 0x80u}, - {0x0Bu, 0x05u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x12u}, - {0x10u, 0x80u}, - {0x14u, 0x02u}, - {0x15u, 0x14u}, - {0x16u, 0x40u}, - {0x19u, 0x01u}, - {0x1Au, 0x28u}, - {0x1Bu, 0x80u}, - {0x1Fu, 0x02u}, - {0x20u, 0x40u}, - {0x21u, 0x88u}, - {0x22u, 0x20u}, - {0x24u, 0x10u}, - {0x26u, 0x18u}, - {0x27u, 0x01u}, - {0x2Fu, 0x08u}, - {0x31u, 0x88u}, - {0x32u, 0x20u}, - {0x36u, 0x18u}, - {0x37u, 0x01u}, - {0x38u, 0x44u}, - {0x3Fu, 0x20u}, - {0x58u, 0x94u}, - {0x5Cu, 0x10u}, - {0x5Fu, 0x8Au}, - {0x60u, 0x04u}, - {0x62u, 0x40u}, - {0x63u, 0x20u}, - {0x65u, 0x40u}, - {0x80u, 0x40u}, - {0x83u, 0x89u}, - {0x85u, 0x40u}, - {0x88u, 0x04u}, - {0x89u, 0x14u}, - {0x8Du, 0x15u}, - {0x90u, 0x80u}, - {0x91u, 0x40u}, - {0x92u, 0x80u}, - {0x93u, 0x04u}, - {0x96u, 0x20u}, - {0x98u, 0x12u}, - {0x99u, 0x30u}, - {0x9Du, 0x0Cu}, - {0xA0u, 0x81u}, - {0xA1u, 0x04u}, - {0xA2u, 0x80u}, - {0xA3u, 0x01u}, - {0xA8u, 0x01u}, - {0xA9u, 0x24u}, - {0xAAu, 0x04u}, - {0xABu, 0x41u}, - {0xACu, 0x01u}, - {0xADu, 0x10u}, - {0xAFu, 0x80u}, - {0xB0u, 0x10u}, - {0xB2u, 0x02u}, - {0xB3u, 0x10u}, - {0xB4u, 0x40u}, - {0xB6u, 0x20u}, - {0xC0u, 0x6Du}, - {0xC2u, 0xEFu}, - {0xC4u, 0xF8u}, - {0xCAu, 0x20u}, - {0xCCu, 0xEEu}, - {0xCEu, 0x2Au}, - {0xD6u, 0xFEu}, - {0xD8u, 0x1Eu}, - {0xE0u, 0xB0u}, - {0xE2u, 0x40u}, - {0xE4u, 0x04u}, - {0xEAu, 0x10u}, - {0xECu, 0x84u}, - {0x01u, 0xFFu}, - {0x04u, 0x03u}, - {0x05u, 0x03u}, - {0x06u, 0x0Cu}, - {0x07u, 0x0Cu}, - {0x09u, 0x30u}, - {0x0Au, 0xFFu}, - {0x0Bu, 0xC0u}, - {0x0Cu, 0x05u}, - {0x0Du, 0x06u}, - {0x0Eu, 0x0Au}, - {0x0Fu, 0x09u}, - {0x10u, 0x09u}, - {0x12u, 0x06u}, - {0x14u, 0x90u}, - {0x16u, 0x60u}, - {0x17u, 0xFFu}, - {0x18u, 0x50u}, - {0x1Au, 0xA0u}, - {0x1Bu, 0xFFu}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0xFFu}, - {0x1Fu, 0xF0u}, - {0x20u, 0x0Fu}, - {0x21u, 0x60u}, - {0x22u, 0xF0u}, - {0x23u, 0x90u}, - {0x25u, 0x50u}, - {0x26u, 0xFFu}, - {0x27u, 0xA0u}, - {0x28u, 0x30u}, - {0x2Au, 0xC0u}, - {0x2Du, 0x05u}, - {0x2Fu, 0x0Au}, - {0x30u, 0xFFu}, - {0x37u, 0xFFu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x81u, 0x08u}, - {0x83u, 0x50u}, - {0x88u, 0x20u}, - {0x8Au, 0x10u}, - {0x8Cu, 0x01u}, - {0x8Eu, 0x02u}, - {0x90u, 0x20u}, - {0x91u, 0x26u}, - {0x92u, 0x10u}, - {0x93u, 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{0x19u, 0x29u}, - {0x1Au, 0x2Fu}, - {0x1Bu, 0x46u}, + {0x13u, 0x64u}, + {0x15u, 0x11u}, + {0x19u, 0x0Cu}, + {0x1Fu, 0x11u}, + {0x21u, 0x11u}, + {0x25u, 0x02u}, + {0x27u, 0xA8u}, + {0x29u, 0xC4u}, + {0x2Bu, 0x02u}, + {0x2Fu, 0x01u}, + {0x31u, 0xE0u}, + {0x33u, 0x01u}, + {0x35u, 0x0Eu}, + {0x37u, 0x10u}, + {0x39u, 0x20u}, + {0x3Fu, 0x44u}, + {0x40u, 0x36u}, + {0x41u, 0x04u}, + {0x42u, 0x10u}, + {0x44u, 0x05u}, + {0x45u, 0xCEu}, + {0x46u, 0xFDu}, + {0x47u, 0x0Bu}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x22u}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x08u}, + {0x50u, 0x04u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Fu, 0x01u}, + {0x62u, 0xC0u}, + {0x64u, 0x40u}, + {0x65u, 0x01u}, + {0x66u, 0x10u}, + {0x67u, 0x11u}, + {0x68u, 0xC0u}, + {0x69u, 0x01u}, + {0x6Bu, 0x11u}, + {0x6Cu, 0x40u}, + {0x6Du, 0x01u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x80u, 0x07u}, + {0x81u, 0x6Cu}, + {0x82u, 0x18u}, + {0x84u, 0x04u}, + {0x85u, 0x64u}, + {0x87u, 0x08u}, + {0x88u, 0x10u}, + {0x8Au, 0x40u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x2Cu}, + {0x8Fu, 0x40u}, + {0x90u, 0x01u}, + {0x91u, 0xA4u}, + {0x93u, 0x40u}, + {0x95u, 0x91u}, + {0x97u, 0x4Eu}, + {0x98u, 0x01u}, + {0x99u, 0xC0u}, + {0x9Bu, 0x2Fu}, + {0x9Cu, 0x01u}, + {0x9Du, 0x08u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x01u}, + {0xA1u, 0x6Cu}, + {0xA4u, 0x08u}, + {0xA6u, 0x21u}, + {0xA8u, 0x22u}, + {0xA9u, 0x40u}, + {0xAAu, 0x08u}, + {0xABu, 0x2Cu}, + {0xADu, 0x71u}, + {0xAFu, 0x82u}, + {0xB0u, 0x3Fu}, + {0xB1u, 0xC0u}, + {0xB3u, 0x31u}, + {0xB4u, 0x40u}, + {0xB7u, 0x0Fu}, + {0xB8u, 0x02u}, + {0xBBu, 0x0Eu}, + {0xBEu, 0x01u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x04u, 0x02u}, + {0x06u, 0x06u}, + {0x07u, 0x20u}, + {0x0Eu, 0x46u}, + {0x14u, 0x04u}, + {0x15u, 0x01u}, + {0x17u, 0x18u}, {0x1Cu, 0x08u}, - {0x1Du, 0xD6u}, - {0x1Eu, 0x10u}, - {0x20u, 0x6Cu}, + {0x1Fu, 0x01u}, + {0x20u, 0x11u}, + {0x22u, 0x10u}, + {0x23u, 0x40u}, + {0x24u, 0x02u}, + {0x25u, 0x40u}, + {0x26u, 0x05u}, + {0x27u, 0x51u}, + {0x28u, 0x24u}, + {0x2Au, 0x42u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x90u}, + {0x32u, 0x54u}, + {0x33u, 0x01u}, + {0x36u, 0x81u}, + {0x37u, 0x18u}, + {0x39u, 0x21u}, + {0x3Bu, 0x40u}, + {0x3Eu, 0x46u}, + {0x40u, 0x21u}, + {0x42u, 0x80u}, + {0x43u, 0x05u}, + {0x48u, 0x80u}, + {0x4Au, 0x86u}, + {0x4Bu, 0x04u}, + {0x51u, 0x20u}, + {0x52u, 0x44u}, + {0x53u, 0x04u}, + {0x60u, 0x90u}, + {0x61u, 0x20u}, + {0x62u, 0x40u}, + {0x80u, 0x01u}, + {0x84u, 0x80u}, + {0x8Bu, 0x40u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x10u}, + {0x91u, 0x21u}, + {0x92u, 0xDCu}, + {0x94u, 0x03u}, + {0x96u, 0x20u}, + {0x97u, 0x0Eu}, + {0x9Au, 0x02u}, + {0x9Bu, 0x2Cu}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x51u}, + {0xA4u, 0x84u}, + {0xA5u, 0x40u}, + {0xA6u, 0x01u}, + {0xA9u, 0x08u}, + {0xAAu, 0x02u}, + {0xACu, 0xC0u}, + {0xADu, 0x40u}, + {0xB0u, 0x80u}, + {0xB3u, 0x10u}, + {0xB5u, 0x04u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xD0u}, + {0xC4u, 0x70u}, + {0xCAu, 0xBFu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xDDu}, + {0xD0u, 0x0Bu}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x0Fu}, + {0xE2u, 0x20u}, + {0xE4u, 0x14u}, + {0xEAu, 0x02u}, + {0xECu, 0x08u}, + {0xEEu, 0x02u}, + {0x00u, 0xFFu}, + {0x01u, 0xD6u}, + {0x04u, 0x0Fu}, + {0x05u, 0xD2u}, + {0x06u, 0xF0u}, + {0x07u, 0x04u}, + {0x09u, 0x20u}, + {0x0Bu, 0xD0u}, + {0x0Du, 0x17u}, + {0x0Eu, 0xFFu}, + {0x0Fu, 0x28u}, + {0x10u, 0x33u}, + {0x11u, 0x02u}, + {0x12u, 0xCCu}, + {0x14u, 0x96u}, + {0x15u, 0x29u}, + {0x16u, 0x69u}, + {0x17u, 0x46u}, + {0x19u, 0x21u}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x8Eu}, + {0x20u, 0x55u}, {0x21u, 0x04u}, - {0x25u, 0xD2u}, - {0x27u, 0x04u}, - {0x28u, 0x91u}, + {0x22u, 0xAAu}, + {0x25u, 0xD6u}, + {0x26u, 0xFFu}, + {0x28u, 0xFFu}, {0x29u, 0xD0u}, - {0x2Au, 0x4Eu}, {0x2Bu, 0x06u}, - {0x2Cu, 0x2Cu}, {0x2Du, 0xD6u}, - {0x2Eu, 0x40u}, - {0x30u, 0xC0u}, - {0x32u, 0x0Fu}, - {0x33u, 0x0Fu}, - {0x34u, 0x31u}, - {0x35u, 0xF0u}, + {0x31u, 0x01u}, + {0x33u, 0xF0u}, + {0x34u, 0xFFu}, + {0x35u, 0x0Fu}, {0x37u, 0x08u}, - {0x39u, 0x08u}, - {0x3Au, 0x32u}, - {0x3Bu, 0x20u}, - {0x3Fu, 0x40u}, + {0x39u, 0x20u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x08u}, + {0x3Fu, 0x41u}, {0x54u, 0x09u}, {0x56u, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x01u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, - {0x81u, 0x03u}, - {0x82u, 0x30u}, - {0x86u, 0x01u}, - {0x87u, 0x01u}, - {0x88u, 0x05u}, - {0x89u, 0x03u}, - {0x8Au, 0x38u}, - {0x8Cu, 0x10u}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x03u}, - {0x90u, 0x01u}, - {0x92u, 0x38u}, - {0x94u, 0x10u}, - {0x95u, 0x03u}, - {0x96u, 0x20u}, - {0x9Cu, 0x30u}, - {0x9Eu, 0x08u}, - {0xA8u, 0x34u}, - {0xAAu, 0x08u}, - {0xADu, 0x03u}, - {0xB0u, 0x30u}, - {0xB3u, 0x01u}, - {0xB4u, 0x0Fu}, - {0xB7u, 0x02u}, - {0xB8u, 0x20u}, - {0xBAu, 0x02u}, - {0xBFu, 0x44u}, - {0xD4u, 0x40u}, - {0xD6u, 0x04u}, + {0x87u, 0x20u}, + {0x89u, 0x24u}, + {0x8Bu, 0x09u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x18u}, + {0x97u, 0x04u}, + {0x9Bu, 0x40u}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x03u}, + {0xA5u, 0x24u}, + {0xA7u, 0x12u}, + {0xAFu, 0x24u}, + {0xB1u, 0x38u}, + {0xB2u, 0x02u}, + {0xB5u, 0x40u}, + {0xB6u, 0x01u}, + {0xB7u, 0x07u}, + {0xD6u, 0x02u}, + {0xD7u, 0x2Cu}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0x24u}, - {0x03u, 0x42u}, - {0x04u, 0x20u}, - {0x05u, 0x45u}, - {0x08u, 0x08u}, + {0x00u, 0x80u}, + {0x04u, 0x04u}, + {0x05u, 0x82u}, {0x0Au, 0x02u}, - {0x0Bu, 0x80u}, - {0x0Cu, 0x88u}, - {0x0Eu, 0x04u}, - {0x10u, 0x04u}, - {0x15u, 0x41u}, - {0x17u, 0x10u}, - {0x19u, 0x20u}, - {0x1Bu, 0x03u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x08u}, + {0x16u, 0xA8u}, + {0x19u, 0x44u}, + {0x1Au, 0x02u}, {0x1Cu, 0x04u}, - {0x1Du, 0x05u}, - {0x1Eu, 0x04u}, - {0x1Fu, 0x19u}, - {0x20u, 0x02u}, - {0x22u, 0x08u}, - {0x23u, 0x01u}, - {0x25u, 0x10u}, - {0x26u, 0x44u}, - {0x27u, 0x10u}, - {0x29u, 0x40u}, - {0x2Cu, 0x88u}, - {0x2Du, 0x40u}, - {0x2Fu, 0x20u}, + {0x20u, 0x40u}, + {0x21u, 0x20u}, + {0x22u, 0x80u}, + {0x24u, 0x10u}, + {0x25u, 0x01u}, + {0x26u, 0x40u}, + {0x27u, 0x0Cu}, + {0x29u, 0x80u}, + {0x2Au, 0x08u}, + {0x2Cu, 0x80u}, + {0x2Du, 0x08u}, + {0x2Eu, 0x50u}, {0x30u, 0x08u}, - {0x35u, 0x45u}, - {0x37u, 0x10u}, - {0x38u, 0x28u}, - {0x39u, 0x41u}, - {0x3Cu, 0x04u}, - {0x3Du, 0x21u}, - {0x4Cu, 0x04u}, - {0x4Du, 0x10u}, + {0x32u, 0xA0u}, + {0x36u, 0x01u}, + {0x37u, 0x18u}, + {0x38u, 0x60u}, + {0x39u, 0x04u}, + {0x3Cu, 0x10u}, + {0x3Du, 0x81u}, + {0x3Eu, 0x04u}, + {0x5Cu, 0x01u}, {0x5Eu, 0x80u}, - {0x5Fu, 0x15u}, - {0x61u, 0x02u}, - {0x62u, 0xA8u}, - {0x64u, 0x80u}, - {0x66u, 0x80u}, + {0x5Fu, 0x14u}, + {0x60u, 0x80u}, + {0x64u, 0x02u}, + {0x67u, 0x40u}, + {0x69u, 0x21u}, + {0x6Au, 0xDCu}, + {0x72u, 0x02u}, + {0x73u, 0x01u}, + {0x7Cu, 0x02u}, + {0x7Du, 0x02u}, + {0x80u, 0x40u}, + {0x82u, 0x20u}, + {0x85u, 0x20u}, + {0x86u, 0x80u}, + {0x87u, 0x40u}, + {0x8Au, 0x90u}, + {0x8Fu, 0x08u}, + {0x90u, 0x20u}, {0x91u, 0x04u}, - {0x92u, 0x02u}, - {0x93u, 0x80u}, - {0x97u, 0x20u}, - {0x98u, 0x0Cu}, - {0x99u, 0x08u}, - {0x9Bu, 0x60u}, - {0x9Cu, 0xC0u}, - {0x9Du, 0x20u}, - {0x9Fu, 0x10u}, - {0xA4u, 0x40u}, - {0xA7u, 0x09u}, - {0xAAu, 0x40u}, - {0xB0u, 0x04u}, - {0xB4u, 0x80u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xEDu}, - {0xC4u, 0xD2u}, - {0xCAu, 0xF8u}, - {0xCCu, 0xF2u}, - {0xCEu, 0xEFu}, + {0x94u, 0x06u}, + {0x95u, 0x01u}, + {0x96u, 0x74u}, + {0x97u, 0x0Bu}, + {0x99u, 0x82u}, + {0x9Au, 0x28u}, + {0x9Bu, 0x20u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x59u}, + {0xA0u, 0x08u}, + {0xA1u, 0x02u}, + {0xA3u, 0x04u}, + {0xA4u, 0x04u}, + {0xABu, 0x04u}, + {0xB0u, 0x40u}, + {0xB6u, 0x12u}, + {0xC0u, 0xB1u}, + {0xC2u, 0x71u}, + {0xC4u, 0x70u}, + {0xCAu, 0xFAu}, + {0xCCu, 0xEEu}, + {0xCEu, 0xFEu}, {0xD6u, 0xF0u}, - {0xD8u, 0x9Fu}, - {0xEAu, 0x12u}, - {0xEEu, 0x08u}, - {0xB8u, 0x08u}, - {0xBEu, 0x04u}, - {0xD8u, 0x04u}, - {0xDFu, 0x01u}, - {0x1Bu, 0x08u}, - {0xB3u, 0x08u}, - {0xE8u, 0x20u}, + {0xD8u, 0x91u}, + {0xE0u, 0x08u}, + {0xE4u, 0x0Cu}, + {0xE6u, 0x01u}, {0xEAu, 0x02u}, {0xEEu, 0x08u}, - {0xAFu, 0x08u}, + {0x00u, 0x02u}, + {0x02u, 0x01u}, + {0x04u, 0x02u}, + {0x05u, 0x08u}, + {0x06u, 0x01u}, + {0x08u, 0x02u}, + {0x0Au, 0x11u}, + {0x0Cu, 0x01u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x02u}, + {0x0Fu, 0x06u}, + {0x11u, 0x08u}, + {0x14u, 0x02u}, + {0x15u, 0x03u}, + {0x16u, 0x01u}, + {0x17u, 0x04u}, + {0x19u, 0x04u}, + {0x1Bu, 0x03u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x01u}, + {0x21u, 0x08u}, + {0x24u, 0x02u}, + {0x25u, 0x08u}, + {0x26u, 0x05u}, + {0x28u, 0x02u}, + {0x2Au, 0x09u}, + {0x2Du, 0x05u}, + {0x2Fu, 0x02u}, + {0x30u, 0x03u}, + {0x32u, 0x10u}, + {0x33u, 0x08u}, + {0x34u, 0x04u}, + {0x35u, 0x07u}, + {0x36u, 0x08u}, + {0x39u, 0x08u}, + {0x3Au, 0x02u}, + {0x3Bu, 0x20u}, + {0x3Fu, 0x04u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x01u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x81u, 0x02u}, + {0x82u, 0x08u}, + {0x83u, 0x01u}, + {0x85u, 0x02u}, + {0x87u, 0x05u}, + {0x89u, 0x02u}, + {0x8Au, 0x10u}, + {0x8Bu, 0x11u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x01u}, + {0x94u, 0x0Au}, + {0x95u, 0x02u}, + {0x96u, 0x14u}, + {0x97u, 0x09u}, + {0x99u, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x01u}, + {0xA9u, 0x02u}, + {0xAAu, 0x04u}, + {0xABu, 0x01u}, + {0xB0u, 0x01u}, + {0xB1u, 0x10u}, + {0xB2u, 0x18u}, + {0xB3u, 0x08u}, + {0xB4u, 0x06u}, + {0xB5u, 0x03u}, + {0xB7u, 0x04u}, + {0xBBu, 0x20u}, + {0xBEu, 0x14u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x19u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x82u}, + {0x01u, 0x10u}, + {0x03u, 0x01u}, + {0x04u, 0x08u}, + {0x05u, 0x12u}, + {0x07u, 0x01u}, + {0x08u, 0x08u}, + {0x09u, 0x40u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x02u}, + {0x13u, 0x10u}, + {0x16u, 0x20u}, + {0x17u, 0x10u}, + {0x19u, 0x04u}, + {0x1Au, 0x40u}, + {0x1Bu, 0x10u}, + {0x1Cu, 0x80u}, + {0x1Du, 0x18u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x02u}, + {0x20u, 0x10u}, + {0x21u, 0xA1u}, + {0x22u, 0x10u}, + {0x23u, 0x02u}, + {0x24u, 0x20u}, + {0x26u, 0x20u}, + {0x2Bu, 0x04u}, + {0x2Du, 0x80u}, + {0x2Fu, 0xA0u}, + {0x31u, 0xA0u}, + {0x32u, 0x04u}, + {0x36u, 0x2Au}, + {0x38u, 0x14u}, + {0x39u, 0x02u}, + {0x3Bu, 0x80u}, + {0x3Cu, 0x48u}, + {0x58u, 0x20u}, + {0x5Bu, 0x40u}, + {0x5Fu, 0x60u}, + {0x60u, 0x04u}, + {0x63u, 0x02u}, + {0x64u, 0x01u}, + {0x66u, 0x20u}, + {0x67u, 0x02u}, + {0x80u, 0x10u}, + {0x81u, 0x40u}, + {0x83u, 0x02u}, + {0x84u, 0x01u}, + {0x85u, 0x44u}, + {0x87u, 0x40u}, + {0x88u, 0x01u}, + {0x8Bu, 0x41u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x40u}, + {0x91u, 0x10u}, + {0x92u, 0x0Au}, + {0x93u, 0x10u}, + {0x95u, 0x48u}, + {0x96u, 0x60u}, + {0x97u, 0x02u}, + {0x98u, 0x28u}, + {0x9Bu, 0x30u}, + {0x9Du, 0x60u}, + {0xA0u, 0x04u}, + {0xA1u, 0x40u}, + {0xA2u, 0x02u}, + {0xA3u, 0xA4u}, + {0xA7u, 0x12u}, + {0xB2u, 0x10u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xA5u}, + {0xC4u, 0x62u}, + {0xCAu, 0xD4u}, + {0xCCu, 0xEEu}, + {0xCEu, 0x5Fu}, + {0xD6u, 0x3Cu}, + {0xD8u, 0x3Cu}, + {0xE0u, 0x04u}, {0xE2u, 0x80u}, - {0x06u, 0x02u}, - {0x0Du, 0x20u}, - {0x12u, 0x08u}, - {0x13u, 0x02u}, + {0xE4u, 0x40u}, + {0xE6u, 0x20u}, + {0xEAu, 0x02u}, + {0xECu, 0x20u}, + {0xEEu, 0x08u}, + {0x80u, 0x40u}, + {0x86u, 0x01u}, + {0x8Du, 0x80u}, + {0x92u, 0x02u}, + {0x94u, 0x40u}, + {0x9Du, 0x80u}, + {0xA9u, 0x04u}, + {0xADu, 0x0Au}, + {0xAEu, 0x20u}, + {0xB4u, 0x04u}, + {0xB5u, 0x20u}, + {0xE4u, 0x42u}, + {0xE8u, 0x10u}, + {0xECu, 0x01u}, + {0x04u, 0x80u}, + {0x0Eu, 0x08u}, + {0x13u, 0x42u}, {0x16u, 0x80u}, - {0x17u, 0x80u}, + {0x17u, 0x40u}, {0x30u, 0x10u}, {0x33u, 0x01u}, - {0x36u, 0x20u}, - {0x37u, 0x04u}, - {0x39u, 0x04u}, - {0x3Au, 0x80u}, - {0x3Cu, 0x01u}, - {0x3Du, 0x10u}, - {0x40u, 0x02u}, - {0x5Bu, 0x08u}, + {0x35u, 0x01u}, + {0x37u, 0x80u}, + {0x3Au, 0x82u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x04u}, + {0x42u, 0x08u}, + {0x67u, 0x80u}, {0x6Bu, 0x03u}, - {0x89u, 0x10u}, {0xC0u, 0x80u}, {0xC2u, 0x80u}, {0xC4u, 0xF0u}, {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD6u, 0x40u}, - {0x33u, 0x11u}, - {0x36u, 0x01u}, - {0x37u, 0x80u}, + {0xD8u, 0x80u}, + {0x32u, 0x20u}, + {0x33u, 0x01u}, + {0x37u, 0x44u}, {0x39u, 0x80u}, - {0x5Au, 0x10u}, - {0x5Eu, 0x80u}, - {0x63u, 0x02u}, - {0x8Au, 0x40u}, - {0x94u, 0x01u}, - {0x9Bu, 0x90u}, - {0x9Cu, 0x12u}, - {0x9Fu, 0x08u}, - {0xA1u, 0x20u}, - {0xA6u, 0x20u}, - {0xAAu, 0x08u}, - {0xABu, 0x14u}, - {0xADu, 0x04u}, + {0x5Bu, 0x20u}, + {0x5Cu, 0x10u}, + {0x67u, 0x08u}, + {0x82u, 0x04u}, + {0x8Bu, 0x40u}, + {0x90u, 0x80u}, + {0x95u, 0x04u}, + {0x97u, 0x80u}, + {0x9Bu, 0x40u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x08u}, + {0xA2u, 0x24u}, + {0xABu, 0x80u}, + {0xAEu, 0x20u}, + {0xAFu, 0x40u}, + {0xB0u, 0x40u}, {0xB6u, 0x02u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0x80u}, - {0xD6u, 0x60u}, + {0xD6u, 0x20u}, + {0xD8u, 0x80u}, + {0xE4u, 0x20u}, {0xEAu, 0x80u}, - {0xEEu, 0x40u}, {0x10u, 0x10u}, - {0x31u, 0x40u}, - {0x94u, 0x01u}, - {0x95u, 0x80u}, - {0x96u, 0x10u}, - {0x9Cu, 0x12u}, - {0x9Fu, 0x09u}, - {0xA6u, 0x01u}, - {0xA7u, 0x01u}, - {0xB1u, 0x20u}, - {0xB6u, 0x20u}, + {0x33u, 0x80u}, + {0x8Du, 0x40u}, + {0x90u, 0x80u}, + {0x95u, 0x84u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x05u}, + {0xAFu, 0x24u}, + {0xB4u, 0x10u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0x82u, 0x11u}, - {0x87u, 0x01u}, - {0x94u, 0x01u}, - {0x96u, 0x10u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x40u}, - {0x9Fu, 0x09u}, - {0xA6u, 0x01u}, - {0xA7u, 0x01u}, - {0xA9u, 0x40u}, - {0xE2u, 0x80u}, - {0xE6u, 0x90u}, + {0xEAu, 0x40u}, + {0xEEu, 0x10u}, + {0x6Bu, 0x40u}, + {0x81u, 0x01u}, + {0x83u, 0x40u}, + {0x8Cu, 0x40u}, + {0x90u, 0x80u}, + {0x95u, 0x04u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x01u}, + {0xA7u, 0x80u}, + {0xABu, 0x04u}, + {0xDCu, 0x20u}, + {0xE2u, 0x20u}, + {0xE6u, 0x80u}, {0xEAu, 0x80u}, - {0x02u, 0x01u}, - {0x07u, 0x08u}, + {0x03u, 0x08u}, + {0x04u, 0x40u}, {0x09u, 0x80u}, - {0x0Cu, 0x40u}, - {0x10u, 0x20u}, - {0x16u, 0x80u}, - {0x60u, 0x20u}, - {0x66u, 0x02u}, - {0x81u, 0x80u}, - {0x8Bu, 0x20u}, - {0x8Eu, 0x02u}, + {0x0Cu, 0x80u}, + {0x12u, 0x20u}, + {0x15u, 0x04u}, + {0x5Fu, 0x02u}, + {0x65u, 0x20u}, + {0x8Fu, 0x02u}, {0xC0u, 0x03u}, {0xC2u, 0x03u}, {0xC4u, 0x0Cu}, - {0xD8u, 0x03u}, - {0xE0u, 0x02u}, - {0xE4u, 0x04u}, - {0x00u, 0x08u}, - {0x05u, 0x04u}, - {0x0Au, 0x20u}, + {0xD6u, 0x01u}, + {0xD8u, 0x01u}, + {0xE0u, 0x08u}, + {0x03u, 0x40u}, + {0x04u, 0x08u}, + {0x0Bu, 0x20u}, {0x0Cu, 0x08u}, - {0x52u, 0x80u}, - {0x5Fu, 0x20u}, - {0x66u, 0x84u}, - {0x80u, 0x08u}, - {0x82u, 0x01u}, - {0x88u, 0x40u}, - {0x98u, 0x40u}, - {0x9Au, 0x05u}, - {0x9Bu, 0x28u}, - {0x9Cu, 0x20u}, - {0xAAu, 0x04u}, - {0xAEu, 0x80u}, - {0xB0u, 0x20u}, + {0x51u, 0x80u}, + {0x55u, 0x40u}, + {0x5Du, 0x01u}, + {0x64u, 0x10u}, + {0x85u, 0x20u}, + {0x88u, 0x10u}, + {0x89u, 0x01u}, + {0x8Fu, 0x40u}, + {0x91u, 0x04u}, + {0x9Du, 0x20u}, + {0xA2u, 0x20u}, + {0xA3u, 0x08u}, + {0xB0u, 0x80u}, + {0xB4u, 0x40u}, + {0xB5u, 0x80u}, {0xC0u, 0x0Cu}, {0xC2u, 0x0Cu}, - {0xD4u, 0x04u}, - {0xD6u, 0x05u}, + {0xD4u, 0x06u}, + {0xD6u, 0x01u}, {0xD8u, 0x01u}, - {0xE2u, 0x01u}, - {0xEEu, 0x04u}, - {0x83u, 0x20u}, - {0x8Bu, 0x08u}, - {0x8Du, 0x04u}, - {0x99u, 0x04u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x20u}, - {0xAAu, 0x80u}, - {0xB0u, 0x04u}, - {0xB2u, 0x80u}, - {0xB6u, 0x10u}, - {0xE4u, 0x02u}, - {0xE6u, 0x01u}, - {0xEAu, 0x06u}, - {0xECu, 0x04u}, - {0x09u, 0x08u}, - {0x0Bu, 0x01u}, - {0x0Fu, 0x22u}, - {0x83u, 0x10u}, - {0x86u, 0x20u}, + {0xE0u, 0x04u}, + {0xE2u, 0x08u}, + {0xE4u, 0x01u}, + {0xEAu, 0x0Au}, + {0xEEu, 0x01u}, + {0x83u, 0x08u}, {0x8Du, 0x10u}, - {0x97u, 0x01u}, - {0xA1u, 0x04u}, - {0xA3u, 0x20u}, - {0xABu, 0x01u}, - {0xACu, 0x20u}, - {0xB5u, 0x04u}, + {0x90u, 0x08u}, + {0x91u, 0x04u}, + {0x93u, 0x20u}, + {0xA0u, 0x08u}, + {0xA3u, 0x08u}, + {0xA5u, 0xC0u}, + {0xAEu, 0x20u}, + {0xE6u, 0x08u}, + {0x09u, 0x18u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x02u}, + {0x89u, 0x40u}, + {0x8Du, 0x10u}, + {0x90u, 0x08u}, + {0x93u, 0x20u}, + {0x95u, 0x40u}, + {0xA5u, 0x52u}, + {0xA9u, 0x42u}, + {0xACu, 0x08u}, + {0xB1u, 0x04u}, + {0xB5u, 0x80u}, {0xC2u, 0x0Fu}, {0xE2u, 0x02u}, - {0xEAu, 0x08u}, - {0x67u, 0x40u}, - {0x94u, 0x01u}, - {0xABu, 0x08u}, - {0xADu, 0x40u}, - {0xAFu, 0x01u}, - {0xB4u, 0x02u}, - {0xD8u, 0x80u}, - {0xEAu, 0x60u}, + {0xE4u, 0x04u}, + {0xE8u, 0x08u}, + {0xEAu, 0x04u}, + {0x86u, 0x08u}, + {0x95u, 0x04u}, + {0x9Eu, 0x08u}, + {0xA1u, 0x02u}, + {0xA9u, 0x02u}, + {0xAFu, 0x81u}, + {0xE6u, 0x40u}, + {0xEAu, 0xC0u}, {0xEEu, 0x10u}, - {0x04u, 0x08u}, - {0x51u, 0x10u}, - {0x56u, 0x40u}, - {0x86u, 0x40u}, - {0x89u, 0x10u}, - {0x8Cu, 0x04u}, - {0xA8u, 0x01u}, - {0xAFu, 0x40u}, + {0x06u, 0x80u}, + {0x51u, 0x02u}, + {0x53u, 0x10u}, + {0x85u, 0x04u}, + {0x8Bu, 0x10u}, + {0x8Eu, 0x80u}, + {0x95u, 0x04u}, + {0xA1u, 0x02u}, {0xC0u, 0x20u}, - {0xD4u, 0x60u}, - {0xE2u, 0x10u}, - {0xEAu, 0x80u}, - {0xEEu, 0x40u}, - {0x76u, 0x20u}, - {0x9Au, 0x20u}, + {0xD4u, 0xA0u}, + {0xE6u, 0x40u}, + {0x7Fu, 0x02u}, + {0x83u, 0x02u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x04u}, + {0x90u, 0x08u}, + {0x93u, 0x20u}, + {0x95u, 0x40u}, {0x9Du, 0x10u}, - {0xA1u, 0x04u}, - {0xA3u, 0x20u}, {0xADu, 0x08u}, {0xAFu, 0x01u}, {0xDEu, 0x04u}, - {0x01u, 0x10u}, + {0xE2u, 0x0Cu}, + {0x01u, 0x40u}, {0x05u, 0x10u}, - {0x53u, 0x20u}, - {0x55u, 0x04u}, - {0x89u, 0x10u}, + {0x53u, 0x10u}, + {0x5Du, 0x20u}, + {0x87u, 0x10u}, + {0x95u, 0x40u}, + {0x99u, 0x20u}, {0x9Du, 0x10u}, - {0xA1u, 0x04u}, - {0xA3u, 0x20u}, + {0xA9u, 0x20u}, {0xC0u, 0x03u}, - {0xD4u, 0x06u}, - {0xE2u, 0x01u}, + {0xD4u, 0x04u}, + {0xD6u, 0x04u}, {0x10u, 0x03u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, - {0x1Bu, 0x01u}, + {0x1Cu, 0x03u}, + {0x1Du, 0x01u}, {0x00u, 0xFFu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, @@ -2099,30 +2336,18 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x04u, 0x80u, 0x00u, 0x00u, 0x08u, 0x00u, 0x21u, 0x00u, 0x07u, 0x7Fu, 0x18u, 0x80u, 0x01u, 0xC0u, 0x00u, 0x02u, - 0x01u, 0x90u, 0x00u, 0x40u, 0x22u, 0xC0u, 0x08u, 0x08u, 0x40u, 0x00u, 0x00u, 0xFFu, 0x01u, 0x00u, 0x00u, 0x9Fu, - 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x04u, 0x40u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x00u, 0x01u, - 0x40u, 0x00u, 0x00u, 0xFFu, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x04u, - 0x62u, 0x03u, 0x50u, 0x00u, 0x01u, 0xBEu, 0xFCu, 0x0Du, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index 3a40dcb..fea1312 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 9a3d42a..2a0af67 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfittergnu.inc * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -19,68 +19,6 @@ .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" -/* Debug_Timer_Interrupt */ -.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set Debug_Timer_Interrupt__INTC_MASK, 0x01 -.set Debug_Timer_Interrupt__INTC_NUMBER, 0 -.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 -.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 -.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 -.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 -.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 -.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 -.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 -.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 -.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 -.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 -.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 -.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 -.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 -.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 -.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 -.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 -.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 -.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 - -/* EXTLED */ -.set EXTLED__0__INTTYPE, CYREG_PICU0_INTTYPE0 -.set EXTLED__0__MASK, 0x01 -.set EXTLED__0__PC, CYREG_PRT0_PC0 -.set EXTLED__0__PORT, 0 -.set EXTLED__0__SHIFT, 0 -.set EXTLED__AG, CYREG_PRT0_AG -.set EXTLED__AMUX, CYREG_PRT0_AMUX -.set EXTLED__BIE, CYREG_PRT0_BIE -.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK -.set EXTLED__BYP, CYREG_PRT0_BYP -.set EXTLED__CTL, CYREG_PRT0_CTL -.set EXTLED__DM0, CYREG_PRT0_DM0 -.set EXTLED__DM1, CYREG_PRT0_DM1 -.set EXTLED__DM2, CYREG_PRT0_DM2 -.set EXTLED__DR, CYREG_PRT0_DR -.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS -.set EXTLED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE -.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN -.set EXTLED__MASK, 0x01 -.set EXTLED__PORT, 0 -.set EXTLED__PRT, CYREG_PRT0_PRT -.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set EXTLED__PS, CYREG_PRT0_PS -.set EXTLED__SHIFT, 0 -.set EXTLED__SLW, CYREG_PRT0_SLW - /* LED1 */ .set LED1__0__INTTYPE, CYREG_PICU0_INTTYPE1 .set LED1__0__MASK, 0x02 @@ -115,82 +53,478 @@ .set LED1__SHIFT, 1 .set LED1__SLW, CYREG_PRT0_SLW -/* SCSI_CLK */ -.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 -.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 -.set SCSI_CLK__INDEX, 0x01 -.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SCSI_CLK__PM_ACT_MSK, 0x02 -.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SCSI_CLK__PM_STBY_MSK, 0x02 +/* SD_CD */ +.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SD_CD__0__MASK, 0x20 +.set SD_CD__0__PC, CYREG_PRT3_PC5 +.set SD_CD__0__PORT, 3 +.set SD_CD__0__SHIFT, 5 +.set SD_CD__AG, CYREG_PRT3_AG +.set SD_CD__AMUX, CYREG_PRT3_AMUX +.set SD_CD__BIE, CYREG_PRT3_BIE +.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CD__BYP, CYREG_PRT3_BYP +.set SD_CD__CTL, CYREG_PRT3_CTL +.set SD_CD__DM0, CYREG_PRT3_DM0 +.set SD_CD__DM1, CYREG_PRT3_DM1 +.set SD_CD__DM2, CYREG_PRT3_DM2 +.set SD_CD__DR, CYREG_PRT3_DR +.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CD__MASK, 0x20 +.set SD_CD__PORT, 3 +.set SD_CD__PRT, CYREG_PRT3_PRT +.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CD__PS, CYREG_PRT3_PS +.set SD_CD__SHIFT, 5 +.set SD_CD__SLW, CYREG_PRT3_SLW -/* SCSI_CTL_PHASE */ -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK +/* SD_CS */ +.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SD_CS__0__MASK, 0x10 +.set SD_CS__0__PC, CYREG_PRT3_PC4 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 4 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x10 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 4 +.set SD_CS__SLW, CYREG_PRT3_SLW -/* SCSI_Filtered */ -.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Filtered_sts_sts_reg__0__POS, 0 -.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 -.set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST -.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 -.set SCSI_Filtered_sts_sts_reg__2__POS, 2 -.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 -.set SCSI_Filtered_sts_sts_reg__3__POS, 3 -.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 -.set SCSI_Filtered_sts_sts_reg__4__POS, 4 -.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 6 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_PRIOR_NUM, 7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_PRIOR_NUM, 7 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 -/* SCSI_Glitch_Ctl */ -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK +/* EXTLED */ +.set EXTLED__0__INTTYPE, CYREG_PICU0_INTTYPE0 +.set EXTLED__0__MASK, 0x01 +.set EXTLED__0__PC, CYREG_PRT0_PC0 +.set EXTLED__0__PORT, 0 +.set EXTLED__0__SHIFT, 0 +.set EXTLED__AG, CYREG_PRT0_AG +.set EXTLED__AMUX, CYREG_PRT0_AMUX +.set EXTLED__BIE, CYREG_PRT0_BIE +.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK +.set EXTLED__BYP, CYREG_PRT0_BYP +.set EXTLED__CTL, CYREG_PRT0_CTL +.set EXTLED__DM0, CYREG_PRT0_DM0 +.set EXTLED__DM1, CYREG_PRT0_DM1 +.set EXTLED__DM2, CYREG_PRT0_DM2 +.set EXTLED__DR, CYREG_PRT0_DR +.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS +.set EXTLED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE +.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN +.set EXTLED__MASK, 0x01 +.set EXTLED__PORT, 0 +.set EXTLED__PRT, CYREG_PRT0_PRT +.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set EXTLED__PS, CYREG_PRT0_PS +.set EXTLED__SHIFT, 0 +.set EXTLED__SLW, CYREG_PRT0_SLW + +/* SDCard */ +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST + +/* SD_SCK */ +.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_SCK__0__MASK, 0x04 +.set SD_SCK__0__PC, CYREG_PRT3_PC2 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 2 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x04 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 2 +.set SD_SCK__SLW, CYREG_PRT3_SLW /* SCSI_In */ .set SCSI_In__0__AG, CYREG_PRT2_AG @@ -918,287 +1252,84 @@ .set SCSI_In_DBx__DB7__SHIFT, 4 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW -/* SCSI_Noise */ -.set SCSI_Noise__0__AG, CYREG_PRT2_AG -.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX -.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE -.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK -.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP -.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL -.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0 -.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1 -.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2 -.set SCSI_Noise__0__DR, CYREG_PRT2_DR -.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS -.set SCSI_Noise__0__INTTYPE, CYREG_PICU2_INTTYPE0 -.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG -.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN -.set SCSI_Noise__0__MASK, 0x01 -.set SCSI_Noise__0__PC, CYREG_PRT2_PC0 -.set SCSI_Noise__0__PORT, 2 -.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT -.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL -.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN -.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 -.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 -.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 -.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 -.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT -.set SCSI_Noise__0__PS, CYREG_PRT2_PS -.set SCSI_Noise__0__SHIFT, 0 -.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW -.set SCSI_Noise__1__AG, CYREG_PRT6_AG -.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__1__DR, CYREG_PRT6_DR -.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE3 -.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__1__MASK, 0x08 -.set SCSI_Noise__1__PC, CYREG_PRT6_PC3 -.set SCSI_Noise__1__PORT, 6 -.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__1__PS, CYREG_PRT6_PS -.set SCSI_Noise__1__SHIFT, 3 -.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__2__AG, CYREG_PRT4_AG -.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__2__DR, CYREG_PRT4_DR -.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__2__INTTYPE, CYREG_PICU4_INTTYPE3 -.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__2__MASK, 0x08 -.set SCSI_Noise__2__PC, CYREG_PRT4_PC3 -.set SCSI_Noise__2__PORT, 4 -.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__2__PS, CYREG_PRT4_PS -.set SCSI_Noise__2__SHIFT, 3 -.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__3__AG, CYREG_PRT4_AG -.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__3__DR, CYREG_PRT4_DR -.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__3__INTTYPE, CYREG_PICU4_INTTYPE7 -.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__3__MASK, 0x80 -.set SCSI_Noise__3__PC, CYREG_PRT4_PC7 -.set SCSI_Noise__3__PORT, 4 -.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__3__PS, CYREG_PRT4_PS -.set SCSI_Noise__3__SHIFT, 7 -.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__4__AG, CYREG_PRT6_AG -.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__4__DR, CYREG_PRT6_DR -.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE2 -.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__4__MASK, 0x04 -.set SCSI_Noise__4__PC, CYREG_PRT6_PC2 -.set SCSI_Noise__4__PORT, 6 -.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__4__PS, CYREG_PRT6_PS -.set SCSI_Noise__4__SHIFT, 2 -.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG -.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR -.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE2 -.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__ACK__MASK, 0x04 -.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2 -.set SCSI_Noise__ACK__PORT, 6 -.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS -.set SCSI_Noise__ACK__SHIFT, 2 -.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG -.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX -.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE -.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK -.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP -.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL -.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0 -.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1 -.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2 -.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR -.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS -.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU2_INTTYPE0 -.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG -.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN -.set SCSI_Noise__ATN__MASK, 0x01 -.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0 -.set SCSI_Noise__ATN__PORT, 2 -.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT -.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL -.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN -.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 -.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 -.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT -.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS -.set SCSI_Noise__ATN__SHIFT, 0 -.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW -.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG -.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX -.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE -.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP -.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL -.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 -.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 -.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 -.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR -.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE3 -.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_Noise__BSY__MASK, 0x08 -.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3 -.set SCSI_Noise__BSY__PORT, 6 -.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT -.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS -.set SCSI_Noise__BSY__SHIFT, 3 -.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW -.set SCSI_Noise__RST__AG, CYREG_PRT4_AG -.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__RST__DR, CYREG_PRT4_DR -.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__RST__INTTYPE, CYREG_PICU4_INTTYPE7 -.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__RST__MASK, 0x80 -.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7 -.set SCSI_Noise__RST__PORT, 4 -.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__RST__PS, CYREG_PRT4_PS -.set SCSI_Noise__RST__SHIFT, 7 -.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW -.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG -.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX -.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE -.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP -.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL -.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0 -.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1 -.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2 -.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR -.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU4_INTTYPE3 -.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_Noise__SEL__MASK, 0x08 -.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3 -.set SCSI_Noise__SEL__PORT, 4 -.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT -.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS -.set SCSI_Noise__SEL__SHIFT, 3 -.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW +/* SD_MISO */ +.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 +.set SD_MISO__0__MASK, 0x02 +.set SD_MISO__0__PC, CYREG_PRT3_PC1 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 1 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x02 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 1 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_MOSI__0__MASK, 0x08 +.set SD_MOSI__0__PC, CYREG_PRT3_PC3 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 3 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x08 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 3 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT15_AG @@ -1765,15 +1896,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1786,35 +1917,35 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK .set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE @@ -2264,296 +2395,6 @@ .set SCSI_Out_DBx__DB7__SHIFT, 2 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW -/* SCSI_Parity_Error */ -.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST -.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST - -/* SCSI_RST_ISR */ -.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x02 -.set SCSI_RST_ISR__INTC_NUMBER, 1 -.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 -.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_RX_DMA */ -.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 -.set SCSI_RX_DMA__NUMBEROF_TDS, 0 -.set SCSI_RX_DMA__PRIORITY, 2 -.set SCSI_RX_DMA__TERMIN_EN, 0 -.set SCSI_RX_DMA__TERMIN_SEL, 0 -.set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 -.set SCSI_RX_DMA__TERMOUT1_EN, 0 -.set SCSI_RX_DMA__TERMOUT1_SEL, 0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 -.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 -.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 -.set SCSI_TX_DMA__NUMBEROF_TDS, 0 -.set SCSI_TX_DMA__PRIORITY, 2 -.set SCSI_TX_DMA__TERMIN_EN, 0 -.set SCSI_TX_DMA__TERMIN_SEL, 0 -.set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 -.set SCSI_TX_DMA__TERMOUT1_EN, 0 -.set SCSI_TX_DMA__TERMOUT1_SEL, 0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - -/* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_RxStsReg__4__POS, 4 -.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 -.set SDCard_BSPIM_RxStsReg__5__POS, 5 -.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 -.set SDCard_BSPIM_RxStsReg__6__POS, 6 -.set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 -.set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 -.set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST -.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 -.set SDCard_BSPIM_TxStsReg__2__POS, 2 -.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 -.set SDCard_BSPIM_TxStsReg__3__POS, 3 -.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 -.set SDCard_BSPIM_TxStsReg__4__POS, 4 -.set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST - -/* SD_CD */ -.set SD_CD__0__INTTYPE, CYREG_PICU3_INTTYPE5 -.set SD_CD__0__MASK, 0x20 -.set SD_CD__0__PC, CYREG_PRT3_PC5 -.set SD_CD__0__PORT, 3 -.set SD_CD__0__SHIFT, 5 -.set SD_CD__AG, CYREG_PRT3_AG -.set SD_CD__AMUX, CYREG_PRT3_AMUX -.set SD_CD__BIE, CYREG_PRT3_BIE -.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CD__BYP, CYREG_PRT3_BYP -.set SD_CD__CTL, CYREG_PRT3_CTL -.set SD_CD__DM0, CYREG_PRT3_DM0 -.set SD_CD__DM1, CYREG_PRT3_DM1 -.set SD_CD__DM2, CYREG_PRT3_DM2 -.set SD_CD__DR, CYREG_PRT3_DR -.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CD__MASK, 0x20 -.set SD_CD__PORT, 3 -.set SD_CD__PRT, CYREG_PRT3_PRT -.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CD__PS, CYREG_PRT3_PS -.set SD_CD__SHIFT, 5 -.set SD_CD__SLW, CYREG_PRT3_SLW - -/* SD_CS */ -.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 -.set SD_CS__0__MASK, 0x10 -.set SD_CS__0__PC, CYREG_PRT3_PC4 -.set SD_CS__0__PORT, 3 -.set SD_CS__0__SHIFT, 4 -.set SD_CS__AG, CYREG_PRT3_AG -.set SD_CS__AMUX, CYREG_PRT3_AMUX -.set SD_CS__BIE, CYREG_PRT3_BIE -.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_CS__BYP, CYREG_PRT3_BYP -.set SD_CS__CTL, CYREG_PRT3_CTL -.set SD_CS__DM0, CYREG_PRT3_DM0 -.set SD_CS__DM1, CYREG_PRT3_DM1 -.set SD_CS__DM2, CYREG_PRT3_DM2 -.set SD_CS__DR, CYREG_PRT3_DR -.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_CS__MASK, 0x10 -.set SD_CS__PORT, 3 -.set SD_CS__PRT, CYREG_PRT3_PRT -.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_CS__PS, CYREG_PRT3_PS -.set SD_CS__SHIFT, 4 -.set SD_CS__SLW, CYREG_PRT3_SLW - -/* SD_Data_Clk */ -.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 -.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 -.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 -.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Data_Clk__INDEX, 0x00 -.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Data_Clk__PM_ACT_MSK, 0x01 -.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Data_Clk__PM_STBY_MSK, 0x01 - -/* SD_MISO */ -.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE1 -.set SD_MISO__0__MASK, 0x02 -.set SD_MISO__0__PC, CYREG_PRT3_PC1 -.set SD_MISO__0__PORT, 3 -.set SD_MISO__0__SHIFT, 1 -.set SD_MISO__AG, CYREG_PRT3_AG -.set SD_MISO__AMUX, CYREG_PRT3_AMUX -.set SD_MISO__BIE, CYREG_PRT3_BIE -.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MISO__BYP, CYREG_PRT3_BYP -.set SD_MISO__CTL, CYREG_PRT3_CTL -.set SD_MISO__DM0, CYREG_PRT3_DM0 -.set SD_MISO__DM1, CYREG_PRT3_DM1 -.set SD_MISO__DM2, CYREG_PRT3_DM2 -.set SD_MISO__DR, CYREG_PRT3_DR -.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MISO__MASK, 0x02 -.set SD_MISO__PORT, 3 -.set SD_MISO__PRT, CYREG_PRT3_PRT -.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MISO__PS, CYREG_PRT3_PS -.set SD_MISO__SHIFT, 1 -.set SD_MISO__SLW, CYREG_PRT3_SLW - -/* SD_MOSI */ -.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE3 -.set SD_MOSI__0__MASK, 0x08 -.set SD_MOSI__0__PC, CYREG_PRT3_PC3 -.set SD_MOSI__0__PORT, 3 -.set SD_MOSI__0__SHIFT, 3 -.set SD_MOSI__AG, CYREG_PRT3_AG -.set SD_MOSI__AMUX, CYREG_PRT3_AMUX -.set SD_MOSI__BIE, CYREG_PRT3_BIE -.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_MOSI__BYP, CYREG_PRT3_BYP -.set SD_MOSI__CTL, CYREG_PRT3_CTL -.set SD_MOSI__DM0, CYREG_PRT3_DM0 -.set SD_MOSI__DM1, CYREG_PRT3_DM1 -.set SD_MOSI__DM2, CYREG_PRT3_DM2 -.set SD_MOSI__DR, CYREG_PRT3_DR -.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_MOSI__MASK, 0x08 -.set SD_MOSI__PORT, 3 -.set SD_MOSI__PRT, CYREG_PRT3_PRT -.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_MOSI__PS, CYREG_PRT3_PS -.set SD_MOSI__SHIFT, 3 -.set SD_MOSI__SLW, CYREG_PRT3_SLW - /* SD_RX_DMA */ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 @@ -2574,40 +2415,6 @@ .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SD_SCK */ -.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 -.set SD_SCK__0__MASK, 0x04 -.set SD_SCK__0__PC, CYREG_PRT3_PC2 -.set SD_SCK__0__PORT, 3 -.set SD_SCK__0__SHIFT, 2 -.set SD_SCK__AG, CYREG_PRT3_AG -.set SD_SCK__AMUX, CYREG_PRT3_AMUX -.set SD_SCK__BIE, CYREG_PRT3_BIE -.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SD_SCK__BYP, CYREG_PRT3_BYP -.set SD_SCK__CTL, CYREG_PRT3_CTL -.set SD_SCK__DM0, CYREG_PRT3_DM0 -.set SD_SCK__DM1, CYREG_PRT3_DM1 -.set SD_SCK__DM2, CYREG_PRT3_DM2 -.set SD_SCK__DR, CYREG_PRT3_DR -.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS -.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN -.set SD_SCK__MASK, 0x04 -.set SD_SCK__PORT, 3 -.set SD_SCK__PRT, CYREG_PRT3_PRT -.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SD_SCK__PS, CYREG_PRT3_PS -.set SD_SCK__SHIFT, 2 -.set SD_SCK__SLW, CYREG_PRT3_SLW - /* SD_TX_DMA */ .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_TX_DMA__DRQ_NUMBER, 3 @@ -2628,269 +2435,287 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* USBFS */ -.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_arb_int__INTC_MASK, 0x400000 -.set USBFS_arb_int__INTC_NUMBER, 22 -.set USBFS_arb_int__INTC_PRIOR_NUM, 6 -.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 -.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_bus_reset__INTC_MASK, 0x800000 -.set USBFS_bus_reset__INTC_NUMBER, 23 -.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 -.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 -.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 -.set USBFS_Dm__0__MASK, 0x80 -.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 -.set USBFS_Dm__0__PORT, 15 -.set USBFS_Dm__0__SHIFT, 7 -.set USBFS_Dm__AG, CYREG_PRT15_AG -.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dm__BIE, CYREG_PRT15_BIE -.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dm__BYP, CYREG_PRT15_BYP -.set USBFS_Dm__CTL, CYREG_PRT15_CTL -.set USBFS_Dm__DM0, CYREG_PRT15_DM0 -.set USBFS_Dm__DM1, CYREG_PRT15_DM1 -.set USBFS_Dm__DM2, CYREG_PRT15_DM2 -.set USBFS_Dm__DR, CYREG_PRT15_DR -.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dm__MASK, 0x80 -.set USBFS_Dm__PORT, 15 -.set USBFS_Dm__PRT, CYREG_PRT15_PRT -.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dm__PS, CYREG_PRT15_PS -.set USBFS_Dm__SHIFT, 7 -.set USBFS_Dm__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 -.set USBFS_Dp__0__MASK, 0x40 -.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 -.set USBFS_Dp__0__PORT, 15 -.set USBFS_Dp__0__SHIFT, 6 -.set USBFS_Dp__AG, CYREG_PRT15_AG -.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX -.set USBFS_Dp__BIE, CYREG_PRT15_BIE -.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK -.set USBFS_Dp__BYP, CYREG_PRT15_BYP -.set USBFS_Dp__CTL, CYREG_PRT15_CTL -.set USBFS_Dp__DM0, CYREG_PRT15_DM0 -.set USBFS_Dp__DM1, CYREG_PRT15_DM1 -.set USBFS_Dp__DM2, CYREG_PRT15_DM2 -.set USBFS_Dp__DR, CYREG_PRT15_DR -.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS -.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT -.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE -.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG -.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN -.set USBFS_Dp__MASK, 0x40 -.set USBFS_Dp__PORT, 15 -.set USBFS_Dp__PRT, CYREG_PRT15_PRT -.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL -.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN -.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 -.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 -.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 -.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 -.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT -.set USBFS_Dp__PS, CYREG_PRT15_PS -.set USBFS_Dp__SHIFT, 6 -.set USBFS_Dp__SLW, CYREG_PRT15_SLW -.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 -.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_dp_int__INTC_MASK, 0x1000 -.set USBFS_dp_int__INTC_NUMBER, 12 -.set USBFS_dp_int__INTC_PRIOR_NUM, 7 -.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 -.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_0__INTC_MASK, 0x1000000 -.set USBFS_ep_0__INTC_NUMBER, 24 -.set USBFS_ep_0__INTC_PRIOR_NUM, 7 -.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 -.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 -.set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 -.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 -.set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 -.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 -.set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 -.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 -.set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 -.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_sof_int__INTC_MASK, 0x200000 -.set USBFS_sof_int__INTC_NUMBER, 21 -.set USBFS_sof_int__INTC_PRIOR_NUM, 7 -.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 -.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG -.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG -.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN -.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR -.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG -.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN -.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR -.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG -.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN -.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR -.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG -.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN -.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR -.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG -.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN -.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR -.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG -.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN -.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR -.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG -.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN -.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR -.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG -.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN -.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR -.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN -.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR -.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR -.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA -.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB -.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA -.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB -.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR -.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA -.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB -.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA -.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB -.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR -.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA -.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB -.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA -.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB -.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR -.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA -.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB -.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA -.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB -.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR -.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA -.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB -.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA -.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB -.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR -.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA -.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB -.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA -.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB -.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR -.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA -.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB -.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA -.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB -.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR -.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA -.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB -.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA -.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB -.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE -.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT -.set USBFS_USB__CR0, CYREG_USB_CR0 -.set USBFS_USB__CR1, CYREG_USB_CR1 -.set USBFS_USB__CWA, CYREG_USB_CWA -.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB -.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES -.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB -.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG -.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE -.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE -.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT -.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR -.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 -.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 -.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 -.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 -.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 -.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 -.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 -.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 -.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE -.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 -.set USBFS_USB__PM_ACT_MSK, 0x01 -.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 -.set USBFS_USB__PM_STBY_MSK, 0x01 -.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN -.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR -.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 -.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 -.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 -.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 -.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 -.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 -.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 -.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 -.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 -.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 -.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 -.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 -.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 -.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 -.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 -.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 -.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 -.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 -.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 -.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 -.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 -.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 -.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 -.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 -.set USBFS_USB__SOF0, CYREG_USB_SOF0 -.set USBFS_USB__SOF1, CYREG_USB_SOF1 -.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 -.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT2_AG +.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX +.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP +.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL +.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT2_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Noise__0__INTTYPE, CYREG_PICU2_INTTYPE0 +.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Noise__0__MASK, 0x01 +.set SCSI_Noise__0__PC, CYREG_PRT2_PC0 +.set SCSI_Noise__0__PORT, 2 +.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT +.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT2_PS +.set SCSI_Noise__0__SHIFT, 0 +.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW +.set SCSI_Noise__1__AG, CYREG_PRT6_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT6_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__1__INTTYPE, CYREG_PICU6_INTTYPE3 +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__1__MASK, 0x08 +.set SCSI_Noise__1__PC, CYREG_PRT6_PC3 +.set SCSI_Noise__1__PORT, 6 +.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT6_PS +.set SCSI_Noise__1__SHIFT, 3 +.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__2__AG, CYREG_PRT4_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT4_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__2__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__2__MASK, 0x08 +.set SCSI_Noise__2__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__2__PORT, 4 +.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT4_PS +.set SCSI_Noise__2__SHIFT, 3 +.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__3__AG, CYREG_PRT4_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT4_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__3__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__3__MASK, 0x80 +.set SCSI_Noise__3__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__3__PORT, 4 +.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT4_PS +.set SCSI_Noise__3__SHIFT, 7 +.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__4__AG, CYREG_PRT6_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT6_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__4__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__4__MASK, 0x04 +.set SCSI_Noise__4__PC, CYREG_PRT6_PC2 +.set SCSI_Noise__4__PORT, 6 +.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT6_PS +.set SCSI_Noise__4__SHIFT, 2 +.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x04 +.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2 +.set SCSI_Noise__ACK__PORT, 6 +.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS +.set SCSI_Noise__ACK__SHIFT, 2 +.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG +.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX +.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP +.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL +.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU2_INTTYPE0 +.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Noise__ATN__MASK, 0x01 +.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0 +.set SCSI_Noise__ATN__PORT, 2 +.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT +.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS +.set SCSI_Noise__ATN__SHIFT, 0 +.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU6_INTTYPE3 +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x08 +.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3 +.set SCSI_Noise__BSY__PORT, 6 +.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS +.set SCSI_Noise__BSY__SHIFT, 3 +.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT4_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT4_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__RST__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__RST__MASK, 0x80 +.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__RST__PORT, 4 +.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT4_PS +.set SCSI_Noise__RST__SHIFT, 7 +.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x08 +.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__SEL__PORT, 4 +.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS +.set SCSI_Noise__SEL__SHIFT, 3 +.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW /* scsiTarget */ .set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 @@ -2942,8 +2767,8 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2951,9 +2776,90 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST + +/* Debug_Timer */ +.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x01 +.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 +.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 +.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 +.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 +.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 +.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 +.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 /* timer_clock */ .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 @@ -2966,12 +2872,108 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x02 +.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST + +/* SCSI_CTL_PHASE */ +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK + +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK + +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST + /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 16 +.set CYDEV_CHIP_DIE_PSOC4A, 18 .set CYDEV_CHIP_DIE_PSOC5LP, 2 .set CYDEV_CHIP_DIE_PSOC5TM, 3 .set CYDEV_CHIP_DIE_TMA4, 4 @@ -2987,32 +2989,34 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 16 -.set CYDEV_CHIP_MEMBER_4D, 12 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 .set CYDEV_CHIP_MEMBER_4E, 6 -.set CYDEV_CHIP_MEMBER_4F, 17 +.set CYDEV_CHIP_MEMBER_4F, 19 .set CYDEV_CHIP_MEMBER_4G, 4 -.set CYDEV_CHIP_MEMBER_4H, 15 -.set CYDEV_CHIP_MEMBER_4I, 21 -.set CYDEV_CHIP_MEMBER_4J, 13 -.set CYDEV_CHIP_MEMBER_4K, 14 -.set CYDEV_CHIP_MEMBER_4L, 20 -.set CYDEV_CHIP_MEMBER_4M, 19 -.set CYDEV_CHIP_MEMBER_4N, 9 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 .set CYDEV_CHIP_MEMBER_4O, 7 -.set CYDEV_CHIP_MEMBER_4P, 18 -.set CYDEV_CHIP_MEMBER_4Q, 11 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 .set CYDEV_CHIP_MEMBER_4R, 8 -.set CYDEV_CHIP_MEMBER_4S, 10 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 .set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 .set CYDEV_CHIP_MEMBER_5A, 3 .set CYDEV_CHIP_MEMBER_5B, 2 -.set CYDEV_CHIP_MEMBER_6A, 22 -.set CYDEV_CHIP_MEMBER_FM3, 26 -.set CYDEV_CHIP_MEMBER_FM4, 27 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 23 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 24 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 25 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -3038,6 +3042,7 @@ .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 @@ -3057,14 +3062,17 @@ .set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 .set CYDEV_CHIP_REVISION_5B_ES0, 0 .set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 -.set CYDEV_CHIP_REVISION_6A_NO_UDB, 0 -.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 .set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 0ecaa26..7f8f4fb 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitteriar.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -18,68 +18,6 @@ INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc -/* Debug_Timer_Interrupt */ -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x01 -Debug_Timer_Interrupt__INTC_NUMBER EQU 0 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* Debug_Timer_TimerHW */ -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -/* EXTLED */ -EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 -EXTLED__0__MASK EQU 0x01 -EXTLED__0__PC EQU CYREG_PRT0_PC0 -EXTLED__0__PORT EQU 0 -EXTLED__0__SHIFT EQU 0 -EXTLED__AG EQU CYREG_PRT0_AG -EXTLED__AMUX EQU CYREG_PRT0_AMUX -EXTLED__BIE EQU CYREG_PRT0_BIE -EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK -EXTLED__BYP EQU CYREG_PRT0_BYP -EXTLED__CTL EQU CYREG_PRT0_CTL -EXTLED__DM0 EQU CYREG_PRT0_DM0 -EXTLED__DM1 EQU CYREG_PRT0_DM1 -EXTLED__DM2 EQU CYREG_PRT0_DM2 -EXTLED__DR EQU CYREG_PRT0_DR -EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS -EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE -EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN -EXTLED__MASK EQU 0x01 -EXTLED__PORT EQU 0 -EXTLED__PRT EQU CYREG_PRT0_PRT -EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -EXTLED__PS EQU CYREG_PRT0_PS -EXTLED__SHIFT EQU 0 -EXTLED__SLW EQU CYREG_PRT0_SLW - /* LED1 */ LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1 LED1__0__MASK EQU 0x02 @@ -114,82 +52,478 @@ LED1__PS EQU CYREG_PRT0_PS LED1__SHIFT EQU 1 LED1__SLW EQU CYREG_PRT0_SLW -/* SCSI_CLK */ -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +/* SD_CD */ +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_CD__0__MASK EQU 0x20 +SD_CD__0__PC EQU CYREG_PRT3_PC5 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 5 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x20 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 5 +SD_CD__SLW EQU CYREG_PRT3_SLW -/* SCSI_CTL_PHASE */ -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK +/* SD_CS */ +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW -/* SCSI_Filtered */ -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 -/* SCSI_Glitch_Ctl */ -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +/* EXTLED */ +EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 +EXTLED__0__MASK EQU 0x01 +EXTLED__0__PC EQU CYREG_PRT0_PC0 +EXTLED__0__PORT EQU 0 +EXTLED__0__SHIFT EQU 0 +EXTLED__AG EQU CYREG_PRT0_AG +EXTLED__AMUX EQU CYREG_PRT0_AMUX +EXTLED__BIE EQU CYREG_PRT0_BIE +EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK +EXTLED__BYP EQU CYREG_PRT0_BYP +EXTLED__CTL EQU CYREG_PRT0_CTL +EXTLED__DM0 EQU CYREG_PRT0_DM0 +EXTLED__DM1 EQU CYREG_PRT0_DM1 +EXTLED__DM2 EQU CYREG_PRT0_DM2 +EXTLED__DR EQU CYREG_PRT0_DR +EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS +EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN +EXTLED__MASK EQU 0x01 +EXTLED__PORT EQU 0 +EXTLED__PRT EQU CYREG_PRT0_PRT +EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +EXTLED__PS EQU CYREG_PRT0_PS +EXTLED__SHIFT EQU 0 +EXTLED__SLW EQU CYREG_PRT0_SLW + +/* SDCard */ +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST + +/* SD_SCK */ +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW /* SCSI_In */ SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -917,287 +1251,84 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 4 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -/* SCSI_Noise */ -SCSI_Noise__0__AG EQU CYREG_PRT2_AG -SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT2_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__0__MASK EQU 0x01 -SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__0__PORT EQU 2 -SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT2_PS -SCSI_Noise__0__SHIFT EQU 0 -SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x08 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 3 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT4_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT4_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__2__MASK EQU 0x08 -SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__2__PORT EQU 4 -SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT4_PS -SCSI_Noise__2__SHIFT EQU 3 -SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__3__AG EQU CYREG_PRT4_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT4_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__3__MASK EQU 0x80 -SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__3__PORT EQU 4 -SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT4_PS -SCSI_Noise__3__SHIFT EQU 7 -SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x04 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 2 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x04 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 2 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG -SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__ATN__MASK EQU 0x01 -SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__ATN__PORT EQU 2 -SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS -SCSI_Noise__ATN__SHIFT EQU 0 -SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x08 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 3 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT4_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT4_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__RST__MASK EQU 0x80 -SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__RST__PORT EQU 4 -SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT4_PS -SCSI_Noise__RST__SHIFT EQU 7 -SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x08 -SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__SEL__PORT EQU 4 -SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS -SCSI_Noise__SEL__SHIFT EQU 3 -SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW +/* SD_MISO */ +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT15_AG @@ -1764,15 +1895,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1785,35 +1916,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE @@ -2263,296 +2394,6 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_Out_DBx__DB7__SHIFT EQU 2 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW -/* SCSI_Parity_Error */ -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST - -/* SCSI_RST_ISR */ -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_RX_DMA */ -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_SEL_ISR */ -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SCSI_TX_DMA */ -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -/* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST - -/* SD_CD */ -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_CD__0__MASK EQU 0x20 -SD_CD__0__PC EQU CYREG_PRT3_PC5 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 5 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x20 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 5 -SD_CD__SLW EQU CYREG_PRT3_SLW - -/* SD_CS */ -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW - -/* SD_Data_Clk */ -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - -/* SD_MISO */ -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -/* SD_MOSI */ -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - /* SD_RX_DMA */ SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2573,40 +2414,6 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SD_SCK */ -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW - /* SD_TX_DMA */ SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2627,269 +2434,287 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* USBFS */ -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT2_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT2_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__0__MASK EQU 0x01 +SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__0__PORT EQU 2 +SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT2_PS +SCSI_Noise__0__SHIFT EQU 0 +SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x08 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 3 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT4_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT4_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__2__MASK EQU 0x08 +SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__2__PORT EQU 4 +SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT4_PS +SCSI_Noise__2__SHIFT EQU 3 +SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__3__AG EQU CYREG_PRT4_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT4_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__3__MASK EQU 0x80 +SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__3__PORT EQU 4 +SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT4_PS +SCSI_Noise__3__SHIFT EQU 7 +SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x04 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 2 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x04 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 2 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x01 +SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__ATN__PORT EQU 2 +SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS +SCSI_Noise__ATN__SHIFT EQU 0 +SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x08 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 3 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT4_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT4_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__RST__MASK EQU 0x80 +SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__RST__PORT EQU 4 +SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT4_PS +SCSI_Noise__RST__SHIFT EQU 7 +SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x08 +SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__SEL__PORT EQU 4 +SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS +SCSI_Noise__SEL__SHIFT EQU 3 +SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW /* scsiTarget */ scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2941,8 +2766,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2950,9 +2775,90 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST + +/* Debug_Timer */ +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 /* timer_clock */ timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 @@ -2965,12 +2871,108 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST + +/* SCSI_CTL_PHASE */ +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK + +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK + +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST + /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC4A EQU 18 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -2986,32 +2988,34 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 16 -CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4F EQU 19 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 15 -CYDEV_CHIP_MEMBER_4I EQU 21 -CYDEV_CHIP_MEMBER_4J EQU 13 -CYDEV_CHIP_MEMBER_4K EQU 14 -CYDEV_CHIP_MEMBER_4L EQU 20 -CYDEV_CHIP_MEMBER_4M EQU 19 -CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 18 -CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 22 -CYDEV_CHIP_MEMBER_FM3 EQU 26 -CYDEV_CHIP_MEMBER_FM4 EQU 27 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3037,6 +3041,7 @@ CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 @@ -3056,14 +3061,17 @@ CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 -CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index a3484aa..798b8af 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitterrv.inc ; -; PSoC Creator 4.1 +; PSoC Creator 4.2 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -18,68 +18,6 @@ INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc -; Debug_Timer_Interrupt -Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x01 -Debug_Timer_Interrupt__INTC_NUMBER EQU 0 -Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 -Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; Debug_Timer_TimerHW -Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 -Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 -Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 -Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 -Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 -Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 -Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 -Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 -Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 -Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 -Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 -Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 -Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 -Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 -Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 -Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 - -; EXTLED -EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 -EXTLED__0__MASK EQU 0x01 -EXTLED__0__PC EQU CYREG_PRT0_PC0 -EXTLED__0__PORT EQU 0 -EXTLED__0__SHIFT EQU 0 -EXTLED__AG EQU CYREG_PRT0_AG -EXTLED__AMUX EQU CYREG_PRT0_AMUX -EXTLED__BIE EQU CYREG_PRT0_BIE -EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK -EXTLED__BYP EQU CYREG_PRT0_BYP -EXTLED__CTL EQU CYREG_PRT0_CTL -EXTLED__DM0 EQU CYREG_PRT0_DM0 -EXTLED__DM1 EQU CYREG_PRT0_DM1 -EXTLED__DM2 EQU CYREG_PRT0_DM2 -EXTLED__DR EQU CYREG_PRT0_DR -EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS -EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE -EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN -EXTLED__MASK EQU 0x01 -EXTLED__PORT EQU 0 -EXTLED__PRT EQU CYREG_PRT0_PRT -EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -EXTLED__PS EQU CYREG_PRT0_PS -EXTLED__SHIFT EQU 0 -EXTLED__SLW EQU CYREG_PRT0_SLW - ; LED1 LED1__0__INTTYPE EQU CYREG_PICU0_INTTYPE1 LED1__0__MASK EQU 0x02 @@ -114,82 +52,478 @@ LED1__PS EQU CYREG_PRT0_PS LED1__SHIFT EQU 1 LED1__SLW EQU CYREG_PRT0_SLW -; SCSI_CLK -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 -SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 -SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 -SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +; SD_CD +SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SD_CD__0__MASK EQU 0x20 +SD_CD__0__PC EQU CYREG_PRT3_PC5 +SD_CD__0__PORT EQU 3 +SD_CD__0__SHIFT EQU 5 +SD_CD__AG EQU CYREG_PRT3_AG +SD_CD__AMUX EQU CYREG_PRT3_AMUX +SD_CD__BIE EQU CYREG_PRT3_BIE +SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CD__BYP EQU CYREG_PRT3_BYP +SD_CD__CTL EQU CYREG_PRT3_CTL +SD_CD__DM0 EQU CYREG_PRT3_DM0 +SD_CD__DM1 EQU CYREG_PRT3_DM1 +SD_CD__DM2 EQU CYREG_PRT3_DM2 +SD_CD__DR EQU CYREG_PRT3_DR +SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CD__MASK EQU 0x20 +SD_CD__PORT EQU 3 +SD_CD__PRT EQU CYREG_PRT3_PRT +SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CD__PS EQU CYREG_PRT3_PS +SD_CD__SHIFT EQU 5 +SD_CD__SLW EQU CYREG_PRT3_SLW -; SCSI_CTL_PHASE -SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 -SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 -SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK +; SD_CS +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SD_CS__0__MASK EQU 0x10 +SD_CS__0__PC EQU CYREG_PRT3_PC4 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 4 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x10 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 4 +SD_CS__SLW EQU CYREG_PRT3_SLW -; SCSI_Filtered -SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Filtered_sts_sts_reg__0__POS EQU 0 -SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 -SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 -SCSI_Filtered_sts_sts_reg__2__POS EQU 2 -SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 -SCSI_Filtered_sts_sts_reg__3__POS EQU 3 -SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 -SCSI_Filtered_sts_sts_reg__4__POS EQU 4 -SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 -; SCSI_Glitch_Ctl -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +; EXTLED +EXTLED__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 +EXTLED__0__MASK EQU 0x01 +EXTLED__0__PC EQU CYREG_PRT0_PC0 +EXTLED__0__PORT EQU 0 +EXTLED__0__SHIFT EQU 0 +EXTLED__AG EQU CYREG_PRT0_AG +EXTLED__AMUX EQU CYREG_PRT0_AMUX +EXTLED__BIE EQU CYREG_PRT0_BIE +EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK +EXTLED__BYP EQU CYREG_PRT0_BYP +EXTLED__CTL EQU CYREG_PRT0_CTL +EXTLED__DM0 EQU CYREG_PRT0_DM0 +EXTLED__DM1 EQU CYREG_PRT0_DM1 +EXTLED__DM2 EQU CYREG_PRT0_DM2 +EXTLED__DR EQU CYREG_PRT0_DR +EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS +EXTLED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN +EXTLED__MASK EQU 0x01 +EXTLED__PORT EQU 0 +EXTLED__PRT EQU CYREG_PRT0_PRT +EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +EXTLED__PS EQU CYREG_PRT0_PS +EXTLED__SHIFT EQU 0 +EXTLED__SLW EQU CYREG_PRT0_SLW + +; SDCard +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST + +; SD_SCK +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_SCK__0__MASK EQU 0x04 +SD_SCK__0__PC EQU CYREG_PRT3_PC2 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 2 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x04 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 2 +SD_SCK__SLW EQU CYREG_PRT3_SLW ; SCSI_In SCSI_In__0__AG EQU CYREG_PRT2_AG @@ -917,287 +1251,84 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 4 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW -; SCSI_Noise -SCSI_Noise__0__AG EQU CYREG_PRT2_AG -SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__0__DR EQU CYREG_PRT2_DR -SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__0__MASK EQU 0x01 -SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__0__PORT EQU 2 -SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__0__PS EQU CYREG_PRT2_PS -SCSI_Noise__0__SHIFT EQU 0 -SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__1__AG EQU CYREG_PRT6_AG -SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__1__DR EQU CYREG_PRT6_DR -SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__1__MASK EQU 0x08 -SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__1__PORT EQU 6 -SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__1__PS EQU CYREG_PRT6_PS -SCSI_Noise__1__SHIFT EQU 3 -SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__2__AG EQU CYREG_PRT4_AG -SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__2__DR EQU CYREG_PRT4_DR -SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__2__MASK EQU 0x08 -SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__2__PORT EQU 4 -SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__2__PS EQU CYREG_PRT4_PS -SCSI_Noise__2__SHIFT EQU 3 -SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__3__AG EQU CYREG_PRT4_AG -SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__3__DR EQU CYREG_PRT4_DR -SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__3__MASK EQU 0x80 -SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__3__PORT EQU 4 -SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__3__PS EQU CYREG_PRT4_PS -SCSI_Noise__3__SHIFT EQU 7 -SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__4__AG EQU CYREG_PRT6_AG -SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__4__DR EQU CYREG_PRT6_DR -SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__4__MASK EQU 0x04 -SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__4__PORT EQU 6 -SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__4__PS EQU CYREG_PRT6_PS -SCSI_Noise__4__SHIFT EQU 2 -SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG -SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR -SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 -SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__ACK__MASK EQU 0x04 -SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 -SCSI_Noise__ACK__PORT EQU 6 -SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS -SCSI_Noise__ACK__SHIFT EQU 2 -SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG -SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX -SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE -SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP -SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL -SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 -SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 -SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 -SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR -SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 -SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_Noise__ATN__MASK EQU 0x01 -SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 -SCSI_Noise__ATN__PORT EQU 2 -SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT -SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS -SCSI_Noise__ATN__SHIFT EQU 0 -SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW -SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG -SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR -SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 -SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_Noise__BSY__MASK EQU 0x08 -SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 -SCSI_Noise__BSY__PORT EQU 6 -SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS -SCSI_Noise__BSY__SHIFT EQU 3 -SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW -SCSI_Noise__RST__AG EQU CYREG_PRT4_AG -SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__RST__DR EQU CYREG_PRT4_DR -SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 -SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__RST__MASK EQU 0x80 -SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 -SCSI_Noise__RST__PORT EQU 4 -SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__RST__PS EQU CYREG_PRT4_PS -SCSI_Noise__RST__SHIFT EQU 7 -SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW -SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG -SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX -SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE -SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP -SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL -SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 -SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 -SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 -SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR -SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 -SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_Noise__SEL__MASK EQU 0x08 -SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 -SCSI_Noise__SEL__PORT EQU 4 -SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT -SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS -SCSI_Noise__SEL__SHIFT EQU 3 -SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW +; SD_MISO +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_MISO__0__MASK EQU 0x02 +SD_MISO__0__PC EQU CYREG_PRT3_PC1 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 1 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x02 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 1 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_MOSI__0__MASK EQU 0x08 +SD_MOSI__0__PC EQU CYREG_PRT3_PC3 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 3 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x08 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 3 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT15_AG @@ -1764,15 +1895,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1785,35 +1916,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE @@ -2263,296 +2394,6 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_Out_DBx__DB7__SHIFT EQU 2 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW -; SCSI_Parity_Error -SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST -SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST - -; SCSI_RST_ISR -SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 -SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 -SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_RX_DMA -SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 -SCSI_RX_DMA__NUMBEROF_TDS EQU 0 -SCSI_RX_DMA__PRIORITY EQU 2 -SCSI_RX_DMA__TERMIN_EN EQU 0 -SCSI_RX_DMA__TERMIN_SEL EQU 0 -SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 -SCSI_RX_DMA__TERMOUT1_EN EQU 0 -SCSI_RX_DMA__TERMOUT1_SEL EQU 0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 -SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_SEL_ISR -SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 -SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 -SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SCSI_TX_DMA -SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 -SCSI_TX_DMA__NUMBEROF_TDS EQU 0 -SCSI_TX_DMA__PRIORITY EQU 2 -SCSI_TX_DMA__TERMIN_EN EQU 0 -SCSI_TX_DMA__TERMIN_SEL EQU 0 -SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 -SCSI_TX_DMA__TERMOUT1_EN EQU 0 -SCSI_TX_DMA__TERMOUT1_SEL EQU 0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 -SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - -; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_RxStsReg__4__POS EQU 4 -SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 -SDCard_BSPIM_RxStsReg__5__POS EQU 5 -SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 -SDCard_BSPIM_RxStsReg__6__POS EQU 6 -SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 -SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 -SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 -SDCard_BSPIM_TxStsReg__2__POS EQU 2 -SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 -SDCard_BSPIM_TxStsReg__3__POS EQU 3 -SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 -SDCard_BSPIM_TxStsReg__4__POS EQU 4 -SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST - -; SD_CD -SD_CD__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SD_CD__0__MASK EQU 0x20 -SD_CD__0__PC EQU CYREG_PRT3_PC5 -SD_CD__0__PORT EQU 3 -SD_CD__0__SHIFT EQU 5 -SD_CD__AG EQU CYREG_PRT3_AG -SD_CD__AMUX EQU CYREG_PRT3_AMUX -SD_CD__BIE EQU CYREG_PRT3_BIE -SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CD__BYP EQU CYREG_PRT3_BYP -SD_CD__CTL EQU CYREG_PRT3_CTL -SD_CD__DM0 EQU CYREG_PRT3_DM0 -SD_CD__DM1 EQU CYREG_PRT3_DM1 -SD_CD__DM2 EQU CYREG_PRT3_DM2 -SD_CD__DR EQU CYREG_PRT3_DR -SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CD__MASK EQU 0x20 -SD_CD__PORT EQU 3 -SD_CD__PRT EQU CYREG_PRT3_PRT -SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CD__PS EQU CYREG_PRT3_PS -SD_CD__SHIFT EQU 5 -SD_CD__SLW EQU CYREG_PRT3_SLW - -; SD_CS -SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SD_CS__0__MASK EQU 0x10 -SD_CS__0__PC EQU CYREG_PRT3_PC4 -SD_CS__0__PORT EQU 3 -SD_CS__0__SHIFT EQU 4 -SD_CS__AG EQU CYREG_PRT3_AG -SD_CS__AMUX EQU CYREG_PRT3_AMUX -SD_CS__BIE EQU CYREG_PRT3_BIE -SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_CS__BYP EQU CYREG_PRT3_BYP -SD_CS__CTL EQU CYREG_PRT3_CTL -SD_CS__DM0 EQU CYREG_PRT3_DM0 -SD_CS__DM1 EQU CYREG_PRT3_DM1 -SD_CS__DM2 EQU CYREG_PRT3_DM2 -SD_CS__DR EQU CYREG_PRT3_DR -SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_CS__MASK EQU 0x10 -SD_CS__PORT EQU 3 -SD_CS__PRT EQU CYREG_PRT3_PRT -SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_CS__PS EQU CYREG_PRT3_PS -SD_CS__SHIFT EQU 4 -SD_CS__SLW EQU CYREG_PRT3_SLW - -; SD_Data_Clk -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 -SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 -SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 -SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - -; SD_MISO -SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 -SD_MISO__0__MASK EQU 0x02 -SD_MISO__0__PC EQU CYREG_PRT3_PC1 -SD_MISO__0__PORT EQU 3 -SD_MISO__0__SHIFT EQU 1 -SD_MISO__AG EQU CYREG_PRT3_AG -SD_MISO__AMUX EQU CYREG_PRT3_AMUX -SD_MISO__BIE EQU CYREG_PRT3_BIE -SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MISO__BYP EQU CYREG_PRT3_BYP -SD_MISO__CTL EQU CYREG_PRT3_CTL -SD_MISO__DM0 EQU CYREG_PRT3_DM0 -SD_MISO__DM1 EQU CYREG_PRT3_DM1 -SD_MISO__DM2 EQU CYREG_PRT3_DM2 -SD_MISO__DR EQU CYREG_PRT3_DR -SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MISO__MASK EQU 0x02 -SD_MISO__PORT EQU 3 -SD_MISO__PRT EQU CYREG_PRT3_PRT -SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MISO__PS EQU CYREG_PRT3_PS -SD_MISO__SHIFT EQU 1 -SD_MISO__SLW EQU CYREG_PRT3_SLW - -; SD_MOSI -SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 -SD_MOSI__0__MASK EQU 0x08 -SD_MOSI__0__PC EQU CYREG_PRT3_PC3 -SD_MOSI__0__PORT EQU 3 -SD_MOSI__0__SHIFT EQU 3 -SD_MOSI__AG EQU CYREG_PRT3_AG -SD_MOSI__AMUX EQU CYREG_PRT3_AMUX -SD_MOSI__BIE EQU CYREG_PRT3_BIE -SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_MOSI__BYP EQU CYREG_PRT3_BYP -SD_MOSI__CTL EQU CYREG_PRT3_CTL -SD_MOSI__DM0 EQU CYREG_PRT3_DM0 -SD_MOSI__DM1 EQU CYREG_PRT3_DM1 -SD_MOSI__DM2 EQU CYREG_PRT3_DM2 -SD_MOSI__DR EQU CYREG_PRT3_DR -SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_MOSI__MASK EQU 0x08 -SD_MOSI__PORT EQU 3 -SD_MOSI__PRT EQU CYREG_PRT3_PRT -SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_MOSI__PS EQU CYREG_PRT3_PS -SD_MOSI__SHIFT EQU 3 -SD_MOSI__SLW EQU CYREG_PRT3_SLW - ; SD_RX_DMA SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2573,40 +2414,6 @@ SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SD_SCK -SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 -SD_SCK__0__MASK EQU 0x04 -SD_SCK__0__PC EQU CYREG_PRT3_PC2 -SD_SCK__0__PORT EQU 3 -SD_SCK__0__SHIFT EQU 2 -SD_SCK__AG EQU CYREG_PRT3_AG -SD_SCK__AMUX EQU CYREG_PRT3_AMUX -SD_SCK__BIE EQU CYREG_PRT3_BIE -SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SD_SCK__BYP EQU CYREG_PRT3_BYP -SD_SCK__CTL EQU CYREG_PRT3_CTL -SD_SCK__DM0 EQU CYREG_PRT3_DM0 -SD_SCK__DM1 EQU CYREG_PRT3_DM1 -SD_SCK__DM2 EQU CYREG_PRT3_DM2 -SD_SCK__DR EQU CYREG_PRT3_DR -SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS -SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN -SD_SCK__MASK EQU 0x04 -SD_SCK__PORT EQU 3 -SD_SCK__PRT EQU CYREG_PRT3_PRT -SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SD_SCK__PS EQU CYREG_PRT3_PS -SD_SCK__SHIFT EQU 2 -SD_SCK__SLW EQU CYREG_PRT3_SLW - ; SD_TX_DMA SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 @@ -2627,269 +2434,287 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; USBFS -USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_arb_int__INTC_MASK EQU 0x400000 -USBFS_arb_int__INTC_NUMBER EQU 22 -USBFS_arb_int__INTC_PRIOR_NUM EQU 6 -USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 -USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_bus_reset__INTC_MASK EQU 0x800000 -USBFS_bus_reset__INTC_NUMBER EQU 23 -USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 -USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 -USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 -USBFS_Dm__0__MASK EQU 0x80 -USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 -USBFS_Dm__0__PORT EQU 15 -USBFS_Dm__0__SHIFT EQU 7 -USBFS_Dm__AG EQU CYREG_PRT15_AG -USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dm__BIE EQU CYREG_PRT15_BIE -USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dm__BYP EQU CYREG_PRT15_BYP -USBFS_Dm__CTL EQU CYREG_PRT15_CTL -USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dm__DR EQU CYREG_PRT15_DR -USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dm__MASK EQU 0x80 -USBFS_Dm__PORT EQU 15 -USBFS_Dm__PRT EQU CYREG_PRT15_PRT -USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dm__PS EQU CYREG_PRT15_PS -USBFS_Dm__SHIFT EQU 7 -USBFS_Dm__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 -USBFS_Dp__0__MASK EQU 0x40 -USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 -USBFS_Dp__0__PORT EQU 15 -USBFS_Dp__0__SHIFT EQU 6 -USBFS_Dp__AG EQU CYREG_PRT15_AG -USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX -USBFS_Dp__BIE EQU CYREG_PRT15_BIE -USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK -USBFS_Dp__BYP EQU CYREG_PRT15_BYP -USBFS_Dp__CTL EQU CYREG_PRT15_CTL -USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 -USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 -USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 -USBFS_Dp__DR EQU CYREG_PRT15_DR -USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS -USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT -USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE -USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG -USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN -USBFS_Dp__MASK EQU 0x40 -USBFS_Dp__PORT EQU 15 -USBFS_Dp__PRT EQU CYREG_PRT15_PRT -USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL -USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN -USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 -USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 -USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 -USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 -USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT -USBFS_Dp__PS EQU CYREG_PRT15_PS -USBFS_Dp__SHIFT EQU 6 -USBFS_Dp__SLW EQU CYREG_PRT15_SLW -USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 -USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_dp_int__INTC_MASK EQU 0x1000 -USBFS_dp_int__INTC_NUMBER EQU 12 -USBFS_dp_int__INTC_PRIOR_NUM EQU 7 -USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 -USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_0__INTC_MASK EQU 0x1000000 -USBFS_ep_0__INTC_NUMBER EQU 24 -USBFS_ep_0__INTC_PRIOR_NUM EQU 7 -USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 -USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 -USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 -USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 -USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 -USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 -USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 -USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 -USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 -USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_sof_int__INTC_MASK EQU 0x200000 -USBFS_sof_int__INTC_NUMBER EQU 21 -USBFS_sof_int__INTC_PRIOR_NUM EQU 7 -USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 -USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG -USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG -USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN -USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR -USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG -USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN -USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR -USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG -USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN -USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR -USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG -USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN -USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR -USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG -USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN -USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR -USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG -USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN -USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR -USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG -USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN -USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR -USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG -USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN -USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR -USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN -USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR -USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR -USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA -USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB -USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA -USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB -USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR -USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA -USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB -USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA -USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB -USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR -USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA -USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB -USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA -USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB -USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR -USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA -USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB -USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA -USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB -USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR -USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA -USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB -USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA -USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB -USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR -USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA -USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB -USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA -USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB -USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR -USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA -USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB -USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA -USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB -USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR -USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA -USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB -USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA -USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB -USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE -USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT -USBFS_USB__CR0 EQU CYREG_USB_CR0 -USBFS_USB__CR1 EQU CYREG_USB_CR1 -USBFS_USB__CWA EQU CYREG_USB_CWA -USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB -USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES -USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB -USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG -USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE -USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE -USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT -USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR -USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 -USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 -USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 -USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 -USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 -USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 -USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 -USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 -USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE -USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 -USBFS_USB__PM_ACT_MSK EQU 0x01 -USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 -USBFS_USB__PM_STBY_MSK EQU 0x01 -USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN -USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR -USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 -USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 -USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 -USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 -USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 -USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 -USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 -USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 -USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 -USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 -USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 -USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 -USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 -USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 -USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 -USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 -USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 -USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 -USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 -USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 -USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 -USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 -USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 -USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 -USBFS_USB__SOF0 EQU CYREG_USB_SOF0 -USBFS_USB__SOF1 EQU CYREG_USB_SOF1 -USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 -USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT2_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT2_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__0__MASK EQU 0x01 +SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__0__PORT EQU 2 +SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT2_PS +SCSI_Noise__0__SHIFT EQU 0 +SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x08 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 3 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT4_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT4_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__2__MASK EQU 0x08 +SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__2__PORT EQU 4 +SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT4_PS +SCSI_Noise__2__SHIFT EQU 3 +SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__3__AG EQU CYREG_PRT4_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT4_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__3__MASK EQU 0x80 +SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__3__PORT EQU 4 +SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT4_PS +SCSI_Noise__3__SHIFT EQU 7 +SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x04 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 2 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x04 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 2 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x01 +SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__ATN__PORT EQU 2 +SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS +SCSI_Noise__ATN__SHIFT EQU 0 +SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x08 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 3 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT4_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT4_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__RST__MASK EQU 0x80 +SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__RST__PORT EQU 4 +SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT4_PS +SCSI_Noise__RST__SHIFT EQU 7 +SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x08 +SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__SEL__PORT EQU 4 +SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS +SCSI_Noise__SEL__SHIFT EQU 3 +SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW ; scsiTarget scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 @@ -2941,8 +2766,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2950,9 +2775,90 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST + +; Debug_Timer +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 ; timer_clock timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 @@ -2965,12 +2871,108 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST + +; SCSI_CTL_PHASE +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK + +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK + +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST + ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 16 +CYDEV_CHIP_DIE_PSOC4A EQU 18 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -2986,32 +2988,34 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 16 -CYDEV_CHIP_MEMBER_4D EQU 12 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 17 +CYDEV_CHIP_MEMBER_4F EQU 19 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 15 -CYDEV_CHIP_MEMBER_4I EQU 21 -CYDEV_CHIP_MEMBER_4J EQU 13 -CYDEV_CHIP_MEMBER_4K EQU 14 -CYDEV_CHIP_MEMBER_4L EQU 20 -CYDEV_CHIP_MEMBER_4M EQU 19 -CYDEV_CHIP_MEMBER_4N EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 18 -CYDEV_CHIP_MEMBER_4Q EQU 11 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 10 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 22 -CYDEV_CHIP_MEMBER_FM3 EQU 26 -CYDEV_CHIP_MEMBER_FM4 EQU 27 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 23 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 24 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 25 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -3037,6 +3041,7 @@ CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 @@ -3056,14 +3061,17 @@ CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 CYDEV_CHIP_REVISION_5B_ES0 EQU 0 CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 -CYDEV_CHIP_REVISION_6A_NO_UDB EQU 0 -CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index e8e92b1..e793f24 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 9e44652..b3b4679 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.1 +* PSoC Creator 4.2 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -83,6 +83,7 @@ #include "cyPm.h" #include "CySpc.h" #include "cytypes.h" +#include "cy_em_eeprom.h" /*[]*/ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx index c2f0cec..2a4999b 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,12 +1,42 @@ +