Macintosh-HW/SCSI2SD
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Lots of bug fixes.

Browse Source 
- Reset fix
 - Overrun fifo on fast scsi host fix
 - Startup time improvement
 - Allows overwriting the bootloader
 - Adds "sticky" sel option
 - Adds map luns to id option
This commit is contained in:
Michael McMaster 2016-01-07 22:15:45 +10:00
parent 5418ee6229
commit ff3ca448a5
65 changed files with 5205 additions and 4503 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
CHANGELOG
View File

@ -1,3 +1,14 @@
201601XX 4.6
- Fixed bug when using sector size that isn't a multiple of 4
(eg. 522 bytes)
- Fixed a bug that caused hanging or scsi phase errors on
high speed scsi hosts.
- Fixed a hang when processing a SCSI RESET in a data phase.
- scsi2sd-util: Fixed USB connection problems under Windows 10.
- Added option to treat luns as separate devices
- Improved boot up time.
20151105 4.5
- Fix bug in SCSI MODE SENSE that returned the wrong mode type
- Fixes CDROM emulation

28
software/SCSI2SD/src/config.c
View File

@ -33,7 +33,7 @@
#include <string.h>
static const uint16_t FIRMWARE_VERSION = 0x0450;
static const uint16_t FIRMWARE_VERSION = 0x0460;
// 1 flash row
static const uint8_t DEFAULT_CONFIG[256] =
@ -142,26 +142,14 @@ writeFlashCommand(const uint8_t* cmd, size_t cmdSize)
uint8_t flashArray = cmd[257];
uint8_t flashRow = cmd[258];
// Be very careful not to overwrite the bootloader or other
// code
if ((flashArray != SCSI_CONFIG_ARRAY) ||
(flashRow < SCSI_CONFIG_BOARD_ROW) ||
(flashRow >= SCSI_CONFIG_3_ROW + SCSI_CONFIG_ROWS))
{
uint8_t response[] = { CONFIG_STATUS_ERR};
hidPacket_send(response, sizeof(response));
}
else
{
CySetTemp();
int status = CyWriteRowData(flashArray, flashRow, cmd + 1);
CySetTemp();
int status = CyWriteRowData(flashArray, flashRow, cmd + 1);
uint8_t response[] =
{
status == CYRET_SUCCESS ? CONFIG_STATUS_GOOD : CONFIG_STATUS_ERR
};
hidPacket_send(response, sizeof(response));
}
uint8_t response[] =
{
status == CYRET_SUCCESS ? CONFIG_STATUS_GOOD : CONFIG_STATUS_ERR
};
hidPacket_send(response, sizeof(response));
}
static void

34
software/SCSI2SD/src/scsi.c
View File

@ -76,6 +76,7 @@ static void enter_BusFree()
ledOff();
scsiDev.phase = BUS_FREE;
scsiDev.selFlag = 0;
}
static void enter_MessageIn(uint8 message)
@ -263,10 +264,27 @@ static void process_Command()
scsiDev.lun = scsiDev.cdb[1] >> 5;
}
// For Philips P2000C with Xebec S1410 SASI/MFM adapter
// http://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf
if ((scsiDev.lun > 0) && (scsiDev.boardCfg.flags & CONFIG_MAP_LUNS_TO_IDS))
{
int tgtIndex;
for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex)
{
if (scsiDev.targets[tgtIndex].targetId == scsiDev.lun)
{
scsiDev.target = &scsiDev.targets[tgtIndex];
scsiDev.lun = 0;
break;
}
}
}
control = scsiDev.cdb[scsiDev.cdbLen - 1];
scsiDev.cmdCount++;
TargetConfig* cfg = scsiDev.target->cfg;
const TargetConfig* cfg = scsiDev.target->cfg;
if (unlikely(scsiDev.resetFlag))
{
@ -467,6 +485,7 @@ static void scsiReset()
scsiDev.phase = BUS_FREE;
scsiDev.atnFlag = 0;
scsiDev.resetFlag = 0;
scsiDev.selFlag = 0;
scsiDev.lun = -1;
scsiDev.compatMode = COMPAT_UNKNOWN;
@ -539,7 +558,9 @@ static void process_SelectionPhase()
CyDelay(scsiDev.boardCfg.selectionDelay);
}
int sel = SCSI_ReadFilt(SCSI_Filt_SEL);
int selLatchCfg = scsiDev.boardCfg.flags & CONFIG_ENABLE_SEL_LATCH;
int sel = (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);
int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);
int io = SCSI_ReadPin(SCSI_In_IO);
@ -560,7 +581,7 @@ static void process_SelectionPhase()
break;
}
}
sel &= SCSI_ReadFilt(SCSI_Filt_SEL);
sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);
bsy |= SCSI_ReadFilt(SCSI_Filt_BSY);
io |= SCSI_ReadPin(SCSI_In_IO);
if (!bsy && !io && sel &&
@ -638,6 +659,8 @@ static void process_SelectionPhase()
{
scsiDev.phase = BUS_BUSY;
}
scsiDev.selFlag = 0;
}
static void process_MessageOut()
@ -812,7 +835,7 @@ void scsiPoll(void)
// one initiator in the chain. Support this by moving
// straight to selection if SEL is asserted.
// ie. the initiator won't assert BSY and it's own ID before moving to selection.
else if (SCSI_ReadFilt(SCSI_Filt_SEL))
else if (SCSI_ReadFilt(SCSI_Filt_SEL) || scsiDev.selFlag)
{
enter_SelectionPhase();
}
@ -821,7 +844,7 @@ void scsiPoll(void)
case BUS_BUSY:
// Someone is using the bus. Perhaps they are trying to
// select us.
if (SCSI_ReadFilt(SCSI_Filt_SEL))
if (SCSI_ReadFilt(SCSI_Filt_SEL) || scsiDev.selFlag)
{
enter_SelectionPhase();
}
@ -916,6 +939,7 @@ void scsiInit()
{
scsiDev.atnFlag = 0;
scsiDev.resetFlag = 1;
scsiDev.selFlag = 0;
scsiDev.phase = BUS_FREE;
scsiDev.target = NULL;
scsiDev.compatMode = COMPAT_UNKNOWN;

3
software/SCSI2SD/src/scsi.h
View File

@ -106,6 +106,9 @@ typedef struct
// Set to true (1) if the RST flag was set.
volatile int resetFlag;
// Set to true (1) if the SEL flag was set.
volatile int selFlag;
// Set to true (1) if a parity error was observed.
int parityError;

39
software/SCSI2SD/src/scsiPhy.c
View File

@ -76,6 +76,10 @@ CY_ISR(scsiSelectionISR)
// The SEL signal ISR ensures we wake up from a _WFI() (wait-for-interrupt)
// call in the main loop without waiting for our 1ms timer to
// expire. This is done to meet the 250us selection abort time.
// selFlag is required for Philips P2000C which releases it after 600ns
// without waiting for BSY.
scsiDev.selFlag = 1;
}
uint8_t
@ -227,8 +231,7 @@ scsiRead(uint8_t* data, uint32_t count)
}
else
{
uint32_t alignedCount = count & 0xFFFFFFF8;
scsiReadDMA(data, alignedCount);
scsiReadDMA(data, count);
// Wait for the next DMA interrupt (or the 1ms systick)
// It's beneficial to halt the processor to
@ -240,11 +243,6 @@ scsiRead(uint8_t* data, uint32_t count)
{
__WFI();
};
if (count > alignedCount)
{
scsiReadPIO(data + alignedCount, count - alignedCount);
}
}
}
@ -364,8 +362,7 @@ scsiWrite(const uint8_t* data, uint32_t count)
}
else
{
uint32_t alignedCount = count & 0xFFFFFFF8;
scsiWriteDMA(data, alignedCount);
scsiWriteDMA(data, count);
// Wait for the next DMA interrupt (or the 1ms systick)
// It's beneficial to halt the processor to
@ -377,11 +374,6 @@ scsiWrite(const uint8_t* data, uint32_t count)
{
__WFI();
};
if (count > alignedCount)
{
scsiWritePIO(data + alignedCount, count - alignedCount);
}
}
}
@ -428,8 +420,19 @@ void scsiPhyReset()
// CyDmaChGetRequest returns 0 for the relevant bit once the
// request is completed.
trace(trace_spinDMAReset);
while (CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) {}
while (CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) {}
while (
(CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) &&
!scsiTxDMAComplete
)
{}
while ((
CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) &&
!scsiRxDMAComplete
)
{}
CyDelayUs(1);
CyDmaChDisable(scsiDmaTxChan);
CyDmaChDisable(scsiDmaRxChan);
@ -468,7 +471,7 @@ static void scsiPhyInitDMA()
{
scsiDmaRxChan =
SCSI_RX_DMA_DmaInitialize(
4, // Bytes per burst
1, // Bytes per burst
1, // request per burst
HI16(CYDEV_PERIPH_BASE),
HI16(CYDEV_SRAM_BASE)
@ -476,7 +479,7 @@ static void scsiPhyInitDMA()
scsiDmaTxChan =
SCSI_TX_DMA_DmaInitialize(
4, // Bytes per burst
1, // Bytes per burst
1, // request per burst
HI16(CYDEV_SRAM_BASE),
HI16(CYDEV_PERIPH_BASE)

10
software/SCSI2SD/src/sd.c
View File

@ -951,6 +951,7 @@ void sdPoll()
void sdCheckPresent()
{
static int firstCheck = 1;
// Check if there's an SD card present.
if ((scsiDev.phase == BUS_FREE) &&
(sdIOState == SD_IDLE) &&
@ -973,8 +974,12 @@ void sdCheckPresent()
{
static int firstInit = 1;
// Debounce
CyDelay(250);
// Debounce, except on startup if the card is present at
// power on
if (!firstCheck)
{
CyDelay(250);
}
if (sdInit())
{
@ -1010,6 +1015,7 @@ void sdCheckPresent()
}
}
}
firstCheck = 0;
}
#pragma GCC pop_options

240
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -391,34 +391,34 @@
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -426,9 +426,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@ -459,9 +459,13 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@ -1941,15 +1945,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1962,37 +1966,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@ -2818,8 +2822,6 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2827,9 +2829,9 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2950,8 +2952,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2959,67 +2961,67 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3189
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

240
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -391,34 +391,34 @@
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -426,9 +426,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@ -459,9 +459,13 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@ -1941,15 +1945,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1962,37 +1966,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@ -2818,8 +2822,6 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2827,9 +2829,9 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2950,8 +2952,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2959,67 +2961,67 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

240
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -459,9 +459,13 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1941,15 +1945,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1962,37 +1966,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -2818,8 +2822,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2827,9 +2829,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2950,8 +2952,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2959,67 +2961,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

240
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
; SDCard_BSPIM
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@ -459,9 +459,13 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@ -1941,15 +1945,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1962,37 +1966,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@ -2818,8 +2822,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2827,9 +2829,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2950,8 +2952,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2959,67 +2961,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

2
software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
View File

@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x04u,
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

20
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -66,7 +66,7 @@
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -76,15 +76,15 @@
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -112,9 +112,9 @@
</register>
</block>
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -151,7 +151,7 @@
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -264,7 +264,7 @@
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

12
software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -301,7 +301,7 @@
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x4000647E</baseAddress>
<baseAddress>0x40006477</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -322,7 +322,7 @@
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006474</baseAddress>
<baseAddress>0x40006473</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -343,7 +343,7 @@
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x40006462</baseAddress>
<baseAddress>0x40006465</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -498,7 +498,7 @@
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x40006469</baseAddress>
<baseAddress>0x40006466</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -653,7 +653,7 @@
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
<baseAddress>0x40006475</baseAddress>
<baseAddress>0x40006472</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -1158,7 +1158,7 @@
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x4000647A</baseAddress>
<baseAddress>0x4000647C</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>

BIN
software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
View File

Binary file not shown.

19
software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v
View File

@ -173,10 +173,10 @@ cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg
);
// DMA outputs
//assign tx_intr = f0_bus_stat;
assign tx_intr = f0_blk_stat;
//assign rx_intr = f1_bus_stat;
assign rx_intr = f1_blk_stat;
assign tx_intr = f0_bus_stat;
//assign tx_intr = f0_blk_stat;
assign rx_intr = f1_bus_stat;
//assign rx_intr = f1_blk_stat;
/////////////////////////////////////////////////////////////////////////////
// State machine
@ -207,11 +207,11 @@ always @(posedge op_clk) begin
else if (IO == IO_WRITE)
state <= STATE_TX;
// Check the output FIFO is not full.
else if (!f1_blk_stat) begin
state <= STATE_READY;
REQReg <= 1'b1;
end else begin
// Note: Cannot check whether the output FIFO is not full
// because we haven't finished writing to it yet.
// causes a rare race condition issue on fast SCSI hosts
else begin
state <= STATE_WAIT_TIL_READY;
end
end
@ -248,6 +248,7 @@ always @(posedge op_clk) begin
STATE_READY:
if (!nRST) state <= STATE_IDLE;
else if (~nACK) begin
REQReg <= 1'b0;
state <= STATE_RX;
dbxInReg[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus

188
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -452,8 +452,8 @@
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -461,9 +461,13 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB08_MSK
#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB08_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@ -497,7 +501,11 @@
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SD_SCK */
@ -1908,15 +1916,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@ -1929,37 +1937,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
@ -2787,8 +2795,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@ -2796,13 +2804,9 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@ -2923,8 +2927,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@ -2932,67 +2936,67 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB05_MSK
#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB05_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U

3302
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
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File diff suppressed because it is too large Load Diff

188
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -452,8 +452,8 @@
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -461,9 +461,13 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB08_MSK
.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB08_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@ -497,7 +501,11 @@
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SD_SCK */
@ -1908,15 +1916,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@ -1929,37 +1937,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
@ -2787,8 +2795,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@ -2796,13 +2804,9 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@ -2923,8 +2927,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@ -2932,67 +2936,67 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB05_MSK
.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB05_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000

188
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
View File

@ -452,8 +452,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -461,9 +461,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -497,7 +501,11 @@ SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SD_SCK */
@ -1908,15 +1916,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1929,37 +1937,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@ -2787,8 +2795,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2796,13 +2804,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2923,8 +2927,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2932,67 +2936,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB05_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000

188
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -452,8 +452,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -461,9 +461,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@ -497,7 +501,11 @@ SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SD_SCK
@ -1908,15 +1916,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@ -1929,37 +1937,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL
SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@ -2787,8 +2795,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@ -2796,13 +2804,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@ -2923,8 +2927,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@ -2932,67 +2936,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB05_MSK
SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB05_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000

2
software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
View File

@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x04u,
0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,

20
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
View File

@ -4,9 +4,9 @@
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Parity_Error_STATUS_REG" address="0x40006565" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_MASK_REG" address="0x40006585" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006595" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -42,9 +42,9 @@
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">
<register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
@ -76,7 +76,7 @@
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
</block>
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -153,7 +153,7 @@
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
@ -256,10 +256,10 @@
</block>
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
<register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
View File

Binary file not shown.

12
software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -9,7 +9,7 @@
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x40006465</baseAddress>
<baseAddress>0x40006565</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -164,7 +164,7 @@
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x40006468</baseAddress>
<baseAddress>0x4000646B</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -319,7 +319,7 @@
<peripheral>
<name>SCSI_Glitch_Ctl</name>
<description>No description available</description>
<baseAddress>0x4000647D</baseAddress>
<baseAddress>0x40006474</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -632,7 +632,7 @@
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
<baseAddress>0x4000647C</baseAddress>
<baseAddress>0x40006475</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -1137,7 +1137,7 @@
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006474</baseAddress>
<baseAddress>0x40006478</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
@ -1158,7 +1158,7 @@
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x40006473</baseAddress>
<baseAddress>0x40006477</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>

BIN
software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
View File

Binary file not shown.

4
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h Normal file → Executable file
View File

@ -22,9 +22,9 @@
#define BL_DUAL_APP_BOOTLOADER (0u)
#define BL_BOOTLOADER_APP_VERSION (0u)
#define BL_FAST_APP_VALIDATION (0u)
#define BL_FAST_APP_VALIDATION (1u)
#define BL_PACKET_CHECKSUM_CRC (0u)
#define BL_WAIT_FOR_COMMAND (1u)
#define BL_WAIT_FOR_COMMAND (0u)
#define BL_WAIT_FOR_COMMAND_TIME (20u)
#define BL_BOOTLOADER_APP_VALIDATION (1u)

47
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c Normal file → Executable file
View File

@ -17,6 +17,7 @@
#include "USBFS.h"
#if defined(USBFS_ENABLE_AUDIO_CLASS)
#include "USBFS_audio.h"
@ -124,6 +125,11 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#START AUDIO_READ_REQUESTS` Place other request handler here */
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK
USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK */
break;
default:
break;
@ -142,7 +148,11 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#END` */
/* Entity ID Control Selector is MUTE */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK
USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK */
/* Entity ID Control Selector is MUTE */
USBFS_currentTD.wCount = 1u;
USBFS_currentTD.pData = &USBFS_currentMute;
requestHandled = USBFS_InitControlRead();
@ -153,6 +163,10 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK
USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK */
/* Entity ID Control Selector is VOLUME, */
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;
USBFS_currentTD.pData = USBFS_currentVolume;
@ -163,6 +177,10 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK
USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK */
}
break;
case USBFS_GET_MIN: /* GET_MIN */
@ -205,6 +223,11 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK
USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK */
break;
default:
break;
@ -237,6 +260,11 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK
USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK */
break;
default:
break;
@ -255,6 +283,10 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK
USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK */
/* Entity ID Control Selector is MUTE */
USBFS_currentTD.wCount = 1u;
USBFS_currentTD.pData = &USBFS_currentMute;
@ -266,6 +298,10 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK
USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK */
/* Entity ID Control Selector is VOLUME */
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;
USBFS_currentTD.pData = USBFS_currentVolume;
@ -276,12 +312,21 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
/* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK
USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK */
}
#endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
/* `#END` */
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK
USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK */
break;
default:
break;

9
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c Normal file → Executable file
View File

@ -23,6 +23,7 @@
#include "USBFS_pvt.h"
/***************************************
* CDC Variables
***************************************/
@ -104,6 +105,10 @@ uint8 USBFS_DispatchCDCClassRqst(void)
/* `#END` */
#ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK
USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK */
default: /* requestHandled is initialized as FALSE by default */
break;
}
@ -130,6 +135,10 @@ uint8 USBFS_DispatchCDCClassRqst(void)
/* `#END` */
#ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK
USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback();
#endif /* USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK */
default: /* requestHandled is initialized as FALSE by default */
break;
}

5
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c Normal file → Executable file
View File

@ -21,6 +21,7 @@
#include "USBFS_pvt.h"
/***************************************
* User Implemented Class Driver Declarations.
***************************************/
@ -89,6 +90,10 @@ uint8 USBFS_DispatchClassRqst(void)
/* `#END` */
#ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK
USBFS_DispatchClassRqst_Callback();
#endif /* USBFS_DISPATCH_CLASS_RQST_CALLBACK */
return(requestHandled);
}

9
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c Normal file → Executable file
View File

@ -18,6 +18,7 @@
#include "USBFS_pvt.h"
/***************************************
* Global data allocation
***************************************/
@ -68,7 +69,10 @@ CY_ISR(USBFS_EP_0_ISR)
uint8 bRegTemp;
uint8 modifyReg;
#ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK
USBFS_EP_0_ISR_EntryCallback();
#endif /* USBFS_EP_0_ISR_ENTRY_CALLBACK */
bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR);
if ((bRegTemp & USBFS_MODE_ACKD) != 0u)
{
@ -128,6 +132,9 @@ CY_ISR(USBFS_EP_0_ISR)
}
}
}
#ifdef USBFS_EP_0_ISR_EXIT_CALLBACK
USBFS_EP_0_ISR_ExitCallback();
#endif /* USBFS_EP_0_ISR_EXIT_CALLBACK */
}

101
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c Normal file → Executable file
View File

@ -16,6 +16,7 @@
#include "USBFS.h"
#include "USBFS_pvt.h"
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
#include "USBFS_midi.h"
#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
@ -57,6 +58,10 @@
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
#ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK
USBFS_EP_1_ISR_EntryCallback();
#endif /* USBFS_EP_1_ISR_ENTRY_CALLBACK */
/* `#START EP1_USER_CODE` Place your code here */
/* `#END` */
@ -90,6 +95,10 @@
/* `#END` */
#ifdef USBFS_EP_1_ISR_EXIT_CALLBACK
USBFS_EP_1_ISR_ExitCallback();
#endif /* USBFS_EP_1_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -122,6 +131,10 @@
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
#ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK
USBFS_EP_2_ISR_EntryCallback();
#endif /* USBFS_EP_2_ISR_ENTRY_CALLBACK */
/* `#START EP2_USER_CODE` Place your code here */
/* `#END` */
@ -155,6 +168,10 @@
/* `#END` */
#ifdef USBFS_EP_2_ISR_EXIT_CALLBACK
USBFS_EP_2_ISR_ExitCallback();
#endif /* USBFS_EP_2_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -187,6 +204,10 @@
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
#ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK
USBFS_EP_3_ISR_EntryCallback();
#endif /* USBFS_EP_3_ISR_ENTRY_CALLBACK */
/* `#START EP3_USER_CODE` Place your code here */
/* `#END` */
@ -220,6 +241,10 @@
/* `#END` */
#ifdef USBFS_EP_3_ISR_EXIT_CALLBACK
USBFS_EP_3_ISR_ExitCallback();
#endif /* USBFS_EP_3_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -252,6 +277,10 @@
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
#ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK
USBFS_EP_4_ISR_EntryCallback();
#endif /* USBFS_EP_4_ISR_ENTRY_CALLBACK */
/* `#START EP4_USER_CODE` Place your code here */
/* `#END` */
@ -285,6 +314,10 @@
/* `#END` */
#ifdef USBFS_EP_4_ISR_EXIT_CALLBACK
USBFS_EP_4_ISR_ExitCallback();
#endif /* USBFS_EP_4_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -317,6 +350,10 @@
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
#ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK
USBFS_EP_5_ISR_EntryCallback();
#endif /* USBFS_EP_5_ISR_ENTRY_CALLBACK */
/* `#START EP5_USER_CODE` Place your code here */
/* `#END` */
@ -350,6 +387,10 @@
/* `#END` */
#ifdef USBFS_EP_5_ISR_EXIT_CALLBACK
USBFS_EP_5_ISR_ExitCallback();
#endif /* USBFS_EP_5_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -381,6 +422,10 @@
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
#ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK
USBFS_EP_6_ISR_EntryCallback();
#endif /* USBFS_EP_6_ISR_ENTRY_CALLBACK */
/* `#START EP6_USER_CODE` Place your code here */
/* `#END` */
@ -414,6 +459,10 @@
/* `#END` */
#ifdef USBFS_EP_6_ISR_EXIT_CALLBACK
USBFS_EP_6_ISR_ExitCallback();
#endif /* USBFS_EP_6_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -446,6 +495,10 @@
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
#ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK
USBFS_EP_7_ISR_EntryCallback();
#endif /* USBFS_EP_7_ISR_ENTRY_CALLBACK */
/* `#START EP7_USER_CODE` Place your code here */
/* `#END` */
@ -479,6 +532,10 @@
/* `#END` */
#ifdef USBFS_EP_7_ISR_EXIT_CALLBACK
USBFS_EP_7_ISR_ExitCallback();
#endif /* USBFS_EP_7_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -511,6 +568,10 @@
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
#ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK
USBFS_EP_8_ISR_EntryCallback();
#endif /* USBFS_EP_8_ISR_ENTRY_CALLBACK */
/* `#START EP8_USER_CODE` Place your code here */
/* `#END` */
@ -544,6 +605,10 @@
/* `#END` */
#ifdef USBFS_EP_8_ISR_EXIT_CALLBACK
USBFS_EP_8_ISR_ExitCallback();
#endif /* USBFS_EP_8_ISR_EXIT_CALLBACK */
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
@ -569,6 +634,10 @@
*******************************************************************************/
CY_ISR(USBFS_SOF_ISR)
{
#ifdef USBFS_SOF_ISR_INTERRUPT_CALLBACK
USBFS_SOF_ISR_InterruptCallback();
#endif /* USBFS_SOF_ISR_INTERRUPT_CALLBACK */
/* `#START SOF_USER_CODE` Place your code here */
/* `#END` */
@ -592,11 +661,19 @@ CY_ISR(USBFS_SOF_ISR)
*******************************************************************************/
CY_ISR(USBFS_BUS_RESET_ISR)
{
#ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK
USBFS_BUS_RESET_ISR_EntryCallback();
#endif /* USBFS_BUS_RESET_ISR_ENTRY_CALLBACK */
/* `#START BUS_RESET_USER_CODE` Place your code here */
/* `#END` */
USBFS_ReInitComponent();
#ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK
USBFS_BUS_RESET_ISR_ExitCallback();
#endif /* USBFS_BUS_RESET_ISR_EXIT_CALLBACK */
}
@ -627,6 +704,10 @@ CY_ISR(USBFS_BUS_RESET_ISR)
uint8 ep = USBFS_EP1;
uint8 ptr = 0u;
#ifdef USBFS_ARB_ISR_ENTRY_CALLBACK
USBFS_ARB_ISR_EntryCallback();
#endif /* USBFS_ARB_ISR_ENTRY_CALLBACK */
/* `#START ARB_BEGIN_USER_CODE` Place your code here */
/* `#END` */
@ -687,6 +768,10 @@ CY_ISR(USBFS_BUS_RESET_ISR)
/* `#END` */
#ifdef USBFS_ARB_ISR_CALLBACK
USBFS_ARB_ISR_Callback();
#endif /* USBFS_ARB_ISR_CALLBACK */
CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */
}
ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */
@ -697,6 +782,10 @@ CY_ISR(USBFS_BUS_RESET_ISR)
/* `#START ARB_END_USER_CODE` Place your code here */
/* `#END` */
#ifdef USBFS_ARB_ISR_EXIT_CALLBACK
USBFS_ARB_ISR_ExitCallback();
#endif /* USBFS_ARB_ISR_EXIT_CALLBACK */
}
#endif /* USBFS_EP_MM */
@ -724,6 +813,10 @@ CY_ISR(USBFS_BUS_RESET_ISR)
uint8 ep = USBFS_EP1;
uint8 ptr = 0u;
#ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK
USBFS_EP_DMA_DONE_ISR_EntryCallback();
#endif /* USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK */
/* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
/* `#END` */
@ -747,6 +840,10 @@ CY_ISR(USBFS_BUS_RESET_ISR)
/* `#END` */
#ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK
USBFS_EP_DMA_DONE_ISR_Callback();
#endif /* USBFS_EP_DMA_DONE_ISR_CALLBACK */
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
/* repeat 2 last bytes to prefetch endpoint area */
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
@ -773,6 +870,10 @@ CY_ISR(USBFS_BUS_RESET_ISR)
/* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
/* `#END` */
#ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK
USBFS_EP_DMA_DONE_ISR_ExitCallback();
#endif /* USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK */
}
#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */

6
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c Normal file → Executable file
View File

@ -25,6 +25,7 @@
#include "USBFS_hid.h"
/***************************************
* HID Variables
***************************************/
@ -375,6 +376,11 @@ void USBFS_FindReport(void)
/* `#START HID_FINDREPORT` Place custom handling here */
/* `#END` */
#ifdef USBFS_FIND_REPORT_CALLBACK
USBFS_FindReport_Callback();
#endif /* USBFS_FIND_REPORT_CALLBACK */
USBFS_currentTD.count = 0u; /* Init not supported condition */
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
reportType = CY_GET_REG8(USBFS_wValueHi);

24
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c Normal file → Executable file
View File

@ -26,6 +26,7 @@
#include "USBFS_pvt.h"
/***************************************
* MIDI Constants
***************************************/
@ -269,6 +270,10 @@ void USBFS_MIDI_EP_Init(void)
/* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */
/* `#END` */
#ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK
USBFS_MIDI_OUT_EP_Service_Callback();
#endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */
}
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
@ -732,6 +737,9 @@ void USBFS_MIDI_EP_Init(void)
/* `#END` */
#ifdef USBFS_MIDI_INIT_CALLBACK
USBFS_MIDI_Init_Callback();
#endif /* USBFS_MIDI_INIT_CALLBACK */
}
@ -1046,6 +1054,10 @@ void USBFS_MIDI_EP_Init(void)
/* `#END` */
#ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK
USBFS_MIDI1_ProcessUsbOut_EntryCallback();
#endif /* USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK */
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;
if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))
{
@ -1118,6 +1130,10 @@ void USBFS_MIDI_EP_Init(void)
/* `#START MIDI1_PROCESS_OUT_END` */
/* `#END` */
#ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK
USBFS_MIDI1_ProcessUsbOut_ExitCallback();
#endif /* USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK */
}
@ -1269,6 +1285,10 @@ void USBFS_MIDI_EP_Init(void)
/* `#END` */
#ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK
USBFS_MIDI2_ProcessUsbOut_EntryCallback();
#endif /* USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK */
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;
if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))
{
@ -1341,6 +1361,10 @@ void USBFS_MIDI_EP_Init(void)
/* `#START MIDI2_PROCESS_OUT_END` */
/* `#END` */
#ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK
USBFS_MIDI2_ProcessUsbOut_ExitCallback();
#endif /* USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK */
}
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */

9
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c Normal file → Executable file
View File

@ -19,6 +19,7 @@
#include "USBFS_pvt.h"
/***************************************
* Custom Declarations
***************************************/
@ -53,12 +54,20 @@ static USBFS_BACKUP_STRUCT USBFS_backup;
*******************************************************************************/
CY_ISR(USBFS_DP_ISR)
{
#ifdef USBFS_DP_ISR_ENTRY_CALLBACK
USBFS_DP_ISR_EntryCallback();
#endif /* USBFS_DP_ISR_ENTRY_CALLBACK */
/* `#START DP_USER_CODE` Place your code here */
/* `#END` */
/* Clears active interrupt */
CY_GET_REG8(USBFS_DP_INTSTAT_PTR);
#ifdef USBFS_DP_ISR_EXIT_CALLBACK
USBFS_DP_ISR_ExitCallback();
#endif /* USBFS_DP_ISR_EXIT_CALLBACK */
}
#endif /* (USBFS_DP_ISR_REMOVE == 0u) */

6
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c Normal file → Executable file
View File

@ -17,6 +17,7 @@
#include "USBFS.h"
#include "USBFS_pvt.h"
#if(USBFS_EXTERN_VND == USBFS_FALSE)
@ -77,6 +78,10 @@ uint8 USBFS_HandleVendorRqst(void)
/* `#END` */
#ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK
USBFS_HandleVendorRqst_Callback();
#endif /* USBFS_HANDLE_VENDOR_RQST_CALLBACK */
return(requestHandled);
}
@ -89,7 +94,6 @@ uint8 USBFS_HandleVendorRqst(void)
/* `#END` */
#endif /* USBFS_EXTERN_VND */

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h Normal file → Executable file
View File

@ -1,14 +1,14 @@
/*******************************************************************************
* FILENAME: cydevice.h
* File Name: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
* PSoC Creator 3.1
* PSoC Creator 3.3
*
* DESCRIPTION:
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h Normal file → Executable file
View File

@ -1,14 +1,14 @@
/*******************************************************************************
* FILENAME: cydevice_trm.h
* File Name: cydevice_trm.h
*
* PSoC Creator 3.1
* PSoC Creator 3.3
*
* DESCRIPTION:
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc Normal file → Executable file
View File

@ -1,14 +1,14 @@
/*******************************************************************************
* FILENAME: cydevicegnu.inc
* File Name: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
* PSoC Creator 3.1
* PSoC Creator 3.3
*
* DESCRIPTION:
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc Normal file → Executable file
View File

@ -1,14 +1,14 @@
/*******************************************************************************
* FILENAME: cydevicegnu_trm.inc
* File Name: cydevicegnu_trm.inc
*
* PSoC Creator 3.1
* PSoC Creator 3.3
*
* DESCRIPTION:
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc Normal file → Executable file
View File

@ -1,13 +1,13 @@
;
; FILENAME: cydeviceiar.inc
; File Name: cydeviceiar.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
; PSoC Creator 3.1
; PSoC Creator 3.3
;
; DESCRIPTION:
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc Normal file → Executable file
View File

@ -1,13 +1,13 @@
;
; FILENAME: cydeviceiar_trm.inc
; File Name: cydeviceiar_trm.inc
;
; PSoC Creator 3.1
; PSoC Creator 3.3
;
; DESCRIPTION:
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc Normal file → Executable file
View File

@ -1,13 +1,13 @@
;
; FILENAME: cydevicerv.inc
; File Name: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
; PSoC Creator 3.1
; PSoC Creator 3.3
;
; DESCRIPTION:
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc Normal file → Executable file
View File

@ -1,13 +1,13 @@
;
; FILENAME: cydevicerv_trm.inc
; File Name: cydevicerv_trm.inc
;
; PSoC Creator 3.1
; PSoC Creator 3.3
;
; DESCRIPTION:
; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.

107
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h Normal file → Executable file
View File

@ -1,9 +1,10 @@
#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include <cydevice.h>
#include <cydevice_trm.h>
#include "cydevice.h"
#include "cydevice_trm.h"
/* LED */
#define LED__0__INTTYPE CYREG_PICU0_INTTYPE1
#define LED__0__MASK 0x02u
#define LED__0__PC CYREG_PRT0_PC1
#define LED__0__PORT 0u
@ -19,6 +20,7 @@
#define LED__DM2 CYREG_PRT0_DM2
#define LED__DR CYREG_PRT0_DR
#define LED__INP_DIS CYREG_PRT0_INP_DIS
#define LED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define LED__LCD_EN CYREG_PRT0_LCD_EN
#define LED__MASK 0x02u
@ -56,6 +58,7 @@
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_Dm */
#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
#define USBFS_Dm__0__MASK 0x80u
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBFS_Dm__0__PORT 15u
@ -71,6 +74,7 @@
#define USBFS_Dm__DM2 CYREG_PRT15_DM2
#define USBFS_Dm__DR CYREG_PRT15_DR
#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_Dm__MASK 0x80u
@ -88,6 +92,7 @@
#define USBFS_Dm__SLW CYREG_PRT15_SLW
/* USBFS_Dp */
#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
#define USBFS_Dp__0__MASK 0x40u
#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBFS_Dp__0__PORT 15u
@ -104,6 +109,7 @@
#define USBFS_Dp__DR CYREG_PRT15_DR
#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_Dp__MASK 0x40u
@ -309,6 +315,7 @@
#define SCSI_Out__0__DM2 CYREG_PRT15_DM2
#define SCSI_Out__0__DR CYREG_PRT15_DR
#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS
#define SCSI_Out__0__INTTYPE CYREG_PICU15_INTTYPE5
#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__0__MASK 0x20u
@ -336,6 +343,7 @@
#define SCSI_Out__1__DM2 CYREG_PRT15_DM2
#define SCSI_Out__1__DR CYREG_PRT15_DR
#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS
#define SCSI_Out__1__INTTYPE CYREG_PICU15_INTTYPE4
#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__1__MASK 0x10u
@ -363,6 +371,7 @@
#define SCSI_Out__2__DM2 CYREG_PRT6_DM2
#define SCSI_Out__2__DR CYREG_PRT6_DR
#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out__2__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__2__MASK 0x02u
@ -390,6 +399,7 @@
#define SCSI_Out__3__DM2 CYREG_PRT6_DM2
#define SCSI_Out__3__DR CYREG_PRT6_DR
#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out__3__INTTYPE CYREG_PICU6_INTTYPE0
#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__3__MASK 0x01u
@ -417,6 +427,7 @@
#define SCSI_Out__4__DM2 CYREG_PRT4_DM2
#define SCSI_Out__4__DR CYREG_PRT4_DR
#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS
#define SCSI_Out__4__INTTYPE CYREG_PICU4_INTTYPE5
#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__4__MASK 0x20u
@ -444,6 +455,7 @@
#define SCSI_Out__5__DM2 CYREG_PRT4_DM2
#define SCSI_Out__5__DR CYREG_PRT4_DR
#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS
#define SCSI_Out__5__INTTYPE CYREG_PICU4_INTTYPE4
#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__5__MASK 0x10u
@ -471,6 +483,7 @@
#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
#define SCSI_Out__6__DR CYREG_PRT0_DR
#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE7
#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__6__MASK 0x80u
@ -498,6 +511,7 @@
#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
#define SCSI_Out__7__DR CYREG_PRT0_DR
#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE6
#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__7__MASK 0x40u
@ -525,6 +539,7 @@
#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
#define SCSI_Out__8__DR CYREG_PRT0_DR
#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE3
#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__8__MASK 0x08u
@ -552,6 +567,7 @@
#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
#define SCSI_Out__9__DR CYREG_PRT0_DR
#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE2
#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__9__MASK 0x04u
@ -579,6 +595,7 @@
#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2
#define SCSI_Out__ACK__DR CYREG_PRT6_DR
#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out__ACK__INTTYPE CYREG_PICU6_INTTYPE0
#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__ACK__MASK 0x01u
@ -606,6 +623,7 @@
#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2
#define SCSI_Out__ATN__DR CYREG_PRT15_DR
#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS
#define SCSI_Out__ATN__INTTYPE CYREG_PICU15_INTTYPE4
#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__ATN__MASK 0x10u
@ -633,6 +651,7 @@
#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2
#define SCSI_Out__BSY__DR CYREG_PRT6_DR
#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out__BSY__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__BSY__MASK 0x02u
@ -660,6 +679,7 @@
#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2
#define SCSI_Out__CD__DR CYREG_PRT0_DR
#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__CD__INTTYPE CYREG_PICU0_INTTYPE6
#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__CD__MASK 0x40u
@ -687,6 +707,7 @@
#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2
#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR
#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS
#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU15_INTTYPE5
#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__DBP_raw__MASK 0x20u
@ -714,6 +735,7 @@
#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE2
#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__IO_raw__MASK 0x04u
@ -741,6 +763,7 @@
#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2
#define SCSI_Out__MSG__DR CYREG_PRT4_DR
#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS
#define SCSI_Out__MSG__INTTYPE CYREG_PICU4_INTTYPE4
#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__MSG__MASK 0x10u
@ -768,6 +791,7 @@
#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
#define SCSI_Out__REQ__DR CYREG_PRT0_DR
#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE3
#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__REQ__MASK 0x08u
@ -795,6 +819,7 @@
#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2
#define SCSI_Out__RST__DR CYREG_PRT4_DR
#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS
#define SCSI_Out__RST__INTTYPE CYREG_PICU4_INTTYPE5
#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__RST__MASK 0x20u
@ -822,6 +847,7 @@
#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
#define SCSI_Out__SEL__DR CYREG_PRT0_DR
#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE7
#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__SEL__MASK 0x80u
@ -851,6 +877,7 @@
#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU5_INTTYPE1
#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__0__MASK 0x02u
@ -878,6 +905,7 @@
#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU5_INTTYPE0
#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__1__MASK 0x01u
@ -905,6 +933,7 @@
#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE5
#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__2__MASK 0x20u
@ -932,6 +961,7 @@
#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE4
#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__3__MASK 0x10u
@ -959,6 +989,7 @@
#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE7
#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__4__MASK 0x80u
@ -986,6 +1017,7 @@
#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE6
#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__5__MASK 0x40u
@ -1013,6 +1045,7 @@
#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE3
#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__6__MASK 0x08u
@ -1040,6 +1073,7 @@
#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU2_INTTYPE2
#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__7__MASK 0x04u
@ -1067,6 +1101,7 @@
#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU5_INTTYPE1
#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__DB0__MASK 0x02u
@ -1094,6 +1129,7 @@
#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU5_INTTYPE0
#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__DB1__MASK 0x01u
@ -1121,6 +1157,7 @@
#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE5
#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__DB2__MASK 0x20u
@ -1148,6 +1185,7 @@
#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE4
#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__DB3__MASK 0x10u
@ -1175,6 +1213,7 @@
#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE7
#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB4__MASK 0x80u
@ -1202,6 +1241,7 @@
#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE6
#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB5__MASK 0x40u
@ -1229,6 +1269,7 @@
#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE3
#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB6__MASK 0x08u
@ -1256,6 +1297,7 @@
#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE2
#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB7__MASK 0x04u
@ -1274,22 +1316,27 @@
#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
/* SD_PULLUP */
#define SD_PULLUP__0__INTTYPE CYREG_PICU3_INTTYPE1
#define SD_PULLUP__0__MASK 0x02u
#define SD_PULLUP__0__PC CYREG_PRT3_PC1
#define SD_PULLUP__0__PORT 3u
#define SD_PULLUP__0__SHIFT 1
#define SD_PULLUP__1__INTTYPE CYREG_PICU3_INTTYPE2
#define SD_PULLUP__1__MASK 0x04u
#define SD_PULLUP__1__PC CYREG_PRT3_PC2
#define SD_PULLUP__1__PORT 3u
#define SD_PULLUP__1__SHIFT 2
#define SD_PULLUP__2__INTTYPE CYREG_PICU3_INTTYPE3
#define SD_PULLUP__2__MASK 0x08u
#define SD_PULLUP__2__PC CYREG_PRT3_PC3
#define SD_PULLUP__2__PORT 3u
#define SD_PULLUP__2__SHIFT 3
#define SD_PULLUP__3__INTTYPE CYREG_PICU3_INTTYPE4
#define SD_PULLUP__3__MASK 0x10u
#define SD_PULLUP__3__PC CYREG_PRT3_PC4
#define SD_PULLUP__3__PORT 3u
#define SD_PULLUP__3__SHIFT 4
#define SD_PULLUP__4__INTTYPE CYREG_PICU3_INTTYPE5
#define SD_PULLUP__4__MASK 0x20u
#define SD_PULLUP__4__PC CYREG_PRT3_PC5
#define SD_PULLUP__4__PORT 3u
@ -1305,6 +1352,7 @@
#define SD_PULLUP__DM2 CYREG_PRT3_DM2
#define SD_PULLUP__DR CYREG_PRT3_DR
#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
#define SD_PULLUP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
#define SD_PULLUP__MASK 0x3Eu
@ -1325,7 +1373,8 @@
#define BCLK__BUS_CLK__HZ 64000000U
#define BCLK__BUS_CLK__KHZ 64000U
#define BCLK__BUS_CLK__MHZ 64U
#define CY_VERSION "PSoC Creator 3.1"
#define CY_PROJECT_NAME "USB_Bootloader"
#define CY_VERSION "PSoC Creator 3.3"
#define CYDEV_BOOTLOADER_APPLICATIONS 1u
#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
@ -1335,9 +1384,10 @@
#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 6u
#define CYDEV_CHIP_DIE_PSOC4A 3u
#define CYDEV_CHIP_DIE_PSOC5LP 5u
#define CYDEV_CHIP_DIE_PANTHER 18u
#define CYDEV_CHIP_DIE_PSOC4A 10u
#define CYDEV_CHIP_DIE_PSOC5LP 17u
#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
@ -1346,11 +1396,22 @@
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 3u
#define CYDEV_CHIP_MEMBER_4D 2u
#define CYDEV_CHIP_MEMBER_4F 4u
#define CYDEV_CHIP_MEMBER_5A 6u
#define CYDEV_CHIP_MEMBER_5B 5u
#define CYDEV_CHIP_MEMBER_4A 10u
#define CYDEV_CHIP_MEMBER_4C 15u
#define CYDEV_CHIP_MEMBER_4D 6u
#define CYDEV_CHIP_MEMBER_4E 4u
#define CYDEV_CHIP_MEMBER_4F 11u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 9u
#define CYDEV_CHIP_MEMBER_4I 14u
#define CYDEV_CHIP_MEMBER_4J 7u
#define CYDEV_CHIP_MEMBER_4K 8u
#define CYDEV_CHIP_MEMBER_4L 13u
#define CYDEV_CHIP_MEMBER_4M 12u
#define CYDEV_CHIP_MEMBER_4N 5u
#define CYDEV_CHIP_MEMBER_4U 3u
#define CYDEV_CHIP_MEMBER_5A 17u
#define CYDEV_CHIP_MEMBER_5B 16u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
@ -1366,14 +1427,32 @@
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
@ -1388,7 +1467,7 @@
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 0
#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
@ -1409,9 +1488,13 @@
#define CYDEV_HEAP_SIZE 0x0800
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00000000u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 1
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0

25
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c Normal file → Executable file
View File

@ -1,25 +1,26 @@
/*******************************************************************************
* FILENAME: cyfitter_cfg.c
* PSoC Creator 3.1
* File Name: cyfitter_cfg.c
*
* PSoC Creator 3.3
*
* Description:
* This file is automatically generated by PSoC Creator with device
* initialization code. Except for the user defined sections in
* CyClockStartupError(), this file should not be modified.
* This file contains device initialization code.
* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <string.h>
#include <cytypes.h>
#include <cydevice_trm.h>
#include <cyfitter.h>
#include <CyLib.h>
#include <cyfitter_cfg.h>
#include "cytypes.h"
#include "cydevice_trm.h"
#include "cyfitter.h"
#include "CyLib.h"
#include "cyfitter_cfg.h"
#define CY_NEED_CYCLOCKSTARTUPERROR 1
@ -424,6 +425,7 @@ void cyfitter_cfg(void)
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
@ -432,7 +434,6 @@ void cyfitter_cfg(void)
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
/* Switch Boost to the precision bandgap reference from its internal reference */
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));

10
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h Normal file → Executable file
View File

@ -1,12 +1,14 @@
/*******************************************************************************
* FILENAME: cyfitter_cfg.h
* PSoC Creator 3.1
* File Name: cyfitter_cfg.h
*
* PSoC Creator 3.3
*
* Description:
* This file provides basic startup and mux configration settings
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
@ -15,7 +17,7 @@
#ifndef CYFITTER_CFG_H
#define CYFITTER_CFG_H
#include <cytypes.h>
#include "cytypes.h"
extern void cyfitter_cfg(void);

100
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc Normal file → Executable file
View File

@ -4,6 +4,7 @@
.include "cydevicegnu_trm.inc"
/* LED */
.set LED__0__INTTYPE, CYREG_PICU0_INTTYPE1
.set LED__0__MASK, 0x02
.set LED__0__PC, CYREG_PRT0_PC1
.set LED__0__PORT, 0
@ -19,6 +20,7 @@
.set LED__DM2, CYREG_PRT0_DM2
.set LED__DR, CYREG_PRT0_DR
.set LED__INP_DIS, CYREG_PRT0_INP_DIS
.set LED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE
.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set LED__LCD_EN, CYREG_PRT0_LCD_EN
.set LED__MASK, 0x02
@ -56,6 +58,7 @@
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_Dm */
.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7
.set USBFS_Dm__0__MASK, 0x80
.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
.set USBFS_Dm__0__PORT, 15
@ -71,6 +74,7 @@
.set USBFS_Dm__DM2, CYREG_PRT15_DM2
.set USBFS_Dm__DR, CYREG_PRT15_DR
.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
.set USBFS_Dm__MASK, 0x80
@ -88,6 +92,7 @@
.set USBFS_Dm__SLW, CYREG_PRT15_SLW
/* USBFS_Dp */
.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6
.set USBFS_Dp__0__MASK, 0x40
.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
.set USBFS_Dp__0__PORT, 15
@ -104,6 +109,7 @@
.set USBFS_Dp__DR, CYREG_PRT15_DR
.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
.set USBFS_Dp__MASK, 0x40
@ -309,6 +315,7 @@
.set SCSI_Out__0__DM2, CYREG_PRT15_DM2
.set SCSI_Out__0__DR, CYREG_PRT15_DR
.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS
.set SCSI_Out__0__INTTYPE, CYREG_PICU15_INTTYPE5
.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__0__MASK, 0x20
@ -336,6 +343,7 @@
.set SCSI_Out__1__DM2, CYREG_PRT15_DM2
.set SCSI_Out__1__DR, CYREG_PRT15_DR
.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS
.set SCSI_Out__1__INTTYPE, CYREG_PICU15_INTTYPE4
.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__1__MASK, 0x10
@ -363,6 +371,7 @@
.set SCSI_Out__2__DM2, CYREG_PRT6_DM2
.set SCSI_Out__2__DR, CYREG_PRT6_DR
.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out__2__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__2__MASK, 0x02
@ -390,6 +399,7 @@
.set SCSI_Out__3__DM2, CYREG_PRT6_DM2
.set SCSI_Out__3__DR, CYREG_PRT6_DR
.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out__3__INTTYPE, CYREG_PICU6_INTTYPE0
.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__3__MASK, 0x01
@ -417,6 +427,7 @@
.set SCSI_Out__4__DM2, CYREG_PRT4_DM2
.set SCSI_Out__4__DR, CYREG_PRT4_DR
.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS
.set SCSI_Out__4__INTTYPE, CYREG_PICU4_INTTYPE5
.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__4__MASK, 0x20
@ -444,6 +455,7 @@
.set SCSI_Out__5__DM2, CYREG_PRT4_DM2
.set SCSI_Out__5__DR, CYREG_PRT4_DR
.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS
.set SCSI_Out__5__INTTYPE, CYREG_PICU4_INTTYPE4
.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__5__MASK, 0x10
@ -471,6 +483,7 @@
.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
.set SCSI_Out__6__DR, CYREG_PRT0_DR
.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE7
.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__6__MASK, 0x80
@ -498,6 +511,7 @@
.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
.set SCSI_Out__7__DR, CYREG_PRT0_DR
.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE6
.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__7__MASK, 0x40
@ -525,6 +539,7 @@
.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
.set SCSI_Out__8__DR, CYREG_PRT0_DR
.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE3
.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__8__MASK, 0x08
@ -552,6 +567,7 @@
.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
.set SCSI_Out__9__DR, CYREG_PRT0_DR
.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE2
.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__9__MASK, 0x04
@ -579,6 +595,7 @@
.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2
.set SCSI_Out__ACK__DR, CYREG_PRT6_DR
.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out__ACK__INTTYPE, CYREG_PICU6_INTTYPE0
.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__ACK__MASK, 0x01
@ -606,6 +623,7 @@
.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2
.set SCSI_Out__ATN__DR, CYREG_PRT15_DR
.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS
.set SCSI_Out__ATN__INTTYPE, CYREG_PICU15_INTTYPE4
.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__ATN__MASK, 0x10
@ -633,6 +651,7 @@
.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2
.set SCSI_Out__BSY__DR, CYREG_PRT6_DR
.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out__BSY__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__BSY__MASK, 0x02
@ -660,6 +679,7 @@
.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2
.set SCSI_Out__CD__DR, CYREG_PRT0_DR
.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__CD__INTTYPE, CYREG_PICU0_INTTYPE6
.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__CD__MASK, 0x40
@ -687,6 +707,7 @@
.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2
.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR
.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS
.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU15_INTTYPE5
.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__DBP_raw__MASK, 0x20
@ -714,6 +735,7 @@
.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE2
.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__IO_raw__MASK, 0x04
@ -741,6 +763,7 @@
.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2
.set SCSI_Out__MSG__DR, CYREG_PRT4_DR
.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS
.set SCSI_Out__MSG__INTTYPE, CYREG_PICU4_INTTYPE4
.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__MSG__MASK, 0x10
@ -768,6 +791,7 @@
.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE3
.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__REQ__MASK, 0x08
@ -795,6 +819,7 @@
.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2
.set SCSI_Out__RST__DR, CYREG_PRT4_DR
.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS
.set SCSI_Out__RST__INTTYPE, CYREG_PICU4_INTTYPE5
.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__RST__MASK, 0x20
@ -822,6 +847,7 @@
.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE7
.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__SEL__MASK, 0x80
@ -851,6 +877,7 @@
.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU5_INTTYPE1
.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__0__MASK, 0x02
@ -878,6 +905,7 @@
.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU5_INTTYPE0
.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__1__MASK, 0x01
@ -905,6 +933,7 @@
.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE5
.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__2__MASK, 0x20
@ -932,6 +961,7 @@
.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE4
.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__3__MASK, 0x10
@ -959,6 +989,7 @@
.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE7
.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__4__MASK, 0x80
@ -986,6 +1017,7 @@
.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE6
.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__5__MASK, 0x40
@ -1013,6 +1045,7 @@
.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE3
.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__6__MASK, 0x08
@ -1040,6 +1073,7 @@
.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE2
.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__7__MASK, 0x04
@ -1067,6 +1101,7 @@
.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU5_INTTYPE1
.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__DB0__MASK, 0x02
@ -1094,6 +1129,7 @@
.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU5_INTTYPE0
.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__DB1__MASK, 0x01
@ -1121,6 +1157,7 @@
.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE5
.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__DB2__MASK, 0x20
@ -1148,6 +1185,7 @@
.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE4
.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__DB3__MASK, 0x10
@ -1175,6 +1213,7 @@
.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE7
.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB4__MASK, 0x80
@ -1202,6 +1241,7 @@
.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE6
.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB5__MASK, 0x40
@ -1229,6 +1269,7 @@
.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE3
.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB6__MASK, 0x08
@ -1256,6 +1297,7 @@
.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE2
.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB7__MASK, 0x04
@ -1274,22 +1316,27 @@
.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
/* SD_PULLUP */
.set SD_PULLUP__0__INTTYPE, CYREG_PICU3_INTTYPE1
.set SD_PULLUP__0__MASK, 0x02
.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
.set SD_PULLUP__0__PORT, 3
.set SD_PULLUP__0__SHIFT, 1
.set SD_PULLUP__1__INTTYPE, CYREG_PICU3_INTTYPE2
.set SD_PULLUP__1__MASK, 0x04
.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
.set SD_PULLUP__1__PORT, 3
.set SD_PULLUP__1__SHIFT, 2
.set SD_PULLUP__2__INTTYPE, CYREG_PICU3_INTTYPE3
.set SD_PULLUP__2__MASK, 0x08
.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
.set SD_PULLUP__2__PORT, 3
.set SD_PULLUP__2__SHIFT, 3
.set SD_PULLUP__3__INTTYPE, CYREG_PICU3_INTTYPE4
.set SD_PULLUP__3__MASK, 0x10
.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
.set SD_PULLUP__3__PORT, 3
.set SD_PULLUP__3__SHIFT, 4
.set SD_PULLUP__4__INTTYPE, CYREG_PICU3_INTTYPE5
.set SD_PULLUP__4__MASK, 0x20
.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
.set SD_PULLUP__4__PORT, 3
@ -1305,6 +1352,7 @@
.set SD_PULLUP__DM2, CYREG_PRT3_DM2
.set SD_PULLUP__DR, CYREG_PRT3_DR
.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
.set SD_PULLUP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
.set SD_PULLUP__MASK, 0x3E
@ -1334,9 +1382,10 @@
.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS
.set CYDEV_CHIP_DIE_LEOPARD, 1
.set CYDEV_CHIP_DIE_PANTHER, 6
.set CYDEV_CHIP_DIE_PSOC4A, 3
.set CYDEV_CHIP_DIE_PSOC5LP, 5
.set CYDEV_CHIP_DIE_PANTHER, 18
.set CYDEV_CHIP_DIE_PSOC4A, 10
.set CYDEV_CHIP_DIE_PSOC5LP, 17
.set CYDEV_CHIP_DIE_TMA4, 2
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
@ -1345,11 +1394,22 @@
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
.set CYDEV_CHIP_JTAG_ID, 0x2E133069
.set CYDEV_CHIP_MEMBER_3A, 1
.set CYDEV_CHIP_MEMBER_4A, 3
.set CYDEV_CHIP_MEMBER_4D, 2
.set CYDEV_CHIP_MEMBER_4F, 4
.set CYDEV_CHIP_MEMBER_5A, 6
.set CYDEV_CHIP_MEMBER_5B, 5
.set CYDEV_CHIP_MEMBER_4A, 10
.set CYDEV_CHIP_MEMBER_4C, 15
.set CYDEV_CHIP_MEMBER_4D, 6
.set CYDEV_CHIP_MEMBER_4E, 4
.set CYDEV_CHIP_MEMBER_4F, 11
.set CYDEV_CHIP_MEMBER_4G, 2
.set CYDEV_CHIP_MEMBER_4H, 9
.set CYDEV_CHIP_MEMBER_4I, 14
.set CYDEV_CHIP_MEMBER_4J, 7
.set CYDEV_CHIP_MEMBER_4K, 8
.set CYDEV_CHIP_MEMBER_4L, 13
.set CYDEV_CHIP_MEMBER_4M, 12
.set CYDEV_CHIP_MEMBER_4N, 5
.set CYDEV_CHIP_MEMBER_4U, 3
.set CYDEV_CHIP_MEMBER_5A, 17
.set CYDEV_CHIP_MEMBER_5B, 16
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
@ -1365,14 +1425,32 @@
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REV_TMA4_ES, 17
.set CYDEV_CHIP_REV_TMA4_ES2, 33
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
.set CYDEV_CHIP_REVISION_4G_ES, 17
.set CYDEV_CHIP_REVISION_4G_ES2, 33
.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
@ -1387,7 +1465,7 @@
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_DMA, 0
.set CYDEV_CONFIGURATION_ECC, 0
.set CYDEV_CONFIGURATION_ECC, 1
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
@ -1408,9 +1486,13 @@
.set CYDEV_HEAP_SIZE, 0x0800
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
.set CYDEV_INTR_RISING, 0x00000000
.set CYDEV_IS_EXPORTING_CODE, 0
.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 1
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_PROTECTION_ENABLE, 0

100
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc Normal file → Executable file
View File

@ -4,6 +4,7 @@
INCLUDE cydeviceiar_trm.inc
/* LED */
LED__0__INTTYPE EQU CYREG_PICU0_INTTYPE1
LED__0__MASK EQU 0x02
LED__0__PC EQU CYREG_PRT0_PC1
LED__0__PORT EQU 0
@ -19,6 +20,7 @@ LED__DM1 EQU CYREG_PRT0_DM1
LED__DM2 EQU CYREG_PRT0_DM2
LED__DR EQU CYREG_PRT0_DR
LED__INP_DIS EQU CYREG_PRT0_INP_DIS
LED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
LED__LCD_EN EQU CYREG_PRT0_LCD_EN
LED__MASK EQU 0x02
@ -56,6 +58,7 @@ USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_Dm */
USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBFS_Dm__0__PORT EQU 15
@ -71,6 +74,7 @@ USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
USBFS_Dm__DR EQU CYREG_PRT15_DR
USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dm__MASK EQU 0x80
@ -88,6 +92,7 @@ USBFS_Dm__SHIFT EQU 7
USBFS_Dm__SLW EQU CYREG_PRT15_SLW
/* USBFS_Dp */
USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
USBFS_Dp__0__MASK EQU 0x40
USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBFS_Dp__0__PORT EQU 15
@ -104,6 +109,7 @@ USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
USBFS_Dp__DR EQU CYREG_PRT15_DR
USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dp__MASK EQU 0x40
@ -309,6 +315,7 @@ SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__0__DR EQU CYREG_PRT15_DR
SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__0__MASK EQU 0x20
@ -336,6 +343,7 @@ SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__1__DR EQU CYREG_PRT15_DR
SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__1__MASK EQU 0x10
@ -363,6 +371,7 @@ SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__2__DR EQU CYREG_PRT6_DR
SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__2__MASK EQU 0x02
@ -390,6 +399,7 @@ SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__3__DR EQU CYREG_PRT6_DR
SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__3__MASK EQU 0x01
@ -417,6 +427,7 @@ SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__4__DR EQU CYREG_PRT4_DR
SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__4__MASK EQU 0x20
@ -444,6 +455,7 @@ SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__5__DR EQU CYREG_PRT4_DR
SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__5__MASK EQU 0x10
@ -471,6 +483,7 @@ SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__6__DR EQU CYREG_PRT0_DR
SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__6__MASK EQU 0x80
@ -498,6 +511,7 @@ SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__7__DR EQU CYREG_PRT0_DR
SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__7__MASK EQU 0x40
@ -525,6 +539,7 @@ SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__8__DR EQU CYREG_PRT0_DR
SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__8__MASK EQU 0x08
@ -552,6 +567,7 @@ SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__9__DR EQU CYREG_PRT0_DR
SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__9__MASK EQU 0x04
@ -579,6 +595,7 @@ SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__ACK__MASK EQU 0x01
@ -606,6 +623,7 @@ SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__ATN__MASK EQU 0x10
@ -633,6 +651,7 @@ SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__BSY__MASK EQU 0x02
@ -660,6 +679,7 @@ SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD__DR EQU CYREG_PRT0_DR
SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__CD__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD__MASK EQU 0x40
@ -687,6 +707,7 @@ SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__DBP_raw__MASK EQU 0x20
@ -714,6 +735,7 @@ SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__IO_raw__MASK EQU 0x04
@ -741,6 +763,7 @@ SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG__MASK EQU 0x10
@ -768,6 +791,7 @@ SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__REQ__MASK EQU 0x08
@ -795,6 +819,7 @@ SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__RST__DR EQU CYREG_PRT4_DR
SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__RST__MASK EQU 0x20
@ -822,6 +847,7 @@ SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__SEL__MASK EQU 0x80
@ -851,6 +877,7 @@ SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__0__MASK EQU 0x02
@ -878,6 +905,7 @@ SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__1__MASK EQU 0x01
@ -905,6 +933,7 @@ SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__2__MASK EQU 0x20
@ -932,6 +961,7 @@ SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__3__MASK EQU 0x10
@ -959,6 +989,7 @@ SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__4__MASK EQU 0x80
@ -986,6 +1017,7 @@ SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__5__MASK EQU 0x40
@ -1013,6 +1045,7 @@ SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__6__MASK EQU 0x08
@ -1040,6 +1073,7 @@ SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__7__MASK EQU 0x04
@ -1067,6 +1101,7 @@ SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB0__MASK EQU 0x02
@ -1094,6 +1129,7 @@ SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB1__MASK EQU 0x01
@ -1121,6 +1157,7 @@ SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB2__MASK EQU 0x20
@ -1148,6 +1185,7 @@ SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB3__MASK EQU 0x10
@ -1175,6 +1213,7 @@ SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB4__MASK EQU 0x80
@ -1202,6 +1241,7 @@ SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB5__MASK EQU 0x40
@ -1229,6 +1269,7 @@ SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB6__MASK EQU 0x08
@ -1256,6 +1297,7 @@ SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB7__MASK EQU 0x04
@ -1274,22 +1316,27 @@ SCSI_Out_DBx__DB7__SHIFT EQU 2
SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
/* SD_PULLUP */
SD_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
SD_PULLUP__0__MASK EQU 0x02
SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
SD_PULLUP__0__PORT EQU 3
SD_PULLUP__0__SHIFT EQU 1
SD_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE2
SD_PULLUP__1__MASK EQU 0x04
SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
SD_PULLUP__1__PORT EQU 3
SD_PULLUP__1__SHIFT EQU 2
SD_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE3
SD_PULLUP__2__MASK EQU 0x08
SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
SD_PULLUP__2__PORT EQU 3
SD_PULLUP__2__SHIFT EQU 3
SD_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE4
SD_PULLUP__3__MASK EQU 0x10
SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
SD_PULLUP__3__PORT EQU 3
SD_PULLUP__3__SHIFT EQU 4
SD_PULLUP__4__INTTYPE EQU CYREG_PICU3_INTTYPE5
SD_PULLUP__4__MASK EQU 0x20
SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
SD_PULLUP__4__PORT EQU 3
@ -1305,6 +1352,7 @@ SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
SD_PULLUP__DR EQU CYREG_PRT3_DR
SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
SD_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
SD_PULLUP__MASK EQU 0x3E
@ -1334,9 +1382,10 @@ CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 6
CYDEV_CHIP_DIE_PSOC4A EQU 3
CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_PANTHER EQU 18
CYDEV_CHIP_DIE_PSOC4A EQU 10
CYDEV_CHIP_DIE_PSOC5LP EQU 17
CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
@ -1345,11 +1394,22 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 3
CYDEV_CHIP_MEMBER_4D EQU 2
CYDEV_CHIP_MEMBER_4F EQU 4
CYDEV_CHIP_MEMBER_5A EQU 6
CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_4A EQU 10
CYDEV_CHIP_MEMBER_4C EQU 15
CYDEV_CHIP_MEMBER_4D EQU 6
CYDEV_CHIP_MEMBER_4E EQU 4
CYDEV_CHIP_MEMBER_4F EQU 11
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 9
CYDEV_CHIP_MEMBER_4I EQU 14
CYDEV_CHIP_MEMBER_4J EQU 7
CYDEV_CHIP_MEMBER_4K EQU 8
CYDEV_CHIP_MEMBER_4L EQU 13
CYDEV_CHIP_MEMBER_4M EQU 12
CYDEV_CHIP_MEMBER_4N EQU 5
CYDEV_CHIP_MEMBER_4U EQU 3
CYDEV_CHIP_MEMBER_5A EQU 17
CYDEV_CHIP_MEMBER_5B EQU 16
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
@ -1365,14 +1425,32 @@ CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
@ -1387,7 +1465,7 @@ CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
@ -1408,9 +1486,13 @@ CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0800
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000000
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 1
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0

100
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc Normal file → Executable file
View File

@ -4,6 +4,7 @@ INCLUDED_CYFITTERRV_INC EQU 1
GET cydevicerv_trm.inc
; LED
LED__0__INTTYPE EQU CYREG_PICU0_INTTYPE1
LED__0__MASK EQU 0x02
LED__0__PC EQU CYREG_PRT0_PC1
LED__0__PORT EQU 0
@ -19,6 +20,7 @@ LED__DM1 EQU CYREG_PRT0_DM1
LED__DM2 EQU CYREG_PRT0_DM2
LED__DR EQU CYREG_PRT0_DR
LED__INP_DIS EQU CYREG_PRT0_INP_DIS
LED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
LED__LCD_EN EQU CYREG_PRT0_LCD_EN
LED__MASK EQU 0x02
@ -56,6 +58,7 @@ USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_Dm
USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBFS_Dm__0__PORT EQU 15
@ -71,6 +74,7 @@ USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
USBFS_Dm__DR EQU CYREG_PRT15_DR
USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dm__MASK EQU 0x80
@ -88,6 +92,7 @@ USBFS_Dm__SHIFT EQU 7
USBFS_Dm__SLW EQU CYREG_PRT15_SLW
; USBFS_Dp
USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
USBFS_Dp__0__MASK EQU 0x40
USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBFS_Dp__0__PORT EQU 15
@ -104,6 +109,7 @@ USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
USBFS_Dp__DR EQU CYREG_PRT15_DR
USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dp__MASK EQU 0x40
@ -309,6 +315,7 @@ SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__0__DR EQU CYREG_PRT15_DR
SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__0__MASK EQU 0x20
@ -336,6 +343,7 @@ SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__1__DR EQU CYREG_PRT15_DR
SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__1__MASK EQU 0x10
@ -363,6 +371,7 @@ SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__2__DR EQU CYREG_PRT6_DR
SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__2__MASK EQU 0x02
@ -390,6 +399,7 @@ SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__3__DR EQU CYREG_PRT6_DR
SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__3__MASK EQU 0x01
@ -417,6 +427,7 @@ SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__4__DR EQU CYREG_PRT4_DR
SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__4__MASK EQU 0x20
@ -444,6 +455,7 @@ SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__5__DR EQU CYREG_PRT4_DR
SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__5__MASK EQU 0x10
@ -471,6 +483,7 @@ SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__6__DR EQU CYREG_PRT0_DR
SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__6__MASK EQU 0x80
@ -498,6 +511,7 @@ SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__7__DR EQU CYREG_PRT0_DR
SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__7__MASK EQU 0x40
@ -525,6 +539,7 @@ SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__8__DR EQU CYREG_PRT0_DR
SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__8__MASK EQU 0x08
@ -552,6 +567,7 @@ SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__9__DR EQU CYREG_PRT0_DR
SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__9__MASK EQU 0x04
@ -579,6 +595,7 @@ SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__ACK__MASK EQU 0x01
@ -606,6 +623,7 @@ SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__ATN__MASK EQU 0x10
@ -633,6 +651,7 @@ SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__BSY__MASK EQU 0x02
@ -660,6 +679,7 @@ SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD__DR EQU CYREG_PRT0_DR
SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__CD__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD__MASK EQU 0x40
@ -687,6 +707,7 @@ SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__DBP_raw__MASK EQU 0x20
@ -714,6 +735,7 @@ SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__IO_raw__MASK EQU 0x04
@ -741,6 +763,7 @@ SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG__MASK EQU 0x10
@ -768,6 +791,7 @@ SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__REQ__MASK EQU 0x08
@ -795,6 +819,7 @@ SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__RST__DR EQU CYREG_PRT4_DR
SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__RST__MASK EQU 0x20
@ -822,6 +847,7 @@ SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__SEL__MASK EQU 0x80
@ -851,6 +877,7 @@ SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__0__MASK EQU 0x02
@ -878,6 +905,7 @@ SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__1__MASK EQU 0x01
@ -905,6 +933,7 @@ SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__2__MASK EQU 0x20
@ -932,6 +961,7 @@ SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__3__MASK EQU 0x10
@ -959,6 +989,7 @@ SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__4__MASK EQU 0x80
@ -986,6 +1017,7 @@ SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__5__MASK EQU 0x40
@ -1013,6 +1045,7 @@ SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__6__MASK EQU 0x08
@ -1040,6 +1073,7 @@ SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__7__MASK EQU 0x04
@ -1067,6 +1101,7 @@ SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB0__MASK EQU 0x02
@ -1094,6 +1129,7 @@ SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB1__MASK EQU 0x01
@ -1121,6 +1157,7 @@ SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB2__MASK EQU 0x20
@ -1148,6 +1185,7 @@ SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB3__MASK EQU 0x10
@ -1175,6 +1213,7 @@ SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB4__MASK EQU 0x80
@ -1202,6 +1241,7 @@ SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB5__MASK EQU 0x40
@ -1229,6 +1269,7 @@ SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB6__MASK EQU 0x08
@ -1256,6 +1297,7 @@ SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB7__MASK EQU 0x04
@ -1274,22 +1316,27 @@ SCSI_Out_DBx__DB7__SHIFT EQU 2
SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
; SD_PULLUP
SD_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
SD_PULLUP__0__MASK EQU 0x02
SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
SD_PULLUP__0__PORT EQU 3
SD_PULLUP__0__SHIFT EQU 1
SD_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE2
SD_PULLUP__1__MASK EQU 0x04
SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
SD_PULLUP__1__PORT EQU 3
SD_PULLUP__1__SHIFT EQU 2
SD_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE3
SD_PULLUP__2__MASK EQU 0x08
SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
SD_PULLUP__2__PORT EQU 3
SD_PULLUP__2__SHIFT EQU 3
SD_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE4
SD_PULLUP__3__MASK EQU 0x10
SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
SD_PULLUP__3__PORT EQU 3
SD_PULLUP__3__SHIFT EQU 4
SD_PULLUP__4__INTTYPE EQU CYREG_PICU3_INTTYPE5
SD_PULLUP__4__MASK EQU 0x20
SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
SD_PULLUP__4__PORT EQU 3
@ -1305,6 +1352,7 @@ SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
SD_PULLUP__DR EQU CYREG_PRT3_DR
SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
SD_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
SD_PULLUP__MASK EQU 0x3E
@ -1334,9 +1382,10 @@ CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 6
CYDEV_CHIP_DIE_PSOC4A EQU 3
CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_PANTHER EQU 18
CYDEV_CHIP_DIE_PSOC4A EQU 10
CYDEV_CHIP_DIE_PSOC5LP EQU 17
CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
@ -1345,11 +1394,22 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 3
CYDEV_CHIP_MEMBER_4D EQU 2
CYDEV_CHIP_MEMBER_4F EQU 4
CYDEV_CHIP_MEMBER_5A EQU 6
CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_4A EQU 10
CYDEV_CHIP_MEMBER_4C EQU 15
CYDEV_CHIP_MEMBER_4D EQU 6
CYDEV_CHIP_MEMBER_4E EQU 4
CYDEV_CHIP_MEMBER_4F EQU 11
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 9
CYDEV_CHIP_MEMBER_4I EQU 14
CYDEV_CHIP_MEMBER_4J EQU 7
CYDEV_CHIP_MEMBER_4K EQU 8
CYDEV_CHIP_MEMBER_4L EQU 13
CYDEV_CHIP_MEMBER_4M EQU 12
CYDEV_CHIP_MEMBER_4N EQU 5
CYDEV_CHIP_MEMBER_4U EQU 3
CYDEV_CHIP_MEMBER_5A EQU 17
CYDEV_CHIP_MEMBER_5B EQU 16
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
@ -1365,14 +1425,32 @@ CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REV_TMA4_ES EQU 17
CYDEV_CHIP_REV_TMA4_ES2 EQU 33
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
@ -1387,7 +1465,7 @@ CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
@ -1408,9 +1486,13 @@ CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0800
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000000
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 1
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0

8
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c Normal file → Executable file
View File

@ -1,14 +1,14 @@
/*******************************************************************************
* FILENAME: cymetadata.c
* File Name: cymetadata.c
*
* PSoC Creator 3.1
* PSoC Creator 3.3
*
* DESCRIPTION:
* Description:
* This file defines all extra memory spaces that need to be included.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.

0
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex Normal file → Executable file
View File

96
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h Normal file → Executable file
View File

@ -1,53 +1,53 @@
/*******************************************************************************
* File Name: project.h
* PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator and should not
* be edited by hand.
*
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
* File Name: project.h
*
* PSoC Creator 3.3
*
* Description:
* It contains references to all generated header files and should not be modified.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <cyfitter_cfg.h>
#include <cydevice.h>
#include <cydevice_trm.h>
#include <cyfitter.h>
#include <cydisabledsheets.h>
#include <USBFS.h>
#include <USBFS_audio.h>
#include <USBFS_cdc.h>
#include <USBFS_hid.h>
#include <USBFS_midi.h>
#include <USBFS_pvt.h>
#include <BL.h>
#include <BL_PVT.h>
#include <SCSI_Out_DBx_aliases.h>
#include <SCSI_Out_aliases.h>
#include <SD_PULLUP_aliases.h>
#include <SD_PULLUP.h>
#include <LED_aliases.h>
#include <LED.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>
#include <USBFS_Dp.h>
#include <core_cm3_psoc5.h>
#include <core_cm3.h>
#include <CyDmac.h>
#include <CyFlash.h>
#include <CyLib.h>
#include <cypins.h>
#include <cyPm.h>
#include <CySpc.h>
#include <cytypes.h>
#include <core_cmFunc.h>
#include <core_cmInstr.h>
#include "cyfitter_cfg.h"
#include "cydevice.h"
#include "cydevice_trm.h"
#include "cyfitter.h"
#include "cydisabledsheets.h"
#include "USBFS.h"
#include "USBFS_audio.h"
#include "USBFS_cdc.h"
#include "USBFS_hid.h"
#include "USBFS_midi.h"
#include "USBFS_pvt.h"
#include "BL.h"
#include "BL_PVT.h"
#include "SCSI_Out_DBx_aliases.h"
#include "SCSI_Out_aliases.h"
#include "SD_PULLUP_aliases.h"
#include "SD_PULLUP.h"
#include "LED_aliases.h"
#include "LED.h"
#include "USBFS_Dm_aliases.h"
#include "USBFS_Dm.h"
#include "USBFS_Dp_aliases.h"
#include "USBFS_Dp.h"
#include "core_cm3_psoc5.h"
#include "core_cm3.h"
#include "CyDmac.h"
#include "CyFlash.h"
#include "CyLib.h"
#include "cypins.h"
#include "cyPm.h"
#include "CySpc.h"
#include "cytypes.h"
#include "core_cmFunc.h"
#include "core_cmInstr.h"
/*[]*/

0
software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/protect.hex Normal file → Executable file
View File

BIN
software/SCSI2SD/v4/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch
View File

Binary file not shown.

129
software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cycdx
View File

@ -1,102 +1,103 @@
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="LED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
<block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="LED" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0" hidden="false">
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
<field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
<field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" />
<register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" />
<register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register">
<register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" hidden="false" />
<register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" hidden="false" />
<register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register" hidden="false">
<field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />
<field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />
</register>
<register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register">
<register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
<field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register">
<register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
<field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override">
<register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override" hidden="false">
<field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" />
<register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" />
<register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" />
<register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" />
<register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" />
<register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" />
<register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
<register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
<register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
<register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" hidden="false" />
<register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" hidden="false" />
<register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" hidden="false" />
<register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" hidden="false" />
<register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" hidden="false" />
<register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" hidden="false" />
<register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" hidden="false" />
<register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" hidden="false" />
<register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0" hidden="false">
<field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
<field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
<register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1" hidden="false">
<field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />
<field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />
<field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />
<field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" />
<register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0">
<register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" hidden="false" />
<register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0" hidden="false">
<field name="rd" from="0" to="0" access="R" resetVal="" desc="" />
<field name="td" from="5" to="5" access="RW" resetVal="" desc="" />
<field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1">
<register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1" hidden="false">
<field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />
<field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />
<field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />
<field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" />
<register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" />
<register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" />
<register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" />
<register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" />
<register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" />
<register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" />
<register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" />
<register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" />
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
<register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" hidden="false" />
<register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" hidden="false" />
<register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" hidden="false" />
<register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" hidden="false" />
<register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" hidden="false" />
<register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" hidden="false" />
<register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" hidden="false" />
<register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="false" />
<register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="false" />
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />
</block>
<block name="BL" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="BL" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</blockRegMap>

BIN
software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cydwr
View File

Binary file not shown.

BIN
software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit
View File

Binary file not shown.

116
software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyprj
View File

@ -926,6 +926,24 @@
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="cycodeshareimport.ld" persistent=".\Generated_Source\PSoC5\cycodeshareimport.ld">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="cycodeshareimport.scat" persistent=".\Generated_Source\PSoC5\cycodeshareimport.scat">
<Hidden v="False" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<PropertyDeltas />
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@ -947,7 +965,6 @@
<GlobalPages />
<GlobalTools name="Code Generation">
<GlobalPages>
<name_val_pair name="General@Application Type" v="Bootloader" />
<name_val_pair name="General@Custom Code Gen Options" v="" />
<name_val_pair name="General@Skip Code Generation" v="False" />
<name_val_pair name="General@Custom Synthesis Options" v="" />
@ -995,6 +1012,7 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
@ -1002,11 +1020,9 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@ -1030,6 +1046,7 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Libraries" v="" />
@ -1037,11 +1054,9 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable printf Float" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@ -1065,6 +1080,7 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
@ -1072,11 +1088,9 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Enable printf Float" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@ -1100,6 +1114,7 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />
@ -1107,11 +1122,9 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable printf Float" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
</name>
@ -1139,6 +1152,7 @@
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
@ -1146,11 +1160,9 @@
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable printf Float" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Optimization Level" v="None" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
@ -1174,6 +1186,7 @@
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
@ -1181,11 +1194,9 @@
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Link Files" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable printf Float" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Optimization Level" v="None" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
</name>
@ -1193,53 +1204,7 @@
<platform>
<name v="5bca58cd-5542-421c-b08d-9513dbb687fd">
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Generate List Files" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Strict Compilation" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate List Files" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
</name>
</platform>
<platform>
@ -1263,6 +1228,7 @@
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use MicroLib" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
@ -1287,6 +1253,7 @@
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use MicroLib" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
@ -1294,14 +1261,21 @@
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
</name>
</platform>
<platform>
<name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M&lt;&gt; -w+ -r -DNDEBUG --fpu None" />
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --config Generated_Source\PSoC5\Cm3Iar.icf" />
</name>
</platform>
</platforms>
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />
<project_current_processor v="CortexM3" />
<component_generation v="PSoC Creator 3.0" />
<last_selected_tab v="Cypress" />
<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1)" />
<WriteAppVersionLastSavedWith v="3.1.0.1570" />
<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
<WriteAppVersionLastSavedWith v="3.3.0.410" />
<WriteAppMarketingVersionLastSavedWith v=" 3.3" />
<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
<top_block v="TopDesign" />
@ -1314,7 +1288,5 @@
<ignored_deps />
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
<boot_component v="cy_boot_v4_20" />
<BootloaderTag hexFile="" elfFile="" />
<current_generation v="0" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
<current_generation v="0" /><BootloaderTag hexFile="" elfFile="" /></CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
</CyXmlSerializer>

4
software/include/scsi2sd.h
View File

@ -91,7 +91,9 @@ typedef enum
CONFIG_ENABLE_SCSI2 = 4,
CONFIG_DISABLE_GLITCH = 8,
CONFIG_ENABLE_CACHE = 16,
CONFIG_ENABLE_DISCONNECT = 32
CONFIG_ENABLE_DISCONNECT = 32,
CONFIG_ENABLE_SEL_LATCH = 64,
CONFIG_MAP_LUNS_TO_IDS = 128
} CONFIG_FLAGS;
typedef enum

26
software/scsi2sd-util/BoardPanel.cc
View File

@ -53,7 +53,7 @@ BoardPanel::BoardPanel(wxWindow* parent, const BoardConfig& initialConfig) :
myParent(parent),
myDelayValidator(new wxIntegerValidator<uint8_t>)
{
wxFlexGridSizer *fgs = new wxFlexGridSizer(8, 2, 9, 25);
wxFlexGridSizer *fgs = new wxFlexGridSizer(10, 2, 9, 25);
fgs->Add(new wxStaticText(this, wxID_ANY, _("Startup Delay (seconds)")));
myStartDelayCtrl =
@ -136,6 +136,24 @@ BoardPanel::BoardPanel(wxWindow* parent, const BoardConfig& initialConfig) :
myDisconnectCtrl->SetToolTip(_("Release the SCSI bus while waiting for SD card writes to complete. Must also be enabled in host OS."));
fgs->Add(myDisconnectCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
mySelLatchCtrl =
new wxCheckBox(
this,
ID_selLatchCtrl,
_("Respond to short SCSI selection pulses"));
mySelLatchCtrl->SetToolTip(_("Respond to very short duration selection attempts. This supports non-standard hardware, but is generally safe to enable. Required for Philips P2000C."));
fgs->Add(mySelLatchCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myMapLunsCtrl =
new wxCheckBox(
this,
ID_mapLunsCtrl,
_("Map LUNS to SCSI IDs"));
myMapLunsCtrl->SetToolTip(_("Treat LUNS as IDs instead. Supports multiple drives on XEBEC S1410 SASI Bridge"));
fgs->Add(myMapLunsCtrl);
wxBoxSizer* hbox = new wxBoxSizer(wxHORIZONTAL);
hbox->Add(fgs, 1, wxALL | wxEXPAND, 15);
this->SetSizer(hbox);
@ -160,7 +178,9 @@ BoardPanel::getConfig() const
(myScsi2Ctrl->IsChecked() ? CONFIG_ENABLE_SCSI2 : 0) |
(myGlitchCtrl->IsChecked() ? CONFIG_DISABLE_GLITCH : 0) |
(myCacheCtrl->IsChecked() ? CONFIG_ENABLE_CACHE: 0) |
(myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0);
(myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0) |
(mySelLatchCtrl->IsChecked() ? CONFIG_ENABLE_SEL_LATCH : 0) |
(myMapLunsCtrl->IsChecked() ? CONFIG_MAP_LUNS_TO_IDS : 0);
config.startupDelay = CtrlGetValue<unsigned int>(myStartDelayCtrl).first;
config.selectionDelay = CtrlGetValue<unsigned int>(mySelDelayCtrl).first;
@ -178,6 +198,8 @@ BoardPanel::setConfig(const BoardConfig& config)
myGlitchCtrl->SetValue(config.flags & CONFIG_DISABLE_GLITCH);
myCacheCtrl->SetValue(config.flags & CONFIG_ENABLE_CACHE);
myDisconnectCtrl->SetValue(config.flags & CONFIG_ENABLE_DISCONNECT);
mySelLatchCtrl->SetValue(config.flags & CONFIG_ENABLE_SEL_LATCH);
myMapLunsCtrl->SetValue(config.flags & CONFIG_MAP_LUNS_TO_IDS);
{
std::stringstream conv;

4
software/scsi2sd-util/BoardPanel.hh
View File

@ -58,6 +58,8 @@ private:
ID_glitchCtrl,
ID_cacheCtrl,
ID_disconnectCtrl,
ID_selLatchCtrl,
ID_mapLunsCtrl,
ID_startDelayCtrl,
ID_selDelayCtrl
};
@ -72,6 +74,8 @@ private:
wxCheckBox* myGlitchCtrl;
wxCheckBox* myCacheCtrl;
wxCheckBox* myDisconnectCtrl;
wxCheckBox* mySelLatchCtrl;
wxCheckBox* myMapLunsCtrl;
wxIntegerValidator<uint8_t>* myDelayValidator;
wxTextCtrl* myStartDelayCtrl;

46
software/scsi2sd-util/ConfigUtil.cc
View File

@ -316,6 +316,28 @@ ConfigUtil::toXML(const BoardConfig& config)
" <enableDisconnect>" <<
(config.flags & CONFIG_ENABLE_DISCONNECT ? "true" : "false") <<
"</enableDisconnect>\n" <<
" <!-- ********************************************************\n" <<
" Respond to very short duration selection attempts. This supports\n" <<
" non-standard hardware, but is generally safe to enable.\n" <<
" Required for Philips P2000C.\n" <<
" ********************************************************* -->\n" <<
" <selLatch>" <<
(config.flags & CONFIG_ENABLE_SEL_LATCH? "true" : "false") <<
"</selLatch>\n" <<
" <!-- ********************************************************\n" <<
" Convert luns to IDs. The unit must already be configured to respond\n" <<
" on the ID. Allows dual drives to be accessed from a \n" <<
" XEBEC S1410 SASI bridge.\n" <<
" eg. Configured for dual drives as IDs 0 and 1, but the XEBEC will\n" <<
" access the second disk as ID0, lun 1.\n" <<
" See ttp://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf\n" <<
" ********************************************************* -->\n" <<
" <mapLunsToIds>" <<
(config.flags & CONFIG_MAP_LUNS_TO_IDS ? "true" : "false") <<
"</mapLunsToIds>\n" <<
"</BoardConfig>\n";
return s.str();
@ -538,6 +560,30 @@ parseBoardConfig(wxXmlNode* node)
result.flags = result.flags & ~CONFIG_ENABLE_DISCONNECT;
}
}
else if (child->GetName() == "selLatch")
{
std::string s(child->GetNodeContent().mb_str());
if (s == "true")
{
result.flags |= CONFIG_ENABLE_SEL_LATCH;
}
else
{
result.flags = result.flags & ~CONFIG_ENABLE_SEL_LATCH;
}
}
else if (child->GetName() == "mapLunsToIds")
{
std::string s(child->GetNodeContent().mb_str());
if (s == "true")
{
result.flags |= CONFIG_MAP_LUNS_TO_IDS;
}
else
{
result.flags = result.flags & ~CONFIG_MAP_LUNS_TO_IDS;
}
}
child = child->GetNext();
}
return result;

138
software/scsi2sd-util/scsi2sd-util.cc
View File

@ -181,6 +181,10 @@ public:
ID_Firmware,
_("&Upgrade Firmware..."),
_("Upgrade or inspect device firmware version."));
menuFile->Append(
ID_Bootloader,
_("&Upgrade Bootloader (ADVANCED) ..."),
_("Upgrade device bootloader."));
menuFile->AppendSeparator();
menuFile->Append(wxID_EXIT);
@ -365,6 +369,7 @@ private:
{
ID_ConfigDefaults = wxID_HIGHEST + 1,
ID_Firmware,
ID_Bootloader,
ID_Timer,
ID_Notebook,
ID_BtnLoad,
@ -471,6 +476,12 @@ private:
doFirmwareUpdate();
}
void OnID_Bootloader(wxCommandEvent& event)
{
TimerLock lock(myTimer);
doBootloaderUpdate();
}
void OnID_LogWindow(wxCommandEvent& event)
{
myLogWindow->Show();
@ -651,6 +662,129 @@ private:
}
}
void doBootloaderUpdate()
{
if (!myHID)
{
wxMessageBox(
"No device",
"No device",
wxOK | wxICON_ERROR);
return;
}
wxFileDialog dlg(
this,
"Load bootloader file",
"",
"",
"SCSI2SD Bootloader files (*.bin)|*.bin",
wxFD_OPEN | wxFD_FILE_MUST_EXIST);
if (dlg.ShowModal() == wxID_CANCEL) return;
std::string filename(dlg.GetPath());
wxFile file(filename);
if (file.Length() != 0x2400)
{
wxMessageBox(
"Invalid file",
"Invalid file",
wxOK | wxICON_ERROR);
return;
}
uint8_t data[0x2400];
if (file.Read(data, sizeof(data)) != sizeof(data))
{
wxMessageBox(
"Couldn't read file",
"Couldn't read file",
wxOK | wxICON_ERROR);
return;
}
static char magic[] = {
'P', 0, 'S', 0, 'o', 0, 'C', 0, '3', 0, ' ', 0,
'B', 0, 'o', 0, 'o', 0, 't', 0, 'l', 0, 'o', 0, 'a', 0, 'd', 0, 'e', 0, 'r', 0};
uint8_t* dataEnd = data + sizeof(data);
if (std::search(data, dataEnd, magic, magic + sizeof(magic)) >= dataEnd)
{
wxMessageBox(
"Bad file",
"Not a valid bootloader file.",
wxOK | wxICON_ERROR);
return;
}
std::stringstream msg;
msg << "Upgrading bootloader from file: " << filename;
mmLogStatus(msg.str());
wxWindowPtr<wxGenericProgressDialog> progress(
new wxGenericProgressDialog(
"Update bootloader",
"Update bootloader",
100,
this,
wxPD_REMAINING_TIME)
);
int currentProgress = 0;
int totalProgress = 36;
for (size_t flashRow = 0; flashRow < 36; ++flashRow)
{
std::stringstream ss;
ss << "Programming flash array 0 row " << (flashRow);
mmLogStatus(ss.str());
currentProgress += 1;
if (currentProgress == totalProgress)
{
ss.str("Save Complete.");
mmLogStatus("Save Complete.");
}
if (!progress->Update(
(100 * currentProgress) / totalProgress,
ss.str()
)
)
{
goto abort;
}
uint8_t* rowData = data + (flashRow * 256);
std::vector<uint8_t> flashData(rowData, rowData + 256);
try
{
myHID->writeFlashRow(0, flashRow, flashData);
}
catch (std::runtime_error& e)
{
mmLogStatus(e.what());
goto err;
}
}
goto out;
err:
mmLogStatus("Bootloader update failed");
progress->Update(100, "Bootloader update failed");
goto out;
abort:
mmLogStatus("Bootloader update aborted");
out:
return;
}
void dumpSCSICommand(std::vector<uint8_t> buf)
{
std::stringstream msg;
@ -1046,11 +1180,8 @@ private:
}
}
// Reboot so new settings take effect.
myHID->enterBootloader();
myHID.reset();
goto out;
err:
@ -1098,6 +1229,7 @@ private:
wxBEGIN_EVENT_TABLE(AppFrame, wxFrame)
EVT_MENU(AppFrame::ID_ConfigDefaults, AppFrame::OnID_ConfigDefaults)
EVT_MENU(AppFrame::ID_Firmware, AppFrame::OnID_Firmware)
EVT_MENU(AppFrame::ID_Bootloader, AppFrame::OnID_Bootloader)
EVT_MENU(AppFrame::ID_LogWindow, AppFrame::OnID_LogWindow)
EVT_MENU(AppFrame::ID_SaveFile, AppFrame::OnID_SaveFile)
EVT_MENU(AppFrame::ID_OpenFile, AppFrame::OnID_OpenFile)