v 20060113 1 P 100 17900 400 17900 1 0 0 { T 300 17950 5 8 1 1 0 6 1 pinnumber=1 T 300 17850 5 8 0 1 0 8 1 pinseq=1 T 450 17900 9 8 1 1 0 0 1 pinlabel=P2[5] T 450 17900 5 8 0 1 0 2 1 pintype=io } P 100 17200 400 17200 1 0 0 { T 300 17250 5 8 1 1 0 6 1 pinnumber=2 T 300 17150 5 8 0 1 0 8 1 pinseq=2 T 450 17200 9 8 1 1 0 0 1 pinlabel=P2[6] T 450 17200 5 8 0 1 0 2 1 pintype=io } P 100 16500 400 16500 1 0 0 { T 300 16550 5 8 1 1 0 6 1 pinnumber=3 T 300 16450 5 8 0 1 0 8 1 pinseq=3 T 450 16500 9 8 1 1 0 0 1 pinlabel=P2[7] T 450 16500 5 8 0 1 0 2 1 pintype=io } P 100 15800 400 15800 1 0 0 { T 300 15850 5 8 1 1 0 6 1 pinnumber=4 T 300 15750 5 8 0 1 0 8 1 pinseq=4 T 450 15800 9 8 1 1 0 0 1 pinlabel=P12[4] T 450 15800 5 8 0 1 0 2 1 pintype=io } P 100 15100 400 15100 1 0 0 { T 300 15150 5 8 1 1 0 6 1 pinnumber=5 T 300 15050 5 8 0 1 0 8 1 pinseq=5 T 450 15100 9 8 1 1 0 0 1 pinlabel=P12[5] T 450 15100 5 8 0 1 0 2 1 pintype=io } P 100 14400 400 14400 1 0 0 { T 300 14450 5 8 1 1 0 6 1 pinnumber=6 T 300 14350 5 8 0 1 0 8 1 pinseq=6 T 450 14400 9 8 1 1 0 0 1 pinlabel=P6[4] T 450 14400 5 8 0 1 0 2 1 pintype=io } P 100 13700 400 13700 1 0 0 { T 300 13750 5 8 1 1 0 6 1 pinnumber=7 T 300 13650 5 8 0 1 0 8 1 pinseq=7 T 450 13700 9 8 1 1 0 0 1 pinlabel=P6[5] T 450 13700 5 8 0 1 0 2 1 pintype=io } P 100 13000 400 13000 1 0 0 { T 300 13050 5 8 1 1 0 6 1 pinnumber=8 T 300 12950 5 8 0 1 0 8 1 pinseq=8 T 450 13000 9 8 1 1 0 0 1 pinlabel=P6[6] T 450 13000 5 8 0 1 0 2 1 pintype=io } P 100 12300 400 12300 1 0 0 { T 300 12350 5 8 1 1 0 6 1 pinnumber=9 T 300 12250 5 8 0 1 0 8 1 pinseq=9 T 450 12300 9 8 1 1 0 0 1 pinlabel=P6[7] T 450 12300 5 8 0 1 0 2 1 pintype=io } P 100 11600 400 11600 1 0 0 { T 300 11650 5 8 1 1 0 6 1 pinnumber=10 T 300 11550 5 8 0 1 0 8 1 pinseq=10 T 450 11600 9 8 1 1 0 0 1 pinlabel=VSSD T 450 11600 5 8 0 1 0 2 1 pintype=pwr } P 100 10900 400 10900 1 0 0 { T 300 10950 5 8 1 1 0 6 1 pinnumber=11 T 300 10850 5 8 0 1 0 8 1 pinseq=11 T 450 10900 9 8 1 1 0 0 1 pinlabel=NC T 450 10900 5 8 0 1 0 2 1 pintype=io } P 100 10200 400 10200 1 0 0 { T 300 10250 5 8 1 1 0 6 1 pinnumber=12 T 300 10150 5 8 0 1 0 8 1 pinseq=12 T 450 10200 9 8 1 1 0 0 1 pinlabel=VSSD T 450 10200 5 8 0 1 0 2 1 pintype=pwr } P 100 9500 400 9500 1 0 0 { T 300 9550 5 8 1 1 0 6 1 pinnumber=13 T 300 9450 5 8 0 1 0 8 1 pinseq=13 T 450 9500 9 8 1 1 0 0 1 pinlabel=VSSD T 450 9500 5 8 0 1 0 2 1 pintype=pwr } P 100 8800 400 8800 1 0 0 { T 300 8850 5 8 1 1 0 6 1 pinnumber=14 T 300 8750 5 8 0 1 0 8 1 pinseq=14 T 450 8800 9 8 1 1 0 0 1 pinlabel=VSSD T 450 8800 5 8 0 1 0 2 1 pintype=pwr } P 100 8100 400 8100 1 0 0 { T 300 8150 5 8 1 1 0 6 1 pinnumber=15 T 300 8050 5 8 0 1 0 8 1 pinseq=15 T 450 8100 9 8 1 1 0 0 1 pinlabel=\_XRES\_ T 450 8100 5 8 0 1 0 2 1 pintype=in } P 100 7400 400 7400 1 0 0 { T 300 7450 5 8 1 1 0 6 1 pinnumber=16 T 300 7350 5 8 0 1 0 8 1 pinseq=16 T 450 7400 9 8 1 1 0 0 1 pinlabel=P5[0] T 450 7400 5 8 0 1 0 2 1 pintype=io } P 100 6700 400 6700 1 0 0 { T 300 6750 5 8 1 1 0 6 1 pinnumber=17 T 300 6650 5 8 0 1 0 8 1 pinseq=17 T 450 6700 9 8 1 1 0 0 1 pinlabel=P5[1] T 450 6700 5 8 0 1 0 2 1 pintype=io } P 100 6000 400 6000 1 0 0 { T 300 6050 5 8 1 1 0 6 1 pinnumber=18 T 300 5950 5 8 0 1 0 8 1 pinseq=18 T 450 6000 9 8 1 1 0 0 1 pinlabel=P5[2] T 450 6000 5 8 0 1 0 2 1 pintype=io } P 100 5300 400 5300 1 0 0 { T 300 5350 5 8 1 1 0 6 1 pinnumber=19 T 300 5250 5 8 0 1 0 8 1 pinseq=19 T 450 5300 9 8 1 1 0 0 1 pinlabel=P5[3] T 450 5300 5 8 0 1 0 2 1 pintype=io } P 100 4600 400 4600 1 0 0 { T 300 4650 5 8 1 1 0 6 1 pinnumber=20 T 300 4550 5 8 0 1 0 8 1 pinseq=20 T 450 4600 9 8 1 1 0 0 1 pinlabel=SWDIO,P1[0] T 450 4600 5 8 0 1 0 2 1 pintype=io } P 100 3900 400 3900 1 0 0 { T 300 3950 5 8 1 1 0 6 1 pinnumber=21 T 300 3850 5 8 0 1 0 8 1 pinseq=21 T 450 3900 9 8 1 1 0 0 1 pinlabel=SWDCK,P1[1] T 450 3900 5 8 0 1 0 2 1 pintype=io } P 100 3200 400 3200 1 0 0 { T 300 3250 5 8 1 1 0 6 1 pinnumber=22 T 300 3150 5 8 0 1 0 8 1 pinseq=22 T 450 3200 9 8 1 1 0 0 1 pinlabel=P1[2] T 450 3200 5 8 0 1 0 2 1 pintype=io } P 100 2500 400 2500 1 0 0 { T 300 2550 5 8 1 1 0 6 1 pinnumber=23 T 300 2450 5 8 0 1 0 8 1 pinseq=23 T 450 2500 9 8 1 1 0 0 1 pinlabel=SWV,P1[3] T 450 2500 5 8 0 1 0 2 1 pintype=io } P 100 1800 400 1800 1 0 0 { T 300 1850 5 8 1 1 0 6 1 pinnumber=24 T 300 1750 5 8 0 1 0 8 1 pinseq=24 T 450 1800 9 8 1 1 0 0 1 pinlabel=P1[4] T 450 1800 5 8 0 1 0 2 1 pintype=io } P 100 1100 400 1100 1 0 0 { T 300 1150 5 8 1 1 0 6 1 pinnumber=25 T 300 1050 5 8 0 1 0 8 1 pinseq=25 T 450 1100 9 8 1 1 0 0 1 pinlabel=P1[5] T 450 1100 5 8 0 1 0 2 1 pintype=io } P 1000 100 1000 400 1 0 0 { T 950 300 5 8 1 1 90 6 1 pinnumber=26 T 1050 300 5 8 0 1 90 8 1 pinseq=26 T 1000 450 9 8 1 1 90 0 1 pinlabel=VDDIO1 T 1000 450 5 8 0 1 90 2 1 pintype=pwr } P 1700 100 1700 400 1 0 0 { T 1650 300 5 8 1 1 90 6 1 pinnumber=27 T 1750 300 5 8 0 1 90 8 1 pinseq=27 T 1700 450 9 8 1 1 90 0 1 pinlabel=P1[6] T 1700 450 5 8 0 1 90 2 1 pintype=io } P 2400 100 2400 400 1 0 0 { T 2350 300 5 8 1 1 90 6 1 pinnumber=28 T 2450 300 5 8 0 1 90 8 1 pinseq=28 T 2400 450 9 8 1 1 90 0 1 pinlabel=P1[7] T 2400 450 5 8 0 1 90 2 1 pintype=io } P 3100 100 3100 400 1 0 0 { T 3050 300 5 8 1 1 90 6 1 pinnumber=29 T 3150 300 5 8 0 1 90 8 1 pinseq=29 T 3100 450 9 8 1 1 90 0 1 pinlabel=P12[6] T 3100 450 5 8 0 1 90 2 1 pintype=io } P 3800 100 3800 400 1 0 0 { T 3750 300 5 8 1 1 90 6 1 pinnumber=30 T 3850 300 5 8 0 1 90 8 1 pinseq=30 T 3800 450 9 8 1 1 90 0 1 pinlabel=P12[7] T 3800 450 5 8 0 1 90 2 1 pintype=io } P 4500 100 4500 400 1 0 0 { T 4450 300 5 8 1 1 90 6 1 pinnumber=31 T 4550 300 5 8 0 1 90 8 1 pinseq=31 T 4500 450 9 8 1 1 90 0 1 pinlabel=P5[4] T 4500 450 5 8 0 1 90 2 1 pintype=io } P 5200 100 5200 400 1 0 0 { T 5150 300 5 8 1 1 90 6 1 pinnumber=32 T 5250 300 5 8 0 1 90 8 1 pinseq=32 T 5200 450 9 8 1 1 90 0 1 pinlabel=P5[5] T 5200 450 5 8 0 1 90 2 1 pintype=io } P 5900 100 5900 400 1 0 0 { T 5850 300 5 8 1 1 90 6 1 pinnumber=33 T 5950 300 5 8 0 1 90 8 1 pinseq=33 T 5900 450 9 8 1 1 90 0 1 pinlabel=P5[6] T 5900 450 5 8 0 1 90 2 1 pintype=io } P 6600 100 6600 400 1 0 0 { T 6550 300 5 8 1 1 90 6 1 pinnumber=34 T 6650 300 5 8 0 1 90 8 1 pinseq=34 T 6600 450 9 8 1 1 90 0 1 pinlabel=P5[7] T 6600 450 5 8 0 1 90 2 1 pintype=io } P 7300 100 7300 400 1 0 0 { T 7250 300 5 8 1 1 90 6 1 pinnumber=35 T 7350 300 5 8 0 1 90 8 1 pinseq=35 T 7300 450 9 8 1 1 90 0 1 pinlabel=SWDIO,USB D+ T 7300 450 5 8 0 1 90 2 1 pintype=io } P 8000 100 8000 400 1 0 0 { T 7950 300 5 8 1 1 90 6 1 pinnumber=36 T 8050 300 5 8 0 1 90 8 1 pinseq=36 T 8000 450 9 8 1 1 90 0 1 pinlabel=SWDCK,USB D- T 8000 450 5 8 0 1 90 2 1 pintype=io } P 8700 100 8700 400 1 0 0 { T 8650 300 5 8 1 1 90 6 1 pinnumber=37 T 8750 300 5 8 0 1 90 8 1 pinseq=37 T 8700 450 9 8 1 1 90 0 1 pinlabel=VDDD T 8700 450 5 8 0 1 90 2 1 pintype=pwr } P 9400 100 9400 400 1 0 0 { T 9350 300 5 8 1 1 90 6 1 pinnumber=38 T 9450 300 5 8 0 1 90 8 1 pinseq=38 T 9400 450 9 8 1 1 90 0 1 pinlabel=VSSD T 9400 450 5 8 0 1 90 2 1 pintype=pwr } P 10100 100 10100 400 1 0 0 { T 10050 300 5 8 1 1 90 6 1 pinnumber=39 T 10150 300 5 8 0 1 90 8 1 pinseq=39 T 10100 450 9 8 1 1 90 0 1 pinlabel=VCCD T 10100 450 5 8 0 1 90 2 1 pintype=pwr } P 10800 100 10800 400 1 0 0 { T 10750 300 5 8 1 1 90 6 1 pinnumber=40 T 10850 300 5 8 0 1 90 8 1 pinseq=40 T 10800 450 9 8 1 1 90 0 1 pinlabel=NC T 10800 450 5 8 0 1 90 2 1 pintype=io } P 11500 100 11500 400 1 0 0 { T 11450 300 5 8 1 1 90 6 1 pinnumber=41 T 11550 300 5 8 0 1 90 8 1 pinseq=41 T 11500 450 9 8 1 1 90 0 1 pinlabel=NC T 11500 450 5 8 0 1 90 2 1 pintype=io } P 12200 100 12200 400 1 0 0 { T 12150 300 5 8 1 1 90 6 1 pinnumber=42 T 12250 300 5 8 0 1 90 8 1 pinseq=42 T 12200 525 9 8 1 1 90 0 1 pinlabel=MHZ XTAL XO T 12200 525 5 8 0 1 90 2 1 pintype=clk } L 12200 500 12275 400 3 0 0 0 -1 -1 L 12200 500 12125 400 3 0 0 0 -1 -1 P 12900 100 12900 400 1 0 0 { T 12850 300 5 8 1 1 90 6 1 pinnumber=43 T 12950 300 5 8 0 1 90 8 1 pinseq=43 T 12900 525 9 8 1 1 90 0 1 pinlabel=MHZ XTAL XI T 12900 525 5 8 0 1 90 2 1 pintype=clk } L 12900 500 12975 400 3 0 0 0 -1 -1 L 12900 500 12825 400 3 0 0 0 -1 -1 P 13600 100 13600 400 1 0 0 { T 13550 300 5 8 1 1 90 6 1 pinnumber=44 T 13650 300 5 8 0 1 90 8 1 pinseq=44 T 13600 450 9 8 1 1 90 0 1 pinlabel=P3[0] T 13600 450 5 8 0 1 90 2 1 pintype=io } P 14300 100 14300 400 1 0 0 { T 14250 300 5 8 1 1 90 6 1 pinnumber=45 T 14350 300 5 8 0 1 90 8 1 pinseq=45 T 14300 450 9 8 1 1 90 0 1 pinlabel=P3[1] T 14300 450 5 8 0 1 90 2 1 pintype=io } P 15000 100 15000 400 1 0 0 { T 14950 300 5 8 1 1 90 6 1 pinnumber=46 T 15050 300 5 8 0 1 90 8 1 pinseq=46 T 15000 450 9 8 1 1 90 0 1 pinlabel=P3[2] T 15000 450 5 8 0 1 90 2 1 pintype=io } P 15700 100 15700 400 1 0 0 { T 15650 300 5 8 1 1 90 6 1 pinnumber=47 T 15750 300 5 8 0 1 90 8 1 pinseq=47 T 15700 450 9 8 1 1 90 0 1 pinlabel=P3[3] T 15700 450 5 8 0 1 90 2 1 pintype=io } P 16400 100 16400 400 1 0 0 { T 16350 300 5 8 1 1 90 6 1 pinnumber=48 T 16450 300 5 8 0 1 90 8 1 pinseq=48 T 16400 450 9 8 1 1 90 0 1 pinlabel=P3[4] T 16400 450 5 8 0 1 90 2 1 pintype=io } P 17100 100 17100 400 1 0 0 { T 17050 300 5 8 1 1 90 6 1 pinnumber=49 T 17150 300 5 8 0 1 90 8 1 pinseq=49 T 17100 450 9 8 1 1 90 0 1 pinlabel=P3[5] T 17100 450 5 8 0 1 90 2 1 pintype=io } P 17800 100 17800 400 1 0 0 { T 17750 300 5 8 1 1 90 6 1 pinnumber=50 T 17850 300 5 8 0 1 90 8 1 pinseq=50 T 17800 450 9 8 1 1 90 0 1 pinlabel=VDDIO3 T 17800 450 5 8 0 1 90 2 1 pintype=pwr } P 18700 17900 18400 17900 1 0 0 { T 18500 17950 5 8 1 1 0 0 1 pinnumber=75 T 18500 17850 5 8 0 1 0 2 1 pinseq=51 T 18350 17900 9 8 1 1 0 6 1 pinlabel=VDDIO0 T 18350 17900 5 8 0 1 0 8 1 pintype=pwr } P 18700 17200 18400 17200 1 0 0 { T 18500 17250 5 8 1 1 0 0 1 pinnumber=74 T 18500 17150 5 8 0 1 0 2 1 pinseq=52 T 18350 17200 9 8 1 1 0 6 1 pinlabel=P0[3] T 18350 17200 5 8 0 1 0 8 1 pintype=io } P 18700 16500 18400 16500 1 0 0 { T 18500 16550 5 8 1 1 0 0 1 pinnumber=73 T 18500 16450 5 8 0 1 0 2 1 pinseq=53 T 18350 16500 9 8 1 1 0 6 1 pinlabel=P0[2] T 18350 16500 5 8 0 1 0 8 1 pintype=io } P 18700 15800 18400 15800 1 0 0 { T 18500 15850 5 8 1 1 0 0 1 pinnumber=72 T 18500 15750 5 8 0 1 0 2 1 pinseq=54 T 18350 15800 9 8 1 1 0 6 1 pinlabel=P0[1] T 18350 15800 5 8 0 1 0 8 1 pintype=io } P 18700 15100 18400 15100 1 0 0 { T 18500 15150 5 8 1 1 0 0 1 pinnumber=71 T 18500 15050 5 8 0 1 0 2 1 pinseq=55 T 18350 15100 9 8 1 1 0 6 1 pinlabel=P0[0] T 18350 15100 5 8 0 1 0 8 1 pintype=io } P 18700 14400 18400 14400 1 0 0 { T 18500 14450 5 8 1 1 0 0 1 pinnumber=70 T 18500 14350 5 8 0 1 0 2 1 pinseq=56 T 18350 14400 9 8 1 1 0 6 1 pinlabel=P4[1] T 18350 14400 5 8 0 1 0 8 1 pintype=io } P 18700 13700 18400 13700 1 0 0 { T 18500 13750 5 8 1 1 0 0 1 pinnumber=69 T 18500 13650 5 8 0 1 0 2 1 pinseq=57 T 18350 13700 9 8 1 1 0 6 1 pinlabel=P4[0] T 18350 13700 5 8 0 1 0 8 1 pintype=io } P 18700 13000 18400 13000 1 0 0 { T 18500 13050 5 8 1 1 0 0 1 pinnumber=68 T 18500 12950 5 8 0 1 0 2 1 pinseq=58 T 18350 13000 9 8 1 1 0 6 1 pinlabel=P12[3] T 18350 13000 5 8 0 1 0 8 1 pintype=io } P 18700 12300 18400 12300 1 0 0 { T 18500 12350 5 8 1 1 0 0 1 pinnumber=67 T 18500 12250 5 8 0 1 0 2 1 pinseq=59 T 18350 12300 9 8 1 1 0 6 1 pinlabel=P12[2] T 18350 12300 5 8 0 1 0 8 1 pintype=io } P 18700 11600 18400 11600 1 0 0 { T 18500 11650 5 8 1 1 0 0 1 pinnumber=66 T 18500 11550 5 8 0 1 0 2 1 pinseq=60 T 18350 11600 9 8 1 1 0 6 1 pinlabel=VSSD T 18350 11600 5 8 0 1 0 8 1 pintype=pwr } P 18700 10900 18400 10900 1 0 0 { T 18500 10950 5 8 1 1 0 0 1 pinnumber=65 T 18500 10850 5 8 0 1 0 2 1 pinseq=61 T 18350 10900 9 8 1 1 0 6 1 pinlabel=VDDA T 18350 10900 5 8 0 1 0 8 1 pintype=pwr } P 18700 10200 18400 10200 1 0 0 { T 18500 10250 5 8 1 1 0 0 1 pinnumber=64 T 18500 10150 5 8 0 1 0 2 1 pinseq=62 T 18350 10200 9 8 1 1 0 6 1 pinlabel=VSSA T 18350 10200 5 8 0 1 0 8 1 pintype=pwr } P 18700 9500 18400 9500 1 0 0 { T 18500 9550 5 8 1 1 0 0 1 pinnumber=63 T 18500 9450 5 8 0 1 0 2 1 pinseq=63 T 18350 9500 9 8 1 1 0 6 1 pinlabel=VCCA T 18350 9500 5 8 0 1 0 8 1 pintype=pwr } P 18700 8800 18400 8800 1 0 0 { T 18500 8850 5 8 1 1 0 0 1 pinnumber=62 T 18500 8750 5 8 0 1 0 2 1 pinseq=64 T 18350 8800 9 8 1 1 0 6 1 pinlabel=NC T 18350 8800 5 8 0 1 0 8 1 pintype=io } P 18700 8100 18400 8100 1 0 0 { T 18500 8150 5 8 1 1 0 0 1 pinnumber=61 T 18500 8050 5 8 0 1 0 2 1 pinseq=65 T 18350 8100 9 8 1 1 0 6 1 pinlabel=NC T 18350 8100 5 8 0 1 0 8 1 pintype=io } P 18700 7400 18400 7400 1 0 0 { T 18500 7450 5 8 1 1 0 0 1 pinnumber=60 T 18500 7350 5 8 0 1 0 2 1 pinseq=66 T 18350 7400 9 8 1 1 0 6 1 pinlabel=NC T 18350 7400 5 8 0 1 0 8 1 pintype=io } P 18700 6700 18400 6700 1 0 0 { T 18500 6750 5 8 1 1 0 0 1 pinnumber=59 T 18500 6650 5 8 0 1 0 2 1 pinseq=67 T 18350 6700 9 8 1 1 0 6 1 pinlabel=NC T 18350 6700 5 8 0 1 0 8 1 pintype=io } P 18700 6000 18400 6000 1 0 0 { T 18500 6050 5 8 1 1 0 0 1 pinnumber=58 T 18500 5950 5 8 0 1 0 2 1 pinseq=68 T 18350 6000 9 8 1 1 0 6 1 pinlabel=NC T 18350 6000 5 8 0 1 0 8 1 pintype=io } P 18700 5300 18400 5300 1 0 0 { T 18500 5350 5 8 1 1 0 0 1 pinnumber=57 T 18500 5250 5 8 0 1 0 2 1 pinseq=69 T 18350 5300 9 8 1 1 0 6 1 pinlabel=NC T 18350 5300 5 8 0 1 0 8 1 pintype=io } P 18700 4600 18400 4600 1 0 0 { T 18500 4650 5 8 1 1 0 0 1 pinnumber=56 T 18500 4550 5 8 0 1 0 2 1 pinseq=70 T 18350 4600 9 8 1 1 0 6 1 pinlabel=XI XTAL P15[3],KHZ T 18350 4600 5 8 0 1 0 8 1 pintype=io } P 18700 3900 18400 3900 1 0 0 { T 18500 3950 5 8 1 1 0 0 1 pinnumber=55 T 18500 3850 5 8 0 1 0 2 1 pinseq=71 T 18350 3900 9 8 1 1 0 6 1 pinlabel=XO XTAL P15[2],KHZ T 18350 3900 5 8 0 1 0 8 1 pintype=io } P 18700 3200 18400 3200 1 0 0 { T 18500 3250 5 8 1 1 0 0 1 pinnumber=54 T 18500 3150 5 8 0 1 0 2 1 pinseq=72 T 18350 3200 9 8 1 1 0 6 1 pinlabel=P12[1] T 18350 3200 5 8 0 1 0 8 1 pintype=io } P 18700 2500 18400 2500 1 0 0 { T 18500 2550 5 8 1 1 0 0 1 pinnumber=53 T 18500 2450 5 8 0 1 0 2 1 pinseq=73 T 18350 2500 9 8 1 1 0 6 1 pinlabel=P12[0] T 18350 2500 5 8 0 1 0 8 1 pintype=io } P 18700 1800 18400 1800 1 0 0 { T 18500 1850 5 8 1 1 0 0 1 pinnumber=52 T 18500 1750 5 8 0 1 0 2 1 pinseq=74 T 18350 1800 9 8 1 1 0 6 1 pinlabel=P3[7] T 18350 1800 5 8 0 1 0 8 1 pintype=io } P 18700 1100 18400 1100 1 0 0 { T 18500 1150 5 8 1 1 0 0 1 pinnumber=51 T 18500 1050 5 8 0 1 0 2 1 pinseq=75 T 18350 1100 9 8 1 1 0 6 1 pinlabel=P3[6] T 18350 1100 5 8 0 1 0 8 1 pintype=io } P 1000 18900 1000 18600 1 0 0 { T 950 18700 5 8 1 1 90 0 1 pinnumber=100 T 1050 18700 5 8 0 1 90 2 1 pinseq=76 T 1000 18550 9 8 1 1 90 6 1 pinlabel=VDDIO2 T 1000 18550 5 8 0 1 90 8 1 pintype=pwr } P 1700 18900 1700 18600 1 0 0 { T 1650 18700 5 8 1 1 90 0 1 pinnumber=99 T 1750 18700 5 8 0 1 90 2 1 pinseq=77 T 1700 18550 9 8 1 1 90 6 1 pinlabel=P2[4] T 1700 18550 5 8 0 1 90 8 1 pintype=io } P 2400 18900 2400 18600 1 0 0 { T 2350 18700 5 8 1 1 90 0 1 pinnumber=98 T 2450 18700 5 8 0 1 90 2 1 pinseq=78 T 2400 18550 9 8 1 1 90 6 1 pinlabel=P2[3] T 2400 18550 5 8 0 1 90 8 1 pintype=io } P 3100 18900 3100 18600 1 0 0 { T 3050 18700 5 8 1 1 90 0 1 pinnumber=97 T 3150 18700 5 8 0 1 90 2 1 pinseq=79 T 3100 18550 9 8 1 1 90 6 1 pinlabel=P2[2] T 3100 18550 5 8 0 1 90 8 1 pintype=io } P 3800 18900 3800 18600 1 0 0 { T 3750 18700 5 8 1 1 90 0 1 pinnumber=96 T 3850 18700 5 8 0 1 90 2 1 pinseq=80 T 3800 18550 9 8 1 1 90 6 1 pinlabel=P2[1] T 3800 18550 5 8 0 1 90 8 1 pintype=io } P 4500 18900 4500 18600 1 0 0 { T 4450 18700 5 8 1 1 90 0 1 pinnumber=95 T 4550 18700 5 8 0 1 90 2 1 pinseq=81 T 4500 18550 9 8 1 1 90 6 1 pinlabel=P2[0] T 4500 18550 5 8 0 1 90 8 1 pintype=io } P 5200 18900 5200 18600 1 0 0 { T 5150 18700 5 8 1 1 90 0 1 pinnumber=94 T 5250 18700 5 8 0 1 90 2 1 pinseq=82 T 5200 18550 9 8 1 1 90 6 1 pinlabel=P15[5] T 5200 18550 5 8 0 1 90 8 1 pintype=io } P 5900 18900 5900 18600 1 0 0 { T 5850 18700 5 8 1 1 90 0 1 pinnumber=93 T 5950 18700 5 8 0 1 90 2 1 pinseq=83 T 5900 18550 9 8 1 1 90 6 1 pinlabel=P15[4] T 5900 18550 5 8 0 1 90 8 1 pintype=io } P 6600 18900 6600 18600 1 0 0 { T 6550 18700 5 8 1 1 90 0 1 pinnumber=92 T 6650 18700 5 8 0 1 90 2 1 pinseq=84 T 6600 18550 9 8 1 1 90 6 1 pinlabel=P6[3] T 6600 18550 5 8 0 1 90 8 1 pintype=io } P 7300 18900 7300 18600 1 0 0 { T 7250 18700 5 8 1 1 90 0 1 pinnumber=91 T 7350 18700 5 8 0 1 90 2 1 pinseq=85 T 7300 18550 9 8 1 1 90 6 1 pinlabel=P6[2] T 7300 18550 5 8 0 1 90 8 1 pintype=io } P 8000 18900 8000 18600 1 0 0 { T 7950 18700 5 8 1 1 90 0 1 pinnumber=90 T 8050 18700 5 8 0 1 90 2 1 pinseq=86 T 8000 18550 9 8 1 1 90 6 1 pinlabel=P6[1] T 8000 18550 5 8 0 1 90 8 1 pintype=io } P 8700 18900 8700 18600 1 0 0 { T 8650 18700 5 8 1 1 90 0 1 pinnumber=89 T 8750 18700 5 8 0 1 90 2 1 pinseq=87 T 8700 18550 9 8 1 1 90 6 1 pinlabel=P6[0] T 8700 18550 5 8 0 1 90 8 1 pintype=io } P 9400 18900 9400 18600 1 0 0 { T 9350 18700 5 8 1 1 90 0 1 pinnumber=88 T 9450 18700 5 8 0 1 90 2 1 pinseq=88 T 9400 18550 9 8 1 1 90 6 1 pinlabel=VDDD T 9400 18550 5 8 0 1 90 8 1 pintype=pwr } P 10100 18900 10100 18600 1 0 0 { T 10050 18700 5 8 1 1 90 0 1 pinnumber=87 T 10150 18700 5 8 0 1 90 2 1 pinseq=89 T 10100 18550 9 8 1 1 90 6 1 pinlabel=VSSD T 10100 18550 5 8 0 1 90 8 1 pintype=pwr } P 10800 18900 10800 18600 1 0 0 { T 10750 18700 5 8 1 1 90 0 1 pinnumber=86 T 10850 18700 5 8 0 1 90 2 1 pinseq=90 T 10800 18550 9 8 1 1 90 6 1 pinlabel=VCCD T 10800 18550 5 8 0 1 90 8 1 pintype=pwr } P 11500 18900 11500 18600 1 0 0 { T 11450 18700 5 8 1 1 90 0 1 pinnumber=85 T 11550 18700 5 8 0 1 90 2 1 pinseq=91 T 11500 18550 9 8 1 1 90 6 1 pinlabel=P4[7] T 11500 18550 5 8 0 1 90 8 1 pintype=io } P 12200 18900 12200 18600 1 0 0 { T 12150 18700 5 8 1 1 90 0 1 pinnumber=84 T 12250 18700 5 8 0 1 90 2 1 pinseq=92 T 12200 18550 9 8 1 1 90 6 1 pinlabel=P4[6] T 12200 18550 5 8 0 1 90 8 1 pintype=io } P 12900 18900 12900 18600 1 0 0 { T 12850 18700 5 8 1 1 90 0 1 pinnumber=83 T 12950 18700 5 8 0 1 90 2 1 pinseq=93 T 12900 18550 9 8 1 1 90 6 1 pinlabel=P4[5] T 12900 18550 5 8 0 1 90 8 1 pintype=io } P 13600 18900 13600 18600 1 0 0 { T 13550 18700 5 8 1 1 90 0 1 pinnumber=82 T 13650 18700 5 8 0 1 90 2 1 pinseq=94 T 13600 18550 9 8 1 1 90 6 1 pinlabel=P4[4] T 13600 18550 5 8 0 1 90 8 1 pintype=io } P 14300 18900 14300 18600 1 0 0 { T 14250 18700 5 8 1 1 90 0 1 pinnumber=81 T 14350 18700 5 8 0 1 90 2 1 pinseq=95 T 14300 18550 9 8 1 1 90 6 1 pinlabel=P4[3] T 14300 18550 5 8 0 1 90 8 1 pintype=io } P 15000 18900 15000 18600 1 0 0 { T 14950 18700 5 8 1 1 90 0 1 pinnumber=80 T 15050 18700 5 8 0 1 90 2 1 pinseq=96 T 15000 18550 9 8 1 1 90 6 1 pinlabel=P4[2] T 15000 18550 5 8 0 1 90 8 1 pintype=io } P 15700 18900 15700 18600 1 0 0 { T 15650 18700 5 8 1 1 90 0 1 pinnumber=79 T 15750 18700 5 8 0 1 90 2 1 pinseq=97 T 15700 18550 9 8 1 1 90 6 1 pinlabel=P0[7] T 15700 18550 5 8 0 1 90 8 1 pintype=io } P 16400 18900 16400 18600 1 0 0 { T 16350 18700 5 8 1 1 90 0 1 pinnumber=78 T 16450 18700 5 8 0 1 90 2 1 pinseq=98 T 16400 18550 9 8 1 1 90 6 1 pinlabel=P0[6] T 16400 18550 5 8 0 1 90 8 1 pintype=io } P 17100 18900 17100 18600 1 0 0 { T 17050 18700 5 8 1 1 90 0 1 pinnumber=77 T 17150 18700 5 8 0 1 90 2 1 pinseq=99 T 17100 18550 9 8 1 1 90 6 1 pinlabel=P0[5] T 17100 18550 5 8 0 1 90 8 1 pintype=io } P 17800 18900 17800 18600 1 0 0 { T 17750 18700 5 8 1 1 90 0 1 pinnumber=76 T 17850 18700 5 8 0 1 90 2 1 pinseq=100 T 17800 18550 9 8 1 1 90 6 1 pinlabel=P0[4] T 17800 18550 5 8 0 1 90 8 1 pintype=io } B 400 400 18000 18200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 T 18400 18700 8 10 1 1 0 6 1 refdes=U? T 9200 9400 9 10 1 0 0 0 1 CY8C53 T 9200 9700 5 10 0 0 0 0 1 device=CY8C53 T 9200 9900 5 10 0 0 0 0 1 footprint=TQFP100_14 T 9200 10100 5 10 0 0 0 0 1 author=Michael McMaster T 9200 10300 5 10 0 0 0 0 1 documentation=http://www.cypress.com/?id=2233 T 9200 10500 5 10 0 0 0 0 1 description=Cypress PSoC5 CY8C53 T 9200 10700 5 10 0 0 0 0 1 numslots=0 T 9200 10900 5 10 0 0 0 0 1 dist-license=gpl3+ T 9200 11100 5 10 0 0 0 0 1 use-license=gpl3+