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https://github.com/fhgwright/SCSI2SD.git
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105 lines
3.1 KiB
C
Executable File
105 lines
3.1 KiB
C
Executable File
// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
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//
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// This file is part of SCSI2SD.
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//
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// SCSI2SD is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// SCSI2SD is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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#ifndef SCSIPHY_H
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#define SCSIPHY_H
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// Definitions to match the scsiTarget status register.
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typedef enum
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{
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SCSI_PHY_TX_FIFO_NOT_FULL = 0x01,
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SCSI_PHY_RX_FIFO_NOT_EMPTY = 0x02,
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// The TX FIFO is empty and the state machine is in the idle state
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SCSI_PHY_TX_COMPLETE = 0x10
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} SCSI_PHY_STATE;
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#define scsiPhyStatus() CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG)
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#define scsiPhyTxFifoFull() ((scsiPhyStatus() & SCSI_PHY_TX_FIFO_NOT_FULL) == 0)
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#define scsiPhyRxFifoEmpty() ((scsiPhyStatus() & SCSI_PHY_RX_FIFO_NOT_EMPTY) == 0)
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// Clear 4 byte fifo
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#define scsiPhyRxFifoClear() scsiPhyRx(); scsiPhyRx(); scsiPhyRx(); scsiPhyRx();
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#define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val))
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#define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG)
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#if defined(TERM_EN_0) || defined(BOOTLDR_0)
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// V5.1 and v5.5 is active-low
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#define SCSI_SetPin(pin) \
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CyPins_ClearPin((pin));
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#define SCSI_ClearPin(pin) \
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CyPins_SetPin((pin));
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#else
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// <= V5.0 is active-high
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#define SCSI_SetPin(pin) \
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CyPins_SetPin((pin));
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#define SCSI_ClearPin(pin) \
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CyPins_ClearPin((pin));
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#endif
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// Active low: we interpret a 0 as "true", and non-zero as "false"
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#define SCSI_ReadPin(pin) \
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(CyPins_ReadPin((pin)) == 0)
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// These signals go through a glitch filter - we do not access the pin
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// directly
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enum FilteredInputs
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{
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SCSI_Filt_ATN = 0x01,
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SCSI_Filt_BSY = 0x02,
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SCSI_Filt_SEL = 0x04,
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SCSI_Filt_RST = 0x08,
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SCSI_Filt_ACK = 0x10
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};
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#define SCSI_ReadFilt(filt) \
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((SCSI_Filtered_Read() & (filt)) == 0)
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// SCSI delays, as referenced to the cpu clock
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#define CPU_CLK_PERIOD_NS (1000000000U / BCLK__BUS_CLK__HZ)
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#define scsiDeskewDelay() CyDelayCycles((55 / CPU_CLK_PERIOD_NS) + 1)
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// Contains the odd-parity flag for a given 8-bit value.
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extern const uint8_t Lookup_OddParity[256];
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extern volatile uint8_t scsiRxDMAComplete;
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extern volatile uint8_t scsiTxDMAComplete;
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#define scsiDMABusy() (!(scsiRxDMAComplete && scsiTxDMAComplete))
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void scsiPhyReset(void);
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void scsiPhyInit(void);
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void scsiPhyConfig(void);
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uint8_t scsiReadByte(void);
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void scsiRead(uint8_t* data, uint32_t count);
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void scsiReadDMA(uint8_t* data, uint32_t count);
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int scsiReadDMAPoll();
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void scsiWriteByte(uint8_t value);
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void scsiWrite(const uint8_t* data, uint32_t count);
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void scsiWriteDMA(const uint8_t* data, uint32_t count);
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int scsiWriteDMAPoll();
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uint8_t scsiReadDBxPins(void);
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void scsiEnterPhase(int phase);
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int scsiSelfTest(void);
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#endif
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