mirror of
https://github.com/fhgwright/SCSI2SD.git
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435 lines
24 KiB
C
435 lines
24 KiB
C
/*******************************************************************************
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* File Name: Debug_Timer.h
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* Version 2.70
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*
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* Description:
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* Contains the function prototypes and constants available to the timer
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* user module.
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*
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* Note:
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* None
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*
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********************************************************************************
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* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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********************************************************************************/
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#if !defined(CY_Timer_v2_60_Debug_Timer_H)
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#define CY_Timer_v2_60_Debug_Timer_H
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#include "cytypes.h"
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#include "cyfitter.h"
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#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
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extern uint8 Debug_Timer_initVar;
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/* Check to see if required defines such as CY_PSOC5LP are available */
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/* They are defined starting with cy_boot v3.0 */
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#if !defined (CY_PSOC5LP)
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#error Component Timer_v2_70 requires cy_boot v3.0 or later
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#endif /* (CY_ PSOC5LP) */
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/**************************************
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* Parameter Defaults
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**************************************/
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#define Debug_Timer_Resolution 16u
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#define Debug_Timer_UsingFixedFunction 1u
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#define Debug_Timer_UsingHWCaptureCounter 0u
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#define Debug_Timer_SoftwareCaptureMode 0u
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#define Debug_Timer_SoftwareTriggerMode 0u
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#define Debug_Timer_UsingHWEnable 0u
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#define Debug_Timer_EnableTriggerMode 0u
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#define Debug_Timer_InterruptOnCaptureCount 0u
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#define Debug_Timer_RunModeUsed 0u
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#define Debug_Timer_ControlRegRemoved 0u
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#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
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#define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
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#elif (Debug_Timer_UsingFixedFunction)
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#define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
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#else
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#define Debug_Timer_UDB_CONTROL_REG_REMOVED (1u)
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#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
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/***************************************
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* Type defines
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***************************************/
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/**************************************************************************
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* Sleep Wakeup Backup structure for Timer Component
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*************************************************************************/
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typedef struct
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{
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uint8 TimerEnableState;
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#if(!Debug_Timer_UsingFixedFunction)
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uint16 TimerUdb;
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uint8 InterruptMaskValue;
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#if (Debug_Timer_UsingHWCaptureCounter)
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uint8 TimerCaptureCounter;
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#endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
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#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
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uint8 TimerControlRegister;
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#endif /* variable declaration for backing up enable state of the Timer */
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#endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
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}Debug_Timer_backupStruct;
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/***************************************
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* Function Prototypes
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***************************************/
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void Debug_Timer_Start(void) ;
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void Debug_Timer_Stop(void) ;
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void Debug_Timer_SetInterruptMode(uint8 interruptMode) ;
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uint8 Debug_Timer_ReadStatusRegister(void) ;
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/* Deprecated function. Do not use this in future. Retained for backward compatibility */
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#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
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#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
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uint8 Debug_Timer_ReadControlRegister(void) ;
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void Debug_Timer_WriteControlRegister(uint8 control) ;
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#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
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uint16 Debug_Timer_ReadPeriod(void) ;
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void Debug_Timer_WritePeriod(uint16 period) ;
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uint16 Debug_Timer_ReadCounter(void) ;
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void Debug_Timer_WriteCounter(uint16 counter) ;
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uint16 Debug_Timer_ReadCapture(void) ;
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void Debug_Timer_SoftwareCapture(void) ;
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#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
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#if (Debug_Timer_SoftwareCaptureMode)
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void Debug_Timer_SetCaptureMode(uint8 captureMode) ;
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#endif /* (!Debug_Timer_UsingFixedFunction) */
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#if (Debug_Timer_SoftwareTriggerMode)
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void Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
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#endif /* (Debug_Timer_SoftwareTriggerMode) */
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#if (Debug_Timer_EnableTriggerMode)
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void Debug_Timer_EnableTrigger(void) ;
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void Debug_Timer_DisableTrigger(void) ;
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#endif /* (Debug_Timer_EnableTriggerMode) */
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#if(Debug_Timer_InterruptOnCaptureCount)
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void Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
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#endif /* (Debug_Timer_InterruptOnCaptureCount) */
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#if (Debug_Timer_UsingHWCaptureCounter)
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void Debug_Timer_SetCaptureCount(uint8 captureCount) ;
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uint8 Debug_Timer_ReadCaptureCount(void) ;
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#endif /* (Debug_Timer_UsingHWCaptureCounter) */
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void Debug_Timer_ClearFIFO(void) ;
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#endif /* UDB Prototypes */
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/* Sleep Retention APIs */
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void Debug_Timer_Init(void) ;
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void Debug_Timer_Enable(void) ;
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void Debug_Timer_SaveConfig(void) ;
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void Debug_Timer_RestoreConfig(void) ;
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void Debug_Timer_Sleep(void) ;
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void Debug_Timer_Wakeup(void) ;
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/***************************************
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* Enumerated Types and Parameters
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***************************************/
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/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
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#define Debug_Timer__B_TIMER__CM_NONE 0
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#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
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#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
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#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
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#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
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/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
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#define Debug_Timer__B_TIMER__TM_NONE 0x00u
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#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
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#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
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#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
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#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
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/***************************************
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* Initialial Parameter Constants
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***************************************/
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#define Debug_Timer_INIT_PERIOD 31999u
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#define Debug_Timer_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
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#define Debug_Timer_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
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#if (Debug_Timer_UsingFixedFunction)
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#define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
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((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)))
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#else
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#define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
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((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
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((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT)))
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#endif /* (Debug_Timer_UsingFixedFunction) */
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#define Debug_Timer_INIT_CAPTURE_COUNT (2u)
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#define Debug_Timer_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT))
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/***************************************
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* Registers
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***************************************/
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#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
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/***************************************
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* Fixed Function Registers
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***************************************/
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#define Debug_Timer_STATUS (*(reg8 *) Debug_Timer_TimerHW__SR0 )
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/* In Fixed Function Block Status and Mask are the same register */
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#define Debug_Timer_STATUS_MASK (*(reg8 *) Debug_Timer_TimerHW__SR0 )
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#define Debug_Timer_CONTROL (*(reg8 *) Debug_Timer_TimerHW__CFG0)
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#define Debug_Timer_CONTROL2 (*(reg8 *) Debug_Timer_TimerHW__CFG1)
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#define Debug_Timer_CONTROL2_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG1)
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#define Debug_Timer_RT1 (*(reg8 *) Debug_Timer_TimerHW__RT1)
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#define Debug_Timer_RT1_PTR ( (reg8 *) Debug_Timer_TimerHW__RT1)
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#if (CY_PSOC3 || CY_PSOC5LP)
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#define Debug_Timer_CONTROL3 (*(reg8 *) Debug_Timer_TimerHW__CFG2)
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#define Debug_Timer_CONTROL3_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG2)
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#endif /* (CY_PSOC3 || CY_PSOC5LP) */
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#define Debug_Timer_GLOBAL_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG)
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#define Debug_Timer_GLOBAL_STBY_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG)
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#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerHW__CAP0 )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CAP0 )
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#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerHW__PER0 )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__PER0 )
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#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
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/***************************************
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* Register Constants
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***************************************/
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/* Fixed Function Block Chosen */
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#define Debug_Timer_BLOCK_EN_MASK Debug_Timer_TimerHW__PM_ACT_MSK
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#define Debug_Timer_BLOCK_STBY_EN_MASK Debug_Timer_TimerHW__PM_STBY_MSK
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/* Control Register Bit Locations */
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/* Interrupt Count - Not valid for Fixed Function Block */
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#define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u
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/* Trigger Polarity - Not valid for Fixed Function Block */
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#define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x00u
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/* Trigger Enable - Not valid for Fixed Function Block */
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#define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x00u
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/* Capture Polarity - Not valid for Fixed Function Block */
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#define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x00u
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/* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
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#define Debug_Timer_CTRL_ENABLE_SHIFT 0x00u
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/* Control Register Bit Masks */
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#define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
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/* Control2 Register Bit Masks */
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/* As defined in Register Map, Part of the TMRX_CFG1 register */
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#define Debug_Timer_CTRL2_IRQ_SEL_SHIFT 0x00u
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#define Debug_Timer_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT))
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#if (CY_PSOC5A)
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/* Use CFG1 Mode bits to set run mode */
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/* As defined by Verilog Implementation */
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#define Debug_Timer_CTRL_MODE_SHIFT 0x01u
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#define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
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#endif /* (CY_PSOC5A) */
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#if (CY_PSOC3 || CY_PSOC5LP)
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/* Control3 Register Bit Locations */
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#define Debug_Timer_CTRL_RCOD_SHIFT 0x02u
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#define Debug_Timer_CTRL_ENBL_SHIFT 0x00u
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#define Debug_Timer_CTRL_MODE_SHIFT 0x00u
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/* Control3 Register Bit Masks */
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#define Debug_Timer_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
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#define Debug_Timer_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
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#define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */
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#define Debug_Timer_CTRL_RCOD ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT))
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#define Debug_Timer_CTRL_ENBL ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT))
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#endif /* (CY_PSOC3 || CY_PSOC5LP) */
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/*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
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#define Debug_Timer_RT1_SHIFT 0x04u
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/* Sync TC and CMP bit masks */
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#define Debug_Timer_RT1_MASK ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
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#define Debug_Timer_SYNC ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
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#define Debug_Timer_SYNCDSI_SHIFT 0x00u
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/* Sync all DSI inputs with Mask */
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#define Debug_Timer_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
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/* Sync all DSI inputs */
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#define Debug_Timer_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
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#define Debug_Timer_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT))
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#define Debug_Timer_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT))
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#define Debug_Timer_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT))
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/* Status Register Bit Locations */
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/* As defined in Register Map, part of TMRX_SR0 register */
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#define Debug_Timer_STATUS_TC_SHIFT 0x07u
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/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
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#define Debug_Timer_STATUS_CAPTURE_SHIFT 0x06u
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/* As defined in Register Map, part of TMRX_SR0 register */
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#define Debug_Timer_STATUS_TC_INT_MASK_SHIFT (Debug_Timer_STATUS_TC_SHIFT - 0x04u)
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/* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
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#define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u)
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/* Status Register Bit Masks */
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#define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
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#define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
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/* Interrupt Enable Bit-Mask for interrupt on TC */
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#define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT))
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/* Interrupt Enable Bit-Mask for interrupt on Capture */
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#define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))
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#else /* UDB Registers and Register Constants */
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/***************************************
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* UDB Registers
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***************************************/
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#define Debug_Timer_STATUS (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG )
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#define Debug_Timer_STATUS_MASK (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG)
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#define Debug_Timer_STATUS_AUX_CTRL (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
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#define Debug_Timer_CONTROL (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
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#if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */
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#define Debug_Timer_CAPTURE_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_PERIOD_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_COUNTER_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */
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#if(CY_PSOC3) /* 8-bit addres space */
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#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#else /* 16-bit address space */
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#define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
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#define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
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#define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
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#endif /* CY_PSOC3 */
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#elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */
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#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#else /* 32-bit Timer */
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#if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
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#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
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#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
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#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#else /* 32-bit address space */
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#define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
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#define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
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#define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
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#define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
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#define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
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#define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
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#endif /* CY_PSOC3 || CY_PSOC5 */
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#endif
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#define Debug_Timer_COUNTER_LSB_PTR_8BIT ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
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#if (Debug_Timer_UsingHWCaptureCounter)
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#define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
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#define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
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#define Debug_Timer_CAPTURE_COUNT_CTRL (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
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#define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
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#endif /* (Debug_Timer_UsingHWCaptureCounter) */
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/***************************************
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* Register Constants
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***************************************/
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/* Control Register Bit Locations */
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#define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */
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#define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */
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#define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */
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#define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */
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#define Debug_Timer_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */
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/* Control Register Bit Masks */
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#define Debug_Timer_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT))
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#define Debug_Timer_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
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#define Debug_Timer_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT))
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#define Debug_Timer_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
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#define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
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/* Bit Counter (7-bit) Control Register Bit Definitions */
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/* As defined by the Register map for the AUX Control Register */
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#define Debug_Timer_CNTR_ENABLE 0x20u
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/* Status Register Bit Locations */
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#define Debug_Timer_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */
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#define Debug_Timer_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */
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#define Debug_Timer_STATUS_TC_INT_MASK_SHIFT Debug_Timer_STATUS_TC_SHIFT
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#define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT Debug_Timer_STATUS_CAPTURE_SHIFT
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#define Debug_Timer_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */
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#define Debug_Timer_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */
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#define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT
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/* Status Register Bit Masks */
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/* Sticky TC Event Bit-Mask */
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#define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
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/* Sticky Capture Event Bit-Mask */
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#define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
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/* Interrupt Enable Bit-Mask */
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#define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
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/* Interrupt Enable Bit-Mask */
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#define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
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/* NOT-Sticky FIFO Full Bit-Mask */
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#define Debug_Timer_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
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/* NOT-Sticky FIFO Not Empty Bit-Mask */
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#define Debug_Timer_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT))
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/* Interrupt Enable Bit-Mask */
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#define Debug_Timer_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
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#define Debug_Timer_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */
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/* Datapath Auxillary Control Register definitions */
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#define Debug_Timer_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */
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#define Debug_Timer_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */
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#define Debug_Timer_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */
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#define Debug_Timer_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */
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#define Debug_Timer_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */
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#endif /* Implementation Specific Registers and Register Constants */
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#endif /* CY_Timer_v2_30_Debug_Timer_H */
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/* [] END OF FILE */
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