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125 lines
4.6 KiB
C
125 lines
4.6 KiB
C
/*******************************************************************************
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* File Name: NOR_Clock.h
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* Version 2.20
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*
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* Description:
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* Provides the function and constant definitions for the clock component.
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*
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* Note:
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*
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********************************************************************************
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* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#if !defined(CY_CLOCK_NOR_Clock_H)
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#define CY_CLOCK_NOR_Clock_H
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#include <cytypes.h>
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#include <cyfitter.h>
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/***************************************
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* Conditional Compilation Parameters
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***************************************/
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/* Check to see if required defines such as CY_PSOC5LP are available */
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/* They are defined starting with cy_boot v3.0 */
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#if !defined (CY_PSOC5LP)
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#error Component cy_clock_v2_20 requires cy_boot v3.0 or later
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#endif /* (CY_PSOC5LP) */
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/***************************************
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* Function Prototypes
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***************************************/
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void NOR_Clock_Start(void) ;
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void NOR_Clock_Stop(void) ;
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#if(CY_PSOC3 || CY_PSOC5LP)
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void NOR_Clock_StopBlock(void) ;
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#endif /* (CY_PSOC3 || CY_PSOC5LP) */
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void NOR_Clock_StandbyPower(uint8 state) ;
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void NOR_Clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
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;
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uint16 NOR_Clock_GetDividerRegister(void) ;
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void NOR_Clock_SetModeRegister(uint8 modeBitMask) ;
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void NOR_Clock_ClearModeRegister(uint8 modeBitMask) ;
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uint8 NOR_Clock_GetModeRegister(void) ;
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void NOR_Clock_SetSourceRegister(uint8 clkSource) ;
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uint8 NOR_Clock_GetSourceRegister(void) ;
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#if defined(NOR_Clock__CFG3)
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void NOR_Clock_SetPhaseRegister(uint8 clkPhase) ;
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uint8 NOR_Clock_GetPhaseRegister(void) ;
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#endif /* defined(NOR_Clock__CFG3) */
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#define NOR_Clock_Enable() NOR_Clock_Start()
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#define NOR_Clock_Disable() NOR_Clock_Stop()
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#define NOR_Clock_SetDivider(clkDivider) NOR_Clock_SetDividerRegister(clkDivider, 1u)
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#define NOR_Clock_SetDividerValue(clkDivider) NOR_Clock_SetDividerRegister((clkDivider) - 1u, 1u)
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#define NOR_Clock_SetMode(clkMode) NOR_Clock_SetModeRegister(clkMode)
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#define NOR_Clock_SetSource(clkSource) NOR_Clock_SetSourceRegister(clkSource)
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#if defined(NOR_Clock__CFG3)
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#define NOR_Clock_SetPhase(clkPhase) NOR_Clock_SetPhaseRegister(clkPhase)
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#define NOR_Clock_SetPhaseValue(clkPhase) NOR_Clock_SetPhaseRegister((clkPhase) + 1u)
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#endif /* defined(NOR_Clock__CFG3) */
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/***************************************
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* Registers
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***************************************/
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/* Register to enable or disable the clock */
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#define NOR_Clock_CLKEN (* (reg8 *) NOR_Clock__PM_ACT_CFG)
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#define NOR_Clock_CLKEN_PTR ((reg8 *) NOR_Clock__PM_ACT_CFG)
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/* Register to enable or disable the clock */
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#define NOR_Clock_CLKSTBY (* (reg8 *) NOR_Clock__PM_STBY_CFG)
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#define NOR_Clock_CLKSTBY_PTR ((reg8 *) NOR_Clock__PM_STBY_CFG)
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/* Clock LSB divider configuration register. */
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#define NOR_Clock_DIV_LSB (* (reg8 *) NOR_Clock__CFG0)
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#define NOR_Clock_DIV_LSB_PTR ((reg8 *) NOR_Clock__CFG0)
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#define NOR_Clock_DIV_PTR ((reg16 *) NOR_Clock__CFG0)
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/* Clock MSB divider configuration register. */
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#define NOR_Clock_DIV_MSB (* (reg8 *) NOR_Clock__CFG1)
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#define NOR_Clock_DIV_MSB_PTR ((reg8 *) NOR_Clock__CFG1)
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/* Mode and source configuration register */
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#define NOR_Clock_MOD_SRC (* (reg8 *) NOR_Clock__CFG2)
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#define NOR_Clock_MOD_SRC_PTR ((reg8 *) NOR_Clock__CFG2)
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#if defined(NOR_Clock__CFG3)
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/* Analog clock phase configuration register */
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#define NOR_Clock_PHASE (* (reg8 *) NOR_Clock__CFG3)
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#define NOR_Clock_PHASE_PTR ((reg8 *) NOR_Clock__CFG3)
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#endif /* defined(NOR_Clock__CFG3) */
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/**************************************
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* Register Constants
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**************************************/
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/* Power manager register masks */
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#define NOR_Clock_CLKEN_MASK NOR_Clock__PM_ACT_MSK
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#define NOR_Clock_CLKSTBY_MASK NOR_Clock__PM_STBY_MSK
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/* CFG2 field masks */
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#define NOR_Clock_SRC_SEL_MSK NOR_Clock__CFG2_SRC_SEL_MASK
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#define NOR_Clock_MODE_MASK (~(NOR_Clock_SRC_SEL_MSK))
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#if defined(NOR_Clock__CFG3)
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/* CFG3 phase mask */
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#define NOR_Clock_PHASE_MASK NOR_Clock__CFG3_PHASE_DLY_MASK
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#endif /* defined(NOR_Clock__CFG3) */
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#endif /* CY_CLOCK_NOR_Clock_H */
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/* [] END OF FILE */
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