mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2024-06-02 06:41:36 +00:00
5361 lines
223 KiB
C
Executable File
5361 lines
223 KiB
C
Executable File
/*******************************************************************************
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* FILENAME: cydevice_trm.h
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*
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* PSoC Creator 3.2
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*
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* DESCRIPTION:
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* This file provides all of the address values for the entire PSoC device.
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* This file is automatically generated by PSoC Creator.
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*
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********************************************************************************
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* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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********************************************************************************/
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#if !defined(CYDEVICE_TRM_H)
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#define CYDEVICE_TRM_H
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#define CYDEV_FLASH_BASE 0x00000000u
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#define CYDEV_FLASH_SIZE 0x00020000u
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#define CYREG_FLASH_DATA_MBASE 0x00000000u
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#define CYREG_FLASH_DATA_MSIZE 0x00020000u
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#define CYDEV_SRAM_BASE 0x1fffc000u
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#define CYDEV_SRAM_SIZE 0x00008000u
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#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u
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#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u
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#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u
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#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u
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#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u
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#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u
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#define CYREG_SRAM_CODE_MBASE 0x1fffc000u
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#define CYREG_SRAM_CODE_MSIZE 0x00004000u
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#define CYREG_SRAM_DATA_MBASE 0x20000000u
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#define CYREG_SRAM_DATA_MSIZE 0x00004000u
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#define CYREG_SRAM_DATA16K_MBASE 0x20001000u
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#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u
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#define CYREG_SRAM_DATA32K_MBASE 0x20002000u
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#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u
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#define CYREG_SRAM_DATA64K_MBASE 0x20004000u
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#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u
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#define CYDEV_DMA_BASE 0x20008000u
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#define CYDEV_DMA_SIZE 0x00008000u
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#define CYREG_DMA_SRAM64K_MBASE 0x20008000u
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#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u
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#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u
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#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u
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#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u
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#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u
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#define CYREG_DMA_SRAM_MBASE 0x2000f000u
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#define CYREG_DMA_SRAM_MSIZE 0x00001000u
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#define CYDEV_CLKDIST_BASE 0x40004000u
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#define CYDEV_CLKDIST_SIZE 0x00000110u
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#define CYREG_CLKDIST_CR 0x40004000u
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#define CYREG_CLKDIST_LD 0x40004001u
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#define CYREG_CLKDIST_WRK0 0x40004002u
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#define CYREG_CLKDIST_WRK1 0x40004003u
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#define CYREG_CLKDIST_MSTR0 0x40004004u
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#define CYREG_CLKDIST_MSTR1 0x40004005u
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#define CYREG_CLKDIST_BCFG0 0x40004006u
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#define CYREG_CLKDIST_BCFG1 0x40004007u
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#define CYREG_CLKDIST_BCFG2 0x40004008u
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#define CYREG_CLKDIST_UCFG 0x40004009u
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#define CYREG_CLKDIST_DLY0 0x4000400au
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#define CYREG_CLKDIST_DLY1 0x4000400bu
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#define CYREG_CLKDIST_DMASK 0x40004010u
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#define CYREG_CLKDIST_AMASK 0x40004014u
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#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u
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#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u
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#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u
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#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u
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#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u
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#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u
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#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u
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#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u
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#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u
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#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u
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#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u
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#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au
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#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu
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#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu
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#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du
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#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu
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#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u
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#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u
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#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u
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#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u
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#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u
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#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u
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#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u
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#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u
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#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u
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#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u
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#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u
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#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au
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#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu
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#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u
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#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu
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#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du
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#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu
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#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u
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#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u
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#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u
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#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u
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#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u
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#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u
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#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u
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#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u
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#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u
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#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u
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#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u
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#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u
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#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u
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#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u
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#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u
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#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u
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#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au
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#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu
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#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu
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#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u
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#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu
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#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du
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#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu
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#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu
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#define CYDEV_FASTCLK_BASE 0x40004200u
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#define CYDEV_FASTCLK_SIZE 0x00000026u
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#define CYDEV_FASTCLK_IMO_BASE 0x40004200u
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#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u
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#define CYREG_FASTCLK_IMO_CR 0x40004200u
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#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u
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#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u
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#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u
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#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u
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#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u
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#define CYDEV_FASTCLK_PLL_BASE 0x40004220u
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#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u
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#define CYREG_FASTCLK_PLL_CFG0 0x40004220u
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#define CYREG_FASTCLK_PLL_CFG1 0x40004221u
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#define CYREG_FASTCLK_PLL_P 0x40004222u
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#define CYREG_FASTCLK_PLL_Q 0x40004223u
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#define CYREG_FASTCLK_PLL_SR 0x40004225u
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#define CYDEV_SLOWCLK_BASE 0x40004300u
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#define CYDEV_SLOWCLK_SIZE 0x0000000bu
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#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u
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#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u
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#define CYREG_SLOWCLK_ILO_CR0 0x40004300u
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#define CYREG_SLOWCLK_ILO_CR1 0x40004301u
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#define CYDEV_SLOWCLK_X32_BASE 0x40004308u
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#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u
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#define CYREG_SLOWCLK_X32_CR 0x40004308u
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#define CYREG_SLOWCLK_X32_CFG 0x40004309u
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#define CYREG_SLOWCLK_X32_TST 0x4000430au
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#define CYDEV_BOOST_BASE 0x40004320u
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#define CYDEV_BOOST_SIZE 0x00000007u
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#define CYREG_BOOST_CR0 0x40004320u
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#define CYREG_BOOST_CR1 0x40004321u
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#define CYREG_BOOST_CR2 0x40004322u
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#define CYREG_BOOST_CR3 0x40004323u
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#define CYREG_BOOST_SR 0x40004324u
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#define CYREG_BOOST_CR4 0x40004325u
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#define CYREG_BOOST_SR2 0x40004326u
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#define CYDEV_PWRSYS_BASE 0x40004330u
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#define CYDEV_PWRSYS_SIZE 0x00000002u
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#define CYREG_PWRSYS_CR0 0x40004330u
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#define CYREG_PWRSYS_CR1 0x40004331u
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#define CYDEV_PM_BASE 0x40004380u
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#define CYDEV_PM_SIZE 0x00000057u
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#define CYREG_PM_TW_CFG0 0x40004380u
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#define CYREG_PM_TW_CFG1 0x40004381u
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#define CYREG_PM_TW_CFG2 0x40004382u
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#define CYREG_PM_WDT_CFG 0x40004383u
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#define CYREG_PM_WDT_CR 0x40004384u
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#define CYREG_PM_INT_SR 0x40004390u
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#define CYREG_PM_MODE_CFG0 0x40004391u
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#define CYREG_PM_MODE_CFG1 0x40004392u
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#define CYREG_PM_MODE_CSR 0x40004393u
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#define CYREG_PM_USB_CR0 0x40004394u
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#define CYREG_PM_WAKEUP_CFG0 0x40004398u
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#define CYREG_PM_WAKEUP_CFG1 0x40004399u
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#define CYREG_PM_WAKEUP_CFG2 0x4000439au
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#define CYDEV_PM_ACT_BASE 0x400043a0u
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#define CYDEV_PM_ACT_SIZE 0x0000000eu
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#define CYREG_PM_ACT_CFG0 0x400043a0u
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#define CYREG_PM_ACT_CFG1 0x400043a1u
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#define CYREG_PM_ACT_CFG2 0x400043a2u
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#define CYREG_PM_ACT_CFG3 0x400043a3u
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#define CYREG_PM_ACT_CFG4 0x400043a4u
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#define CYREG_PM_ACT_CFG5 0x400043a5u
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#define CYREG_PM_ACT_CFG6 0x400043a6u
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#define CYREG_PM_ACT_CFG7 0x400043a7u
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#define CYREG_PM_ACT_CFG8 0x400043a8u
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#define CYREG_PM_ACT_CFG9 0x400043a9u
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#define CYREG_PM_ACT_CFG10 0x400043aau
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#define CYREG_PM_ACT_CFG11 0x400043abu
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#define CYREG_PM_ACT_CFG12 0x400043acu
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#define CYREG_PM_ACT_CFG13 0x400043adu
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#define CYDEV_PM_STBY_BASE 0x400043b0u
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#define CYDEV_PM_STBY_SIZE 0x0000000eu
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#define CYREG_PM_STBY_CFG0 0x400043b0u
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#define CYREG_PM_STBY_CFG1 0x400043b1u
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#define CYREG_PM_STBY_CFG2 0x400043b2u
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#define CYREG_PM_STBY_CFG3 0x400043b3u
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#define CYREG_PM_STBY_CFG4 0x400043b4u
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#define CYREG_PM_STBY_CFG5 0x400043b5u
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#define CYREG_PM_STBY_CFG6 0x400043b6u
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#define CYREG_PM_STBY_CFG7 0x400043b7u
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#define CYREG_PM_STBY_CFG8 0x400043b8u
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#define CYREG_PM_STBY_CFG9 0x400043b9u
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#define CYREG_PM_STBY_CFG10 0x400043bau
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#define CYREG_PM_STBY_CFG11 0x400043bbu
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#define CYREG_PM_STBY_CFG12 0x400043bcu
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#define CYREG_PM_STBY_CFG13 0x400043bdu
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#define CYDEV_PM_AVAIL_BASE 0x400043c0u
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#define CYDEV_PM_AVAIL_SIZE 0x00000017u
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#define CYREG_PM_AVAIL_CR0 0x400043c0u
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#define CYREG_PM_AVAIL_CR1 0x400043c1u
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#define CYREG_PM_AVAIL_CR2 0x400043c2u
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#define CYREG_PM_AVAIL_CR3 0x400043c3u
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#define CYREG_PM_AVAIL_CR4 0x400043c4u
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#define CYREG_PM_AVAIL_CR5 0x400043c5u
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#define CYREG_PM_AVAIL_CR6 0x400043c6u
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#define CYREG_PM_AVAIL_SR0 0x400043d0u
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#define CYREG_PM_AVAIL_SR1 0x400043d1u
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#define CYREG_PM_AVAIL_SR2 0x400043d2u
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#define CYREG_PM_AVAIL_SR3 0x400043d3u
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#define CYREG_PM_AVAIL_SR4 0x400043d4u
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#define CYREG_PM_AVAIL_SR5 0x400043d5u
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#define CYREG_PM_AVAIL_SR6 0x400043d6u
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#define CYDEV_PICU_BASE 0x40004500u
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#define CYDEV_PICU_SIZE 0x000000b0u
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#define CYDEV_PICU_INTTYPE_BASE 0x40004500u
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#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u
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#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u
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#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u
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#define CYREG_PICU0_INTTYPE0 0x40004500u
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#define CYREG_PICU0_INTTYPE1 0x40004501u
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#define CYREG_PICU0_INTTYPE2 0x40004502u
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#define CYREG_PICU0_INTTYPE3 0x40004503u
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#define CYREG_PICU0_INTTYPE4 0x40004504u
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#define CYREG_PICU0_INTTYPE5 0x40004505u
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#define CYREG_PICU0_INTTYPE6 0x40004506u
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#define CYREG_PICU0_INTTYPE7 0x40004507u
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#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u
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#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u
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#define CYREG_PICU1_INTTYPE0 0x40004508u
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#define CYREG_PICU1_INTTYPE1 0x40004509u
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#define CYREG_PICU1_INTTYPE2 0x4000450au
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#define CYREG_PICU1_INTTYPE3 0x4000450bu
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#define CYREG_PICU1_INTTYPE4 0x4000450cu
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#define CYREG_PICU1_INTTYPE5 0x4000450du
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#define CYREG_PICU1_INTTYPE6 0x4000450eu
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#define CYREG_PICU1_INTTYPE7 0x4000450fu
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#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u
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#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u
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#define CYREG_PICU2_INTTYPE0 0x40004510u
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#define CYREG_PICU2_INTTYPE1 0x40004511u
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#define CYREG_PICU2_INTTYPE2 0x40004512u
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#define CYREG_PICU2_INTTYPE3 0x40004513u
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#define CYREG_PICU2_INTTYPE4 0x40004514u
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#define CYREG_PICU2_INTTYPE5 0x40004515u
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#define CYREG_PICU2_INTTYPE6 0x40004516u
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#define CYREG_PICU2_INTTYPE7 0x40004517u
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#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u
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#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u
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#define CYREG_PICU3_INTTYPE0 0x40004518u
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#define CYREG_PICU3_INTTYPE1 0x40004519u
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#define CYREG_PICU3_INTTYPE2 0x4000451au
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#define CYREG_PICU3_INTTYPE3 0x4000451bu
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#define CYREG_PICU3_INTTYPE4 0x4000451cu
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#define CYREG_PICU3_INTTYPE5 0x4000451du
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#define CYREG_PICU3_INTTYPE6 0x4000451eu
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#define CYREG_PICU3_INTTYPE7 0x4000451fu
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#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u
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#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u
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#define CYREG_PICU4_INTTYPE0 0x40004520u
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#define CYREG_PICU4_INTTYPE1 0x40004521u
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#define CYREG_PICU4_INTTYPE2 0x40004522u
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#define CYREG_PICU4_INTTYPE3 0x40004523u
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#define CYREG_PICU4_INTTYPE4 0x40004524u
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#define CYREG_PICU4_INTTYPE5 0x40004525u
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#define CYREG_PICU4_INTTYPE6 0x40004526u
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#define CYREG_PICU4_INTTYPE7 0x40004527u
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#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u
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#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u
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#define CYREG_PICU5_INTTYPE0 0x40004528u
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#define CYREG_PICU5_INTTYPE1 0x40004529u
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#define CYREG_PICU5_INTTYPE2 0x4000452au
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#define CYREG_PICU5_INTTYPE3 0x4000452bu
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#define CYREG_PICU5_INTTYPE4 0x4000452cu
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#define CYREG_PICU5_INTTYPE5 0x4000452du
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#define CYREG_PICU5_INTTYPE6 0x4000452eu
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#define CYREG_PICU5_INTTYPE7 0x4000452fu
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#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u
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#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u
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#define CYREG_PICU6_INTTYPE0 0x40004530u
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#define CYREG_PICU6_INTTYPE1 0x40004531u
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#define CYREG_PICU6_INTTYPE2 0x40004532u
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#define CYREG_PICU6_INTTYPE3 0x40004533u
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#define CYREG_PICU6_INTTYPE4 0x40004534u
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#define CYREG_PICU6_INTTYPE5 0x40004535u
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#define CYREG_PICU6_INTTYPE6 0x40004536u
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#define CYREG_PICU6_INTTYPE7 0x40004537u
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#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u
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#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u
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#define CYREG_PICU12_INTTYPE0 0x40004560u
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#define CYREG_PICU12_INTTYPE1 0x40004561u
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#define CYREG_PICU12_INTTYPE2 0x40004562u
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#define CYREG_PICU12_INTTYPE3 0x40004563u
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#define CYREG_PICU12_INTTYPE4 0x40004564u
|
|
#define CYREG_PICU12_INTTYPE5 0x40004565u
|
|
#define CYREG_PICU12_INTTYPE6 0x40004566u
|
|
#define CYREG_PICU12_INTTYPE7 0x40004567u
|
|
#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u
|
|
#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u
|
|
#define CYREG_PICU15_INTTYPE0 0x40004578u
|
|
#define CYREG_PICU15_INTTYPE1 0x40004579u
|
|
#define CYREG_PICU15_INTTYPE2 0x4000457au
|
|
#define CYREG_PICU15_INTTYPE3 0x4000457bu
|
|
#define CYREG_PICU15_INTTYPE4 0x4000457cu
|
|
#define CYREG_PICU15_INTTYPE5 0x4000457du
|
|
#define CYREG_PICU15_INTTYPE6 0x4000457eu
|
|
#define CYREG_PICU15_INTTYPE7 0x4000457fu
|
|
#define CYDEV_PICU_STAT_BASE 0x40004580u
|
|
#define CYDEV_PICU_STAT_SIZE 0x00000010u
|
|
#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u
|
|
#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u
|
|
#define CYREG_PICU0_INTSTAT 0x40004580u
|
|
#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u
|
|
#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u
|
|
#define CYREG_PICU1_INTSTAT 0x40004581u
|
|
#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u
|
|
#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u
|
|
#define CYREG_PICU2_INTSTAT 0x40004582u
|
|
#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u
|
|
#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u
|
|
#define CYREG_PICU3_INTSTAT 0x40004583u
|
|
#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u
|
|
#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u
|
|
#define CYREG_PICU4_INTSTAT 0x40004584u
|
|
#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u
|
|
#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u
|
|
#define CYREG_PICU5_INTSTAT 0x40004585u
|
|
#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u
|
|
#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u
|
|
#define CYREG_PICU6_INTSTAT 0x40004586u
|
|
#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu
|
|
#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u
|
|
#define CYREG_PICU12_INTSTAT 0x4000458cu
|
|
#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu
|
|
#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u
|
|
#define CYREG_PICU15_INTSTAT 0x4000458fu
|
|
#define CYDEV_PICU_SNAP_BASE 0x40004590u
|
|
#define CYDEV_PICU_SNAP_SIZE 0x00000010u
|
|
#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u
|
|
#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u
|
|
#define CYREG_PICU0_SNAP 0x40004590u
|
|
#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u
|
|
#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u
|
|
#define CYREG_PICU1_SNAP 0x40004591u
|
|
#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u
|
|
#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u
|
|
#define CYREG_PICU2_SNAP 0x40004592u
|
|
#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u
|
|
#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u
|
|
#define CYREG_PICU3_SNAP 0x40004593u
|
|
#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u
|
|
#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u
|
|
#define CYREG_PICU4_SNAP 0x40004594u
|
|
#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u
|
|
#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u
|
|
#define CYREG_PICU5_SNAP 0x40004595u
|
|
#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u
|
|
#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u
|
|
#define CYREG_PICU6_SNAP 0x40004596u
|
|
#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu
|
|
#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u
|
|
#define CYREG_PICU12_SNAP 0x4000459cu
|
|
#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu
|
|
#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u
|
|
#define CYREG_PICU_15_SNAP_15 0x4000459fu
|
|
#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u
|
|
#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u
|
|
#define CYREG_PICU0_DISABLE_COR 0x400045a0u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u
|
|
#define CYREG_PICU1_DISABLE_COR 0x400045a1u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u
|
|
#define CYREG_PICU2_DISABLE_COR 0x400045a2u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u
|
|
#define CYREG_PICU3_DISABLE_COR 0x400045a3u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u
|
|
#define CYREG_PICU4_DISABLE_COR 0x400045a4u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u
|
|
#define CYREG_PICU5_DISABLE_COR 0x400045a5u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u
|
|
#define CYREG_PICU6_DISABLE_COR 0x400045a6u
|
|
#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu
|
|
#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u
|
|
#define CYREG_PICU12_DISABLE_COR 0x400045acu
|
|
#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu
|
|
#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u
|
|
#define CYREG_PICU15_DISABLE_COR 0x400045afu
|
|
#define CYDEV_MFGCFG_BASE 0x40004600u
|
|
#define CYDEV_MFGCFG_SIZE 0x000000edu
|
|
#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u
|
|
#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u
|
|
#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u
|
|
#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u
|
|
#define CYREG_DAC0_TR 0x40004608u
|
|
#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u
|
|
#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u
|
|
#define CYREG_DAC1_TR 0x40004609u
|
|
#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au
|
|
#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u
|
|
#define CYREG_DAC2_TR 0x4000460au
|
|
#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu
|
|
#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u
|
|
#define CYREG_DAC3_TR 0x4000460bu
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u
|
|
#define CYREG_NPUMP_DSM_TR0 0x40004610u
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u
|
|
#define CYREG_NPUMP_SC_TR0 0x40004611u
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u
|
|
#define CYREG_NPUMP_OPAMP_TR0 0x40004612u
|
|
#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u
|
|
#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u
|
|
#define CYREG_SAR0_TR0 0x40004614u
|
|
#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u
|
|
#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u
|
|
#define CYREG_SAR1_TR0 0x40004616u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u
|
|
#define CYREG_OPAMP0_TR0 0x40004620u
|
|
#define CYREG_OPAMP0_TR1 0x40004621u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u
|
|
#define CYREG_OPAMP1_TR0 0x40004622u
|
|
#define CYREG_OPAMP1_TR1 0x40004623u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u
|
|
#define CYREG_OPAMP2_TR0 0x40004624u
|
|
#define CYREG_OPAMP2_TR1 0x40004625u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u
|
|
#define CYREG_OPAMP3_TR0 0x40004626u
|
|
#define CYREG_OPAMP3_TR1 0x40004627u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u
|
|
#define CYREG_CMP0_TR0 0x40004630u
|
|
#define CYREG_CMP0_TR1 0x40004631u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u
|
|
#define CYREG_CMP1_TR0 0x40004632u
|
|
#define CYREG_CMP1_TR1 0x40004633u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u
|
|
#define CYREG_CMP2_TR0 0x40004634u
|
|
#define CYREG_CMP2_TR1 0x40004635u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u
|
|
#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u
|
|
#define CYREG_CMP3_TR0 0x40004636u
|
|
#define CYREG_CMP3_TR1 0x40004637u
|
|
#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u
|
|
#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu
|
|
#define CYREG_PWRSYS_HIB_TR0 0x40004680u
|
|
#define CYREG_PWRSYS_HIB_TR1 0x40004681u
|
|
#define CYREG_PWRSYS_I2C_TR 0x40004682u
|
|
#define CYREG_PWRSYS_SLP_TR 0x40004683u
|
|
#define CYREG_PWRSYS_BUZZ_TR 0x40004684u
|
|
#define CYREG_PWRSYS_WAKE_TR0 0x40004685u
|
|
#define CYREG_PWRSYS_WAKE_TR1 0x40004686u
|
|
#define CYREG_PWRSYS_BREF_TR 0x40004687u
|
|
#define CYREG_PWRSYS_BG_TR 0x40004688u
|
|
#define CYREG_PWRSYS_WAKE_TR2 0x40004689u
|
|
#define CYREG_PWRSYS_WAKE_TR3 0x4000468au
|
|
#define CYDEV_MFGCFG_ILO_BASE 0x40004690u
|
|
#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u
|
|
#define CYREG_ILO_TR0 0x40004690u
|
|
#define CYREG_ILO_TR1 0x40004691u
|
|
#define CYDEV_MFGCFG_X32_BASE 0x40004698u
|
|
#define CYDEV_MFGCFG_X32_SIZE 0x00000001u
|
|
#define CYREG_X32_TR 0x40004698u
|
|
#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u
|
|
#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u
|
|
#define CYREG_IMO_TR0 0x400046a0u
|
|
#define CYREG_IMO_TR1 0x400046a1u
|
|
#define CYREG_IMO_GAIN 0x400046a2u
|
|
#define CYREG_IMO_C36M 0x400046a3u
|
|
#define CYREG_IMO_TR2 0x400046a4u
|
|
#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u
|
|
#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u
|
|
#define CYREG_XMHZ_TR 0x400046a8u
|
|
#define CYREG_MFGCFG_DLY 0x400046c0u
|
|
#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u
|
|
#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du
|
|
#define CYREG_MLOGIC_DMPSTR 0x400046e2u
|
|
#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u
|
|
#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u
|
|
#define CYREG_MLOGIC_SEG_CR 0x400046e4u
|
|
#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u
|
|
#define CYREG_MLOGIC_DEBUG 0x400046e8u
|
|
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau
|
|
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u
|
|
#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau
|
|
#define CYREG_MLOGIC_REV_ID 0x400046ecu
|
|
#define CYDEV_RESET_BASE 0x400046f0u
|
|
#define CYDEV_RESET_SIZE 0x0000000fu
|
|
#define CYREG_RESET_IPOR_CR0 0x400046f0u
|
|
#define CYREG_RESET_IPOR_CR1 0x400046f1u
|
|
#define CYREG_RESET_IPOR_CR2 0x400046f2u
|
|
#define CYREG_RESET_IPOR_CR3 0x400046f3u
|
|
#define CYREG_RESET_CR0 0x400046f4u
|
|
#define CYREG_RESET_CR1 0x400046f5u
|
|
#define CYREG_RESET_CR2 0x400046f6u
|
|
#define CYREG_RESET_CR3 0x400046f7u
|
|
#define CYREG_RESET_CR4 0x400046f8u
|
|
#define CYREG_RESET_CR5 0x400046f9u
|
|
#define CYREG_RESET_SR0 0x400046fau
|
|
#define CYREG_RESET_SR1 0x400046fbu
|
|
#define CYREG_RESET_SR2 0x400046fcu
|
|
#define CYREG_RESET_SR3 0x400046fdu
|
|
#define CYREG_RESET_TR 0x400046feu
|
|
#define CYDEV_SPC_BASE 0x40004700u
|
|
#define CYDEV_SPC_SIZE 0x00000100u
|
|
#define CYREG_SPC_FM_EE_CR 0x40004700u
|
|
#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u
|
|
#define CYREG_SPC_EE_SCR 0x40004702u
|
|
#define CYREG_SPC_EE_ERR 0x40004703u
|
|
#define CYREG_SPC_CPU_DATA 0x40004720u
|
|
#define CYREG_SPC_DMA_DATA 0x40004721u
|
|
#define CYREG_SPC_SR 0x40004722u
|
|
#define CYREG_SPC_CR 0x40004723u
|
|
#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u
|
|
#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u
|
|
#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u
|
|
#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u
|
|
#define CYDEV_CACHE_BASE 0x40004800u
|
|
#define CYDEV_CACHE_SIZE 0x0000009cu
|
|
#define CYREG_CACHE_CC_CTL 0x40004800u
|
|
#define CYREG_CACHE_ECC_CORR 0x40004880u
|
|
#define CYREG_CACHE_ECC_ERR 0x40004888u
|
|
#define CYREG_CACHE_FLASH_ERR 0x40004890u
|
|
#define CYREG_CACHE_HITMISS 0x40004898u
|
|
#define CYDEV_I2C_BASE 0x40004900u
|
|
#define CYDEV_I2C_SIZE 0x000000e1u
|
|
#define CYREG_I2C_XCFG 0x400049c8u
|
|
#define CYREG_I2C_ADR 0x400049cau
|
|
#define CYREG_I2C_CFG 0x400049d6u
|
|
#define CYREG_I2C_CSR 0x400049d7u
|
|
#define CYREG_I2C_D 0x400049d8u
|
|
#define CYREG_I2C_MCSR 0x400049d9u
|
|
#define CYREG_I2C_CLK_DIV1 0x400049dbu
|
|
#define CYREG_I2C_CLK_DIV2 0x400049dcu
|
|
#define CYREG_I2C_TMOUT_CSR 0x400049ddu
|
|
#define CYREG_I2C_TMOUT_SR 0x400049deu
|
|
#define CYREG_I2C_TMOUT_CFG0 0x400049dfu
|
|
#define CYREG_I2C_TMOUT_CFG1 0x400049e0u
|
|
#define CYDEV_DEC_BASE 0x40004e00u
|
|
#define CYDEV_DEC_SIZE 0x00000015u
|
|
#define CYREG_DEC_CR 0x40004e00u
|
|
#define CYREG_DEC_SR 0x40004e01u
|
|
#define CYREG_DEC_SHIFT1 0x40004e02u
|
|
#define CYREG_DEC_SHIFT2 0x40004e03u
|
|
#define CYREG_DEC_DR2 0x40004e04u
|
|
#define CYREG_DEC_DR2H 0x40004e05u
|
|
#define CYREG_DEC_DR1 0x40004e06u
|
|
#define CYREG_DEC_OCOR 0x40004e08u
|
|
#define CYREG_DEC_OCORM 0x40004e09u
|
|
#define CYREG_DEC_OCORH 0x40004e0au
|
|
#define CYREG_DEC_GCOR 0x40004e0cu
|
|
#define CYREG_DEC_GCORH 0x40004e0du
|
|
#define CYREG_DEC_GVAL 0x40004e0eu
|
|
#define CYREG_DEC_OUTSAMP 0x40004e10u
|
|
#define CYREG_DEC_OUTSAMPM 0x40004e11u
|
|
#define CYREG_DEC_OUTSAMPH 0x40004e12u
|
|
#define CYREG_DEC_OUTSAMPS 0x40004e13u
|
|
#define CYREG_DEC_COHER 0x40004e14u
|
|
#define CYDEV_TMR0_BASE 0x40004f00u
|
|
#define CYDEV_TMR0_SIZE 0x0000000cu
|
|
#define CYREG_TMR0_CFG0 0x40004f00u
|
|
#define CYREG_TMR0_CFG1 0x40004f01u
|
|
#define CYREG_TMR0_CFG2 0x40004f02u
|
|
#define CYREG_TMR0_SR0 0x40004f03u
|
|
#define CYREG_TMR0_PER0 0x40004f04u
|
|
#define CYREG_TMR0_PER1 0x40004f05u
|
|
#define CYREG_TMR0_CNT_CMP0 0x40004f06u
|
|
#define CYREG_TMR0_CNT_CMP1 0x40004f07u
|
|
#define CYREG_TMR0_CAP0 0x40004f08u
|
|
#define CYREG_TMR0_CAP1 0x40004f09u
|
|
#define CYREG_TMR0_RT0 0x40004f0au
|
|
#define CYREG_TMR0_RT1 0x40004f0bu
|
|
#define CYDEV_TMR1_BASE 0x40004f0cu
|
|
#define CYDEV_TMR1_SIZE 0x0000000cu
|
|
#define CYREG_TMR1_CFG0 0x40004f0cu
|
|
#define CYREG_TMR1_CFG1 0x40004f0du
|
|
#define CYREG_TMR1_CFG2 0x40004f0eu
|
|
#define CYREG_TMR1_SR0 0x40004f0fu
|
|
#define CYREG_TMR1_PER0 0x40004f10u
|
|
#define CYREG_TMR1_PER1 0x40004f11u
|
|
#define CYREG_TMR1_CNT_CMP0 0x40004f12u
|
|
#define CYREG_TMR1_CNT_CMP1 0x40004f13u
|
|
#define CYREG_TMR1_CAP0 0x40004f14u
|
|
#define CYREG_TMR1_CAP1 0x40004f15u
|
|
#define CYREG_TMR1_RT0 0x40004f16u
|
|
#define CYREG_TMR1_RT1 0x40004f17u
|
|
#define CYDEV_TMR2_BASE 0x40004f18u
|
|
#define CYDEV_TMR2_SIZE 0x0000000cu
|
|
#define CYREG_TMR2_CFG0 0x40004f18u
|
|
#define CYREG_TMR2_CFG1 0x40004f19u
|
|
#define CYREG_TMR2_CFG2 0x40004f1au
|
|
#define CYREG_TMR2_SR0 0x40004f1bu
|
|
#define CYREG_TMR2_PER0 0x40004f1cu
|
|
#define CYREG_TMR2_PER1 0x40004f1du
|
|
#define CYREG_TMR2_CNT_CMP0 0x40004f1eu
|
|
#define CYREG_TMR2_CNT_CMP1 0x40004f1fu
|
|
#define CYREG_TMR2_CAP0 0x40004f20u
|
|
#define CYREG_TMR2_CAP1 0x40004f21u
|
|
#define CYREG_TMR2_RT0 0x40004f22u
|
|
#define CYREG_TMR2_RT1 0x40004f23u
|
|
#define CYDEV_TMR3_BASE 0x40004f24u
|
|
#define CYDEV_TMR3_SIZE 0x0000000cu
|
|
#define CYREG_TMR3_CFG0 0x40004f24u
|
|
#define CYREG_TMR3_CFG1 0x40004f25u
|
|
#define CYREG_TMR3_CFG2 0x40004f26u
|
|
#define CYREG_TMR3_SR0 0x40004f27u
|
|
#define CYREG_TMR3_PER0 0x40004f28u
|
|
#define CYREG_TMR3_PER1 0x40004f29u
|
|
#define CYREG_TMR3_CNT_CMP0 0x40004f2au
|
|
#define CYREG_TMR3_CNT_CMP1 0x40004f2bu
|
|
#define CYREG_TMR3_CAP0 0x40004f2cu
|
|
#define CYREG_TMR3_CAP1 0x40004f2du
|
|
#define CYREG_TMR3_RT0 0x40004f2eu
|
|
#define CYREG_TMR3_RT1 0x40004f2fu
|
|
#define CYDEV_IO_BASE 0x40005000u
|
|
#define CYDEV_IO_SIZE 0x00000200u
|
|
#define CYDEV_IO_PC_BASE 0x40005000u
|
|
#define CYDEV_IO_PC_SIZE 0x00000080u
|
|
#define CYDEV_IO_PC_PRT0_BASE 0x40005000u
|
|
#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u
|
|
#define CYREG_PRT0_PC0 0x40005000u
|
|
#define CYREG_PRT0_PC1 0x40005001u
|
|
#define CYREG_PRT0_PC2 0x40005002u
|
|
#define CYREG_PRT0_PC3 0x40005003u
|
|
#define CYREG_PRT0_PC4 0x40005004u
|
|
#define CYREG_PRT0_PC5 0x40005005u
|
|
#define CYREG_PRT0_PC6 0x40005006u
|
|
#define CYREG_PRT0_PC7 0x40005007u
|
|
#define CYDEV_IO_PC_PRT1_BASE 0x40005008u
|
|
#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u
|
|
#define CYREG_PRT1_PC0 0x40005008u
|
|
#define CYREG_PRT1_PC1 0x40005009u
|
|
#define CYREG_PRT1_PC2 0x4000500au
|
|
#define CYREG_PRT1_PC3 0x4000500bu
|
|
#define CYREG_PRT1_PC4 0x4000500cu
|
|
#define CYREG_PRT1_PC5 0x4000500du
|
|
#define CYREG_PRT1_PC6 0x4000500eu
|
|
#define CYREG_PRT1_PC7 0x4000500fu
|
|
#define CYDEV_IO_PC_PRT2_BASE 0x40005010u
|
|
#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u
|
|
#define CYREG_PRT2_PC0 0x40005010u
|
|
#define CYREG_PRT2_PC1 0x40005011u
|
|
#define CYREG_PRT2_PC2 0x40005012u
|
|
#define CYREG_PRT2_PC3 0x40005013u
|
|
#define CYREG_PRT2_PC4 0x40005014u
|
|
#define CYREG_PRT2_PC5 0x40005015u
|
|
#define CYREG_PRT2_PC6 0x40005016u
|
|
#define CYREG_PRT2_PC7 0x40005017u
|
|
#define CYDEV_IO_PC_PRT3_BASE 0x40005018u
|
|
#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u
|
|
#define CYREG_PRT3_PC0 0x40005018u
|
|
#define CYREG_PRT3_PC1 0x40005019u
|
|
#define CYREG_PRT3_PC2 0x4000501au
|
|
#define CYREG_PRT3_PC3 0x4000501bu
|
|
#define CYREG_PRT3_PC4 0x4000501cu
|
|
#define CYREG_PRT3_PC5 0x4000501du
|
|
#define CYREG_PRT3_PC6 0x4000501eu
|
|
#define CYREG_PRT3_PC7 0x4000501fu
|
|
#define CYDEV_IO_PC_PRT4_BASE 0x40005020u
|
|
#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u
|
|
#define CYREG_PRT4_PC0 0x40005020u
|
|
#define CYREG_PRT4_PC1 0x40005021u
|
|
#define CYREG_PRT4_PC2 0x40005022u
|
|
#define CYREG_PRT4_PC3 0x40005023u
|
|
#define CYREG_PRT4_PC4 0x40005024u
|
|
#define CYREG_PRT4_PC5 0x40005025u
|
|
#define CYREG_PRT4_PC6 0x40005026u
|
|
#define CYREG_PRT4_PC7 0x40005027u
|
|
#define CYDEV_IO_PC_PRT5_BASE 0x40005028u
|
|
#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u
|
|
#define CYREG_PRT5_PC0 0x40005028u
|
|
#define CYREG_PRT5_PC1 0x40005029u
|
|
#define CYREG_PRT5_PC2 0x4000502au
|
|
#define CYREG_PRT5_PC3 0x4000502bu
|
|
#define CYREG_PRT5_PC4 0x4000502cu
|
|
#define CYREG_PRT5_PC5 0x4000502du
|
|
#define CYREG_PRT5_PC6 0x4000502eu
|
|
#define CYREG_PRT5_PC7 0x4000502fu
|
|
#define CYDEV_IO_PC_PRT6_BASE 0x40005030u
|
|
#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u
|
|
#define CYREG_PRT6_PC0 0x40005030u
|
|
#define CYREG_PRT6_PC1 0x40005031u
|
|
#define CYREG_PRT6_PC2 0x40005032u
|
|
#define CYREG_PRT6_PC3 0x40005033u
|
|
#define CYREG_PRT6_PC4 0x40005034u
|
|
#define CYREG_PRT6_PC5 0x40005035u
|
|
#define CYREG_PRT6_PC6 0x40005036u
|
|
#define CYREG_PRT6_PC7 0x40005037u
|
|
#define CYDEV_IO_PC_PRT12_BASE 0x40005060u
|
|
#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u
|
|
#define CYREG_PRT12_PC0 0x40005060u
|
|
#define CYREG_PRT12_PC1 0x40005061u
|
|
#define CYREG_PRT12_PC2 0x40005062u
|
|
#define CYREG_PRT12_PC3 0x40005063u
|
|
#define CYREG_PRT12_PC4 0x40005064u
|
|
#define CYREG_PRT12_PC5 0x40005065u
|
|
#define CYREG_PRT12_PC6 0x40005066u
|
|
#define CYREG_PRT12_PC7 0x40005067u
|
|
#define CYDEV_IO_PC_PRT15_BASE 0x40005078u
|
|
#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u
|
|
#define CYREG_IO_PC_PRT15_PC0 0x40005078u
|
|
#define CYREG_IO_PC_PRT15_PC1 0x40005079u
|
|
#define CYREG_IO_PC_PRT15_PC2 0x4000507au
|
|
#define CYREG_IO_PC_PRT15_PC3 0x4000507bu
|
|
#define CYREG_IO_PC_PRT15_PC4 0x4000507cu
|
|
#define CYREG_IO_PC_PRT15_PC5 0x4000507du
|
|
#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu
|
|
#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u
|
|
#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu
|
|
#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu
|
|
#define CYDEV_IO_DR_BASE 0x40005080u
|
|
#define CYDEV_IO_DR_SIZE 0x00000010u
|
|
#define CYDEV_IO_DR_PRT0_BASE 0x40005080u
|
|
#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u
|
|
#define CYREG_PRT0_DR_ALIAS 0x40005080u
|
|
#define CYDEV_IO_DR_PRT1_BASE 0x40005081u
|
|
#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u
|
|
#define CYREG_PRT1_DR_ALIAS 0x40005081u
|
|
#define CYDEV_IO_DR_PRT2_BASE 0x40005082u
|
|
#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u
|
|
#define CYREG_PRT2_DR_ALIAS 0x40005082u
|
|
#define CYDEV_IO_DR_PRT3_BASE 0x40005083u
|
|
#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u
|
|
#define CYREG_PRT3_DR_ALIAS 0x40005083u
|
|
#define CYDEV_IO_DR_PRT4_BASE 0x40005084u
|
|
#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u
|
|
#define CYREG_PRT4_DR_ALIAS 0x40005084u
|
|
#define CYDEV_IO_DR_PRT5_BASE 0x40005085u
|
|
#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u
|
|
#define CYREG_PRT5_DR_ALIAS 0x40005085u
|
|
#define CYDEV_IO_DR_PRT6_BASE 0x40005086u
|
|
#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u
|
|
#define CYREG_PRT6_DR_ALIAS 0x40005086u
|
|
#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu
|
|
#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u
|
|
#define CYREG_PRT12_DR_ALIAS 0x4000508cu
|
|
#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu
|
|
#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u
|
|
#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu
|
|
#define CYDEV_IO_PS_BASE 0x40005090u
|
|
#define CYDEV_IO_PS_SIZE 0x00000010u
|
|
#define CYDEV_IO_PS_PRT0_BASE 0x40005090u
|
|
#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u
|
|
#define CYREG_PRT0_PS_ALIAS 0x40005090u
|
|
#define CYDEV_IO_PS_PRT1_BASE 0x40005091u
|
|
#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u
|
|
#define CYREG_PRT1_PS_ALIAS 0x40005091u
|
|
#define CYDEV_IO_PS_PRT2_BASE 0x40005092u
|
|
#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u
|
|
#define CYREG_PRT2_PS_ALIAS 0x40005092u
|
|
#define CYDEV_IO_PS_PRT3_BASE 0x40005093u
|
|
#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u
|
|
#define CYREG_PRT3_PS_ALIAS 0x40005093u
|
|
#define CYDEV_IO_PS_PRT4_BASE 0x40005094u
|
|
#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u
|
|
#define CYREG_PRT4_PS_ALIAS 0x40005094u
|
|
#define CYDEV_IO_PS_PRT5_BASE 0x40005095u
|
|
#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u
|
|
#define CYREG_PRT5_PS_ALIAS 0x40005095u
|
|
#define CYDEV_IO_PS_PRT6_BASE 0x40005096u
|
|
#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u
|
|
#define CYREG_PRT6_PS_ALIAS 0x40005096u
|
|
#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu
|
|
#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u
|
|
#define CYREG_PRT12_PS_ALIAS 0x4000509cu
|
|
#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu
|
|
#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u
|
|
#define CYREG_PRT15_PS15_ALIAS 0x4000509fu
|
|
#define CYDEV_IO_PRT_BASE 0x40005100u
|
|
#define CYDEV_IO_PRT_SIZE 0x00000100u
|
|
#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u
|
|
#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u
|
|
#define CYREG_PRT0_DR 0x40005100u
|
|
#define CYREG_PRT0_PS 0x40005101u
|
|
#define CYREG_PRT0_DM0 0x40005102u
|
|
#define CYREG_PRT0_DM1 0x40005103u
|
|
#define CYREG_PRT0_DM2 0x40005104u
|
|
#define CYREG_PRT0_SLW 0x40005105u
|
|
#define CYREG_PRT0_BYP 0x40005106u
|
|
#define CYREG_PRT0_BIE 0x40005107u
|
|
#define CYREG_PRT0_INP_DIS 0x40005108u
|
|
#define CYREG_PRT0_CTL 0x40005109u
|
|
#define CYREG_PRT0_PRT 0x4000510au
|
|
#define CYREG_PRT0_BIT_MASK 0x4000510bu
|
|
#define CYREG_PRT0_AMUX 0x4000510cu
|
|
#define CYREG_PRT0_AG 0x4000510du
|
|
#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu
|
|
#define CYREG_PRT0_LCD_EN 0x4000510fu
|
|
#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u
|
|
#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u
|
|
#define CYREG_PRT1_DR 0x40005110u
|
|
#define CYREG_PRT1_PS 0x40005111u
|
|
#define CYREG_PRT1_DM0 0x40005112u
|
|
#define CYREG_PRT1_DM1 0x40005113u
|
|
#define CYREG_PRT1_DM2 0x40005114u
|
|
#define CYREG_PRT1_SLW 0x40005115u
|
|
#define CYREG_PRT1_BYP 0x40005116u
|
|
#define CYREG_PRT1_BIE 0x40005117u
|
|
#define CYREG_PRT1_INP_DIS 0x40005118u
|
|
#define CYREG_PRT1_CTL 0x40005119u
|
|
#define CYREG_PRT1_PRT 0x4000511au
|
|
#define CYREG_PRT1_BIT_MASK 0x4000511bu
|
|
#define CYREG_PRT1_AMUX 0x4000511cu
|
|
#define CYREG_PRT1_AG 0x4000511du
|
|
#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu
|
|
#define CYREG_PRT1_LCD_EN 0x4000511fu
|
|
#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u
|
|
#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u
|
|
#define CYREG_PRT2_DR 0x40005120u
|
|
#define CYREG_PRT2_PS 0x40005121u
|
|
#define CYREG_PRT2_DM0 0x40005122u
|
|
#define CYREG_PRT2_DM1 0x40005123u
|
|
#define CYREG_PRT2_DM2 0x40005124u
|
|
#define CYREG_PRT2_SLW 0x40005125u
|
|
#define CYREG_PRT2_BYP 0x40005126u
|
|
#define CYREG_PRT2_BIE 0x40005127u
|
|
#define CYREG_PRT2_INP_DIS 0x40005128u
|
|
#define CYREG_PRT2_CTL 0x40005129u
|
|
#define CYREG_PRT2_PRT 0x4000512au
|
|
#define CYREG_PRT2_BIT_MASK 0x4000512bu
|
|
#define CYREG_PRT2_AMUX 0x4000512cu
|
|
#define CYREG_PRT2_AG 0x4000512du
|
|
#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu
|
|
#define CYREG_PRT2_LCD_EN 0x4000512fu
|
|
#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u
|
|
#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u
|
|
#define CYREG_PRT3_DR 0x40005130u
|
|
#define CYREG_PRT3_PS 0x40005131u
|
|
#define CYREG_PRT3_DM0 0x40005132u
|
|
#define CYREG_PRT3_DM1 0x40005133u
|
|
#define CYREG_PRT3_DM2 0x40005134u
|
|
#define CYREG_PRT3_SLW 0x40005135u
|
|
#define CYREG_PRT3_BYP 0x40005136u
|
|
#define CYREG_PRT3_BIE 0x40005137u
|
|
#define CYREG_PRT3_INP_DIS 0x40005138u
|
|
#define CYREG_PRT3_CTL 0x40005139u
|
|
#define CYREG_PRT3_PRT 0x4000513au
|
|
#define CYREG_PRT3_BIT_MASK 0x4000513bu
|
|
#define CYREG_PRT3_AMUX 0x4000513cu
|
|
#define CYREG_PRT3_AG 0x4000513du
|
|
#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu
|
|
#define CYREG_PRT3_LCD_EN 0x4000513fu
|
|
#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u
|
|
#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u
|
|
#define CYREG_PRT4_DR 0x40005140u
|
|
#define CYREG_PRT4_PS 0x40005141u
|
|
#define CYREG_PRT4_DM0 0x40005142u
|
|
#define CYREG_PRT4_DM1 0x40005143u
|
|
#define CYREG_PRT4_DM2 0x40005144u
|
|
#define CYREG_PRT4_SLW 0x40005145u
|
|
#define CYREG_PRT4_BYP 0x40005146u
|
|
#define CYREG_PRT4_BIE 0x40005147u
|
|
#define CYREG_PRT4_INP_DIS 0x40005148u
|
|
#define CYREG_PRT4_CTL 0x40005149u
|
|
#define CYREG_PRT4_PRT 0x4000514au
|
|
#define CYREG_PRT4_BIT_MASK 0x4000514bu
|
|
#define CYREG_PRT4_AMUX 0x4000514cu
|
|
#define CYREG_PRT4_AG 0x4000514du
|
|
#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu
|
|
#define CYREG_PRT4_LCD_EN 0x4000514fu
|
|
#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u
|
|
#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u
|
|
#define CYREG_PRT5_DR 0x40005150u
|
|
#define CYREG_PRT5_PS 0x40005151u
|
|
#define CYREG_PRT5_DM0 0x40005152u
|
|
#define CYREG_PRT5_DM1 0x40005153u
|
|
#define CYREG_PRT5_DM2 0x40005154u
|
|
#define CYREG_PRT5_SLW 0x40005155u
|
|
#define CYREG_PRT5_BYP 0x40005156u
|
|
#define CYREG_PRT5_BIE 0x40005157u
|
|
#define CYREG_PRT5_INP_DIS 0x40005158u
|
|
#define CYREG_PRT5_CTL 0x40005159u
|
|
#define CYREG_PRT5_PRT 0x4000515au
|
|
#define CYREG_PRT5_BIT_MASK 0x4000515bu
|
|
#define CYREG_PRT5_AMUX 0x4000515cu
|
|
#define CYREG_PRT5_AG 0x4000515du
|
|
#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu
|
|
#define CYREG_PRT5_LCD_EN 0x4000515fu
|
|
#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u
|
|
#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u
|
|
#define CYREG_PRT6_DR 0x40005160u
|
|
#define CYREG_PRT6_PS 0x40005161u
|
|
#define CYREG_PRT6_DM0 0x40005162u
|
|
#define CYREG_PRT6_DM1 0x40005163u
|
|
#define CYREG_PRT6_DM2 0x40005164u
|
|
#define CYREG_PRT6_SLW 0x40005165u
|
|
#define CYREG_PRT6_BYP 0x40005166u
|
|
#define CYREG_PRT6_BIE 0x40005167u
|
|
#define CYREG_PRT6_INP_DIS 0x40005168u
|
|
#define CYREG_PRT6_CTL 0x40005169u
|
|
#define CYREG_PRT6_PRT 0x4000516au
|
|
#define CYREG_PRT6_BIT_MASK 0x4000516bu
|
|
#define CYREG_PRT6_AMUX 0x4000516cu
|
|
#define CYREG_PRT6_AG 0x4000516du
|
|
#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu
|
|
#define CYREG_PRT6_LCD_EN 0x4000516fu
|
|
#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u
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#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u
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#define CYREG_PRT12_DR 0x400051c0u
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#define CYREG_PRT12_PS 0x400051c1u
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#define CYREG_PRT12_DM0 0x400051c2u
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#define CYREG_PRT12_DM1 0x400051c3u
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#define CYREG_PRT12_DM2 0x400051c4u
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#define CYREG_PRT12_SLW 0x400051c5u
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#define CYREG_PRT12_BYP 0x400051c6u
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#define CYREG_PRT12_BIE 0x400051c7u
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#define CYREG_PRT12_INP_DIS 0x400051c8u
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#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u
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#define CYREG_PRT12_PRT 0x400051cau
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#define CYREG_PRT12_BIT_MASK 0x400051cbu
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#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu
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#define CYREG_PRT12_AG 0x400051cdu
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#define CYREG_PRT12_SIO_CFG 0x400051ceu
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#define CYREG_PRT12_SIO_DIFF 0x400051cfu
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#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u
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#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u
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#define CYREG_PRT15_DR 0x400051f0u
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#define CYREG_PRT15_PS 0x400051f1u
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#define CYREG_PRT15_DM0 0x400051f2u
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#define CYREG_PRT15_DM1 0x400051f3u
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#define CYREG_PRT15_DM2 0x400051f4u
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#define CYREG_PRT15_SLW 0x400051f5u
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#define CYREG_PRT15_BYP 0x400051f6u
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#define CYREG_PRT15_BIE 0x400051f7u
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#define CYREG_PRT15_INP_DIS 0x400051f8u
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#define CYREG_PRT15_CTL 0x400051f9u
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#define CYREG_PRT15_PRT 0x400051fau
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#define CYREG_PRT15_BIT_MASK 0x400051fbu
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#define CYREG_PRT15_AMUX 0x400051fcu
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#define CYREG_PRT15_AG 0x400051fdu
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#define CYREG_PRT15_LCD_COM_SEG 0x400051feu
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#define CYREG_PRT15_LCD_EN 0x400051ffu
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#define CYDEV_PRTDSI_BASE 0x40005200u
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#define CYDEV_PRTDSI_SIZE 0x0000007fu
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#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u
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#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u
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#define CYREG_PRT0_OUT_SEL0 0x40005200u
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#define CYREG_PRT0_OUT_SEL1 0x40005201u
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#define CYREG_PRT0_OE_SEL0 0x40005202u
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#define CYREG_PRT0_OE_SEL1 0x40005203u
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#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u
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#define CYREG_PRT0_SYNC_OUT 0x40005205u
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#define CYREG_PRT0_CAPS_SEL 0x40005206u
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#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u
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#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u
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#define CYREG_PRT1_OUT_SEL0 0x40005208u
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#define CYREG_PRT1_OUT_SEL1 0x40005209u
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#define CYREG_PRT1_OE_SEL0 0x4000520au
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#define CYREG_PRT1_OE_SEL1 0x4000520bu
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#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu
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#define CYREG_PRT1_SYNC_OUT 0x4000520du
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#define CYREG_PRT1_CAPS_SEL 0x4000520eu
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#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u
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#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u
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#define CYREG_PRT2_OUT_SEL0 0x40005210u
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#define CYREG_PRT2_OUT_SEL1 0x40005211u
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#define CYREG_PRT2_OE_SEL0 0x40005212u
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#define CYREG_PRT2_OE_SEL1 0x40005213u
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#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u
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#define CYREG_PRT2_SYNC_OUT 0x40005215u
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#define CYREG_PRT2_CAPS_SEL 0x40005216u
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#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u
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#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u
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#define CYREG_PRT3_OUT_SEL0 0x40005218u
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#define CYREG_PRT3_OUT_SEL1 0x40005219u
|
|
#define CYREG_PRT3_OE_SEL0 0x4000521au
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#define CYREG_PRT3_OE_SEL1 0x4000521bu
|
|
#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu
|
|
#define CYREG_PRT3_SYNC_OUT 0x4000521du
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|
#define CYREG_PRT3_CAPS_SEL 0x4000521eu
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#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u
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#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u
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|
#define CYREG_PRT4_OUT_SEL0 0x40005220u
|
|
#define CYREG_PRT4_OUT_SEL1 0x40005221u
|
|
#define CYREG_PRT4_OE_SEL0 0x40005222u
|
|
#define CYREG_PRT4_OE_SEL1 0x40005223u
|
|
#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u
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#define CYREG_PRT4_SYNC_OUT 0x40005225u
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#define CYREG_PRT4_CAPS_SEL 0x40005226u
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|
#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u
|
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#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u
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|
#define CYREG_PRT5_OUT_SEL0 0x40005228u
|
|
#define CYREG_PRT5_OUT_SEL1 0x40005229u
|
|
#define CYREG_PRT5_OE_SEL0 0x4000522au
|
|
#define CYREG_PRT5_OE_SEL1 0x4000522bu
|
|
#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu
|
|
#define CYREG_PRT5_SYNC_OUT 0x4000522du
|
|
#define CYREG_PRT5_CAPS_SEL 0x4000522eu
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|
#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u
|
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#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u
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|
#define CYREG_PRT6_OUT_SEL0 0x40005230u
|
|
#define CYREG_PRT6_OUT_SEL1 0x40005231u
|
|
#define CYREG_PRT6_OE_SEL0 0x40005232u
|
|
#define CYREG_PRT6_OE_SEL1 0x40005233u
|
|
#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u
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|
#define CYREG_PRT6_SYNC_OUT 0x40005235u
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|
#define CYREG_PRT6_CAPS_SEL 0x40005236u
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|
#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u
|
|
#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u
|
|
#define CYREG_PRT12_OUT_SEL0 0x40005260u
|
|
#define CYREG_PRT12_OUT_SEL1 0x40005261u
|
|
#define CYREG_PRT12_OE_SEL0 0x40005262u
|
|
#define CYREG_PRT12_OE_SEL1 0x40005263u
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|
#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u
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|
#define CYREG_PRT12_SYNC_OUT 0x40005265u
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|
#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u
|
|
#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u
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|
#define CYREG_PRT15_OUT_SEL0 0x40005278u
|
|
#define CYREG_PRT15_OUT_SEL1 0x40005279u
|
|
#define CYREG_PRT15_OE_SEL0 0x4000527au
|
|
#define CYREG_PRT15_OE_SEL1 0x4000527bu
|
|
#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu
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|
#define CYREG_PRT15_SYNC_OUT 0x4000527du
|
|
#define CYREG_PRT15_CAPS_SEL 0x4000527eu
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|
#define CYDEV_EMIF_BASE 0x40005400u
|
|
#define CYDEV_EMIF_SIZE 0x00000007u
|
|
#define CYREG_EMIF_NO_UDB 0x40005400u
|
|
#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u
|
|
#define CYREG_EMIF_MEM_DWN 0x40005402u
|
|
#define CYREG_EMIF_MEMCLK_DIV 0x40005403u
|
|
#define CYREG_EMIF_CLOCK_EN 0x40005404u
|
|
#define CYREG_EMIF_EM_TYPE 0x40005405u
|
|
#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u
|
|
#define CYDEV_ANAIF_BASE 0x40005800u
|
|
#define CYDEV_ANAIF_SIZE 0x000003a9u
|
|
#define CYDEV_ANAIF_CFG_BASE 0x40005800u
|
|
#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu
|
|
#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u
|
|
#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u
|
|
#define CYREG_SC0_CR0 0x40005800u
|
|
#define CYREG_SC0_CR1 0x40005801u
|
|
#define CYREG_SC0_CR2 0x40005802u
|
|
#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u
|
|
#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u
|
|
#define CYREG_SC1_CR0 0x40005804u
|
|
#define CYREG_SC1_CR1 0x40005805u
|
|
#define CYREG_SC1_CR2 0x40005806u
|
|
#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u
|
|
#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u
|
|
#define CYREG_SC2_CR0 0x40005808u
|
|
#define CYREG_SC2_CR1 0x40005809u
|
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#define CYREG_SC2_CR2 0x4000580au
|
|
#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu
|
|
#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u
|
|
#define CYREG_SC3_CR0 0x4000580cu
|
|
#define CYREG_SC3_CR1 0x4000580du
|
|
#define CYREG_SC3_CR2 0x4000580eu
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|
#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u
|
|
#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u
|
|
#define CYREG_DAC0_CR0 0x40005820u
|
|
#define CYREG_DAC0_CR1 0x40005821u
|
|
#define CYREG_DAC0_TST 0x40005822u
|
|
#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u
|
|
#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u
|
|
#define CYREG_DAC1_CR0 0x40005824u
|
|
#define CYREG_DAC1_CR1 0x40005825u
|
|
#define CYREG_DAC1_TST 0x40005826u
|
|
#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u
|
|
#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u
|
|
#define CYREG_DAC2_CR0 0x40005828u
|
|
#define CYREG_DAC2_CR1 0x40005829u
|
|
#define CYREG_DAC2_TST 0x4000582au
|
|
#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu
|
|
#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u
|
|
#define CYREG_DAC3_CR0 0x4000582cu
|
|
#define CYREG_DAC3_CR1 0x4000582du
|
|
#define CYREG_DAC3_TST 0x4000582eu
|
|
#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u
|
|
#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u
|
|
#define CYREG_CMP0_CR 0x40005840u
|
|
#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u
|
|
#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u
|
|
#define CYREG_CMP1_CR 0x40005841u
|
|
#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u
|
|
#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u
|
|
#define CYREG_CMP2_CR 0x40005842u
|
|
#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u
|
|
#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u
|
|
#define CYREG_CMP3_CR 0x40005843u
|
|
#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u
|
|
#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u
|
|
#define CYREG_LUT0_CR 0x40005848u
|
|
#define CYREG_LUT0_MX 0x40005849u
|
|
#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au
|
|
#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u
|
|
#define CYREG_LUT1_CR 0x4000584au
|
|
#define CYREG_LUT1_MX 0x4000584bu
|
|
#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu
|
|
#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u
|
|
#define CYREG_LUT2_CR 0x4000584cu
|
|
#define CYREG_LUT2_MX 0x4000584du
|
|
#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu
|
|
#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u
|
|
#define CYREG_LUT3_CR 0x4000584eu
|
|
#define CYREG_LUT3_MX 0x4000584fu
|
|
#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u
|
|
#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u
|
|
#define CYREG_OPAMP0_CR 0x40005858u
|
|
#define CYREG_OPAMP0_RSVD 0x40005859u
|
|
#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au
|
|
#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u
|
|
#define CYREG_OPAMP1_CR 0x4000585au
|
|
#define CYREG_OPAMP1_RSVD 0x4000585bu
|
|
#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu
|
|
#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u
|
|
#define CYREG_OPAMP2_CR 0x4000585cu
|
|
#define CYREG_OPAMP2_RSVD 0x4000585du
|
|
#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu
|
|
#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u
|
|
#define CYREG_OPAMP3_CR 0x4000585eu
|
|
#define CYREG_OPAMP3_RSVD 0x4000585fu
|
|
#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u
|
|
#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u
|
|
#define CYREG_LCDDAC_CR0 0x40005868u
|
|
#define CYREG_LCDDAC_CR1 0x40005869u
|
|
#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au
|
|
#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u
|
|
#define CYREG_LCDDRV_CR 0x4000586au
|
|
#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu
|
|
#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u
|
|
#define CYREG_LCDTMR_CFG 0x4000586bu
|
|
#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu
|
|
#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u
|
|
#define CYREG_BG_CR0 0x4000586cu
|
|
#define CYREG_BG_RSVD 0x4000586du
|
|
#define CYREG_BG_DFT0 0x4000586eu
|
|
#define CYREG_BG_DFT1 0x4000586fu
|
|
#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u
|
|
#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u
|
|
#define CYREG_CAPSL_CFG0 0x40005870u
|
|
#define CYREG_CAPSL_CFG1 0x40005871u
|
|
#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u
|
|
#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u
|
|
#define CYREG_CAPSR_CFG0 0x40005872u
|
|
#define CYREG_CAPSR_CFG1 0x40005873u
|
|
#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u
|
|
#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u
|
|
#define CYREG_PUMP_CR0 0x40005876u
|
|
#define CYREG_PUMP_CR1 0x40005877u
|
|
#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u
|
|
#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u
|
|
#define CYREG_LPF0_CR0 0x40005878u
|
|
#define CYREG_LPF0_RSVD 0x40005879u
|
|
#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au
|
|
#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u
|
|
#define CYREG_LPF1_CR0 0x4000587au
|
|
#define CYREG_LPF1_RSVD 0x4000587bu
|
|
#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu
|
|
#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u
|
|
#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu
|
|
#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u
|
|
#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u
|
|
#define CYREG_DSM0_CR0 0x40005880u
|
|
#define CYREG_DSM0_CR1 0x40005881u
|
|
#define CYREG_DSM0_CR2 0x40005882u
|
|
#define CYREG_DSM0_CR3 0x40005883u
|
|
#define CYREG_DSM0_CR4 0x40005884u
|
|
#define CYREG_DSM0_CR5 0x40005885u
|
|
#define CYREG_DSM0_CR6 0x40005886u
|
|
#define CYREG_DSM0_CR7 0x40005887u
|
|
#define CYREG_DSM0_CR8 0x40005888u
|
|
#define CYREG_DSM0_CR9 0x40005889u
|
|
#define CYREG_DSM0_CR10 0x4000588au
|
|
#define CYREG_DSM0_CR11 0x4000588bu
|
|
#define CYREG_DSM0_CR12 0x4000588cu
|
|
#define CYREG_DSM0_CR13 0x4000588du
|
|
#define CYREG_DSM0_CR14 0x4000588eu
|
|
#define CYREG_DSM0_CR15 0x4000588fu
|
|
#define CYREG_DSM0_CR16 0x40005890u
|
|
#define CYREG_DSM0_CR17 0x40005891u
|
|
#define CYREG_DSM0_REF0 0x40005892u
|
|
#define CYREG_DSM0_REF1 0x40005893u
|
|
#define CYREG_DSM0_REF2 0x40005894u
|
|
#define CYREG_DSM0_REF3 0x40005895u
|
|
#define CYREG_DSM0_DEM0 0x40005896u
|
|
#define CYREG_DSM0_DEM1 0x40005897u
|
|
#define CYREG_DSM0_TST0 0x40005898u
|
|
#define CYREG_DSM0_TST1 0x40005899u
|
|
#define CYREG_DSM0_BUF0 0x4000589au
|
|
#define CYREG_DSM0_BUF1 0x4000589bu
|
|
#define CYREG_DSM0_BUF2 0x4000589cu
|
|
#define CYREG_DSM0_BUF3 0x4000589du
|
|
#define CYREG_DSM0_MISC 0x4000589eu
|
|
#define CYREG_DSM0_RSVD1 0x4000589fu
|
|
#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u
|
|
#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u
|
|
#define CYREG_SAR0_CSR0 0x40005900u
|
|
#define CYREG_SAR0_CSR1 0x40005901u
|
|
#define CYREG_SAR0_CSR2 0x40005902u
|
|
#define CYREG_SAR0_CSR3 0x40005903u
|
|
#define CYREG_SAR0_CSR4 0x40005904u
|
|
#define CYREG_SAR0_CSR5 0x40005905u
|
|
#define CYREG_SAR0_CSR6 0x40005906u
|
|
#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u
|
|
#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u
|
|
#define CYREG_SAR1_CSR0 0x40005908u
|
|
#define CYREG_SAR1_CSR1 0x40005909u
|
|
#define CYREG_SAR1_CSR2 0x4000590au
|
|
#define CYREG_SAR1_CSR3 0x4000590bu
|
|
#define CYREG_SAR1_CSR4 0x4000590cu
|
|
#define CYREG_SAR1_CSR5 0x4000590du
|
|
#define CYREG_SAR1_CSR6 0x4000590eu
|
|
#define CYDEV_ANAIF_RT_BASE 0x40005a00u
|
|
#define CYDEV_ANAIF_RT_SIZE 0x00000162u
|
|
#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u
|
|
#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du
|
|
#define CYREG_SC0_SW0 0x40005a00u
|
|
#define CYREG_SC0_SW2 0x40005a02u
|
|
#define CYREG_SC0_SW3 0x40005a03u
|
|
#define CYREG_SC0_SW4 0x40005a04u
|
|
#define CYREG_SC0_SW6 0x40005a06u
|
|
#define CYREG_SC0_SW7 0x40005a07u
|
|
#define CYREG_SC0_SW8 0x40005a08u
|
|
#define CYREG_SC0_SW10 0x40005a0au
|
|
#define CYREG_SC0_CLK 0x40005a0bu
|
|
#define CYREG_SC0_BST 0x40005a0cu
|
|
#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u
|
|
#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du
|
|
#define CYREG_SC1_SW0 0x40005a10u
|
|
#define CYREG_SC1_SW2 0x40005a12u
|
|
#define CYREG_SC1_SW3 0x40005a13u
|
|
#define CYREG_SC1_SW4 0x40005a14u
|
|
#define CYREG_SC1_SW6 0x40005a16u
|
|
#define CYREG_SC1_SW7 0x40005a17u
|
|
#define CYREG_SC1_SW8 0x40005a18u
|
|
#define CYREG_SC1_SW10 0x40005a1au
|
|
#define CYREG_SC1_CLK 0x40005a1bu
|
|
#define CYREG_SC1_BST 0x40005a1cu
|
|
#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u
|
|
#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du
|
|
#define CYREG_SC2_SW0 0x40005a20u
|
|
#define CYREG_SC2_SW2 0x40005a22u
|
|
#define CYREG_SC2_SW3 0x40005a23u
|
|
#define CYREG_SC2_SW4 0x40005a24u
|
|
#define CYREG_SC2_SW6 0x40005a26u
|
|
#define CYREG_SC2_SW7 0x40005a27u
|
|
#define CYREG_SC2_SW8 0x40005a28u
|
|
#define CYREG_SC2_SW10 0x40005a2au
|
|
#define CYREG_SC2_CLK 0x40005a2bu
|
|
#define CYREG_SC2_BST 0x40005a2cu
|
|
#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u
|
|
#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du
|
|
#define CYREG_SC3_SW0 0x40005a30u
|
|
#define CYREG_SC3_SW2 0x40005a32u
|
|
#define CYREG_SC3_SW3 0x40005a33u
|
|
#define CYREG_SC3_SW4 0x40005a34u
|
|
#define CYREG_SC3_SW6 0x40005a36u
|
|
#define CYREG_SC3_SW7 0x40005a37u
|
|
#define CYREG_SC3_SW8 0x40005a38u
|
|
#define CYREG_SC3_SW10 0x40005a3au
|
|
#define CYREG_SC3_CLK 0x40005a3bu
|
|
#define CYREG_SC3_BST 0x40005a3cu
|
|
#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u
|
|
#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u
|
|
#define CYREG_DAC0_SW0 0x40005a80u
|
|
#define CYREG_DAC0_SW2 0x40005a82u
|
|
#define CYREG_DAC0_SW3 0x40005a83u
|
|
#define CYREG_DAC0_SW4 0x40005a84u
|
|
#define CYREG_DAC0_STROBE 0x40005a87u
|
|
#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u
|
|
#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u
|
|
#define CYREG_DAC1_SW0 0x40005a88u
|
|
#define CYREG_DAC1_SW2 0x40005a8au
|
|
#define CYREG_DAC1_SW3 0x40005a8bu
|
|
#define CYREG_DAC1_SW4 0x40005a8cu
|
|
#define CYREG_DAC1_STROBE 0x40005a8fu
|
|
#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u
|
|
#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u
|
|
#define CYREG_DAC2_SW0 0x40005a90u
|
|
#define CYREG_DAC2_SW2 0x40005a92u
|
|
#define CYREG_DAC2_SW3 0x40005a93u
|
|
#define CYREG_DAC2_SW4 0x40005a94u
|
|
#define CYREG_DAC2_STROBE 0x40005a97u
|
|
#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u
|
|
#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u
|
|
#define CYREG_DAC3_SW0 0x40005a98u
|
|
#define CYREG_DAC3_SW2 0x40005a9au
|
|
#define CYREG_DAC3_SW3 0x40005a9bu
|
|
#define CYREG_DAC3_SW4 0x40005a9cu
|
|
#define CYREG_DAC3_STROBE 0x40005a9fu
|
|
#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u
|
|
#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u
|
|
#define CYREG_CMP0_SW0 0x40005ac0u
|
|
#define CYREG_CMP0_SW2 0x40005ac2u
|
|
#define CYREG_CMP0_SW3 0x40005ac3u
|
|
#define CYREG_CMP0_SW4 0x40005ac4u
|
|
#define CYREG_CMP0_SW6 0x40005ac6u
|
|
#define CYREG_CMP0_CLK 0x40005ac7u
|
|
#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u
|
|
#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u
|
|
#define CYREG_CMP1_SW0 0x40005ac8u
|
|
#define CYREG_CMP1_SW2 0x40005acau
|
|
#define CYREG_CMP1_SW3 0x40005acbu
|
|
#define CYREG_CMP1_SW4 0x40005accu
|
|
#define CYREG_CMP1_SW6 0x40005aceu
|
|
#define CYREG_CMP1_CLK 0x40005acfu
|
|
#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u
|
|
#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u
|
|
#define CYREG_CMP2_SW0 0x40005ad0u
|
|
#define CYREG_CMP2_SW2 0x40005ad2u
|
|
#define CYREG_CMP2_SW3 0x40005ad3u
|
|
#define CYREG_CMP2_SW4 0x40005ad4u
|
|
#define CYREG_CMP2_SW6 0x40005ad6u
|
|
#define CYREG_CMP2_CLK 0x40005ad7u
|
|
#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u
|
|
#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u
|
|
#define CYREG_CMP3_SW0 0x40005ad8u
|
|
#define CYREG_CMP3_SW2 0x40005adau
|
|
#define CYREG_CMP3_SW3 0x40005adbu
|
|
#define CYREG_CMP3_SW4 0x40005adcu
|
|
#define CYREG_CMP3_SW6 0x40005adeu
|
|
#define CYREG_CMP3_CLK 0x40005adfu
|
|
#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u
|
|
#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u
|
|
#define CYREG_DSM0_SW0 0x40005b00u
|
|
#define CYREG_DSM0_SW2 0x40005b02u
|
|
#define CYREG_DSM0_SW3 0x40005b03u
|
|
#define CYREG_DSM0_SW4 0x40005b04u
|
|
#define CYREG_DSM0_SW6 0x40005b06u
|
|
#define CYREG_DSM0_CLK 0x40005b07u
|
|
#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u
|
|
#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u
|
|
#define CYREG_SAR0_SW0 0x40005b20u
|
|
#define CYREG_SAR0_SW2 0x40005b22u
|
|
#define CYREG_SAR0_SW3 0x40005b23u
|
|
#define CYREG_SAR0_SW4 0x40005b24u
|
|
#define CYREG_SAR0_SW6 0x40005b26u
|
|
#define CYREG_SAR0_CLK 0x40005b27u
|
|
#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u
|
|
#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u
|
|
#define CYREG_SAR1_SW0 0x40005b28u
|
|
#define CYREG_SAR1_SW2 0x40005b2au
|
|
#define CYREG_SAR1_SW3 0x40005b2bu
|
|
#define CYREG_SAR1_SW4 0x40005b2cu
|
|
#define CYREG_SAR1_SW6 0x40005b2eu
|
|
#define CYREG_SAR1_CLK 0x40005b2fu
|
|
#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u
|
|
#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u
|
|
#define CYREG_OPAMP0_MX 0x40005b40u
|
|
#define CYREG_OPAMP0_SW 0x40005b41u
|
|
#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u
|
|
#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u
|
|
#define CYREG_OPAMP1_MX 0x40005b42u
|
|
#define CYREG_OPAMP1_SW 0x40005b43u
|
|
#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u
|
|
#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u
|
|
#define CYREG_OPAMP2_MX 0x40005b44u
|
|
#define CYREG_OPAMP2_SW 0x40005b45u
|
|
#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u
|
|
#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u
|
|
#define CYREG_OPAMP3_MX 0x40005b46u
|
|
#define CYREG_OPAMP3_SW 0x40005b47u
|
|
#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u
|
|
#define CYREG_LCDDAC_SW0 0x40005b50u
|
|
#define CYREG_LCDDAC_SW1 0x40005b51u
|
|
#define CYREG_LCDDAC_SW2 0x40005b52u
|
|
#define CYREG_LCDDAC_SW3 0x40005b53u
|
|
#define CYREG_LCDDAC_SW4 0x40005b54u
|
|
#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u
|
|
#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u
|
|
#define CYREG_SC_MISC 0x40005b56u
|
|
#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u
|
|
#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u
|
|
#define CYREG_BUS_SW0 0x40005b58u
|
|
#define CYREG_BUS_SW2 0x40005b5au
|
|
#define CYREG_BUS_SW3 0x40005b5bu
|
|
#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu
|
|
#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u
|
|
#define CYREG_DFT_CR0 0x40005b5cu
|
|
#define CYREG_DFT_CR1 0x40005b5du
|
|
#define CYREG_DFT_CR2 0x40005b5eu
|
|
#define CYREG_DFT_CR3 0x40005b5fu
|
|
#define CYREG_DFT_CR4 0x40005b60u
|
|
#define CYREG_DFT_CR5 0x40005b61u
|
|
#define CYDEV_ANAIF_WRK_BASE 0x40005b80u
|
|
#define CYDEV_ANAIF_WRK_SIZE 0x00000029u
|
|
#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u
|
|
#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u
|
|
#define CYREG_DAC0_D 0x40005b80u
|
|
#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u
|
|
#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u
|
|
#define CYREG_DAC1_D 0x40005b81u
|
|
#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u
|
|
#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u
|
|
#define CYREG_DAC2_D 0x40005b82u
|
|
#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u
|
|
#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u
|
|
#define CYREG_DAC3_D 0x40005b83u
|
|
#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u
|
|
#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u
|
|
#define CYREG_DSM0_OUT0 0x40005b88u
|
|
#define CYREG_DSM0_OUT1 0x40005b89u
|
|
#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u
|
|
#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u
|
|
#define CYREG_LUT_SR 0x40005b90u
|
|
#define CYREG_LUT_WRK1 0x40005b91u
|
|
#define CYREG_LUT_MSK 0x40005b92u
|
|
#define CYREG_LUT_CLK 0x40005b93u
|
|
#define CYREG_LUT_CPTR 0x40005b94u
|
|
#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u
|
|
#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u
|
|
#define CYREG_CMP_WRK 0x40005b96u
|
|
#define CYREG_CMP_TST 0x40005b97u
|
|
#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u
|
|
#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u
|
|
#define CYREG_SC_SR 0x40005b98u
|
|
#define CYREG_SC_WRK1 0x40005b99u
|
|
#define CYREG_SC_MSK 0x40005b9au
|
|
#define CYREG_SC_CMPINV 0x40005b9bu
|
|
#define CYREG_SC_CPTR 0x40005b9cu
|
|
#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u
|
|
#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u
|
|
#define CYREG_SAR0_WRK0 0x40005ba0u
|
|
#define CYREG_SAR0_WRK1 0x40005ba1u
|
|
#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u
|
|
#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u
|
|
#define CYREG_SAR1_WRK0 0x40005ba2u
|
|
#define CYREG_SAR1_WRK1 0x40005ba3u
|
|
#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u
|
|
#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u
|
|
#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u
|
|
#define CYDEV_USB_BASE 0x40006000u
|
|
#define CYDEV_USB_SIZE 0x00000300u
|
|
#define CYREG_USB_EP0_DR0 0x40006000u
|
|
#define CYREG_USB_EP0_DR1 0x40006001u
|
|
#define CYREG_USB_EP0_DR2 0x40006002u
|
|
#define CYREG_USB_EP0_DR3 0x40006003u
|
|
#define CYREG_USB_EP0_DR4 0x40006004u
|
|
#define CYREG_USB_EP0_DR5 0x40006005u
|
|
#define CYREG_USB_EP0_DR6 0x40006006u
|
|
#define CYREG_USB_EP0_DR7 0x40006007u
|
|
#define CYREG_USB_CR0 0x40006008u
|
|
#define CYREG_USB_CR1 0x40006009u
|
|
#define CYREG_USB_SIE_EP_INT_EN 0x4000600au
|
|
#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu
|
|
#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu
|
|
#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu
|
|
#define CYREG_USB_SIE_EP1_CNT1 0x4000600du
|
|
#define CYREG_USB_SIE_EP1_CR0 0x4000600eu
|
|
#define CYREG_USB_USBIO_CR0 0x40006010u
|
|
#define CYREG_USB_USBIO_CR1 0x40006012u
|
|
#define CYREG_USB_DYN_RECONFIG 0x40006014u
|
|
#define CYREG_USB_SOF0 0x40006018u
|
|
#define CYREG_USB_SOF1 0x40006019u
|
|
#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu
|
|
#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu
|
|
#define CYREG_USB_SIE_EP2_CNT1 0x4000601du
|
|
#define CYREG_USB_SIE_EP2_CR0 0x4000601eu
|
|
#define CYREG_USB_EP0_CR 0x40006028u
|
|
#define CYREG_USB_EP0_CNT 0x40006029u
|
|
#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu
|
|
#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu
|
|
#define CYREG_USB_SIE_EP3_CNT1 0x4000602du
|
|
#define CYREG_USB_SIE_EP3_CR0 0x4000602eu
|
|
#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu
|
|
#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu
|
|
#define CYREG_USB_SIE_EP4_CNT1 0x4000603du
|
|
#define CYREG_USB_SIE_EP4_CR0 0x4000603eu
|
|
#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu
|
|
#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu
|
|
#define CYREG_USB_SIE_EP5_CNT1 0x4000604du
|
|
#define CYREG_USB_SIE_EP5_CR0 0x4000604eu
|
|
#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu
|
|
#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu
|
|
#define CYREG_USB_SIE_EP6_CNT1 0x4000605du
|
|
#define CYREG_USB_SIE_EP6_CR0 0x4000605eu
|
|
#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu
|
|
#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu
|
|
#define CYREG_USB_SIE_EP7_CNT1 0x4000606du
|
|
#define CYREG_USB_SIE_EP7_CR0 0x4000606eu
|
|
#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu
|
|
#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u
|
|
#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu
|
|
#define CYREG_USB_SIE_EP8_CNT1 0x4000607du
|
|
#define CYREG_USB_SIE_EP8_CR0 0x4000607eu
|
|
#define CYDEV_USB_ARB_EP1_BASE 0x40006080u
|
|
#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP1_CFG 0x40006080u
|
|
#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u
|
|
#define CYREG_USB_ARB_EP1_SR 0x40006082u
|
|
#define CYDEV_USB_ARB_RW1_BASE 0x40006084u
|
|
#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW1_WA 0x40006084u
|
|
#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u
|
|
#define CYREG_USB_ARB_RW1_RA 0x40006086u
|
|
#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u
|
|
#define CYREG_USB_ARB_RW1_DR 0x40006088u
|
|
#define CYREG_USB_BUF_SIZE 0x4000608cu
|
|
#define CYREG_USB_EP_ACTIVE 0x4000608eu
|
|
#define CYREG_USB_EP_TYPE 0x4000608fu
|
|
#define CYDEV_USB_ARB_EP2_BASE 0x40006090u
|
|
#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP2_CFG 0x40006090u
|
|
#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u
|
|
#define CYREG_USB_ARB_EP2_SR 0x40006092u
|
|
#define CYDEV_USB_ARB_RW2_BASE 0x40006094u
|
|
#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW2_WA 0x40006094u
|
|
#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u
|
|
#define CYREG_USB_ARB_RW2_RA 0x40006096u
|
|
#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u
|
|
#define CYREG_USB_ARB_RW2_DR 0x40006098u
|
|
#define CYREG_USB_ARB_CFG 0x4000609cu
|
|
#define CYREG_USB_USB_CLK_EN 0x4000609du
|
|
#define CYREG_USB_ARB_INT_EN 0x4000609eu
|
|
#define CYREG_USB_ARB_INT_SR 0x4000609fu
|
|
#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u
|
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#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u
|
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#define CYREG_USB_ARB_EP3_CFG 0x400060a0u
|
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#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u
|
|
#define CYREG_USB_ARB_EP3_SR 0x400060a2u
|
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#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u
|
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#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u
|
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#define CYREG_USB_ARB_RW3_WA 0x400060a4u
|
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#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u
|
|
#define CYREG_USB_ARB_RW3_RA 0x400060a6u
|
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#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u
|
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#define CYREG_USB_ARB_RW3_DR 0x400060a8u
|
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#define CYREG_USB_CWA 0x400060acu
|
|
#define CYREG_USB_CWA_MSB 0x400060adu
|
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#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u
|
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#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP4_CFG 0x400060b0u
|
|
#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u
|
|
#define CYREG_USB_ARB_EP4_SR 0x400060b2u
|
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#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u
|
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#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW4_WA 0x400060b4u
|
|
#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u
|
|
#define CYREG_USB_ARB_RW4_RA 0x400060b6u
|
|
#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u
|
|
#define CYREG_USB_ARB_RW4_DR 0x400060b8u
|
|
#define CYREG_USB_DMA_THRES 0x400060bcu
|
|
#define CYREG_USB_DMA_THRES_MSB 0x400060bdu
|
|
#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u
|
|
#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP5_CFG 0x400060c0u
|
|
#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u
|
|
#define CYREG_USB_ARB_EP5_SR 0x400060c2u
|
|
#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u
|
|
#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW5_WA 0x400060c4u
|
|
#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u
|
|
#define CYREG_USB_ARB_RW5_RA 0x400060c6u
|
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#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u
|
|
#define CYREG_USB_ARB_RW5_DR 0x400060c8u
|
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#define CYREG_USB_BUS_RST_CNT 0x400060ccu
|
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#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u
|
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#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP6_CFG 0x400060d0u
|
|
#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u
|
|
#define CYREG_USB_ARB_EP6_SR 0x400060d2u
|
|
#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u
|
|
#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW6_WA 0x400060d4u
|
|
#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u
|
|
#define CYREG_USB_ARB_RW6_RA 0x400060d6u
|
|
#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u
|
|
#define CYREG_USB_ARB_RW6_DR 0x400060d8u
|
|
#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u
|
|
#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP7_CFG 0x400060e0u
|
|
#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u
|
|
#define CYREG_USB_ARB_EP7_SR 0x400060e2u
|
|
#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u
|
|
#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW7_WA 0x400060e4u
|
|
#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u
|
|
#define CYREG_USB_ARB_RW7_RA 0x400060e6u
|
|
#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u
|
|
#define CYREG_USB_ARB_RW7_DR 0x400060e8u
|
|
#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u
|
|
#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u
|
|
#define CYREG_USB_ARB_EP8_CFG 0x400060f0u
|
|
#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u
|
|
#define CYREG_USB_ARB_EP8_SR 0x400060f2u
|
|
#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u
|
|
#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u
|
|
#define CYREG_USB_ARB_RW8_WA 0x400060f4u
|
|
#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u
|
|
#define CYREG_USB_ARB_RW8_RA 0x400060f6u
|
|
#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u
|
|
#define CYREG_USB_ARB_RW8_DR 0x400060f8u
|
|
#define CYDEV_USB_MEM_BASE 0x40006100u
|
|
#define CYDEV_USB_MEM_SIZE 0x00000200u
|
|
#define CYREG_USB_MEM_DATA_MBASE 0x40006100u
|
|
#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u
|
|
#define CYDEV_UWRK_BASE 0x40006400u
|
|
#define CYDEV_UWRK_SIZE 0x00000b60u
|
|
#define CYDEV_UWRK_UWRK8_BASE 0x40006400u
|
|
#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u
|
|
#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u
|
|
#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u
|
|
#define CYREG_B0_UDB00_A0 0x40006400u
|
|
#define CYREG_B0_UDB01_A0 0x40006401u
|
|
#define CYREG_B0_UDB02_A0 0x40006402u
|
|
#define CYREG_B0_UDB03_A0 0x40006403u
|
|
#define CYREG_B0_UDB04_A0 0x40006404u
|
|
#define CYREG_B0_UDB05_A0 0x40006405u
|
|
#define CYREG_B0_UDB06_A0 0x40006406u
|
|
#define CYREG_B0_UDB07_A0 0x40006407u
|
|
#define CYREG_B0_UDB08_A0 0x40006408u
|
|
#define CYREG_B0_UDB09_A0 0x40006409u
|
|
#define CYREG_B0_UDB10_A0 0x4000640au
|
|
#define CYREG_B0_UDB11_A0 0x4000640bu
|
|
#define CYREG_B0_UDB12_A0 0x4000640cu
|
|
#define CYREG_B0_UDB13_A0 0x4000640du
|
|
#define CYREG_B0_UDB14_A0 0x4000640eu
|
|
#define CYREG_B0_UDB15_A0 0x4000640fu
|
|
#define CYREG_B0_UDB00_A1 0x40006410u
|
|
#define CYREG_B0_UDB01_A1 0x40006411u
|
|
#define CYREG_B0_UDB02_A1 0x40006412u
|
|
#define CYREG_B0_UDB03_A1 0x40006413u
|
|
#define CYREG_B0_UDB04_A1 0x40006414u
|
|
#define CYREG_B0_UDB05_A1 0x40006415u
|
|
#define CYREG_B0_UDB06_A1 0x40006416u
|
|
#define CYREG_B0_UDB07_A1 0x40006417u
|
|
#define CYREG_B0_UDB08_A1 0x40006418u
|
|
#define CYREG_B0_UDB09_A1 0x40006419u
|
|
#define CYREG_B0_UDB10_A1 0x4000641au
|
|
#define CYREG_B0_UDB11_A1 0x4000641bu
|
|
#define CYREG_B0_UDB12_A1 0x4000641cu
|
|
#define CYREG_B0_UDB13_A1 0x4000641du
|
|
#define CYREG_B0_UDB14_A1 0x4000641eu
|
|
#define CYREG_B0_UDB15_A1 0x4000641fu
|
|
#define CYREG_B0_UDB00_D0 0x40006420u
|
|
#define CYREG_B0_UDB01_D0 0x40006421u
|
|
#define CYREG_B0_UDB02_D0 0x40006422u
|
|
#define CYREG_B0_UDB03_D0 0x40006423u
|
|
#define CYREG_B0_UDB04_D0 0x40006424u
|
|
#define CYREG_B0_UDB05_D0 0x40006425u
|
|
#define CYREG_B0_UDB06_D0 0x40006426u
|
|
#define CYREG_B0_UDB07_D0 0x40006427u
|
|
#define CYREG_B0_UDB08_D0 0x40006428u
|
|
#define CYREG_B0_UDB09_D0 0x40006429u
|
|
#define CYREG_B0_UDB10_D0 0x4000642au
|
|
#define CYREG_B0_UDB11_D0 0x4000642bu
|
|
#define CYREG_B0_UDB12_D0 0x4000642cu
|
|
#define CYREG_B0_UDB13_D0 0x4000642du
|
|
#define CYREG_B0_UDB14_D0 0x4000642eu
|
|
#define CYREG_B0_UDB15_D0 0x4000642fu
|
|
#define CYREG_B0_UDB00_D1 0x40006430u
|
|
#define CYREG_B0_UDB01_D1 0x40006431u
|
|
#define CYREG_B0_UDB02_D1 0x40006432u
|
|
#define CYREG_B0_UDB03_D1 0x40006433u
|
|
#define CYREG_B0_UDB04_D1 0x40006434u
|
|
#define CYREG_B0_UDB05_D1 0x40006435u
|
|
#define CYREG_B0_UDB06_D1 0x40006436u
|
|
#define CYREG_B0_UDB07_D1 0x40006437u
|
|
#define CYREG_B0_UDB08_D1 0x40006438u
|
|
#define CYREG_B0_UDB09_D1 0x40006439u
|
|
#define CYREG_B0_UDB10_D1 0x4000643au
|
|
#define CYREG_B0_UDB11_D1 0x4000643bu
|
|
#define CYREG_B0_UDB12_D1 0x4000643cu
|
|
#define CYREG_B0_UDB13_D1 0x4000643du
|
|
#define CYREG_B0_UDB14_D1 0x4000643eu
|
|
#define CYREG_B0_UDB15_D1 0x4000643fu
|
|
#define CYREG_B0_UDB00_F0 0x40006440u
|
|
#define CYREG_B0_UDB01_F0 0x40006441u
|
|
#define CYREG_B0_UDB02_F0 0x40006442u
|
|
#define CYREG_B0_UDB03_F0 0x40006443u
|
|
#define CYREG_B0_UDB04_F0 0x40006444u
|
|
#define CYREG_B0_UDB05_F0 0x40006445u
|
|
#define CYREG_B0_UDB06_F0 0x40006446u
|
|
#define CYREG_B0_UDB07_F0 0x40006447u
|
|
#define CYREG_B0_UDB08_F0 0x40006448u
|
|
#define CYREG_B0_UDB09_F0 0x40006449u
|
|
#define CYREG_B0_UDB10_F0 0x4000644au
|
|
#define CYREG_B0_UDB11_F0 0x4000644bu
|
|
#define CYREG_B0_UDB12_F0 0x4000644cu
|
|
#define CYREG_B0_UDB13_F0 0x4000644du
|
|
#define CYREG_B0_UDB14_F0 0x4000644eu
|
|
#define CYREG_B0_UDB15_F0 0x4000644fu
|
|
#define CYREG_B0_UDB00_F1 0x40006450u
|
|
#define CYREG_B0_UDB01_F1 0x40006451u
|
|
#define CYREG_B0_UDB02_F1 0x40006452u
|
|
#define CYREG_B0_UDB03_F1 0x40006453u
|
|
#define CYREG_B0_UDB04_F1 0x40006454u
|
|
#define CYREG_B0_UDB05_F1 0x40006455u
|
|
#define CYREG_B0_UDB06_F1 0x40006456u
|
|
#define CYREG_B0_UDB07_F1 0x40006457u
|
|
#define CYREG_B0_UDB08_F1 0x40006458u
|
|
#define CYREG_B0_UDB09_F1 0x40006459u
|
|
#define CYREG_B0_UDB10_F1 0x4000645au
|
|
#define CYREG_B0_UDB11_F1 0x4000645bu
|
|
#define CYREG_B0_UDB12_F1 0x4000645cu
|
|
#define CYREG_B0_UDB13_F1 0x4000645du
|
|
#define CYREG_B0_UDB14_F1 0x4000645eu
|
|
#define CYREG_B0_UDB15_F1 0x4000645fu
|
|
#define CYREG_B0_UDB00_ST 0x40006460u
|
|
#define CYREG_B0_UDB01_ST 0x40006461u
|
|
#define CYREG_B0_UDB02_ST 0x40006462u
|
|
#define CYREG_B0_UDB03_ST 0x40006463u
|
|
#define CYREG_B0_UDB04_ST 0x40006464u
|
|
#define CYREG_B0_UDB05_ST 0x40006465u
|
|
#define CYREG_B0_UDB06_ST 0x40006466u
|
|
#define CYREG_B0_UDB07_ST 0x40006467u
|
|
#define CYREG_B0_UDB08_ST 0x40006468u
|
|
#define CYREG_B0_UDB09_ST 0x40006469u
|
|
#define CYREG_B0_UDB10_ST 0x4000646au
|
|
#define CYREG_B0_UDB11_ST 0x4000646bu
|
|
#define CYREG_B0_UDB12_ST 0x4000646cu
|
|
#define CYREG_B0_UDB13_ST 0x4000646du
|
|
#define CYREG_B0_UDB14_ST 0x4000646eu
|
|
#define CYREG_B0_UDB15_ST 0x4000646fu
|
|
#define CYREG_B0_UDB00_CTL 0x40006470u
|
|
#define CYREG_B0_UDB01_CTL 0x40006471u
|
|
#define CYREG_B0_UDB02_CTL 0x40006472u
|
|
#define CYREG_B0_UDB03_CTL 0x40006473u
|
|
#define CYREG_B0_UDB04_CTL 0x40006474u
|
|
#define CYREG_B0_UDB05_CTL 0x40006475u
|
|
#define CYREG_B0_UDB06_CTL 0x40006476u
|
|
#define CYREG_B0_UDB07_CTL 0x40006477u
|
|
#define CYREG_B0_UDB08_CTL 0x40006478u
|
|
#define CYREG_B0_UDB09_CTL 0x40006479u
|
|
#define CYREG_B0_UDB10_CTL 0x4000647au
|
|
#define CYREG_B0_UDB11_CTL 0x4000647bu
|
|
#define CYREG_B0_UDB12_CTL 0x4000647cu
|
|
#define CYREG_B0_UDB13_CTL 0x4000647du
|
|
#define CYREG_B0_UDB14_CTL 0x4000647eu
|
|
#define CYREG_B0_UDB15_CTL 0x4000647fu
|
|
#define CYREG_B0_UDB00_MSK 0x40006480u
|
|
#define CYREG_B0_UDB01_MSK 0x40006481u
|
|
#define CYREG_B0_UDB02_MSK 0x40006482u
|
|
#define CYREG_B0_UDB03_MSK 0x40006483u
|
|
#define CYREG_B0_UDB04_MSK 0x40006484u
|
|
#define CYREG_B0_UDB05_MSK 0x40006485u
|
|
#define CYREG_B0_UDB06_MSK 0x40006486u
|
|
#define CYREG_B0_UDB07_MSK 0x40006487u
|
|
#define CYREG_B0_UDB08_MSK 0x40006488u
|
|
#define CYREG_B0_UDB09_MSK 0x40006489u
|
|
#define CYREG_B0_UDB10_MSK 0x4000648au
|
|
#define CYREG_B0_UDB11_MSK 0x4000648bu
|
|
#define CYREG_B0_UDB12_MSK 0x4000648cu
|
|
#define CYREG_B0_UDB13_MSK 0x4000648du
|
|
#define CYREG_B0_UDB14_MSK 0x4000648eu
|
|
#define CYREG_B0_UDB15_MSK 0x4000648fu
|
|
#define CYREG_B0_UDB00_ACTL 0x40006490u
|
|
#define CYREG_B0_UDB01_ACTL 0x40006491u
|
|
#define CYREG_B0_UDB02_ACTL 0x40006492u
|
|
#define CYREG_B0_UDB03_ACTL 0x40006493u
|
|
#define CYREG_B0_UDB04_ACTL 0x40006494u
|
|
#define CYREG_B0_UDB05_ACTL 0x40006495u
|
|
#define CYREG_B0_UDB06_ACTL 0x40006496u
|
|
#define CYREG_B0_UDB07_ACTL 0x40006497u
|
|
#define CYREG_B0_UDB08_ACTL 0x40006498u
|
|
#define CYREG_B0_UDB09_ACTL 0x40006499u
|
|
#define CYREG_B0_UDB10_ACTL 0x4000649au
|
|
#define CYREG_B0_UDB11_ACTL 0x4000649bu
|
|
#define CYREG_B0_UDB12_ACTL 0x4000649cu
|
|
#define CYREG_B0_UDB13_ACTL 0x4000649du
|
|
#define CYREG_B0_UDB14_ACTL 0x4000649eu
|
|
#define CYREG_B0_UDB15_ACTL 0x4000649fu
|
|
#define CYREG_B0_UDB00_MC 0x400064a0u
|
|
#define CYREG_B0_UDB01_MC 0x400064a1u
|
|
#define CYREG_B0_UDB02_MC 0x400064a2u
|
|
#define CYREG_B0_UDB03_MC 0x400064a3u
|
|
#define CYREG_B0_UDB04_MC 0x400064a4u
|
|
#define CYREG_B0_UDB05_MC 0x400064a5u
|
|
#define CYREG_B0_UDB06_MC 0x400064a6u
|
|
#define CYREG_B0_UDB07_MC 0x400064a7u
|
|
#define CYREG_B0_UDB08_MC 0x400064a8u
|
|
#define CYREG_B0_UDB09_MC 0x400064a9u
|
|
#define CYREG_B0_UDB10_MC 0x400064aau
|
|
#define CYREG_B0_UDB11_MC 0x400064abu
|
|
#define CYREG_B0_UDB12_MC 0x400064acu
|
|
#define CYREG_B0_UDB13_MC 0x400064adu
|
|
#define CYREG_B0_UDB14_MC 0x400064aeu
|
|
#define CYREG_B0_UDB15_MC 0x400064afu
|
|
#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u
|
|
#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u
|
|
#define CYREG_B1_UDB04_A0 0x40006504u
|
|
#define CYREG_B1_UDB05_A0 0x40006505u
|
|
#define CYREG_B1_UDB06_A0 0x40006506u
|
|
#define CYREG_B1_UDB07_A0 0x40006507u
|
|
#define CYREG_B1_UDB08_A0 0x40006508u
|
|
#define CYREG_B1_UDB09_A0 0x40006509u
|
|
#define CYREG_B1_UDB10_A0 0x4000650au
|
|
#define CYREG_B1_UDB11_A0 0x4000650bu
|
|
#define CYREG_B1_UDB04_A1 0x40006514u
|
|
#define CYREG_B1_UDB05_A1 0x40006515u
|
|
#define CYREG_B1_UDB06_A1 0x40006516u
|
|
#define CYREG_B1_UDB07_A1 0x40006517u
|
|
#define CYREG_B1_UDB08_A1 0x40006518u
|
|
#define CYREG_B1_UDB09_A1 0x40006519u
|
|
#define CYREG_B1_UDB10_A1 0x4000651au
|
|
#define CYREG_B1_UDB11_A1 0x4000651bu
|
|
#define CYREG_B1_UDB04_D0 0x40006524u
|
|
#define CYREG_B1_UDB05_D0 0x40006525u
|
|
#define CYREG_B1_UDB06_D0 0x40006526u
|
|
#define CYREG_B1_UDB07_D0 0x40006527u
|
|
#define CYREG_B1_UDB08_D0 0x40006528u
|
|
#define CYREG_B1_UDB09_D0 0x40006529u
|
|
#define CYREG_B1_UDB10_D0 0x4000652au
|
|
#define CYREG_B1_UDB11_D0 0x4000652bu
|
|
#define CYREG_B1_UDB04_D1 0x40006534u
|
|
#define CYREG_B1_UDB05_D1 0x40006535u
|
|
#define CYREG_B1_UDB06_D1 0x40006536u
|
|
#define CYREG_B1_UDB07_D1 0x40006537u
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#define CYREG_B1_UDB08_D1 0x40006538u
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#define CYREG_B1_UDB09_D1 0x40006539u
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#define CYREG_B1_UDB10_D1 0x4000653au
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#define CYREG_B1_UDB11_D1 0x4000653bu
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#define CYREG_B1_UDB04_F0 0x40006544u
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#define CYREG_B1_UDB05_F0 0x40006545u
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#define CYREG_B1_UDB06_F0 0x40006546u
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#define CYREG_B1_UDB07_F0 0x40006547u
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#define CYREG_B1_UDB08_F0 0x40006548u
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#define CYREG_B1_UDB09_F0 0x40006549u
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#define CYREG_B1_UDB10_F0 0x4000654au
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#define CYREG_B1_UDB11_F0 0x4000654bu
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#define CYREG_B1_UDB04_F1 0x40006554u
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#define CYREG_B1_UDB05_F1 0x40006555u
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#define CYREG_B1_UDB06_F1 0x40006556u
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#define CYREG_B1_UDB07_F1 0x40006557u
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#define CYREG_B1_UDB08_F1 0x40006558u
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#define CYREG_B1_UDB09_F1 0x40006559u
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#define CYREG_B1_UDB10_F1 0x4000655au
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#define CYREG_B1_UDB11_F1 0x4000655bu
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#define CYREG_B1_UDB04_ST 0x40006564u
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#define CYREG_B1_UDB05_ST 0x40006565u
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#define CYREG_B1_UDB06_ST 0x40006566u
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#define CYREG_B1_UDB07_ST 0x40006567u
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#define CYREG_B1_UDB08_ST 0x40006568u
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#define CYREG_B1_UDB09_ST 0x40006569u
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#define CYREG_B1_UDB10_ST 0x4000656au
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#define CYREG_B1_UDB11_ST 0x4000656bu
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#define CYREG_B1_UDB04_CTL 0x40006574u
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#define CYREG_B1_UDB05_CTL 0x40006575u
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#define CYREG_B1_UDB06_CTL 0x40006576u
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#define CYREG_B1_UDB07_CTL 0x40006577u
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#define CYREG_B1_UDB08_CTL 0x40006578u
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#define CYREG_B1_UDB09_CTL 0x40006579u
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#define CYREG_B1_UDB10_CTL 0x4000657au
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#define CYREG_B1_UDB11_CTL 0x4000657bu
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#define CYREG_B1_UDB04_MSK 0x40006584u
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#define CYREG_B1_UDB05_MSK 0x40006585u
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#define CYREG_B1_UDB06_MSK 0x40006586u
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#define CYREG_B1_UDB07_MSK 0x40006587u
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#define CYREG_B1_UDB08_MSK 0x40006588u
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#define CYREG_B1_UDB09_MSK 0x40006589u
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#define CYREG_B1_UDB10_MSK 0x4000658au
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#define CYREG_B1_UDB11_MSK 0x4000658bu
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#define CYREG_B1_UDB04_ACTL 0x40006594u
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#define CYREG_B1_UDB05_ACTL 0x40006595u
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#define CYREG_B1_UDB06_ACTL 0x40006596u
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#define CYREG_B1_UDB07_ACTL 0x40006597u
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#define CYREG_B1_UDB08_ACTL 0x40006598u
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#define CYREG_B1_UDB09_ACTL 0x40006599u
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#define CYREG_B1_UDB10_ACTL 0x4000659au
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#define CYREG_B1_UDB11_ACTL 0x4000659bu
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#define CYREG_B1_UDB04_MC 0x400065a4u
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#define CYREG_B1_UDB05_MC 0x400065a5u
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#define CYREG_B1_UDB06_MC 0x400065a6u
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#define CYREG_B1_UDB07_MC 0x400065a7u
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#define CYREG_B1_UDB08_MC 0x400065a8u
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#define CYREG_B1_UDB09_MC 0x400065a9u
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#define CYREG_B1_UDB10_MC 0x400065aau
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#define CYREG_B1_UDB11_MC 0x400065abu
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#define CYDEV_UWRK_UWRK16_BASE 0x40006800u
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#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u
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#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u
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#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u
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#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u
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#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u
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#define CYREG_B0_UDB00_A0_A1 0x40006800u
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#define CYREG_B0_UDB01_A0_A1 0x40006802u
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#define CYREG_B0_UDB02_A0_A1 0x40006804u
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#define CYREG_B0_UDB03_A0_A1 0x40006806u
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#define CYREG_B0_UDB04_A0_A1 0x40006808u
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#define CYREG_B0_UDB05_A0_A1 0x4000680au
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#define CYREG_B0_UDB06_A0_A1 0x4000680cu
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#define CYREG_B0_UDB07_A0_A1 0x4000680eu
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#define CYREG_B0_UDB08_A0_A1 0x40006810u
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#define CYREG_B0_UDB09_A0_A1 0x40006812u
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#define CYREG_B0_UDB10_A0_A1 0x40006814u
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#define CYREG_B0_UDB11_A0_A1 0x40006816u
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#define CYREG_B0_UDB12_A0_A1 0x40006818u
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#define CYREG_B0_UDB13_A0_A1 0x4000681au
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#define CYREG_B0_UDB14_A0_A1 0x4000681cu
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#define CYREG_B0_UDB15_A0_A1 0x4000681eu
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#define CYREG_B0_UDB00_D0_D1 0x40006840u
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#define CYREG_B0_UDB01_D0_D1 0x40006842u
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#define CYREG_B0_UDB02_D0_D1 0x40006844u
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#define CYREG_B0_UDB03_D0_D1 0x40006846u
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#define CYREG_B0_UDB04_D0_D1 0x40006848u
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#define CYREG_B0_UDB05_D0_D1 0x4000684au
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#define CYREG_B0_UDB06_D0_D1 0x4000684cu
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#define CYREG_B0_UDB07_D0_D1 0x4000684eu
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#define CYREG_B0_UDB08_D0_D1 0x40006850u
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#define CYREG_B0_UDB09_D0_D1 0x40006852u
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#define CYREG_B0_UDB10_D0_D1 0x40006854u
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#define CYREG_B0_UDB11_D0_D1 0x40006856u
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#define CYREG_B0_UDB12_D0_D1 0x40006858u
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#define CYREG_B0_UDB13_D0_D1 0x4000685au
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#define CYREG_B0_UDB14_D0_D1 0x4000685cu
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#define CYREG_B0_UDB15_D0_D1 0x4000685eu
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#define CYREG_B0_UDB00_F0_F1 0x40006880u
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#define CYREG_B0_UDB01_F0_F1 0x40006882u
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#define CYREG_B0_UDB02_F0_F1 0x40006884u
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#define CYREG_B0_UDB03_F0_F1 0x40006886u
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#define CYREG_B0_UDB04_F0_F1 0x40006888u
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#define CYREG_B0_UDB05_F0_F1 0x4000688au
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#define CYREG_B0_UDB06_F0_F1 0x4000688cu
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#define CYREG_B0_UDB07_F0_F1 0x4000688eu
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#define CYREG_B0_UDB08_F0_F1 0x40006890u
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#define CYREG_B0_UDB09_F0_F1 0x40006892u
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#define CYREG_B0_UDB10_F0_F1 0x40006894u
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#define CYREG_B0_UDB11_F0_F1 0x40006896u
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#define CYREG_B0_UDB12_F0_F1 0x40006898u
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#define CYREG_B0_UDB13_F0_F1 0x4000689au
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#define CYREG_B0_UDB14_F0_F1 0x4000689cu
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#define CYREG_B0_UDB15_F0_F1 0x4000689eu
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#define CYREG_B0_UDB00_ST_CTL 0x400068c0u
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#define CYREG_B0_UDB01_ST_CTL 0x400068c2u
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#define CYREG_B0_UDB02_ST_CTL 0x400068c4u
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#define CYREG_B0_UDB03_ST_CTL 0x400068c6u
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#define CYREG_B0_UDB04_ST_CTL 0x400068c8u
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#define CYREG_B0_UDB05_ST_CTL 0x400068cau
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#define CYREG_B0_UDB06_ST_CTL 0x400068ccu
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#define CYREG_B0_UDB07_ST_CTL 0x400068ceu
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#define CYREG_B0_UDB08_ST_CTL 0x400068d0u
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#define CYREG_B0_UDB09_ST_CTL 0x400068d2u
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#define CYREG_B0_UDB10_ST_CTL 0x400068d4u
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#define CYREG_B0_UDB11_ST_CTL 0x400068d6u
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#define CYREG_B0_UDB12_ST_CTL 0x400068d8u
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#define CYREG_B0_UDB13_ST_CTL 0x400068dau
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#define CYREG_B0_UDB14_ST_CTL 0x400068dcu
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#define CYREG_B0_UDB15_ST_CTL 0x400068deu
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#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u
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#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u
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#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u
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#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u
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#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u
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#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au
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#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu
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#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu
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#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u
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#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u
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#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u
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#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u
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#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u
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#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au
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#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu
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#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu
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#define CYREG_B0_UDB00_MC_00 0x40006940u
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#define CYREG_B0_UDB01_MC_00 0x40006942u
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#define CYREG_B0_UDB02_MC_00 0x40006944u
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#define CYREG_B0_UDB03_MC_00 0x40006946u
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#define CYREG_B0_UDB04_MC_00 0x40006948u
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#define CYREG_B0_UDB05_MC_00 0x4000694au
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#define CYREG_B0_UDB06_MC_00 0x4000694cu
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#define CYREG_B0_UDB07_MC_00 0x4000694eu
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#define CYREG_B0_UDB08_MC_00 0x40006950u
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#define CYREG_B0_UDB09_MC_00 0x40006952u
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#define CYREG_B0_UDB10_MC_00 0x40006954u
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#define CYREG_B0_UDB11_MC_00 0x40006956u
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#define CYREG_B0_UDB12_MC_00 0x40006958u
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#define CYREG_B0_UDB13_MC_00 0x4000695au
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#define CYREG_B0_UDB14_MC_00 0x4000695cu
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#define CYREG_B0_UDB15_MC_00 0x4000695eu
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#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u
|
|
#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u
|
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#define CYREG_B1_UDB04_A0_A1 0x40006a08u
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#define CYREG_B1_UDB05_A0_A1 0x40006a0au
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#define CYREG_B1_UDB06_A0_A1 0x40006a0cu
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#define CYREG_B1_UDB07_A0_A1 0x40006a0eu
|
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#define CYREG_B1_UDB08_A0_A1 0x40006a10u
|
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#define CYREG_B1_UDB09_A0_A1 0x40006a12u
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#define CYREG_B1_UDB10_A0_A1 0x40006a14u
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#define CYREG_B1_UDB11_A0_A1 0x40006a16u
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#define CYREG_B1_UDB04_D0_D1 0x40006a48u
|
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#define CYREG_B1_UDB05_D0_D1 0x40006a4au
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#define CYREG_B1_UDB06_D0_D1 0x40006a4cu
|
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#define CYREG_B1_UDB07_D0_D1 0x40006a4eu
|
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#define CYREG_B1_UDB08_D0_D1 0x40006a50u
|
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#define CYREG_B1_UDB09_D0_D1 0x40006a52u
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#define CYREG_B1_UDB10_D0_D1 0x40006a54u
|
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#define CYREG_B1_UDB11_D0_D1 0x40006a56u
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#define CYREG_B1_UDB04_F0_F1 0x40006a88u
|
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#define CYREG_B1_UDB05_F0_F1 0x40006a8au
|
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#define CYREG_B1_UDB06_F0_F1 0x40006a8cu
|
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#define CYREG_B1_UDB07_F0_F1 0x40006a8eu
|
|
#define CYREG_B1_UDB08_F0_F1 0x40006a90u
|
|
#define CYREG_B1_UDB09_F0_F1 0x40006a92u
|
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#define CYREG_B1_UDB10_F0_F1 0x40006a94u
|
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#define CYREG_B1_UDB11_F0_F1 0x40006a96u
|
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#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u
|
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#define CYREG_B1_UDB05_ST_CTL 0x40006acau
|
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#define CYREG_B1_UDB06_ST_CTL 0x40006accu
|
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#define CYREG_B1_UDB07_ST_CTL 0x40006aceu
|
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#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u
|
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#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u
|
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#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u
|
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#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u
|
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#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u
|
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#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au
|
|
#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu
|
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#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu
|
|
#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u
|
|
#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u
|
|
#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u
|
|
#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u
|
|
#define CYREG_B1_UDB04_MC_00 0x40006b48u
|
|
#define CYREG_B1_UDB05_MC_00 0x40006b4au
|
|
#define CYREG_B1_UDB06_MC_00 0x40006b4cu
|
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#define CYREG_B1_UDB07_MC_00 0x40006b4eu
|
|
#define CYREG_B1_UDB08_MC_00 0x40006b50u
|
|
#define CYREG_B1_UDB09_MC_00 0x40006b52u
|
|
#define CYREG_B1_UDB10_MC_00 0x40006b54u
|
|
#define CYREG_B1_UDB11_MC_00 0x40006b56u
|
|
#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u
|
|
#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu
|
|
#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u
|
|
#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu
|
|
#define CYREG_B0_UDB00_01_A0 0x40006800u
|
|
#define CYREG_B0_UDB01_02_A0 0x40006802u
|
|
#define CYREG_B0_UDB02_03_A0 0x40006804u
|
|
#define CYREG_B0_UDB03_04_A0 0x40006806u
|
|
#define CYREG_B0_UDB04_05_A0 0x40006808u
|
|
#define CYREG_B0_UDB05_06_A0 0x4000680au
|
|
#define CYREG_B0_UDB06_07_A0 0x4000680cu
|
|
#define CYREG_B0_UDB07_08_A0 0x4000680eu
|
|
#define CYREG_B0_UDB08_09_A0 0x40006810u
|
|
#define CYREG_B0_UDB09_10_A0 0x40006812u
|
|
#define CYREG_B0_UDB10_11_A0 0x40006814u
|
|
#define CYREG_B0_UDB11_12_A0 0x40006816u
|
|
#define CYREG_B0_UDB12_13_A0 0x40006818u
|
|
#define CYREG_B0_UDB13_14_A0 0x4000681au
|
|
#define CYREG_B0_UDB14_15_A0 0x4000681cu
|
|
#define CYREG_B0_UDB00_01_A1 0x40006820u
|
|
#define CYREG_B0_UDB01_02_A1 0x40006822u
|
|
#define CYREG_B0_UDB02_03_A1 0x40006824u
|
|
#define CYREG_B0_UDB03_04_A1 0x40006826u
|
|
#define CYREG_B0_UDB04_05_A1 0x40006828u
|
|
#define CYREG_B0_UDB05_06_A1 0x4000682au
|
|
#define CYREG_B0_UDB06_07_A1 0x4000682cu
|
|
#define CYREG_B0_UDB07_08_A1 0x4000682eu
|
|
#define CYREG_B0_UDB08_09_A1 0x40006830u
|
|
#define CYREG_B0_UDB09_10_A1 0x40006832u
|
|
#define CYREG_B0_UDB10_11_A1 0x40006834u
|
|
#define CYREG_B0_UDB11_12_A1 0x40006836u
|
|
#define CYREG_B0_UDB12_13_A1 0x40006838u
|
|
#define CYREG_B0_UDB13_14_A1 0x4000683au
|
|
#define CYREG_B0_UDB14_15_A1 0x4000683cu
|
|
#define CYREG_B0_UDB00_01_D0 0x40006840u
|
|
#define CYREG_B0_UDB01_02_D0 0x40006842u
|
|
#define CYREG_B0_UDB02_03_D0 0x40006844u
|
|
#define CYREG_B0_UDB03_04_D0 0x40006846u
|
|
#define CYREG_B0_UDB04_05_D0 0x40006848u
|
|
#define CYREG_B0_UDB05_06_D0 0x4000684au
|
|
#define CYREG_B0_UDB06_07_D0 0x4000684cu
|
|
#define CYREG_B0_UDB07_08_D0 0x4000684eu
|
|
#define CYREG_B0_UDB08_09_D0 0x40006850u
|
|
#define CYREG_B0_UDB09_10_D0 0x40006852u
|
|
#define CYREG_B0_UDB10_11_D0 0x40006854u
|
|
#define CYREG_B0_UDB11_12_D0 0x40006856u
|
|
#define CYREG_B0_UDB12_13_D0 0x40006858u
|
|
#define CYREG_B0_UDB13_14_D0 0x4000685au
|
|
#define CYREG_B0_UDB14_15_D0 0x4000685cu
|
|
#define CYREG_B0_UDB00_01_D1 0x40006860u
|
|
#define CYREG_B0_UDB01_02_D1 0x40006862u
|
|
#define CYREG_B0_UDB02_03_D1 0x40006864u
|
|
#define CYREG_B0_UDB03_04_D1 0x40006866u
|
|
#define CYREG_B0_UDB04_05_D1 0x40006868u
|
|
#define CYREG_B0_UDB05_06_D1 0x4000686au
|
|
#define CYREG_B0_UDB06_07_D1 0x4000686cu
|
|
#define CYREG_B0_UDB07_08_D1 0x4000686eu
|
|
#define CYREG_B0_UDB08_09_D1 0x40006870u
|
|
#define CYREG_B0_UDB09_10_D1 0x40006872u
|
|
#define CYREG_B0_UDB10_11_D1 0x40006874u
|
|
#define CYREG_B0_UDB11_12_D1 0x40006876u
|
|
#define CYREG_B0_UDB12_13_D1 0x40006878u
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#define CYREG_B0_UDB13_14_D1 0x4000687au
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#define CYREG_B0_UDB14_15_D1 0x4000687cu
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#define CYREG_B0_UDB00_01_F0 0x40006880u
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#define CYREG_B0_UDB01_02_F0 0x40006882u
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#define CYREG_B0_UDB02_03_F0 0x40006884u
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#define CYREG_B0_UDB03_04_F0 0x40006886u
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#define CYREG_B0_UDB04_05_F0 0x40006888u
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#define CYREG_B0_UDB05_06_F0 0x4000688au
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#define CYREG_B0_UDB06_07_F0 0x4000688cu
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#define CYREG_B0_UDB07_08_F0 0x4000688eu
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#define CYREG_B0_UDB08_09_F0 0x40006890u
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#define CYREG_B0_UDB09_10_F0 0x40006892u
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#define CYREG_B0_UDB10_11_F0 0x40006894u
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#define CYREG_B0_UDB11_12_F0 0x40006896u
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#define CYREG_B0_UDB12_13_F0 0x40006898u
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#define CYREG_B0_UDB13_14_F0 0x4000689au
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#define CYREG_B0_UDB14_15_F0 0x4000689cu
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#define CYREG_B0_UDB00_01_F1 0x400068a0u
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#define CYREG_B0_UDB01_02_F1 0x400068a2u
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#define CYREG_B0_UDB02_03_F1 0x400068a4u
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#define CYREG_B0_UDB03_04_F1 0x400068a6u
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#define CYREG_B0_UDB04_05_F1 0x400068a8u
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#define CYREG_B0_UDB05_06_F1 0x400068aau
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#define CYREG_B0_UDB06_07_F1 0x400068acu
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#define CYREG_B0_UDB07_08_F1 0x400068aeu
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#define CYREG_B0_UDB08_09_F1 0x400068b0u
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#define CYREG_B0_UDB09_10_F1 0x400068b2u
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#define CYREG_B0_UDB10_11_F1 0x400068b4u
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#define CYREG_B0_UDB11_12_F1 0x400068b6u
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#define CYREG_B0_UDB12_13_F1 0x400068b8u
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#define CYREG_B0_UDB13_14_F1 0x400068bau
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#define CYREG_B0_UDB14_15_F1 0x400068bcu
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#define CYREG_B0_UDB00_01_ST 0x400068c0u
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#define CYREG_B0_UDB01_02_ST 0x400068c2u
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#define CYREG_B0_UDB02_03_ST 0x400068c4u
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#define CYREG_B0_UDB03_04_ST 0x400068c6u
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#define CYREG_B0_UDB04_05_ST 0x400068c8u
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#define CYREG_B0_UDB05_06_ST 0x400068cau
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#define CYREG_B0_UDB06_07_ST 0x400068ccu
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#define CYREG_B0_UDB07_08_ST 0x400068ceu
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#define CYREG_B0_UDB08_09_ST 0x400068d0u
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#define CYREG_B0_UDB09_10_ST 0x400068d2u
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#define CYREG_B0_UDB10_11_ST 0x400068d4u
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#define CYREG_B0_UDB11_12_ST 0x400068d6u
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#define CYREG_B0_UDB12_13_ST 0x400068d8u
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#define CYREG_B0_UDB13_14_ST 0x400068dau
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#define CYREG_B0_UDB14_15_ST 0x400068dcu
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#define CYREG_B0_UDB00_01_CTL 0x400068e0u
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#define CYREG_B0_UDB01_02_CTL 0x400068e2u
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#define CYREG_B0_UDB02_03_CTL 0x400068e4u
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#define CYREG_B0_UDB03_04_CTL 0x400068e6u
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#define CYREG_B0_UDB04_05_CTL 0x400068e8u
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#define CYREG_B0_UDB05_06_CTL 0x400068eau
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#define CYREG_B0_UDB06_07_CTL 0x400068ecu
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#define CYREG_B0_UDB07_08_CTL 0x400068eeu
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#define CYREG_B0_UDB08_09_CTL 0x400068f0u
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#define CYREG_B0_UDB09_10_CTL 0x400068f2u
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#define CYREG_B0_UDB10_11_CTL 0x400068f4u
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#define CYREG_B0_UDB11_12_CTL 0x400068f6u
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#define CYREG_B0_UDB12_13_CTL 0x400068f8u
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#define CYREG_B0_UDB13_14_CTL 0x400068fau
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#define CYREG_B0_UDB14_15_CTL 0x400068fcu
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#define CYREG_B0_UDB00_01_MSK 0x40006900u
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#define CYREG_B0_UDB01_02_MSK 0x40006902u
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#define CYREG_B0_UDB02_03_MSK 0x40006904u
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#define CYREG_B0_UDB03_04_MSK 0x40006906u
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#define CYREG_B0_UDB04_05_MSK 0x40006908u
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#define CYREG_B0_UDB05_06_MSK 0x4000690au
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#define CYREG_B0_UDB06_07_MSK 0x4000690cu
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#define CYREG_B0_UDB07_08_MSK 0x4000690eu
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#define CYREG_B0_UDB08_09_MSK 0x40006910u
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#define CYREG_B0_UDB09_10_MSK 0x40006912u
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#define CYREG_B0_UDB10_11_MSK 0x40006914u
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#define CYREG_B0_UDB11_12_MSK 0x40006916u
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#define CYREG_B0_UDB12_13_MSK 0x40006918u
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#define CYREG_B0_UDB13_14_MSK 0x4000691au
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#define CYREG_B0_UDB14_15_MSK 0x4000691cu
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#define CYREG_B0_UDB00_01_ACTL 0x40006920u
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#define CYREG_B0_UDB01_02_ACTL 0x40006922u
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#define CYREG_B0_UDB02_03_ACTL 0x40006924u
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#define CYREG_B0_UDB03_04_ACTL 0x40006926u
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#define CYREG_B0_UDB04_05_ACTL 0x40006928u
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#define CYREG_B0_UDB05_06_ACTL 0x4000692au
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#define CYREG_B0_UDB06_07_ACTL 0x4000692cu
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#define CYREG_B0_UDB07_08_ACTL 0x4000692eu
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#define CYREG_B0_UDB08_09_ACTL 0x40006930u
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#define CYREG_B0_UDB09_10_ACTL 0x40006932u
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#define CYREG_B0_UDB10_11_ACTL 0x40006934u
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#define CYREG_B0_UDB11_12_ACTL 0x40006936u
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#define CYREG_B0_UDB12_13_ACTL 0x40006938u
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#define CYREG_B0_UDB13_14_ACTL 0x4000693au
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#define CYREG_B0_UDB14_15_ACTL 0x4000693cu
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#define CYREG_B0_UDB00_01_MC 0x40006940u
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#define CYREG_B0_UDB01_02_MC 0x40006942u
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#define CYREG_B0_UDB02_03_MC 0x40006944u
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#define CYREG_B0_UDB03_04_MC 0x40006946u
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#define CYREG_B0_UDB04_05_MC 0x40006948u
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#define CYREG_B0_UDB05_06_MC 0x4000694au
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#define CYREG_B0_UDB06_07_MC 0x4000694cu
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#define CYREG_B0_UDB07_08_MC 0x4000694eu
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#define CYREG_B0_UDB08_09_MC 0x40006950u
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#define CYREG_B0_UDB09_10_MC 0x40006952u
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#define CYREG_B0_UDB10_11_MC 0x40006954u
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#define CYREG_B0_UDB11_12_MC 0x40006956u
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#define CYREG_B0_UDB12_13_MC 0x40006958u
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#define CYREG_B0_UDB13_14_MC 0x4000695au
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#define CYREG_B0_UDB14_15_MC 0x4000695cu
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#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u
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#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu
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#define CYREG_B1_UDB04_05_A0 0x40006a08u
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#define CYREG_B1_UDB05_06_A0 0x40006a0au
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#define CYREG_B1_UDB06_07_A0 0x40006a0cu
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#define CYREG_B1_UDB07_08_A0 0x40006a0eu
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#define CYREG_B1_UDB08_09_A0 0x40006a10u
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#define CYREG_B1_UDB09_10_A0 0x40006a12u
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#define CYREG_B1_UDB10_11_A0 0x40006a14u
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#define CYREG_B1_UDB11_12_A0 0x40006a16u
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#define CYREG_B1_UDB04_05_A1 0x40006a28u
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#define CYREG_B1_UDB05_06_A1 0x40006a2au
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#define CYREG_B1_UDB06_07_A1 0x40006a2cu
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#define CYREG_B1_UDB07_08_A1 0x40006a2eu
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#define CYREG_B1_UDB08_09_A1 0x40006a30u
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#define CYREG_B1_UDB09_10_A1 0x40006a32u
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#define CYREG_B1_UDB10_11_A1 0x40006a34u
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#define CYREG_B1_UDB11_12_A1 0x40006a36u
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#define CYREG_B1_UDB04_05_D0 0x40006a48u
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#define CYREG_B1_UDB05_06_D0 0x40006a4au
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#define CYREG_B1_UDB06_07_D0 0x40006a4cu
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#define CYREG_B1_UDB07_08_D0 0x40006a4eu
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#define CYREG_B1_UDB08_09_D0 0x40006a50u
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#define CYREG_B1_UDB09_10_D0 0x40006a52u
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#define CYREG_B1_UDB10_11_D0 0x40006a54u
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#define CYREG_B1_UDB11_12_D0 0x40006a56u
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#define CYREG_B1_UDB04_05_D1 0x40006a68u
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#define CYREG_B1_UDB05_06_D1 0x40006a6au
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#define CYREG_B1_UDB06_07_D1 0x40006a6cu
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#define CYREG_B1_UDB07_08_D1 0x40006a6eu
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#define CYREG_B1_UDB08_09_D1 0x40006a70u
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#define CYREG_B1_UDB09_10_D1 0x40006a72u
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#define CYREG_B1_UDB10_11_D1 0x40006a74u
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#define CYREG_B1_UDB11_12_D1 0x40006a76u
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#define CYREG_B1_UDB04_05_F0 0x40006a88u
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#define CYREG_B1_UDB05_06_F0 0x40006a8au
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#define CYREG_B1_UDB06_07_F0 0x40006a8cu
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#define CYREG_B1_UDB07_08_F0 0x40006a8eu
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#define CYREG_B1_UDB08_09_F0 0x40006a90u
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#define CYREG_B1_UDB09_10_F0 0x40006a92u
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#define CYREG_B1_UDB10_11_F0 0x40006a94u
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#define CYREG_B1_UDB11_12_F0 0x40006a96u
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#define CYREG_B1_UDB04_05_F1 0x40006aa8u
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#define CYREG_B1_UDB05_06_F1 0x40006aaau
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#define CYREG_B1_UDB06_07_F1 0x40006aacu
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#define CYREG_B1_UDB07_08_F1 0x40006aaeu
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#define CYREG_B1_UDB08_09_F1 0x40006ab0u
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#define CYREG_B1_UDB09_10_F1 0x40006ab2u
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#define CYREG_B1_UDB10_11_F1 0x40006ab4u
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#define CYREG_B1_UDB11_12_F1 0x40006ab6u
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#define CYREG_B1_UDB04_05_ST 0x40006ac8u
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#define CYREG_B1_UDB05_06_ST 0x40006acau
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#define CYREG_B1_UDB06_07_ST 0x40006accu
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#define CYREG_B1_UDB07_08_ST 0x40006aceu
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#define CYREG_B1_UDB08_09_ST 0x40006ad0u
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#define CYREG_B1_UDB09_10_ST 0x40006ad2u
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#define CYREG_B1_UDB10_11_ST 0x40006ad4u
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#define CYREG_B1_UDB11_12_ST 0x40006ad6u
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#define CYREG_B1_UDB04_05_CTL 0x40006ae8u
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#define CYREG_B1_UDB05_06_CTL 0x40006aeau
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#define CYREG_B1_UDB06_07_CTL 0x40006aecu
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#define CYREG_B1_UDB07_08_CTL 0x40006aeeu
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#define CYREG_B1_UDB08_09_CTL 0x40006af0u
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#define CYREG_B1_UDB09_10_CTL 0x40006af2u
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#define CYREG_B1_UDB10_11_CTL 0x40006af4u
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#define CYREG_B1_UDB11_12_CTL 0x40006af6u
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#define CYREG_B1_UDB04_05_MSK 0x40006b08u
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#define CYREG_B1_UDB05_06_MSK 0x40006b0au
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#define CYREG_B1_UDB06_07_MSK 0x40006b0cu
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#define CYREG_B1_UDB07_08_MSK 0x40006b0eu
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#define CYREG_B1_UDB08_09_MSK 0x40006b10u
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#define CYREG_B1_UDB09_10_MSK 0x40006b12u
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#define CYREG_B1_UDB10_11_MSK 0x40006b14u
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#define CYREG_B1_UDB11_12_MSK 0x40006b16u
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#define CYREG_B1_UDB04_05_ACTL 0x40006b28u
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#define CYREG_B1_UDB05_06_ACTL 0x40006b2au
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#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu
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#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu
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#define CYREG_B1_UDB08_09_ACTL 0x40006b30u
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#define CYREG_B1_UDB09_10_ACTL 0x40006b32u
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#define CYREG_B1_UDB10_11_ACTL 0x40006b34u
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#define CYREG_B1_UDB11_12_ACTL 0x40006b36u
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#define CYREG_B1_UDB04_05_MC 0x40006b48u
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#define CYREG_B1_UDB05_06_MC 0x40006b4au
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#define CYREG_B1_UDB06_07_MC 0x40006b4cu
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#define CYREG_B1_UDB07_08_MC 0x40006b4eu
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#define CYREG_B1_UDB08_09_MC 0x40006b50u
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#define CYREG_B1_UDB09_10_MC 0x40006b52u
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#define CYREG_B1_UDB10_11_MC 0x40006b54u
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#define CYREG_B1_UDB11_12_MC 0x40006b56u
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#define CYDEV_PHUB_BASE 0x40007000u
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#define CYDEV_PHUB_SIZE 0x00000c00u
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#define CYREG_PHUB_CFG 0x40007000u
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#define CYREG_PHUB_ERR 0x40007004u
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#define CYREG_PHUB_ERR_ADR 0x40007008u
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#define CYDEV_PHUB_CH0_BASE 0x40007010u
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#define CYDEV_PHUB_CH0_SIZE 0x0000000cu
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#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u
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#define CYREG_PHUB_CH0_ACTION 0x40007014u
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#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u
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#define CYDEV_PHUB_CH1_BASE 0x40007020u
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#define CYDEV_PHUB_CH1_SIZE 0x0000000cu
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#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u
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#define CYREG_PHUB_CH1_ACTION 0x40007024u
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#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u
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#define CYDEV_PHUB_CH2_BASE 0x40007030u
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#define CYDEV_PHUB_CH2_SIZE 0x0000000cu
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#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u
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#define CYREG_PHUB_CH2_ACTION 0x40007034u
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#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u
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#define CYDEV_PHUB_CH3_BASE 0x40007040u
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#define CYDEV_PHUB_CH3_SIZE 0x0000000cu
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#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u
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#define CYREG_PHUB_CH3_ACTION 0x40007044u
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#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u
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#define CYDEV_PHUB_CH4_BASE 0x40007050u
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#define CYDEV_PHUB_CH4_SIZE 0x0000000cu
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#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u
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#define CYREG_PHUB_CH4_ACTION 0x40007054u
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#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u
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#define CYDEV_PHUB_CH5_BASE 0x40007060u
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#define CYDEV_PHUB_CH5_SIZE 0x0000000cu
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#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u
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#define CYREG_PHUB_CH5_ACTION 0x40007064u
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#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u
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#define CYDEV_PHUB_CH6_BASE 0x40007070u
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#define CYDEV_PHUB_CH6_SIZE 0x0000000cu
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#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u
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#define CYREG_PHUB_CH6_ACTION 0x40007074u
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#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u
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#define CYDEV_PHUB_CH7_BASE 0x40007080u
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#define CYDEV_PHUB_CH7_SIZE 0x0000000cu
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#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u
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#define CYREG_PHUB_CH7_ACTION 0x40007084u
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#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u
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#define CYDEV_PHUB_CH8_BASE 0x40007090u
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#define CYDEV_PHUB_CH8_SIZE 0x0000000cu
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#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u
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#define CYREG_PHUB_CH8_ACTION 0x40007094u
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#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u
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#define CYDEV_PHUB_CH9_BASE 0x400070a0u
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#define CYDEV_PHUB_CH9_SIZE 0x0000000cu
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#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u
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#define CYREG_PHUB_CH9_ACTION 0x400070a4u
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#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u
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#define CYDEV_PHUB_CH10_BASE 0x400070b0u
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#define CYDEV_PHUB_CH10_SIZE 0x0000000cu
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#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u
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#define CYREG_PHUB_CH10_ACTION 0x400070b4u
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#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u
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#define CYDEV_PHUB_CH11_BASE 0x400070c0u
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#define CYDEV_PHUB_CH11_SIZE 0x0000000cu
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#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u
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#define CYREG_PHUB_CH11_ACTION 0x400070c4u
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#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u
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#define CYDEV_PHUB_CH12_BASE 0x400070d0u
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#define CYDEV_PHUB_CH12_SIZE 0x0000000cu
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#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u
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#define CYREG_PHUB_CH12_ACTION 0x400070d4u
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#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u
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#define CYDEV_PHUB_CH13_BASE 0x400070e0u
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#define CYDEV_PHUB_CH13_SIZE 0x0000000cu
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#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u
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#define CYREG_PHUB_CH13_ACTION 0x400070e4u
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#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u
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#define CYDEV_PHUB_CH14_BASE 0x400070f0u
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#define CYDEV_PHUB_CH14_SIZE 0x0000000cu
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#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u
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#define CYREG_PHUB_CH14_ACTION 0x400070f4u
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#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u
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#define CYDEV_PHUB_CH15_BASE 0x40007100u
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#define CYDEV_PHUB_CH15_SIZE 0x0000000cu
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#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u
|
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#define CYREG_PHUB_CH15_ACTION 0x40007104u
|
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#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u
|
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#define CYDEV_PHUB_CH16_BASE 0x40007110u
|
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#define CYDEV_PHUB_CH16_SIZE 0x0000000cu
|
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#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u
|
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#define CYREG_PHUB_CH16_ACTION 0x40007114u
|
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#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u
|
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#define CYDEV_PHUB_CH17_BASE 0x40007120u
|
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#define CYDEV_PHUB_CH17_SIZE 0x0000000cu
|
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#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u
|
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#define CYREG_PHUB_CH17_ACTION 0x40007124u
|
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#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u
|
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#define CYDEV_PHUB_CH18_BASE 0x40007130u
|
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#define CYDEV_PHUB_CH18_SIZE 0x0000000cu
|
|
#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u
|
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#define CYREG_PHUB_CH18_ACTION 0x40007134u
|
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#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u
|
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#define CYDEV_PHUB_CH19_BASE 0x40007140u
|
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#define CYDEV_PHUB_CH19_SIZE 0x0000000cu
|
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#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u
|
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#define CYREG_PHUB_CH19_ACTION 0x40007144u
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#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u
|
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#define CYDEV_PHUB_CH20_BASE 0x40007150u
|
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#define CYDEV_PHUB_CH20_SIZE 0x0000000cu
|
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#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u
|
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#define CYREG_PHUB_CH20_ACTION 0x40007154u
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#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u
|
|
#define CYDEV_PHUB_CH21_BASE 0x40007160u
|
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#define CYDEV_PHUB_CH21_SIZE 0x0000000cu
|
|
#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u
|
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#define CYREG_PHUB_CH21_ACTION 0x40007164u
|
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#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u
|
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#define CYDEV_PHUB_CH22_BASE 0x40007170u
|
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#define CYDEV_PHUB_CH22_SIZE 0x0000000cu
|
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#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u
|
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#define CYREG_PHUB_CH22_ACTION 0x40007174u
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#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u
|
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#define CYDEV_PHUB_CH23_BASE 0x40007180u
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#define CYDEV_PHUB_CH23_SIZE 0x0000000cu
|
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#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u
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#define CYREG_PHUB_CH23_ACTION 0x40007184u
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#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u
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#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u
|
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#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u
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#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u
|
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#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u
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#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u
|
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#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u
|
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#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u
|
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#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu
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#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u
|
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#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u
|
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#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u
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#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u
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#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u
|
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#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u
|
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#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u
|
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#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu
|
|
#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u
|
|
#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u
|
|
#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u
|
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#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u
|
|
#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u
|
|
#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu
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|
#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u
|
|
#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u
|
|
#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u
|
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#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u
|
|
#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u
|
|
#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu
|
|
#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u
|
|
#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u
|
|
#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u
|
|
#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u
|
|
#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u
|
|
#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu
|
|
#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u
|
|
#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u
|
|
#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u
|
|
#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u
|
|
#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u
|
|
#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu
|
|
#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u
|
|
#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u
|
|
#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u
|
|
#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u
|
|
#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u
|
|
#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu
|
|
#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u
|
|
#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u
|
|
#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u
|
|
#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u
|
|
#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u
|
|
#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu
|
|
#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u
|
|
#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u
|
|
#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u
|
|
#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u
|
|
#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u
|
|
#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu
|
|
#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u
|
|
#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u
|
|
#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u
|
|
#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u
|
|
#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u
|
|
#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu
|
|
#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u
|
|
#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u
|
|
#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u
|
|
#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u
|
|
#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u
|
|
#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu
|
|
#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u
|
|
#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u
|
|
#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u
|
|
#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u
|
|
#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u
|
|
#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u
|
|
#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu
|
|
#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u
|
|
#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u
|
|
#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u
|
|
#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u
|
|
#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u
|
|
#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu
|
|
#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u
|
|
#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u
|
|
#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u
|
|
#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u
|
|
#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u
|
|
#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu
|
|
#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u
|
|
#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u
|
|
#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u
|
|
#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u
|
|
#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u
|
|
#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu
|
|
#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u
|
|
#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u
|
|
#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u
|
|
#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u
|
|
#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u
|
|
#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu
|
|
#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u
|
|
#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u
|
|
#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u
|
|
#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u
|
|
#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u
|
|
#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu
|
|
#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u
|
|
#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u
|
|
#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u
|
|
#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u
|
|
#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u
|
|
#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu
|
|
#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u
|
|
#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u
|
|
#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u
|
|
#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u
|
|
#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u
|
|
#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu
|
|
#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u
|
|
#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u
|
|
#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u
|
|
#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u
|
|
#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u
|
|
#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu
|
|
#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u
|
|
#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u
|
|
#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u
|
|
#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u
|
|
#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u
|
|
#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu
|
|
#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u
|
|
#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u
|
|
#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u
|
|
#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u
|
|
#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u
|
|
#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu
|
|
#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u
|
|
#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u
|
|
#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u
|
|
#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u
|
|
#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u
|
|
#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu
|
|
#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u
|
|
#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u
|
|
#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u
|
|
#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u
|
|
#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u
|
|
#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu
|
|
#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u
|
|
#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u
|
|
#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u
|
|
#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u
|
|
#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u
|
|
#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu
|
|
#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u
|
|
#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u
|
|
#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u
|
|
#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u
|
|
#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u
|
|
#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu
|
|
#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u
|
|
#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u
|
|
#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u
|
|
#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u
|
|
#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u
|
|
#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu
|
|
#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u
|
|
#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u
|
|
#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u
|
|
#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u
|
|
#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u
|
|
#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu
|
|
#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u
|
|
#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u
|
|
#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u
|
|
#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u
|
|
#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u
|
|
#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu
|
|
#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u
|
|
#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u
|
|
#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u
|
|
#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u
|
|
#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u
|
|
#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu
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#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u
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#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u
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#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u
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#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u
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#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u
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#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu
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#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u
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#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u
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#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u
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#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u
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#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u
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#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu
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#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u
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#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u
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#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u
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#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u
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#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u
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#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu
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#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u
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#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u
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#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u
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#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u
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#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u
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#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu
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#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u
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#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u
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#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u
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#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u
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#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u
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#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu
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#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u
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#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u
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#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u
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#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u
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#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u
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#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu
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#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u
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#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u
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#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u
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#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u
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#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u
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#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu
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#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u
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#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u
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#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u
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#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u
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#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u
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#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu
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#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u
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#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u
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#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u
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#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u
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#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u
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#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu
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#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u
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#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u
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#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u
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#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u
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#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u
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#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu
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#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u
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#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u
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#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u
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#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u
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#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u
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#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu
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#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u
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#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u
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#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u
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#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u
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#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u
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#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu
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#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u
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#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u
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#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u
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#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u
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#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u
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#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu
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#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u
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#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u
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#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u
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#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u
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#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u
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#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu
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#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u
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#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u
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#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u
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#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u
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#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u
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#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu
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#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u
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#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u
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#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u
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#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u
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#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u
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#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu
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#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u
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#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u
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#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u
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#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u
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#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u
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#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu
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#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u
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#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u
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#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u
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#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u
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#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u
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#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu
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#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u
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#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u
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#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u
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#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u
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#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u
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#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu
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#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u
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#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u
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#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u
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#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u
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#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u
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#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu
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#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u
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#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u
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#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u
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#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u
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#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u
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#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu
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#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u
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#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u
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#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u
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#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u
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#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u
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#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu
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#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u
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#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u
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#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u
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#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u
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#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u
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#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu
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#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u
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#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u
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#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u
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#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u
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#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u
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#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu
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#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u
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#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u
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#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u
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#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u
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#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u
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#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu
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#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u
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#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u
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#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u
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#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u
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#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u
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#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu
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#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u
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#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u
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#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u
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#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u
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#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u
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#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu
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#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u
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#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u
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#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u
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#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u
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#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u
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#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu
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#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u
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#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u
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#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u
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#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u
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#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u
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#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu
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#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u
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#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u
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#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u
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#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u
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#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u
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#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu
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#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u
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#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u
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#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u
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#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u
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#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u
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#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu
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#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u
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#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u
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#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u
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#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u
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#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u
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#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu
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#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u
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#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u
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#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u
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#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u
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#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u
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#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu
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#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u
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#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u
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#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u
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#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u
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#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u
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#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u
|
|
#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu
|
|
#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u
|
|
#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u
|
|
#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u
|
|
#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u
|
|
#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u
|
|
#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu
|
|
#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u
|
|
#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u
|
|
#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u
|
|
#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u
|
|
#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u
|
|
#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu
|
|
#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u
|
|
#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u
|
|
#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u
|
|
#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u
|
|
#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u
|
|
#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu
|
|
#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u
|
|
#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u
|
|
#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u
|
|
#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u
|
|
#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u
|
|
#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu
|
|
#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u
|
|
#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u
|
|
#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u
|
|
#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u
|
|
#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u
|
|
#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu
|
|
#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u
|
|
#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u
|
|
#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u
|
|
#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u
|
|
#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u
|
|
#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu
|
|
#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u
|
|
#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u
|
|
#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u
|
|
#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u
|
|
#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u
|
|
#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu
|
|
#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u
|
|
#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u
|
|
#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u
|
|
#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u
|
|
#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u
|
|
#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu
|
|
#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u
|
|
#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u
|
|
#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u
|
|
#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u
|
|
#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u
|
|
#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu
|
|
#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u
|
|
#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u
|
|
#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u
|
|
#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u
|
|
#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u
|
|
#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu
|
|
#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u
|
|
#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u
|
|
#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u
|
|
#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u
|
|
#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u
|
|
#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu
|
|
#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u
|
|
#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u
|
|
#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u
|
|
#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u
|
|
#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u
|
|
#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u
|
|
#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu
|
|
#define CYDEV_EE_BASE 0x40008000u
|
|
#define CYDEV_EE_SIZE 0x00000800u
|
|
#define CYREG_EE_DATA_MBASE 0x40008000u
|
|
#define CYREG_EE_DATA_MSIZE 0x00000800u
|
|
#define CYDEV_CAN0_BASE 0x4000a000u
|
|
#define CYDEV_CAN0_SIZE 0x000002a0u
|
|
#define CYDEV_CAN0_CSR_BASE 0x4000a000u
|
|
#define CYDEV_CAN0_CSR_SIZE 0x00000018u
|
|
#define CYREG_CAN0_CSR_INT_SR 0x4000a000u
|
|
#define CYREG_CAN0_CSR_INT_EN 0x4000a004u
|
|
#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u
|
|
#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu
|
|
#define CYREG_CAN0_CSR_CMD 0x4000a010u
|
|
#define CYREG_CAN0_CSR_CFG 0x4000a014u
|
|
#define CYDEV_CAN0_TX0_BASE 0x4000a020u
|
|
#define CYDEV_CAN0_TX0_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX0_CMD 0x4000a020u
|
|
#define CYREG_CAN0_TX0_ID 0x4000a024u
|
|
#define CYREG_CAN0_TX0_DH 0x4000a028u
|
|
#define CYREG_CAN0_TX0_DL 0x4000a02cu
|
|
#define CYDEV_CAN0_TX1_BASE 0x4000a030u
|
|
#define CYDEV_CAN0_TX1_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX1_CMD 0x4000a030u
|
|
#define CYREG_CAN0_TX1_ID 0x4000a034u
|
|
#define CYREG_CAN0_TX1_DH 0x4000a038u
|
|
#define CYREG_CAN0_TX1_DL 0x4000a03cu
|
|
#define CYDEV_CAN0_TX2_BASE 0x4000a040u
|
|
#define CYDEV_CAN0_TX2_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX2_CMD 0x4000a040u
|
|
#define CYREG_CAN0_TX2_ID 0x4000a044u
|
|
#define CYREG_CAN0_TX2_DH 0x4000a048u
|
|
#define CYREG_CAN0_TX2_DL 0x4000a04cu
|
|
#define CYDEV_CAN0_TX3_BASE 0x4000a050u
|
|
#define CYDEV_CAN0_TX3_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX3_CMD 0x4000a050u
|
|
#define CYREG_CAN0_TX3_ID 0x4000a054u
|
|
#define CYREG_CAN0_TX3_DH 0x4000a058u
|
|
#define CYREG_CAN0_TX3_DL 0x4000a05cu
|
|
#define CYDEV_CAN0_TX4_BASE 0x4000a060u
|
|
#define CYDEV_CAN0_TX4_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX4_CMD 0x4000a060u
|
|
#define CYREG_CAN0_TX4_ID 0x4000a064u
|
|
#define CYREG_CAN0_TX4_DH 0x4000a068u
|
|
#define CYREG_CAN0_TX4_DL 0x4000a06cu
|
|
#define CYDEV_CAN0_TX5_BASE 0x4000a070u
|
|
#define CYDEV_CAN0_TX5_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX5_CMD 0x4000a070u
|
|
#define CYREG_CAN0_TX5_ID 0x4000a074u
|
|
#define CYREG_CAN0_TX5_DH 0x4000a078u
|
|
#define CYREG_CAN0_TX5_DL 0x4000a07cu
|
|
#define CYDEV_CAN0_TX6_BASE 0x4000a080u
|
|
#define CYDEV_CAN0_TX6_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX6_CMD 0x4000a080u
|
|
#define CYREG_CAN0_TX6_ID 0x4000a084u
|
|
#define CYREG_CAN0_TX6_DH 0x4000a088u
|
|
#define CYREG_CAN0_TX6_DL 0x4000a08cu
|
|
#define CYDEV_CAN0_TX7_BASE 0x4000a090u
|
|
#define CYDEV_CAN0_TX7_SIZE 0x00000010u
|
|
#define CYREG_CAN0_TX7_CMD 0x4000a090u
|
|
#define CYREG_CAN0_TX7_ID 0x4000a094u
|
|
#define CYREG_CAN0_TX7_DH 0x4000a098u
|
|
#define CYREG_CAN0_TX7_DL 0x4000a09cu
|
|
#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u
|
|
#define CYDEV_CAN0_RX0_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX0_CMD 0x4000a0a0u
|
|
#define CYREG_CAN0_RX0_ID 0x4000a0a4u
|
|
#define CYREG_CAN0_RX0_DH 0x4000a0a8u
|
|
#define CYREG_CAN0_RX0_DL 0x4000a0acu
|
|
#define CYREG_CAN0_RX0_AMR 0x4000a0b0u
|
|
#define CYREG_CAN0_RX0_ACR 0x4000a0b4u
|
|
#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u
|
|
#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu
|
|
#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u
|
|
#define CYDEV_CAN0_RX1_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX1_CMD 0x4000a0c0u
|
|
#define CYREG_CAN0_RX1_ID 0x4000a0c4u
|
|
#define CYREG_CAN0_RX1_DH 0x4000a0c8u
|
|
#define CYREG_CAN0_RX1_DL 0x4000a0ccu
|
|
#define CYREG_CAN0_RX1_AMR 0x4000a0d0u
|
|
#define CYREG_CAN0_RX1_ACR 0x4000a0d4u
|
|
#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u
|
|
#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu
|
|
#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u
|
|
#define CYDEV_CAN0_RX2_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX2_CMD 0x4000a0e0u
|
|
#define CYREG_CAN0_RX2_ID 0x4000a0e4u
|
|
#define CYREG_CAN0_RX2_DH 0x4000a0e8u
|
|
#define CYREG_CAN0_RX2_DL 0x4000a0ecu
|
|
#define CYREG_CAN0_RX2_AMR 0x4000a0f0u
|
|
#define CYREG_CAN0_RX2_ACR 0x4000a0f4u
|
|
#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u
|
|
#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu
|
|
#define CYDEV_CAN0_RX3_BASE 0x4000a100u
|
|
#define CYDEV_CAN0_RX3_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX3_CMD 0x4000a100u
|
|
#define CYREG_CAN0_RX3_ID 0x4000a104u
|
|
#define CYREG_CAN0_RX3_DH 0x4000a108u
|
|
#define CYREG_CAN0_RX3_DL 0x4000a10cu
|
|
#define CYREG_CAN0_RX3_AMR 0x4000a110u
|
|
#define CYREG_CAN0_RX3_ACR 0x4000a114u
|
|
#define CYREG_CAN0_RX3_AMRD 0x4000a118u
|
|
#define CYREG_CAN0_RX3_ACRD 0x4000a11cu
|
|
#define CYDEV_CAN0_RX4_BASE 0x4000a120u
|
|
#define CYDEV_CAN0_RX4_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX4_CMD 0x4000a120u
|
|
#define CYREG_CAN0_RX4_ID 0x4000a124u
|
|
#define CYREG_CAN0_RX4_DH 0x4000a128u
|
|
#define CYREG_CAN0_RX4_DL 0x4000a12cu
|
|
#define CYREG_CAN0_RX4_AMR 0x4000a130u
|
|
#define CYREG_CAN0_RX4_ACR 0x4000a134u
|
|
#define CYREG_CAN0_RX4_AMRD 0x4000a138u
|
|
#define CYREG_CAN0_RX4_ACRD 0x4000a13cu
|
|
#define CYDEV_CAN0_RX5_BASE 0x4000a140u
|
|
#define CYDEV_CAN0_RX5_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX5_CMD 0x4000a140u
|
|
#define CYREG_CAN0_RX5_ID 0x4000a144u
|
|
#define CYREG_CAN0_RX5_DH 0x4000a148u
|
|
#define CYREG_CAN0_RX5_DL 0x4000a14cu
|
|
#define CYREG_CAN0_RX5_AMR 0x4000a150u
|
|
#define CYREG_CAN0_RX5_ACR 0x4000a154u
|
|
#define CYREG_CAN0_RX5_AMRD 0x4000a158u
|
|
#define CYREG_CAN0_RX5_ACRD 0x4000a15cu
|
|
#define CYDEV_CAN0_RX6_BASE 0x4000a160u
|
|
#define CYDEV_CAN0_RX6_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX6_CMD 0x4000a160u
|
|
#define CYREG_CAN0_RX6_ID 0x4000a164u
|
|
#define CYREG_CAN0_RX6_DH 0x4000a168u
|
|
#define CYREG_CAN0_RX6_DL 0x4000a16cu
|
|
#define CYREG_CAN0_RX6_AMR 0x4000a170u
|
|
#define CYREG_CAN0_RX6_ACR 0x4000a174u
|
|
#define CYREG_CAN0_RX6_AMRD 0x4000a178u
|
|
#define CYREG_CAN0_RX6_ACRD 0x4000a17cu
|
|
#define CYDEV_CAN0_RX7_BASE 0x4000a180u
|
|
#define CYDEV_CAN0_RX7_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX7_CMD 0x4000a180u
|
|
#define CYREG_CAN0_RX7_ID 0x4000a184u
|
|
#define CYREG_CAN0_RX7_DH 0x4000a188u
|
|
#define CYREG_CAN0_RX7_DL 0x4000a18cu
|
|
#define CYREG_CAN0_RX7_AMR 0x4000a190u
|
|
#define CYREG_CAN0_RX7_ACR 0x4000a194u
|
|
#define CYREG_CAN0_RX7_AMRD 0x4000a198u
|
|
#define CYREG_CAN0_RX7_ACRD 0x4000a19cu
|
|
#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u
|
|
#define CYDEV_CAN0_RX8_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX8_CMD 0x4000a1a0u
|
|
#define CYREG_CAN0_RX8_ID 0x4000a1a4u
|
|
#define CYREG_CAN0_RX8_DH 0x4000a1a8u
|
|
#define CYREG_CAN0_RX8_DL 0x4000a1acu
|
|
#define CYREG_CAN0_RX8_AMR 0x4000a1b0u
|
|
#define CYREG_CAN0_RX8_ACR 0x4000a1b4u
|
|
#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u
|
|
#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu
|
|
#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u
|
|
#define CYDEV_CAN0_RX9_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX9_CMD 0x4000a1c0u
|
|
#define CYREG_CAN0_RX9_ID 0x4000a1c4u
|
|
#define CYREG_CAN0_RX9_DH 0x4000a1c8u
|
|
#define CYREG_CAN0_RX9_DL 0x4000a1ccu
|
|
#define CYREG_CAN0_RX9_AMR 0x4000a1d0u
|
|
#define CYREG_CAN0_RX9_ACR 0x4000a1d4u
|
|
#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u
|
|
#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu
|
|
#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u
|
|
#define CYDEV_CAN0_RX10_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX10_CMD 0x4000a1e0u
|
|
#define CYREG_CAN0_RX10_ID 0x4000a1e4u
|
|
#define CYREG_CAN0_RX10_DH 0x4000a1e8u
|
|
#define CYREG_CAN0_RX10_DL 0x4000a1ecu
|
|
#define CYREG_CAN0_RX10_AMR 0x4000a1f0u
|
|
#define CYREG_CAN0_RX10_ACR 0x4000a1f4u
|
|
#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u
|
|
#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu
|
|
#define CYDEV_CAN0_RX11_BASE 0x4000a200u
|
|
#define CYDEV_CAN0_RX11_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX11_CMD 0x4000a200u
|
|
#define CYREG_CAN0_RX11_ID 0x4000a204u
|
|
#define CYREG_CAN0_RX11_DH 0x4000a208u
|
|
#define CYREG_CAN0_RX11_DL 0x4000a20cu
|
|
#define CYREG_CAN0_RX11_AMR 0x4000a210u
|
|
#define CYREG_CAN0_RX11_ACR 0x4000a214u
|
|
#define CYREG_CAN0_RX11_AMRD 0x4000a218u
|
|
#define CYREG_CAN0_RX11_ACRD 0x4000a21cu
|
|
#define CYDEV_CAN0_RX12_BASE 0x4000a220u
|
|
#define CYDEV_CAN0_RX12_SIZE 0x00000020u
|
|
#define CYREG_CAN0_RX12_CMD 0x4000a220u
|
|
#define CYREG_CAN0_RX12_ID 0x4000a224u
|
|
#define CYREG_CAN0_RX12_DH 0x4000a228u
|
|
#define CYREG_CAN0_RX12_DL 0x4000a22cu
|
|
#define CYREG_CAN0_RX12_AMR 0x4000a230u
|
|
#define CYREG_CAN0_RX12_ACR 0x4000a234u
|
|
#define CYREG_CAN0_RX12_AMRD 0x4000a238u
|
|
#define CYREG_CAN0_RX12_ACRD 0x4000a23cu
|
|
#define CYDEV_CAN0_RX13_BASE 0x4000a240u
|
|
#define CYDEV_CAN0_RX13_SIZE 0x00000020u
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#define CYREG_CAN0_RX13_CMD 0x4000a240u
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#define CYREG_CAN0_RX13_ID 0x4000a244u
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#define CYREG_CAN0_RX13_DH 0x4000a248u
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#define CYREG_CAN0_RX13_DL 0x4000a24cu
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#define CYREG_CAN0_RX13_AMR 0x4000a250u
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#define CYREG_CAN0_RX13_ACR 0x4000a254u
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#define CYREG_CAN0_RX13_AMRD 0x4000a258u
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#define CYREG_CAN0_RX13_ACRD 0x4000a25cu
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#define CYDEV_CAN0_RX14_BASE 0x4000a260u
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#define CYDEV_CAN0_RX14_SIZE 0x00000020u
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#define CYREG_CAN0_RX14_CMD 0x4000a260u
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#define CYREG_CAN0_RX14_ID 0x4000a264u
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#define CYREG_CAN0_RX14_DH 0x4000a268u
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#define CYREG_CAN0_RX14_DL 0x4000a26cu
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#define CYREG_CAN0_RX14_AMR 0x4000a270u
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#define CYREG_CAN0_RX14_ACR 0x4000a274u
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#define CYREG_CAN0_RX14_AMRD 0x4000a278u
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#define CYREG_CAN0_RX14_ACRD 0x4000a27cu
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#define CYDEV_CAN0_RX15_BASE 0x4000a280u
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#define CYDEV_CAN0_RX15_SIZE 0x00000020u
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#define CYREG_CAN0_RX15_CMD 0x4000a280u
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#define CYREG_CAN0_RX15_ID 0x4000a284u
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#define CYREG_CAN0_RX15_DH 0x4000a288u
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#define CYREG_CAN0_RX15_DL 0x4000a28cu
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#define CYREG_CAN0_RX15_AMR 0x4000a290u
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#define CYREG_CAN0_RX15_ACR 0x4000a294u
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#define CYREG_CAN0_RX15_AMRD 0x4000a298u
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#define CYREG_CAN0_RX15_ACRD 0x4000a29cu
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#define CYDEV_DFB0_BASE 0x4000c000u
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#define CYDEV_DFB0_SIZE 0x000007b5u
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#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u
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#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u
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#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u
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#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u
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#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u
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#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u
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#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u
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#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u
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#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u
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#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u
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#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u
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#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u
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#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u
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#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u
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#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u
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#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u
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#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u
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#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u
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#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u
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#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u
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#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u
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#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u
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#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u
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#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u
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#define CYREG_DFB0_CR 0x4000c780u
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#define CYREG_DFB0_SR 0x4000c784u
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#define CYREG_DFB0_RAM_EN 0x4000c788u
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#define CYREG_DFB0_RAM_DIR 0x4000c78cu
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#define CYREG_DFB0_SEMA 0x4000c790u
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#define CYREG_DFB0_DSI_CTRL 0x4000c794u
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#define CYREG_DFB0_INT_CTRL 0x4000c798u
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#define CYREG_DFB0_DMA_CTRL 0x4000c79cu
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#define CYREG_DFB0_STAGEA 0x4000c7a0u
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#define CYREG_DFB0_STAGEAM 0x4000c7a1u
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#define CYREG_DFB0_STAGEAH 0x4000c7a2u
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#define CYREG_DFB0_STAGEB 0x4000c7a4u
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#define CYREG_DFB0_STAGEBM 0x4000c7a5u
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#define CYREG_DFB0_STAGEBH 0x4000c7a6u
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#define CYREG_DFB0_HOLDA 0x4000c7a8u
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#define CYREG_DFB0_HOLDAM 0x4000c7a9u
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#define CYREG_DFB0_HOLDAH 0x4000c7aau
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#define CYREG_DFB0_HOLDAS 0x4000c7abu
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#define CYREG_DFB0_HOLDB 0x4000c7acu
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#define CYREG_DFB0_HOLDBM 0x4000c7adu
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#define CYREG_DFB0_HOLDBH 0x4000c7aeu
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#define CYREG_DFB0_HOLDBS 0x4000c7afu
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#define CYREG_DFB0_COHER 0x4000c7b0u
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#define CYREG_DFB0_DALIGN 0x4000c7b4u
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#define CYDEV_UCFG_BASE 0x40010000u
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#define CYDEV_UCFG_SIZE 0x00005040u
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#define CYDEV_UCFG_B0_BASE 0x40010000u
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#define CYDEV_UCFG_B0_SIZE 0x00000fefu
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#define CYDEV_UCFG_B0_P0_BASE 0x40010000u
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#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u
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#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u
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#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u
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#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u
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#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u
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#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu
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|
#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u
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#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u
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#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u
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#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu
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#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u
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#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u
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#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u
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#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu
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#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u
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|
#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u
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|
#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u
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|
#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u
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#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u
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|
#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au
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#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu
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#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu
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#define CYREG_B0_P0_U0_CFG0 0x40010040u
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#define CYREG_B0_P0_U0_CFG1 0x40010041u
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#define CYREG_B0_P0_U0_CFG2 0x40010042u
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#define CYREG_B0_P0_U0_CFG3 0x40010043u
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#define CYREG_B0_P0_U0_CFG4 0x40010044u
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#define CYREG_B0_P0_U0_CFG5 0x40010045u
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#define CYREG_B0_P0_U0_CFG6 0x40010046u
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#define CYREG_B0_P0_U0_CFG7 0x40010047u
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|
#define CYREG_B0_P0_U0_CFG8 0x40010048u
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#define CYREG_B0_P0_U0_CFG9 0x40010049u
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#define CYREG_B0_P0_U0_CFG10 0x4001004au
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#define CYREG_B0_P0_U0_CFG11 0x4001004bu
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#define CYREG_B0_P0_U0_CFG12 0x4001004cu
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|
#define CYREG_B0_P0_U0_CFG13 0x4001004du
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#define CYREG_B0_P0_U0_CFG14 0x4001004eu
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#define CYREG_B0_P0_U0_CFG15 0x4001004fu
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#define CYREG_B0_P0_U0_CFG16 0x40010050u
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#define CYREG_B0_P0_U0_CFG17 0x40010051u
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#define CYREG_B0_P0_U0_CFG18 0x40010052u
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#define CYREG_B0_P0_U0_CFG19 0x40010053u
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#define CYREG_B0_P0_U0_CFG20 0x40010054u
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#define CYREG_B0_P0_U0_CFG21 0x40010055u
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#define CYREG_B0_P0_U0_CFG22 0x40010056u
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#define CYREG_B0_P0_U0_CFG23 0x40010057u
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#define CYREG_B0_P0_U0_CFG24 0x40010058u
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#define CYREG_B0_P0_U0_CFG25 0x40010059u
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#define CYREG_B0_P0_U0_CFG26 0x4001005au
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#define CYREG_B0_P0_U0_CFG27 0x4001005bu
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#define CYREG_B0_P0_U0_CFG28 0x4001005cu
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#define CYREG_B0_P0_U0_CFG29 0x4001005du
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#define CYREG_B0_P0_U0_CFG30 0x4001005eu
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#define CYREG_B0_P0_U0_CFG31 0x4001005fu
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#define CYREG_B0_P0_U0_DCFG0 0x40010060u
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#define CYREG_B0_P0_U0_DCFG1 0x40010062u
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#define CYREG_B0_P0_U0_DCFG2 0x40010064u
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#define CYREG_B0_P0_U0_DCFG3 0x40010066u
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#define CYREG_B0_P0_U0_DCFG4 0x40010068u
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#define CYREG_B0_P0_U0_DCFG5 0x4001006au
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#define CYREG_B0_P0_U0_DCFG6 0x4001006cu
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#define CYREG_B0_P0_U0_DCFG7 0x4001006eu
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#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u
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|
#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u
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|
#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u
|
|
#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u
|
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#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u
|
|
#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu
|
|
#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u
|
|
#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u
|
|
#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u
|
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#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu
|
|
#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u
|
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#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u
|
|
#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u
|
|
#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu
|
|
#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u
|
|
#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u
|
|
#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u
|
|
#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u
|
|
#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u
|
|
#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau
|
|
#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu
|
|
#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu
|
|
#define CYREG_B0_P0_U1_CFG0 0x400100c0u
|
|
#define CYREG_B0_P0_U1_CFG1 0x400100c1u
|
|
#define CYREG_B0_P0_U1_CFG2 0x400100c2u
|
|
#define CYREG_B0_P0_U1_CFG3 0x400100c3u
|
|
#define CYREG_B0_P0_U1_CFG4 0x400100c4u
|
|
#define CYREG_B0_P0_U1_CFG5 0x400100c5u
|
|
#define CYREG_B0_P0_U1_CFG6 0x400100c6u
|
|
#define CYREG_B0_P0_U1_CFG7 0x400100c7u
|
|
#define CYREG_B0_P0_U1_CFG8 0x400100c8u
|
|
#define CYREG_B0_P0_U1_CFG9 0x400100c9u
|
|
#define CYREG_B0_P0_U1_CFG10 0x400100cau
|
|
#define CYREG_B0_P0_U1_CFG11 0x400100cbu
|
|
#define CYREG_B0_P0_U1_CFG12 0x400100ccu
|
|
#define CYREG_B0_P0_U1_CFG13 0x400100cdu
|
|
#define CYREG_B0_P0_U1_CFG14 0x400100ceu
|
|
#define CYREG_B0_P0_U1_CFG15 0x400100cfu
|
|
#define CYREG_B0_P0_U1_CFG16 0x400100d0u
|
|
#define CYREG_B0_P0_U1_CFG17 0x400100d1u
|
|
#define CYREG_B0_P0_U1_CFG18 0x400100d2u
|
|
#define CYREG_B0_P0_U1_CFG19 0x400100d3u
|
|
#define CYREG_B0_P0_U1_CFG20 0x400100d4u
|
|
#define CYREG_B0_P0_U1_CFG21 0x400100d5u
|
|
#define CYREG_B0_P0_U1_CFG22 0x400100d6u
|
|
#define CYREG_B0_P0_U1_CFG23 0x400100d7u
|
|
#define CYREG_B0_P0_U1_CFG24 0x400100d8u
|
|
#define CYREG_B0_P0_U1_CFG25 0x400100d9u
|
|
#define CYREG_B0_P0_U1_CFG26 0x400100dau
|
|
#define CYREG_B0_P0_U1_CFG27 0x400100dbu
|
|
#define CYREG_B0_P0_U1_CFG28 0x400100dcu
|
|
#define CYREG_B0_P0_U1_CFG29 0x400100ddu
|
|
#define CYREG_B0_P0_U1_CFG30 0x400100deu
|
|
#define CYREG_B0_P0_U1_CFG31 0x400100dfu
|
|
#define CYREG_B0_P0_U1_DCFG0 0x400100e0u
|
|
#define CYREG_B0_P0_U1_DCFG1 0x400100e2u
|
|
#define CYREG_B0_P0_U1_DCFG2 0x400100e4u
|
|
#define CYREG_B0_P0_U1_DCFG3 0x400100e6u
|
|
#define CYREG_B0_P0_U1_DCFG4 0x400100e8u
|
|
#define CYREG_B0_P0_U1_DCFG5 0x400100eau
|
|
#define CYREG_B0_P0_U1_DCFG6 0x400100ecu
|
|
#define CYREG_B0_P0_U1_DCFG7 0x400100eeu
|
|
#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u
|
|
#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu
|
|
#define CYDEV_UCFG_B0_P1_BASE 0x40010200u
|
|
#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu
|
|
#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u
|
|
#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u
|
|
#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u
|
|
#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u
|
|
#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u
|
|
#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu
|
|
#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u
|
|
#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u
|
|
#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u
|
|
#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu
|
|
#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u
|
|
#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u
|
|
#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u
|
|
#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu
|
|
#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u
|
|
#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u
|
|
#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u
|
|
#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u
|
|
#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u
|
|
#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au
|
|
#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu
|
|
#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu
|
|
#define CYREG_B0_P1_U0_CFG0 0x40010240u
|
|
#define CYREG_B0_P1_U0_CFG1 0x40010241u
|
|
#define CYREG_B0_P1_U0_CFG2 0x40010242u
|
|
#define CYREG_B0_P1_U0_CFG3 0x40010243u
|
|
#define CYREG_B0_P1_U0_CFG4 0x40010244u
|
|
#define CYREG_B0_P1_U0_CFG5 0x40010245u
|
|
#define CYREG_B0_P1_U0_CFG6 0x40010246u
|
|
#define CYREG_B0_P1_U0_CFG7 0x40010247u
|
|
#define CYREG_B0_P1_U0_CFG8 0x40010248u
|
|
#define CYREG_B0_P1_U0_CFG9 0x40010249u
|
|
#define CYREG_B0_P1_U0_CFG10 0x4001024au
|
|
#define CYREG_B0_P1_U0_CFG11 0x4001024bu
|
|
#define CYREG_B0_P1_U0_CFG12 0x4001024cu
|
|
#define CYREG_B0_P1_U0_CFG13 0x4001024du
|
|
#define CYREG_B0_P1_U0_CFG14 0x4001024eu
|
|
#define CYREG_B0_P1_U0_CFG15 0x4001024fu
|
|
#define CYREG_B0_P1_U0_CFG16 0x40010250u
|
|
#define CYREG_B0_P1_U0_CFG17 0x40010251u
|
|
#define CYREG_B0_P1_U0_CFG18 0x40010252u
|
|
#define CYREG_B0_P1_U0_CFG19 0x40010253u
|
|
#define CYREG_B0_P1_U0_CFG20 0x40010254u
|
|
#define CYREG_B0_P1_U0_CFG21 0x40010255u
|
|
#define CYREG_B0_P1_U0_CFG22 0x40010256u
|
|
#define CYREG_B0_P1_U0_CFG23 0x40010257u
|
|
#define CYREG_B0_P1_U0_CFG24 0x40010258u
|
|
#define CYREG_B0_P1_U0_CFG25 0x40010259u
|
|
#define CYREG_B0_P1_U0_CFG26 0x4001025au
|
|
#define CYREG_B0_P1_U0_CFG27 0x4001025bu
|
|
#define CYREG_B0_P1_U0_CFG28 0x4001025cu
|
|
#define CYREG_B0_P1_U0_CFG29 0x4001025du
|
|
#define CYREG_B0_P1_U0_CFG30 0x4001025eu
|
|
#define CYREG_B0_P1_U0_CFG31 0x4001025fu
|
|
#define CYREG_B0_P1_U0_DCFG0 0x40010260u
|
|
#define CYREG_B0_P1_U0_DCFG1 0x40010262u
|
|
#define CYREG_B0_P1_U0_DCFG2 0x40010264u
|
|
#define CYREG_B0_P1_U0_DCFG3 0x40010266u
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#define CYREG_B0_P1_U0_DCFG4 0x40010268u
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#define CYREG_B0_P1_U0_DCFG5 0x4001026au
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#define CYREG_B0_P1_U0_DCFG6 0x4001026cu
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#define CYREG_B0_P1_U0_DCFG7 0x4001026eu
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#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u
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#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u
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#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u
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#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u
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#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u
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#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu
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#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u
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#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u
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#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u
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#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu
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#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u
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#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u
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#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u
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#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu
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#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u
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#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u
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#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u
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#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u
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#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u
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#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau
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#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu
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#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu
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#define CYREG_B0_P1_U1_CFG0 0x400102c0u
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#define CYREG_B0_P1_U1_CFG1 0x400102c1u
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#define CYREG_B0_P1_U1_CFG2 0x400102c2u
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#define CYREG_B0_P1_U1_CFG3 0x400102c3u
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#define CYREG_B0_P1_U1_CFG4 0x400102c4u
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#define CYREG_B0_P1_U1_CFG5 0x400102c5u
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#define CYREG_B0_P1_U1_CFG6 0x400102c6u
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#define CYREG_B0_P1_U1_CFG7 0x400102c7u
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#define CYREG_B0_P1_U1_CFG8 0x400102c8u
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#define CYREG_B0_P1_U1_CFG9 0x400102c9u
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#define CYREG_B0_P1_U1_CFG10 0x400102cau
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#define CYREG_B0_P1_U1_CFG11 0x400102cbu
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#define CYREG_B0_P1_U1_CFG12 0x400102ccu
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#define CYREG_B0_P1_U1_CFG13 0x400102cdu
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#define CYREG_B0_P1_U1_CFG14 0x400102ceu
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#define CYREG_B0_P1_U1_CFG15 0x400102cfu
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#define CYREG_B0_P1_U1_CFG16 0x400102d0u
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#define CYREG_B0_P1_U1_CFG17 0x400102d1u
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#define CYREG_B0_P1_U1_CFG18 0x400102d2u
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#define CYREG_B0_P1_U1_CFG19 0x400102d3u
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#define CYREG_B0_P1_U1_CFG20 0x400102d4u
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#define CYREG_B0_P1_U1_CFG21 0x400102d5u
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#define CYREG_B0_P1_U1_CFG22 0x400102d6u
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#define CYREG_B0_P1_U1_CFG23 0x400102d7u
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#define CYREG_B0_P1_U1_CFG24 0x400102d8u
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#define CYREG_B0_P1_U1_CFG25 0x400102d9u
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#define CYREG_B0_P1_U1_CFG26 0x400102dau
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#define CYREG_B0_P1_U1_CFG27 0x400102dbu
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#define CYREG_B0_P1_U1_CFG28 0x400102dcu
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#define CYREG_B0_P1_U1_CFG29 0x400102ddu
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#define CYREG_B0_P1_U1_CFG30 0x400102deu
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#define CYREG_B0_P1_U1_CFG31 0x400102dfu
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#define CYREG_B0_P1_U1_DCFG0 0x400102e0u
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#define CYREG_B0_P1_U1_DCFG1 0x400102e2u
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#define CYREG_B0_P1_U1_DCFG2 0x400102e4u
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#define CYREG_B0_P1_U1_DCFG3 0x400102e6u
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#define CYREG_B0_P1_U1_DCFG4 0x400102e8u
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#define CYREG_B0_P1_U1_DCFG5 0x400102eau
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#define CYREG_B0_P1_U1_DCFG6 0x400102ecu
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#define CYREG_B0_P1_U1_DCFG7 0x400102eeu
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#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u
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#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B0_P2_BASE 0x40010400u
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#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u
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#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u
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#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u
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#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u
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#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u
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#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu
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#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u
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#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u
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#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u
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#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu
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#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u
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#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u
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#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u
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#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu
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#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u
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#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u
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#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u
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#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u
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#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u
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#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au
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#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu
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#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu
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#define CYREG_B0_P2_U0_CFG0 0x40010440u
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#define CYREG_B0_P2_U0_CFG1 0x40010441u
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#define CYREG_B0_P2_U0_CFG2 0x40010442u
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#define CYREG_B0_P2_U0_CFG3 0x40010443u
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#define CYREG_B0_P2_U0_CFG4 0x40010444u
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#define CYREG_B0_P2_U0_CFG5 0x40010445u
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#define CYREG_B0_P2_U0_CFG6 0x40010446u
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#define CYREG_B0_P2_U0_CFG7 0x40010447u
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#define CYREG_B0_P2_U0_CFG8 0x40010448u
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#define CYREG_B0_P2_U0_CFG9 0x40010449u
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#define CYREG_B0_P2_U0_CFG10 0x4001044au
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#define CYREG_B0_P2_U0_CFG11 0x4001044bu
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#define CYREG_B0_P2_U0_CFG12 0x4001044cu
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#define CYREG_B0_P2_U0_CFG13 0x4001044du
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#define CYREG_B0_P2_U0_CFG14 0x4001044eu
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#define CYREG_B0_P2_U0_CFG15 0x4001044fu
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#define CYREG_B0_P2_U0_CFG16 0x40010450u
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#define CYREG_B0_P2_U0_CFG17 0x40010451u
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#define CYREG_B0_P2_U0_CFG18 0x40010452u
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#define CYREG_B0_P2_U0_CFG19 0x40010453u
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#define CYREG_B0_P2_U0_CFG20 0x40010454u
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#define CYREG_B0_P2_U0_CFG21 0x40010455u
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#define CYREG_B0_P2_U0_CFG22 0x40010456u
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#define CYREG_B0_P2_U0_CFG23 0x40010457u
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#define CYREG_B0_P2_U0_CFG24 0x40010458u
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#define CYREG_B0_P2_U0_CFG25 0x40010459u
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#define CYREG_B0_P2_U0_CFG26 0x4001045au
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#define CYREG_B0_P2_U0_CFG27 0x4001045bu
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#define CYREG_B0_P2_U0_CFG28 0x4001045cu
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#define CYREG_B0_P2_U0_CFG29 0x4001045du
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#define CYREG_B0_P2_U0_CFG30 0x4001045eu
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#define CYREG_B0_P2_U0_CFG31 0x4001045fu
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#define CYREG_B0_P2_U0_DCFG0 0x40010460u
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#define CYREG_B0_P2_U0_DCFG1 0x40010462u
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#define CYREG_B0_P2_U0_DCFG2 0x40010464u
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#define CYREG_B0_P2_U0_DCFG3 0x40010466u
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#define CYREG_B0_P2_U0_DCFG4 0x40010468u
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#define CYREG_B0_P2_U0_DCFG5 0x4001046au
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#define CYREG_B0_P2_U0_DCFG6 0x4001046cu
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#define CYREG_B0_P2_U0_DCFG7 0x4001046eu
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#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u
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#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u
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#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u
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#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u
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#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u
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#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu
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#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u
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#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u
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#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u
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#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu
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#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u
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#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u
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#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u
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#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu
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#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u
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#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u
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#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u
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#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u
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#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u
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#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau
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#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu
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#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu
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#define CYREG_B0_P2_U1_CFG0 0x400104c0u
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#define CYREG_B0_P2_U1_CFG1 0x400104c1u
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#define CYREG_B0_P2_U1_CFG2 0x400104c2u
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#define CYREG_B0_P2_U1_CFG3 0x400104c3u
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#define CYREG_B0_P2_U1_CFG4 0x400104c4u
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#define CYREG_B0_P2_U1_CFG5 0x400104c5u
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#define CYREG_B0_P2_U1_CFG6 0x400104c6u
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#define CYREG_B0_P2_U1_CFG7 0x400104c7u
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#define CYREG_B0_P2_U1_CFG8 0x400104c8u
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#define CYREG_B0_P2_U1_CFG9 0x400104c9u
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#define CYREG_B0_P2_U1_CFG10 0x400104cau
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#define CYREG_B0_P2_U1_CFG11 0x400104cbu
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#define CYREG_B0_P2_U1_CFG12 0x400104ccu
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#define CYREG_B0_P2_U1_CFG13 0x400104cdu
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#define CYREG_B0_P2_U1_CFG14 0x400104ceu
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#define CYREG_B0_P2_U1_CFG15 0x400104cfu
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#define CYREG_B0_P2_U1_CFG16 0x400104d0u
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#define CYREG_B0_P2_U1_CFG17 0x400104d1u
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#define CYREG_B0_P2_U1_CFG18 0x400104d2u
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#define CYREG_B0_P2_U1_CFG19 0x400104d3u
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#define CYREG_B0_P2_U1_CFG20 0x400104d4u
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#define CYREG_B0_P2_U1_CFG21 0x400104d5u
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#define CYREG_B0_P2_U1_CFG22 0x400104d6u
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#define CYREG_B0_P2_U1_CFG23 0x400104d7u
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#define CYREG_B0_P2_U1_CFG24 0x400104d8u
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#define CYREG_B0_P2_U1_CFG25 0x400104d9u
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#define CYREG_B0_P2_U1_CFG26 0x400104dau
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#define CYREG_B0_P2_U1_CFG27 0x400104dbu
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#define CYREG_B0_P2_U1_CFG28 0x400104dcu
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#define CYREG_B0_P2_U1_CFG29 0x400104ddu
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#define CYREG_B0_P2_U1_CFG30 0x400104deu
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#define CYREG_B0_P2_U1_CFG31 0x400104dfu
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#define CYREG_B0_P2_U1_DCFG0 0x400104e0u
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#define CYREG_B0_P2_U1_DCFG1 0x400104e2u
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#define CYREG_B0_P2_U1_DCFG2 0x400104e4u
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#define CYREG_B0_P2_U1_DCFG3 0x400104e6u
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#define CYREG_B0_P2_U1_DCFG4 0x400104e8u
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#define CYREG_B0_P2_U1_DCFG5 0x400104eau
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#define CYREG_B0_P2_U1_DCFG6 0x400104ecu
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#define CYREG_B0_P2_U1_DCFG7 0x400104eeu
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#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u
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#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B0_P3_BASE 0x40010600u
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#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u
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#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u
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#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u
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#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u
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#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u
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#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu
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#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u
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#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u
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#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u
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#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu
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#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u
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#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u
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#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u
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#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu
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#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u
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#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u
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#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u
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#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u
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#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u
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#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au
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#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu
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#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu
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#define CYREG_B0_P3_U0_CFG0 0x40010640u
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#define CYREG_B0_P3_U0_CFG1 0x40010641u
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#define CYREG_B0_P3_U0_CFG2 0x40010642u
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#define CYREG_B0_P3_U0_CFG3 0x40010643u
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#define CYREG_B0_P3_U0_CFG4 0x40010644u
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#define CYREG_B0_P3_U0_CFG5 0x40010645u
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#define CYREG_B0_P3_U0_CFG6 0x40010646u
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#define CYREG_B0_P3_U0_CFG7 0x40010647u
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#define CYREG_B0_P3_U0_CFG8 0x40010648u
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#define CYREG_B0_P3_U0_CFG9 0x40010649u
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#define CYREG_B0_P3_U0_CFG10 0x4001064au
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#define CYREG_B0_P3_U0_CFG11 0x4001064bu
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#define CYREG_B0_P3_U0_CFG12 0x4001064cu
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#define CYREG_B0_P3_U0_CFG13 0x4001064du
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#define CYREG_B0_P3_U0_CFG14 0x4001064eu
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#define CYREG_B0_P3_U0_CFG15 0x4001064fu
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#define CYREG_B0_P3_U0_CFG16 0x40010650u
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#define CYREG_B0_P3_U0_CFG17 0x40010651u
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#define CYREG_B0_P3_U0_CFG18 0x40010652u
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#define CYREG_B0_P3_U0_CFG19 0x40010653u
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#define CYREG_B0_P3_U0_CFG20 0x40010654u
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#define CYREG_B0_P3_U0_CFG21 0x40010655u
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#define CYREG_B0_P3_U0_CFG22 0x40010656u
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#define CYREG_B0_P3_U0_CFG23 0x40010657u
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#define CYREG_B0_P3_U0_CFG24 0x40010658u
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#define CYREG_B0_P3_U0_CFG25 0x40010659u
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#define CYREG_B0_P3_U0_CFG26 0x4001065au
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#define CYREG_B0_P3_U0_CFG27 0x4001065bu
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#define CYREG_B0_P3_U0_CFG28 0x4001065cu
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#define CYREG_B0_P3_U0_CFG29 0x4001065du
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#define CYREG_B0_P3_U0_CFG30 0x4001065eu
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#define CYREG_B0_P3_U0_CFG31 0x4001065fu
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#define CYREG_B0_P3_U0_DCFG0 0x40010660u
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#define CYREG_B0_P3_U0_DCFG1 0x40010662u
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#define CYREG_B0_P3_U0_DCFG2 0x40010664u
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#define CYREG_B0_P3_U0_DCFG3 0x40010666u
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#define CYREG_B0_P3_U0_DCFG4 0x40010668u
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#define CYREG_B0_P3_U0_DCFG5 0x4001066au
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#define CYREG_B0_P3_U0_DCFG6 0x4001066cu
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#define CYREG_B0_P3_U0_DCFG7 0x4001066eu
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#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u
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#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u
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#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u
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#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u
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#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u
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#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu
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#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u
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#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u
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#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u
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#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu
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#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u
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#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u
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#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u
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#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu
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#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u
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#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u
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#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u
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#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u
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#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u
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#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau
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#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu
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#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu
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#define CYREG_B0_P3_U1_CFG0 0x400106c0u
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#define CYREG_B0_P3_U1_CFG1 0x400106c1u
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#define CYREG_B0_P3_U1_CFG2 0x400106c2u
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#define CYREG_B0_P3_U1_CFG3 0x400106c3u
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#define CYREG_B0_P3_U1_CFG4 0x400106c4u
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#define CYREG_B0_P3_U1_CFG5 0x400106c5u
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#define CYREG_B0_P3_U1_CFG6 0x400106c6u
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#define CYREG_B0_P3_U1_CFG7 0x400106c7u
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#define CYREG_B0_P3_U1_CFG8 0x400106c8u
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#define CYREG_B0_P3_U1_CFG9 0x400106c9u
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#define CYREG_B0_P3_U1_CFG10 0x400106cau
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#define CYREG_B0_P3_U1_CFG11 0x400106cbu
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#define CYREG_B0_P3_U1_CFG12 0x400106ccu
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#define CYREG_B0_P3_U1_CFG13 0x400106cdu
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#define CYREG_B0_P3_U1_CFG14 0x400106ceu
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#define CYREG_B0_P3_U1_CFG15 0x400106cfu
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#define CYREG_B0_P3_U1_CFG16 0x400106d0u
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#define CYREG_B0_P3_U1_CFG17 0x400106d1u
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#define CYREG_B0_P3_U1_CFG18 0x400106d2u
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#define CYREG_B0_P3_U1_CFG19 0x400106d3u
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#define CYREG_B0_P3_U1_CFG20 0x400106d4u
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#define CYREG_B0_P3_U1_CFG21 0x400106d5u
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#define CYREG_B0_P3_U1_CFG22 0x400106d6u
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#define CYREG_B0_P3_U1_CFG23 0x400106d7u
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#define CYREG_B0_P3_U1_CFG24 0x400106d8u
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#define CYREG_B0_P3_U1_CFG25 0x400106d9u
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#define CYREG_B0_P3_U1_CFG26 0x400106dau
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#define CYREG_B0_P3_U1_CFG27 0x400106dbu
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#define CYREG_B0_P3_U1_CFG28 0x400106dcu
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#define CYREG_B0_P3_U1_CFG29 0x400106ddu
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#define CYREG_B0_P3_U1_CFG30 0x400106deu
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#define CYREG_B0_P3_U1_CFG31 0x400106dfu
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#define CYREG_B0_P3_U1_DCFG0 0x400106e0u
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#define CYREG_B0_P3_U1_DCFG1 0x400106e2u
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#define CYREG_B0_P3_U1_DCFG2 0x400106e4u
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#define CYREG_B0_P3_U1_DCFG3 0x400106e6u
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#define CYREG_B0_P3_U1_DCFG4 0x400106e8u
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#define CYREG_B0_P3_U1_DCFG5 0x400106eau
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#define CYREG_B0_P3_U1_DCFG6 0x400106ecu
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#define CYREG_B0_P3_U1_DCFG7 0x400106eeu
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#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u
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#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B0_P4_BASE 0x40010800u
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#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u
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#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u
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#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u
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#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u
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#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u
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#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu
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#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u
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#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u
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#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u
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#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu
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#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u
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#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u
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#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u
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#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu
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#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u
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#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u
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#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u
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#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u
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#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u
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#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au
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#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu
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#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu
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#define CYREG_B0_P4_U0_CFG0 0x40010840u
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#define CYREG_B0_P4_U0_CFG1 0x40010841u
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#define CYREG_B0_P4_U0_CFG2 0x40010842u
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#define CYREG_B0_P4_U0_CFG3 0x40010843u
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#define CYREG_B0_P4_U0_CFG4 0x40010844u
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#define CYREG_B0_P4_U0_CFG5 0x40010845u
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#define CYREG_B0_P4_U0_CFG6 0x40010846u
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#define CYREG_B0_P4_U0_CFG7 0x40010847u
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#define CYREG_B0_P4_U0_CFG8 0x40010848u
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#define CYREG_B0_P4_U0_CFG9 0x40010849u
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#define CYREG_B0_P4_U0_CFG10 0x4001084au
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#define CYREG_B0_P4_U0_CFG11 0x4001084bu
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#define CYREG_B0_P4_U0_CFG12 0x4001084cu
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#define CYREG_B0_P4_U0_CFG13 0x4001084du
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#define CYREG_B0_P4_U0_CFG14 0x4001084eu
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#define CYREG_B0_P4_U0_CFG15 0x4001084fu
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#define CYREG_B0_P4_U0_CFG16 0x40010850u
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#define CYREG_B0_P4_U0_CFG17 0x40010851u
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#define CYREG_B0_P4_U0_CFG18 0x40010852u
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#define CYREG_B0_P4_U0_CFG19 0x40010853u
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#define CYREG_B0_P4_U0_CFG20 0x40010854u
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#define CYREG_B0_P4_U0_CFG21 0x40010855u
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#define CYREG_B0_P4_U0_CFG22 0x40010856u
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#define CYREG_B0_P4_U0_CFG23 0x40010857u
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#define CYREG_B0_P4_U0_CFG24 0x40010858u
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#define CYREG_B0_P4_U0_CFG25 0x40010859u
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#define CYREG_B0_P4_U0_CFG26 0x4001085au
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#define CYREG_B0_P4_U0_CFG27 0x4001085bu
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#define CYREG_B0_P4_U0_CFG28 0x4001085cu
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#define CYREG_B0_P4_U0_CFG29 0x4001085du
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#define CYREG_B0_P4_U0_CFG30 0x4001085eu
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#define CYREG_B0_P4_U0_CFG31 0x4001085fu
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#define CYREG_B0_P4_U0_DCFG0 0x40010860u
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#define CYREG_B0_P4_U0_DCFG1 0x40010862u
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#define CYREG_B0_P4_U0_DCFG2 0x40010864u
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#define CYREG_B0_P4_U0_DCFG3 0x40010866u
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#define CYREG_B0_P4_U0_DCFG4 0x40010868u
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#define CYREG_B0_P4_U0_DCFG5 0x4001086au
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#define CYREG_B0_P4_U0_DCFG6 0x4001086cu
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#define CYREG_B0_P4_U0_DCFG7 0x4001086eu
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#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u
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#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u
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#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u
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#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u
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#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u
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#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu
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#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u
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#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u
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#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u
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#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu
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#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u
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#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u
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#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u
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#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu
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#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u
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#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u
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#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u
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#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u
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#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u
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#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau
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#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu
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#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu
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#define CYREG_B0_P4_U1_CFG0 0x400108c0u
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#define CYREG_B0_P4_U1_CFG1 0x400108c1u
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#define CYREG_B0_P4_U1_CFG2 0x400108c2u
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#define CYREG_B0_P4_U1_CFG3 0x400108c3u
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#define CYREG_B0_P4_U1_CFG4 0x400108c4u
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#define CYREG_B0_P4_U1_CFG5 0x400108c5u
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#define CYREG_B0_P4_U1_CFG6 0x400108c6u
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#define CYREG_B0_P4_U1_CFG7 0x400108c7u
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#define CYREG_B0_P4_U1_CFG8 0x400108c8u
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#define CYREG_B0_P4_U1_CFG9 0x400108c9u
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#define CYREG_B0_P4_U1_CFG10 0x400108cau
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#define CYREG_B0_P4_U1_CFG11 0x400108cbu
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#define CYREG_B0_P4_U1_CFG12 0x400108ccu
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#define CYREG_B0_P4_U1_CFG13 0x400108cdu
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#define CYREG_B0_P4_U1_CFG14 0x400108ceu
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#define CYREG_B0_P4_U1_CFG15 0x400108cfu
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#define CYREG_B0_P4_U1_CFG16 0x400108d0u
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#define CYREG_B0_P4_U1_CFG17 0x400108d1u
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#define CYREG_B0_P4_U1_CFG18 0x400108d2u
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#define CYREG_B0_P4_U1_CFG19 0x400108d3u
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#define CYREG_B0_P4_U1_CFG20 0x400108d4u
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#define CYREG_B0_P4_U1_CFG21 0x400108d5u
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#define CYREG_B0_P4_U1_CFG22 0x400108d6u
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#define CYREG_B0_P4_U1_CFG23 0x400108d7u
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#define CYREG_B0_P4_U1_CFG24 0x400108d8u
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#define CYREG_B0_P4_U1_CFG25 0x400108d9u
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#define CYREG_B0_P4_U1_CFG26 0x400108dau
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#define CYREG_B0_P4_U1_CFG27 0x400108dbu
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#define CYREG_B0_P4_U1_CFG28 0x400108dcu
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#define CYREG_B0_P4_U1_CFG29 0x400108ddu
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#define CYREG_B0_P4_U1_CFG30 0x400108deu
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#define CYREG_B0_P4_U1_CFG31 0x400108dfu
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#define CYREG_B0_P4_U1_DCFG0 0x400108e0u
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#define CYREG_B0_P4_U1_DCFG1 0x400108e2u
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#define CYREG_B0_P4_U1_DCFG2 0x400108e4u
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#define CYREG_B0_P4_U1_DCFG3 0x400108e6u
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#define CYREG_B0_P4_U1_DCFG4 0x400108e8u
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#define CYREG_B0_P4_U1_DCFG5 0x400108eau
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#define CYREG_B0_P4_U1_DCFG6 0x400108ecu
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#define CYREG_B0_P4_U1_DCFG7 0x400108eeu
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#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u
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#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u
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#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u
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#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u
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#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u
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#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u
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#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u
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#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu
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#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u
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#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u
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#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u
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#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu
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#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u
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#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u
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#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u
|
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#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu
|
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#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u
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#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u
|
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#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u
|
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#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u
|
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#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u
|
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#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au
|
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#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu
|
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#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu
|
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#define CYREG_B0_P5_U0_CFG0 0x40010a40u
|
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#define CYREG_B0_P5_U0_CFG1 0x40010a41u
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#define CYREG_B0_P5_U0_CFG2 0x40010a42u
|
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#define CYREG_B0_P5_U0_CFG3 0x40010a43u
|
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#define CYREG_B0_P5_U0_CFG4 0x40010a44u
|
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#define CYREG_B0_P5_U0_CFG5 0x40010a45u
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#define CYREG_B0_P5_U0_CFG6 0x40010a46u
|
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#define CYREG_B0_P5_U0_CFG7 0x40010a47u
|
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#define CYREG_B0_P5_U0_CFG8 0x40010a48u
|
|
#define CYREG_B0_P5_U0_CFG9 0x40010a49u
|
|
#define CYREG_B0_P5_U0_CFG10 0x40010a4au
|
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#define CYREG_B0_P5_U0_CFG11 0x40010a4bu
|
|
#define CYREG_B0_P5_U0_CFG12 0x40010a4cu
|
|
#define CYREG_B0_P5_U0_CFG13 0x40010a4du
|
|
#define CYREG_B0_P5_U0_CFG14 0x40010a4eu
|
|
#define CYREG_B0_P5_U0_CFG15 0x40010a4fu
|
|
#define CYREG_B0_P5_U0_CFG16 0x40010a50u
|
|
#define CYREG_B0_P5_U0_CFG17 0x40010a51u
|
|
#define CYREG_B0_P5_U0_CFG18 0x40010a52u
|
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#define CYREG_B0_P5_U0_CFG19 0x40010a53u
|
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#define CYREG_B0_P5_U0_CFG20 0x40010a54u
|
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#define CYREG_B0_P5_U0_CFG21 0x40010a55u
|
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#define CYREG_B0_P5_U0_CFG22 0x40010a56u
|
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#define CYREG_B0_P5_U0_CFG23 0x40010a57u
|
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#define CYREG_B0_P5_U0_CFG24 0x40010a58u
|
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#define CYREG_B0_P5_U0_CFG25 0x40010a59u
|
|
#define CYREG_B0_P5_U0_CFG26 0x40010a5au
|
|
#define CYREG_B0_P5_U0_CFG27 0x40010a5bu
|
|
#define CYREG_B0_P5_U0_CFG28 0x40010a5cu
|
|
#define CYREG_B0_P5_U0_CFG29 0x40010a5du
|
|
#define CYREG_B0_P5_U0_CFG30 0x40010a5eu
|
|
#define CYREG_B0_P5_U0_CFG31 0x40010a5fu
|
|
#define CYREG_B0_P5_U0_DCFG0 0x40010a60u
|
|
#define CYREG_B0_P5_U0_DCFG1 0x40010a62u
|
|
#define CYREG_B0_P5_U0_DCFG2 0x40010a64u
|
|
#define CYREG_B0_P5_U0_DCFG3 0x40010a66u
|
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#define CYREG_B0_P5_U0_DCFG4 0x40010a68u
|
|
#define CYREG_B0_P5_U0_DCFG5 0x40010a6au
|
|
#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu
|
|
#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu
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#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u
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#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u
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#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u
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#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u
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#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u
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#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu
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#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u
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#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u
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#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u
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#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu
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#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u
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#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u
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#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u
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#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu
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#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u
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#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u
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#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u
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#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u
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#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u
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#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau
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#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu
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#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu
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#define CYREG_B0_P5_U1_CFG0 0x40010ac0u
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#define CYREG_B0_P5_U1_CFG1 0x40010ac1u
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#define CYREG_B0_P5_U1_CFG2 0x40010ac2u
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#define CYREG_B0_P5_U1_CFG3 0x40010ac3u
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#define CYREG_B0_P5_U1_CFG4 0x40010ac4u
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#define CYREG_B0_P5_U1_CFG5 0x40010ac5u
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#define CYREG_B0_P5_U1_CFG6 0x40010ac6u
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#define CYREG_B0_P5_U1_CFG7 0x40010ac7u
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#define CYREG_B0_P5_U1_CFG8 0x40010ac8u
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#define CYREG_B0_P5_U1_CFG9 0x40010ac9u
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#define CYREG_B0_P5_U1_CFG10 0x40010acau
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#define CYREG_B0_P5_U1_CFG11 0x40010acbu
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#define CYREG_B0_P5_U1_CFG12 0x40010accu
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#define CYREG_B0_P5_U1_CFG13 0x40010acdu
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#define CYREG_B0_P5_U1_CFG14 0x40010aceu
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#define CYREG_B0_P5_U1_CFG15 0x40010acfu
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#define CYREG_B0_P5_U1_CFG16 0x40010ad0u
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#define CYREG_B0_P5_U1_CFG17 0x40010ad1u
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#define CYREG_B0_P5_U1_CFG18 0x40010ad2u
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#define CYREG_B0_P5_U1_CFG19 0x40010ad3u
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#define CYREG_B0_P5_U1_CFG20 0x40010ad4u
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#define CYREG_B0_P5_U1_CFG21 0x40010ad5u
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#define CYREG_B0_P5_U1_CFG22 0x40010ad6u
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#define CYREG_B0_P5_U1_CFG23 0x40010ad7u
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#define CYREG_B0_P5_U1_CFG24 0x40010ad8u
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#define CYREG_B0_P5_U1_CFG25 0x40010ad9u
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#define CYREG_B0_P5_U1_CFG26 0x40010adau
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#define CYREG_B0_P5_U1_CFG27 0x40010adbu
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#define CYREG_B0_P5_U1_CFG28 0x40010adcu
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#define CYREG_B0_P5_U1_CFG29 0x40010addu
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#define CYREG_B0_P5_U1_CFG30 0x40010adeu
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#define CYREG_B0_P5_U1_CFG31 0x40010adfu
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#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u
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#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u
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#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u
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#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u
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#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u
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#define CYREG_B0_P5_U1_DCFG5 0x40010aeau
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#define CYREG_B0_P5_U1_DCFG6 0x40010aecu
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#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu
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#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u
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#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u
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#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u
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#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u
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#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u
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#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u
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#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u
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#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu
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#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u
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#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u
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#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u
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#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu
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#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u
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#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u
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#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u
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#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu
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#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u
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#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u
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#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u
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#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u
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#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u
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#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au
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#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu
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#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu
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#define CYREG_B0_P6_U0_CFG0 0x40010c40u
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#define CYREG_B0_P6_U0_CFG1 0x40010c41u
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#define CYREG_B0_P6_U0_CFG2 0x40010c42u
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#define CYREG_B0_P6_U0_CFG3 0x40010c43u
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#define CYREG_B0_P6_U0_CFG4 0x40010c44u
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#define CYREG_B0_P6_U0_CFG5 0x40010c45u
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#define CYREG_B0_P6_U0_CFG6 0x40010c46u
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#define CYREG_B0_P6_U0_CFG7 0x40010c47u
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#define CYREG_B0_P6_U0_CFG8 0x40010c48u
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#define CYREG_B0_P6_U0_CFG9 0x40010c49u
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#define CYREG_B0_P6_U0_CFG10 0x40010c4au
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#define CYREG_B0_P6_U0_CFG11 0x40010c4bu
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#define CYREG_B0_P6_U0_CFG12 0x40010c4cu
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#define CYREG_B0_P6_U0_CFG13 0x40010c4du
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#define CYREG_B0_P6_U0_CFG14 0x40010c4eu
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#define CYREG_B0_P6_U0_CFG15 0x40010c4fu
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#define CYREG_B0_P6_U0_CFG16 0x40010c50u
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#define CYREG_B0_P6_U0_CFG17 0x40010c51u
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#define CYREG_B0_P6_U0_CFG18 0x40010c52u
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#define CYREG_B0_P6_U0_CFG19 0x40010c53u
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#define CYREG_B0_P6_U0_CFG20 0x40010c54u
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#define CYREG_B0_P6_U0_CFG21 0x40010c55u
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#define CYREG_B0_P6_U0_CFG22 0x40010c56u
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#define CYREG_B0_P6_U0_CFG23 0x40010c57u
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#define CYREG_B0_P6_U0_CFG24 0x40010c58u
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#define CYREG_B0_P6_U0_CFG25 0x40010c59u
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#define CYREG_B0_P6_U0_CFG26 0x40010c5au
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#define CYREG_B0_P6_U0_CFG27 0x40010c5bu
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#define CYREG_B0_P6_U0_CFG28 0x40010c5cu
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#define CYREG_B0_P6_U0_CFG29 0x40010c5du
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#define CYREG_B0_P6_U0_CFG30 0x40010c5eu
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#define CYREG_B0_P6_U0_CFG31 0x40010c5fu
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#define CYREG_B0_P6_U0_DCFG0 0x40010c60u
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#define CYREG_B0_P6_U0_DCFG1 0x40010c62u
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#define CYREG_B0_P6_U0_DCFG2 0x40010c64u
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#define CYREG_B0_P6_U0_DCFG3 0x40010c66u
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#define CYREG_B0_P6_U0_DCFG4 0x40010c68u
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#define CYREG_B0_P6_U0_DCFG5 0x40010c6au
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#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu
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#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu
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#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u
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#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u
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#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u
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#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u
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#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u
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#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu
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#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u
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#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u
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#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u
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#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu
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#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u
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#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u
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#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u
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#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu
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#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u
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#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u
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#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u
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#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u
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#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u
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#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau
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#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu
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#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu
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#define CYREG_B0_P6_U1_CFG0 0x40010cc0u
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#define CYREG_B0_P6_U1_CFG1 0x40010cc1u
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#define CYREG_B0_P6_U1_CFG2 0x40010cc2u
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#define CYREG_B0_P6_U1_CFG3 0x40010cc3u
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#define CYREG_B0_P6_U1_CFG4 0x40010cc4u
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#define CYREG_B0_P6_U1_CFG5 0x40010cc5u
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#define CYREG_B0_P6_U1_CFG6 0x40010cc6u
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#define CYREG_B0_P6_U1_CFG7 0x40010cc7u
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#define CYREG_B0_P6_U1_CFG8 0x40010cc8u
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#define CYREG_B0_P6_U1_CFG9 0x40010cc9u
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#define CYREG_B0_P6_U1_CFG10 0x40010ccau
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#define CYREG_B0_P6_U1_CFG11 0x40010ccbu
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#define CYREG_B0_P6_U1_CFG12 0x40010cccu
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#define CYREG_B0_P6_U1_CFG13 0x40010ccdu
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#define CYREG_B0_P6_U1_CFG14 0x40010cceu
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#define CYREG_B0_P6_U1_CFG15 0x40010ccfu
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#define CYREG_B0_P6_U1_CFG16 0x40010cd0u
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#define CYREG_B0_P6_U1_CFG17 0x40010cd1u
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#define CYREG_B0_P6_U1_CFG18 0x40010cd2u
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#define CYREG_B0_P6_U1_CFG19 0x40010cd3u
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#define CYREG_B0_P6_U1_CFG20 0x40010cd4u
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#define CYREG_B0_P6_U1_CFG21 0x40010cd5u
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#define CYREG_B0_P6_U1_CFG22 0x40010cd6u
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#define CYREG_B0_P6_U1_CFG23 0x40010cd7u
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#define CYREG_B0_P6_U1_CFG24 0x40010cd8u
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#define CYREG_B0_P6_U1_CFG25 0x40010cd9u
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#define CYREG_B0_P6_U1_CFG26 0x40010cdau
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#define CYREG_B0_P6_U1_CFG27 0x40010cdbu
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#define CYREG_B0_P6_U1_CFG28 0x40010cdcu
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#define CYREG_B0_P6_U1_CFG29 0x40010cddu
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#define CYREG_B0_P6_U1_CFG30 0x40010cdeu
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#define CYREG_B0_P6_U1_CFG31 0x40010cdfu
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#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u
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#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u
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#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u
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#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u
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#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u
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#define CYREG_B0_P6_U1_DCFG5 0x40010ceau
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#define CYREG_B0_P6_U1_DCFG6 0x40010cecu
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#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu
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#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u
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#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u
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#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu
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#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u
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#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u
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#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u
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#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u
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#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u
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#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu
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#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u
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#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u
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#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u
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#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu
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#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u
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#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u
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#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u
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#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu
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#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u
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#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u
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#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u
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#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u
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#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u
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#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au
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#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu
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#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu
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#define CYREG_B0_P7_U0_CFG0 0x40010e40u
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#define CYREG_B0_P7_U0_CFG1 0x40010e41u
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#define CYREG_B0_P7_U0_CFG2 0x40010e42u
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#define CYREG_B0_P7_U0_CFG3 0x40010e43u
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#define CYREG_B0_P7_U0_CFG4 0x40010e44u
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#define CYREG_B0_P7_U0_CFG5 0x40010e45u
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#define CYREG_B0_P7_U0_CFG6 0x40010e46u
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#define CYREG_B0_P7_U0_CFG7 0x40010e47u
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#define CYREG_B0_P7_U0_CFG8 0x40010e48u
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#define CYREG_B0_P7_U0_CFG9 0x40010e49u
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#define CYREG_B0_P7_U0_CFG10 0x40010e4au
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#define CYREG_B0_P7_U0_CFG11 0x40010e4bu
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#define CYREG_B0_P7_U0_CFG12 0x40010e4cu
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#define CYREG_B0_P7_U0_CFG13 0x40010e4du
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#define CYREG_B0_P7_U0_CFG14 0x40010e4eu
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#define CYREG_B0_P7_U0_CFG15 0x40010e4fu
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#define CYREG_B0_P7_U0_CFG16 0x40010e50u
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#define CYREG_B0_P7_U0_CFG17 0x40010e51u
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#define CYREG_B0_P7_U0_CFG18 0x40010e52u
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#define CYREG_B0_P7_U0_CFG19 0x40010e53u
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#define CYREG_B0_P7_U0_CFG20 0x40010e54u
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#define CYREG_B0_P7_U0_CFG21 0x40010e55u
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#define CYREG_B0_P7_U0_CFG22 0x40010e56u
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#define CYREG_B0_P7_U0_CFG23 0x40010e57u
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#define CYREG_B0_P7_U0_CFG24 0x40010e58u
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#define CYREG_B0_P7_U0_CFG25 0x40010e59u
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#define CYREG_B0_P7_U0_CFG26 0x40010e5au
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#define CYREG_B0_P7_U0_CFG27 0x40010e5bu
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|
#define CYREG_B0_P7_U0_CFG28 0x40010e5cu
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#define CYREG_B0_P7_U0_CFG29 0x40010e5du
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#define CYREG_B0_P7_U0_CFG30 0x40010e5eu
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#define CYREG_B0_P7_U0_CFG31 0x40010e5fu
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#define CYREG_B0_P7_U0_DCFG0 0x40010e60u
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#define CYREG_B0_P7_U0_DCFG1 0x40010e62u
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#define CYREG_B0_P7_U0_DCFG2 0x40010e64u
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#define CYREG_B0_P7_U0_DCFG3 0x40010e66u
|
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#define CYREG_B0_P7_U0_DCFG4 0x40010e68u
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#define CYREG_B0_P7_U0_DCFG5 0x40010e6au
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#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu
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#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu
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#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u
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#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u
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#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u
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#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u
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#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u
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#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu
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#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u
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#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u
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#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u
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#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu
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#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u
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#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u
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#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u
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#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu
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#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u
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#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u
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#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u
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#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u
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#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u
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#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau
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#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu
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#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu
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#define CYREG_B0_P7_U1_CFG0 0x40010ec0u
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#define CYREG_B0_P7_U1_CFG1 0x40010ec1u
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#define CYREG_B0_P7_U1_CFG2 0x40010ec2u
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#define CYREG_B0_P7_U1_CFG3 0x40010ec3u
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#define CYREG_B0_P7_U1_CFG4 0x40010ec4u
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#define CYREG_B0_P7_U1_CFG5 0x40010ec5u
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#define CYREG_B0_P7_U1_CFG6 0x40010ec6u
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#define CYREG_B0_P7_U1_CFG7 0x40010ec7u
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#define CYREG_B0_P7_U1_CFG8 0x40010ec8u
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#define CYREG_B0_P7_U1_CFG9 0x40010ec9u
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#define CYREG_B0_P7_U1_CFG10 0x40010ecau
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#define CYREG_B0_P7_U1_CFG11 0x40010ecbu
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#define CYREG_B0_P7_U1_CFG12 0x40010eccu
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#define CYREG_B0_P7_U1_CFG13 0x40010ecdu
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#define CYREG_B0_P7_U1_CFG14 0x40010eceu
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#define CYREG_B0_P7_U1_CFG15 0x40010ecfu
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#define CYREG_B0_P7_U1_CFG16 0x40010ed0u
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#define CYREG_B0_P7_U1_CFG17 0x40010ed1u
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#define CYREG_B0_P7_U1_CFG18 0x40010ed2u
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#define CYREG_B0_P7_U1_CFG19 0x40010ed3u
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#define CYREG_B0_P7_U1_CFG20 0x40010ed4u
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#define CYREG_B0_P7_U1_CFG21 0x40010ed5u
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#define CYREG_B0_P7_U1_CFG22 0x40010ed6u
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#define CYREG_B0_P7_U1_CFG23 0x40010ed7u
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#define CYREG_B0_P7_U1_CFG24 0x40010ed8u
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#define CYREG_B0_P7_U1_CFG25 0x40010ed9u
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#define CYREG_B0_P7_U1_CFG26 0x40010edau
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#define CYREG_B0_P7_U1_CFG27 0x40010edbu
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#define CYREG_B0_P7_U1_CFG28 0x40010edcu
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#define CYREG_B0_P7_U1_CFG29 0x40010eddu
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#define CYREG_B0_P7_U1_CFG30 0x40010edeu
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#define CYREG_B0_P7_U1_CFG31 0x40010edfu
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#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u
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#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u
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#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u
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#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u
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#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u
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#define CYREG_B0_P7_U1_DCFG5 0x40010eeau
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#define CYREG_B0_P7_U1_DCFG6 0x40010eecu
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#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu
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#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u
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#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B1_BASE 0x40011000u
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#define CYDEV_UCFG_B1_SIZE 0x00000fefu
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#define CYDEV_UCFG_B1_P2_BASE 0x40011400u
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#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu
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#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u
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#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u
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#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u
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#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u
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#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u
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#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu
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#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u
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#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u
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#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u
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#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu
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#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u
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#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u
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#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u
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#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu
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#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u
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#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u
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#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u
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#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u
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#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u
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#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au
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#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu
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#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu
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#define CYREG_B1_P2_U0_CFG0 0x40011440u
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#define CYREG_B1_P2_U0_CFG1 0x40011441u
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#define CYREG_B1_P2_U0_CFG2 0x40011442u
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#define CYREG_B1_P2_U0_CFG3 0x40011443u
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#define CYREG_B1_P2_U0_CFG4 0x40011444u
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#define CYREG_B1_P2_U0_CFG5 0x40011445u
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#define CYREG_B1_P2_U0_CFG6 0x40011446u
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#define CYREG_B1_P2_U0_CFG7 0x40011447u
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#define CYREG_B1_P2_U0_CFG8 0x40011448u
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#define CYREG_B1_P2_U0_CFG9 0x40011449u
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#define CYREG_B1_P2_U0_CFG10 0x4001144au
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#define CYREG_B1_P2_U0_CFG11 0x4001144bu
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#define CYREG_B1_P2_U0_CFG12 0x4001144cu
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#define CYREG_B1_P2_U0_CFG13 0x4001144du
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#define CYREG_B1_P2_U0_CFG14 0x4001144eu
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#define CYREG_B1_P2_U0_CFG15 0x4001144fu
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#define CYREG_B1_P2_U0_CFG16 0x40011450u
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#define CYREG_B1_P2_U0_CFG17 0x40011451u
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#define CYREG_B1_P2_U0_CFG18 0x40011452u
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#define CYREG_B1_P2_U0_CFG19 0x40011453u
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#define CYREG_B1_P2_U0_CFG20 0x40011454u
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#define CYREG_B1_P2_U0_CFG21 0x40011455u
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#define CYREG_B1_P2_U0_CFG22 0x40011456u
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#define CYREG_B1_P2_U0_CFG23 0x40011457u
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#define CYREG_B1_P2_U0_CFG24 0x40011458u
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#define CYREG_B1_P2_U0_CFG25 0x40011459u
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#define CYREG_B1_P2_U0_CFG26 0x4001145au
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#define CYREG_B1_P2_U0_CFG27 0x4001145bu
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#define CYREG_B1_P2_U0_CFG28 0x4001145cu
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#define CYREG_B1_P2_U0_CFG29 0x4001145du
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#define CYREG_B1_P2_U0_CFG30 0x4001145eu
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#define CYREG_B1_P2_U0_CFG31 0x4001145fu
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#define CYREG_B1_P2_U0_DCFG0 0x40011460u
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#define CYREG_B1_P2_U0_DCFG1 0x40011462u
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#define CYREG_B1_P2_U0_DCFG2 0x40011464u
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#define CYREG_B1_P2_U0_DCFG3 0x40011466u
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#define CYREG_B1_P2_U0_DCFG4 0x40011468u
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#define CYREG_B1_P2_U0_DCFG5 0x4001146au
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#define CYREG_B1_P2_U0_DCFG6 0x4001146cu
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#define CYREG_B1_P2_U0_DCFG7 0x4001146eu
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#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u
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#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u
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#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u
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#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u
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#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u
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#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu
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#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u
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#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u
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#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u
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#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu
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#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u
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#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u
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#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u
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#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu
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#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u
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#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u
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#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u
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#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u
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#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u
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#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau
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#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu
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#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu
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#define CYREG_B1_P2_U1_CFG0 0x400114c0u
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#define CYREG_B1_P2_U1_CFG1 0x400114c1u
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#define CYREG_B1_P2_U1_CFG2 0x400114c2u
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#define CYREG_B1_P2_U1_CFG3 0x400114c3u
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#define CYREG_B1_P2_U1_CFG4 0x400114c4u
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#define CYREG_B1_P2_U1_CFG5 0x400114c5u
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#define CYREG_B1_P2_U1_CFG6 0x400114c6u
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#define CYREG_B1_P2_U1_CFG7 0x400114c7u
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#define CYREG_B1_P2_U1_CFG8 0x400114c8u
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#define CYREG_B1_P2_U1_CFG9 0x400114c9u
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#define CYREG_B1_P2_U1_CFG10 0x400114cau
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#define CYREG_B1_P2_U1_CFG11 0x400114cbu
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#define CYREG_B1_P2_U1_CFG12 0x400114ccu
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#define CYREG_B1_P2_U1_CFG13 0x400114cdu
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#define CYREG_B1_P2_U1_CFG14 0x400114ceu
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#define CYREG_B1_P2_U1_CFG15 0x400114cfu
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#define CYREG_B1_P2_U1_CFG16 0x400114d0u
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#define CYREG_B1_P2_U1_CFG17 0x400114d1u
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#define CYREG_B1_P2_U1_CFG18 0x400114d2u
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#define CYREG_B1_P2_U1_CFG19 0x400114d3u
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#define CYREG_B1_P2_U1_CFG20 0x400114d4u
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#define CYREG_B1_P2_U1_CFG21 0x400114d5u
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#define CYREG_B1_P2_U1_CFG22 0x400114d6u
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#define CYREG_B1_P2_U1_CFG23 0x400114d7u
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#define CYREG_B1_P2_U1_CFG24 0x400114d8u
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#define CYREG_B1_P2_U1_CFG25 0x400114d9u
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#define CYREG_B1_P2_U1_CFG26 0x400114dau
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#define CYREG_B1_P2_U1_CFG27 0x400114dbu
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#define CYREG_B1_P2_U1_CFG28 0x400114dcu
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#define CYREG_B1_P2_U1_CFG29 0x400114ddu
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#define CYREG_B1_P2_U1_CFG30 0x400114deu
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#define CYREG_B1_P2_U1_CFG31 0x400114dfu
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#define CYREG_B1_P2_U1_DCFG0 0x400114e0u
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#define CYREG_B1_P2_U1_DCFG1 0x400114e2u
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#define CYREG_B1_P2_U1_DCFG2 0x400114e4u
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#define CYREG_B1_P2_U1_DCFG3 0x400114e6u
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#define CYREG_B1_P2_U1_DCFG4 0x400114e8u
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#define CYREG_B1_P2_U1_DCFG5 0x400114eau
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#define CYREG_B1_P2_U1_DCFG6 0x400114ecu
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#define CYREG_B1_P2_U1_DCFG7 0x400114eeu
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#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u
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#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B1_P3_BASE 0x40011600u
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#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu
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#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u
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#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u
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#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u
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#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u
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#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u
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#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu
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#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u
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#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u
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#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u
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#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu
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#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u
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#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u
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#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u
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#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu
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#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u
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#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u
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#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u
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#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u
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#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u
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#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au
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#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu
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#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu
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#define CYREG_B1_P3_U0_CFG0 0x40011640u
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#define CYREG_B1_P3_U0_CFG1 0x40011641u
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#define CYREG_B1_P3_U0_CFG2 0x40011642u
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#define CYREG_B1_P3_U0_CFG3 0x40011643u
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#define CYREG_B1_P3_U0_CFG4 0x40011644u
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#define CYREG_B1_P3_U0_CFG5 0x40011645u
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#define CYREG_B1_P3_U0_CFG6 0x40011646u
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#define CYREG_B1_P3_U0_CFG7 0x40011647u
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#define CYREG_B1_P3_U0_CFG8 0x40011648u
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#define CYREG_B1_P3_U0_CFG9 0x40011649u
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#define CYREG_B1_P3_U0_CFG10 0x4001164au
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#define CYREG_B1_P3_U0_CFG11 0x4001164bu
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#define CYREG_B1_P3_U0_CFG12 0x4001164cu
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#define CYREG_B1_P3_U0_CFG13 0x4001164du
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#define CYREG_B1_P3_U0_CFG14 0x4001164eu
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#define CYREG_B1_P3_U0_CFG15 0x4001164fu
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#define CYREG_B1_P3_U0_CFG16 0x40011650u
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#define CYREG_B1_P3_U0_CFG17 0x40011651u
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#define CYREG_B1_P3_U0_CFG18 0x40011652u
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#define CYREG_B1_P3_U0_CFG19 0x40011653u
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#define CYREG_B1_P3_U0_CFG20 0x40011654u
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#define CYREG_B1_P3_U0_CFG21 0x40011655u
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#define CYREG_B1_P3_U0_CFG22 0x40011656u
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#define CYREG_B1_P3_U0_CFG23 0x40011657u
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#define CYREG_B1_P3_U0_CFG24 0x40011658u
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#define CYREG_B1_P3_U0_CFG25 0x40011659u
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#define CYREG_B1_P3_U0_CFG26 0x4001165au
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#define CYREG_B1_P3_U0_CFG27 0x4001165bu
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#define CYREG_B1_P3_U0_CFG28 0x4001165cu
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#define CYREG_B1_P3_U0_CFG29 0x4001165du
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#define CYREG_B1_P3_U0_CFG30 0x4001165eu
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#define CYREG_B1_P3_U0_CFG31 0x4001165fu
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#define CYREG_B1_P3_U0_DCFG0 0x40011660u
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#define CYREG_B1_P3_U0_DCFG1 0x40011662u
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#define CYREG_B1_P3_U0_DCFG2 0x40011664u
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#define CYREG_B1_P3_U0_DCFG3 0x40011666u
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#define CYREG_B1_P3_U0_DCFG4 0x40011668u
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#define CYREG_B1_P3_U0_DCFG5 0x4001166au
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#define CYREG_B1_P3_U0_DCFG6 0x4001166cu
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#define CYREG_B1_P3_U0_DCFG7 0x4001166eu
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#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u
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#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u
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#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u
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#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u
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#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u
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#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu
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#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u
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#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u
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#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u
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#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu
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#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u
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#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u
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#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u
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#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu
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#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u
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#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u
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#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u
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#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u
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#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u
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#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau
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#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu
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#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu
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#define CYREG_B1_P3_U1_CFG0 0x400116c0u
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#define CYREG_B1_P3_U1_CFG1 0x400116c1u
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#define CYREG_B1_P3_U1_CFG2 0x400116c2u
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#define CYREG_B1_P3_U1_CFG3 0x400116c3u
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#define CYREG_B1_P3_U1_CFG4 0x400116c4u
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#define CYREG_B1_P3_U1_CFG5 0x400116c5u
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#define CYREG_B1_P3_U1_CFG6 0x400116c6u
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#define CYREG_B1_P3_U1_CFG7 0x400116c7u
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#define CYREG_B1_P3_U1_CFG8 0x400116c8u
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#define CYREG_B1_P3_U1_CFG9 0x400116c9u
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#define CYREG_B1_P3_U1_CFG10 0x400116cau
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#define CYREG_B1_P3_U1_CFG11 0x400116cbu
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#define CYREG_B1_P3_U1_CFG12 0x400116ccu
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#define CYREG_B1_P3_U1_CFG13 0x400116cdu
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#define CYREG_B1_P3_U1_CFG14 0x400116ceu
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#define CYREG_B1_P3_U1_CFG15 0x400116cfu
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#define CYREG_B1_P3_U1_CFG16 0x400116d0u
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#define CYREG_B1_P3_U1_CFG17 0x400116d1u
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#define CYREG_B1_P3_U1_CFG18 0x400116d2u
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#define CYREG_B1_P3_U1_CFG19 0x400116d3u
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#define CYREG_B1_P3_U1_CFG20 0x400116d4u
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#define CYREG_B1_P3_U1_CFG21 0x400116d5u
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#define CYREG_B1_P3_U1_CFG22 0x400116d6u
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#define CYREG_B1_P3_U1_CFG23 0x400116d7u
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#define CYREG_B1_P3_U1_CFG24 0x400116d8u
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#define CYREG_B1_P3_U1_CFG25 0x400116d9u
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#define CYREG_B1_P3_U1_CFG26 0x400116dau
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#define CYREG_B1_P3_U1_CFG27 0x400116dbu
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#define CYREG_B1_P3_U1_CFG28 0x400116dcu
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#define CYREG_B1_P3_U1_CFG29 0x400116ddu
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#define CYREG_B1_P3_U1_CFG30 0x400116deu
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#define CYREG_B1_P3_U1_CFG31 0x400116dfu
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#define CYREG_B1_P3_U1_DCFG0 0x400116e0u
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#define CYREG_B1_P3_U1_DCFG1 0x400116e2u
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#define CYREG_B1_P3_U1_DCFG2 0x400116e4u
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#define CYREG_B1_P3_U1_DCFG3 0x400116e6u
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#define CYREG_B1_P3_U1_DCFG4 0x400116e8u
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#define CYREG_B1_P3_U1_DCFG5 0x400116eau
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#define CYREG_B1_P3_U1_DCFG6 0x400116ecu
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#define CYREG_B1_P3_U1_DCFG7 0x400116eeu
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#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u
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#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B1_P4_BASE 0x40011800u
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#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu
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#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u
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#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u
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#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u
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#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u
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#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u
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#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu
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#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u
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#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u
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#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u
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#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu
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#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u
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#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u
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#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u
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#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu
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#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u
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#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u
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#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u
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#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u
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#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u
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#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au
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#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu
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#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu
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#define CYREG_B1_P4_U0_CFG0 0x40011840u
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#define CYREG_B1_P4_U0_CFG1 0x40011841u
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#define CYREG_B1_P4_U0_CFG2 0x40011842u
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#define CYREG_B1_P4_U0_CFG3 0x40011843u
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#define CYREG_B1_P4_U0_CFG4 0x40011844u
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#define CYREG_B1_P4_U0_CFG5 0x40011845u
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#define CYREG_B1_P4_U0_CFG6 0x40011846u
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#define CYREG_B1_P4_U0_CFG7 0x40011847u
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#define CYREG_B1_P4_U0_CFG8 0x40011848u
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#define CYREG_B1_P4_U0_CFG9 0x40011849u
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#define CYREG_B1_P4_U0_CFG10 0x4001184au
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#define CYREG_B1_P4_U0_CFG11 0x4001184bu
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#define CYREG_B1_P4_U0_CFG12 0x4001184cu
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#define CYREG_B1_P4_U0_CFG13 0x4001184du
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#define CYREG_B1_P4_U0_CFG14 0x4001184eu
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#define CYREG_B1_P4_U0_CFG15 0x4001184fu
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#define CYREG_B1_P4_U0_CFG16 0x40011850u
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#define CYREG_B1_P4_U0_CFG17 0x40011851u
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#define CYREG_B1_P4_U0_CFG18 0x40011852u
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#define CYREG_B1_P4_U0_CFG19 0x40011853u
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#define CYREG_B1_P4_U0_CFG20 0x40011854u
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#define CYREG_B1_P4_U0_CFG21 0x40011855u
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#define CYREG_B1_P4_U0_CFG22 0x40011856u
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#define CYREG_B1_P4_U0_CFG23 0x40011857u
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#define CYREG_B1_P4_U0_CFG24 0x40011858u
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#define CYREG_B1_P4_U0_CFG25 0x40011859u
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#define CYREG_B1_P4_U0_CFG26 0x4001185au
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#define CYREG_B1_P4_U0_CFG27 0x4001185bu
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#define CYREG_B1_P4_U0_CFG28 0x4001185cu
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#define CYREG_B1_P4_U0_CFG29 0x4001185du
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#define CYREG_B1_P4_U0_CFG30 0x4001185eu
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#define CYREG_B1_P4_U0_CFG31 0x4001185fu
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#define CYREG_B1_P4_U0_DCFG0 0x40011860u
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#define CYREG_B1_P4_U0_DCFG1 0x40011862u
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#define CYREG_B1_P4_U0_DCFG2 0x40011864u
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#define CYREG_B1_P4_U0_DCFG3 0x40011866u
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#define CYREG_B1_P4_U0_DCFG4 0x40011868u
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#define CYREG_B1_P4_U0_DCFG5 0x4001186au
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#define CYREG_B1_P4_U0_DCFG6 0x4001186cu
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#define CYREG_B1_P4_U0_DCFG7 0x4001186eu
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#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u
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#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u
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#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u
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#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u
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#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u
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#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu
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#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u
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#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u
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#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u
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#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu
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#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u
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#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u
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#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u
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#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu
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#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u
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#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u
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#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u
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#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u
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#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u
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#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau
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#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu
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#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu
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#define CYREG_B1_P4_U1_CFG0 0x400118c0u
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#define CYREG_B1_P4_U1_CFG1 0x400118c1u
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#define CYREG_B1_P4_U1_CFG2 0x400118c2u
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#define CYREG_B1_P4_U1_CFG3 0x400118c3u
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#define CYREG_B1_P4_U1_CFG4 0x400118c4u
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#define CYREG_B1_P4_U1_CFG5 0x400118c5u
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#define CYREG_B1_P4_U1_CFG6 0x400118c6u
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#define CYREG_B1_P4_U1_CFG7 0x400118c7u
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#define CYREG_B1_P4_U1_CFG8 0x400118c8u
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#define CYREG_B1_P4_U1_CFG9 0x400118c9u
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#define CYREG_B1_P4_U1_CFG10 0x400118cau
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#define CYREG_B1_P4_U1_CFG11 0x400118cbu
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#define CYREG_B1_P4_U1_CFG12 0x400118ccu
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#define CYREG_B1_P4_U1_CFG13 0x400118cdu
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#define CYREG_B1_P4_U1_CFG14 0x400118ceu
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#define CYREG_B1_P4_U1_CFG15 0x400118cfu
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#define CYREG_B1_P4_U1_CFG16 0x400118d0u
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#define CYREG_B1_P4_U1_CFG17 0x400118d1u
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#define CYREG_B1_P4_U1_CFG18 0x400118d2u
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#define CYREG_B1_P4_U1_CFG19 0x400118d3u
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#define CYREG_B1_P4_U1_CFG20 0x400118d4u
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#define CYREG_B1_P4_U1_CFG21 0x400118d5u
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#define CYREG_B1_P4_U1_CFG22 0x400118d6u
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#define CYREG_B1_P4_U1_CFG23 0x400118d7u
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#define CYREG_B1_P4_U1_CFG24 0x400118d8u
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#define CYREG_B1_P4_U1_CFG25 0x400118d9u
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#define CYREG_B1_P4_U1_CFG26 0x400118dau
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#define CYREG_B1_P4_U1_CFG27 0x400118dbu
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#define CYREG_B1_P4_U1_CFG28 0x400118dcu
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#define CYREG_B1_P4_U1_CFG29 0x400118ddu
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#define CYREG_B1_P4_U1_CFG30 0x400118deu
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#define CYREG_B1_P4_U1_CFG31 0x400118dfu
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#define CYREG_B1_P4_U1_DCFG0 0x400118e0u
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#define CYREG_B1_P4_U1_DCFG1 0x400118e2u
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#define CYREG_B1_P4_U1_DCFG2 0x400118e4u
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#define CYREG_B1_P4_U1_DCFG3 0x400118e6u
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#define CYREG_B1_P4_U1_DCFG4 0x400118e8u
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#define CYREG_B1_P4_U1_DCFG5 0x400118eau
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#define CYREG_B1_P4_U1_DCFG6 0x400118ecu
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#define CYREG_B1_P4_U1_DCFG7 0x400118eeu
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#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u
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#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u
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#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu
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#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u
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#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u
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#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u
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#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u
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#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u
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#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu
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#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u
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#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u
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#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u
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#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu
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#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u
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#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u
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#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u
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#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu
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#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u
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#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u
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#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u
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#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u
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#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u
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#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au
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#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu
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#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu
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#define CYREG_B1_P5_U0_CFG0 0x40011a40u
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#define CYREG_B1_P5_U0_CFG1 0x40011a41u
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#define CYREG_B1_P5_U0_CFG2 0x40011a42u
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#define CYREG_B1_P5_U0_CFG3 0x40011a43u
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#define CYREG_B1_P5_U0_CFG4 0x40011a44u
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#define CYREG_B1_P5_U0_CFG5 0x40011a45u
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#define CYREG_B1_P5_U0_CFG6 0x40011a46u
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#define CYREG_B1_P5_U0_CFG7 0x40011a47u
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#define CYREG_B1_P5_U0_CFG8 0x40011a48u
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#define CYREG_B1_P5_U0_CFG9 0x40011a49u
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#define CYREG_B1_P5_U0_CFG10 0x40011a4au
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#define CYREG_B1_P5_U0_CFG11 0x40011a4bu
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#define CYREG_B1_P5_U0_CFG12 0x40011a4cu
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#define CYREG_B1_P5_U0_CFG13 0x40011a4du
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#define CYREG_B1_P5_U0_CFG14 0x40011a4eu
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#define CYREG_B1_P5_U0_CFG15 0x40011a4fu
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#define CYREG_B1_P5_U0_CFG16 0x40011a50u
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#define CYREG_B1_P5_U0_CFG17 0x40011a51u
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#define CYREG_B1_P5_U0_CFG18 0x40011a52u
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#define CYREG_B1_P5_U0_CFG19 0x40011a53u
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#define CYREG_B1_P5_U0_CFG20 0x40011a54u
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#define CYREG_B1_P5_U0_CFG21 0x40011a55u
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#define CYREG_B1_P5_U0_CFG22 0x40011a56u
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#define CYREG_B1_P5_U0_CFG23 0x40011a57u
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#define CYREG_B1_P5_U0_CFG24 0x40011a58u
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#define CYREG_B1_P5_U0_CFG25 0x40011a59u
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#define CYREG_B1_P5_U0_CFG26 0x40011a5au
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#define CYREG_B1_P5_U0_CFG27 0x40011a5bu
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#define CYREG_B1_P5_U0_CFG28 0x40011a5cu
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#define CYREG_B1_P5_U0_CFG29 0x40011a5du
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#define CYREG_B1_P5_U0_CFG30 0x40011a5eu
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#define CYREG_B1_P5_U0_CFG31 0x40011a5fu
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#define CYREG_B1_P5_U0_DCFG0 0x40011a60u
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#define CYREG_B1_P5_U0_DCFG1 0x40011a62u
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#define CYREG_B1_P5_U0_DCFG2 0x40011a64u
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#define CYREG_B1_P5_U0_DCFG3 0x40011a66u
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#define CYREG_B1_P5_U0_DCFG4 0x40011a68u
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#define CYREG_B1_P5_U0_DCFG5 0x40011a6au
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#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu
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#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu
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#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u
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#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u
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#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u
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#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u
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#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u
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#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu
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#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u
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#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u
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#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u
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#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu
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#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u
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#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u
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#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u
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#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu
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#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u
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#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u
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#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u
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#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u
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#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u
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#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau
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#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu
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#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu
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#define CYREG_B1_P5_U1_CFG0 0x40011ac0u
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#define CYREG_B1_P5_U1_CFG1 0x40011ac1u
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#define CYREG_B1_P5_U1_CFG2 0x40011ac2u
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#define CYREG_B1_P5_U1_CFG3 0x40011ac3u
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#define CYREG_B1_P5_U1_CFG4 0x40011ac4u
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#define CYREG_B1_P5_U1_CFG5 0x40011ac5u
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#define CYREG_B1_P5_U1_CFG6 0x40011ac6u
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#define CYREG_B1_P5_U1_CFG7 0x40011ac7u
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#define CYREG_B1_P5_U1_CFG8 0x40011ac8u
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#define CYREG_B1_P5_U1_CFG9 0x40011ac9u
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#define CYREG_B1_P5_U1_CFG10 0x40011acau
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#define CYREG_B1_P5_U1_CFG11 0x40011acbu
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#define CYREG_B1_P5_U1_CFG12 0x40011accu
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#define CYREG_B1_P5_U1_CFG13 0x40011acdu
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#define CYREG_B1_P5_U1_CFG14 0x40011aceu
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#define CYREG_B1_P5_U1_CFG15 0x40011acfu
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#define CYREG_B1_P5_U1_CFG16 0x40011ad0u
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#define CYREG_B1_P5_U1_CFG17 0x40011ad1u
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#define CYREG_B1_P5_U1_CFG18 0x40011ad2u
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#define CYREG_B1_P5_U1_CFG19 0x40011ad3u
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#define CYREG_B1_P5_U1_CFG20 0x40011ad4u
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#define CYREG_B1_P5_U1_CFG21 0x40011ad5u
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#define CYREG_B1_P5_U1_CFG22 0x40011ad6u
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#define CYREG_B1_P5_U1_CFG23 0x40011ad7u
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#define CYREG_B1_P5_U1_CFG24 0x40011ad8u
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#define CYREG_B1_P5_U1_CFG25 0x40011ad9u
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#define CYREG_B1_P5_U1_CFG26 0x40011adau
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#define CYREG_B1_P5_U1_CFG27 0x40011adbu
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#define CYREG_B1_P5_U1_CFG28 0x40011adcu
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#define CYREG_B1_P5_U1_CFG29 0x40011addu
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#define CYREG_B1_P5_U1_CFG30 0x40011adeu
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#define CYREG_B1_P5_U1_CFG31 0x40011adfu
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#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u
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#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u
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#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u
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#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u
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#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u
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#define CYREG_B1_P5_U1_DCFG5 0x40011aeau
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#define CYREG_B1_P5_U1_DCFG6 0x40011aecu
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#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu
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#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u
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#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI0_BASE 0x40014000u
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#define CYDEV_UCFG_DSI0_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI1_BASE 0x40014100u
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#define CYDEV_UCFG_DSI1_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI2_BASE 0x40014200u
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#define CYDEV_UCFG_DSI2_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI3_BASE 0x40014300u
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#define CYDEV_UCFG_DSI3_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI4_BASE 0x40014400u
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#define CYDEV_UCFG_DSI4_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI5_BASE 0x40014500u
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#define CYDEV_UCFG_DSI5_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI6_BASE 0x40014600u
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#define CYDEV_UCFG_DSI6_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI7_BASE 0x40014700u
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#define CYDEV_UCFG_DSI7_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI8_BASE 0x40014800u
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#define CYDEV_UCFG_DSI8_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI9_BASE 0x40014900u
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#define CYDEV_UCFG_DSI9_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI12_BASE 0x40014c00u
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#define CYDEV_UCFG_DSI12_SIZE 0x000000efu
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#define CYDEV_UCFG_DSI13_BASE 0x40014d00u
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#define CYDEV_UCFG_DSI13_SIZE 0x000000efu
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#define CYDEV_UCFG_BCTL0_BASE 0x40015000u
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#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u
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#define CYREG_BCTL0_MDCLK_EN 0x40015000u
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#define CYREG_BCTL0_MBCLK_EN 0x40015001u
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#define CYREG_BCTL0_WAIT_CFG 0x40015002u
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#define CYREG_BCTL0_BANK_CTL 0x40015003u
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#define CYREG_BCTL0_UDB_TEST_3 0x40015007u
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#define CYREG_BCTL0_DCLK_EN0 0x40015008u
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#define CYREG_BCTL0_BCLK_EN0 0x40015009u
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#define CYREG_BCTL0_DCLK_EN1 0x4001500au
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#define CYREG_BCTL0_BCLK_EN1 0x4001500bu
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#define CYREG_BCTL0_DCLK_EN2 0x4001500cu
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#define CYREG_BCTL0_BCLK_EN2 0x4001500du
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#define CYREG_BCTL0_DCLK_EN3 0x4001500eu
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#define CYREG_BCTL0_BCLK_EN3 0x4001500fu
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#define CYDEV_UCFG_BCTL1_BASE 0x40015010u
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#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u
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#define CYREG_BCTL1_MDCLK_EN 0x40015010u
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#define CYREG_BCTL1_MBCLK_EN 0x40015011u
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#define CYREG_BCTL1_WAIT_CFG 0x40015012u
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#define CYREG_BCTL1_BANK_CTL 0x40015013u
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#define CYREG_BCTL1_UDB_TEST_3 0x40015017u
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#define CYREG_BCTL1_DCLK_EN0 0x40015018u
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#define CYREG_BCTL1_BCLK_EN0 0x40015019u
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#define CYREG_BCTL1_DCLK_EN1 0x4001501au
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#define CYREG_BCTL1_BCLK_EN1 0x4001501bu
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#define CYREG_BCTL1_DCLK_EN2 0x4001501cu
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#define CYREG_BCTL1_BCLK_EN2 0x4001501du
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#define CYREG_BCTL1_DCLK_EN3 0x4001501eu
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#define CYREG_BCTL1_BCLK_EN3 0x4001501fu
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#define CYDEV_IDMUX_BASE 0x40015100u
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#define CYDEV_IDMUX_SIZE 0x00000016u
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#define CYREG_IDMUX_IRQ_CTL0 0x40015100u
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#define CYREG_IDMUX_IRQ_CTL1 0x40015101u
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#define CYREG_IDMUX_IRQ_CTL2 0x40015102u
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#define CYREG_IDMUX_IRQ_CTL3 0x40015103u
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#define CYREG_IDMUX_IRQ_CTL4 0x40015104u
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#define CYREG_IDMUX_IRQ_CTL5 0x40015105u
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#define CYREG_IDMUX_IRQ_CTL6 0x40015106u
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#define CYREG_IDMUX_IRQ_CTL7 0x40015107u
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#define CYREG_IDMUX_DRQ_CTL0 0x40015110u
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#define CYREG_IDMUX_DRQ_CTL1 0x40015111u
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#define CYREG_IDMUX_DRQ_CTL2 0x40015112u
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#define CYREG_IDMUX_DRQ_CTL3 0x40015113u
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#define CYREG_IDMUX_DRQ_CTL4 0x40015114u
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#define CYREG_IDMUX_DRQ_CTL5 0x40015115u
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#define CYDEV_CACHERAM_BASE 0x40030000u
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#define CYDEV_CACHERAM_SIZE 0x00000400u
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#define CYREG_CACHERAM_DATA_MBASE 0x40030000u
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#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u
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#define CYDEV_SFR_BASE 0x40050100u
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#define CYDEV_SFR_SIZE 0x000000fbu
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#define CYREG_SFR_GPIO0 0x40050180u
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#define CYREG_SFR_GPIRD0 0x40050189u
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#define CYREG_SFR_GPIO0_SEL 0x4005018au
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#define CYREG_SFR_GPIO1 0x40050190u
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#define CYREG_SFR_GPIRD1 0x40050191u
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#define CYREG_SFR_GPIO2 0x40050198u
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#define CYREG_SFR_GPIRD2 0x40050199u
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#define CYREG_SFR_GPIO2_SEL 0x4005019au
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#define CYREG_SFR_GPIO1_SEL 0x400501a2u
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#define CYREG_SFR_GPIO3 0x400501b0u
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#define CYREG_SFR_GPIRD3 0x400501b1u
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#define CYREG_SFR_GPIO3_SEL 0x400501b2u
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#define CYREG_SFR_GPIO4 0x400501c0u
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#define CYREG_SFR_GPIRD4 0x400501c1u
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#define CYREG_SFR_GPIO4_SEL 0x400501c2u
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#define CYREG_SFR_GPIO5 0x400501c8u
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#define CYREG_SFR_GPIRD5 0x400501c9u
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#define CYREG_SFR_GPIO5_SEL 0x400501cau
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#define CYREG_SFR_GPIO6 0x400501d8u
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#define CYREG_SFR_GPIRD6 0x400501d9u
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#define CYREG_SFR_GPIO6_SEL 0x400501dau
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#define CYREG_SFR_GPIO12 0x400501e8u
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#define CYREG_SFR_GPIRD12 0x400501e9u
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#define CYREG_SFR_GPIO12_SEL 0x400501f2u
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#define CYREG_SFR_GPIO15 0x400501f8u
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#define CYREG_SFR_GPIRD15 0x400501f9u
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#define CYREG_SFR_GPIO15_SEL 0x400501fau
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#define CYDEV_P3BA_BASE 0x40050300u
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#define CYDEV_P3BA_SIZE 0x0000002bu
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#define CYREG_P3BA_Y_START 0x40050300u
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#define CYREG_P3BA_YROLL 0x40050301u
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#define CYREG_P3BA_YCFG 0x40050302u
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#define CYREG_P3BA_X_START1 0x40050303u
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#define CYREG_P3BA_X_START2 0x40050304u
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#define CYREG_P3BA_XROLL1 0x40050305u
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#define CYREG_P3BA_XROLL2 0x40050306u
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#define CYREG_P3BA_XINC 0x40050307u
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#define CYREG_P3BA_XCFG 0x40050308u
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#define CYREG_P3BA_OFFSETADDR1 0x40050309u
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#define CYREG_P3BA_OFFSETADDR2 0x4005030au
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#define CYREG_P3BA_OFFSETADDR3 0x4005030bu
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#define CYREG_P3BA_ABSADDR1 0x4005030cu
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#define CYREG_P3BA_ABSADDR2 0x4005030du
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#define CYREG_P3BA_ABSADDR3 0x4005030eu
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#define CYREG_P3BA_ABSADDR4 0x4005030fu
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#define CYREG_P3BA_DATCFG1 0x40050310u
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#define CYREG_P3BA_DATCFG2 0x40050311u
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#define CYREG_P3BA_CMP_RSLT1 0x40050314u
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#define CYREG_P3BA_CMP_RSLT2 0x40050315u
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#define CYREG_P3BA_CMP_RSLT3 0x40050316u
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#define CYREG_P3BA_CMP_RSLT4 0x40050317u
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#define CYREG_P3BA_DATA_REG1 0x40050318u
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#define CYREG_P3BA_DATA_REG2 0x40050319u
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#define CYREG_P3BA_DATA_REG3 0x4005031au
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#define CYREG_P3BA_DATA_REG4 0x4005031bu
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#define CYREG_P3BA_EXP_DATA1 0x4005031cu
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#define CYREG_P3BA_EXP_DATA2 0x4005031du
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#define CYREG_P3BA_EXP_DATA3 0x4005031eu
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#define CYREG_P3BA_EXP_DATA4 0x4005031fu
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#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u
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#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u
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#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u
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#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u
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#define CYREG_P3BA_BIST_EN 0x40050324u
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#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u
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#define CYREG_P3BA_SEQCFG1 0x40050326u
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#define CYREG_P3BA_SEQCFG2 0x40050327u
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#define CYREG_P3BA_Y_CURR 0x40050328u
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#define CYREG_P3BA_X_CURR1 0x40050329u
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#define CYREG_P3BA_X_CURR2 0x4005032au
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#define CYDEV_PANTHER_BASE 0x40080000u
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#define CYDEV_PANTHER_SIZE 0x00000020u
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#define CYREG_PANTHER_STCALIB_CFG 0x40080000u
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#define CYREG_PANTHER_WAITPIPE 0x40080004u
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#define CYREG_PANTHER_TRACE_CFG 0x40080008u
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#define CYREG_PANTHER_DBG_CFG 0x4008000cu
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#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u
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#define CYREG_PANTHER_DEVICE_ID 0x4008001cu
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#define CYDEV_FLSECC_BASE 0x48000000u
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#define CYDEV_FLSECC_SIZE 0x00008000u
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#define CYREG_FLSECC_DATA_MBASE 0x48000000u
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#define CYREG_FLSECC_DATA_MSIZE 0x00008000u
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#define CYDEV_FLSHID_BASE 0x49000000u
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#define CYDEV_FLSHID_SIZE 0x00000200u
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#define CYREG_FLSHID_RSVD_MBASE 0x49000000u
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#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u
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#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u
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#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u
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#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u
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#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u
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#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u
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#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u
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#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u
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#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u
|
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#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u
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|
#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u
|
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#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u
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#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u
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#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u
|
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#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u
|
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#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au
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#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu
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#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu
|
|
#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du
|
|
#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu
|
|
#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu
|
|
#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u
|
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#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u
|
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#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u
|
|
#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u
|
|
#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u
|
|
#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u
|
|
#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u
|
|
#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu
|
|
#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u
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|
#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u
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#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u
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#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u
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|
#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u
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|
#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u
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|
#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u
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|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u
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|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u
|
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#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu
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|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du
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|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu
|
|
#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu
|
|
#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u
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|
#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u
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|
#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u
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|
#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu
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#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu
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#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u
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#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u
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|
#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u
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|
#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u
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#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u
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#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau
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#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu
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#define CYDEV_EXTMEM_BASE 0x60000000u
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#define CYDEV_EXTMEM_SIZE 0x00800000u
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#define CYREG_EXTMEM_DATA_MBASE 0x60000000u
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#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u
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|
#define CYDEV_ITM_BASE 0xe0000000u
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|
#define CYDEV_ITM_SIZE 0x00001000u
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#define CYREG_ITM_TRACE_EN 0xe0000e00u
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#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u
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#define CYREG_ITM_TRACE_CTRL 0xe0000e80u
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#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u
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#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u
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#define CYREG_ITM_PID4 0xe0000fd0u
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#define CYREG_ITM_PID5 0xe0000fd4u
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#define CYREG_ITM_PID6 0xe0000fd8u
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#define CYREG_ITM_PID7 0xe0000fdcu
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#define CYREG_ITM_PID0 0xe0000fe0u
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#define CYREG_ITM_PID1 0xe0000fe4u
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#define CYREG_ITM_PID2 0xe0000fe8u
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#define CYREG_ITM_PID3 0xe0000fecu
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#define CYREG_ITM_CID0 0xe0000ff0u
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#define CYREG_ITM_CID1 0xe0000ff4u
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#define CYREG_ITM_CID2 0xe0000ff8u
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#define CYREG_ITM_CID3 0xe0000ffcu
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|
#define CYDEV_DWT_BASE 0xe0001000u
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|
#define CYDEV_DWT_SIZE 0x0000005cu
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|
#define CYREG_DWT_CTRL 0xe0001000u
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|
#define CYREG_DWT_CYCLE_COUNT 0xe0001004u
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|
#define CYREG_DWT_CPI_COUNT 0xe0001008u
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|
#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu
|
|
#define CYREG_DWT_SLEEP_COUNT 0xe0001010u
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|
#define CYREG_DWT_LSU_COUNT 0xe0001014u
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#define CYREG_DWT_FOLD_COUNT 0xe0001018u
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|
#define CYREG_DWT_PC_SAMPLE 0xe000101cu
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|
#define CYREG_DWT_COMP_0 0xe0001020u
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|
#define CYREG_DWT_MASK_0 0xe0001024u
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|
#define CYREG_DWT_FUNCTION_0 0xe0001028u
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|
#define CYREG_DWT_COMP_1 0xe0001030u
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|
#define CYREG_DWT_MASK_1 0xe0001034u
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|
#define CYREG_DWT_FUNCTION_1 0xe0001038u
|
|
#define CYREG_DWT_COMP_2 0xe0001040u
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|
#define CYREG_DWT_MASK_2 0xe0001044u
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|
#define CYREG_DWT_FUNCTION_2 0xe0001048u
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|
#define CYREG_DWT_COMP_3 0xe0001050u
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|
#define CYREG_DWT_MASK_3 0xe0001054u
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|
#define CYREG_DWT_FUNCTION_3 0xe0001058u
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|
#define CYDEV_FPB_BASE 0xe0002000u
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|
#define CYDEV_FPB_SIZE 0x00001000u
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|
#define CYREG_FPB_CTRL 0xe0002000u
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|
#define CYREG_FPB_REMAP 0xe0002004u
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|
#define CYREG_FPB_FP_COMP_0 0xe0002008u
|
|
#define CYREG_FPB_FP_COMP_1 0xe000200cu
|
|
#define CYREG_FPB_FP_COMP_2 0xe0002010u
|
|
#define CYREG_FPB_FP_COMP_3 0xe0002014u
|
|
#define CYREG_FPB_FP_COMP_4 0xe0002018u
|
|
#define CYREG_FPB_FP_COMP_5 0xe000201cu
|
|
#define CYREG_FPB_FP_COMP_6 0xe0002020u
|
|
#define CYREG_FPB_FP_COMP_7 0xe0002024u
|
|
#define CYREG_FPB_PID4 0xe0002fd0u
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|
#define CYREG_FPB_PID5 0xe0002fd4u
|
|
#define CYREG_FPB_PID6 0xe0002fd8u
|
|
#define CYREG_FPB_PID7 0xe0002fdcu
|
|
#define CYREG_FPB_PID0 0xe0002fe0u
|
|
#define CYREG_FPB_PID1 0xe0002fe4u
|
|
#define CYREG_FPB_PID2 0xe0002fe8u
|
|
#define CYREG_FPB_PID3 0xe0002fecu
|
|
#define CYREG_FPB_CID0 0xe0002ff0u
|
|
#define CYREG_FPB_CID1 0xe0002ff4u
|
|
#define CYREG_FPB_CID2 0xe0002ff8u
|
|
#define CYREG_FPB_CID3 0xe0002ffcu
|
|
#define CYDEV_NVIC_BASE 0xe000e000u
|
|
#define CYDEV_NVIC_SIZE 0x00000d3cu
|
|
#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u
|
|
#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u
|
|
#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u
|
|
#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u
|
|
#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu
|
|
#define CYREG_NVIC_SETENA0 0xe000e100u
|
|
#define CYREG_NVIC_CLRENA0 0xe000e180u
|
|
#define CYREG_NVIC_SETPEND0 0xe000e200u
|
|
#define CYREG_NVIC_CLRPEND0 0xe000e280u
|
|
#define CYREG_NVIC_ACTIVE0 0xe000e300u
|
|
#define CYREG_NVIC_PRI_0 0xe000e400u
|
|
#define CYREG_NVIC_PRI_1 0xe000e401u
|
|
#define CYREG_NVIC_PRI_2 0xe000e402u
|
|
#define CYREG_NVIC_PRI_3 0xe000e403u
|
|
#define CYREG_NVIC_PRI_4 0xe000e404u
|
|
#define CYREG_NVIC_PRI_5 0xe000e405u
|
|
#define CYREG_NVIC_PRI_6 0xe000e406u
|
|
#define CYREG_NVIC_PRI_7 0xe000e407u
|
|
#define CYREG_NVIC_PRI_8 0xe000e408u
|
|
#define CYREG_NVIC_PRI_9 0xe000e409u
|
|
#define CYREG_NVIC_PRI_10 0xe000e40au
|
|
#define CYREG_NVIC_PRI_11 0xe000e40bu
|
|
#define CYREG_NVIC_PRI_12 0xe000e40cu
|
|
#define CYREG_NVIC_PRI_13 0xe000e40du
|
|
#define CYREG_NVIC_PRI_14 0xe000e40eu
|
|
#define CYREG_NVIC_PRI_15 0xe000e40fu
|
|
#define CYREG_NVIC_PRI_16 0xe000e410u
|
|
#define CYREG_NVIC_PRI_17 0xe000e411u
|
|
#define CYREG_NVIC_PRI_18 0xe000e412u
|
|
#define CYREG_NVIC_PRI_19 0xe000e413u
|
|
#define CYREG_NVIC_PRI_20 0xe000e414u
|
|
#define CYREG_NVIC_PRI_21 0xe000e415u
|
|
#define CYREG_NVIC_PRI_22 0xe000e416u
|
|
#define CYREG_NVIC_PRI_23 0xe000e417u
|
|
#define CYREG_NVIC_PRI_24 0xe000e418u
|
|
#define CYREG_NVIC_PRI_25 0xe000e419u
|
|
#define CYREG_NVIC_PRI_26 0xe000e41au
|
|
#define CYREG_NVIC_PRI_27 0xe000e41bu
|
|
#define CYREG_NVIC_PRI_28 0xe000e41cu
|
|
#define CYREG_NVIC_PRI_29 0xe000e41du
|
|
#define CYREG_NVIC_PRI_30 0xe000e41eu
|
|
#define CYREG_NVIC_PRI_31 0xe000e41fu
|
|
#define CYREG_NVIC_CPUID_BASE 0xe000ed00u
|
|
#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u
|
|
#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u
|
|
#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu
|
|
#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u
|
|
#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u
|
|
#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u
|
|
#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu
|
|
#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u
|
|
#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u
|
|
#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u
|
|
#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u
|
|
#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au
|
|
#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu
|
|
#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u
|
|
#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u
|
|
#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u
|
|
#define CYDEV_CORE_DBG_BASE 0xe000edf0u
|
|
#define CYDEV_CORE_DBG_SIZE 0x00000010u
|
|
#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u
|
|
#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u
|
|
#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u
|
|
#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu
|
|
#define CYDEV_TPIU_BASE 0xe0040000u
|
|
#define CYDEV_TPIU_SIZE 0x00001000u
|
|
#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u
|
|
#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u
|
|
#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u
|
|
#define CYREG_TPIU_PROTOCOL 0xe00400f0u
|
|
#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u
|
|
#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u
|
|
#define CYREG_TPIU_TRIGGER 0xe0040ee8u
|
|
#define CYREG_TPIU_ITETMDATA 0xe0040eecu
|
|
#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u
|
|
#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u
|
|
#define CYREG_TPIU_ITITMDATA 0xe0040efcu
|
|
#define CYREG_TPIU_ITCTRL 0xe0040f00u
|
|
#define CYREG_TPIU_DEVID 0xe0040fc8u
|
|
#define CYREG_TPIU_DEVTYPE 0xe0040fccu
|
|
#define CYREG_TPIU_PID4 0xe0040fd0u
|
|
#define CYREG_TPIU_PID5 0xe0040fd4u
|
|
#define CYREG_TPIU_PID6 0xe0040fd8u
|
|
#define CYREG_TPIU_PID7 0xe0040fdcu
|
|
#define CYREG_TPIU_PID0 0xe0040fe0u
|
|
#define CYREG_TPIU_PID1 0xe0040fe4u
|
|
#define CYREG_TPIU_PID2 0xe0040fe8u
|
|
#define CYREG_TPIU_PID3 0xe0040fecu
|
|
#define CYREG_TPIU_CID0 0xe0040ff0u
|
|
#define CYREG_TPIU_CID1 0xe0040ff4u
|
|
#define CYREG_TPIU_CID2 0xe0040ff8u
|
|
#define CYREG_TPIU_CID3 0xe0040ffcu
|
|
#define CYDEV_ETM_BASE 0xe0041000u
|
|
#define CYDEV_ETM_SIZE 0x00001000u
|
|
#define CYREG_ETM_CTL 0xe0041000u
|
|
#define CYREG_ETM_CFG_CODE 0xe0041004u
|
|
#define CYREG_ETM_TRIG_EVENT 0xe0041008u
|
|
#define CYREG_ETM_STATUS 0xe0041010u
|
|
#define CYREG_ETM_SYS_CFG 0xe0041014u
|
|
#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u
|
|
#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u
|
|
#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu
|
|
#define CYREG_ETM_SYNC_FREQ 0xe00411e0u
|
|
#define CYREG_ETM_ETM_ID 0xe00411e4u
|
|
#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u
|
|
#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u
|
|
#define CYREG_ETM_CS_TRACE_ID 0xe0041200u
|
|
#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u
|
|
#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u
|
|
#define CYREG_ETM_PDSR 0xe0041314u
|
|
#define CYREG_ETM_ITMISCIN 0xe0041ee0u
|
|
#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u
|
|
#define CYREG_ETM_ITATBCTR2 0xe0041ef0u
|
|
#define CYREG_ETM_ITATBCTR0 0xe0041ef8u
|
|
#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u
|
|
#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u
|
|
#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u
|
|
#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u
|
|
#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u
|
|
#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u
|
|
#define CYREG_ETM_DEV_TYPE 0xe0041fccu
|
|
#define CYREG_ETM_PID4 0xe0041fd0u
|
|
#define CYREG_ETM_PID5 0xe0041fd4u
|
|
#define CYREG_ETM_PID6 0xe0041fd8u
|
|
#define CYREG_ETM_PID7 0xe0041fdcu
|
|
#define CYREG_ETM_PID0 0xe0041fe0u
|
|
#define CYREG_ETM_PID1 0xe0041fe4u
|
|
#define CYREG_ETM_PID2 0xe0041fe8u
|
|
#define CYREG_ETM_PID3 0xe0041fecu
|
|
#define CYREG_ETM_CID0 0xe0041ff0u
|
|
#define CYREG_ETM_CID1 0xe0041ff4u
|
|
#define CYREG_ETM_CID2 0xe0041ff8u
|
|
#define CYREG_ETM_CID3 0xe0041ffcu
|
|
#define CYDEV_ROM_TABLE_BASE 0xe00ff000u
|
|
#define CYDEV_ROM_TABLE_SIZE 0x00001000u
|
|
#define CYREG_ROM_TABLE_NVIC 0xe00ff000u
|
|
#define CYREG_ROM_TABLE_DWT 0xe00ff004u
|
|
#define CYREG_ROM_TABLE_FPB 0xe00ff008u
|
|
#define CYREG_ROM_TABLE_ITM 0xe00ff00cu
|
|
#define CYREG_ROM_TABLE_TPIU 0xe00ff010u
|
|
#define CYREG_ROM_TABLE_ETM 0xe00ff014u
|
|
#define CYREG_ROM_TABLE_END 0xe00ff018u
|
|
#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu
|
|
#define CYREG_ROM_TABLE_PID4 0xe00fffd0u
|
|
#define CYREG_ROM_TABLE_PID5 0xe00fffd4u
|
|
#define CYREG_ROM_TABLE_PID6 0xe00fffd8u
|
|
#define CYREG_ROM_TABLE_PID7 0xe00fffdcu
|
|
#define CYREG_ROM_TABLE_PID0 0xe00fffe0u
|
|
#define CYREG_ROM_TABLE_PID1 0xe00fffe4u
|
|
#define CYREG_ROM_TABLE_PID2 0xe00fffe8u
|
|
#define CYREG_ROM_TABLE_PID3 0xe00fffecu
|
|
#define CYREG_ROM_TABLE_CID0 0xe00ffff0u
|
|
#define CYREG_ROM_TABLE_CID1 0xe00ffff4u
|
|
#define CYREG_ROM_TABLE_CID2 0xe00ffff8u
|
|
#define CYREG_ROM_TABLE_CID3 0xe00ffffcu
|
|
#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE
|
|
#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
|
|
#define CYDEV_FLS_SECTOR_SIZE 0x00010000u
|
|
#define CYDEV_FLS_ROW_SIZE 0x00000100u
|
|
#define CYDEV_ECC_SECTOR_SIZE 0x00002000u
|
|
#define CYDEV_ECC_ROW_SIZE 0x00000020u
|
|
#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u
|
|
#define CYDEV_EEPROM_ROW_SIZE 0x00000010u
|
|
#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE
|
|
#define CYCLK_LD_DISABLE 0x00000004u
|
|
#define CYCLK_LD_SYNC_EN 0x00000002u
|
|
#define CYCLK_LD_LOAD 0x00000001u
|
|
#define CYCLK_PIPE 0x00000080u
|
|
#define CYCLK_SSS 0x00000040u
|
|
#define CYCLK_EARLY 0x00000020u
|
|
#define CYCLK_DUTY 0x00000010u
|
|
#define CYCLK_SYNC 0x00000008u
|
|
#define CYCLK_SRC_SEL_CLK_SYNC_D 0
|
|
#define CYCLK_SRC_SEL_SYNC_DIG 0
|
|
#define CYCLK_SRC_SEL_IMO 1
|
|
#define CYCLK_SRC_SEL_XTAL_MHZ 2
|
|
#define CYCLK_SRC_SEL_XTALM 2
|
|
#define CYCLK_SRC_SEL_ILO 3
|
|
#define CYCLK_SRC_SEL_PLL 4
|
|
#define CYCLK_SRC_SEL_XTAL_KHZ 5
|
|
#define CYCLK_SRC_SEL_XTALK 5
|
|
#define CYCLK_SRC_SEL_DSI_G 6
|
|
#define CYCLK_SRC_SEL_DSI_D 7
|
|
#define CYCLK_SRC_SEL_CLK_SYNC_A 0
|
|
#define CYCLK_SRC_SEL_DSI_A 7
|
|
#endif /* CYDEVICE_TRM_H */
|