mirror of
https://github.com/fhgwright/SCSI2SD.git
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5357 lines
240 KiB
PHP
Executable File
5357 lines
240 KiB
PHP
Executable File
;
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; FILENAME: cydeviceiar.inc
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; OBSOLETE: Do not use this file. Use the _trm version instead.
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; PSoC Creator 3.2
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;
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; DESCRIPTION:
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; This file provides all of the address values for the entire PSoC device.
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;
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;-------------------------------------------------------------------------------
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; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
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; You may use this file only in accordance with the license, terms, conditions,
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; disclaimers, and limitations in the end user license agreement accompanying
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; the software package with which this file was provided.
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;-------------------------------------------------------------------------------
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#define CYDEV_FLASH_BASE 0x00000000
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#define CYDEV_FLASH_SIZE 0x00020000
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#define CYDEV_FLASH_DATA_MBASE 0x00000000
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#define CYDEV_FLASH_DATA_MSIZE 0x00020000
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#define CYDEV_SRAM_BASE 0x1fffc000
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#define CYDEV_SRAM_SIZE 0x00008000
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#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000
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#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000
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#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000
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#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000
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#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000
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#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000
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#define CYDEV_SRAM_CODE_MBASE 0x1fffc000
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#define CYDEV_SRAM_CODE_MSIZE 0x00004000
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#define CYDEV_SRAM_DATA_MBASE 0x20000000
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#define CYDEV_SRAM_DATA_MSIZE 0x00004000
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#define CYDEV_SRAM_DATA16K_MBASE 0x20001000
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#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000
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#define CYDEV_SRAM_DATA32K_MBASE 0x20002000
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#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000
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#define CYDEV_SRAM_DATA64K_MBASE 0x20004000
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#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000
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#define CYDEV_DMA_BASE 0x20008000
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#define CYDEV_DMA_SIZE 0x00008000
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#define CYDEV_DMA_SRAM64K_MBASE 0x20008000
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#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000
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#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000
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#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000
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#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000
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#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000
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#define CYDEV_DMA_SRAM_MBASE 0x2000f000
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#define CYDEV_DMA_SRAM_MSIZE 0x00001000
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#define CYDEV_CLKDIST_BASE 0x40004000
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#define CYDEV_CLKDIST_SIZE 0x00000110
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#define CYDEV_CLKDIST_CR 0x40004000
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#define CYDEV_CLKDIST_LD 0x40004001
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#define CYDEV_CLKDIST_WRK0 0x40004002
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#define CYDEV_CLKDIST_WRK1 0x40004003
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#define CYDEV_CLKDIST_MSTR0 0x40004004
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#define CYDEV_CLKDIST_MSTR1 0x40004005
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#define CYDEV_CLKDIST_BCFG0 0x40004006
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#define CYDEV_CLKDIST_BCFG1 0x40004007
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#define CYDEV_CLKDIST_BCFG2 0x40004008
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#define CYDEV_CLKDIST_UCFG 0x40004009
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#define CYDEV_CLKDIST_DLY0 0x4000400a
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#define CYDEV_CLKDIST_DLY1 0x4000400b
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#define CYDEV_CLKDIST_DMASK 0x40004010
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#define CYDEV_CLKDIST_AMASK 0x40004014
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#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080
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#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080
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#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081
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#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082
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#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084
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#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084
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#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085
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#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086
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#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088
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#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088
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#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089
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#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a
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#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c
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#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c
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#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d
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#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e
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#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090
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#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090
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#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091
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#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092
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#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094
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#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094
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#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095
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#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096
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#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098
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#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098
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#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099
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#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a
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#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c
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#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003
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#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c
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#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d
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#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e
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#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100
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#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004
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#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100
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#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101
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#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102
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#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103
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#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104
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#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004
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#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104
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#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105
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#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106
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#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107
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#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108
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#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004
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#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108
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#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109
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#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a
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#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b
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#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c
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#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004
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#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c
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#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d
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#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e
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#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f
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#define CYDEV_FASTCLK_BASE 0x40004200
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#define CYDEV_FASTCLK_SIZE 0x00000026
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#define CYDEV_FASTCLK_IMO_BASE 0x40004200
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#define CYDEV_FASTCLK_IMO_SIZE 0x00000001
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#define CYDEV_FASTCLK_IMO_CR 0x40004200
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#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210
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#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004
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#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210
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#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212
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#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213
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#define CYDEV_FASTCLK_PLL_BASE 0x40004220
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#define CYDEV_FASTCLK_PLL_SIZE 0x00000006
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#define CYDEV_FASTCLK_PLL_CFG0 0x40004220
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#define CYDEV_FASTCLK_PLL_CFG1 0x40004221
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#define CYDEV_FASTCLK_PLL_P 0x40004222
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#define CYDEV_FASTCLK_PLL_Q 0x40004223
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#define CYDEV_FASTCLK_PLL_SR 0x40004225
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#define CYDEV_SLOWCLK_BASE 0x40004300
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#define CYDEV_SLOWCLK_SIZE 0x0000000b
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#define CYDEV_SLOWCLK_ILO_BASE 0x40004300
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#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002
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#define CYDEV_SLOWCLK_ILO_CR0 0x40004300
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#define CYDEV_SLOWCLK_ILO_CR1 0x40004301
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#define CYDEV_SLOWCLK_X32_BASE 0x40004308
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#define CYDEV_SLOWCLK_X32_SIZE 0x00000003
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#define CYDEV_SLOWCLK_X32_CR 0x40004308
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#define CYDEV_SLOWCLK_X32_CFG 0x40004309
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#define CYDEV_SLOWCLK_X32_TST 0x4000430a
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#define CYDEV_BOOST_BASE 0x40004320
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#define CYDEV_BOOST_SIZE 0x00000007
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#define CYDEV_BOOST_CR0 0x40004320
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#define CYDEV_BOOST_CR1 0x40004321
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#define CYDEV_BOOST_CR2 0x40004322
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#define CYDEV_BOOST_CR3 0x40004323
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#define CYDEV_BOOST_SR 0x40004324
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#define CYDEV_BOOST_CR4 0x40004325
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#define CYDEV_BOOST_SR2 0x40004326
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#define CYDEV_PWRSYS_BASE 0x40004330
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#define CYDEV_PWRSYS_SIZE 0x00000002
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#define CYDEV_PWRSYS_CR0 0x40004330
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#define CYDEV_PWRSYS_CR1 0x40004331
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#define CYDEV_PM_BASE 0x40004380
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#define CYDEV_PM_SIZE 0x00000057
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#define CYDEV_PM_TW_CFG0 0x40004380
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#define CYDEV_PM_TW_CFG1 0x40004381
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#define CYDEV_PM_TW_CFG2 0x40004382
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#define CYDEV_PM_WDT_CFG 0x40004383
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#define CYDEV_PM_WDT_CR 0x40004384
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#define CYDEV_PM_INT_SR 0x40004390
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#define CYDEV_PM_MODE_CFG0 0x40004391
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#define CYDEV_PM_MODE_CFG1 0x40004392
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#define CYDEV_PM_MODE_CSR 0x40004393
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#define CYDEV_PM_USB_CR0 0x40004394
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#define CYDEV_PM_WAKEUP_CFG0 0x40004398
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#define CYDEV_PM_WAKEUP_CFG1 0x40004399
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#define CYDEV_PM_WAKEUP_CFG2 0x4000439a
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#define CYDEV_PM_ACT_BASE 0x400043a0
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#define CYDEV_PM_ACT_SIZE 0x0000000e
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#define CYDEV_PM_ACT_CFG0 0x400043a0
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#define CYDEV_PM_ACT_CFG1 0x400043a1
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#define CYDEV_PM_ACT_CFG2 0x400043a2
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#define CYDEV_PM_ACT_CFG3 0x400043a3
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#define CYDEV_PM_ACT_CFG4 0x400043a4
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#define CYDEV_PM_ACT_CFG5 0x400043a5
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#define CYDEV_PM_ACT_CFG6 0x400043a6
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#define CYDEV_PM_ACT_CFG7 0x400043a7
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#define CYDEV_PM_ACT_CFG8 0x400043a8
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#define CYDEV_PM_ACT_CFG9 0x400043a9
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#define CYDEV_PM_ACT_CFG10 0x400043aa
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#define CYDEV_PM_ACT_CFG11 0x400043ab
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#define CYDEV_PM_ACT_CFG12 0x400043ac
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#define CYDEV_PM_ACT_CFG13 0x400043ad
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#define CYDEV_PM_STBY_BASE 0x400043b0
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#define CYDEV_PM_STBY_SIZE 0x0000000e
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#define CYDEV_PM_STBY_CFG0 0x400043b0
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#define CYDEV_PM_STBY_CFG1 0x400043b1
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#define CYDEV_PM_STBY_CFG2 0x400043b2
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#define CYDEV_PM_STBY_CFG3 0x400043b3
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#define CYDEV_PM_STBY_CFG4 0x400043b4
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#define CYDEV_PM_STBY_CFG5 0x400043b5
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#define CYDEV_PM_STBY_CFG6 0x400043b6
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#define CYDEV_PM_STBY_CFG7 0x400043b7
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#define CYDEV_PM_STBY_CFG8 0x400043b8
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#define CYDEV_PM_STBY_CFG9 0x400043b9
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#define CYDEV_PM_STBY_CFG10 0x400043ba
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#define CYDEV_PM_STBY_CFG11 0x400043bb
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#define CYDEV_PM_STBY_CFG12 0x400043bc
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#define CYDEV_PM_STBY_CFG13 0x400043bd
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#define CYDEV_PM_AVAIL_BASE 0x400043c0
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#define CYDEV_PM_AVAIL_SIZE 0x00000017
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#define CYDEV_PM_AVAIL_CR0 0x400043c0
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#define CYDEV_PM_AVAIL_CR1 0x400043c1
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#define CYDEV_PM_AVAIL_CR2 0x400043c2
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#define CYDEV_PM_AVAIL_CR3 0x400043c3
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#define CYDEV_PM_AVAIL_CR4 0x400043c4
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#define CYDEV_PM_AVAIL_CR5 0x400043c5
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#define CYDEV_PM_AVAIL_CR6 0x400043c6
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#define CYDEV_PM_AVAIL_SR0 0x400043d0
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#define CYDEV_PM_AVAIL_SR1 0x400043d1
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#define CYDEV_PM_AVAIL_SR2 0x400043d2
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#define CYDEV_PM_AVAIL_SR3 0x400043d3
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#define CYDEV_PM_AVAIL_SR4 0x400043d4
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#define CYDEV_PM_AVAIL_SR5 0x400043d5
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#define CYDEV_PM_AVAIL_SR6 0x400043d6
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#define CYDEV_PICU_BASE 0x40004500
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#define CYDEV_PICU_SIZE 0x000000b0
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#define CYDEV_PICU_INTTYPE_BASE 0x40004500
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#define CYDEV_PICU_INTTYPE_SIZE 0x00000080
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#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500
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#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506
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#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507
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#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508
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#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e
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#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f
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#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510
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#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516
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#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517
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#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518
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#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e
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#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f
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#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520
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#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526
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#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527
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#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528
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#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e
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#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f
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#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530
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#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536
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#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537
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#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560
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#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008
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#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566
|
|
#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567
|
|
#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578
|
|
#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e
|
|
#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f
|
|
#define CYDEV_PICU_STAT_BASE 0x40004580
|
|
#define CYDEV_PICU_STAT_SIZE 0x00000010
|
|
#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580
|
|
#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580
|
|
#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581
|
|
#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581
|
|
#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582
|
|
#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582
|
|
#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583
|
|
#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583
|
|
#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584
|
|
#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584
|
|
#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585
|
|
#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585
|
|
#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586
|
|
#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586
|
|
#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c
|
|
#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c
|
|
#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f
|
|
#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001
|
|
#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f
|
|
#define CYDEV_PICU_SNAP_BASE 0x40004590
|
|
#define CYDEV_PICU_SNAP_SIZE 0x00000010
|
|
#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590
|
|
#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590
|
|
#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591
|
|
#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591
|
|
#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592
|
|
#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592
|
|
#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593
|
|
#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593
|
|
#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594
|
|
#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594
|
|
#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595
|
|
#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595
|
|
#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596
|
|
#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596
|
|
#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c
|
|
#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c
|
|
#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f
|
|
#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001
|
|
#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f
|
|
#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0
|
|
#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010
|
|
#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0
|
|
#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0
|
|
#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1
|
|
#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1
|
|
#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2
|
|
#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2
|
|
#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3
|
|
#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3
|
|
#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4
|
|
#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4
|
|
#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5
|
|
#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5
|
|
#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6
|
|
#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6
|
|
#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac
|
|
#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac
|
|
#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af
|
|
#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001
|
|
#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af
|
|
#define CYDEV_MFGCFG_BASE 0x40004600
|
|
#define CYDEV_MFGCFG_SIZE 0x000000ed
|
|
#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600
|
|
#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038
|
|
#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608
|
|
#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608
|
|
#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609
|
|
#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609
|
|
#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a
|
|
#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a
|
|
#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b
|
|
#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612
|
|
#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614
|
|
#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614
|
|
#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616
|
|
#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626
|
|
#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627
|
|
#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630
|
|
#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630
|
|
#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631
|
|
#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632
|
|
#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632
|
|
#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633
|
|
#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634
|
|
#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634
|
|
#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635
|
|
#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636
|
|
#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636
|
|
#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637
|
|
#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680
|
|
#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b
|
|
#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680
|
|
#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681
|
|
#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682
|
|
#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683
|
|
#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684
|
|
#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685
|
|
#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686
|
|
#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687
|
|
#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688
|
|
#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689
|
|
#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a
|
|
#define CYDEV_MFGCFG_ILO_BASE 0x40004690
|
|
#define CYDEV_MFGCFG_ILO_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_ILO_TR0 0x40004690
|
|
#define CYDEV_MFGCFG_ILO_TR1 0x40004691
|
|
#define CYDEV_MFGCFG_X32_BASE 0x40004698
|
|
#define CYDEV_MFGCFG_X32_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_X32_TR 0x40004698
|
|
#define CYDEV_MFGCFG_IMO_BASE 0x400046a0
|
|
#define CYDEV_MFGCFG_IMO_SIZE 0x00000005
|
|
#define CYDEV_MFGCFG_IMO_TR0 0x400046a0
|
|
#define CYDEV_MFGCFG_IMO_TR1 0x400046a1
|
|
#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2
|
|
#define CYDEV_MFGCFG_IMO_C36M 0x400046a3
|
|
#define CYDEV_MFGCFG_IMO_TR2 0x400046a4
|
|
#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8
|
|
#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8
|
|
#define CYDEV_MFGCFG_DLY 0x400046c0
|
|
#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0
|
|
#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d
|
|
#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2
|
|
#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4
|
|
#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002
|
|
#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4
|
|
#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5
|
|
#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8
|
|
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea
|
|
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001
|
|
#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea
|
|
#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec
|
|
#define CYDEV_RESET_BASE 0x400046f0
|
|
#define CYDEV_RESET_SIZE 0x0000000f
|
|
#define CYDEV_RESET_IPOR_CR0 0x400046f0
|
|
#define CYDEV_RESET_IPOR_CR1 0x400046f1
|
|
#define CYDEV_RESET_IPOR_CR2 0x400046f2
|
|
#define CYDEV_RESET_IPOR_CR3 0x400046f3
|
|
#define CYDEV_RESET_CR0 0x400046f4
|
|
#define CYDEV_RESET_CR1 0x400046f5
|
|
#define CYDEV_RESET_CR2 0x400046f6
|
|
#define CYDEV_RESET_CR3 0x400046f7
|
|
#define CYDEV_RESET_CR4 0x400046f8
|
|
#define CYDEV_RESET_CR5 0x400046f9
|
|
#define CYDEV_RESET_SR0 0x400046fa
|
|
#define CYDEV_RESET_SR1 0x400046fb
|
|
#define CYDEV_RESET_SR2 0x400046fc
|
|
#define CYDEV_RESET_SR3 0x400046fd
|
|
#define CYDEV_RESET_TR 0x400046fe
|
|
#define CYDEV_SPC_BASE 0x40004700
|
|
#define CYDEV_SPC_SIZE 0x00000100
|
|
#define CYDEV_SPC_FM_EE_CR 0x40004700
|
|
#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701
|
|
#define CYDEV_SPC_EE_SCR 0x40004702
|
|
#define CYDEV_SPC_EE_ERR 0x40004703
|
|
#define CYDEV_SPC_CPU_DATA 0x40004720
|
|
#define CYDEV_SPC_DMA_DATA 0x40004721
|
|
#define CYDEV_SPC_SR 0x40004722
|
|
#define CYDEV_SPC_CR 0x40004723
|
|
#define CYDEV_SPC_DMM_MAP_BASE 0x40004780
|
|
#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080
|
|
#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780
|
|
#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080
|
|
#define CYDEV_CACHE_BASE 0x40004800
|
|
#define CYDEV_CACHE_SIZE 0x0000009c
|
|
#define CYDEV_CACHE_CC_CTL 0x40004800
|
|
#define CYDEV_CACHE_ECC_CORR 0x40004880
|
|
#define CYDEV_CACHE_ECC_ERR 0x40004888
|
|
#define CYDEV_CACHE_FLASH_ERR 0x40004890
|
|
#define CYDEV_CACHE_HITMISS 0x40004898
|
|
#define CYDEV_I2C_BASE 0x40004900
|
|
#define CYDEV_I2C_SIZE 0x000000e1
|
|
#define CYDEV_I2C_XCFG 0x400049c8
|
|
#define CYDEV_I2C_ADR 0x400049ca
|
|
#define CYDEV_I2C_CFG 0x400049d6
|
|
#define CYDEV_I2C_CSR 0x400049d7
|
|
#define CYDEV_I2C_D 0x400049d8
|
|
#define CYDEV_I2C_MCSR 0x400049d9
|
|
#define CYDEV_I2C_CLK_DIV1 0x400049db
|
|
#define CYDEV_I2C_CLK_DIV2 0x400049dc
|
|
#define CYDEV_I2C_TMOUT_CSR 0x400049dd
|
|
#define CYDEV_I2C_TMOUT_SR 0x400049de
|
|
#define CYDEV_I2C_TMOUT_CFG0 0x400049df
|
|
#define CYDEV_I2C_TMOUT_CFG1 0x400049e0
|
|
#define CYDEV_DEC_BASE 0x40004e00
|
|
#define CYDEV_DEC_SIZE 0x00000015
|
|
#define CYDEV_DEC_CR 0x40004e00
|
|
#define CYDEV_DEC_SR 0x40004e01
|
|
#define CYDEV_DEC_SHIFT1 0x40004e02
|
|
#define CYDEV_DEC_SHIFT2 0x40004e03
|
|
#define CYDEV_DEC_DR2 0x40004e04
|
|
#define CYDEV_DEC_DR2H 0x40004e05
|
|
#define CYDEV_DEC_DR1 0x40004e06
|
|
#define CYDEV_DEC_OCOR 0x40004e08
|
|
#define CYDEV_DEC_OCORM 0x40004e09
|
|
#define CYDEV_DEC_OCORH 0x40004e0a
|
|
#define CYDEV_DEC_GCOR 0x40004e0c
|
|
#define CYDEV_DEC_GCORH 0x40004e0d
|
|
#define CYDEV_DEC_GVAL 0x40004e0e
|
|
#define CYDEV_DEC_OUTSAMP 0x40004e10
|
|
#define CYDEV_DEC_OUTSAMPM 0x40004e11
|
|
#define CYDEV_DEC_OUTSAMPH 0x40004e12
|
|
#define CYDEV_DEC_OUTSAMPS 0x40004e13
|
|
#define CYDEV_DEC_COHER 0x40004e14
|
|
#define CYDEV_TMR0_BASE 0x40004f00
|
|
#define CYDEV_TMR0_SIZE 0x0000000c
|
|
#define CYDEV_TMR0_CFG0 0x40004f00
|
|
#define CYDEV_TMR0_CFG1 0x40004f01
|
|
#define CYDEV_TMR0_CFG2 0x40004f02
|
|
#define CYDEV_TMR0_SR0 0x40004f03
|
|
#define CYDEV_TMR0_PER0 0x40004f04
|
|
#define CYDEV_TMR0_PER1 0x40004f05
|
|
#define CYDEV_TMR0_CNT_CMP0 0x40004f06
|
|
#define CYDEV_TMR0_CNT_CMP1 0x40004f07
|
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#define CYDEV_TMR0_CAP0 0x40004f08
|
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#define CYDEV_TMR0_CAP1 0x40004f09
|
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#define CYDEV_TMR0_RT0 0x40004f0a
|
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#define CYDEV_TMR0_RT1 0x40004f0b
|
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#define CYDEV_TMR1_BASE 0x40004f0c
|
|
#define CYDEV_TMR1_SIZE 0x0000000c
|
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#define CYDEV_TMR1_CFG0 0x40004f0c
|
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#define CYDEV_TMR1_CFG1 0x40004f0d
|
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#define CYDEV_TMR1_CFG2 0x40004f0e
|
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#define CYDEV_TMR1_SR0 0x40004f0f
|
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#define CYDEV_TMR1_PER0 0x40004f10
|
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#define CYDEV_TMR1_PER1 0x40004f11
|
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#define CYDEV_TMR1_CNT_CMP0 0x40004f12
|
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#define CYDEV_TMR1_CNT_CMP1 0x40004f13
|
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#define CYDEV_TMR1_CAP0 0x40004f14
|
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#define CYDEV_TMR1_CAP1 0x40004f15
|
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#define CYDEV_TMR1_RT0 0x40004f16
|
|
#define CYDEV_TMR1_RT1 0x40004f17
|
|
#define CYDEV_TMR2_BASE 0x40004f18
|
|
#define CYDEV_TMR2_SIZE 0x0000000c
|
|
#define CYDEV_TMR2_CFG0 0x40004f18
|
|
#define CYDEV_TMR2_CFG1 0x40004f19
|
|
#define CYDEV_TMR2_CFG2 0x40004f1a
|
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#define CYDEV_TMR2_SR0 0x40004f1b
|
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#define CYDEV_TMR2_PER0 0x40004f1c
|
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#define CYDEV_TMR2_PER1 0x40004f1d
|
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#define CYDEV_TMR2_CNT_CMP0 0x40004f1e
|
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#define CYDEV_TMR2_CNT_CMP1 0x40004f1f
|
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#define CYDEV_TMR2_CAP0 0x40004f20
|
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#define CYDEV_TMR2_CAP1 0x40004f21
|
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#define CYDEV_TMR2_RT0 0x40004f22
|
|
#define CYDEV_TMR2_RT1 0x40004f23
|
|
#define CYDEV_TMR3_BASE 0x40004f24
|
|
#define CYDEV_TMR3_SIZE 0x0000000c
|
|
#define CYDEV_TMR3_CFG0 0x40004f24
|
|
#define CYDEV_TMR3_CFG1 0x40004f25
|
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#define CYDEV_TMR3_CFG2 0x40004f26
|
|
#define CYDEV_TMR3_SR0 0x40004f27
|
|
#define CYDEV_TMR3_PER0 0x40004f28
|
|
#define CYDEV_TMR3_PER1 0x40004f29
|
|
#define CYDEV_TMR3_CNT_CMP0 0x40004f2a
|
|
#define CYDEV_TMR3_CNT_CMP1 0x40004f2b
|
|
#define CYDEV_TMR3_CAP0 0x40004f2c
|
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#define CYDEV_TMR3_CAP1 0x40004f2d
|
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#define CYDEV_TMR3_RT0 0x40004f2e
|
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#define CYDEV_TMR3_RT1 0x40004f2f
|
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#define CYDEV_IO_BASE 0x40005000
|
|
#define CYDEV_IO_SIZE 0x00000200
|
|
#define CYDEV_IO_PC_BASE 0x40005000
|
|
#define CYDEV_IO_PC_SIZE 0x00000080
|
|
#define CYDEV_IO_PC_PRT0_BASE 0x40005000
|
|
#define CYDEV_IO_PC_PRT0_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT0_PC0 0x40005000
|
|
#define CYDEV_IO_PC_PRT0_PC1 0x40005001
|
|
#define CYDEV_IO_PC_PRT0_PC2 0x40005002
|
|
#define CYDEV_IO_PC_PRT0_PC3 0x40005003
|
|
#define CYDEV_IO_PC_PRT0_PC4 0x40005004
|
|
#define CYDEV_IO_PC_PRT0_PC5 0x40005005
|
|
#define CYDEV_IO_PC_PRT0_PC6 0x40005006
|
|
#define CYDEV_IO_PC_PRT0_PC7 0x40005007
|
|
#define CYDEV_IO_PC_PRT1_BASE 0x40005008
|
|
#define CYDEV_IO_PC_PRT1_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT1_PC0 0x40005008
|
|
#define CYDEV_IO_PC_PRT1_PC1 0x40005009
|
|
#define CYDEV_IO_PC_PRT1_PC2 0x4000500a
|
|
#define CYDEV_IO_PC_PRT1_PC3 0x4000500b
|
|
#define CYDEV_IO_PC_PRT1_PC4 0x4000500c
|
|
#define CYDEV_IO_PC_PRT1_PC5 0x4000500d
|
|
#define CYDEV_IO_PC_PRT1_PC6 0x4000500e
|
|
#define CYDEV_IO_PC_PRT1_PC7 0x4000500f
|
|
#define CYDEV_IO_PC_PRT2_BASE 0x40005010
|
|
#define CYDEV_IO_PC_PRT2_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT2_PC0 0x40005010
|
|
#define CYDEV_IO_PC_PRT2_PC1 0x40005011
|
|
#define CYDEV_IO_PC_PRT2_PC2 0x40005012
|
|
#define CYDEV_IO_PC_PRT2_PC3 0x40005013
|
|
#define CYDEV_IO_PC_PRT2_PC4 0x40005014
|
|
#define CYDEV_IO_PC_PRT2_PC5 0x40005015
|
|
#define CYDEV_IO_PC_PRT2_PC6 0x40005016
|
|
#define CYDEV_IO_PC_PRT2_PC7 0x40005017
|
|
#define CYDEV_IO_PC_PRT3_BASE 0x40005018
|
|
#define CYDEV_IO_PC_PRT3_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT3_PC0 0x40005018
|
|
#define CYDEV_IO_PC_PRT3_PC1 0x40005019
|
|
#define CYDEV_IO_PC_PRT3_PC2 0x4000501a
|
|
#define CYDEV_IO_PC_PRT3_PC3 0x4000501b
|
|
#define CYDEV_IO_PC_PRT3_PC4 0x4000501c
|
|
#define CYDEV_IO_PC_PRT3_PC5 0x4000501d
|
|
#define CYDEV_IO_PC_PRT3_PC6 0x4000501e
|
|
#define CYDEV_IO_PC_PRT3_PC7 0x4000501f
|
|
#define CYDEV_IO_PC_PRT4_BASE 0x40005020
|
|
#define CYDEV_IO_PC_PRT4_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT4_PC0 0x40005020
|
|
#define CYDEV_IO_PC_PRT4_PC1 0x40005021
|
|
#define CYDEV_IO_PC_PRT4_PC2 0x40005022
|
|
#define CYDEV_IO_PC_PRT4_PC3 0x40005023
|
|
#define CYDEV_IO_PC_PRT4_PC4 0x40005024
|
|
#define CYDEV_IO_PC_PRT4_PC5 0x40005025
|
|
#define CYDEV_IO_PC_PRT4_PC6 0x40005026
|
|
#define CYDEV_IO_PC_PRT4_PC7 0x40005027
|
|
#define CYDEV_IO_PC_PRT5_BASE 0x40005028
|
|
#define CYDEV_IO_PC_PRT5_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT5_PC0 0x40005028
|
|
#define CYDEV_IO_PC_PRT5_PC1 0x40005029
|
|
#define CYDEV_IO_PC_PRT5_PC2 0x4000502a
|
|
#define CYDEV_IO_PC_PRT5_PC3 0x4000502b
|
|
#define CYDEV_IO_PC_PRT5_PC4 0x4000502c
|
|
#define CYDEV_IO_PC_PRT5_PC5 0x4000502d
|
|
#define CYDEV_IO_PC_PRT5_PC6 0x4000502e
|
|
#define CYDEV_IO_PC_PRT5_PC7 0x4000502f
|
|
#define CYDEV_IO_PC_PRT6_BASE 0x40005030
|
|
#define CYDEV_IO_PC_PRT6_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT6_PC0 0x40005030
|
|
#define CYDEV_IO_PC_PRT6_PC1 0x40005031
|
|
#define CYDEV_IO_PC_PRT6_PC2 0x40005032
|
|
#define CYDEV_IO_PC_PRT6_PC3 0x40005033
|
|
#define CYDEV_IO_PC_PRT6_PC4 0x40005034
|
|
#define CYDEV_IO_PC_PRT6_PC5 0x40005035
|
|
#define CYDEV_IO_PC_PRT6_PC6 0x40005036
|
|
#define CYDEV_IO_PC_PRT6_PC7 0x40005037
|
|
#define CYDEV_IO_PC_PRT12_BASE 0x40005060
|
|
#define CYDEV_IO_PC_PRT12_SIZE 0x00000008
|
|
#define CYDEV_IO_PC_PRT12_PC0 0x40005060
|
|
#define CYDEV_IO_PC_PRT12_PC1 0x40005061
|
|
#define CYDEV_IO_PC_PRT12_PC2 0x40005062
|
|
#define CYDEV_IO_PC_PRT12_PC3 0x40005063
|
|
#define CYDEV_IO_PC_PRT12_PC4 0x40005064
|
|
#define CYDEV_IO_PC_PRT12_PC5 0x40005065
|
|
#define CYDEV_IO_PC_PRT12_PC6 0x40005066
|
|
#define CYDEV_IO_PC_PRT12_PC7 0x40005067
|
|
#define CYDEV_IO_PC_PRT15_BASE 0x40005078
|
|
#define CYDEV_IO_PC_PRT15_SIZE 0x00000006
|
|
#define CYDEV_IO_PC_PRT15_PC0 0x40005078
|
|
#define CYDEV_IO_PC_PRT15_PC1 0x40005079
|
|
#define CYDEV_IO_PC_PRT15_PC2 0x4000507a
|
|
#define CYDEV_IO_PC_PRT15_PC3 0x4000507b
|
|
#define CYDEV_IO_PC_PRT15_PC4 0x4000507c
|
|
#define CYDEV_IO_PC_PRT15_PC5 0x4000507d
|
|
#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e
|
|
#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002
|
|
#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e
|
|
#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f
|
|
#define CYDEV_IO_DR_BASE 0x40005080
|
|
#define CYDEV_IO_DR_SIZE 0x00000010
|
|
#define CYDEV_IO_DR_PRT0_BASE 0x40005080
|
|
#define CYDEV_IO_DR_PRT0_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080
|
|
#define CYDEV_IO_DR_PRT1_BASE 0x40005081
|
|
#define CYDEV_IO_DR_PRT1_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081
|
|
#define CYDEV_IO_DR_PRT2_BASE 0x40005082
|
|
#define CYDEV_IO_DR_PRT2_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082
|
|
#define CYDEV_IO_DR_PRT3_BASE 0x40005083
|
|
#define CYDEV_IO_DR_PRT3_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083
|
|
#define CYDEV_IO_DR_PRT4_BASE 0x40005084
|
|
#define CYDEV_IO_DR_PRT4_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084
|
|
#define CYDEV_IO_DR_PRT5_BASE 0x40005085
|
|
#define CYDEV_IO_DR_PRT5_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085
|
|
#define CYDEV_IO_DR_PRT6_BASE 0x40005086
|
|
#define CYDEV_IO_DR_PRT6_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086
|
|
#define CYDEV_IO_DR_PRT12_BASE 0x4000508c
|
|
#define CYDEV_IO_DR_PRT12_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c
|
|
#define CYDEV_IO_DR_PRT15_BASE 0x4000508f
|
|
#define CYDEV_IO_DR_PRT15_SIZE 0x00000001
|
|
#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f
|
|
#define CYDEV_IO_PS_BASE 0x40005090
|
|
#define CYDEV_IO_PS_SIZE 0x00000010
|
|
#define CYDEV_IO_PS_PRT0_BASE 0x40005090
|
|
#define CYDEV_IO_PS_PRT0_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090
|
|
#define CYDEV_IO_PS_PRT1_BASE 0x40005091
|
|
#define CYDEV_IO_PS_PRT1_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091
|
|
#define CYDEV_IO_PS_PRT2_BASE 0x40005092
|
|
#define CYDEV_IO_PS_PRT2_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092
|
|
#define CYDEV_IO_PS_PRT3_BASE 0x40005093
|
|
#define CYDEV_IO_PS_PRT3_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093
|
|
#define CYDEV_IO_PS_PRT4_BASE 0x40005094
|
|
#define CYDEV_IO_PS_PRT4_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094
|
|
#define CYDEV_IO_PS_PRT5_BASE 0x40005095
|
|
#define CYDEV_IO_PS_PRT5_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095
|
|
#define CYDEV_IO_PS_PRT6_BASE 0x40005096
|
|
#define CYDEV_IO_PS_PRT6_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096
|
|
#define CYDEV_IO_PS_PRT12_BASE 0x4000509c
|
|
#define CYDEV_IO_PS_PRT12_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c
|
|
#define CYDEV_IO_PS_PRT15_BASE 0x4000509f
|
|
#define CYDEV_IO_PS_PRT15_SIZE 0x00000001
|
|
#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f
|
|
#define CYDEV_IO_PRT_BASE 0x40005100
|
|
#define CYDEV_IO_PRT_SIZE 0x00000100
|
|
#define CYDEV_IO_PRT_PRT0_BASE 0x40005100
|
|
#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT0_DR 0x40005100
|
|
#define CYDEV_IO_PRT_PRT0_PS 0x40005101
|
|
#define CYDEV_IO_PRT_PRT0_DM0 0x40005102
|
|
#define CYDEV_IO_PRT_PRT0_DM1 0x40005103
|
|
#define CYDEV_IO_PRT_PRT0_DM2 0x40005104
|
|
#define CYDEV_IO_PRT_PRT0_SLW 0x40005105
|
|
#define CYDEV_IO_PRT_PRT0_BYP 0x40005106
|
|
#define CYDEV_IO_PRT_PRT0_BIE 0x40005107
|
|
#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108
|
|
#define CYDEV_IO_PRT_PRT0_CTL 0x40005109
|
|
#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a
|
|
#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b
|
|
#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c
|
|
#define CYDEV_IO_PRT_PRT0_AG 0x4000510d
|
|
#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e
|
|
#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f
|
|
#define CYDEV_IO_PRT_PRT1_BASE 0x40005110
|
|
#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT1_DR 0x40005110
|
|
#define CYDEV_IO_PRT_PRT1_PS 0x40005111
|
|
#define CYDEV_IO_PRT_PRT1_DM0 0x40005112
|
|
#define CYDEV_IO_PRT_PRT1_DM1 0x40005113
|
|
#define CYDEV_IO_PRT_PRT1_DM2 0x40005114
|
|
#define CYDEV_IO_PRT_PRT1_SLW 0x40005115
|
|
#define CYDEV_IO_PRT_PRT1_BYP 0x40005116
|
|
#define CYDEV_IO_PRT_PRT1_BIE 0x40005117
|
|
#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118
|
|
#define CYDEV_IO_PRT_PRT1_CTL 0x40005119
|
|
#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a
|
|
#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b
|
|
#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c
|
|
#define CYDEV_IO_PRT_PRT1_AG 0x4000511d
|
|
#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e
|
|
#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f
|
|
#define CYDEV_IO_PRT_PRT2_BASE 0x40005120
|
|
#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT2_DR 0x40005120
|
|
#define CYDEV_IO_PRT_PRT2_PS 0x40005121
|
|
#define CYDEV_IO_PRT_PRT2_DM0 0x40005122
|
|
#define CYDEV_IO_PRT_PRT2_DM1 0x40005123
|
|
#define CYDEV_IO_PRT_PRT2_DM2 0x40005124
|
|
#define CYDEV_IO_PRT_PRT2_SLW 0x40005125
|
|
#define CYDEV_IO_PRT_PRT2_BYP 0x40005126
|
|
#define CYDEV_IO_PRT_PRT2_BIE 0x40005127
|
|
#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128
|
|
#define CYDEV_IO_PRT_PRT2_CTL 0x40005129
|
|
#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a
|
|
#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b
|
|
#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c
|
|
#define CYDEV_IO_PRT_PRT2_AG 0x4000512d
|
|
#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e
|
|
#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f
|
|
#define CYDEV_IO_PRT_PRT3_BASE 0x40005130
|
|
#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT3_DR 0x40005130
|
|
#define CYDEV_IO_PRT_PRT3_PS 0x40005131
|
|
#define CYDEV_IO_PRT_PRT3_DM0 0x40005132
|
|
#define CYDEV_IO_PRT_PRT3_DM1 0x40005133
|
|
#define CYDEV_IO_PRT_PRT3_DM2 0x40005134
|
|
#define CYDEV_IO_PRT_PRT3_SLW 0x40005135
|
|
#define CYDEV_IO_PRT_PRT3_BYP 0x40005136
|
|
#define CYDEV_IO_PRT_PRT3_BIE 0x40005137
|
|
#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138
|
|
#define CYDEV_IO_PRT_PRT3_CTL 0x40005139
|
|
#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a
|
|
#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b
|
|
#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c
|
|
#define CYDEV_IO_PRT_PRT3_AG 0x4000513d
|
|
#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e
|
|
#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f
|
|
#define CYDEV_IO_PRT_PRT4_BASE 0x40005140
|
|
#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT4_DR 0x40005140
|
|
#define CYDEV_IO_PRT_PRT4_PS 0x40005141
|
|
#define CYDEV_IO_PRT_PRT4_DM0 0x40005142
|
|
#define CYDEV_IO_PRT_PRT4_DM1 0x40005143
|
|
#define CYDEV_IO_PRT_PRT4_DM2 0x40005144
|
|
#define CYDEV_IO_PRT_PRT4_SLW 0x40005145
|
|
#define CYDEV_IO_PRT_PRT4_BYP 0x40005146
|
|
#define CYDEV_IO_PRT_PRT4_BIE 0x40005147
|
|
#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148
|
|
#define CYDEV_IO_PRT_PRT4_CTL 0x40005149
|
|
#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a
|
|
#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b
|
|
#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c
|
|
#define CYDEV_IO_PRT_PRT4_AG 0x4000514d
|
|
#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e
|
|
#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f
|
|
#define CYDEV_IO_PRT_PRT5_BASE 0x40005150
|
|
#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT5_DR 0x40005150
|
|
#define CYDEV_IO_PRT_PRT5_PS 0x40005151
|
|
#define CYDEV_IO_PRT_PRT5_DM0 0x40005152
|
|
#define CYDEV_IO_PRT_PRT5_DM1 0x40005153
|
|
#define CYDEV_IO_PRT_PRT5_DM2 0x40005154
|
|
#define CYDEV_IO_PRT_PRT5_SLW 0x40005155
|
|
#define CYDEV_IO_PRT_PRT5_BYP 0x40005156
|
|
#define CYDEV_IO_PRT_PRT5_BIE 0x40005157
|
|
#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158
|
|
#define CYDEV_IO_PRT_PRT5_CTL 0x40005159
|
|
#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a
|
|
#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b
|
|
#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c
|
|
#define CYDEV_IO_PRT_PRT5_AG 0x4000515d
|
|
#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e
|
|
#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f
|
|
#define CYDEV_IO_PRT_PRT6_BASE 0x40005160
|
|
#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT6_DR 0x40005160
|
|
#define CYDEV_IO_PRT_PRT6_PS 0x40005161
|
|
#define CYDEV_IO_PRT_PRT6_DM0 0x40005162
|
|
#define CYDEV_IO_PRT_PRT6_DM1 0x40005163
|
|
#define CYDEV_IO_PRT_PRT6_DM2 0x40005164
|
|
#define CYDEV_IO_PRT_PRT6_SLW 0x40005165
|
|
#define CYDEV_IO_PRT_PRT6_BYP 0x40005166
|
|
#define CYDEV_IO_PRT_PRT6_BIE 0x40005167
|
|
#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168
|
|
#define CYDEV_IO_PRT_PRT6_CTL 0x40005169
|
|
#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a
|
|
#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b
|
|
#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c
|
|
#define CYDEV_IO_PRT_PRT6_AG 0x4000516d
|
|
#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e
|
|
#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f
|
|
#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0
|
|
#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT12_DR 0x400051c0
|
|
#define CYDEV_IO_PRT_PRT12_PS 0x400051c1
|
|
#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2
|
|
#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3
|
|
#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4
|
|
#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5
|
|
#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6
|
|
#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7
|
|
#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8
|
|
#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9
|
|
#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca
|
|
#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb
|
|
#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc
|
|
#define CYDEV_IO_PRT_PRT12_AG 0x400051cd
|
|
#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce
|
|
#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf
|
|
#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0
|
|
#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010
|
|
#define CYDEV_IO_PRT_PRT15_DR 0x400051f0
|
|
#define CYDEV_IO_PRT_PRT15_PS 0x400051f1
|
|
#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2
|
|
#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3
|
|
#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4
|
|
#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5
|
|
#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6
|
|
#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7
|
|
#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8
|
|
#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9
|
|
#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa
|
|
#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb
|
|
#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc
|
|
#define CYDEV_IO_PRT_PRT15_AG 0x400051fd
|
|
#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe
|
|
#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff
|
|
#define CYDEV_PRTDSI_BASE 0x40005200
|
|
#define CYDEV_PRTDSI_SIZE 0x0000007f
|
|
#define CYDEV_PRTDSI_PRT0_BASE 0x40005200
|
|
#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200
|
|
#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201
|
|
#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202
|
|
#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203
|
|
#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204
|
|
#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205
|
|
#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206
|
|
#define CYDEV_PRTDSI_PRT1_BASE 0x40005208
|
|
#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208
|
|
#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209
|
|
#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a
|
|
#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b
|
|
#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c
|
|
#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d
|
|
#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e
|
|
#define CYDEV_PRTDSI_PRT2_BASE 0x40005210
|
|
#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210
|
|
#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211
|
|
#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212
|
|
#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213
|
|
#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214
|
|
#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215
|
|
#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216
|
|
#define CYDEV_PRTDSI_PRT3_BASE 0x40005218
|
|
#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218
|
|
#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219
|
|
#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a
|
|
#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b
|
|
#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c
|
|
#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d
|
|
#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e
|
|
#define CYDEV_PRTDSI_PRT4_BASE 0x40005220
|
|
#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220
|
|
#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221
|
|
#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222
|
|
#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223
|
|
#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224
|
|
#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225
|
|
#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226
|
|
#define CYDEV_PRTDSI_PRT5_BASE 0x40005228
|
|
#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228
|
|
#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229
|
|
#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a
|
|
#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b
|
|
#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c
|
|
#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d
|
|
#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e
|
|
#define CYDEV_PRTDSI_PRT6_BASE 0x40005230
|
|
#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230
|
|
#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231
|
|
#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232
|
|
#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233
|
|
#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234
|
|
#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235
|
|
#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236
|
|
#define CYDEV_PRTDSI_PRT12_BASE 0x40005260
|
|
#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006
|
|
#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260
|
|
#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261
|
|
#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262
|
|
#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263
|
|
#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264
|
|
#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265
|
|
#define CYDEV_PRTDSI_PRT15_BASE 0x40005278
|
|
#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007
|
|
#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278
|
|
#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279
|
|
#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a
|
|
#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b
|
|
#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c
|
|
#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d
|
|
#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e
|
|
#define CYDEV_EMIF_BASE 0x40005400
|
|
#define CYDEV_EMIF_SIZE 0x00000007
|
|
#define CYDEV_EMIF_NO_UDB 0x40005400
|
|
#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401
|
|
#define CYDEV_EMIF_MEM_DWN 0x40005402
|
|
#define CYDEV_EMIF_MEMCLK_DIV 0x40005403
|
|
#define CYDEV_EMIF_CLOCK_EN 0x40005404
|
|
#define CYDEV_EMIF_EM_TYPE 0x40005405
|
|
#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406
|
|
#define CYDEV_ANAIF_BASE 0x40005800
|
|
#define CYDEV_ANAIF_SIZE 0x000003a9
|
|
#define CYDEV_ANAIF_CFG_BASE 0x40005800
|
|
#define CYDEV_ANAIF_CFG_SIZE 0x0000010f
|
|
#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800
|
|
#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800
|
|
#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801
|
|
#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802
|
|
#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804
|
|
#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804
|
|
#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805
|
|
#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806
|
|
#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808
|
|
#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808
|
|
#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809
|
|
#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a
|
|
#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c
|
|
#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c
|
|
#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d
|
|
#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e
|
|
#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820
|
|
#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820
|
|
#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821
|
|
#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822
|
|
#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824
|
|
#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824
|
|
#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825
|
|
#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826
|
|
#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828
|
|
#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828
|
|
#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829
|
|
#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a
|
|
#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c
|
|
#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003
|
|
#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c
|
|
#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d
|
|
#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e
|
|
#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840
|
|
#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840
|
|
#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841
|
|
#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841
|
|
#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842
|
|
#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842
|
|
#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843
|
|
#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843
|
|
#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848
|
|
#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848
|
|
#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849
|
|
#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a
|
|
#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a
|
|
#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b
|
|
#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c
|
|
#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c
|
|
#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d
|
|
#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e
|
|
#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e
|
|
#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f
|
|
#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858
|
|
#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858
|
|
#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859
|
|
#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a
|
|
#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a
|
|
#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b
|
|
#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c
|
|
#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c
|
|
#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d
|
|
#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e
|
|
#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e
|
|
#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f
|
|
#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868
|
|
#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868
|
|
#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869
|
|
#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a
|
|
#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a
|
|
#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b
|
|
#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b
|
|
#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c
|
|
#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004
|
|
#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c
|
|
#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d
|
|
#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e
|
|
#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f
|
|
#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870
|
|
#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870
|
|
#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871
|
|
#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872
|
|
#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872
|
|
#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873
|
|
#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876
|
|
#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876
|
|
#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877
|
|
#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878
|
|
#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878
|
|
#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879
|
|
#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a
|
|
#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a
|
|
#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b
|
|
#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c
|
|
#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c
|
|
#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880
|
|
#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890
|
|
#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891
|
|
#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892
|
|
#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893
|
|
#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894
|
|
#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895
|
|
#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896
|
|
#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897
|
|
#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898
|
|
#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899
|
|
#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a
|
|
#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b
|
|
#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c
|
|
#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d
|
|
#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e
|
|
#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f
|
|
#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900
|
|
#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905
|
|
#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906
|
|
#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908
|
|
#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d
|
|
#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e
|
|
#define CYDEV_ANAIF_RT_BASE 0x40005a00
|
|
#define CYDEV_ANAIF_RT_SIZE 0x00000162
|
|
#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00
|
|
#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d
|
|
#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00
|
|
#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02
|
|
#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03
|
|
#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04
|
|
#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06
|
|
#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07
|
|
#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08
|
|
#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a
|
|
#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b
|
|
#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c
|
|
#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10
|
|
#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d
|
|
#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10
|
|
#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12
|
|
#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13
|
|
#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14
|
|
#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16
|
|
#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17
|
|
#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18
|
|
#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a
|
|
#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b
|
|
#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c
|
|
#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20
|
|
#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d
|
|
#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20
|
|
#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22
|
|
#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23
|
|
#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24
|
|
#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26
|
|
#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27
|
|
#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28
|
|
#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a
|
|
#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b
|
|
#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c
|
|
#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30
|
|
#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d
|
|
#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30
|
|
#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32
|
|
#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33
|
|
#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34
|
|
#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36
|
|
#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37
|
|
#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38
|
|
#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a
|
|
#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b
|
|
#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c
|
|
#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80
|
|
#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80
|
|
#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82
|
|
#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83
|
|
#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84
|
|
#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87
|
|
#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88
|
|
#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88
|
|
#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a
|
|
#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b
|
|
#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c
|
|
#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f
|
|
#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90
|
|
#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90
|
|
#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92
|
|
#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93
|
|
#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94
|
|
#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97
|
|
#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98
|
|
#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98
|
|
#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a
|
|
#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b
|
|
#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c
|
|
#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f
|
|
#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0
|
|
#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0
|
|
#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2
|
|
#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3
|
|
#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4
|
|
#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6
|
|
#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7
|
|
#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8
|
|
#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8
|
|
#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca
|
|
#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb
|
|
#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc
|
|
#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace
|
|
#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf
|
|
#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0
|
|
#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0
|
|
#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2
|
|
#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3
|
|
#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4
|
|
#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6
|
|
#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7
|
|
#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8
|
|
#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8
|
|
#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada
|
|
#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb
|
|
#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc
|
|
#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade
|
|
#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf
|
|
#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00
|
|
#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00
|
|
#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02
|
|
#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03
|
|
#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04
|
|
#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06
|
|
#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07
|
|
#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20
|
|
#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20
|
|
#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22
|
|
#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23
|
|
#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24
|
|
#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26
|
|
#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27
|
|
#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28
|
|
#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008
|
|
#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28
|
|
#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a
|
|
#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b
|
|
#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c
|
|
#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e
|
|
#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f
|
|
#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40
|
|
#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40
|
|
#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41
|
|
#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42
|
|
#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42
|
|
#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43
|
|
#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44
|
|
#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44
|
|
#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45
|
|
#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46
|
|
#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46
|
|
#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47
|
|
#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53
|
|
#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54
|
|
#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56
|
|
#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56
|
|
#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58
|
|
#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004
|
|
#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58
|
|
#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a
|
|
#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b
|
|
#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c
|
|
#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006
|
|
#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c
|
|
#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d
|
|
#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e
|
|
#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f
|
|
#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60
|
|
#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61
|
|
#define CYDEV_ANAIF_WRK_BASE 0x40005b80
|
|
#define CYDEV_ANAIF_WRK_SIZE 0x00000029
|
|
#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80
|
|
#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80
|
|
#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81
|
|
#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81
|
|
#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82
|
|
#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82
|
|
#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83
|
|
#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83
|
|
#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88
|
|
#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88
|
|
#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89
|
|
#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90
|
|
#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005
|
|
#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90
|
|
#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91
|
|
#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92
|
|
#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93
|
|
#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94
|
|
#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96
|
|
#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96
|
|
#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97
|
|
#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98
|
|
#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005
|
|
#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98
|
|
#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99
|
|
#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a
|
|
#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b
|
|
#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c
|
|
#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0
|
|
#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0
|
|
#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1
|
|
#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2
|
|
#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002
|
|
#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2
|
|
#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3
|
|
#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8
|
|
#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001
|
|
#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8
|
|
#define CYDEV_USB_BASE 0x40006000
|
|
#define CYDEV_USB_SIZE 0x00000300
|
|
#define CYDEV_USB_EP0_DR0 0x40006000
|
|
#define CYDEV_USB_EP0_DR1 0x40006001
|
|
#define CYDEV_USB_EP0_DR2 0x40006002
|
|
#define CYDEV_USB_EP0_DR3 0x40006003
|
|
#define CYDEV_USB_EP0_DR4 0x40006004
|
|
#define CYDEV_USB_EP0_DR5 0x40006005
|
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#define CYDEV_USB_EP0_DR6 0x40006006
|
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#define CYDEV_USB_EP0_DR7 0x40006007
|
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#define CYDEV_USB_CR0 0x40006008
|
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#define CYDEV_USB_CR1 0x40006009
|
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#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a
|
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#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b
|
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#define CYDEV_USB_SIE_EP1_BASE 0x4000600c
|
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#define CYDEV_USB_SIE_EP1_SIZE 0x00000003
|
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#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c
|
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#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d
|
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#define CYDEV_USB_SIE_EP1_CR0 0x4000600e
|
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#define CYDEV_USB_USBIO_CR0 0x40006010
|
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#define CYDEV_USB_USBIO_CR1 0x40006012
|
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#define CYDEV_USB_DYN_RECONFIG 0x40006014
|
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#define CYDEV_USB_SOF0 0x40006018
|
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#define CYDEV_USB_SOF1 0x40006019
|
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#define CYDEV_USB_SIE_EP2_BASE 0x4000601c
|
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#define CYDEV_USB_SIE_EP2_SIZE 0x00000003
|
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#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c
|
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#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d
|
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#define CYDEV_USB_SIE_EP2_CR0 0x4000601e
|
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#define CYDEV_USB_EP0_CR 0x40006028
|
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#define CYDEV_USB_EP0_CNT 0x40006029
|
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#define CYDEV_USB_SIE_EP3_BASE 0x4000602c
|
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#define CYDEV_USB_SIE_EP3_SIZE 0x00000003
|
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#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c
|
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#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d
|
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#define CYDEV_USB_SIE_EP3_CR0 0x4000602e
|
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#define CYDEV_USB_SIE_EP4_BASE 0x4000603c
|
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#define CYDEV_USB_SIE_EP4_SIZE 0x00000003
|
|
#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c
|
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#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d
|
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#define CYDEV_USB_SIE_EP4_CR0 0x4000603e
|
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#define CYDEV_USB_SIE_EP5_BASE 0x4000604c
|
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#define CYDEV_USB_SIE_EP5_SIZE 0x00000003
|
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#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c
|
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#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d
|
|
#define CYDEV_USB_SIE_EP5_CR0 0x4000604e
|
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#define CYDEV_USB_SIE_EP6_BASE 0x4000605c
|
|
#define CYDEV_USB_SIE_EP6_SIZE 0x00000003
|
|
#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c
|
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#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d
|
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#define CYDEV_USB_SIE_EP6_CR0 0x4000605e
|
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#define CYDEV_USB_SIE_EP7_BASE 0x4000606c
|
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#define CYDEV_USB_SIE_EP7_SIZE 0x00000003
|
|
#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c
|
|
#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d
|
|
#define CYDEV_USB_SIE_EP7_CR0 0x4000606e
|
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#define CYDEV_USB_SIE_EP8_BASE 0x4000607c
|
|
#define CYDEV_USB_SIE_EP8_SIZE 0x00000003
|
|
#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c
|
|
#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d
|
|
#define CYDEV_USB_SIE_EP8_CR0 0x4000607e
|
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#define CYDEV_USB_ARB_EP1_BASE 0x40006080
|
|
#define CYDEV_USB_ARB_EP1_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP1_CFG 0x40006080
|
|
#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081
|
|
#define CYDEV_USB_ARB_EP1_SR 0x40006082
|
|
#define CYDEV_USB_ARB_RW1_BASE 0x40006084
|
|
#define CYDEV_USB_ARB_RW1_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW1_WA 0x40006084
|
|
#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085
|
|
#define CYDEV_USB_ARB_RW1_RA 0x40006086
|
|
#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087
|
|
#define CYDEV_USB_ARB_RW1_DR 0x40006088
|
|
#define CYDEV_USB_BUF_SIZE 0x4000608c
|
|
#define CYDEV_USB_EP_ACTIVE 0x4000608e
|
|
#define CYDEV_USB_EP_TYPE 0x4000608f
|
|
#define CYDEV_USB_ARB_EP2_BASE 0x40006090
|
|
#define CYDEV_USB_ARB_EP2_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP2_CFG 0x40006090
|
|
#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091
|
|
#define CYDEV_USB_ARB_EP2_SR 0x40006092
|
|
#define CYDEV_USB_ARB_RW2_BASE 0x40006094
|
|
#define CYDEV_USB_ARB_RW2_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW2_WA 0x40006094
|
|
#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095
|
|
#define CYDEV_USB_ARB_RW2_RA 0x40006096
|
|
#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097
|
|
#define CYDEV_USB_ARB_RW2_DR 0x40006098
|
|
#define CYDEV_USB_ARB_CFG 0x4000609c
|
|
#define CYDEV_USB_USB_CLK_EN 0x4000609d
|
|
#define CYDEV_USB_ARB_INT_EN 0x4000609e
|
|
#define CYDEV_USB_ARB_INT_SR 0x4000609f
|
|
#define CYDEV_USB_ARB_EP3_BASE 0x400060a0
|
|
#define CYDEV_USB_ARB_EP3_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP3_CFG 0x400060a0
|
|
#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1
|
|
#define CYDEV_USB_ARB_EP3_SR 0x400060a2
|
|
#define CYDEV_USB_ARB_RW3_BASE 0x400060a4
|
|
#define CYDEV_USB_ARB_RW3_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW3_WA 0x400060a4
|
|
#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5
|
|
#define CYDEV_USB_ARB_RW3_RA 0x400060a6
|
|
#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7
|
|
#define CYDEV_USB_ARB_RW3_DR 0x400060a8
|
|
#define CYDEV_USB_CWA 0x400060ac
|
|
#define CYDEV_USB_CWA_MSB 0x400060ad
|
|
#define CYDEV_USB_ARB_EP4_BASE 0x400060b0
|
|
#define CYDEV_USB_ARB_EP4_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP4_CFG 0x400060b0
|
|
#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1
|
|
#define CYDEV_USB_ARB_EP4_SR 0x400060b2
|
|
#define CYDEV_USB_ARB_RW4_BASE 0x400060b4
|
|
#define CYDEV_USB_ARB_RW4_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW4_WA 0x400060b4
|
|
#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5
|
|
#define CYDEV_USB_ARB_RW4_RA 0x400060b6
|
|
#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7
|
|
#define CYDEV_USB_ARB_RW4_DR 0x400060b8
|
|
#define CYDEV_USB_DMA_THRES 0x400060bc
|
|
#define CYDEV_USB_DMA_THRES_MSB 0x400060bd
|
|
#define CYDEV_USB_ARB_EP5_BASE 0x400060c0
|
|
#define CYDEV_USB_ARB_EP5_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP5_CFG 0x400060c0
|
|
#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1
|
|
#define CYDEV_USB_ARB_EP5_SR 0x400060c2
|
|
#define CYDEV_USB_ARB_RW5_BASE 0x400060c4
|
|
#define CYDEV_USB_ARB_RW5_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW5_WA 0x400060c4
|
|
#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5
|
|
#define CYDEV_USB_ARB_RW5_RA 0x400060c6
|
|
#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7
|
|
#define CYDEV_USB_ARB_RW5_DR 0x400060c8
|
|
#define CYDEV_USB_BUS_RST_CNT 0x400060cc
|
|
#define CYDEV_USB_ARB_EP6_BASE 0x400060d0
|
|
#define CYDEV_USB_ARB_EP6_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP6_CFG 0x400060d0
|
|
#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1
|
|
#define CYDEV_USB_ARB_EP6_SR 0x400060d2
|
|
#define CYDEV_USB_ARB_RW6_BASE 0x400060d4
|
|
#define CYDEV_USB_ARB_RW6_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW6_WA 0x400060d4
|
|
#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5
|
|
#define CYDEV_USB_ARB_RW6_RA 0x400060d6
|
|
#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7
|
|
#define CYDEV_USB_ARB_RW6_DR 0x400060d8
|
|
#define CYDEV_USB_ARB_EP7_BASE 0x400060e0
|
|
#define CYDEV_USB_ARB_EP7_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP7_CFG 0x400060e0
|
|
#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1
|
|
#define CYDEV_USB_ARB_EP7_SR 0x400060e2
|
|
#define CYDEV_USB_ARB_RW7_BASE 0x400060e4
|
|
#define CYDEV_USB_ARB_RW7_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW7_WA 0x400060e4
|
|
#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5
|
|
#define CYDEV_USB_ARB_RW7_RA 0x400060e6
|
|
#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7
|
|
#define CYDEV_USB_ARB_RW7_DR 0x400060e8
|
|
#define CYDEV_USB_ARB_EP8_BASE 0x400060f0
|
|
#define CYDEV_USB_ARB_EP8_SIZE 0x00000003
|
|
#define CYDEV_USB_ARB_EP8_CFG 0x400060f0
|
|
#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1
|
|
#define CYDEV_USB_ARB_EP8_SR 0x400060f2
|
|
#define CYDEV_USB_ARB_RW8_BASE 0x400060f4
|
|
#define CYDEV_USB_ARB_RW8_SIZE 0x00000005
|
|
#define CYDEV_USB_ARB_RW8_WA 0x400060f4
|
|
#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5
|
|
#define CYDEV_USB_ARB_RW8_RA 0x400060f6
|
|
#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7
|
|
#define CYDEV_USB_ARB_RW8_DR 0x400060f8
|
|
#define CYDEV_USB_MEM_BASE 0x40006100
|
|
#define CYDEV_USB_MEM_SIZE 0x00000200
|
|
#define CYDEV_USB_MEM_DATA_MBASE 0x40006100
|
|
#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200
|
|
#define CYDEV_UWRK_BASE 0x40006400
|
|
#define CYDEV_UWRK_SIZE 0x00000b60
|
|
#define CYDEV_UWRK_UWRK8_BASE 0x40006400
|
|
#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0
|
|
#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400
|
|
#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e
|
|
#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f
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#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460
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#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461
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#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462
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#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463
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#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464
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#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465
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#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466
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#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467
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#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468
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#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469
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#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a
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#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b
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#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c
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#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d
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#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e
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#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f
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#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470
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#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471
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#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472
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#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473
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#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474
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#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475
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#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476
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#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477
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#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478
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#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479
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#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a
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#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b
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#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c
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#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d
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#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e
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#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f
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#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480
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#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481
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#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482
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#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483
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#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484
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#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485
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#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486
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#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487
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#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488
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#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489
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#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a
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#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b
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#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c
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#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d
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#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e
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#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f
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#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490
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#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491
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#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492
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#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493
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#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494
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#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495
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#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496
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#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497
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#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498
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#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499
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#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a
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#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b
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#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c
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#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d
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#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e
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#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f
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#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0
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#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1
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#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2
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#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3
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#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4
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#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5
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#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6
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#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7
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#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8
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#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9
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#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa
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#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab
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#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac
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#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad
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#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae
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#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af
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#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500
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#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0
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#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504
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#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505
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#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506
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#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507
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#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508
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#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509
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#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514
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#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515
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#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516
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#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517
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#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518
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#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519
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#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524
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#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525
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#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526
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#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527
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#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528
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#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529
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#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534
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#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535
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#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536
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#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537
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#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538
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#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539
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#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544
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#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545
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#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546
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#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547
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#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548
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#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549
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#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554
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#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555
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#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556
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#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557
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#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558
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#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559
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#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564
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#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565
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#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566
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#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567
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#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568
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#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569
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#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574
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#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575
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#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576
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#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577
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#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578
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#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579
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#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584
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#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585
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#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586
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#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587
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#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588
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#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589
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#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594
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#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595
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#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596
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#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597
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#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598
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#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599
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#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a
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#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b
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#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4
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#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5
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#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6
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#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7
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#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8
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#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9
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#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa
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#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab
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#define CYDEV_UWRK_UWRK16_BASE 0x40006800
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#define CYDEV_UWRK_UWRK16_SIZE 0x00000760
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#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800
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#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760
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#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800
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#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c
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#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e
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#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00
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#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54
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#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56
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#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800
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#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e
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#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800
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#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a
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#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c
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#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00
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#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54
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#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56
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#define CYDEV_PHUB_BASE 0x40007000
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#define CYDEV_PHUB_SIZE 0x00000c00
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#define CYDEV_PHUB_CFG 0x40007000
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#define CYDEV_PHUB_ERR 0x40007004
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#define CYDEV_PHUB_ERR_ADR 0x40007008
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#define CYDEV_PHUB_CH0_BASE 0x40007010
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#define CYDEV_PHUB_CH0_SIZE 0x0000000c
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#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010
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#define CYDEV_PHUB_CH0_ACTION 0x40007014
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#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018
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#define CYDEV_PHUB_CH1_BASE 0x40007020
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#define CYDEV_PHUB_CH1_SIZE 0x0000000c
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#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020
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#define CYDEV_PHUB_CH1_ACTION 0x40007024
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#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028
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#define CYDEV_PHUB_CH2_BASE 0x40007030
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#define CYDEV_PHUB_CH2_SIZE 0x0000000c
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#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030
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#define CYDEV_PHUB_CH2_ACTION 0x40007034
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#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038
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#define CYDEV_PHUB_CH3_BASE 0x40007040
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#define CYDEV_PHUB_CH3_SIZE 0x0000000c
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#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040
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#define CYDEV_PHUB_CH3_ACTION 0x40007044
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#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048
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#define CYDEV_PHUB_CH4_BASE 0x40007050
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#define CYDEV_PHUB_CH4_SIZE 0x0000000c
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#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050
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#define CYDEV_PHUB_CH4_ACTION 0x40007054
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#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058
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#define CYDEV_PHUB_CH5_BASE 0x40007060
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#define CYDEV_PHUB_CH5_SIZE 0x0000000c
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#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060
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#define CYDEV_PHUB_CH5_ACTION 0x40007064
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#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068
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#define CYDEV_PHUB_CH6_BASE 0x40007070
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#define CYDEV_PHUB_CH6_SIZE 0x0000000c
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#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070
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#define CYDEV_PHUB_CH6_ACTION 0x40007074
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#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078
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#define CYDEV_PHUB_CH7_BASE 0x40007080
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#define CYDEV_PHUB_CH7_SIZE 0x0000000c
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#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080
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#define CYDEV_PHUB_CH7_ACTION 0x40007084
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#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088
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#define CYDEV_PHUB_CH8_BASE 0x40007090
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#define CYDEV_PHUB_CH8_SIZE 0x0000000c
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#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090
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#define CYDEV_PHUB_CH8_ACTION 0x40007094
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#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098
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#define CYDEV_PHUB_CH9_BASE 0x400070a0
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#define CYDEV_PHUB_CH9_SIZE 0x0000000c
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#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0
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#define CYDEV_PHUB_CH9_ACTION 0x400070a4
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#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8
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#define CYDEV_PHUB_CH10_BASE 0x400070b0
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#define CYDEV_PHUB_CH10_SIZE 0x0000000c
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#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0
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#define CYDEV_PHUB_CH10_ACTION 0x400070b4
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#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8
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#define CYDEV_PHUB_CH11_BASE 0x400070c0
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#define CYDEV_PHUB_CH11_SIZE 0x0000000c
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#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0
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#define CYDEV_PHUB_CH11_ACTION 0x400070c4
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#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8
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#define CYDEV_PHUB_CH12_BASE 0x400070d0
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#define CYDEV_PHUB_CH12_SIZE 0x0000000c
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#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0
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#define CYDEV_PHUB_CH12_ACTION 0x400070d4
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#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8
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#define CYDEV_PHUB_CH13_BASE 0x400070e0
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#define CYDEV_PHUB_CH13_SIZE 0x0000000c
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#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0
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#define CYDEV_PHUB_CH13_ACTION 0x400070e4
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#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8
|
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#define CYDEV_PHUB_CH14_BASE 0x400070f0
|
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#define CYDEV_PHUB_CH14_SIZE 0x0000000c
|
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#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0
|
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#define CYDEV_PHUB_CH14_ACTION 0x400070f4
|
|
#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8
|
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#define CYDEV_PHUB_CH15_BASE 0x40007100
|
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#define CYDEV_PHUB_CH15_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100
|
|
#define CYDEV_PHUB_CH15_ACTION 0x40007104
|
|
#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108
|
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#define CYDEV_PHUB_CH16_BASE 0x40007110
|
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#define CYDEV_PHUB_CH16_SIZE 0x0000000c
|
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#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110
|
|
#define CYDEV_PHUB_CH16_ACTION 0x40007114
|
|
#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118
|
|
#define CYDEV_PHUB_CH17_BASE 0x40007120
|
|
#define CYDEV_PHUB_CH17_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120
|
|
#define CYDEV_PHUB_CH17_ACTION 0x40007124
|
|
#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128
|
|
#define CYDEV_PHUB_CH18_BASE 0x40007130
|
|
#define CYDEV_PHUB_CH18_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130
|
|
#define CYDEV_PHUB_CH18_ACTION 0x40007134
|
|
#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138
|
|
#define CYDEV_PHUB_CH19_BASE 0x40007140
|
|
#define CYDEV_PHUB_CH19_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140
|
|
#define CYDEV_PHUB_CH19_ACTION 0x40007144
|
|
#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148
|
|
#define CYDEV_PHUB_CH20_BASE 0x40007150
|
|
#define CYDEV_PHUB_CH20_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150
|
|
#define CYDEV_PHUB_CH20_ACTION 0x40007154
|
|
#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158
|
|
#define CYDEV_PHUB_CH21_BASE 0x40007160
|
|
#define CYDEV_PHUB_CH21_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160
|
|
#define CYDEV_PHUB_CH21_ACTION 0x40007164
|
|
#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168
|
|
#define CYDEV_PHUB_CH22_BASE 0x40007170
|
|
#define CYDEV_PHUB_CH22_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170
|
|
#define CYDEV_PHUB_CH22_ACTION 0x40007174
|
|
#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178
|
|
#define CYDEV_PHUB_CH23_BASE 0x40007180
|
|
#define CYDEV_PHUB_CH23_SIZE 0x0000000c
|
|
#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180
|
|
#define CYDEV_PHUB_CH23_ACTION 0x40007184
|
|
#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188
|
|
#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600
|
|
#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600
|
|
#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604
|
|
#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608
|
|
#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608
|
|
#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c
|
|
#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610
|
|
#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610
|
|
#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614
|
|
#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618
|
|
#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618
|
|
#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c
|
|
#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620
|
|
#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620
|
|
#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624
|
|
#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628
|
|
#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628
|
|
#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c
|
|
#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630
|
|
#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630
|
|
#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634
|
|
#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638
|
|
#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638
|
|
#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c
|
|
#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640
|
|
#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640
|
|
#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644
|
|
#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648
|
|
#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648
|
|
#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c
|
|
#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650
|
|
#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650
|
|
#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654
|
|
#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658
|
|
#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658
|
|
#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c
|
|
#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660
|
|
#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660
|
|
#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664
|
|
#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668
|
|
#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668
|
|
#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c
|
|
#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670
|
|
#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670
|
|
#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674
|
|
#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678
|
|
#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678
|
|
#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c
|
|
#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680
|
|
#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680
|
|
#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684
|
|
#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688
|
|
#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688
|
|
#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c
|
|
#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690
|
|
#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690
|
|
#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694
|
|
#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698
|
|
#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698
|
|
#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c
|
|
#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0
|
|
#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0
|
|
#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4
|
|
#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8
|
|
#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8
|
|
#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac
|
|
#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0
|
|
#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0
|
|
#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4
|
|
#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8
|
|
#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008
|
|
#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8
|
|
#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc
|
|
#define CYDEV_PHUB_TDMEM0_BASE 0x40007800
|
|
#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800
|
|
#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804
|
|
#define CYDEV_PHUB_TDMEM1_BASE 0x40007808
|
|
#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808
|
|
#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c
|
|
#define CYDEV_PHUB_TDMEM2_BASE 0x40007810
|
|
#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810
|
|
#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814
|
|
#define CYDEV_PHUB_TDMEM3_BASE 0x40007818
|
|
#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818
|
|
#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c
|
|
#define CYDEV_PHUB_TDMEM4_BASE 0x40007820
|
|
#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820
|
|
#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824
|
|
#define CYDEV_PHUB_TDMEM5_BASE 0x40007828
|
|
#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828
|
|
#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c
|
|
#define CYDEV_PHUB_TDMEM6_BASE 0x40007830
|
|
#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830
|
|
#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834
|
|
#define CYDEV_PHUB_TDMEM7_BASE 0x40007838
|
|
#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838
|
|
#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c
|
|
#define CYDEV_PHUB_TDMEM8_BASE 0x40007840
|
|
#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840
|
|
#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844
|
|
#define CYDEV_PHUB_TDMEM9_BASE 0x40007848
|
|
#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848
|
|
#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c
|
|
#define CYDEV_PHUB_TDMEM10_BASE 0x40007850
|
|
#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850
|
|
#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854
|
|
#define CYDEV_PHUB_TDMEM11_BASE 0x40007858
|
|
#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858
|
|
#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c
|
|
#define CYDEV_PHUB_TDMEM12_BASE 0x40007860
|
|
#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860
|
|
#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864
|
|
#define CYDEV_PHUB_TDMEM13_BASE 0x40007868
|
|
#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868
|
|
#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c
|
|
#define CYDEV_PHUB_TDMEM14_BASE 0x40007870
|
|
#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870
|
|
#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874
|
|
#define CYDEV_PHUB_TDMEM15_BASE 0x40007878
|
|
#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878
|
|
#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c
|
|
#define CYDEV_PHUB_TDMEM16_BASE 0x40007880
|
|
#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880
|
|
#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884
|
|
#define CYDEV_PHUB_TDMEM17_BASE 0x40007888
|
|
#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888
|
|
#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c
|
|
#define CYDEV_PHUB_TDMEM18_BASE 0x40007890
|
|
#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890
|
|
#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894
|
|
#define CYDEV_PHUB_TDMEM19_BASE 0x40007898
|
|
#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898
|
|
#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c
|
|
#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0
|
|
#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0
|
|
#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4
|
|
#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8
|
|
#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8
|
|
#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac
|
|
#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0
|
|
#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0
|
|
#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4
|
|
#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8
|
|
#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8
|
|
#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc
|
|
#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0
|
|
#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0
|
|
#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4
|
|
#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8
|
|
#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8
|
|
#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc
|
|
#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0
|
|
#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0
|
|
#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4
|
|
#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8
|
|
#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8
|
|
#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc
|
|
#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0
|
|
#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0
|
|
#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4
|
|
#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8
|
|
#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8
|
|
#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec
|
|
#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0
|
|
#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0
|
|
#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4
|
|
#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8
|
|
#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8
|
|
#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc
|
|
#define CYDEV_PHUB_TDMEM32_BASE 0x40007900
|
|
#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900
|
|
#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904
|
|
#define CYDEV_PHUB_TDMEM33_BASE 0x40007908
|
|
#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908
|
|
#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c
|
|
#define CYDEV_PHUB_TDMEM34_BASE 0x40007910
|
|
#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910
|
|
#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914
|
|
#define CYDEV_PHUB_TDMEM35_BASE 0x40007918
|
|
#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918
|
|
#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c
|
|
#define CYDEV_PHUB_TDMEM36_BASE 0x40007920
|
|
#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920
|
|
#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924
|
|
#define CYDEV_PHUB_TDMEM37_BASE 0x40007928
|
|
#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928
|
|
#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c
|
|
#define CYDEV_PHUB_TDMEM38_BASE 0x40007930
|
|
#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930
|
|
#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934
|
|
#define CYDEV_PHUB_TDMEM39_BASE 0x40007938
|
|
#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938
|
|
#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c
|
|
#define CYDEV_PHUB_TDMEM40_BASE 0x40007940
|
|
#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940
|
|
#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944
|
|
#define CYDEV_PHUB_TDMEM41_BASE 0x40007948
|
|
#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948
|
|
#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c
|
|
#define CYDEV_PHUB_TDMEM42_BASE 0x40007950
|
|
#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950
|
|
#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954
|
|
#define CYDEV_PHUB_TDMEM43_BASE 0x40007958
|
|
#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958
|
|
#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c
|
|
#define CYDEV_PHUB_TDMEM44_BASE 0x40007960
|
|
#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960
|
|
#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964
|
|
#define CYDEV_PHUB_TDMEM45_BASE 0x40007968
|
|
#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968
|
|
#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c
|
|
#define CYDEV_PHUB_TDMEM46_BASE 0x40007970
|
|
#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970
|
|
#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974
|
|
#define CYDEV_PHUB_TDMEM47_BASE 0x40007978
|
|
#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978
|
|
#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c
|
|
#define CYDEV_PHUB_TDMEM48_BASE 0x40007980
|
|
#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980
|
|
#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984
|
|
#define CYDEV_PHUB_TDMEM49_BASE 0x40007988
|
|
#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988
|
|
#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c
|
|
#define CYDEV_PHUB_TDMEM50_BASE 0x40007990
|
|
#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990
|
|
#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994
|
|
#define CYDEV_PHUB_TDMEM51_BASE 0x40007998
|
|
#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998
|
|
#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c
|
|
#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0
|
|
#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0
|
|
#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4
|
|
#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8
|
|
#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8
|
|
#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac
|
|
#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0
|
|
#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0
|
|
#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4
|
|
#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8
|
|
#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8
|
|
#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc
|
|
#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0
|
|
#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0
|
|
#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4
|
|
#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8
|
|
#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8
|
|
#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc
|
|
#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0
|
|
#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0
|
|
#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4
|
|
#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8
|
|
#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8
|
|
#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc
|
|
#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0
|
|
#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0
|
|
#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4
|
|
#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8
|
|
#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8
|
|
#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec
|
|
#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0
|
|
#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0
|
|
#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4
|
|
#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8
|
|
#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8
|
|
#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc
|
|
#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00
|
|
#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00
|
|
#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04
|
|
#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08
|
|
#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08
|
|
#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c
|
|
#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10
|
|
#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10
|
|
#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14
|
|
#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18
|
|
#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18
|
|
#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c
|
|
#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20
|
|
#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20
|
|
#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24
|
|
#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28
|
|
#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28
|
|
#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c
|
|
#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30
|
|
#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30
|
|
#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34
|
|
#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38
|
|
#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38
|
|
#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c
|
|
#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40
|
|
#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40
|
|
#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44
|
|
#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48
|
|
#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48
|
|
#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c
|
|
#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50
|
|
#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50
|
|
#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54
|
|
#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58
|
|
#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58
|
|
#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c
|
|
#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60
|
|
#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60
|
|
#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64
|
|
#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68
|
|
#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68
|
|
#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c
|
|
#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70
|
|
#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70
|
|
#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74
|
|
#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78
|
|
#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78
|
|
#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c
|
|
#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80
|
|
#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80
|
|
#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84
|
|
#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88
|
|
#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88
|
|
#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c
|
|
#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90
|
|
#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90
|
|
#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94
|
|
#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98
|
|
#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98
|
|
#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c
|
|
#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0
|
|
#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0
|
|
#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4
|
|
#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8
|
|
#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8
|
|
#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac
|
|
#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0
|
|
#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0
|
|
#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4
|
|
#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8
|
|
#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8
|
|
#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc
|
|
#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0
|
|
#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0
|
|
#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4
|
|
#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8
|
|
#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8
|
|
#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc
|
|
#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0
|
|
#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0
|
|
#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4
|
|
#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8
|
|
#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8
|
|
#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc
|
|
#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0
|
|
#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0
|
|
#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4
|
|
#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8
|
|
#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8
|
|
#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec
|
|
#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0
|
|
#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0
|
|
#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4
|
|
#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8
|
|
#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8
|
|
#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc
|
|
#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00
|
|
#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00
|
|
#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04
|
|
#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08
|
|
#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08
|
|
#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c
|
|
#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10
|
|
#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10
|
|
#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14
|
|
#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18
|
|
#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18
|
|
#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c
|
|
#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20
|
|
#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20
|
|
#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24
|
|
#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28
|
|
#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28
|
|
#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c
|
|
#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30
|
|
#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30
|
|
#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34
|
|
#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38
|
|
#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38
|
|
#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c
|
|
#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40
|
|
#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40
|
|
#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44
|
|
#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48
|
|
#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48
|
|
#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c
|
|
#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50
|
|
#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50
|
|
#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54
|
|
#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58
|
|
#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58
|
|
#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c
|
|
#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60
|
|
#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60
|
|
#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64
|
|
#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68
|
|
#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68
|
|
#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c
|
|
#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70
|
|
#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70
|
|
#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74
|
|
#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78
|
|
#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78
|
|
#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c
|
|
#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80
|
|
#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80
|
|
#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84
|
|
#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88
|
|
#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88
|
|
#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c
|
|
#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90
|
|
#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90
|
|
#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94
|
|
#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98
|
|
#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98
|
|
#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c
|
|
#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0
|
|
#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0
|
|
#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4
|
|
#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8
|
|
#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8
|
|
#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac
|
|
#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0
|
|
#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0
|
|
#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4
|
|
#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8
|
|
#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8
|
|
#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc
|
|
#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0
|
|
#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0
|
|
#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4
|
|
#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8
|
|
#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8
|
|
#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc
|
|
#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0
|
|
#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0
|
|
#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4
|
|
#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8
|
|
#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8
|
|
#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc
|
|
#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0
|
|
#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0
|
|
#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4
|
|
#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8
|
|
#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8
|
|
#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec
|
|
#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0
|
|
#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0
|
|
#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4
|
|
#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8
|
|
#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008
|
|
#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8
|
|
#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc
|
|
#define CYDEV_EE_BASE 0x40008000
|
|
#define CYDEV_EE_SIZE 0x00000800
|
|
#define CYDEV_EE_DATA_MBASE 0x40008000
|
|
#define CYDEV_EE_DATA_MSIZE 0x00000800
|
|
#define CYDEV_CAN0_BASE 0x4000a000
|
|
#define CYDEV_CAN0_SIZE 0x000002a0
|
|
#define CYDEV_CAN0_CSR_BASE 0x4000a000
|
|
#define CYDEV_CAN0_CSR_SIZE 0x00000018
|
|
#define CYDEV_CAN0_CSR_INT_SR 0x4000a000
|
|
#define CYDEV_CAN0_CSR_INT_EN 0x4000a004
|
|
#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008
|
|
#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c
|
|
#define CYDEV_CAN0_CSR_CMD 0x4000a010
|
|
#define CYDEV_CAN0_CSR_CFG 0x4000a014
|
|
#define CYDEV_CAN0_TX0_BASE 0x4000a020
|
|
#define CYDEV_CAN0_TX0_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX0_CMD 0x4000a020
|
|
#define CYDEV_CAN0_TX0_ID 0x4000a024
|
|
#define CYDEV_CAN0_TX0_DH 0x4000a028
|
|
#define CYDEV_CAN0_TX0_DL 0x4000a02c
|
|
#define CYDEV_CAN0_TX1_BASE 0x4000a030
|
|
#define CYDEV_CAN0_TX1_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX1_CMD 0x4000a030
|
|
#define CYDEV_CAN0_TX1_ID 0x4000a034
|
|
#define CYDEV_CAN0_TX1_DH 0x4000a038
|
|
#define CYDEV_CAN0_TX1_DL 0x4000a03c
|
|
#define CYDEV_CAN0_TX2_BASE 0x4000a040
|
|
#define CYDEV_CAN0_TX2_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX2_CMD 0x4000a040
|
|
#define CYDEV_CAN0_TX2_ID 0x4000a044
|
|
#define CYDEV_CAN0_TX2_DH 0x4000a048
|
|
#define CYDEV_CAN0_TX2_DL 0x4000a04c
|
|
#define CYDEV_CAN0_TX3_BASE 0x4000a050
|
|
#define CYDEV_CAN0_TX3_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX3_CMD 0x4000a050
|
|
#define CYDEV_CAN0_TX3_ID 0x4000a054
|
|
#define CYDEV_CAN0_TX3_DH 0x4000a058
|
|
#define CYDEV_CAN0_TX3_DL 0x4000a05c
|
|
#define CYDEV_CAN0_TX4_BASE 0x4000a060
|
|
#define CYDEV_CAN0_TX4_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX4_CMD 0x4000a060
|
|
#define CYDEV_CAN0_TX4_ID 0x4000a064
|
|
#define CYDEV_CAN0_TX4_DH 0x4000a068
|
|
#define CYDEV_CAN0_TX4_DL 0x4000a06c
|
|
#define CYDEV_CAN0_TX5_BASE 0x4000a070
|
|
#define CYDEV_CAN0_TX5_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX5_CMD 0x4000a070
|
|
#define CYDEV_CAN0_TX5_ID 0x4000a074
|
|
#define CYDEV_CAN0_TX5_DH 0x4000a078
|
|
#define CYDEV_CAN0_TX5_DL 0x4000a07c
|
|
#define CYDEV_CAN0_TX6_BASE 0x4000a080
|
|
#define CYDEV_CAN0_TX6_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX6_CMD 0x4000a080
|
|
#define CYDEV_CAN0_TX6_ID 0x4000a084
|
|
#define CYDEV_CAN0_TX6_DH 0x4000a088
|
|
#define CYDEV_CAN0_TX6_DL 0x4000a08c
|
|
#define CYDEV_CAN0_TX7_BASE 0x4000a090
|
|
#define CYDEV_CAN0_TX7_SIZE 0x00000010
|
|
#define CYDEV_CAN0_TX7_CMD 0x4000a090
|
|
#define CYDEV_CAN0_TX7_ID 0x4000a094
|
|
#define CYDEV_CAN0_TX7_DH 0x4000a098
|
|
#define CYDEV_CAN0_TX7_DL 0x4000a09c
|
|
#define CYDEV_CAN0_RX0_BASE 0x4000a0a0
|
|
#define CYDEV_CAN0_RX0_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX0_CMD 0x4000a0a0
|
|
#define CYDEV_CAN0_RX0_ID 0x4000a0a4
|
|
#define CYDEV_CAN0_RX0_DH 0x4000a0a8
|
|
#define CYDEV_CAN0_RX0_DL 0x4000a0ac
|
|
#define CYDEV_CAN0_RX0_AMR 0x4000a0b0
|
|
#define CYDEV_CAN0_RX0_ACR 0x4000a0b4
|
|
#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8
|
|
#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc
|
|
#define CYDEV_CAN0_RX1_BASE 0x4000a0c0
|
|
#define CYDEV_CAN0_RX1_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX1_CMD 0x4000a0c0
|
|
#define CYDEV_CAN0_RX1_ID 0x4000a0c4
|
|
#define CYDEV_CAN0_RX1_DH 0x4000a0c8
|
|
#define CYDEV_CAN0_RX1_DL 0x4000a0cc
|
|
#define CYDEV_CAN0_RX1_AMR 0x4000a0d0
|
|
#define CYDEV_CAN0_RX1_ACR 0x4000a0d4
|
|
#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8
|
|
#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc
|
|
#define CYDEV_CAN0_RX2_BASE 0x4000a0e0
|
|
#define CYDEV_CAN0_RX2_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX2_CMD 0x4000a0e0
|
|
#define CYDEV_CAN0_RX2_ID 0x4000a0e4
|
|
#define CYDEV_CAN0_RX2_DH 0x4000a0e8
|
|
#define CYDEV_CAN0_RX2_DL 0x4000a0ec
|
|
#define CYDEV_CAN0_RX2_AMR 0x4000a0f0
|
|
#define CYDEV_CAN0_RX2_ACR 0x4000a0f4
|
|
#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8
|
|
#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc
|
|
#define CYDEV_CAN0_RX3_BASE 0x4000a100
|
|
#define CYDEV_CAN0_RX3_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX3_CMD 0x4000a100
|
|
#define CYDEV_CAN0_RX3_ID 0x4000a104
|
|
#define CYDEV_CAN0_RX3_DH 0x4000a108
|
|
#define CYDEV_CAN0_RX3_DL 0x4000a10c
|
|
#define CYDEV_CAN0_RX3_AMR 0x4000a110
|
|
#define CYDEV_CAN0_RX3_ACR 0x4000a114
|
|
#define CYDEV_CAN0_RX3_AMRD 0x4000a118
|
|
#define CYDEV_CAN0_RX3_ACRD 0x4000a11c
|
|
#define CYDEV_CAN0_RX4_BASE 0x4000a120
|
|
#define CYDEV_CAN0_RX4_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX4_CMD 0x4000a120
|
|
#define CYDEV_CAN0_RX4_ID 0x4000a124
|
|
#define CYDEV_CAN0_RX4_DH 0x4000a128
|
|
#define CYDEV_CAN0_RX4_DL 0x4000a12c
|
|
#define CYDEV_CAN0_RX4_AMR 0x4000a130
|
|
#define CYDEV_CAN0_RX4_ACR 0x4000a134
|
|
#define CYDEV_CAN0_RX4_AMRD 0x4000a138
|
|
#define CYDEV_CAN0_RX4_ACRD 0x4000a13c
|
|
#define CYDEV_CAN0_RX5_BASE 0x4000a140
|
|
#define CYDEV_CAN0_RX5_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX5_CMD 0x4000a140
|
|
#define CYDEV_CAN0_RX5_ID 0x4000a144
|
|
#define CYDEV_CAN0_RX5_DH 0x4000a148
|
|
#define CYDEV_CAN0_RX5_DL 0x4000a14c
|
|
#define CYDEV_CAN0_RX5_AMR 0x4000a150
|
|
#define CYDEV_CAN0_RX5_ACR 0x4000a154
|
|
#define CYDEV_CAN0_RX5_AMRD 0x4000a158
|
|
#define CYDEV_CAN0_RX5_ACRD 0x4000a15c
|
|
#define CYDEV_CAN0_RX6_BASE 0x4000a160
|
|
#define CYDEV_CAN0_RX6_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX6_CMD 0x4000a160
|
|
#define CYDEV_CAN0_RX6_ID 0x4000a164
|
|
#define CYDEV_CAN0_RX6_DH 0x4000a168
|
|
#define CYDEV_CAN0_RX6_DL 0x4000a16c
|
|
#define CYDEV_CAN0_RX6_AMR 0x4000a170
|
|
#define CYDEV_CAN0_RX6_ACR 0x4000a174
|
|
#define CYDEV_CAN0_RX6_AMRD 0x4000a178
|
|
#define CYDEV_CAN0_RX6_ACRD 0x4000a17c
|
|
#define CYDEV_CAN0_RX7_BASE 0x4000a180
|
|
#define CYDEV_CAN0_RX7_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX7_CMD 0x4000a180
|
|
#define CYDEV_CAN0_RX7_ID 0x4000a184
|
|
#define CYDEV_CAN0_RX7_DH 0x4000a188
|
|
#define CYDEV_CAN0_RX7_DL 0x4000a18c
|
|
#define CYDEV_CAN0_RX7_AMR 0x4000a190
|
|
#define CYDEV_CAN0_RX7_ACR 0x4000a194
|
|
#define CYDEV_CAN0_RX7_AMRD 0x4000a198
|
|
#define CYDEV_CAN0_RX7_ACRD 0x4000a19c
|
|
#define CYDEV_CAN0_RX8_BASE 0x4000a1a0
|
|
#define CYDEV_CAN0_RX8_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX8_CMD 0x4000a1a0
|
|
#define CYDEV_CAN0_RX8_ID 0x4000a1a4
|
|
#define CYDEV_CAN0_RX8_DH 0x4000a1a8
|
|
#define CYDEV_CAN0_RX8_DL 0x4000a1ac
|
|
#define CYDEV_CAN0_RX8_AMR 0x4000a1b0
|
|
#define CYDEV_CAN0_RX8_ACR 0x4000a1b4
|
|
#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8
|
|
#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc
|
|
#define CYDEV_CAN0_RX9_BASE 0x4000a1c0
|
|
#define CYDEV_CAN0_RX9_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX9_CMD 0x4000a1c0
|
|
#define CYDEV_CAN0_RX9_ID 0x4000a1c4
|
|
#define CYDEV_CAN0_RX9_DH 0x4000a1c8
|
|
#define CYDEV_CAN0_RX9_DL 0x4000a1cc
|
|
#define CYDEV_CAN0_RX9_AMR 0x4000a1d0
|
|
#define CYDEV_CAN0_RX9_ACR 0x4000a1d4
|
|
#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8
|
|
#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc
|
|
#define CYDEV_CAN0_RX10_BASE 0x4000a1e0
|
|
#define CYDEV_CAN0_RX10_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX10_CMD 0x4000a1e0
|
|
#define CYDEV_CAN0_RX10_ID 0x4000a1e4
|
|
#define CYDEV_CAN0_RX10_DH 0x4000a1e8
|
|
#define CYDEV_CAN0_RX10_DL 0x4000a1ec
|
|
#define CYDEV_CAN0_RX10_AMR 0x4000a1f0
|
|
#define CYDEV_CAN0_RX10_ACR 0x4000a1f4
|
|
#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8
|
|
#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc
|
|
#define CYDEV_CAN0_RX11_BASE 0x4000a200
|
|
#define CYDEV_CAN0_RX11_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX11_CMD 0x4000a200
|
|
#define CYDEV_CAN0_RX11_ID 0x4000a204
|
|
#define CYDEV_CAN0_RX11_DH 0x4000a208
|
|
#define CYDEV_CAN0_RX11_DL 0x4000a20c
|
|
#define CYDEV_CAN0_RX11_AMR 0x4000a210
|
|
#define CYDEV_CAN0_RX11_ACR 0x4000a214
|
|
#define CYDEV_CAN0_RX11_AMRD 0x4000a218
|
|
#define CYDEV_CAN0_RX11_ACRD 0x4000a21c
|
|
#define CYDEV_CAN0_RX12_BASE 0x4000a220
|
|
#define CYDEV_CAN0_RX12_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX12_CMD 0x4000a220
|
|
#define CYDEV_CAN0_RX12_ID 0x4000a224
|
|
#define CYDEV_CAN0_RX12_DH 0x4000a228
|
|
#define CYDEV_CAN0_RX12_DL 0x4000a22c
|
|
#define CYDEV_CAN0_RX12_AMR 0x4000a230
|
|
#define CYDEV_CAN0_RX12_ACR 0x4000a234
|
|
#define CYDEV_CAN0_RX12_AMRD 0x4000a238
|
|
#define CYDEV_CAN0_RX12_ACRD 0x4000a23c
|
|
#define CYDEV_CAN0_RX13_BASE 0x4000a240
|
|
#define CYDEV_CAN0_RX13_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX13_CMD 0x4000a240
|
|
#define CYDEV_CAN0_RX13_ID 0x4000a244
|
|
#define CYDEV_CAN0_RX13_DH 0x4000a248
|
|
#define CYDEV_CAN0_RX13_DL 0x4000a24c
|
|
#define CYDEV_CAN0_RX13_AMR 0x4000a250
|
|
#define CYDEV_CAN0_RX13_ACR 0x4000a254
|
|
#define CYDEV_CAN0_RX13_AMRD 0x4000a258
|
|
#define CYDEV_CAN0_RX13_ACRD 0x4000a25c
|
|
#define CYDEV_CAN0_RX14_BASE 0x4000a260
|
|
#define CYDEV_CAN0_RX14_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX14_CMD 0x4000a260
|
|
#define CYDEV_CAN0_RX14_ID 0x4000a264
|
|
#define CYDEV_CAN0_RX14_DH 0x4000a268
|
|
#define CYDEV_CAN0_RX14_DL 0x4000a26c
|
|
#define CYDEV_CAN0_RX14_AMR 0x4000a270
|
|
#define CYDEV_CAN0_RX14_ACR 0x4000a274
|
|
#define CYDEV_CAN0_RX14_AMRD 0x4000a278
|
|
#define CYDEV_CAN0_RX14_ACRD 0x4000a27c
|
|
#define CYDEV_CAN0_RX15_BASE 0x4000a280
|
|
#define CYDEV_CAN0_RX15_SIZE 0x00000020
|
|
#define CYDEV_CAN0_RX15_CMD 0x4000a280
|
|
#define CYDEV_CAN0_RX15_ID 0x4000a284
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#define CYDEV_CAN0_RX15_DH 0x4000a288
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#define CYDEV_CAN0_RX15_DL 0x4000a28c
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#define CYDEV_CAN0_RX15_AMR 0x4000a290
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#define CYDEV_CAN0_RX15_ACR 0x4000a294
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#define CYDEV_CAN0_RX15_AMRD 0x4000a298
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#define CYDEV_CAN0_RX15_ACRD 0x4000a29c
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#define CYDEV_DFB0_BASE 0x4000c000
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#define CYDEV_DFB0_SIZE 0x000007b5
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#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000
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#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200
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#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000
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#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200
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#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200
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#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200
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#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200
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#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200
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#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400
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#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100
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#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400
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#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100
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#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500
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#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100
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#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500
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#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100
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#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600
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#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100
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#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600
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#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100
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#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700
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#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040
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#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700
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#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040
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#define CYDEV_DFB0_CR 0x4000c780
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#define CYDEV_DFB0_SR 0x4000c784
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#define CYDEV_DFB0_RAM_EN 0x4000c788
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#define CYDEV_DFB0_RAM_DIR 0x4000c78c
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#define CYDEV_DFB0_SEMA 0x4000c790
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#define CYDEV_DFB0_DSI_CTRL 0x4000c794
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#define CYDEV_DFB0_INT_CTRL 0x4000c798
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#define CYDEV_DFB0_DMA_CTRL 0x4000c79c
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#define CYDEV_DFB0_STAGEA 0x4000c7a0
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#define CYDEV_DFB0_STAGEAM 0x4000c7a1
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#define CYDEV_DFB0_STAGEAH 0x4000c7a2
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#define CYDEV_DFB0_STAGEB 0x4000c7a4
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#define CYDEV_DFB0_STAGEBM 0x4000c7a5
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#define CYDEV_DFB0_STAGEBH 0x4000c7a6
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#define CYDEV_DFB0_HOLDA 0x4000c7a8
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#define CYDEV_DFB0_HOLDAM 0x4000c7a9
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#define CYDEV_DFB0_HOLDAH 0x4000c7aa
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#define CYDEV_DFB0_HOLDAS 0x4000c7ab
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#define CYDEV_DFB0_HOLDB 0x4000c7ac
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#define CYDEV_DFB0_HOLDBM 0x4000c7ad
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#define CYDEV_DFB0_HOLDBH 0x4000c7ae
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#define CYDEV_DFB0_HOLDBS 0x4000c7af
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#define CYDEV_DFB0_COHER 0x4000c7b0
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#define CYDEV_DFB0_DALIGN 0x4000c7b4
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#define CYDEV_UCFG_BASE 0x40010000
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#define CYDEV_UCFG_SIZE 0x00005040
|
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#define CYDEV_UCFG_B0_BASE 0x40010000
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#define CYDEV_UCFG_B0_SIZE 0x00000fef
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#define CYDEV_UCFG_B0_P0_BASE 0x40010000
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#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef
|
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#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000
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|
#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000
|
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#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004
|
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#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008
|
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#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c
|
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#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010
|
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#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034
|
|
#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036
|
|
#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038
|
|
#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a
|
|
#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c
|
|
#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e
|
|
#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c
|
|
#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e
|
|
#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080
|
|
#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4
|
|
#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6
|
|
#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8
|
|
#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba
|
|
#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc
|
|
#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de
|
|
#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec
|
|
#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee
|
|
#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100
|
|
#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef
|
|
#define CYDEV_UCFG_B0_P1_BASE 0x40010200
|
|
#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef
|
|
#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200
|
|
#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234
|
|
#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236
|
|
#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238
|
|
#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a
|
|
#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c
|
|
#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e
|
|
#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c
|
|
#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e
|
|
#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280
|
|
#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070
|
|
#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8
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#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac
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#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0
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#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2
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#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4
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#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6
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#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8
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#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba
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#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc
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#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be
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#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0
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#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1
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#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2
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#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3
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#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4
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#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5
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#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6
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#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7
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#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8
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#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9
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#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca
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#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb
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#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc
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#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd
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#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce
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#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf
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#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0
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#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1
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#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2
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#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3
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#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4
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#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5
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#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6
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#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7
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#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8
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#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9
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#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da
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#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db
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#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc
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#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd
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#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de
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#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df
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#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0
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#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2
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#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4
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#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6
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#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8
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#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea
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#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec
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#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee
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#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300
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#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B0_P2_BASE 0x40010400
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#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef
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#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400
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#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428
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#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c
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#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430
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#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432
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#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434
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#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436
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#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438
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#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a
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#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c
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#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e
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#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440
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#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441
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#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442
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#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443
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#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444
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#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445
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#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446
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#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447
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#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448
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#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449
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#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a
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#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b
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#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c
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#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d
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#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e
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#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f
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#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450
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#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451
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#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452
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#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453
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#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454
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#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455
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#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456
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#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457
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#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458
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#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459
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#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a
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#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b
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#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c
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#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d
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#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e
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#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f
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#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460
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#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462
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#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464
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#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466
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#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468
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#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a
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#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c
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#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e
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#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480
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#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8
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#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac
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#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0
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#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2
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#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4
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#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6
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#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8
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#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba
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#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc
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#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be
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#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0
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#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1
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#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2
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#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3
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#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4
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#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5
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#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6
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#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7
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#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8
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#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9
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#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca
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#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb
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#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc
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#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd
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#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce
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#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf
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#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0
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#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1
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#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2
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#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3
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#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4
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#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5
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#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6
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#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7
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#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8
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#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9
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#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da
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#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db
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#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc
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#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd
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#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de
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#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df
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#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0
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#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2
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#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4
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#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6
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#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8
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#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea
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#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec
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#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee
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#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500
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#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B0_P3_BASE 0x40010600
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#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef
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#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600
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#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c
|
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#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630
|
|
#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632
|
|
#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634
|
|
#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636
|
|
#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638
|
|
#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a
|
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#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c
|
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#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e
|
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#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640
|
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#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641
|
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#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642
|
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#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643
|
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#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644
|
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#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645
|
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#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649
|
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#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a
|
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#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b
|
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#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c
|
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#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d
|
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#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a
|
|
#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b
|
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#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c
|
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#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d
|
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#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e
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#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f
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#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660
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#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662
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#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664
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#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666
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#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668
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#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a
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#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c
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#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e
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#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680
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#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8
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#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac
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#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0
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#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2
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#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4
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#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6
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#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8
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#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba
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#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc
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#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be
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#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0
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#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1
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#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2
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#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3
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#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4
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#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5
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#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6
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#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7
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#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8
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#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9
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#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca
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#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb
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#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc
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#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd
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#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce
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#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf
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#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0
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#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1
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#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2
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#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3
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#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4
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#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5
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#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6
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#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7
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#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8
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#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9
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#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da
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#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db
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#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc
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#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd
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#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de
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#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df
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#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0
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#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2
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#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4
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#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6
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#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8
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#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea
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#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec
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#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee
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#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700
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#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B0_P4_BASE 0x40010800
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#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef
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#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800
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#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828
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#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c
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#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830
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#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832
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#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834
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#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836
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#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838
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#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a
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#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c
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#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e
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#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840
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#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841
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#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842
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#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843
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#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844
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#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845
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#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846
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#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847
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#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848
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#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849
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#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a
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#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b
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#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c
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#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d
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#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e
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#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f
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#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850
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#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851
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#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852
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#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853
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#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854
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#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855
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#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856
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#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857
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#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858
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#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859
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#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a
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#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b
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#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c
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#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d
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#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e
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#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f
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#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860
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#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862
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#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864
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#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866
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#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868
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#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a
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#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c
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#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e
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#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880
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#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8
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#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac
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#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0
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#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2
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#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4
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#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6
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#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8
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#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba
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#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc
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#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be
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#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0
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#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1
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#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2
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#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3
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#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4
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#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5
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#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6
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#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7
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#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8
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#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9
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#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca
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#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb
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#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc
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#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd
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#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce
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#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf
|
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#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0
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#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1
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#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2
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#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3
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#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4
|
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#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5
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#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6
|
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#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7
|
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#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8
|
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#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9
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#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da
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#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db
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#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc
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#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd
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#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de
|
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#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df
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|
#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0
|
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#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2
|
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#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4
|
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#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6
|
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#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8
|
|
#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea
|
|
#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec
|
|
#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee
|
|
#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900
|
|
#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef
|
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#define CYDEV_UCFG_B0_P5_BASE 0x40010a00
|
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#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef
|
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#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00
|
|
#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14
|
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#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34
|
|
#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36
|
|
#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38
|
|
#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a
|
|
#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c
|
|
#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e
|
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#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f
|
|
#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50
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#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51
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#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52
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#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53
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#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54
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#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55
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#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56
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#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57
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#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58
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#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59
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#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a
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#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b
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#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c
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#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d
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#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e
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#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f
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#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60
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#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62
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#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64
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#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66
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#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68
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#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a
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#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c
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#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e
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#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80
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#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8
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#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac
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#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0
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#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2
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#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4
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#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6
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#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8
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#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba
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#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc
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#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe
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#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0
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#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1
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#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2
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#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3
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#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4
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#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5
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#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6
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#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7
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#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8
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#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9
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#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca
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#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb
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#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc
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#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd
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#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace
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#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf
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#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0
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#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1
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#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2
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#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3
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#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4
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#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5
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#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6
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#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7
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#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8
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#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9
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#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada
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#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb
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#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc
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#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add
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#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade
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#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf
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#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0
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#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2
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#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4
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#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6
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#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8
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#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea
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#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec
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#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee
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#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00
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#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B0_P6_BASE 0x40010c00
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#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef
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#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00
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#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28
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#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c
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#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30
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#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32
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#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34
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#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36
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#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38
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#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a
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#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c
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#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e
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#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40
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#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41
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#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42
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#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43
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#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44
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#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45
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#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46
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#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47
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#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48
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#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49
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#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a
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#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b
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#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c
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#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d
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#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e
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#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f
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#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50
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#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51
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#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52
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#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53
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#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54
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#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55
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#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56
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#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57
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#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58
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#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59
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#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a
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#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b
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#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c
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#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d
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#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e
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#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f
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#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60
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#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62
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#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64
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#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66
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#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68
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#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a
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#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c
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#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e
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#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80
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#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8
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#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac
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#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0
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#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2
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#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4
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#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6
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#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8
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#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba
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#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc
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#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe
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#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0
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#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1
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#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2
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#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3
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#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4
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#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5
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#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6
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#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7
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#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8
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#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9
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#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca
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#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb
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#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc
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#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd
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#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce
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#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf
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#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0
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#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1
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#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2
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#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3
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#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4
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#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5
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#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6
|
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#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7
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#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8
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#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9
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#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda
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#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb
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#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc
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#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd
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#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde
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#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf
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#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0
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#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2
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#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4
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#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6
|
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#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8
|
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#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea
|
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#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec
|
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#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee
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#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00
|
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#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B0_P7_BASE 0x40010e00
|
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#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef
|
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#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00
|
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#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c
|
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#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30
|
|
#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32
|
|
#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34
|
|
#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36
|
|
#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38
|
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#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a
|
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#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c
|
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#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e
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#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40
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#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41
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#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42
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#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43
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#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44
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#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45
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#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46
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#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47
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#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48
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#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49
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#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a
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#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b
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#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c
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#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d
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#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e
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#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f
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#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50
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#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51
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#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52
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#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53
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#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54
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#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55
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#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56
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#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57
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#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58
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#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59
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#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a
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#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b
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#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c
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#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d
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#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e
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#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f
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#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60
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#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62
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#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64
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#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66
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#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68
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#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a
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#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c
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#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e
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#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80
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#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8
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#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac
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#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0
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#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2
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#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4
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#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6
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#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8
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#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba
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#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc
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#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe
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#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0
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#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1
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#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2
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#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3
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#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4
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#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5
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#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6
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#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7
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#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8
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#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9
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#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca
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#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb
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#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc
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#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd
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#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece
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#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf
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#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0
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#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1
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#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2
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#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3
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#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4
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#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5
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#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6
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#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7
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#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8
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#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9
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#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda
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#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb
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#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc
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#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd
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#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede
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#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf
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#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0
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#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2
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#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4
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#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6
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#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8
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#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea
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#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec
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#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee
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#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00
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#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B1_BASE 0x40011000
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#define CYDEV_UCFG_B1_SIZE 0x00000fef
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#define CYDEV_UCFG_B1_P2_BASE 0x40011400
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#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef
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#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400
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#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428
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#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c
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#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430
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#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432
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#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434
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#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436
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#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438
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#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a
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#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c
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#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e
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#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440
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#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441
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#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442
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#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443
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#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444
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#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445
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#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446
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#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447
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#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448
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#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449
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#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a
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#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b
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#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c
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#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d
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#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e
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#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f
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#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450
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#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451
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#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452
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#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453
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#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454
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#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455
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#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456
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#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457
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#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458
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#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459
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#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a
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#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b
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#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c
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#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d
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#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e
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#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f
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#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460
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#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462
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#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464
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#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466
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#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468
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#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a
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#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c
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#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e
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#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480
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#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8
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#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac
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#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0
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#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2
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#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4
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#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6
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#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8
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#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba
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#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc
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#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be
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#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0
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#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1
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#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2
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#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3
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#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4
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#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5
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#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6
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#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7
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#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8
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#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9
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#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca
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#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb
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#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc
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#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd
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#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce
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#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf
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#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0
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#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1
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#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2
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#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3
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#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4
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#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5
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#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6
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#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7
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#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8
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#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9
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#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da
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#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db
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#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc
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#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd
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#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de
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#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df
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#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0
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#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2
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#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4
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#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6
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#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8
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#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea
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#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec
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#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee
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#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500
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#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B1_P3_BASE 0x40011600
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#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef
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#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600
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#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628
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#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c
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#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630
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#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632
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#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634
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#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636
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#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638
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#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a
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#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c
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#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e
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#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640
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#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641
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#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642
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#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643
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#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644
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#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645
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#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646
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#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647
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#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648
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#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649
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#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a
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#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b
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#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c
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#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d
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#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e
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#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f
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#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650
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#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651
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#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652
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#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653
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#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654
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#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655
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#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656
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#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657
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#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658
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#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659
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#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a
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#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b
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#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c
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#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d
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#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e
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#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f
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#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660
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#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662
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#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664
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#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666
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#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668
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#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a
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#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c
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#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e
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#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680
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#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8
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#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac
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#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0
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#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2
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#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4
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#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6
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#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8
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#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba
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#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc
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#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be
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#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0
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#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1
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#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2
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#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3
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#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4
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#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5
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#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6
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#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7
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#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8
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#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9
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#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca
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#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb
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#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc
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#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd
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#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce
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#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf
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#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0
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#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1
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#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2
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#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3
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#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4
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#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5
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#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6
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#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7
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#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8
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#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9
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#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da
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#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db
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#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc
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#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd
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#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de
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#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df
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#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0
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#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2
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#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4
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#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6
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#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8
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#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea
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#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec
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#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee
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#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700
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#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B1_P4_BASE 0x40011800
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#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef
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#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800
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#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828
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#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c
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#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830
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#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832
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#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834
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#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836
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#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838
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#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a
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#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c
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#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e
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#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840
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#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841
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#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842
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#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843
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#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844
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#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845
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#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846
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#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847
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#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848
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#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849
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#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a
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#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b
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#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c
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#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d
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#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e
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#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f
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#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850
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#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851
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#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852
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#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853
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#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854
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#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855
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#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856
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#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857
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#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858
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#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859
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#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a
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#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b
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#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c
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#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d
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#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e
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#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f
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#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860
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#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862
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#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864
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#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866
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#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868
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#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a
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#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c
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#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e
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#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880
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#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8
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#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac
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#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0
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#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2
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#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4
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#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6
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#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8
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#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba
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#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc
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#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be
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#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0
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#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1
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#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2
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#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3
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#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4
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#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5
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#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6
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#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7
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#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8
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#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9
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#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca
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#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb
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#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc
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#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd
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#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce
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#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf
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#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0
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#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1
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#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2
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#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3
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#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4
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#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5
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#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6
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#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7
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#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8
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#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9
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#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da
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#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db
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#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc
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#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd
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#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de
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#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df
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#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0
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#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2
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#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4
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#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6
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#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8
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#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea
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#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec
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#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee
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#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900
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#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_B1_P5_BASE 0x40011a00
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#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef
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#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00
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#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28
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#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c
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#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30
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#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32
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#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34
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#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36
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#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38
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#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a
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#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c
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#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e
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#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40
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#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41
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#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42
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#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43
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#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44
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#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45
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#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46
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#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47
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#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48
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#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49
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#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a
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#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b
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#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c
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#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d
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#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e
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#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f
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#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50
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#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51
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#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52
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#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53
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#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54
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#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55
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#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56
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#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57
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#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58
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#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59
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#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a
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#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b
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#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c
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#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d
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#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e
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#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f
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#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60
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#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62
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#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64
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#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66
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#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68
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#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a
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#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c
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#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e
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#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80
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#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4
|
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8
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#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac
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#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0
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#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2
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#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4
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#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6
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#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8
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#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba
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#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc
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#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe
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#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0
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#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1
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#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2
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#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3
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#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4
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#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5
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#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6
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#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7
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#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8
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#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9
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#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca
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#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb
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#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc
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#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd
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#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace
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#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf
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#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0
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#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1
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#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2
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#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3
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#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4
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#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5
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#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6
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#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7
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#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8
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#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9
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#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada
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#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb
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#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc
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#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add
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#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade
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#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf
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#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0
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#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2
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#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4
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#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6
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#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8
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#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea
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#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec
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#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee
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#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00
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#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef
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#define CYDEV_UCFG_DSI0_BASE 0x40014000
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#define CYDEV_UCFG_DSI0_SIZE 0x000000ef
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#define CYDEV_UCFG_DSI1_BASE 0x40014100
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#define CYDEV_UCFG_DSI1_SIZE 0x000000ef
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#define CYDEV_UCFG_DSI2_BASE 0x40014200
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#define CYDEV_UCFG_DSI2_SIZE 0x000000ef
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#define CYDEV_UCFG_DSI3_BASE 0x40014300
|
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#define CYDEV_UCFG_DSI3_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI4_BASE 0x40014400
|
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#define CYDEV_UCFG_DSI4_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI5_BASE 0x40014500
|
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#define CYDEV_UCFG_DSI5_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI6_BASE 0x40014600
|
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#define CYDEV_UCFG_DSI6_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI7_BASE 0x40014700
|
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#define CYDEV_UCFG_DSI7_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI8_BASE 0x40014800
|
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#define CYDEV_UCFG_DSI8_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI9_BASE 0x40014900
|
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#define CYDEV_UCFG_DSI9_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI12_BASE 0x40014c00
|
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#define CYDEV_UCFG_DSI12_SIZE 0x000000ef
|
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#define CYDEV_UCFG_DSI13_BASE 0x40014d00
|
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#define CYDEV_UCFG_DSI13_SIZE 0x000000ef
|
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#define CYDEV_UCFG_BCTL0_BASE 0x40015000
|
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#define CYDEV_UCFG_BCTL0_SIZE 0x00000010
|
|
#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000
|
|
#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001
|
|
#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002
|
|
#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003
|
|
#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007
|
|
#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008
|
|
#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009
|
|
#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a
|
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#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b
|
|
#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c
|
|
#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d
|
|
#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e
|
|
#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f
|
|
#define CYDEV_UCFG_BCTL1_BASE 0x40015010
|
|
#define CYDEV_UCFG_BCTL1_SIZE 0x00000010
|
|
#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010
|
|
#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011
|
|
#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012
|
|
#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013
|
|
#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017
|
|
#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018
|
|
#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019
|
|
#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a
|
|
#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b
|
|
#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c
|
|
#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d
|
|
#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e
|
|
#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f
|
|
#define CYDEV_IDMUX_BASE 0x40015100
|
|
#define CYDEV_IDMUX_SIZE 0x00000016
|
|
#define CYDEV_IDMUX_IRQ_CTL0 0x40015100
|
|
#define CYDEV_IDMUX_IRQ_CTL1 0x40015101
|
|
#define CYDEV_IDMUX_IRQ_CTL2 0x40015102
|
|
#define CYDEV_IDMUX_IRQ_CTL3 0x40015103
|
|
#define CYDEV_IDMUX_IRQ_CTL4 0x40015104
|
|
#define CYDEV_IDMUX_IRQ_CTL5 0x40015105
|
|
#define CYDEV_IDMUX_IRQ_CTL6 0x40015106
|
|
#define CYDEV_IDMUX_IRQ_CTL7 0x40015107
|
|
#define CYDEV_IDMUX_DRQ_CTL0 0x40015110
|
|
#define CYDEV_IDMUX_DRQ_CTL1 0x40015111
|
|
#define CYDEV_IDMUX_DRQ_CTL2 0x40015112
|
|
#define CYDEV_IDMUX_DRQ_CTL3 0x40015113
|
|
#define CYDEV_IDMUX_DRQ_CTL4 0x40015114
|
|
#define CYDEV_IDMUX_DRQ_CTL5 0x40015115
|
|
#define CYDEV_CACHERAM_BASE 0x40030000
|
|
#define CYDEV_CACHERAM_SIZE 0x00000400
|
|
#define CYDEV_CACHERAM_DATA_MBASE 0x40030000
|
|
#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400
|
|
#define CYDEV_SFR_BASE 0x40050100
|
|
#define CYDEV_SFR_SIZE 0x000000fb
|
|
#define CYDEV_SFR_GPIO0 0x40050180
|
|
#define CYDEV_SFR_GPIRD0 0x40050189
|
|
#define CYDEV_SFR_GPIO0_SEL 0x4005018a
|
|
#define CYDEV_SFR_GPIO1 0x40050190
|
|
#define CYDEV_SFR_GPIRD1 0x40050191
|
|
#define CYDEV_SFR_GPIO2 0x40050198
|
|
#define CYDEV_SFR_GPIRD2 0x40050199
|
|
#define CYDEV_SFR_GPIO2_SEL 0x4005019a
|
|
#define CYDEV_SFR_GPIO1_SEL 0x400501a2
|
|
#define CYDEV_SFR_GPIO3 0x400501b0
|
|
#define CYDEV_SFR_GPIRD3 0x400501b1
|
|
#define CYDEV_SFR_GPIO3_SEL 0x400501b2
|
|
#define CYDEV_SFR_GPIO4 0x400501c0
|
|
#define CYDEV_SFR_GPIRD4 0x400501c1
|
|
#define CYDEV_SFR_GPIO4_SEL 0x400501c2
|
|
#define CYDEV_SFR_GPIO5 0x400501c8
|
|
#define CYDEV_SFR_GPIRD5 0x400501c9
|
|
#define CYDEV_SFR_GPIO5_SEL 0x400501ca
|
|
#define CYDEV_SFR_GPIO6 0x400501d8
|
|
#define CYDEV_SFR_GPIRD6 0x400501d9
|
|
#define CYDEV_SFR_GPIO6_SEL 0x400501da
|
|
#define CYDEV_SFR_GPIO12 0x400501e8
|
|
#define CYDEV_SFR_GPIRD12 0x400501e9
|
|
#define CYDEV_SFR_GPIO12_SEL 0x400501f2
|
|
#define CYDEV_SFR_GPIO15 0x400501f8
|
|
#define CYDEV_SFR_GPIRD15 0x400501f9
|
|
#define CYDEV_SFR_GPIO15_SEL 0x400501fa
|
|
#define CYDEV_P3BA_BASE 0x40050300
|
|
#define CYDEV_P3BA_SIZE 0x0000002b
|
|
#define CYDEV_P3BA_Y_START 0x40050300
|
|
#define CYDEV_P3BA_YROLL 0x40050301
|
|
#define CYDEV_P3BA_YCFG 0x40050302
|
|
#define CYDEV_P3BA_X_START1 0x40050303
|
|
#define CYDEV_P3BA_X_START2 0x40050304
|
|
#define CYDEV_P3BA_XROLL1 0x40050305
|
|
#define CYDEV_P3BA_XROLL2 0x40050306
|
|
#define CYDEV_P3BA_XINC 0x40050307
|
|
#define CYDEV_P3BA_XCFG 0x40050308
|
|
#define CYDEV_P3BA_OFFSETADDR1 0x40050309
|
|
#define CYDEV_P3BA_OFFSETADDR2 0x4005030a
|
|
#define CYDEV_P3BA_OFFSETADDR3 0x4005030b
|
|
#define CYDEV_P3BA_ABSADDR1 0x4005030c
|
|
#define CYDEV_P3BA_ABSADDR2 0x4005030d
|
|
#define CYDEV_P3BA_ABSADDR3 0x4005030e
|
|
#define CYDEV_P3BA_ABSADDR4 0x4005030f
|
|
#define CYDEV_P3BA_DATCFG1 0x40050310
|
|
#define CYDEV_P3BA_DATCFG2 0x40050311
|
|
#define CYDEV_P3BA_CMP_RSLT1 0x40050314
|
|
#define CYDEV_P3BA_CMP_RSLT2 0x40050315
|
|
#define CYDEV_P3BA_CMP_RSLT3 0x40050316
|
|
#define CYDEV_P3BA_CMP_RSLT4 0x40050317
|
|
#define CYDEV_P3BA_DATA_REG1 0x40050318
|
|
#define CYDEV_P3BA_DATA_REG2 0x40050319
|
|
#define CYDEV_P3BA_DATA_REG3 0x4005031a
|
|
#define CYDEV_P3BA_DATA_REG4 0x4005031b
|
|
#define CYDEV_P3BA_EXP_DATA1 0x4005031c
|
|
#define CYDEV_P3BA_EXP_DATA2 0x4005031d
|
|
#define CYDEV_P3BA_EXP_DATA3 0x4005031e
|
|
#define CYDEV_P3BA_EXP_DATA4 0x4005031f
|
|
#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320
|
|
#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321
|
|
#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322
|
|
#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323
|
|
#define CYDEV_P3BA_BIST_EN 0x40050324
|
|
#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325
|
|
#define CYDEV_P3BA_SEQCFG1 0x40050326
|
|
#define CYDEV_P3BA_SEQCFG2 0x40050327
|
|
#define CYDEV_P3BA_Y_CURR 0x40050328
|
|
#define CYDEV_P3BA_X_CURR1 0x40050329
|
|
#define CYDEV_P3BA_X_CURR2 0x4005032a
|
|
#define CYDEV_PANTHER_BASE 0x40080000
|
|
#define CYDEV_PANTHER_SIZE 0x00000020
|
|
#define CYDEV_PANTHER_STCALIB_CFG 0x40080000
|
|
#define CYDEV_PANTHER_WAITPIPE 0x40080004
|
|
#define CYDEV_PANTHER_TRACE_CFG 0x40080008
|
|
#define CYDEV_PANTHER_DBG_CFG 0x4008000c
|
|
#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018
|
|
#define CYDEV_PANTHER_DEVICE_ID 0x4008001c
|
|
#define CYDEV_FLSECC_BASE 0x48000000
|
|
#define CYDEV_FLSECC_SIZE 0x00008000
|
|
#define CYDEV_FLSECC_DATA_MBASE 0x48000000
|
|
#define CYDEV_FLSECC_DATA_MSIZE 0x00008000
|
|
#define CYDEV_FLSHID_BASE 0x49000000
|
|
#define CYDEV_FLSHID_SIZE 0x00000200
|
|
#define CYDEV_FLSHID_RSVD_MBASE 0x49000000
|
|
#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080
|
|
#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080
|
|
#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080
|
|
#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100
|
|
#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040
|
|
#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100
|
|
#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101
|
|
#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102
|
|
#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103
|
|
#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104
|
|
#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105
|
|
#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106
|
|
#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e
|
|
#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116
|
|
#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e
|
|
#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e
|
|
#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f
|
|
#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180
|
|
#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080
|
|
#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8
|
|
#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba
|
|
#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce
|
|
#define CYDEV_EXTMEM_BASE 0x60000000
|
|
#define CYDEV_EXTMEM_SIZE 0x00800000
|
|
#define CYDEV_EXTMEM_DATA_MBASE 0x60000000
|
|
#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000
|
|
#define CYDEV_ITM_BASE 0xe0000000
|
|
#define CYDEV_ITM_SIZE 0x00001000
|
|
#define CYDEV_ITM_TRACE_EN 0xe0000e00
|
|
#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40
|
|
#define CYDEV_ITM_TRACE_CTRL 0xe0000e80
|
|
#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0
|
|
#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4
|
|
#define CYDEV_ITM_PID4 0xe0000fd0
|
|
#define CYDEV_ITM_PID5 0xe0000fd4
|
|
#define CYDEV_ITM_PID6 0xe0000fd8
|
|
#define CYDEV_ITM_PID7 0xe0000fdc
|
|
#define CYDEV_ITM_PID0 0xe0000fe0
|
|
#define CYDEV_ITM_PID1 0xe0000fe4
|
|
#define CYDEV_ITM_PID2 0xe0000fe8
|
|
#define CYDEV_ITM_PID3 0xe0000fec
|
|
#define CYDEV_ITM_CID0 0xe0000ff0
|
|
#define CYDEV_ITM_CID1 0xe0000ff4
|
|
#define CYDEV_ITM_CID2 0xe0000ff8
|
|
#define CYDEV_ITM_CID3 0xe0000ffc
|
|
#define CYDEV_DWT_BASE 0xe0001000
|
|
#define CYDEV_DWT_SIZE 0x0000005c
|
|
#define CYDEV_DWT_CTRL 0xe0001000
|
|
#define CYDEV_DWT_CYCLE_COUNT 0xe0001004
|
|
#define CYDEV_DWT_CPI_COUNT 0xe0001008
|
|
#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c
|
|
#define CYDEV_DWT_SLEEP_COUNT 0xe0001010
|
|
#define CYDEV_DWT_LSU_COUNT 0xe0001014
|
|
#define CYDEV_DWT_FOLD_COUNT 0xe0001018
|
|
#define CYDEV_DWT_PC_SAMPLE 0xe000101c
|
|
#define CYDEV_DWT_COMP_0 0xe0001020
|
|
#define CYDEV_DWT_MASK_0 0xe0001024
|
|
#define CYDEV_DWT_FUNCTION_0 0xe0001028
|
|
#define CYDEV_DWT_COMP_1 0xe0001030
|
|
#define CYDEV_DWT_MASK_1 0xe0001034
|
|
#define CYDEV_DWT_FUNCTION_1 0xe0001038
|
|
#define CYDEV_DWT_COMP_2 0xe0001040
|
|
#define CYDEV_DWT_MASK_2 0xe0001044
|
|
#define CYDEV_DWT_FUNCTION_2 0xe0001048
|
|
#define CYDEV_DWT_COMP_3 0xe0001050
|
|
#define CYDEV_DWT_MASK_3 0xe0001054
|
|
#define CYDEV_DWT_FUNCTION_3 0xe0001058
|
|
#define CYDEV_FPB_BASE 0xe0002000
|
|
#define CYDEV_FPB_SIZE 0x00001000
|
|
#define CYDEV_FPB_CTRL 0xe0002000
|
|
#define CYDEV_FPB_REMAP 0xe0002004
|
|
#define CYDEV_FPB_FP_COMP_0 0xe0002008
|
|
#define CYDEV_FPB_FP_COMP_1 0xe000200c
|
|
#define CYDEV_FPB_FP_COMP_2 0xe0002010
|
|
#define CYDEV_FPB_FP_COMP_3 0xe0002014
|
|
#define CYDEV_FPB_FP_COMP_4 0xe0002018
|
|
#define CYDEV_FPB_FP_COMP_5 0xe000201c
|
|
#define CYDEV_FPB_FP_COMP_6 0xe0002020
|
|
#define CYDEV_FPB_FP_COMP_7 0xe0002024
|
|
#define CYDEV_FPB_PID4 0xe0002fd0
|
|
#define CYDEV_FPB_PID5 0xe0002fd4
|
|
#define CYDEV_FPB_PID6 0xe0002fd8
|
|
#define CYDEV_FPB_PID7 0xe0002fdc
|
|
#define CYDEV_FPB_PID0 0xe0002fe0
|
|
#define CYDEV_FPB_PID1 0xe0002fe4
|
|
#define CYDEV_FPB_PID2 0xe0002fe8
|
|
#define CYDEV_FPB_PID3 0xe0002fec
|
|
#define CYDEV_FPB_CID0 0xe0002ff0
|
|
#define CYDEV_FPB_CID1 0xe0002ff4
|
|
#define CYDEV_FPB_CID2 0xe0002ff8
|
|
#define CYDEV_FPB_CID3 0xe0002ffc
|
|
#define CYDEV_NVIC_BASE 0xe000e000
|
|
#define CYDEV_NVIC_SIZE 0x00000d3c
|
|
#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004
|
|
#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010
|
|
#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014
|
|
#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018
|
|
#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c
|
|
#define CYDEV_NVIC_SETENA0 0xe000e100
|
|
#define CYDEV_NVIC_CLRENA0 0xe000e180
|
|
#define CYDEV_NVIC_SETPEND0 0xe000e200
|
|
#define CYDEV_NVIC_CLRPEND0 0xe000e280
|
|
#define CYDEV_NVIC_ACTIVE0 0xe000e300
|
|
#define CYDEV_NVIC_PRI_0 0xe000e400
|
|
#define CYDEV_NVIC_PRI_1 0xe000e401
|
|
#define CYDEV_NVIC_PRI_2 0xe000e402
|
|
#define CYDEV_NVIC_PRI_3 0xe000e403
|
|
#define CYDEV_NVIC_PRI_4 0xe000e404
|
|
#define CYDEV_NVIC_PRI_5 0xe000e405
|
|
#define CYDEV_NVIC_PRI_6 0xe000e406
|
|
#define CYDEV_NVIC_PRI_7 0xe000e407
|
|
#define CYDEV_NVIC_PRI_8 0xe000e408
|
|
#define CYDEV_NVIC_PRI_9 0xe000e409
|
|
#define CYDEV_NVIC_PRI_10 0xe000e40a
|
|
#define CYDEV_NVIC_PRI_11 0xe000e40b
|
|
#define CYDEV_NVIC_PRI_12 0xe000e40c
|
|
#define CYDEV_NVIC_PRI_13 0xe000e40d
|
|
#define CYDEV_NVIC_PRI_14 0xe000e40e
|
|
#define CYDEV_NVIC_PRI_15 0xe000e40f
|
|
#define CYDEV_NVIC_PRI_16 0xe000e410
|
|
#define CYDEV_NVIC_PRI_17 0xe000e411
|
|
#define CYDEV_NVIC_PRI_18 0xe000e412
|
|
#define CYDEV_NVIC_PRI_19 0xe000e413
|
|
#define CYDEV_NVIC_PRI_20 0xe000e414
|
|
#define CYDEV_NVIC_PRI_21 0xe000e415
|
|
#define CYDEV_NVIC_PRI_22 0xe000e416
|
|
#define CYDEV_NVIC_PRI_23 0xe000e417
|
|
#define CYDEV_NVIC_PRI_24 0xe000e418
|
|
#define CYDEV_NVIC_PRI_25 0xe000e419
|
|
#define CYDEV_NVIC_PRI_26 0xe000e41a
|
|
#define CYDEV_NVIC_PRI_27 0xe000e41b
|
|
#define CYDEV_NVIC_PRI_28 0xe000e41c
|
|
#define CYDEV_NVIC_PRI_29 0xe000e41d
|
|
#define CYDEV_NVIC_PRI_30 0xe000e41e
|
|
#define CYDEV_NVIC_PRI_31 0xe000e41f
|
|
#define CYDEV_NVIC_CPUID_BASE 0xe000ed00
|
|
#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04
|
|
#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08
|
|
#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c
|
|
#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10
|
|
#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14
|
|
#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18
|
|
#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c
|
|
#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20
|
|
#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24
|
|
#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28
|
|
#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29
|
|
#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a
|
|
#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c
|
|
#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30
|
|
#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34
|
|
#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38
|
|
#define CYDEV_CORE_DBG_BASE 0xe000edf0
|
|
#define CYDEV_CORE_DBG_SIZE 0x00000010
|
|
#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0
|
|
#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4
|
|
#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8
|
|
#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc
|
|
#define CYDEV_TPIU_BASE 0xe0040000
|
|
#define CYDEV_TPIU_SIZE 0x00001000
|
|
#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000
|
|
#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004
|
|
#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010
|
|
#define CYDEV_TPIU_PROTOCOL 0xe00400f0
|
|
#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300
|
|
#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304
|
|
#define CYDEV_TPIU_TRIGGER 0xe0040ee8
|
|
#define CYDEV_TPIU_ITETMDATA 0xe0040eec
|
|
#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0
|
|
#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8
|
|
#define CYDEV_TPIU_ITITMDATA 0xe0040efc
|
|
#define CYDEV_TPIU_ITCTRL 0xe0040f00
|
|
#define CYDEV_TPIU_DEVID 0xe0040fc8
|
|
#define CYDEV_TPIU_DEVTYPE 0xe0040fcc
|
|
#define CYDEV_TPIU_PID4 0xe0040fd0
|
|
#define CYDEV_TPIU_PID5 0xe0040fd4
|
|
#define CYDEV_TPIU_PID6 0xe0040fd8
|
|
#define CYDEV_TPIU_PID7 0xe0040fdc
|
|
#define CYDEV_TPIU_PID0 0xe0040fe0
|
|
#define CYDEV_TPIU_PID1 0xe0040fe4
|
|
#define CYDEV_TPIU_PID2 0xe0040fe8
|
|
#define CYDEV_TPIU_PID3 0xe0040fec
|
|
#define CYDEV_TPIU_CID0 0xe0040ff0
|
|
#define CYDEV_TPIU_CID1 0xe0040ff4
|
|
#define CYDEV_TPIU_CID2 0xe0040ff8
|
|
#define CYDEV_TPIU_CID3 0xe0040ffc
|
|
#define CYDEV_ETM_BASE 0xe0041000
|
|
#define CYDEV_ETM_SIZE 0x00001000
|
|
#define CYDEV_ETM_CTL 0xe0041000
|
|
#define CYDEV_ETM_CFG_CODE 0xe0041004
|
|
#define CYDEV_ETM_TRIG_EVENT 0xe0041008
|
|
#define CYDEV_ETM_STATUS 0xe0041010
|
|
#define CYDEV_ETM_SYS_CFG 0xe0041014
|
|
#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020
|
|
#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024
|
|
#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c
|
|
#define CYDEV_ETM_SYNC_FREQ 0xe00411e0
|
|
#define CYDEV_ETM_ETM_ID 0xe00411e4
|
|
#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8
|
|
#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0
|
|
#define CYDEV_ETM_CS_TRACE_ID 0xe0041200
|
|
#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300
|
|
#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304
|
|
#define CYDEV_ETM_PDSR 0xe0041314
|
|
#define CYDEV_ETM_ITMISCIN 0xe0041ee0
|
|
#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8
|
|
#define CYDEV_ETM_ITATBCTR2 0xe0041ef0
|
|
#define CYDEV_ETM_ITATBCTR0 0xe0041ef8
|
|
#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00
|
|
#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0
|
|
#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4
|
|
#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0
|
|
#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4
|
|
#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8
|
|
#define CYDEV_ETM_DEV_TYPE 0xe0041fcc
|
|
#define CYDEV_ETM_PID4 0xe0041fd0
|
|
#define CYDEV_ETM_PID5 0xe0041fd4
|
|
#define CYDEV_ETM_PID6 0xe0041fd8
|
|
#define CYDEV_ETM_PID7 0xe0041fdc
|
|
#define CYDEV_ETM_PID0 0xe0041fe0
|
|
#define CYDEV_ETM_PID1 0xe0041fe4
|
|
#define CYDEV_ETM_PID2 0xe0041fe8
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#define CYDEV_ETM_PID3 0xe0041fec
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#define CYDEV_ETM_CID0 0xe0041ff0
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#define CYDEV_ETM_CID1 0xe0041ff4
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#define CYDEV_ETM_CID2 0xe0041ff8
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#define CYDEV_ETM_CID3 0xe0041ffc
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#define CYDEV_ROM_TABLE_BASE 0xe00ff000
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#define CYDEV_ROM_TABLE_SIZE 0x00001000
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#define CYDEV_ROM_TABLE_NVIC 0xe00ff000
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#define CYDEV_ROM_TABLE_DWT 0xe00ff004
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#define CYDEV_ROM_TABLE_FPB 0xe00ff008
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#define CYDEV_ROM_TABLE_ITM 0xe00ff00c
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#define CYDEV_ROM_TABLE_TPIU 0xe00ff010
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#define CYDEV_ROM_TABLE_ETM 0xe00ff014
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#define CYDEV_ROM_TABLE_END 0xe00ff018
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#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc
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#define CYDEV_ROM_TABLE_PID4 0xe00fffd0
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#define CYDEV_ROM_TABLE_PID5 0xe00fffd4
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#define CYDEV_ROM_TABLE_PID6 0xe00fffd8
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#define CYDEV_ROM_TABLE_PID7 0xe00fffdc
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#define CYDEV_ROM_TABLE_PID0 0xe00fffe0
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#define CYDEV_ROM_TABLE_PID1 0xe00fffe4
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#define CYDEV_ROM_TABLE_PID2 0xe00fffe8
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#define CYDEV_ROM_TABLE_PID3 0xe00fffec
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#define CYDEV_ROM_TABLE_CID0 0xe00ffff0
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#define CYDEV_ROM_TABLE_CID1 0xe00ffff4
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#define CYDEV_ROM_TABLE_CID2 0xe00ffff8
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#define CYDEV_ROM_TABLE_CID3 0xe00ffffc
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#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE
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#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE
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#define CYDEV_FLS_SECTOR_SIZE 0x00010000
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#define CYDEV_FLS_ROW_SIZE 0x00000100
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#define CYDEV_ECC_SECTOR_SIZE 0x00002000
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#define CYDEV_ECC_ROW_SIZE 0x00000020
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#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400
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#define CYDEV_EEPROM_ROW_SIZE 0x00000010
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#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE
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#define CYCLK_LD_DISABLE 0x00000004
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#define CYCLK_LD_SYNC_EN 0x00000002
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#define CYCLK_LD_LOAD 0x00000001
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#define CYCLK_PIPE 0x00000080
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#define CYCLK_SSS 0x00000040
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#define CYCLK_EARLY 0x00000020
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#define CYCLK_DUTY 0x00000010
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#define CYCLK_SYNC 0x00000008
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#define CYCLK_SRC_SEL_CLK_SYNC_D 0
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#define CYCLK_SRC_SEL_SYNC_DIG 0
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#define CYCLK_SRC_SEL_IMO 1
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#define CYCLK_SRC_SEL_XTAL_MHZ 2
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#define CYCLK_SRC_SEL_XTALM 2
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#define CYCLK_SRC_SEL_ILO 3
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#define CYCLK_SRC_SEL_PLL 4
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#define CYCLK_SRC_SEL_XTAL_KHZ 5
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#define CYCLK_SRC_SEL_XTALK 5
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#define CYCLK_SRC_SEL_DSI_G 6
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#define CYCLK_SRC_SEL_DSI_D 7
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#define CYCLK_SRC_SEL_CLK_SYNC_A 0
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#define CYCLK_SRC_SEL_DSI_A 7
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