mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2024-06-02 22:41:29 +00:00
477 lines
16 KiB
C
477 lines
16 KiB
C
|
|
/*******************************************************************************
|
|
* File Name: cyfitter_cfg.c
|
|
*
|
|
* PSoC Creator 4.4
|
|
*
|
|
* Description:
|
|
* This file contains device initialization code.
|
|
* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
|
|
* This file is automatically generated by PSoC Creator.
|
|
*
|
|
********************************************************************************
|
|
* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved.
|
|
* You may use this file only in accordance with the license, terms, conditions,
|
|
* disclaimers, and limitations in the end user license agreement accompanying
|
|
* the software package with which this file was provided.
|
|
********************************************************************************/
|
|
|
|
#include <string.h>
|
|
#include "cytypes.h"
|
|
#include "cydevice_trm.h"
|
|
#include "cyfitter.h"
|
|
#include "CyLib.h"
|
|
#include "cyfitter_cfg.h"
|
|
|
|
#define CY_NEED_CYCLOCKSTARTUPERROR 1
|
|
|
|
|
|
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
|
|
#define CYPACKED
|
|
#define CYPACKED_ATTR __attribute__ ((packed))
|
|
#define CYALIGNED __attribute__ ((aligned))
|
|
#define CY_CFG_UNUSED __attribute__ ((unused))
|
|
#ifndef CY_CFG_SECTION
|
|
#define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
|
|
#endif
|
|
|
|
#if defined(__ARMCC_VERSION)
|
|
#define CY_CFG_MEMORY_BARRIER() __memory_changed()
|
|
#else
|
|
#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
|
|
#endif
|
|
|
|
#elif defined(__ICCARM__)
|
|
#include <intrinsics.h>
|
|
|
|
#define CYPACKED __packed
|
|
#define CYPACKED_ATTR
|
|
#define CYALIGNED _Pragma("data_alignment=4")
|
|
#define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
|
|
#define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
|
|
|
|
#define CY_CFG_MEMORY_BARRIER() __DMB()
|
|
|
|
#else
|
|
#error Unsupported toolchain
|
|
#endif
|
|
|
|
#ifndef CYCODE
|
|
#define CYCODE
|
|
#endif
|
|
#ifndef CYDATA
|
|
#define CYDATA
|
|
#endif
|
|
#ifndef CYFAR
|
|
#define CYFAR
|
|
#endif
|
|
#ifndef CYXDATA
|
|
#define CYXDATA
|
|
#endif
|
|
|
|
|
|
CY_CFG_UNUSED
|
|
static void CYMEMZERO(void *s, size_t n);
|
|
CY_CFG_UNUSED
|
|
static void CYMEMZERO(void *s, size_t n)
|
|
{
|
|
(void)memset(s, 0, n);
|
|
}
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPY(void *dest, const void *src, size_t n);
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPY(void *dest, const void *src, size_t n)
|
|
{
|
|
(void)memcpy(dest, src, n);
|
|
}
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
|
|
CY_CFG_UNUSED
|
|
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
|
|
{
|
|
(void)memcpy(dest, src, n);
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Clock startup error codes */
|
|
#define CYCLOCKSTART_NO_ERROR 0u
|
|
#define CYCLOCKSTART_XTAL_ERROR 1u
|
|
#define CYCLOCKSTART_32KHZ_ERROR 2u
|
|
#define CYCLOCKSTART_PLL_ERROR 3u
|
|
#define CYCLOCKSTART_FLL_ERROR 4u
|
|
#define CYCLOCKSTART_WCO_ERROR 5u
|
|
|
|
|
|
#ifdef CY_NEED_CYCLOCKSTARTUPERROR
|
|
/*******************************************************************************
|
|
* Function Name: CyClockStartupError
|
|
********************************************************************************
|
|
* Summary:
|
|
* If an error is encountered during clock configuration (crystal startup error,
|
|
* PLL lock error, etc.), the system will end up here. Unless reimplemented by
|
|
* the customer, this function will stop in an infinite loop.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
CY_CFG_UNUSED
|
|
static void CyClockStartupError(uint8 errorCode);
|
|
CY_CFG_UNUSED
|
|
static void CyClockStartupError(uint8 errorCode)
|
|
{
|
|
/* To remove the compiler warning if errorCode not used. */
|
|
errorCode = errorCode;
|
|
|
|
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
|
|
/* we will end up here to allow the customer to implement something to */
|
|
/* deal with the clock condition. */
|
|
|
|
#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK
|
|
CY_CFG_Clock_Startup_ErrorCallback();
|
|
#else
|
|
/* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */
|
|
/* `#START CyClockStartupError` */
|
|
|
|
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */
|
|
/* we will end up here to allow the customer to implement something to */
|
|
/* deal with the clock condition. */
|
|
|
|
/* `#END` */
|
|
|
|
while(1) {}
|
|
#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */
|
|
}
|
|
#endif
|
|
|
|
#define CY_CFG_BASE_ADDR_COUNT 12u
|
|
CYPACKED typedef struct
|
|
{
|
|
uint8 offset;
|
|
uint8 value;
|
|
} CYPACKED_ATTR cy_cfg_addrvalue_t;
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: cfg_write_bytes32
|
|
********************************************************************************
|
|
* Summary:
|
|
* This function is used for setting up the chip configuration areas that
|
|
* contain relatively sparse data.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);
|
|
static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])
|
|
{
|
|
/* For 32-bit little-endian architectures */
|
|
uint32 i, j = 0u;
|
|
for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)
|
|
{
|
|
uint32 baseAddr = addr_table[i];
|
|
uint8 count = (uint8)baseAddr;
|
|
baseAddr &= 0xFFFFFF00u;
|
|
while (count != 0u)
|
|
{
|
|
CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value);
|
|
j++;
|
|
count--;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*******************************************************************************
|
|
* Function Name: ClockSetup
|
|
********************************************************************************
|
|
*
|
|
* Summary:
|
|
* Performs the initialization of all of the clocks in the device based on the
|
|
* settings in the Clock tab of the DWR. This includes enabling the requested
|
|
* clocks and setting the necessary dividers to produce the desired frequency.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
static void ClockSetup(void);
|
|
static void ClockSetup(void)
|
|
{
|
|
uint32 timeout;
|
|
uint8 pllLock;
|
|
|
|
|
|
/* Configure ILO based on settings from Clock DWR */
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
|
|
|
|
/* Configure IMO based on settings from Clock DWR */
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u);
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB)));
|
|
|
|
/* Configure PLL based on settings from Clock DWR */
|
|
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u);
|
|
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
|
|
/* Wait up to 250us for the PLL to lock */
|
|
pllLock = 0u;
|
|
for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
|
|
{
|
|
pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
|
|
CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
|
|
}
|
|
/* If we ran out of time the PLL didn't lock so go to the error function */
|
|
if (timeout == 0u)
|
|
{
|
|
CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
|
|
}
|
|
|
|
/* Configure Bus/Master Clock based on settings from Clock DWR */
|
|
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);
|
|
|
|
/* Configure USB Clock based on settings from Clock DWR */
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
|
|
}
|
|
|
|
|
|
/* Analog API Functions */
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: AnalogSetDefault
|
|
********************************************************************************
|
|
*
|
|
* Summary:
|
|
* Sets up the analog portions of the chip to default values based on chip
|
|
* configuration options from the project.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
static void AnalogSetDefault(void);
|
|
static void AnalogSetDefault(void)
|
|
{
|
|
uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
|
|
CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
|
|
}
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: SetAnalogRoutingPumps
|
|
********************************************************************************
|
|
*
|
|
* Summary:
|
|
* Enables or disables the analog pumps feeding analog routing switches.
|
|
* Intended to be called at startup, based on the Vdda system configuration;
|
|
* may be called during operation when the user informs us that the Vdda voltage
|
|
* crossed the pump threshold.
|
|
*
|
|
* Parameters:
|
|
* enabled - 1 to enable the pumps, 0 to disable the pumps
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
void SetAnalogRoutingPumps(uint8 enabled)
|
|
{
|
|
uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);
|
|
if (enabled != 0u)
|
|
{
|
|
regValue |= 0x00u;
|
|
}
|
|
else
|
|
{
|
|
regValue &= (uint8)~0x00u;
|
|
}
|
|
CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);
|
|
}
|
|
|
|
|
|
|
|
|
|
/*******************************************************************************
|
|
* Function Name: cyfitter_cfg
|
|
********************************************************************************
|
|
* Summary:
|
|
* This function is called by the start-up code for the selected device. It
|
|
* performs all of the necessary device configuration based on the design
|
|
* settings. This includes settings from the Design Wide Resources (DWR) such
|
|
* as Clocks and Pins as well as any component configuration that is necessary.
|
|
*
|
|
* Parameters:
|
|
* void
|
|
*
|
|
* Return:
|
|
* void
|
|
*
|
|
*******************************************************************************/
|
|
|
|
void cyfitter_cfg(void)
|
|
{
|
|
/* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */
|
|
static const uint8 CYCODE BS_IOPINS0_0_VAL[] = {
|
|
0x01u, 0x00u, 0x00u, 0xABu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
|
|
static const uint8 CYCODE BS_IOPINS0_7_VAL[] = {
|
|
0x0Fu, 0x00u, 0x00u, 0x2Fu, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
/* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */
|
|
static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {
|
|
0x00u, 0x00u, 0x00u, 0x28u, 0x28u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};
|
|
|
|
/* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */
|
|
static const uint8 CYCODE BS_IOPINS0_1_VAL[] = {
|
|
0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
|
|
static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {
|
|
0x00u, 0xAAu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
/* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */
|
|
static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {
|
|
0x00u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
|
|
static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {
|
|
0x00u, 0x43u, 0x43u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
|
|
static const uint8 CYCODE BS_IOPINS0_6_VAL[] = {
|
|
0x00u, 0xA4u, 0xA4u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
|
|
|
|
#ifdef CYGlobalIntDisable
|
|
/* Disable interrupts by default. Let user enable if/when they want. */
|
|
CYGlobalIntDisable
|
|
#endif
|
|
|
|
|
|
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u));
|
|
/* Setup clocks based on selections from Clock DWR */
|
|
ClockSetup();
|
|
/* Set Flash Cycles based on newly configured 64.00MHz Bus Clock. */
|
|
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));
|
|
/* Enable/Disable Debug functionality based on settings from System DWR */
|
|
CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));
|
|
|
|
{
|
|
static const uint32 CYCODE cy_cfg_addr_table[] = {
|
|
0x40004501u, /* Base address: 0x40004500 Count: 1 */
|
|
0x40005204u, /* Base address: 0x40005200 Count: 4 */
|
|
0x40011701u, /* Base address: 0x40011700 Count: 1 */
|
|
0x40011901u, /* Base address: 0x40011900 Count: 1 */
|
|
0x40014003u, /* Base address: 0x40014000 Count: 3 */
|
|
0x40014102u, /* Base address: 0x40014100 Count: 2 */
|
|
0x40014202u, /* Base address: 0x40014200 Count: 2 */
|
|
0x40014302u, /* Base address: 0x40014300 Count: 2 */
|
|
0x40014703u, /* Base address: 0x40014700 Count: 3 */
|
|
0x40014803u, /* Base address: 0x40014800 Count: 3 */
|
|
0x40014C02u, /* Base address: 0x40014C00 Count: 2 */
|
|
0x40015101u, /* Base address: 0x40015100 Count: 1 */
|
|
};
|
|
|
|
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
|
|
{0x7Eu, 0x02u},
|
|
{0x04u, 0x01u},
|
|
{0x1Cu, 0xFFu},
|
|
{0x64u, 0x03u},
|
|
{0x7Cu, 0x40u},
|
|
{0xEEu, 0x0Au},
|
|
{0xEEu, 0x0Au},
|
|
{0x33u, 0x80u},
|
|
{0x36u, 0x40u},
|
|
{0xCCu, 0x30u},
|
|
{0xA6u, 0x40u},
|
|
{0xA7u, 0x80u},
|
|
{0xA6u, 0x40u},
|
|
{0xA7u, 0x80u},
|
|
{0xA6u, 0x40u},
|
|
{0xA7u, 0x80u},
|
|
{0x08u, 0x08u},
|
|
{0x0Fu, 0x40u},
|
|
{0xC2u, 0x0Cu},
|
|
{0xAEu, 0x40u},
|
|
{0xAFu, 0x80u},
|
|
{0xEEu, 0x50u},
|
|
{0xACu, 0x08u},
|
|
{0xAFu, 0x40u},
|
|
{0x00u, 0x0Au},
|
|
};
|
|
|
|
|
|
|
|
CYPACKED typedef struct {
|
|
void CYFAR *address;
|
|
uint16 size;
|
|
} CYPACKED_ATTR cfg_memset_t;
|
|
|
|
static const cfg_memset_t CYCODE cfg_memset_list[] = {
|
|
/* address, size */
|
|
{(void CYFAR *)(CYREG_PRT5_DR), 16u},
|
|
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
|
|
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
|
|
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
|
|
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
|
|
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
|
|
};
|
|
|
|
uint8 CYDATA i;
|
|
|
|
/* Zero out critical memory blocks before beginning configuration */
|
|
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
|
|
{
|
|
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
|
|
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
|
|
}
|
|
|
|
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
|
|
|
|
/* Enable digital routing */
|
|
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
|
|
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);
|
|
}
|
|
|
|
|
|
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
|
|
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
|
|
/* Switch Boost to the precision bandgap reference from its internal reference */
|
|
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
|
|
|
|
/* Perform basic analog initialization to defaults */
|
|
AnalogSetDefault();
|
|
|
|
/* Configure alternate active mode */
|
|
CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);
|
|
}
|