First Run

First live tests on actual hardware

se-vga.sv

@@ -116,7 +116,7 @@ always_comb begin
 end
 
 assign nvramCE0 = (nvramWEpre | nvramCE0pre) & (nvramOE | vidBufSel);
-assign nvramCE1 = (nvramWEpre | nvramCE1pre) & (nvramOE | !vidBufSel);
+assign nvramCE1 = (nvramWEpre | nvramCE1pre) & (nvramOE | ~vidBufSel);
 
 assign nvramWE = nvramWEpre | pixClk;
 

sevga.vwf

@@ -842,11 +842,6 @@ SIGNAL("vramData[0]")
 	PARENT = "vramData";
 }
 
-GROUP("cpuAddr")
-{
-	MEMBERS = "cpuAddr[1]", "cpuAddr[2]", "cpuAddr[3]", "cpuAddr[4]", "cpuAddr[5]", "cpuAddr[6]", "cpuAddr[7]", "cpuAddr[8]", "cpuAddr[9]", "cpuAddr[10]", "cpuAddr[11]", "cpuAddr[12]", "cpuAddr[13]", "cpuAddr[14]", "cpuAddr[15]", "cpuAddr[16]", "cpuAddr[17]", "cpuAddr[18]", "cpuAddr[19]", "cpuAddr[20]", "cpuAddr[21]", "cpuAddr[22]", "cpuAddr[23]";
-}
-
 SIGNAL("cpusnoop:cpusnp|addrCache")
 {
 	VALUE_TYPE = NINE_LEVEL_BIT;
@@ -1197,6 +1192,31 @@ SIGNAL("cpusnoop:cpusnp|pendWriteLo")
 	PARENT = "";
 }
 
+GROUP("cpuAddr")
+{
+	MEMBERS = "cpuAddr[1]", "cpuAddr[2]", "cpuAddr[3]", "cpuAddr[4]", "cpuAddr[5]", "cpuAddr[6]", "cpuAddr[7]", "cpuAddr[8]", "cpuAddr[9]", "cpuAddr[10]", "cpuAddr[11]", "cpuAddr[12]", "cpuAddr[13]", "cpuAddr[14]", "cpuAddr[15]", "cpuAddr[16]", "cpuAddr[17]", "cpuAddr[18]", "cpuAddr[19]", "cpuAddr[20]", "cpuAddr[21]", "cpuAddr[22]", "cpuAddr[23]";
+}
+
+SIGNAL("nvramCE0")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("nvramCE1")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
 TRANSITION_LIST("cpuAddr[1]")
 {
 	NODE
@@ -2749,6 +2769,24 @@ TRANSITION_LIST("cpusnoop:cpusnp|pendWriteLo")
 	}
 }
 
+TRANSITION_LIST("nvramCE0")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 33000.0;
+	}
+}
+
+TRANSITION_LIST("nvramCE1")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 33000.0;
+	}
+}
+
 DISPLAY_LINE
 {
 	CHANNEL = "cpuAddr";
@@ -3905,6 +3943,24 @@ DISPLAY_LINE
 	TREE_LEVEL = 0;
 }
 
+DISPLAY_LINE
+{
+	CHANNEL = "nvramCE0";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 117;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "nvramCE1";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 118;
+	TREE_LEVEL = 0;
+}
+
 TIME_BAR
 {
 	TIME = 0;

vgaout.sv

@@ -25,29 +25,18 @@ module vgaout (
 wire vidMuxOut; // pixel data shift out
 wire vidActive; // combined active video signal
 
-wire vgaShiftL1; // Load VRAM data into register
-wire vgaShiftL2; // Load VRAM data into shifter
-
-// connect module for video out shift register
+wire nVidLoad;  // Load VRAM data into shifter
 vgaShiftOut vOut(
     .nReset(nReset),
     .clk(pixClock),
-    .shiftEn(vidActive),
-    .nLoad1(vgaShiftL1),
-    .nLoad2(vgaShiftL2),
+    .nLoad(nVidLoad),
     .parIn(vramData),
     .out(vidMuxOut)
 );
 
 always_comb begin
-    // load VRAM data into register
-    if(hCount[2:0] == 0) vgaShiftL1 <= !pixClock;
-    else vgaShiftL1 <= 1;
-
-    // load VRAM data into shifter
-    if(hCount[2:0] == 0) vgaShiftL2 <= !pixClock;
-    else if(hCount[2:0] == 1) vgaShiftL2 <= pixClock;
-    else vgaShiftL2 <= 1;
+    if(hCount[2:0] == 0) nVidLoad <= 0;
+    else nVidLoad <= 1;
 
     // combined video active signal
     if(hSEActive == 1'b1 && vSEActive == 1'b1) begin
@@ -58,7 +47,7 @@ always_comb begin
 
     // video data output
     if(vidActive == 1'b1) begin
-        vidOut <= vidMuxOut;
+        vidOut <= ~vidMuxOut;
     end else begin
         vidOut <= 1'b0;
     end
@@ -76,4 +65,4 @@ always_comb begin
     vramAddr[5:0]  <= hCount[8:3];
 end
     
-endmodule
+endmodule

vgashiftout.sv

@@ -10,6 +10,32 @@
 `ifndef VGASHIFTOUT
     `define VGASHIFTOUT
 
+module vgaShiftOut (
+    input wire nReset, clk, nLoad,
+    input logic [7:0] parIn,
+    output wire out
+);
+
+reg [8:0] shiftReg;
+
+always @(negedge clk or negedge nReset) begin
+    if(!nReset) shiftReg <= 0;
+    else begin
+        if(!nLoad) begin
+            shiftReg[8] <= shiftReg[7];
+            shiftReg[7:0] <= parIn;
+        end else begin
+            shiftReg[8:1] <= shiftReg[7:0];
+            shiftReg[0] <= 0;
+        end
+    end
+end
+
+assign out = shiftReg[8];
+
+endmodule
+
+/*
 module vgaShiftOut (
     input wire nReset,
     input wire clk,
@@ -53,5 +79,6 @@ module vgaShiftOut (
     // high-order bit of the shift register (second stage) is the serial output
     assign out = outReg[7];
 endmodule
+*/
 
 `endif

vgatest.sv

@@ -0,0 +1,75 @@
+/******************************************************************************
+ * SE-VGA
+ * VGA Output Test
+ * techav
+ * 2021-05-14
+ ******************************************************************************
+ * Test configuration for testily testing testy test hardware. 
+ * This is not a part of the actual configuration. It is a separate top-level
+ * entity for testing modules and hardware. Outputs a 512x342 pixel window of
+ * alternating black and white pixels in a 640x480 resolution screen.
+ *****************************************************************************/
+
+// all the same I's and O's as our proper configuration
+module vgatest (
+    input wire              nReset,     // System reset signal
+    input wire              pixClk,     // 25.175MHz pixel clock
+    output wire             nhSync,     // HSync signal
+    output wire             nvSync,     // VSync signal
+    output wire             vidOut,     // 1-bit Monochrome video signal
+
+    output logic [14:0]     vramAddr,   // VRAM Address bus
+    //inout logic [7:0]       vramData,   // VRAM Data bus
+    input logic [7:0]       vramData,
+    output wire             nvramOE,    // VRAM Read strobe
+    output wire             nvramWE,    // VRAM Write strobe
+    output wire             nvramCE0,   // VRAM Main chip select signal
+    output wire             nvramCE1,   // VRAM Alt chip select signal
+
+    input logic [23:1]      cpuAddr,    // CPU Address bus
+    //input logic [15:0]      cpuData,    // CPU Data bus
+    output logic [15:0]     cpuData,
+    input wire              ncpuAS,     // CPU Address Strobe signal
+    input wire              ncpuUDS,    // CPU Upper Data Strobe signal
+    input wire              ncpuLDS,    // CPU Lower Data Strobe signal
+    input wire              cpuRnW,     // CPU Read/Write select signal
+    input logic [2:0]       ramSize     // Select installed RAM size
+);
+
+logic [9:0] hCount, vCount;
+wire hActive, hSEActive;
+wire vActive, vSEActive;
+
+vgagen vgatiming(
+    .nReset(nReset),
+    .pixClk(pixClk),
+    .hCount(hCount),
+    .hActive(hActive),
+    .hSEActive(hSEActive),
+    .nhSync(nhSync),
+    .vCount(vCount),
+    .vActive(vActive),
+    .vSEActive(vSEActive),
+    .nvSync(nvSync)
+);
+
+reg outTog;
+
+always @(negedge pixClk or negedge nReset) begin
+    if(nReset == 0) begin
+        outTog <= 0;
+    end else begin
+        outTog <= !outTog;
+    end
+end
+
+assign vidOut = outTog & hSEActive & vSEActive;
+assign vramAddr = 0;
+assign nvramOE = 1;
+assign nvramWE = 1;
+assign nvramCE0 = 1;
+assign nvramCE1 = 1;
+assign cpuData[7:0] = ~vramData;
+assign cpuData[15:8] = vramData;
+
+endmodule