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https://github.com/techav-homebrew/SE-VGA.git
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Fixed image overwrite issues
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parent
5377d05895
commit
4be7d63105
21
se-xga.sv
21
se-xga.sv
@ -52,7 +52,8 @@ end
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// horizontal and vertical sync signals
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// horizontal and vertical sync signals
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always_comb begin
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always_comb begin
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if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
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//if(hCount >= 11'd1048 && hCount < 11'd1184) nhSyncInner <= 0;
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if(hCount >= 11'd1052 && hCount < 11'd1187) nhSyncInner <= 0;
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else nhSyncInner <= 1;
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else nhSyncInner <= 1;
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nhSync <= nhSyncInner;
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nhSync <= nhSyncInner;
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@ -72,7 +73,7 @@ wire hLoad; // load pixel data from vram when asserted
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assign vidActive = hActive & vActive;
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assign vidActive = hActive & vActive;
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always_comb begin
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always_comb begin
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if(hCount >= 0 && hCount < 1024) hActive <= 1;
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if(hCount >= 3 && hCount < 1027) hActive <= 1;
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else hActive <= 0;
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else hActive <= 0;
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if(vCount >= 0 && vCount < 684) vActive <= 1;
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if(vCount >= 0 && vCount < 684) vActive <= 1;
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@ -181,12 +182,12 @@ always_comb begin
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end
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end
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S3, S4: begin
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S3, S4: begin
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// address bus for upper write cycles
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// address bus for upper write cycles
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vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
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vramAddr[14:1] <= cpuAddrShift;
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vramAddr[0] <= 0;
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vramAddr[0] <= 0;
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end
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end
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S5, S6: begin
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S5, S6: begin
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// address bus for lower write cycles
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// address bus for lower write cycles
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vramAddr[14:1] <= cpuAddr[14:1] - 14'h1380;
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vramAddr[14:1] <= cpuAddrShift;
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vramAddr[0] <= 1;
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vramAddr[0] <= 1;
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end
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end
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default: begin
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default: begin
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@ -210,8 +211,6 @@ end
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* signals and see the strapped pattern output on screen.
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* signals and see the strapped pattern output on screen.
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*****************************************************************************/
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*****************************************************************************/
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logic [8:0] vidData; // the video data we are displaying
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logic [8:0] vidData; // the video data we are displaying
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//wire [2:0] vidSeq; // sequence counter, derived from hCount
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//wire tick, tock; // even/odd pulses of pixel clock divided by 2
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// output shift register
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// output shift register
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always @(posedge pixClk) begin
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always @(posedge pixClk) begin
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@ -221,7 +220,7 @@ always @(posedge pixClk) begin
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end else if(!hCount[0] && vidActive) begin
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end else if(!hCount[0] && vidActive) begin
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// shift out video data
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// shift out video data
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vidData[8:1] <= vidData[7:0];
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vidData[8:1] <= vidData[7:0];
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vidData[0] <= 0;
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vidData[0] <= 1;
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end
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end
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end
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end
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@ -263,9 +262,15 @@ reg cpuUWriteSrv, cpuLWriteSrv, cpuVIASrv;
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wire cpuBufSel;
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wire cpuBufSel;
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wire cpuBufAddr;
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wire cpuBufAddr;
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reg vidBufSel;
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reg vidBufSel;
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wire [13:0] cpuAddrShift = cpuAddr[14:1] - 14'h1380;
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wire cpuBufRange;
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// these are some helpful signals that shortcut the CPU buffer & VIA addresses
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// these are some helpful signals that shortcut the CPU buffer & VIA addresses
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always_comb begin
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always_comb begin
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/*if(cpuAddr[14:1] >= 14'h1380
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&& cpuAddr[14:1] < 14'h3E40) cpuBufRange <= 1;
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else cpuBufRange <= 0;*/
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cpuBufRange <= (cpuAddr[14:1] >= 14'h1380) & (cpuAddr[14:1] < 14'h3E40);
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if(!ncpuAS && !cpuRnW
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if(!ncpuAS && !cpuRnW
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&& !cpuAddr[23] && !cpuAddr[22] // first two bits always 0
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&& !cpuAddr[23] && !cpuAddr[22] // first two bits always 0
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&& !(cpuAddr[21] ^ ramSize[2]) // compare with RAM Size bits
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&& !(cpuAddr[21] ^ ramSize[2]) // compare with RAM Size bits
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@ -273,7 +278,7 @@ always_comb begin
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&& !(cpuAddr[19] ^ ramSize[0])
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&& !(cpuAddr[19] ^ ramSize[0])
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&& cpuAddr[18] && cpuAddr[17] // next three bits always 1
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&& cpuAddr[18] && cpuAddr[17] // next three bits always 1
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&& cpuAddr[16] // skip 15, it selects buffers
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&& cpuAddr[16] // skip 15, it selects buffers
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&& (cpuAddr[14] || cpuAddr[13]) // if neither 13|14 then not buffer
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&& cpuBufRange // only select buffer addresses
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) begin
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) begin
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cpuBufAddr <= 1;
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cpuBufAddr <= 1;
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end else begin
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end else begin
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