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Starting new cpu snoop
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65
se-xga.sv
65
se-xga.sv
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@ -42,17 +42,17 @@ logic [9:0] vCount; // 0..805
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// horizontal counter
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) hCount <= 0;
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else begin
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if(hCount < 1343) hCount <= hCount + 1;
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else if(!pixClk) begin
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if(hCount < 1343) hCount <= hCount + 11'd1;
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else hCount <= 0;
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end
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end
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// vertical counter
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always @(negedge pixClk or negedge nReset) begin
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always @(negedge nhSync or negedge nReset) begin
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if(!nReset) vCount <= 0;
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else begin
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if(vCount < 805) vCount <= vCount + 1;
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else if(!pixClk) begin
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if(vCount < 805) vCount <= vCount + 10'd1;
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else vCount <= 0;
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end
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end
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@ -75,7 +75,7 @@ wire hActive, vActive; // active video signals. vidout black when negated
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wire vidActive; // active when both hActive and vActive asserted
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wire hLoad; // load pixel data from vram when asserted
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assign vidActive = hActive & vidActive;
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assign vidActive = hActive & vActive;
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always_comb begin
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if(hCount >= 1 && hCount < 1025) hActive <= 1;
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@ -97,6 +97,7 @@ end
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logic [8:0] vidData; // the video data we are displaying
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wire [2:0] vidSeq; // sequence counter, derived from hCount
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wire tick, tock; // even/odd pulses of pixel clock divided by 2
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wire [14:0] readAddr; // VRAM read address
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assign vidSeq = hCount[3:1];
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assign tick = !hCount[0];
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@ -104,8 +105,8 @@ assign tock = hCount[0];
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) vidData <= 0;
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else
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if(tock && hLoad && vidSeq == 0) begin
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else if(!pixClk) begin
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if(tock && hLoad && vidSeq == 3'd0) begin
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// store the VRAM data in vidData[8:1]
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//vidData[0] <= vidData[1]; // this should actually have already been done
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vidData[8:1] <= vramData;
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@ -123,8 +124,15 @@ always_comb begin
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else vidOut <= 0;
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// vram read signal can be asserted here
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if(vidActive && vidSeq == 0) nvramOE <= 0;
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if(vidActive && vidSeq == 3'd0) nvramOE <= 0;
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else nvramOE <= 1;
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// we'll be interleaving VRAM accesses, so the highest address bit will be
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// used to select between Main & Aux video buffers.
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// hCount[4] will be used to select between SRAM chips
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readAddr[14] <= vidBufSel;
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readAddr[13:5] <= vCount[9:1];
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readAddr[4:0] <= hCount[9:5];
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end
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@ -140,6 +148,20 @@ end
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// vramCE[x] should be asserted when vidSeq == 0
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// vramOE should be asserted when vidSeq == 0 && vidActive
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// vramWE should be asserted on tock pulses of write sequences
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wire [14:0] writeAddr;
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reg vidBufSel;
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wire nvramCE0cpu, nvramCE1cpu;
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reg nvramWEpre;
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always @(negedge pixClk or negedge nReset) begin
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if(nReset) begin
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nvramWEpre <= 1;
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end else if(!pixClk && vidSeq != 0 && (!ncpuLDS || !ncpuUDS) && tock) begin
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end
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end
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/*
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// link module that snoops cpu writes
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@ -176,12 +198,31 @@ cpusnoop cpusnp(
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.ncpuLDS(ncpuLDS),
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.cpuRnW(cpuRnW),
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.cpuClk(cpuClk),
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.vramAddr(),
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.vramAddr(writeAddr),
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.vramDataOut(),
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.nvramWE(),
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.nvramCE0(),
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.nvramCE1(),
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.nvramCE0(nvramCE0cpu),
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.nvramCE1(nvramCE1cpu),
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.vidBufSelOut(),
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.ramSize(ramSize)
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);
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*/
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always_comb begin
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if(nvramOE == 0) vramAddr <= readAddr;
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else if(nvramWE == 0) vramAddr <= writeAddr;
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else vramAddr <= 0;
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if(nvramOE == 0) begin
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nvramCE0 <= hCount[4];
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nvramCE1 <= ~hCount[4];
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end else if(nvramWE == 0) begin
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nvramCE0 <= nvramCE0cpu;
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nvramCE1 <= nvramCE1cpu;
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end else begin
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nvramCE0 <= 1;
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nvramCE1 <= 1;
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end
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end
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endmodule
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