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VIA snooping
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parent
3669e3a66b
commit
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23
se-xga.sv
23
se-xga.sv
@ -183,14 +183,15 @@ end
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wire [14:0] writeAddr;
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reg vidBufSel;
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wire nvramCE0cpu, nvramCE1cpu, nvramWEcpu;
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reg [1:0] snoopCycleState;
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reg [2:0] snoopCycleState;
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// define state machine states
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parameter
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S0 = 2'b00, // idle
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S1 = 2'b01, // write high-order byte
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S2 = 2'b11, // write low-order byte
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S3 = 2'b10; // wait for CPU cycle end
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S0 = 2'b000, // idle
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S1 = 2'b001, // write high-order byte
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S2 = 2'b011, // write low-order byte
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S3 = 2'b010, // wait for CPU cycle end
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S4 = 2'b110; // VIA write cycle
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always @(negedge pixClk or negedge nReset) begin
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if(!nReset) begin snoopCycleState <= S0;
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@ -206,6 +207,9 @@ always @(negedge pixClk or negedge nReset) begin
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// Otherwise, we'll stay here on S0
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if(cpuBufAddr && tock && !ncpuUDS && vidSeq != 7) snoopCycleState <= S1;
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else if(cpuBufAddr && tick && !ncpuLDS && vidSeq != 1) snoopCycleState <= S2;
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else if(!ncpuAS && !ncpuUDS && !cpuRnW
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&& cpuAddr[22:18] == 5'h1D
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&& cpuAddr[11:7] == 5'h1F) snoopCycleState <= S4;
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else snoopCycleState <= S0;
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end
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S1 : begin
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@ -225,6 +229,13 @@ always @(negedge pixClk or negedge nReset) begin
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if(!ncpuLDS || !ncpuUDS) snoopCycleState <= S3;
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else snoopCycleState <= S0;
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end
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S4 : begin
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// CPU is addressing VIA Port A. Bit 6 will select the active
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// screen buffer. 1=Main, 0=Alt
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// After saving the selection, move to S3 to wait for cycle end
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vidBufSel <= !cpuData[14];
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snoopCycleState <= S3
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end
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default: begin
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// shouldn't ever be here
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snoopCycleState <= S0;
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@ -245,7 +256,7 @@ always_comb begin
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else if(snoopCycleState == S2) vramData <= cpuData[7:0];
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else vramData <= 8'hZ;
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writeAddr[13:0] <= cpuAddr[14:1];
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writeAddr[13:0] <= cpuAddr[14:1] - 14'h1380;
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writeAddr[14] <= cpuBufSel;
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end
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