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Author	SHA1	Message	Date
techav	7169786caa	Add CC-BY-SA license and initial Rev3 Readme	2023-07-14 15:25:57 -05:00
techav	a806219b67	Cleanup for DRC	2023-07-14 13:04:30 -05:00
techav	9abd2f0997	Multiplex CPU bus and add 24bpp output	2023-07-13 21:24:12 -05:00
techav	e86cd941ca	R3 PCB layout first draft	2023-07-01 02:08:46 -05:00
techav	f15cd37581	R3 Initial schematic complete, start routing	2023-06-30 00:05:36 -05:00
techav	a351ec4477	Rev3 Initial Schematic	2023-06-29 15:34:40 -05:00
techav	4302d72405	Cleanup old logic	2021-10-22 22:37:15 -05:00
techav	fca75c2c4c	Update readme	2021-10-22 22:36:03 -05:00
techav	42f59513e1	Merge pull request #1 from techav-homebrew/XGA ... Xga	2021-10-22 22:24:59 -05:00
techav	a9b119fb6d	Mostly working	2021-10-22 22:18:44 -05:00
techav	1137244a39	Rewrite again	2021-10-17 03:41:04 -05:00
techav-homebrew	3c12b07c70	Another fresh start	2021-10-17 01:25:27 -05:00
techav	7e2413150f	Cleanup	2021-10-17 01:24:22 -05:00
techav	4be7d63105	Fixed image overwrite issues	2021-10-12 23:28:59 -05:00
techav	5377d05895	Rebuilt state machine again	2021-10-11 21:25:28 -05:00
techav	6f2f67ef05	New State Machine	2021-10-11 16:25:40 -05:00
techav	373b0ec9b5	Debugging VRAM Write Timing	2021-10-09 14:47:53 -05:00
techav-homebrew	97b0b72794	VIA snooping	2021-10-07 21:35:29 -05:00
techav-homebrew	3669e3a66b	CPU Snoop First Draft	2021-10-07 21:17:36 -05:00
techav	90d5384b90	Starting new cpu snoop	2021-10-07 18:54:47 -05:00
techav	4f08c1f6fc	Start logic rebuild for XGA ... Ground-up rewrite of the video timing and output logic for XGA. Much simpler than the initial VGA logic. First draft, incomplete.	2021-08-04 23:40:16 -05:00
techav	c4b11b0a4b	Change multiplier part ... Changed 512MLF to 511MLF due to EOL	2021-07-26 22:23:40 -05:00
techav	51da925261	XGA Board Rev ... Rework of board to add support for pixel-doubled image on XGA resolution frame, and installation in Plus or 512k	2021-07-25 18:11:49 -05:00
techav	89ce4cbc1d	Revert "Preprep for iCE40" ... This reverts commit 0b2eb362d8.	2021-07-25 12:02:03 -05:00
techav	5b67fdfe53	Merge branch 'main' of https://github.com/techav-homebrew/SE-VGA into main	2021-07-25 12:00:29 -05:00
techav	0e9c2df93c	Add Compiled CPLD Configuration ... Both the .pof for Altera CPLD and .jed for Atmel CPLD	2021-07-25 11:59:27 -05:00
techav	eecc0cbe93	Add Compiled CPLD Configuration ... Both the .pof for Altera CPLD and .jed for Atmel CPLD	2021-06-05 17:57:10 -05:00
techav	0b2eb362d8	Preprep for iCE40	2021-05-23 22:10:04 -05:00
techav	5d3dd1f0eb	Update Readme	2021-05-21 22:44:26 -05:00
techav	22239fecef	Add Gerbers	2021-05-21 22:04:00 -05:00
techav	b0815fb726	Merge branch 'main' of https://github.com/techav-homebrew/SE-VGA into main	2021-05-21 21:47:29 -05:00
techav	5b1e2ecc72	CPU Snoop Fixes ... Fix for VRAM writes sometimes overlapping VRAM reads	2021-05-21 21:47:22 -05:00
techav	bfeba8c649	Update README.md	2021-05-20 00:10:00 -05:00
techav	04faf575f9	Debugging CPU Bus Snooping	2021-05-16 12:22:28 -05:00
techav	207acc2eaa	First Run ... First live tests on actual hardware	2021-05-14 23:48:34 -05:00
techav	3fe79659f3	Pin Assignments	2021-04-19 21:01:08 -05:00
techav	85a3cc95d9	Add Alternate Frame Buffer Support	2021-04-19 20:45:11 -05:00
techav	57436785a2	Documentation Cleanup	2021-04-18 14:31:05 -05:00
techav	14e5c8eb39	Refactor Video Out Sequence	2021-04-18 13:19:16 -05:00
techav	995be6b5dc	Getting ready for a large refactor	2021-04-18 12:50:43 -05:00
techav	c4bc1c4be5	CPU Cycle Improvements 2	2021-04-18 12:07:42 -05:00
techav	3b00823d6c	CPU Cycle Improvements 1	2021-04-18 10:28:04 -05:00
techav	7a519feab3	CPU cycle state machine	2021-04-17 15:41:53 -05:00
techav	bbae9212e8	New output stage	2021-04-12 22:07:18 -05:00
techav	89040b43b4	First compile	2021-04-11 23:46:29 -05:00
techav	0e5df6ce76	partial draft 2	2021-04-07 22:50:46 -05:00
techav	77a0a23e1a	partial draft 1	2021-04-06 23:15:48 -05:00
techav	eaf6747995	Initial commit	2021-04-06 19:38:45 -05:00