mirror of
https://github.com/techav-homebrew/SE-VGA.git
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47 lines
1.8 KiB
Systemverilog
47 lines
1.8 KiB
Systemverilog
/******************************************************************************
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* SE-VGA
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* Top-level module
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* techav
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* 2021-04-06
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******************************************************************************
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* Pulls together all the smaller modules to form the SE-VGA adapter
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*****************************************************************************/
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module design sevga (
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input wire nReset, // System reset signal
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input wire pixClk, // 25.175MHz pixel clock
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output wire nhSync, // HSync signal
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output wire nvSync, // VSync signal
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output wire vidOut, // 1-bit Monochrome video signal
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output logic [12:0] vramAddr, // VRAM Address bus
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inout logic [7:0] vramData, // VRAM Data bus
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output wire nvramOE, // VRAM Read strobe
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output wire nvramWE, // VRAM Write strobe
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input logic [23:1] cpuAddr, // CPU Address bus
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input logic [15:0] cpuData, // CPU Data bus
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input wire ncpuAS, // CPU Address Strobe signal
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input wire ncpuUDS, // CPU Upper Data Strobe signal
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input wire ncpuLDS, // CPU Lower Data Strobe signal
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input wire cpuRnW, // CPU Read/Write select signal
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input wire cpuClk // CPU Clock
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);
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logic [9:0] hCount;
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logic [9:0] vCount;
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wire hActive;
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wire hSEActive;
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logic [7:0] vidVramData;
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logic [12:0] vidVramAddr;
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// link module that generates all our timing signals
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vgagen vgatiming(nReset,pixClk,hCount,hActive,hSEActive,nhSync,vCount,vActive,vSEActive,nvSync);
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// link module that fetches & outputs video data
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vgaout vidvram(pixClock,nReset,hCount,vCount,hSEActive,vSEActive,vidVramData,vidVramAddr,nvramOE,vidOut);
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// link module that handles cpu writes
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endmodule |