Macintosh-HW
/
VideoMacPacHack
mirror of https://github.com/apmcpherson/VideoMacPacHack.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added documentation on VMP hardware and software

This commit is contained in:
Andrew McPherson 2020-04-06 01:07:30 +01:00
parent 3467c40331
commit 59c02b972c
2 changed files with 205 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

135
documentation/hardware.md Normal file
View File

@ -0,0 +1,135 @@
# Video Mac Pac hardware
The following document is based on an analysis and reverse engineering of the Video Mac Pac board. To date we have not found any original documentation on this design.
## Operation overview
The Video Mac Pac, designed in 1991 by Computer Care Inc., is a PDS expansion card for the Macintosh Portable (M5120 and M5126) that provides a second video output in addition to the Portable’s built-in screen. It supports 1-bit video at several resolutions:
* 640x872 (Apple Portait Display)
* 640x872 (Sunkyung FPD)
* 640x872 (Samsung FPD)
* 640x480 (Apple Monochrome Display)
* 640x480 (VGA)
* 800x600 (Super VGA)
* 528x348 (Mono TTL)
* 272x208 (TV/VCR)
These resolutions are selectable through the Video Mac Pac control panel which must be installed for the card to work.
The hardware design and software drivers appear to be closely related to the Lapis DisplayServer-SE video card. The card is based on a Xilinx CPLD whose firmware is loaded at boot by the control panel, along with VRAM and some glue logic for interfacing to the PDS slot and to the display.
## CPLD
The Video Mac Pac is based on the Xilinx `XC2018-100PC84` CPLD, which has the following specifications:
* 84-pin PLCC package
* 5V logic
* 1800 gates
* 74 I/Os
* 100ns toggle rate
The size of a program configuration on the XC2018 is 17878 bits. There is no non-volatile storage either on the XC2018 or elsewhere on the Video Mac Pac, meaning that the CPLD configuration is downloaded by the Macintosh on power-up.
On the VMP, the XC2018 mode pins `M0, M1, M2` are configured as `101`, corresponding to Peripheral mode. In this mode, the program is clocked in 1 bit at a time on the `DIN` and `WRT` pins.
For comparison, the Lapis DisplayServer-SE is also based on the XC2018. The SE-DPD (capable of driving dual page displays) instead uses the `XC3020-70-PC84`.
## VRAM
The VMP uses four Micron `MT42C4064Z-10` 64kx4 VRAM ICs. These are in a 24-pin ZIP package (i.e. SIP with staggered leads). Each VRAM chip handles 4 bits of a 16-bit data word.
The CPLD maps the VRAM to the memory address space from `$720000` to `$73FFFF` (128k bytes in total).
## GAL
The CPLD must be programmed by the Macintosh using the Video Mac Pac control panel. A `GAL16V8-25LNC` IC on the board implements an address decoder for address `$740200` (binary `0111 010x xxxx xx1x xxxx xxxx`).
The GAL also takes as input a sense line (active high) from the external video dongle. When the dongle is connected, address `$740200` is matched and `AS/` is low, the output (tied to the `WRT` pin on the CPLD) goes low. This feature is used to program the CPLD after power-on, after which point further communication takes place directly to the CPLD via the bus on the PDS slot.
If the dongle is not connected when the control panel loads, the CPLD will not be programmed and the video card will not operate until a restart takes place.
## PDS slot
See Apple's *Designing Cards and Drivers for the Macintosh Family* for the pinout of the Macintosh Portable PDS slot. The following pins of the PDS slot connect to the CPLD:
* Clock signal `16M`
* All address lines `A23-A0`
* Data line `D0` (connected to `DIN` to program the CPLD)
* Address strobe `/AS`
* Data strobes `/UDS` and `/LDS`
* Read/write signal `R/W`
* Acknowledge signals `/DTACK` and `/EXT.DTACK`
* Reset signal `/SYS.RST`
The following parts of the PDS slot connect directly to the VRAM:
* Data lines `D15-D0`, 4 bits per IC
All other VRAM pins are connected via the CPLD.
## Relay
The VMP contains a miniature 5V relay which is switched by way of the PDS signal `5/0V`. This powers down the card when the Portable goes to sleep.
When the Portable wakes from sleep, the CPLD program will be lost and it appears that a power cycle is required to enable the external screen.
## Oscillators
The VMP has 3 oscillator cans: 36MHz, 50.35MHz, 57.2832MHz. The 36MHz oscillator is socketed, while the other two are soldered. One of the three oscillator signals is chosen by the CPLD depending on the screen resolution. These provide the pixel clock for the video output.
The oscillators are not powered directly on the board. Rather, power to the oscillators is routed to a pin on the external video dongle connector, and the dongle routes the power back to the oscillators. This appears to be a power saving measure when the dongle is not connected.
In addition to the three oscillators, the card receives a 16MHz clock from the PDS slot.
## Outputs
The CPLD generates eight output logic signals which are buffered through a `74F244` octal buffer. These signals include:
* Three video signals. Our testing showed that these three always generate the same signal, as the card is 1-bit monochrome, but perhaps keeping separate signals was intended for a future design which would be full colour.
* Horizontal and vertical sync
* Three other signals which measure as constant high or low depending on the chosen resolution. These may have performed control functions for an external dongle (now lost).
The signals appear on a 20-pin header with the following pinout:
| pin | description | pin | description |
| --- | -------------- | --- | ----------- |
| 1 | oscillator +5V | 2 | +5V out |
| 3 | ground | 4 | sense input |
| 5 | ground | 6 | HSYNC |
| 7 | ground | 8 | VSYNC |
| 9 | ground | 10 | unknown 1 |
| 11 | ground | 12 | video 1 |
| 13 | ground | 14 | video 2 |
| 15 | ground | 16 | video 3 |
| 17 | ground | 18 | unknown 2 |
| 19 | ground | 20 | unknown 3 |
## Video Adapter Dongle
The VMP has a 20-pin IDC header, which connects by a ribbon cable to a DB25 male connector mounted in the rear cover of the Portable. This presumably connects to a dongle which provides the last step of signal conditioning and the correct pinout for the monitor in question.
We do not have the original dongle, however based on experimentation we have worked out its probable functions:
* The dongle provides a loopback between the +5V power supply and the power input to the oscillators. This is presumably to reduce power consumption when the dongle isn’t connected and the card is not in use.
* The DB25 contains a sense line to the GAL which is responsible for programming the CPLD. On the dongle, this line is pulled up to +5V, allowing the GAL to be programmed and the card to become operational only when the dongle is connected at boot.
* The dongle may provide level-shifting for driving analog monitors (e.g. VGA, Apple 13”). For TTL monitors a different dongle might have been used which passed through the video signal directly.
The pinout of the DB25 male is as follows:
| pin | description | pin | description |
| --- | -------------- | --- | ----------- |
| 1 | oscillator +5V | 14 | +5V out |
| 2 | ground | 15 | sense input |
| 3 | ground | 16 | HSYNC |
| 4 | ground | 17 | VSYNC |
| 5 | ground | 18 | unknown 1 |
| 6 | ground | 19 | video 1 |
| 7 | ground | 20 | video 2 |
| 8 | ground | 21 | video 3 |
| 9 | ground | 22 | unknown 2 |
| 10 | ground | 23 | unknown 3 |
| 11 | n/c | 24 | n/c |
| 12 | n/c | 25 | n/c |
| 13 | n/c | | |

70
documentation/software.md Normal file
View File

@ -0,0 +1,70 @@
# Video Mac Pac software
The *Video Mac Pac 4.1* control panel (CDEV) contains the drivers for the CPLD and several options for controlling the card. It allows a choice of resolutions, which take effect on power cycle -- not necessarily on reset since the CPLD needs to be powered down.
The external screen can be configured to be on the left or the right of the Portable screen, and the menu bar can be moved between screens. The Portable screen can also be disabled. These changes also take effect at restart.
When the Portable sleeps, the CPLD settings are lost and the external screen does not reappear on wake. The machine needs to be rebooted for the CPLD code to be reloaded.
## Resolutions
The control panel offers a choice of the following resolutions (all at 1-bit monochrome). The VSYNC and HSYNC frequencies of each resolution were measured, and it was determined which of the three oscillator cans each resolution was derived from:
| Resolution | Name | Frequencies | Oscillator | Notes |
| ---------- | -------------- | ------------------- | ---------- | --------- |
| 640x872 | Apple Portrait | 68.8kHz H, 74.5Hz V | 57.2832MHz | |
| 640x872 | Sunkyung FPD | 68.8kHz H, 74.5Hz V | 57.2832MHz | no video |
| 640x872 | Samsung FPD | n/a | n/a | see below |
| 640x480 | Apple M/C | 39.9kHz? H, 76Hz? V | 36MHz | see below |
| 640x480 | VGA | 31.5kHz H, 60Hz V | 50.35MHz | |
| 800x600 | Super VGA | 35.1kHz H, 56Hz V | 36MHz | |
| 528x348 | Mono TTL | 18.6kHz H, 50Hz V | 50.35MHz | no video |
| 272x208 | TV/VCR | n/a | n/a | untested |
The `Sunkyung FPD` and `TV/VCR` modes appear to use a different pin for video output, so they do not directly work with the dongle we have developed. Mono TTL could not be tested as it was below the scan range of the monitor for testing, but may also use a different video pin.
The `Samsung FPD` mode does not work because its corresponding `DS#1` resource is corrupt, missing a few bytes of the CPLD code.
The `Apple M/C` mode produces the wrong frequenceis for the Apple Monochrome Monitor. This mode may expect a different oscillator to be installed in the 36MHz socket, e.g. 31.5MHz, to produce a 66.7Hz refresh as expected.
## CDEV Resources
The Video Mac Pac control panel (CDEV) appears to be derived from the Lapis DisplayServer CDEV, which is used in several Lapis video cards for the Macintosh SE and later machines.
Some of the important resources in the CDEV include:
* `Glue`: Holds 68k code implementing the display driver and hardware communication.
* `DS#1`: There are several such resources in the CDEV. Each one corresponds to a display resolution.
* Offset `$92`: Holds the length of the CPLD code in bytes. The value in each case is `$8BC`: 2236 bytes, or 17888 bits. The XC2018 has a program space of 17878 bits.
* Offset `$94`: CPLD bit stream begins
* `UVDS`: Holds the information on the current configuration ID (referring to an ID of a `DS#1` resource) and the settings for display arrangement, menu bar, and whether the internal screen is used.
For comparison: `DS#1` resources can also be found in the Lapis Dual Screen Software INIT. The DisplayServer PDS/30 CDEV contains `DS#4` resources, and the DisplayServer II-DPD CDEV contains `DS#6` resources, which appear to operate on similar principles. In principle, it might be possible to find CPLD code to support other resolutions from another CDEV or to reverse engineer it with contemporary Xilinx development tools.
## Memory-Mapped Addressing
The Macintosh Portable is a 68000 machine with 24-bit addressing. It reserves address range `$000000` to `$8FFFFF` for RAM (for a maximum of 9MB total).
On the Video Mac Pac, I/O is memory-mapped with the lowest region starting at `$720000`. This implies that the VMP will not function correctly if more than 7MB of RAM is installed in the Portable. (The largest factory configuration was 4MB (1MB onboard + 3MB expansion), but modern expansion cards are available providing up to 9MB total RAM.)
An analysis of the CDEV shows the following addresses in use:
* `$720000`: VRAM base, addressable once CPLD code is loaded
* Maximum length `$20000` (128 kB = max 1M pixels)
* `$73FFEA` is used in the CDEV for a special checksum word, `BECK`, which is written and subsequently read to detect the presence of the card
* `$73FFEE` is used in the CDEV to hold the ID of the current `DS#1` resource which contains information on the screen resolution
* These two checks also serve to confirm that the CPLD has been programmed, since the VRAM is only accessible on the bus by way of the CPLD.
* `$740000`: unknown function
* This address is referenced in various places in the CDEV code. For example, before the CPLD code is loaded by writing it out to `$740200`, the CDEV writes `$FF` to address `$740000`. However, it is not clear what the function of this write is or whether the address has any specific meaning to the hardware.
* `$740200`: `WRT` pin on CPLD
* Any memory access to this address causes the GAL to bring the `WRT` pin on the CPLD low. Because data line `D0` is attached to the `DIN` pin of the CPLD, the practical effect is that each write to `$740200` shifts in a single bit of the CPLD program.
The programming procedure for the CPLD thus consists of the following for each byte of the `DS#1` resource:
* Write byte to `$740200`
* Shift byte 1 bit right
* Write again
* Repeat the above 8 times in total, then move to the next byte