WarpLC Project Status (11/01/2021 - 06:10:50)
Project File: | WarpLC.xise | Parser Errors: | No Errors
Module Name: | WarpLC | Implementation State: | Mapped

Target Device:

xc6slx9-2ftg256

- Errors:

No Errors

Product Version:

ISE 14.7

- Warnings:

53 Warnings (6 new)

Design Goal:</dif>

Balanced

- Routing Results:

Design Strategy:</dif>

Xilinx Default (unlocked)

- Timing Constraints:

Environment:</dif>

System Settings

- Final Timing Score:

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 1 | 11,440 | 1% |
Number used as Flip Flops | 1 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 105 | 5,720 | 1% |
Number used as logic | 25 | 5,720 | 1% |
Number using O6 output only | 7 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 17 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 80 | 1,440 | 5% |
Number used as Dual Port RAM | 80 |  |  |
Number using O6 output only | 80 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 0 |  |  |
Number of occupied Slices | 35 | 1,430 | 2% |
Number of MUXCYs used | 8 | 2,860 | 1% |
Number of LUT Flip Flop pairs used | 106 |  |  |
Number with an unused Flip Flop | 105 | 106 | 99% |
Number with an unused LUT | 1 | 106 | 1% |
Number of fully used LUT-FF pairs | 0 | 106 | 0% |
Number of unique control sets | 2 |  |  |
Number of slice register sites lost to control set restrictions | 7 | 11,440 | 1% |
Number of bonded IOBs | 66 | 186 | 35% |
IOB Flip Flops | 5 |  |  |
Number of RAMB16BWERs | 4 | 32 | 12% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2FBs | 1 |  |  |
Number used as BUFIO2FB_2CLKs | 0 |  |  |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 5 | 200 | 2% |
Number used as OLOGIC2s | 5 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 0 | 4 | 0% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 16 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 2 | 50% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.54 |  |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Tue Nov 2 00:33:02 2021 | 0 | 40 Warnings (6 new) | 12 Infos (0 new)
Translation Report | Current | Tue Nov 2 00:33:08 2021 | 0 | 13 Warnings (0 new) | 0
Map Report | Current | Tue Nov 2 00:33:32 2021 | 0 | 0 | 8 Infos (1 new)
Place and Route Report | Out of Date | Tue Nov 2 00:29:15 2021 | 0 | 0 | 1 Info (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Out of Date | Tue Nov 2 00:29:21 2021 |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
Post-Map Static Timing Report | Current | Tue Nov 2 00:33:37 2021
Physical Synthesis Report | Current | Tue Nov 2 00:33:32 2021

Date Generated: 11/02/2021 - 11:45:39