ClkGen Project Status (10/31/2021 - 15:38:40)
Project File: | WarpLC.xise | Parser Errors: | No Errors
Module Name: | ClkGen | Implementation State: | Placed and Routed

Target Device:

xc6slx9-2ftg256

- Errors:

Product Version:

ISE 14.7

- Warnings:

Design Goal:</dif>

Balanced

- Routing Results:

Design Strategy:</dif>

Xilinx Default (unlocked)

- Timing Constraints:

Environment:</dif>

- Final Timing Score:

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report |  |  |  |  |
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
CPLD Fitter Report (Text) |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
Post-Map Static Timing Report | Out of Date | Sun Oct 31 14:40:54 2021
Physical Synthesis Report | Out of Date | Sun Oct 31 15:38:26 2021

Date Generated: 10/31/2021 - 15:38:40