// file: PLL.v
// 
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____66.667______0.000______50.0______252.559____182.342
//
//----------------------------------------------------------------------------
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________33.3333____________0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "PLL,clk_wiz_v3_6,{component_name=PLL,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=30.000,clkin2_period=30.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module PLL
 (// Clock in ports
  input         CLKIN,
  input         CLKFB_IN,
  // Clock out ports
  output        FSBCLK,
  output        CLKFB_OUT,
  // Status and control signals
  output        LOCKED
 );

  // Input buffering
  //------------------------------------
  IBUFG clkin1_buf
   (.O (clkin1),
    .I (CLKIN));

  wire clkfb_ibuf2bufio2fb;
  wire clkfb_in_buf_out;

  // feedback clock input buffer
  IBUFG clkfb_ibufg
   (.O  (clkfb_ibuf2bufio2fb),
    .I  (CLKFB_IN));

  // bufio2fb instantiation
  BUFIO2FB #(.DIVIDE_BYPASS("TRUE")) clkfb_bufio2fb
   (.O(clkfb_in_buf_out),
    .I(clkfb_ibuf2bufio2fb));

  // Clocking primitive
  //------------------------------------
  // Instantiation of the PLL primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire [15:0] do_unused;
  wire        drdy_unused;
  wire        clkfbout;
  wire        clkfbout_buf;
  wire        clkout1_unused;
  wire        clkout2_unused;
  wire        clkout3_unused;
  wire        clkout4_unused;
  wire        clkout5_unused;

  PLL_BASE
  #(.BANDWIDTH              ("HIGH"),
    .CLK_FEEDBACK           ("CLKFBOUT"),
    .COMPENSATION           ("EXTERNAL"),
    .DIVCLK_DIVIDE          (1),
    .CLKFBOUT_MULT          (28),
    .CLKFBOUT_PHASE         (0.000),
    .CLKOUT0_DIVIDE         (14),
    .CLKOUT0_PHASE          (0.000),
    .CLKOUT0_DUTY_CYCLE     (0.500),
    .CLKIN_PERIOD           (30.000),
    .REF_JITTER             (0.010))
  pll_base_inst
    // Output clocks
   (.CLKFBOUT              (clkfbout),
    .CLKOUT0               (clkout0),
    .CLKOUT1               (clkout1_unused),
    .CLKOUT2               (clkout2_unused),
    .CLKOUT3               (clkout3_unused),
    .CLKOUT4               (clkout4_unused),
    .CLKOUT5               (clkout5_unused),
    // Status and control signals
    .LOCKED                (LOCKED),
    .RST                   (1'b0),
     // Input clock control
    .CLKFBIN               (clkfb_in_buf_out),
    .CLKIN                 (clkin1));


  // Output buffering
  //-----------------------------------
  wire clkfb_bufg_out;
  wire clkfb_bufg_out_n;
  wire clkfb_oddr_out;
  // Instantiate bufg on fbout
  BUFG clkfbout_bufg
   (.O  (clkfb_bufg_out),
    .I  (clkfbout));
  // Locally invert clkfb_bufg_out for use in ODDR2
  assign clkfb_bufg_out_n = ~clkfb_bufg_out;

  // Forward the feedback clock off-chip
  ODDR2 clkfbout_oddr
   (.Q  (clkfb_oddr_out),
    .C0 (clkfb_bufg_out),
    .C1 (clkfb_bufg_out_n),
    .CE (1'b1),
    .D0 (1'b1),
    .D1 (1'b0),
    .R  (1'b0),
    .S  (1'b0));

  assign CLKFB_OUT = clkfb_oddr_out;
  BUFG clkout1_buf
   (.O   (FSBCLK),
    .I   (clkout0));




endmodule
