<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
					twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt  (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG |  twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)> 
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)> 
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* |  (twPathRpt*, twRacePathRpt?) |  twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET | 
							   NETDELAY | 
							   NETSKEW | 
							   PATH |
							   DEFPERIOD |
							   UNCONSTPATH |
							   DEFPATH | 
							   PATH2SETUP |
							   UNCONSTPATH2SETUP | 
							   PATHCLASS | 
							   PATHDELAY | 
							   PERIOD |
							   FREQUENCY |
							   PATHBLOCK |
							   OFFSET |
							   OFFSETIN |
							   OFFSETINCLOCK | 
							   UNCONSTOFFSETINCLOCK |
							   OFFSETINDELAY |
							   OFFSETINMOD |
							   OFFSETOUT |
							   OFFSETOUTCLOCK |
							   UNCONSTOFFSETOUTCLOCK | 
							   OFFSETOUTDELAY |
							   OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED> 
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
					   twEndPtCnt?,
					   twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest,  (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
						twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED  fInputJit CDATA #IMPLIED
					  fDCMJit CDATA #IMPLIED
					  fPhaseErr CDATA #IMPLIED
					  sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit  EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED                      arrv1 CDATA #IMPLIED
		         arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup  EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED                      requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup  actualRollup CDATA #IMPLIED                      errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED                      itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)> 
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED  slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED  units (MHz | ns) "ns" slack CDATA #IMPLIED
					  best CDATA #IMPLIED requested CDATA #IMPLIED
					  errors CDATA #IMPLIED
					  score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)> 
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>       
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED  twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace  (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
WarpLC.pcf -ucf PLL.ucf

</twCmdLine><twDesign>WarpLC_map.ncd</twDesign><twDesignPath>WarpLC_map.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true"  dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3284 - This timing report was generated using estimated delay information.  For accurate numbers, please refer to the post Place and Route timing report.</twInfo><twInfo anchorID="6">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="7" twNameLen="15"><twSUH2ClkList anchorID="8" twDestWidth="8" twPhaseWidth="6"><twDest>CLKIN</twDest><twSUH2Clk ><twSrc>FSB_A&lt;2&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.357</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.515</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A&lt;3&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.438</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.483</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A&lt;4&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.226</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.369</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A&lt;5&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.134</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.184</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A&lt;6&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.218</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.413</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A&lt;7&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.126</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.249</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A&lt;8&gt;</twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">11.001</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-7.261</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="9" twDestWidth="10" twPhaseWidth="21"><twSrc>CLKIN</twSrc><twClk2Out  twOutPad = "CLKFB_OUT" twMinTime = "-0.086" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.063" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="cg/pll/clkfb_bufg_out" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "CLKFB_OUT" twMinTime = "-0.086" twMinCrnr="f" twMinEdge ="twFalling" twMaxTime = "-0.057" twMaxCrnr="t" twMaxEdge ="twFalling" twInternalClk="cg/pll/clkfb_bufg_out" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "CPUCLK" twMinTime = "-0.086" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.063" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "CPU_nSTERM" twMinTime = "2.355" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "3.670" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FPUCLK" twMinTime = "-0.086" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.063" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;0&gt;" twMinTime = "3.244" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.995" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;1&gt;" twMinTime = "3.390" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.126" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;2&gt;" twMinTime = "3.181" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "6.440" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;3&gt;" twMinTime = "3.333" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "6.008" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;4&gt;" twMinTime = "3.276" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.920" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;5&gt;" twMinTime = "2.948" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.841" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;6&gt;" twMinTime = "2.891" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.753" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;7&gt;" twMinTime = "2.709" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.937" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;8&gt;" twMinTime = "2.621" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.259" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;9&gt;" twMinTime = "2.945" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "5.550" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;10&gt;" twMinTime = "2.838" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.510" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;11&gt;" twMinTime = "3.028" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.669" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;12&gt;" twMinTime = "2.934" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.696" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;13&gt;" twMinTime = "3.334" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.745" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;14&gt;" twMinTime = "3.257" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.637" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;15&gt;" twMinTime = "3.434" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.498" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;16&gt;" twMinTime = "3.301" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.334" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;17&gt;" twMinTime = "3.623" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.352" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;18&gt;" twMinTime = "3.660" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.322" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;19&gt;" twMinTime = "3.571" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.202" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;20&gt;" twMinTime = "3.648" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.326" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;21&gt;" twMinTime = "3.786" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.433" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;22&gt;" twMinTime = "3.815" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.420" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;23&gt;" twMinTime = "3.623" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.313" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;24&gt;" twMinTime = "3.717" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.376" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;25&gt;" twMinTime = "3.918" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.790" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;26&gt;" twMinTime = "3.871" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.530" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;27&gt;" twMinTime = "3.717" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "5.307" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;28&gt;" twMinTime = "3.721" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "5.952" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;29&gt;" twMinTime = "4.158" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "6.358" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;30&gt;" twMinTime = "4.471" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "6.772" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "FSB_D&lt;31&gt;" twMinTime = "4.207" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "6.477" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "RAMCLK0" twMinTime = "-0.086" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.063" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out  twOutPad = "RAMCLK1" twMinTime = "-0.086" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.063" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="10" twDestWidth="5"><twDest>CLKIN</twDest><twClk2SU><twSrc>CLKIN</twSrc><twRiseRise>5.103</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="11" twSrcWidth="9" twDestWidth="10"><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>14.296</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>16.621</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>16.752</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>17.066</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>16.634</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>16.546</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>16.467</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>16.379</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>16.563</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>15.885</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>16.176</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>16.136</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>16.295</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>16.322</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>16.371</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>16.263</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>16.124</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>15.960</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>16.978</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>15.948</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>15.828</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>15.952</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>16.059</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>16.046</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>15.939</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>16.002</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>16.234</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>16.156</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>15.933</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>16.578</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>16.984</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>17.398</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;2&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>17.103</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>14.069</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>16.394</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>16.525</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>16.839</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>16.407</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>16.319</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>16.240</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>16.152</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>16.336</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>15.658</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>15.949</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>15.909</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>16.068</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>16.095</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>16.144</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>16.036</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>15.897</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>15.733</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>16.751</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>15.721</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>15.601</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>15.725</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>15.832</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>15.819</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>15.712</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>15.775</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>16.007</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>15.929</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>15.706</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>16.351</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>16.757</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>17.171</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;3&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>16.876</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>13.511</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>15.836</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>15.967</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>16.281</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>15.849</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>15.761</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>15.682</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>15.594</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>15.778</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>15.100</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>15.391</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>15.351</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>15.510</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>15.537</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>15.586</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>15.478</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>15.339</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>15.175</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>16.193</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>15.163</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>15.043</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>15.167</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>15.274</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>15.261</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>15.154</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>15.217</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>15.449</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>15.371</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>15.148</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>15.793</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>16.199</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>16.613</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;4&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>16.318</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>13.587</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>15.912</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>16.043</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>16.357</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>15.925</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>15.837</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>15.758</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>15.670</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>15.854</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>15.176</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>15.467</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>15.427</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>15.586</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>15.613</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>15.662</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>15.554</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>15.415</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>15.251</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>16.269</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>15.239</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>15.119</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>15.243</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>15.350</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>15.337</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>15.230</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>15.293</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>15.525</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>15.447</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>15.224</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>15.869</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>16.275</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>16.689</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;5&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>16.394</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>13.527</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>15.852</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>15.983</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>16.297</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>15.865</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>15.777</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>15.698</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>15.610</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>15.794</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>15.116</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>15.407</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;6&gt;</twSrc><tw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c>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>13.498</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>13.390</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>13.251</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>13.087</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>14.105</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>13.075</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>12.955</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>13.079</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>13.186</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>13.173</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>13.066</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>13.129</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>13.361</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>13.283</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>13.060</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>13.705</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>14.111</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>14.525</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;16&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>14.230</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>11.557</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>13.882</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>14.013</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>14.327</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>13.895</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>13.807</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>13.728</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>13.640</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>13.824</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>13.146</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>13.437</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>13.397</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>13.556</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>13.583</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>13.632</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>13.524</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>13.385</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>13.221</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>14.239</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>13.209</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>13.089</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>13.213</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>13.320</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>13.307</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>13.200</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>13.263</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>13.495</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>13.417</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;17&gt;</twSrc><twDest>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wDest><twDel>12.844</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>12.765</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>12.677</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>12.861</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>12.183</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>12.474</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>12.434</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>12.593</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>12.620</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>12.669</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>12.561</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>12.422</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>12.258</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>13.276</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>12.246</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>12.126</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>12.250</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>12.357</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>12.344</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>12.237</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>12.300</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>12.532</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>12.454</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>12.231</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>12.876</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>13.282</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>13.696</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;22&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>13.401</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>10.795</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>13.069</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>13.200</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>13.514</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>13.082</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>12.994</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>12.915</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>12.827</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>13.011</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>12.333</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>12.624</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>12.584</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>12.743</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>12.770</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>12.819</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>12.711</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>12.572</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>12.408</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>13.426</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>12.396</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>12.276</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>12.400</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>12.507</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>12.494</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>12.387</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>12.450</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>12.682</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>12.604</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>12.381</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>13.026</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>13.432</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>13.846</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;23&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>13.551</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>10.449</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>12.722</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>12.853</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>13.167</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>12.735</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>12.647</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>12.568</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>12.480</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>12.664</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>11.986</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>12.277</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>12.237</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>12.396</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>12.423</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>12.472</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>12.364</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>12.225</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>12.061</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>13.079</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>12.049</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>11.929</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>12.053</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>12.160</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>12.147</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>12.040</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>12.103</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>12.335</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>12.257</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>12.034</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>12.679</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>13.085</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>13.499</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;24&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>13.204</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>11.667</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>13.940</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>14.071</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>14.385</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>13.953</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>13.865</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>13.786</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>13.698</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>13.882</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>13.204</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>13.495</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>13.455</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>13.614</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>13.641</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>13.690</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>13.582</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>13.443</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>13.279</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>14.297</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>13.267</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>13.147</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>13.271</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>13.378</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>13.365</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>13.258</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>13.321</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>13.553</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>13.475</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>13.252</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>13.897</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>14.303</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>14.717</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;25&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>14.422</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>11.769</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>14.042</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>14.173</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>14.487</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>14.055</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>13.967</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>13.888</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>13.800</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>13.984</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>13.306</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>13.597</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>13.557</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>13.716</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>13.743</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>13.792</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>13.684</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>13.545</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>13.381</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>14.399</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>13.369</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>13.249</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>13.373</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>13.480</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>13.467</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>13.360</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>13.423</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>13.655</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>13.577</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>13.354</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>13.999</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>14.405</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>14.819</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;28&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>14.524</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>CPU_nSTERM</twDest><twDel>11.569</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;0&gt;</twDest><twDel>13.805</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;1&gt;</twDest><twDel>13.936</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;2&gt;</twDest><twDel>14.250</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;3&gt;</twDest><twDel>13.818</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;4&gt;</twDest><twDel>13.730</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;5&gt;</twDest><twDel>13.651</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;6&gt;</twDest><twDel>13.563</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;7&gt;</twDest><twDel>13.747</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;8&gt;</twDest><twDel>13.069</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;9&gt;</twDest><twDel>13.360</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;10&gt;</twDest><twDel>13.320</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;11&gt;</twDest><twDel>13.479</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;12&gt;</twDest><twDel>13.506</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;13&gt;</twDest><twDel>13.555</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;14&gt;</twDest><twDel>13.447</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;15&gt;</twDest><twDel>13.308</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;16&gt;</twDest><twDel>13.144</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;17&gt;</twDest><twDel>14.162</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;18&gt;</twDest><twDel>13.132</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;19&gt;</twDest><twDel>13.012</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;20&gt;</twDest><twDel>13.136</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;21&gt;</twDest><twDel>13.243</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;22&gt;</twDest><twDel>13.230</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;23&gt;</twDest><twDel>13.123</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;24&gt;</twDest><twDel>13.186</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;25&gt;</twDest><twDel>13.418</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;26&gt;</twDest><twDel>13.340</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;27&gt;</twDest><twDel>13.117</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;28&gt;</twDest><twDel>13.762</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;29&gt;</twDest><twDel>14.168</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;30&gt;</twDest><twDel>14.582</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A&lt;30&gt;</twSrc><twDest>FSB_D&lt;31&gt;</twDest><twDel>14.287</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Tue Nov 02 00:33:37 2021 </twTimestamp></twFoot><twClientInfo anchorID="12"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>

Peak Memory Usage: 164 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
