SET_FLAG DEBUG FALSE
SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx9
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package ftg256
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/
SET_PREFERENCE workingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name CLK
SET_PARAMETER Use_Freq_Synth true
SET_PARAMETER Use_Phase_Alignment true
SET_PARAMETER Use_Min_Power false
SET_PARAMETER Use_Dyn_Phase_Shift false
SET_PARAMETER Use_Dyn_Reconfig false
SET_PARAMETER Jitter_Sel No_Jitter
SET_PARAMETER Use_Spread_Spectrum false
SET_PARAMETER Use_Spread_Spectrum_1 false
SET_PARAMETER Prim_In_Freq 40
SET_PARAMETER In_Freq_Units Units_MHz
SET_PARAMETER In_Jitter_Units Units_UI
SET_PARAMETER Relative_Inclk REL_PRIMARY
SET_PARAMETER Secondary_In_Freq 100.000
SET_PARAMETER Jitter_Options PS
SET_PARAMETER Clkin1_UI_Jitter 250.000
SET_PARAMETER Clkin2_UI_Jitter 100.000
SET_PARAMETER Prim_In_Jitter 0.01
SET_PARAMETER Secondary_In_Jitter 0.004
SET_PARAMETER Clkin1_Jitter_Ps 250.0
SET_PARAMETER Clkin2_Jitter_Ps 40.0
SET_PARAMETER Clkout2_Used true
SET_PARAMETER Clkout3_Used true
SET_PARAMETER Clkout4_Used true
SET_PARAMETER Clkout5_Used true
SET_PARAMETER Clkout6_Used false
SET_PARAMETER Clkout7_Used false
SET_PARAMETER Num_Out_Clks 5
SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false
SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false
SET_PARAMETER primary_port CLKIN
SET_PARAMETER CLK_OUT1_port FSBCLK
SET_PARAMETER CLK_OUT2_port RAMCLK
SET_PARAMETER CLK_OUT3_port CPUCLK
SET_PARAMETER CLK_OUT4_port C80M
SET_PARAMETER CLK_OUT5_port C50M
SET_PARAMETER CLK_OUT6_port CLK_OUT6
SET_PARAMETER CLK_OUT7_port CLK_OUT7
SET_PARAMETER DADDR_port DADDR
SET_PARAMETER DCLK_port DCLK
SET_PARAMETER DRDY_port DRDY
SET_PARAMETER DWE_port DWE
SET_PARAMETER DIN_port DIN
SET_PARAMETER DOUT_port DOUT
SET_PARAMETER DEN_port DEN
SET_PARAMETER PSCLK_port PSCLK
SET_PARAMETER PSEN_port PSEN
SET_PARAMETER PSINCDEC_port PSINCDEC
SET_PARAMETER PSDONE_port PSDONE
SET_PARAMETER Clkout1_Requested_Out_Freq 66.667
SET_PARAMETER Clkout1_Requested_Phase 0.000
SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0
SET_PARAMETER Clkout2_Requested_Out_Freq 66.667
SET_PARAMETER Clkout2_Requested_Phase 0
SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0
SET_PARAMETER Clkout3_Requested_Out_Freq 66.667
SET_PARAMETER Clkout3_Requested_Phase -72
SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0
SET_PARAMETER Clkout4_Requested_Out_Freq 80
SET_PARAMETER Clkout4_Requested_Phase 0
SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0
SET_PARAMETER Clkout5_Requested_Out_Freq 50
SET_PARAMETER Clkout5_Requested_Phase 0.000
SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0
SET_PARAMETER Clkout6_Requested_Out_Freq 33.000
SET_PARAMETER Clkout6_Requested_Phase 0.000
SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0
SET_PARAMETER Clkout7_Requested_Out_Freq 33.000
SET_PARAMETER Clkout7_Requested_Phase 0.000
SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0
SET_PARAMETER Use_Max_I_Jitter false
SET_PARAMETER Use_Min_O_Jitter false
SET_PARAMETER Prim_Source Single_ended_clock_capable_pin
SET_PARAMETER Use_Inclk_Switchover false
SET_PARAMETER secondary_port CLK_IN2
SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin
SET_PARAMETER Clkout1_Drives BUFG
SET_PARAMETER Clkout2_Drives BUFG
SET_PARAMETER Clkout3_Drives BUFG
SET_PARAMETER Clkout4_Drives BUFG
SET_PARAMETER Clkout5_Drives BUFG
SET_PARAMETER Clkout6_Drives BUFG
SET_PARAMETER Clkout7_Drives BUFG
SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP
SET_PARAMETER Clkfb_In_Signaling SINGLE
SET_PARAMETER CLKFB_IN_port CLKFB_IN
SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P
SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N
SET_PARAMETER CLKFB_OUT_port CLKFB_OUT
SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P
SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N
SET_PARAMETER Platform nt
SET_PARAMETER Summary_Strings empty
SET_PARAMETER Use_Locked false
SET_PARAMETER calc_done DONE
SET_PARAMETER Use_Reset false
SET_PARAMETER Use_Power_Down false
SET_PARAMETER Use_Status false
SET_PARAMETER Use_Freeze false
SET_PARAMETER Use_Clk_Valid false
SET_PARAMETER Use_Inclk_Stopped false
SET_PARAMETER Use_Clkfb_Stopped false
SET_PARAMETER RESET_port RESET
SET_PARAMETER LOCKED_port LOCKED
SET_PARAMETER Power_Down_port POWER_DOWN
SET_PARAMETER CLK_VALID_port CLK_VALID
SET_PARAMETER STATUS_port STATUS
SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL
SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED
SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED
SET_PARAMETER Override_Mmcm false
SET_PARAMETER Mmcm_Notes None
SET_PARAMETER Mmcm_Divclk_Divide 1
SET_PARAMETER Mmcm_Bandwidth OPTIMIZED
SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000
SET_PARAMETER Mmcm_Clkfbout_Phase 0.000
SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkin1_Period 10.000
SET_PARAMETER Mmcm_Clkin2_Period 10.000
SET_PARAMETER Mmcm_Clkout4_Cascade false
SET_PARAMETER Mmcm_Clock_Hold false
SET_PARAMETER Mmcm_Compensation ZHOLD
SET_PARAMETER Mmcm_Ref_Jitter1 0.010
SET_PARAMETER Mmcm_Ref_Jitter2 0.010
SET_PARAMETER Mmcm_Startup_Wait false
SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000
SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout0_Phase 0.000
SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout1_Divide 1
SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout1_Phase 0.000
SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout2_Divide 1
SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout2_Phase 0.000
SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout3_Divide 1
SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout3_Phase 0.000
SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout4_Divide 1
SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout4_Phase 0.000
SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout5_Divide 1
SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout5_Phase 0.000
SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false
SET_PARAMETER Mmcm_Clkout6_Divide 1
SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500
SET_PARAMETER Mmcm_Clkout6_Phase 0.000
SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false
SET_PARAMETER Override_Dcm false
SET_PARAMETER Dcm_Notes None
SET_PARAMETER Dcm_Clkdv_Divide 2.0
SET_PARAMETER Dcm_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkfx_Multiply 2
SET_PARAMETER Dcm_Clkin_Divide_By_2 false
SET_PARAMETER Dcm_Clkin_Period 30.303
SET_PARAMETER Dcm_Clkout_Phase_Shift NONE
SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS
SET_PARAMETER Dcm_Phase_Shift 0
SET_PARAMETER Dcm_Clk_Feedback NONE
SET_PARAMETER Dcm_Startup_Wait false
SET_PARAMETER Dcm_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clk_Out3_Port CLKFX
SET_PARAMETER Dcm_Clk_Out4_Port CLKFX
SET_PARAMETER Dcm_Clk_Out5_Port CLKFX
SET_PARAMETER Dcm_Clk_Out6_Port CLK0
SET_PARAMETER Override_Dcm_Clkgen false
SET_PARAMETER Dcm_Clkgen_Notes None
SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 2
SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2
SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000
SET_PARAMETER Dcm_Clkgen_Startup_Wait false
SET_PARAMETER Dcm_Clkgen_Clkin_Period 30.303
SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE
SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX
SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX180
SET_PARAMETER Override_Pll false
SET_PARAMETER Pll_Notes None
SET_PARAMETER Pll_Bandwidth OPTIMIZED
SET_PARAMETER Pll_Clkfbout_Mult 20
SET_PARAMETER Pll_Clkfbout_Phase 0.000
SET_PARAMETER Pll_Clk_Feedback CLKFBOUT
SET_PARAMETER Pll_Divclk_Divide 1
SET_PARAMETER Pll_Clkin_Period 25.000
SET_PARAMETER Pll_Compensation EXTERNAL
SET_PARAMETER Pll_Ref_Jitter 0.010
SET_PARAMETER Pll_Clkout0_Divide 12
SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout0_Phase 0.000
SET_PARAMETER Pll_Clkout1_Divide 12
SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout1_Phase 0.000
SET_PARAMETER Pll_Clkout2_Divide 12
SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout2_Phase -71.250
SET_PARAMETER Pll_Clkout3_Divide 10
SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout3_Phase 0.000
SET_PARAMETER Pll_Clkout4_Divide 16
SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout4_Phase 0.000
SET_PARAMETER Pll_Clkout5_Divide 1
SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500
SET_PARAMETER Pll_Clkout5_Phase 0.000
SET_PARAMETER dcm_pll_cascade NONE
SET_PARAMETER clock_mgr_type MANUAL
SET_PARAMETER primtype_sel PLL_BASE
SET_PARAMETER primitive MMCM
SET_PARAMETER SS_Mode CENTER_HIGH
SET_PARAMETER SS_Mod_Freq 250
SET_SIM_PARAMETER c_clkout2_used 1
SET_SIM_PARAMETER c_clkout3_used 1
SET_SIM_PARAMETER c_clkout4_used 1
SET_SIM_PARAMETER c_clkout5_used 1
SET_SIM_PARAMETER c_clkout6_used 0
SET_SIM_PARAMETER c_clkout7_used 0
SET_SIM_PARAMETER c_use_clkout1_bar 0
SET_SIM_PARAMETER c_use_clkout2_bar 0
SET_SIM_PARAMETER c_use_clkout3_bar 0
SET_SIM_PARAMETER c_use_clkout4_bar 0
SET_SIM_PARAMETER c_component_name CLK
SET_SIM_PARAMETER c_platform nt
SET_SIM_PARAMETER c_use_freq_synth 1
SET_SIM_PARAMETER c_use_phase_alignment 1
SET_SIM_PARAMETER c_prim_in_jitter 0.01
SET_SIM_PARAMETER c_secondary_in_jitter 0.004
SET_SIM_PARAMETER c_jitter_sel No_Jitter
SET_SIM_PARAMETER c_use_min_power 0
SET_SIM_PARAMETER c_use_min_o_jitter 0
SET_SIM_PARAMETER c_use_max_i_jitter 0
SET_SIM_PARAMETER c_use_dyn_phase_shift 0
SET_SIM_PARAMETER c_use_inclk_switchover 0
SET_SIM_PARAMETER c_use_dyn_reconfig 0
SET_SIM_PARAMETER c_use_spread_spectrum 0
SET_SIM_PARAMETER c_use_spread_spectrum_1 0
SET_SIM_PARAMETER c_primtype_sel PLL_BASE
SET_SIM_PARAMETER c_use_clk_valid 0
SET_SIM_PARAMETER c_prim_in_freq 40
SET_SIM_PARAMETER c_in_freq_units Units_MHz
SET_SIM_PARAMETER c_secondary_in_freq 100.000
SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP
SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin
SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE
SET_SIM_PARAMETER c_use_reset 0
SET_SIM_PARAMETER c_use_locked 0
SET_SIM_PARAMETER c_use_inclk_stopped 0
SET_SIM_PARAMETER c_use_clkfb_stopped 0
SET_SIM_PARAMETER c_use_power_down 0
SET_SIM_PARAMETER c_use_status 0
SET_SIM_PARAMETER c_use_freeze 0
SET_SIM_PARAMETER c_num_out_clks 5
SET_SIM_PARAMETER c_clkout1_drives BUFG
SET_SIM_PARAMETER c_clkout2_drives BUFG
SET_SIM_PARAMETER c_clkout3_drives BUFG
SET_SIM_PARAMETER c_clkout4_drives BUFG
SET_SIM_PARAMETER c_clkout5_drives BUFG
SET_SIM_PARAMETER c_clkout6_drives BUFG
SET_SIM_PARAMETER c_clkout7_drives BUFG
SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock   Freq (MHz)    Input Jitter (UI)"
SET_SIM_PARAMETER c_inclk_sum_row1 __primary______________40_____________0.01
SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock 
SET_SIM_PARAMETER c_outclk_sum_row0a "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
SET_SIM_PARAMETER c_outclk_sum_row0b "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______255.979____194.528
SET_SIM_PARAMETER c_outclk_sum_row2 CLK_OUT2____66.667______0.000______50.0______255.979____194.528
SET_SIM_PARAMETER c_outclk_sum_row3 CLK_OUT3____66.667____-71.250______50.0______255.979____194.528
SET_SIM_PARAMETER c_outclk_sum_row4 CLK_OUT4____80.000______0.000______50.0______244.226____194.528
SET_SIM_PARAMETER c_outclk_sum_row5 CLK_OUT5____50.000______0.000______50.0______277.107____194.528
SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output
SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output 
SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667
SET_SIM_PARAMETER c_clkout2_requested_out_freq 66.667
SET_SIM_PARAMETER c_clkout3_requested_out_freq 66.667
SET_SIM_PARAMETER c_clkout4_requested_out_freq 80
SET_SIM_PARAMETER c_clkout5_requested_out_freq 50
SET_SIM_PARAMETER c_clkout6_requested_out_freq 33.000
SET_SIM_PARAMETER c_clkout7_requested_out_freq 33.000
SET_SIM_PARAMETER c_clkout1_requested_phase 0.000
SET_SIM_PARAMETER c_clkout2_requested_phase 0
SET_SIM_PARAMETER c_clkout3_requested_phase -72
SET_SIM_PARAMETER c_clkout4_requested_phase 0
SET_SIM_PARAMETER c_clkout5_requested_phase 0.000
SET_SIM_PARAMETER c_clkout6_requested_phase 0.000
SET_SIM_PARAMETER c_clkout7_requested_phase 0.000
SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout1_out_freq 66.667
SET_SIM_PARAMETER c_clkout2_out_freq 66.667
SET_SIM_PARAMETER c_clkout3_out_freq 66.667
SET_SIM_PARAMETER c_clkout4_out_freq 80.000
SET_SIM_PARAMETER c_clkout5_out_freq 50.000
SET_SIM_PARAMETER c_clkout6_out_freq N/A
SET_SIM_PARAMETER c_clkout7_out_freq N/A
SET_SIM_PARAMETER c_clkout1_phase 0.000
SET_SIM_PARAMETER c_clkout2_phase 0.000
SET_SIM_PARAMETER c_clkout3_phase -71.250
SET_SIM_PARAMETER c_clkout4_phase 0.000
SET_SIM_PARAMETER c_clkout5_phase 0.000
SET_SIM_PARAMETER c_clkout6_phase N/A
SET_SIM_PARAMETER c_clkout7_phase N/A
SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout2_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout3_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout4_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout5_duty_cycle 50.0
SET_SIM_PARAMETER c_clkout6_duty_cycle N/A
SET_SIM_PARAMETER c_clkout7_duty_cycle N/A
SET_SIM_PARAMETER c_mmcm_notes None
SET_SIM_PARAMETER c_mmcm_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000
SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000
SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000
SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE
SET_SIM_PARAMETER c_mmcm_clock_hold FALSE
SET_SIM_PARAMETER c_mmcm_compensation ZHOLD
SET_SIM_PARAMETER c_mmcm_divclk_divide 1
SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010
SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010
SET_SIM_PARAMETER c_mmcm_startup_wait FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000
SET_SIM_PARAMETER c_mmcm_clkout1_divide 1
SET_SIM_PARAMETER c_mmcm_clkout2_divide 1
SET_SIM_PARAMETER c_mmcm_clkout3_divide 1
SET_SIM_PARAMETER c_mmcm_clkout4_divide 1
SET_SIM_PARAMETER c_mmcm_clkout5_divide 1
SET_SIM_PARAMETER c_mmcm_clkout6_divide 1
SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500
SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000
SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE
SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE
SET_SIM_PARAMETER c_pll_notes None
SET_SIM_PARAMETER c_pll_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT
SET_SIM_PARAMETER c_pll_clkfbout_mult 20
SET_SIM_PARAMETER c_pll_clkin_period 25.000
SET_SIM_PARAMETER c_pll_compensation EXTERNAL
SET_SIM_PARAMETER c_pll_divclk_divide 1
SET_SIM_PARAMETER c_pll_ref_jitter 0.010
SET_SIM_PARAMETER c_pll_clkout0_divide 12
SET_SIM_PARAMETER c_pll_clkout1_divide 12
SET_SIM_PARAMETER c_pll_clkout2_divide 12
SET_SIM_PARAMETER c_pll_clkout3_divide 10
SET_SIM_PARAMETER c_pll_clkout4_divide 16
SET_SIM_PARAMETER c_pll_clkout5_divide 1
SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500
SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000
SET_SIM_PARAMETER c_pll_clkout0_phase 0.000
SET_SIM_PARAMETER c_pll_clkout1_phase 0.000
SET_SIM_PARAMETER c_pll_clkout2_phase -71.250
SET_SIM_PARAMETER c_pll_clkout3_phase 0.000
SET_SIM_PARAMETER c_pll_clkout4_phase 0.000
SET_SIM_PARAMETER c_pll_clkout5_phase 0.000
SET_SIM_PARAMETER c_dcm_notes None
SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000
SET_SIM_PARAMETER c_dcm_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkfx_multiply 2
SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE
SET_SIM_PARAMETER c_dcm_clkin_period 25.0
SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE
SET_SIM_PARAMETER c_dcm_clk_feedback NONE
SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1
SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS
SET_SIM_PARAMETER c_dcm_phase_shift 0
SET_SIM_PARAMETER c_dcm_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out3_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out4_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out5_port CLKFX
SET_SIM_PARAMETER c_dcm_clk_out6_port CLK0
SET_SIM_PARAMETER c_dcm_clkgen_notes None
SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 2
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 2
SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED
SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 25.0
SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000
SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE
SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE
SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port CLKFX
SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port CLKFX180
SET_SIM_PARAMETER c_clock_mgr_type MANUAL
SET_SIM_PARAMETER c_override_mmcm 0
SET_SIM_PARAMETER c_override_pll 0
SET_SIM_PARAMETER c_override_dcm 0
SET_SIM_PARAMETER c_override_dcm_clkgen 0
SET_SIM_PARAMETER c_dcm_pll_cascade NONE
SET_SIM_PARAMETER c_primary_port CLKIN
SET_SIM_PARAMETER c_secondary_port CLK_IN2
SET_SIM_PARAMETER c_clk_out1_port FSBCLK
SET_SIM_PARAMETER c_clk_out2_port RAMCLK
SET_SIM_PARAMETER c_clk_out3_port CPUCLK
SET_SIM_PARAMETER c_clk_out4_port C80M
SET_SIM_PARAMETER c_clk_out5_port C50M
SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6
SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7
SET_SIM_PARAMETER c_reset_port RESET
SET_SIM_PARAMETER c_locked_port LOCKED
SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN
SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P
SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N
SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT
SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P
SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N
SET_SIM_PARAMETER c_power_down_port POWER_DOWN
SET_SIM_PARAMETER c_daddr_port DADDR
SET_SIM_PARAMETER c_dclk_port DCLK
SET_SIM_PARAMETER c_drdy_port DRDY
SET_SIM_PARAMETER c_dwe_port DWE
SET_SIM_PARAMETER c_din_port DIN
SET_SIM_PARAMETER c_dout_port DOUT
SET_SIM_PARAMETER c_den_port DEN
SET_SIM_PARAMETER c_psclk_port PSCLK
SET_SIM_PARAMETER c_psen_port PSEN
SET_SIM_PARAMETER c_psincdec_port PSINCDEC
SET_SIM_PARAMETER c_psdone_port PSDONE
SET_SIM_PARAMETER c_clk_valid_port CLK_VALID
SET_SIM_PARAMETER c_status_port STATUS
SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL
SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED
SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED
SET_SIM_PARAMETER c_clkin1_jitter_ps 250.0
SET_SIM_PARAMETER c_clkin2_jitter_ps 40.0
SET_SIM_PARAMETER c_primitive MMCM
SET_SIM_PARAMETER c_ss_mode CENTER_HIGH
SET_SIM_PARAMETER c_ss_mod_period 4000
SET_CORE_NAME Clocking Wizard
SET_CORE_VERSION 3.6
SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6
SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl
SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf><pg065_clk_wiz.pdf>
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_readme.txt><clk_wiz_v3_6_readme.txt>
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\clk_wiz_v3_6_vinfo.html><clk_wiz_v3_6_vinfo.html>
