ClkGen Project Status (10/31/2021 - 15:38:40)
Project File: WarpLC.xise Parser Errors: No Errors
Module Name: ClkGen Implementation State: Placed and Routed
Target Device: xc6slx9-2ftg256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateSun Oct 31 14:40:54 2021
Physical Synthesis ReportOut of DateSun Oct 31 15:38:26 2021

Date Generated: 10/31/2021 - 15:38:40