Release 14.7 Map P.20131013 (nt)
Xilinx Map Application Log File for Design 'WarpLC'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high
-xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2
-ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf 
Target Device  : xc6slx9
Target Package : ftg256
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Tue Nov 02 00:33:09 2021

Running global optimization...
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 9 secs 
Total CPU  time at the beginning of Placer: 9 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:a4d8) REAL time: 10 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:a4d8) REAL time: 10 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:a4d8) REAL time: 10 secs 

Phase 4.2  Initial Placement for Architecture Specific Features
...
....
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:2d53f6ff) REAL time: 14 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:2d53f6ff) REAL time: 14 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:2d53f6ff) REAL time: 14 secs 

Phase 7.3  Local Placement Optimization
...
....
Phase 7.3  Local Placement Optimization (Checksum:615a33f3) REAL time: 19 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:615a33f3) REAL time: 19 secs 

Phase 9.8  Global Placement
...................................................
.......................
Phase 9.8  Global Placement (Checksum:b18754dd) REAL time: 19 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:b18754dd) REAL time: 19 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:58c2ff74) REAL time: 20 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:58c2ff74) REAL time: 20 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:58c2ff74) REAL time: 20 secs 

Total REAL time to Placer completion: 20 secs 
Total CPU  time to Placer completion: 20 secs 
Running physical synthesis...

Physical synthesis completed.
Running post-placement packing...
Writing output files...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                     1 out of  11,440    1%
    Number used as Flip Flops:                   1
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        105 out of   5,720    1%
    Number used as logic:                       25 out of   5,720    1%
      Number using O6 output only:               7
      Number using O5 output only:               1
      Number using O5 and O6:                   17
      Number used as ROM:                        0
    Number used as Memory:                      80 out of   1,440    5%
      Number used as Dual Port RAM:             80
        Number using O6 output only:            80
        Number using O5 output only:             0
        Number using O5 and O6:                  0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             0

Slice Logic Distribution:
  Number of occupied Slices:                    35 out of   1,430    2%
  Number of MUXCYs used:                         8 out of   2,860    1%
  Number of LUT Flip Flop pairs used:          106
    Number with an unused Flip Flop:           105 out of     106   99%
    Number with an unused LUT:                   1 out of     106    1%
    Number of fully used LUT-FF pairs:           0 out of     106    0%
    Number of unique control sets:               2
    Number of slice register sites lost
      to control set restrictions:               7 out of  11,440    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        66 out of     186   35%
    IOB Flip Flops:                              5

Specific Feature Utilization:
  Number of RAMB16BWERs:                         4 out of      32   12%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             1 out of      32    3%
    Number used as BUFIO2FBs:                    1
    Number used as BUFIO2FB_2CLKs:               0
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   5 out of     200    2%
    Number used as OLOGIC2s:                     5
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       2   50%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                3.54

Peak Memory Usage:  283 MB
Total REAL time to MAP completion:  22 secs 
Total CPU time to MAP completion (all processors):   22 secs 

Mapping completed.
See MAP report file "WarpLC_map.mrp" for details.
