/*******************************************************************************
*     This file is owned and controlled by Xilinx and must be used solely      *
*     for design, simulation, implementation and creation of design files      *
*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
*     devices or technologies is expressly prohibited and immediately          *
*     terminates your license.                                                 *
*                                                                              *
*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
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*     (c) Copyright 1995-2021 Xilinx, Inc.                                     *
*     All rights reserved.                                                     *
*******************************************************************************/

/*******************************************************************************
*     Generated from core with identifier: xilinx.com:ip:dist_mem_gen:7.2      *
*                                                                              *
*     Rev 1. The LogiCORE Xilinx Distributed Memory Generator creates area     *
*     and performance optimized ROM blocks, single and dual port               *
*     distributed memories, and SRL16-based memories for Xilinx FPGAs. The     *
*     core supersedes the previously released LogiCORE Distributed Memory      *
*     core. Use this core in all new designs for supported families            *
*     wherever a distributed memory is required.                               *
*******************************************************************************/

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
PrefetchTagRAM your_instance_name (
  .a(a), // input [6 : 0] a
  .d(d), // input [19 : 0] d
  .dpra(dpra), // input [6 : 0] dpra
  .clk(clk), // input clk
  .we(we), // input we
  .spo(spo), // output [19 : 0] spo
  .dpo(dpo) // output [19 : 0] dpo
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file PrefetchTagRAM.v when simulating
// the core, PrefetchTagRAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

