--------------------------------------------------------------------------------
Release 14.7 Trace  (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3
-timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o
WarpLC.twr WarpLC.pcf -ucf PLL.ucf

Design file:              WarpLC.ncd
Physical constraint file: WarpLC.pcf
Device,package,speed:     xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level:             verbose report
                          unconstrained path report, limited to 10000 items per endpoint, 3 endpoints per path report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLKIN
------------+------------+------------+------------+------------+------------------+--------+
            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
------------+------------+------------+------------+------------+------------------+--------+
FSB_A<2>    |   13.357(R)|      SLOW  |   -4.792(R)|      FAST  |FSBCLK            |   0.000|
FSB_A<3>    |   13.113(R)|      SLOW  |   -5.235(R)|      FAST  |FSBCLK            |   0.000|
FSB_A<4>    |   13.801(R)|      SLOW  |   -4.763(R)|      FAST  |FSBCLK            |   0.000|
FSB_A<5>    |   13.561(R)|      SLOW  |   -4.981(R)|      FAST  |FSBCLK            |   0.000|
FSB_A<6>    |   13.522(R)|      SLOW  |   -4.617(R)|      FAST  |FSBCLK            |   0.000|
FSB_A<7>    |   12.787(R)|      SLOW  |   -4.498(R)|      FAST  |FSBCLK            |   0.000|
FSB_A<8>    |   13.770(R)|      SLOW  |   -4.347(R)|      FAST  |FSBCLK            |   0.000|
------------+------------+------------+------------+------------+------------------+--------+

Clock CLKIN to Pad
------------+-----------------+------------+-----------------+------------+---------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                     | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s)    | Phase  |
------------+-----------------+------------+-----------------+------------+---------------------+--------+
CLKFB_OUT   |        -0.068(R)|      FAST  |        -0.091(R)|      SLOW  |cg/pll/clkfb_bufg_out|   0.000|
            |        -0.137(F)|      FAST  |        -0.151(F)|      SLOW  |cg/pll/clkfb_bufg_out|   0.000|
CPUCLK      |        -0.176(R)|      FAST  |        -0.184(R)|      SLOW  |FSBCLK               |   0.000|
CPU_nSTERM  |         6.973(R)|      SLOW  |         2.525(R)|      FAST  |FSBCLK               |   0.000|
FPUCLK      |        -0.082(R)|      FAST  |        -0.090(R)|      SLOW  |FSBCLK               |   0.000|
FSB_D<0>    |        10.716(R)|      SLOW  |         4.515(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<1>    |        10.617(R)|      SLOW  |         4.793(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<2>    |        10.803(R)|      SLOW  |         4.489(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<3>    |        10.655(R)|      SLOW  |         4.307(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<4>    |        11.229(R)|      SLOW  |         4.818(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<5>    |        11.167(R)|      SLOW  |         5.205(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<6>    |        10.791(R)|      SLOW  |         4.335(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<7>    |        10.656(R)|      SLOW  |         4.415(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<8>    |        10.494(R)|      SLOW  |         4.544(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<9>    |        10.245(R)|      SLOW  |         3.128(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<10>   |        10.530(R)|      SLOW  |         4.295(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<11>   |        10.150(R)|      SLOW  |         3.901(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<12>   |        10.166(R)|      SLOW  |         4.192(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<13>   |         9.710(R)|      SLOW  |         3.636(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<14>   |         9.683(R)|      SLOW  |         4.134(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<15>   |        10.040(R)|      SLOW  |         4.222(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<16>   |        10.111(R)|      SLOW  |         4.099(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<17>   |         9.393(R)|      SLOW  |         3.734(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<18>   |         9.323(R)|      SLOW  |         3.924(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<19>   |        10.459(R)|      SLOW  |         4.516(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<20>   |        10.580(R)|      SLOW  |         4.373(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<21>   |        10.834(R)|      SLOW  |         4.830(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<22>   |        10.370(R)|      SLOW  |         4.226(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<23>   |        10.133(R)|      SLOW  |         4.299(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<24>   |        10.129(R)|      SLOW  |         4.491(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<25>   |        10.251(R)|      SLOW  |         4.463(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<26>   |        10.102(R)|      SLOW  |         4.439(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<27>   |        10.337(R)|      SLOW  |         4.410(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<28>   |        10.065(R)|      SLOW  |         4.107(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<29>   |        10.537(R)|      SLOW  |         4.734(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<30>   |        10.639(R)|      SLOW  |         4.654(R)|      FAST  |FSBCLK               |   0.000|
FSB_D<31>   |        10.533(R)|      SLOW  |         4.185(R)|      FAST  |FSBCLK               |   0.000|
RAMCLK0     |        -0.132(R)|      FAST  |        -0.140(R)|      SLOW  |FSBCLK               |   0.000|
RAMCLK1     |        -0.171(R)|      FAST  |        -0.179(R)|      SLOW  |FSBCLK               |   0.000|
------------+-----------------+------------+-----------------+------------+---------------------+--------+

Clock to Setup on destination clock CLKIN
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLKIN          |    6.729|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
FSB_A<2>       |CPU_nSTERM     |   16.297|
FSB_A<2>       |FSB_D<0>       |   20.028|
FSB_A<2>       |FSB_D<1>       |   19.929|
FSB_A<2>       |FSB_D<2>       |   20.115|
FSB_A<2>       |FSB_D<3>       |   19.967|
FSB_A<2>       |FSB_D<4>       |   20.541|
FSB_A<2>       |FSB_D<5>       |   20.479|
FSB_A<2>       |FSB_D<6>       |   20.103|
FSB_A<2>       |FSB_D<7>       |   19.968|
FSB_A<2>       |FSB_D<8>       |   19.818|
FSB_A<2>       |FSB_D<9>       |   19.569|
FSB_A<2>       |FSB_D<10>      |   19.854|
FSB_A<2>       |FSB_D<11>      |   19.474|
FSB_A<2>       |FSB_D<12>      |   19.490|
FSB_A<2>       |FSB_D<13>      |   19.034|
FSB_A<2>       |FSB_D<14>      |   19.007|
FSB_A<2>       |FSB_D<15>      |   19.364|
FSB_A<2>       |FSB_D<16>      |   19.423|
FSB_A<2>       |FSB_D<17>      |   18.705|
FSB_A<2>       |FSB_D<18>      |   18.635|
FSB_A<2>       |FSB_D<19>      |   19.771|
FSB_A<2>       |FSB_D<20>      |   19.892|
FSB_A<2>       |FSB_D<21>      |   20.146|
FSB_A<2>       |FSB_D<22>      |   19.682|
FSB_A<2>       |FSB_D<23>      |   19.445|
FSB_A<2>       |FSB_D<24>      |   19.453|
FSB_A<2>       |FSB_D<25>      |   19.575|
FSB_A<2>       |FSB_D<26>      |   19.426|
FSB_A<2>       |FSB_D<27>      |   19.661|
FSB_A<2>       |FSB_D<28>      |   19.389|
FSB_A<2>       |FSB_D<29>      |   19.861|
FSB_A<2>       |FSB_D<30>      |   19.963|
FSB_A<2>       |FSB_D<31>      |   19.595|
FSB_A<3>       |CPU_nSTERM     |   16.266|
FSB_A<3>       |FSB_D<0>       |   19.997|
FSB_A<3>       |FSB_D<1>       |   19.898|
FSB_A<3>       |FSB_D<2>       |   20.084|
FSB_A<3>       |FSB_D<3>       |   19.936|
FSB_A<3>       |FSB_D<4>       |   20.510|
FSB_A<3>       |FSB_D<5>       |   20.448|
FSB_A<3>       |FSB_D<6>       |   20.072|
FSB_A<3>       |FSB_D<7>       |   19.937|
FSB_A<3>       |FSB_D<8>       |   19.787|
FSB_A<3>       |FSB_D<9>       |   19.538|
FSB_A<3>       |FSB_D<10>      |   19.823|
FSB_A<3>       |FSB_D<11>      |   19.443|
FSB_A<3>       |FSB_D<12>      |   19.459|
FSB_A<3>       |FSB_D<13>      |   19.003|
FSB_A<3>       |FSB_D<14>      |   18.976|
FSB_A<3>       |FSB_D<15>      |   19.333|
FSB_A<3>       |FSB_D<16>      |   19.392|
FSB_A<3>       |FSB_D<17>      |   18.674|
FSB_A<3>       |FSB_D<18>      |   18.604|
FSB_A<3>       |FSB_D<19>      |   19.740|
FSB_A<3>       |FSB_D<20>      |   19.861|
FSB_A<3>       |FSB_D<21>      |   20.115|
FSB_A<3>       |FSB_D<22>      |   19.651|
FSB_A<3>       |FSB_D<23>      |   19.414|
FSB_A<3>       |FSB_D<24>      |   19.422|
FSB_A<3>       |FSB_D<25>      |   19.544|
FSB_A<3>       |FSB_D<26>      |   19.395|
FSB_A<3>       |FSB_D<27>      |   19.630|
FSB_A<3>       |FSB_D<28>      |   19.358|
FSB_A<3>       |FSB_D<29>      |   19.830|
FSB_A<3>       |FSB_D<30>      |   19.932|
FSB_A<3>       |FSB_D<31>      |   19.564|
FSB_A<4>       |CPU_nSTERM     |   16.667|
FSB_A<4>       |FSB_D<0>       |   20.398|
FSB_A<4>       |FSB_D<1>       |   20.299|
FSB_A<4>       |FSB_D<2>       |   20.485|
FSB_A<4>       |FSB_D<3>       |   20.337|
FSB_A<4>       |FSB_D<4>       |   20.911|
FSB_A<4>       |FSB_D<5>       |   20.849|
FSB_A<4>       |FSB_D<6>       |   20.473|
FSB_A<4>       |FSB_D<7>       |   20.338|
FSB_A<4>       |FSB_D<8>       |   20.188|
FSB_A<4>       |FSB_D<9>       |   19.939|
FSB_A<4>       |FSB_D<10>      |   20.224|
FSB_A<4>       |FSB_D<11>      |   19.844|
FSB_A<4>       |FSB_D<12>      |   19.860|
FSB_A<4>       |FSB_D<13>      |   19.404|
FSB_A<4>       |FSB_D<14>      |   19.377|
FSB_A<4>       |FSB_D<15>      |   19.734|
FSB_A<4>       |FSB_D<16>      |   19.793|
FSB_A<4>       |FSB_D<17>      |   19.075|
FSB_A<4>       |FSB_D<18>      |   19.005|
FSB_A<4>       |FSB_D<19>      |   20.141|
FSB_A<4>       |FSB_D<20>      |   20.262|
FSB_A<4>       |FSB_D<21>      |   20.516|
FSB_A<4>       |FSB_D<22>      |   20.052|
FSB_A<4>       |FSB_D<23>      |   19.815|
FSB_A<4>       |FSB_D<24>      |   19.823|
FSB_A<4>       |FSB_D<25>      |   19.945|
FSB_A<4>       |FSB_D<26>      |   19.796|
FSB_A<4>       |FSB_D<27>      |   20.031|
FSB_A<4>       |FSB_D<28>      |   19.759|
FSB_A<4>       |FSB_D<29>      |   20.231|
FSB_A<4>       |FSB_D<30>      |   20.333|
FSB_A<4>       |FSB_D<31>      |   19.965|
FSB_A<5>       |CPU_nSTERM     |   16.372|
FSB_A<5>       |FSB_D<0>       |   20.103|
FSB_A<5>       |FSB_D<1>       |   20.004|
FSB_A<5>       |FSB_D<2>       |   20.190|
FSB_A<5>       |FSB_D<3>       |   20.042|
FSB_A<5>       |FSB_D<4>       |   20.616|
FSB_A<5>       |FSB_D<5>       |   20.554|
FSB_A<5>       |FSB_D<6>       |   20.178|
FSB_A<5>       |FSB_D<7>       |   20.043|
FSB_A<5>       |FSB_D<8>       |   19.893|
FSB_A<5>       |FSB_D<9>       |   19.644|
FSB_A<5>       |FSB_D<10>      |   19.929|
FSB_A<5>       |FSB_D<11>      |   19.549|
FSB_A<5>       |FSB_D<12>      |   19.565|
FSB_A<5>       |FSB_D<13>      |   19.109|
FSB_A<5>       |FSB_D<14>      |   19.082|
FSB_A<5>       |FSB_D<15>      |   19.439|
FSB_A<5>       |FSB_D<16>      |   19.498|
FSB_A<5>       |FSB_D<17>      |   18.780|
FSB_A<5>       |FSB_D<18>      |   18.710|
FSB_A<5>       |FSB_D<19>      |   19.846|
FSB_A<5>       |FSB_D<20>      |   19.967|
FSB_A<5>       |FSB_D<21>      |   20.221|
FSB_A<5>       |FSB_D<22>      |   19.757|
FSB_A<5>       |FSB_D<23>      |   19.520|
FSB_A<5>       |FSB_D<24>      |   19.528|
FSB_A<5>       |FSB_D<25>      |   19.650|
FSB_A<5>       |FSB_D<26>      |   19.501|
FSB_A<5>       |FSB_D<27>      |   19.736|
FSB_A<5>       |FSB_D<28>      |   19.464|
FSB_A<5>       |FSB_D<29>      |   19.936|
FSB_A<5>       |FSB_D<30>      |   20.038|
FSB_A<5>       |FSB_D<31>      |   19.670|
FSB_A<6>       |CPU_nSTERM     |   16.060|
FSB_A<6>       |FSB_D<0>       |   19.791|
FSB_A<6>       |FSB_D<1>       |   19.692|
FSB_A<6>       |FSB_D<2>       |   19.878|
FSB_A<6>       |FSB_D<3>       |   19.730|
FSB_A<6>       |FSB_D<4>       |   20.304|
FSB_A<6>       |FSB_D<5>       |   20.242|
FSB_A<6>       |FSB_D<6>       |   19.866|
FSB_A<6>       |FSB_D<7>       |   19.731|
FSB_A<6>       |FSB_D<8>       |   19.581|
FSB_A<6>       |FSB_D<9>       |   19.332|
FSB_A<6>       |FSB_D<10>      |   19.617|
FSB_A<6>       |FSB_D<11>      |   19.237|
FSB_A<6>       |FSB_D<12>      |   19.253|
FSB_A<6>       |FSB_D<13>      |   18.797|
FSB_A<6>       |FSB_D<14>      |   18.770|
FSB_A<6>       |FSB_D<15>      |   19.127|
FSB_A<6>       |FSB_D<16>      |   19.186|
FSB_A<6>       |FSB_D<17>      |   18.468|
FSB_A<6>       |FSB_D<18>      |   18.398|
FSB_A<6>       |FSB_D<19>      |   19.534|
FSB_A<6>       |FSB_D<20>      |   19.655|
FSB_A<6>       |FSB_D<21>      |   19.909|
FSB_A<6>       |FSB_D<22>      |   19.445|
FSB_A<6>       |FSB_D<23>      |   19.208|
FSB_A<6>       |FSB_D<24>      |   19.216|
FSB_A<6>       |FSB_D<25>      |   19.338|
FSB_A<6>       |FSB_D<26>      |   19.189|
FSB_A<6>       |FSB_D<27>      |   19.424|
FSB_A<6>       |FSB_D<28>      |   19.152|
FSB_A<6>       |FSB_D<29>      |   19.624|
FSB_A<6>       |FSB_D<30>      |   19.726|
FSB_A<6>       |FSB_D<31>      |   19.358|
FSB_A<7>       |CPU_nSTERM     |   15.475|
FSB_A<7>       |FSB_D<0>       |   19.206|
FSB_A<7>       |FSB_D<1>       |   19.107|
FSB_A<7>       |FSB_D<2>       |   19.293|
FSB_A<7>       |FSB_D<3>       |   19.145|
FSB_A<7>       |FSB_D<4>       |   19.719|
FSB_A<7>       |FSB_D<5>       |   19.657|
FSB_A<7>       |FSB_D<6>       |   19.281|
FSB_A<7>       |FSB_D<7>       |   19.146|
FSB_A<7>       |FSB_D<8>       |   18.996|
FSB_A<7>       |FSB_D<9>       |   18.747|
FSB_A<7>       |FSB_D<10>      |   19.032|
FSB_A<7>       |FSB_D<11>      |   18.652|
FSB_A<7>       |FSB_D<12>      |   18.668|
FSB_A<7>       |FSB_D<13>      |   18.212|
FSB_A<7>       |FSB_D<14>      |   18.185|
FSB_A<7>       |FSB_D<15>      |   18.542|
FSB_A<7>       |FSB_D<16>      |   18.601|
FSB_A<7>       |FSB_D<17>      |   17.883|
FSB_A<7>       |FSB_D<18>      |   17.813|
FSB_A<7>       |FSB_D<19>      |   18.949|
FSB_A<7>       |FSB_D<20>      |   19.070|
FSB_A<7>       |FSB_D<21>      |   19.324|
FSB_A<7>       |FSB_D<22>      |   18.860|
FSB_A<7>       |FSB_D<23>      |   18.623|
FSB_A<7>       |FSB_D<24>      |   18.631|
FSB_A<7>       |FSB_D<25>      |   18.753|
FSB_A<7>       |FSB_D<26>      |   18.604|
FSB_A<7>       |FSB_D<27>      |   18.839|
FSB_A<7>       |FSB_D<28>      |   18.567|
FSB_A<7>       |FSB_D<29>      |   19.039|
FSB_A<7>       |FSB_D<30>      |   19.141|
FSB_A<7>       |FSB_D<31>      |   18.773|
FSB_A<8>       |CPU_nSTERM     |   15.199|
FSB_A<8>       |FSB_D<0>       |   18.930|
FSB_A<8>       |FSB_D<1>       |   18.831|
FSB_A<8>       |FSB_D<2>       |   19.017|
FSB_A<8>       |FSB_D<3>       |   18.869|
FSB_A<8>       |FSB_D<4>       |   19.443|
FSB_A<8>       |FSB_D<5>       |   19.381|
FSB_A<8>       |FSB_D<6>       |   19.005|
FSB_A<8>       |FSB_D<7>       |   18.870|
FSB_A<8>       |FSB_D<8>       |   18.720|
FSB_A<8>       |FSB_D<9>       |   18.471|
FSB_A<8>       |FSB_D<10>      |   18.756|
FSB_A<8>       |FSB_D<11>      |   18.376|
FSB_A<8>       |FSB_D<12>      |   18.392|
FSB_A<8>       |FSB_D<13>      |   17.936|
FSB_A<8>       |FSB_D<14>      |   17.909|
FSB_A<8>       |FSB_D<15>      |   18.266|
FSB_A<8>       |FSB_D<16>      |   18.325|
FSB_A<8>       |FSB_D<17>      |   17.607|
FSB_A<8>       |FSB_D<18>      |   17.537|
FSB_A<8>       |FSB_D<19>      |   18.673|
FSB_A<8>       |FSB_D<20>      |   18.794|
FSB_A<8>       |FSB_D<21>      |   19.048|
FSB_A<8>       |FSB_D<22>      |   18.584|
FSB_A<8>       |FSB_D<23>      |   18.347|
FSB_A<8>       |FSB_D<24>      |   18.355|
FSB_A<8>       |FSB_D<25>      |   18.477|
FSB_A<8>       |FSB_D<26>      |   18.328|
FSB_A<8>       |FSB_D<27>      |   18.563|
FSB_A<8>       |FSB_D<28>      |   18.291|
FSB_A<8>       |FSB_D<29>      |   18.763|
FSB_A<8>       |FSB_D<30>      |   18.865|
FSB_A<8>       |FSB_D<31>      |   18.497|
FSB_A<9>       |CPU_nSTERM     |   13.588|
FSB_A<9>       |FSB_D<0>       |   17.319|
FSB_A<9>       |FSB_D<1>       |   17.220|
FSB_A<9>       |FSB_D<2>       |   17.406|
FSB_A<9>       |FSB_D<3>       |   17.258|
FSB_A<9>       |FSB_D<4>       |   17.832|
FSB_A<9>       |FSB_D<5>       |   17.770|
FSB_A<9>       |FSB_D<6>       |   17.394|
FSB_A<9>       |FSB_D<7>       |   17.259|
FSB_A<9>       |FSB_D<8>       |   17.109|
FSB_A<9>       |FSB_D<9>       |   16.860|
FSB_A<9>       |FSB_D<10>      |   17.145|
FSB_A<9>       |FSB_D<11>      |   16.765|
FSB_A<9>       |FSB_D<12>      |   16.781|
FSB_A<9>       |FSB_D<13>      |   16.325|
FSB_A<9>       |FSB_D<14>      |   16.298|
FSB_A<9>       |FSB_D<15>      |   16.655|
FSB_A<9>       |FSB_D<16>      |   16.714|
FSB_A<9>       |FSB_D<17>      |   15.996|
FSB_A<9>       |FSB_D<18>      |   15.926|
FSB_A<9>       |FSB_D<19>      |   17.062|
FSB_A<9>       |FSB_D<20>      |   17.183|
FSB_A<9>       |FSB_D<21>      |   17.437|
FSB_A<9>       |FSB_D<22>      |   16.973|
FSB_A<9>       |FSB_D<23>      |   16.736|
FSB_A<9>       |FSB_D<24>      |   16.744|
FSB_A<9>       |FSB_D<25>      |   16.866|
FSB_A<9>       |FSB_D<26>      |   16.717|
FSB_A<9>       |FSB_D<27>      |   16.952|
FSB_A<9>       |FSB_D<28>      |   16.680|
FSB_A<9>       |FSB_D<29>      |   17.152|
FSB_A<9>       |FSB_D<30>      |   17.254|
FSB_A<9>       |FSB_D<31>      |   16.886|
FSB_A<10>      |CPU_nSTERM     |   13.543|
FSB_A<10>      |FSB_D<0>       |   17.274|
FSB_A<10>      |FSB_D<1>       |   17.175|
FSB_A<10>      |FSB_D<2>       |   17.361|
FSB_A<10>      |FSB_D<3>       |   17.213|
FSB_A<10>      |FSB_D<4>       |   17.787|
FSB_A<10>      |FSB_D<5>       |   17.725|
FSB_A<10>      |FSB_D<6>       |   17.349|
FSB_A<10>      |FSB_D<7>       |   17.214|
FSB_A<10>      |FSB_D<8>       |   17.064|
FSB_A<10>      |FSB_D<9>       |   16.815|
FSB_A<10>      |FSB_D<10>      |   17.100|
FSB_A<10>      |FSB_D<11>      |   16.720|
FSB_A<10>      |FSB_D<12>      |   16.736|
FSB_A<10>      |FSB_D<13>      |   16.280|
FSB_A<10>      |FSB_D<14>      |   16.253|
FSB_A<10>      |FSB_D<15>      |   16.610|
FSB_A<10>      |FSB_D<16>      |   16.669|
FSB_A<10>      |FSB_D<17>      |   15.951|
FSB_A<10>      |FSB_D<18>      |   15.881|
FSB_A<10>      |FSB_D<19>      |   17.017|
FSB_A<10>      |FSB_D<20>      |   17.138|
FSB_A<10>      |FSB_D<21>      |   17.392|
FSB_A<10>      |FSB_D<22>      |   16.928|
FSB_A<10>      |FSB_D<23>      |   16.691|
FSB_A<10>      |FSB_D<24>      |   16.699|
FSB_A<10>      |FSB_D<25>      |   16.821|
FSB_A<10>      |FSB_D<26>      |   16.672|
FSB_A<10>      |FSB_D<27>      |   16.907|
FSB_A<10>      |FSB_D<28>      |   16.635|
FSB_A<10>      |FSB_D<29>      |   17.107|
FSB_A<10>      |FSB_D<30>      |   17.209|
FSB_A<10>      |FSB_D<31>      |   16.841|
FSB_A<11>      |CPU_nSTERM     |   13.041|
FSB_A<11>      |FSB_D<0>       |   16.772|
FSB_A<11>      |FSB_D<1>       |   16.673|
FSB_A<11>      |FSB_D<2>       |   16.859|
FSB_A<11>      |FSB_D<3>       |   16.711|
FSB_A<11>      |FSB_D<4>       |   17.285|
FSB_A<11>      |FSB_D<5>       |   17.223|
FSB_A<11>      |FSB_D<6>       |   16.847|
FSB_A<11>      |FSB_D<7>       |   16.712|
FSB_A<11>      |FSB_D<8>       |   16.562|
FSB_A<11>      |FSB_D<9>       |   16.313|
FSB_A<11>      |FSB_D<10>      |   16.598|
FSB_A<11>      |FSB_D<11>      |   16.218|
FSB_A<11>      |FSB_D<12>      |   16.234|
FSB_A<11>      |FSB_D<13>      |   15.778|
FSB_A<11>      |FSB_D<14>      |   15.751|
FSB_A<11>      |FSB_D<15>      |   16.108|
FSB_A<11>      |FSB_D<16>      |   16.167|
FSB_A<11>      |FSB_D<17>      |   15.449|
FSB_A<11>      |FSB_D<18>      |   15.379|
FSB_A<11>      |FSB_D<19>      |   16.515|
FSB_A<11>      |FSB_D<20>      |   16.636|
FSB_A<11>      |FSB_D<21>      |   16.890|
FSB_A<11>      |FSB_D<22>      |   16.426|
FSB_A<11>      |FSB_D<23>      |   16.189|
FSB_A<11>      |FSB_D<24>      |   16.197|
FSB_A<11>      |FSB_D<25>      |   16.319|
FSB_A<11>      |FSB_D<26>      |   16.170|
FSB_A<11>      |FSB_D<27>      |   16.405|
FSB_A<11>      |FSB_D<28>      |   16.133|
FSB_A<11>      |FSB_D<29>      |   16.605|
FSB_A<11>      |FSB_D<30>      |   16.707|
FSB_A<11>      |FSB_D<31>      |   16.339|
FSB_A<12>      |CPU_nSTERM     |   12.951|
FSB_A<12>      |FSB_D<0>       |   21.550|
FSB_A<12>      |FSB_D<1>       |   21.451|
FSB_A<12>      |FSB_D<2>       |   21.637|
FSB_A<12>      |FSB_D<3>       |   21.489|
FSB_A<12>      |FSB_D<4>       |   22.063|
FSB_A<12>      |FSB_D<5>       |   22.001|
FSB_A<12>      |FSB_D<6>       |   21.625|
FSB_A<12>      |FSB_D<7>       |   21.490|
FSB_A<12>      |FSB_D<8>       |   21.340|
FSB_A<12>      |FSB_D<9>       |   21.091|
FSB_A<12>      |FSB_D<10>      |   21.376|
FSB_A<12>      |FSB_D<11>      |   20.996|
FSB_A<12>      |FSB_D<12>      |   21.012|
FSB_A<12>      |FSB_D<13>      |   20.556|
FSB_A<12>      |FSB_D<14>      |   20.529|
FSB_A<12>      |FSB_D<15>      |   20.886|
FSB_A<12>      |FSB_D<16>      |   20.945|
FSB_A<12>      |FSB_D<17>      |   20.843|
FSB_A<12>      |FSB_D<18>      |   20.443|
FSB_A<12>      |FSB_D<19>      |   21.818|
FSB_A<12>      |FSB_D<20>      |   21.414|
FSB_A<12>      |FSB_D<21>      |   21.668|
FSB_A<12>      |FSB_D<22>      |   20.495|
FSB_A<12>      |FSB_D<23>      |   20.569|
FSB_A<12>      |FSB_D<24>      |   21.195|
FSB_A<12>      |FSB_D<25>      |   21.693|
FSB_A<12>      |FSB_D<26>      |   20.948|
FSB_A<12>      |FSB_D<27>      |   21.809|
FSB_A<12>      |FSB_D<28>      |   20.911|
FSB_A<12>      |FSB_D<29>      |   21.459|
FSB_A<12>      |FSB_D<30>      |   21.485|
FSB_A<12>      |FSB_D<31>      |   21.117|
FSB_A<13>      |CPU_nSTERM     |   13.243|
FSB_A<13>      |FSB_D<0>       |   21.353|
FSB_A<13>      |FSB_D<1>       |   21.254|
FSB_A<13>      |FSB_D<2>       |   21.440|
FSB_A<13>      |FSB_D<3>       |   21.292|
FSB_A<13>      |FSB_D<4>       |   21.866|
FSB_A<13>      |FSB_D<5>       |   21.804|
FSB_A<13>      |FSB_D<6>       |   21.428|
FSB_A<13>      |FSB_D<7>       |   21.293|
FSB_A<13>      |FSB_D<8>       |   21.143|
FSB_A<13>      |FSB_D<9>       |   20.894|
FSB_A<13>      |FSB_D<10>      |   21.179|
FSB_A<13>      |FSB_D<11>      |   20.799|
FSB_A<13>      |FSB_D<12>      |   20.815|
FSB_A<13>      |FSB_D<13>      |   20.359|
FSB_A<13>      |FSB_D<14>      |   20.332|
FSB_A<13>      |FSB_D<15>      |   20.689|
FSB_A<13>      |FSB_D<16>      |   20.748|
FSB_A<13>      |FSB_D<17>      |   20.646|
FSB_A<13>      |FSB_D<18>      |   20.539|
FSB_A<13>      |FSB_D<19>      |   21.914|
FSB_A<13>      |FSB_D<20>      |   21.384|
FSB_A<13>      |FSB_D<21>      |   21.756|
FSB_A<13>      |FSB_D<22>      |   20.298|
FSB_A<13>      |FSB_D<23>      |   20.372|
FSB_A<13>      |FSB_D<24>      |   21.291|
FSB_A<13>      |FSB_D<25>      |   21.789|
FSB_A<13>      |FSB_D<26>      |   20.751|
FSB_A<13>      |FSB_D<27>      |   21.905|
FSB_A<13>      |FSB_D<28>      |   20.714|
FSB_A<13>      |FSB_D<29>      |   21.555|
FSB_A<13>      |FSB_D<30>      |   21.288|
FSB_A<13>      |FSB_D<31>      |   20.930|
FSB_A<14>      |CPU_nSTERM     |   13.080|
FSB_A<14>      |FSB_D<0>       |   20.669|
FSB_A<14>      |FSB_D<1>       |   20.570|
FSB_A<14>      |FSB_D<2>       |   20.756|
FSB_A<14>      |FSB_D<3>       |   20.608|
FSB_A<14>      |FSB_D<4>       |   21.182|
FSB_A<14>      |FSB_D<5>       |   21.120|
FSB_A<14>      |FSB_D<6>       |   20.744|
FSB_A<14>      |FSB_D<7>       |   20.609|
FSB_A<14>      |FSB_D<8>       |   20.459|
FSB_A<14>      |FSB_D<9>       |   20.350|
FSB_A<14>      |FSB_D<10>      |   20.495|
FSB_A<14>      |FSB_D<11>      |   20.115|
FSB_A<14>      |FSB_D<12>      |   20.131|
FSB_A<14>      |FSB_D<13>      |   19.675|
FSB_A<14>      |FSB_D<14>      |   19.648|
FSB_A<14>      |FSB_D<15>      |   20.005|
FSB_A<14>      |FSB_D<16>      |   20.194|
FSB_A<14>      |FSB_D<17>      |   19.962|
FSB_A<14>      |FSB_D<18>      |   19.945|
FSB_A<14>      |FSB_D<19>      |   21.320|
FSB_A<14>      |FSB_D<20>      |   20.790|
FSB_A<14>      |FSB_D<21>      |   21.162|
FSB_A<14>      |FSB_D<22>      |   19.614|
FSB_A<14>      |FSB_D<23>      |   19.688|
FSB_A<14>      |FSB_D<24>      |   20.697|
FSB_A<14>      |FSB_D<25>      |   21.195|
FSB_A<14>      |FSB_D<26>      |   20.067|
FSB_A<14>      |FSB_D<27>      |   21.311|
FSB_A<14>      |FSB_D<28>      |   20.030|
FSB_A<14>      |FSB_D<29>      |   20.961|
FSB_A<14>      |FSB_D<30>      |   20.692|
FSB_A<14>      |FSB_D<31>      |   20.336|
FSB_A<15>      |CPU_nSTERM     |   12.967|
FSB_A<15>      |FSB_D<0>       |   21.997|
FSB_A<15>      |FSB_D<1>       |   21.898|
FSB_A<15>      |FSB_D<2>       |   22.084|
FSB_A<15>      |FSB_D<3>       |   21.936|
FSB_A<15>      |FSB_D<4>       |   22.510|
FSB_A<15>      |FSB_D<5>       |   22.448|
FSB_A<15>      |FSB_D<6>       |   22.072|
FSB_A<15>      |FSB_D<7>       |   21.937|
FSB_A<15>      |FSB_D<8>       |   21.787|
FSB_A<15>      |FSB_D<9>       |   21.538|
FSB_A<15>      |FSB_D<10>      |   21.823|
FSB_A<15>      |FSB_D<11>      |   21.443|
FSB_A<15>      |FSB_D<12>      |   21.459|
FSB_A<15>      |FSB_D<13>      |   21.003|
FSB_A<15>      |FSB_D<14>      |   20.976|
FSB_A<15>      |FSB_D<15>      |   21.333|
FSB_A<15>      |FSB_D<16>      |   21.392|
FSB_A<15>      |FSB_D<17>      |   21.290|
FSB_A<15>      |FSB_D<18>      |   20.609|
FSB_A<15>      |FSB_D<19>      |   21.984|
FSB_A<15>      |FSB_D<20>      |   21.861|
FSB_A<15>      |FSB_D<21>      |   22.115|
FSB_A<15>      |FSB_D<22>      |   20.942|
FSB_A<15>      |FSB_D<23>      |   21.016|
FSB_A<15>      |FSB_D<24>      |   21.422|
FSB_A<15>      |FSB_D<25>      |   21.859|
FSB_A<15>      |FSB_D<26>      |   21.395|
FSB_A<15>      |FSB_D<27>      |   21.975|
FSB_A<15>      |FSB_D<28>      |   21.358|
FSB_A<15>      |FSB_D<29>      |   21.800|
FSB_A<15>      |FSB_D<30>      |   21.932|
FSB_A<15>      |FSB_D<31>      |   21.564|
FSB_A<16>      |CPU_nSTERM     |   12.945|
FSB_A<16>      |FSB_D<0>       |   20.513|
FSB_A<16>      |FSB_D<1>       |   20.414|
FSB_A<16>      |FSB_D<2>       |   20.600|
FSB_A<16>      |FSB_D<3>       |   20.452|
FSB_A<16>      |FSB_D<4>       |   21.026|
FSB_A<16>      |FSB_D<5>       |   20.964|
FSB_A<16>      |FSB_D<6>       |   20.588|
FSB_A<16>      |FSB_D<7>       |   20.453|
FSB_A<16>      |FSB_D<8>       |   20.303|
FSB_A<16>      |FSB_D<9>       |   20.054|
FSB_A<16>      |FSB_D<10>      |   20.339|
FSB_A<16>      |FSB_D<11>      |   19.959|
FSB_A<16>      |FSB_D<12>      |   19.975|
FSB_A<16>      |FSB_D<13>      |   19.519|
FSB_A<16>      |FSB_D<14>      |   19.492|
FSB_A<16>      |FSB_D<15>      |   19.849|
FSB_A<16>      |FSB_D<16>      |   19.908|
FSB_A<16>      |FSB_D<17>      |   19.806|
FSB_A<16>      |FSB_D<18>      |   20.036|
FSB_A<16>      |FSB_D<19>      |   21.411|
FSB_A<16>      |FSB_D<20>      |   20.881|
FSB_A<16>      |FSB_D<21>      |   21.253|
FSB_A<16>      |FSB_D<22>      |   19.458|
FSB_A<16>      |FSB_D<23>      |   19.532|
FSB_A<16>      |FSB_D<24>      |   20.788|
FSB_A<16>      |FSB_D<25>      |   21.286|
FSB_A<16>      |FSB_D<26>      |   19.911|
FSB_A<16>      |FSB_D<27>      |   21.402|
FSB_A<16>      |FSB_D<28>      |   20.063|
FSB_A<16>      |FSB_D<29>      |   21.052|
FSB_A<16>      |FSB_D<30>      |   20.783|
FSB_A<16>      |FSB_D<31>      |   20.427|
FSB_A<17>      |CPU_nSTERM     |   13.017|
FSB_A<17>      |FSB_D<0>       |   21.353|
FSB_A<17>      |FSB_D<1>       |   21.254|
FSB_A<17>      |FSB_D<2>       |   21.440|
FSB_A<17>      |FSB_D<3>       |   21.292|
FSB_A<17>      |FSB_D<4>       |   21.866|
FSB_A<17>      |FSB_D<5>       |   21.804|
FSB_A<17>      |FSB_D<6>       |   21.428|
FSB_A<17>      |FSB_D<7>       |   21.293|
FSB_A<17>      |FSB_D<8>       |   21.143|
FSB_A<17>      |FSB_D<9>       |   20.894|
FSB_A<17>      |FSB_D<10>      |   21.179|
FSB_A<17>      |FSB_D<11>      |   20.799|
FSB_A<17>      |FSB_D<12>      |   20.815|
FSB_A<17>      |FSB_D<13>      |   20.359|
FSB_A<17>      |FSB_D<14>      |   20.332|
FSB_A<17>      |FSB_D<15>      |   20.689|
FSB_A<17>      |FSB_D<16>      |   20.748|
FSB_A<17>      |FSB_D<17>      |   20.646|
FSB_A<17>      |FSB_D<18>      |   20.703|
FSB_A<17>      |FSB_D<19>      |   22.078|
FSB_A<17>      |FSB_D<20>      |   21.548|
FSB_A<17>      |FSB_D<21>      |   21.920|
FSB_A<17>      |FSB_D<22>      |   20.298|
FSB_A<17>      |FSB_D<23>      |   20.372|
FSB_A<17>      |FSB_D<24>      |   21.455|
FSB_A<17>      |FSB_D<25>      |   21.953|
FSB_A<17>      |FSB_D<26>      |   20.751|
FSB_A<17>      |FSB_D<27>      |   22.069|
FSB_A<17>      |FSB_D<28>      |   20.730|
FSB_A<17>      |FSB_D<29>      |   21.719|
FSB_A<17>      |FSB_D<30>      |   21.450|
FSB_A<17>      |FSB_D<31>      |   21.094|
FSB_A<18>      |CPU_nSTERM     |   12.735|
FSB_A<18>      |FSB_D<0>       |   21.758|
FSB_A<18>      |FSB_D<1>       |   21.659|
FSB_A<18>      |FSB_D<2>       |   21.845|
FSB_A<18>      |FSB_D<3>       |   21.697|
FSB_A<18>      |FSB_D<4>       |   22.271|
FSB_A<18>      |FSB_D<5>       |   22.209|
FSB_A<18>      |FSB_D<6>       |   21.833|
FSB_A<18>      |FSB_D<7>       |   21.698|
FSB_A<18>      |FSB_D<8>       |   21.548|
FSB_A<18>      |FSB_D<9>       |   21.299|
FSB_A<18>      |FSB_D<10>      |   21.584|
FSB_A<18>      |FSB_D<11>      |   21.204|
FSB_A<18>      |FSB_D<12>      |   21.220|
FSB_A<18>      |FSB_D<13>      |   20.764|
FSB_A<18>      |FSB_D<14>      |   20.737|
FSB_A<18>      |FSB_D<15>      |   21.094|
FSB_A<18>      |FSB_D<16>      |   21.153|
FSB_A<18>      |FSB_D<17>      |   21.051|
FSB_A<18>      |FSB_D<18>      |   20.365|
FSB_A<18>      |FSB_D<19>      |   21.501|
FSB_A<18>      |FSB_D<20>      |   21.622|
FSB_A<18>      |FSB_D<21>      |   21.876|
FSB_A<18>      |FSB_D<22>      |   20.703|
FSB_A<18>      |FSB_D<23>      |   20.777|
FSB_A<18>      |FSB_D<24>      |   21.183|
FSB_A<18>      |FSB_D<25>      |   21.353|
FSB_A<18>      |FSB_D<26>      |   21.156|
FSB_A<18>      |FSB_D<27>      |   21.469|
FSB_A<18>      |FSB_D<28>      |   21.119|
FSB_A<18>      |FSB_D<29>      |   21.561|
FSB_A<18>      |FSB_D<30>      |   21.693|
FSB_A<18>      |FSB_D<31>      |   21.325|
FSB_A<19>      |CPU_nSTERM     |   12.673|
FSB_A<19>      |FSB_D<0>       |   19.929|
FSB_A<19>      |FSB_D<1>       |   19.830|
FSB_A<19>      |FSB_D<2>       |   20.016|
FSB_A<19>      |FSB_D<3>       |   19.868|
FSB_A<19>      |FSB_D<4>       |   20.442|
FSB_A<19>      |FSB_D<5>       |   20.380|
FSB_A<19>      |FSB_D<6>       |   20.004|
FSB_A<19>      |FSB_D<7>       |   19.869|
FSB_A<19>      |FSB_D<8>       |   19.719|
FSB_A<19>      |FSB_D<9>       |   19.487|
FSB_A<19>      |FSB_D<10>      |   19.755|
FSB_A<19>      |FSB_D<11>      |   19.375|
FSB_A<19>      |FSB_D<12>      |   19.391|
FSB_A<19>      |FSB_D<13>      |   18.935|
FSB_A<19>      |FSB_D<14>      |   18.908|
FSB_A<19>      |FSB_D<15>      |   19.265|
FSB_A<19>      |FSB_D<16>      |   19.331|
FSB_A<19>      |FSB_D<17>      |   19.222|
FSB_A<19>      |FSB_D<18>      |   19.542|
FSB_A<19>      |FSB_D<19>      |   20.917|
FSB_A<19>      |FSB_D<20>      |   20.387|
FSB_A<19>      |FSB_D<21>      |   20.759|
FSB_A<19>      |FSB_D<22>      |   18.874|
FSB_A<19>      |FSB_D<23>      |   18.948|
FSB_A<19>      |FSB_D<24>      |   20.294|
FSB_A<19>      |FSB_D<25>      |   20.792|
FSB_A<19>      |FSB_D<26>      |   19.327|
FSB_A<19>      |FSB_D<27>      |   20.908|
FSB_A<19>      |FSB_D<28>      |   19.569|
FSB_A<19>      |FSB_D<29>      |   20.558|
FSB_A<19>      |FSB_D<30>      |   20.289|
FSB_A<19>      |FSB_D<31>      |   19.933|
FSB_A<20>      |CPU_nSTERM     |   13.841|
FSB_A<20>      |FSB_D<0>       |   20.533|
FSB_A<20>      |FSB_D<1>       |   20.434|
FSB_A<20>      |FSB_D<2>       |   20.620|
FSB_A<20>      |FSB_D<3>       |   20.658|
FSB_A<20>      |FSB_D<4>       |   21.046|
FSB_A<20>      |FSB_D<5>       |   21.081|
FSB_A<20>      |FSB_D<6>       |   20.608|
FSB_A<20>      |FSB_D<7>       |   20.473|
FSB_A<20>      |FSB_D<8>       |   20.323|
FSB_A<20>      |FSB_D<9>       |   21.293|
FSB_A<20>      |FSB_D<10>      |   20.840|
FSB_A<20>      |FSB_D<11>      |   20.521|
FSB_A<20>      |FSB_D<12>      |   20.747|
FSB_A<20>      |FSB_D<13>      |   20.015|
FSB_A<20>      |FSB_D<14>      |   20.062|
FSB_A<20>      |FSB_D<15>      |   19.869|
FSB_A<20>      |FSB_D<16>      |   21.137|
FSB_A<20>      |FSB_D<17>      |   20.500|
FSB_A<20>      |FSB_D<18>      |   19.589|
FSB_A<20>      |FSB_D<19>      |   20.964|
FSB_A<20>      |FSB_D<20>      |   20.434|
FSB_A<20>      |FSB_D<21>      |   20.806|
FSB_A<20>      |FSB_D<22>      |   19.478|
FSB_A<20>      |FSB_D<23>      |   19.552|
FSB_A<20>      |FSB_D<24>      |   20.341|
FSB_A<20>      |FSB_D<25>      |   20.839|
FSB_A<20>      |FSB_D<26>      |   19.931|
FSB_A<20>      |FSB_D<27>      |   20.955|
FSB_A<20>      |FSB_D<28>      |   19.894|
FSB_A<20>      |FSB_D<29>      |   20.605|
FSB_A<20>      |FSB_D<30>      |   20.468|
FSB_A<20>      |FSB_D<31>      |   20.100|
FSB_A<21>      |CPU_nSTERM     |   13.532|
FSB_A<21>      |FSB_D<0>       |   20.434|
FSB_A<21>      |FSB_D<1>       |   19.450|
FSB_A<21>      |FSB_D<2>       |   19.876|
FSB_A<21>      |FSB_D<3>       |   20.679|
FSB_A<21>      |FSB_D<4>       |   20.276|
FSB_A<21>      |FSB_D<5>       |   21.102|
FSB_A<21>      |FSB_D<6>       |   20.152|
FSB_A<21>      |FSB_D<7>       |   19.489|
FSB_A<21>      |FSB_D<8>       |   19.860|
FSB_A<21>      |FSB_D<9>       |   21.314|
FSB_A<21>      |FSB_D<10>      |   20.861|
FSB_A<21>      |FSB_D<11>      |   20.542|
FSB_A<21>      |FSB_D<12>      |   20.768|
FSB_A<21>      |FSB_D<13>      |   20.036|
FSB_A<21>      |FSB_D<14>      |   20.083|
FSB_A<21>      |FSB_D<15>      |   19.783|
FSB_A<21>      |FSB_D<16>      |   21.158|
FSB_A<21>      |FSB_D<17>      |   20.521|
FSB_A<21>      |FSB_D<18>      |   20.068|
FSB_A<21>      |FSB_D<19>      |   21.443|
FSB_A<21>      |FSB_D<20>      |   20.913|
FSB_A<21>      |FSB_D<21>      |   21.285|
FSB_A<21>      |FSB_D<22>      |   18.494|
FSB_A<21>      |FSB_D<23>      |   18.568|
FSB_A<21>      |FSB_D<24>      |   20.820|
FSB_A<21>      |FSB_D<25>      |   21.318|
FSB_A<21>      |FSB_D<26>      |   18.947|
FSB_A<21>      |FSB_D<27>      |   21.434|
FSB_A<21>      |FSB_D<28>      |   20.095|
FSB_A<21>      |FSB_D<29>      |   21.084|
FSB_A<21>      |FSB_D<30>      |   20.815|
FSB_A<21>      |FSB_D<31>      |   20.459|
FSB_A<22>      |CPU_nSTERM     |   14.013|
FSB_A<22>      |FSB_D<0>       |   21.071|
FSB_A<22>      |FSB_D<1>       |   20.972|
FSB_A<22>      |FSB_D<2>       |   21.158|
FSB_A<22>      |FSB_D<3>       |   21.010|
FSB_A<22>      |FSB_D<4>       |   21.584|
FSB_A<22>      |FSB_D<5>       |   21.522|
FSB_A<22>      |FSB_D<6>       |   21.146|
FSB_A<22>      |FSB_D<7>       |   21.011|
FSB_A<22>      |FSB_D<8>       |   20.861|
FSB_A<22>      |FSB_D<9>       |   20.934|
FSB_A<22>      |FSB_D<10>      |   20.897|
FSB_A<22>      |FSB_D<11>      |   20.517|
FSB_A<22>      |FSB_D<12>      |   20.533|
FSB_A<22>      |FSB_D<13>      |   20.077|
FSB_A<22>      |FSB_D<14>      |   20.050|
FSB_A<22>      |FSB_D<15>      |   20.407|
FSB_A<22>      |FSB_D<16>      |   20.778|
FSB_A<22>      |FSB_D<17>      |   20.364|
FSB_A<22>      |FSB_D<18>      |   20.707|
FSB_A<22>      |FSB_D<19>      |   22.082|
FSB_A<22>      |FSB_D<20>      |   21.552|
FSB_A<22>      |FSB_D<21>      |   21.924|
FSB_A<22>      |FSB_D<22>      |   20.016|
FSB_A<22>      |FSB_D<23>      |   20.090|
FSB_A<22>      |FSB_D<24>      |   21.459|
FSB_A<22>      |FSB_D<25>      |   21.957|
FSB_A<22>      |FSB_D<26>      |   20.469|
FSB_A<22>      |FSB_D<27>      |   22.073|
FSB_A<22>      |FSB_D<28>      |   20.734|
FSB_A<22>      |FSB_D<29>      |   21.723|
FSB_A<22>      |FSB_D<30>      |   21.454|
FSB_A<22>      |FSB_D<31>      |   21.098|
FSB_A<23>      |CPU_nSTERM     |   13.811|
FSB_A<23>      |FSB_D<0>       |   20.689|
FSB_A<23>      |FSB_D<1>       |   20.590|
FSB_A<23>      |FSB_D<2>       |   20.776|
FSB_A<23>      |FSB_D<3>       |   20.628|
FSB_A<23>      |FSB_D<4>       |   21.202|
FSB_A<23>      |FSB_D<5>       |   21.140|
FSB_A<23>      |FSB_D<6>       |   20.764|
FSB_A<23>      |FSB_D<7>       |   20.629|
FSB_A<23>      |FSB_D<8>       |   20.479|
FSB_A<23>      |FSB_D<9>       |   21.117|
FSB_A<23>      |FSB_D<10>      |   20.664|
FSB_A<23>      |FSB_D<11>      |   20.345|
FSB_A<23>      |FSB_D<12>      |   20.571|
FSB_A<23>      |FSB_D<13>      |   19.839|
FSB_A<23>      |FSB_D<14>      |   19.886|
FSB_A<23>      |FSB_D<15>      |   20.025|
FSB_A<23>      |FSB_D<16>      |   20.961|
FSB_A<23>      |FSB_D<17>      |   20.324|
FSB_A<23>      |FSB_D<18>      |   19.630|
FSB_A<23>      |FSB_D<19>      |   21.005|
FSB_A<23>      |FSB_D<20>      |   20.553|
FSB_A<23>      |FSB_D<21>      |   20.847|
FSB_A<23>      |FSB_D<22>      |   19.634|
FSB_A<23>      |FSB_D<23>      |   19.708|
FSB_A<23>      |FSB_D<24>      |   20.382|
FSB_A<23>      |FSB_D<25>      |   20.880|
FSB_A<23>      |FSB_D<26>      |   20.087|
FSB_A<23>      |FSB_D<27>      |   20.996|
FSB_A<23>      |FSB_D<28>      |   20.050|
FSB_A<23>      |FSB_D<29>      |   20.646|
FSB_A<23>      |FSB_D<30>      |   20.624|
FSB_A<23>      |FSB_D<31>      |   20.256|
FSB_A<24>      |CPU_nSTERM     |   14.200|
FSB_A<24>      |FSB_D<0>       |   20.207|
FSB_A<24>      |FSB_D<1>       |   19.031|
FSB_A<24>      |FSB_D<2>       |   19.649|
FSB_A<24>      |FSB_D<3>       |   20.452|
FSB_A<24>      |FSB_D<4>       |   20.049|
FSB_A<24>      |FSB_D<5>       |   20.875|
FSB_A<24>      |FSB_D<6>       |   19.925|
FSB_A<24>      |FSB_D<7>       |   19.186|
FSB_A<24>      |FSB_D<8>       |   19.633|
FSB_A<24>      |FSB_D<9>       |   21.087|
FSB_A<24>      |FSB_D<10>      |   20.634|
FSB_A<24>      |FSB_D<11>      |   20.315|
FSB_A<24>      |FSB_D<12>      |   20.541|
FSB_A<24>      |FSB_D<13>      |   19.809|
FSB_A<24>      |FSB_D<14>      |   19.856|
FSB_A<24>      |FSB_D<15>      |   19.556|
FSB_A<24>      |FSB_D<16>      |   20.931|
FSB_A<24>      |FSB_D<17>      |   20.294|
FSB_A<24>      |FSB_D<18>      |   19.777|
FSB_A<24>      |FSB_D<19>      |   21.152|
FSB_A<24>      |FSB_D<20>      |   20.622|
FSB_A<24>      |FSB_D<21>      |   20.994|
FSB_A<24>      |FSB_D<22>      |   18.075|
FSB_A<24>      |FSB_D<23>      |   18.149|
FSB_A<24>      |FSB_D<24>      |   20.529|
FSB_A<24>      |FSB_D<25>      |   21.027|
FSB_A<24>      |FSB_D<26>      |   18.528|
FSB_A<24>      |FSB_D<27>      |   21.143|
FSB_A<24>      |FSB_D<28>      |   19.804|
FSB_A<24>      |FSB_D<29>      |   20.793|
FSB_A<24>      |FSB_D<30>      |   20.524|
FSB_A<24>      |FSB_D<31>      |   20.168|
FSB_A<25>      |CPU_nSTERM     |   14.246|
FSB_A<25>      |FSB_D<0>       |   20.894|
FSB_A<25>      |FSB_D<1>       |   20.055|
FSB_A<25>      |FSB_D<2>       |   20.336|
FSB_A<25>      |FSB_D<3>       |   21.139|
FSB_A<25>      |FSB_D<4>       |   20.736|
FSB_A<25>      |FSB_D<5>       |   21.562|
FSB_A<25>      |FSB_D<6>       |   20.612|
FSB_A<25>      |FSB_D<7>       |   20.094|
FSB_A<25>      |FSB_D<8>       |   20.320|
FSB_A<25>      |FSB_D<9>       |   21.774|
FSB_A<25>      |FSB_D<10>      |   21.321|
FSB_A<25>      |FSB_D<11>      |   21.002|
FSB_A<25>      |FSB_D<12>      |   21.228|
FSB_A<25>      |FSB_D<13>      |   20.496|
FSB_A<25>      |FSB_D<14>      |   20.543|
FSB_A<25>      |FSB_D<15>      |   20.243|
FSB_A<25>      |FSB_D<16>      |   21.618|
FSB_A<25>      |FSB_D<17>      |   20.981|
FSB_A<25>      |FSB_D<18>      |   19.868|
FSB_A<25>      |FSB_D<19>      |   20.827|
FSB_A<25>      |FSB_D<20>      |   20.465|
FSB_A<25>      |FSB_D<21>      |   20.613|
FSB_A<25>      |FSB_D<22>      |   19.099|
FSB_A<25>      |FSB_D<23>      |   19.173|
FSB_A<25>      |FSB_D<24>      |   20.421|
FSB_A<25>      |FSB_D<25>      |   21.057|
FSB_A<25>      |FSB_D<26>      |   19.552|
FSB_A<25>      |FSB_D<27>      |   20.818|
FSB_A<25>      |FSB_D<28>      |   19.895|
FSB_A<25>      |FSB_D<29>      |   20.607|
FSB_A<25>      |FSB_D<30>      |   20.801|
FSB_A<25>      |FSB_D<31>      |   20.343|
FSB_A<28>      |CPU_nSTERM     |   14.341|
FSB_A<28>      |FSB_D<0>       |   20.562|
FSB_A<28>      |FSB_D<1>       |   20.463|
FSB_A<28>      |FSB_D<2>       |   20.649|
FSB_A<28>      |FSB_D<3>       |   20.673|
FSB_A<28>      |FSB_D<4>       |   21.075|
FSB_A<28>      |FSB_D<5>       |   21.096|
FSB_A<28>      |FSB_D<6>       |   20.637|
FSB_A<28>      |FSB_D<7>       |   20.502|
FSB_A<28>      |FSB_D<8>       |   20.352|
FSB_A<28>      |FSB_D<9>       |   21.308|
FSB_A<28>      |FSB_D<10>      |   20.855|
FSB_A<28>      |FSB_D<11>      |   20.536|
FSB_A<28>      |FSB_D<12>      |   20.762|
FSB_A<28>      |FSB_D<13>      |   20.030|
FSB_A<28>      |FSB_D<14>      |   20.077|
FSB_A<28>      |FSB_D<15>      |   19.898|
FSB_A<28>      |FSB_D<16>      |   21.152|
FSB_A<28>      |FSB_D<17>      |   20.515|
FSB_A<28>      |FSB_D<18>      |   20.077|
FSB_A<28>      |FSB_D<19>      |   21.452|
FSB_A<28>      |FSB_D<20>      |   20.922|
FSB_A<28>      |FSB_D<21>      |   21.294|
FSB_A<28>      |FSB_D<22>      |   19.507|
FSB_A<28>      |FSB_D<23>      |   19.581|
FSB_A<28>      |FSB_D<24>      |   20.829|
FSB_A<28>      |FSB_D<25>      |   21.327|
FSB_A<28>      |FSB_D<26>      |   19.960|
FSB_A<28>      |FSB_D<27>      |   21.443|
FSB_A<28>      |FSB_D<28>      |   20.104|
FSB_A<28>      |FSB_D<29>      |   21.093|
FSB_A<28>      |FSB_D<30>      |   20.824|
FSB_A<28>      |FSB_D<31>      |   20.468|
FSB_A<30>      |CPU_nSTERM     |   14.246|
FSB_A<30>      |FSB_D<0>       |   20.986|
FSB_A<30>      |FSB_D<1>       |   20.420|
FSB_A<30>      |FSB_D<2>       |   20.606|
FSB_A<30>      |FSB_D<3>       |   21.231|
FSB_A<30>      |FSB_D<4>       |   21.032|
FSB_A<30>      |FSB_D<5>       |   21.654|
FSB_A<30>      |FSB_D<6>       |   20.704|
FSB_A<30>      |FSB_D<7>       |   20.459|
FSB_A<30>      |FSB_D<8>       |   20.412|
FSB_A<30>      |FSB_D<9>       |   21.866|
FSB_A<30>      |FSB_D<10>      |   21.413|
FSB_A<30>      |FSB_D<11>      |   21.094|
FSB_A<30>      |FSB_D<12>      |   21.320|
FSB_A<30>      |FSB_D<13>      |   20.588|
FSB_A<30>      |FSB_D<14>      |   20.635|
FSB_A<30>      |FSB_D<15>      |   20.335|
FSB_A<30>      |FSB_D<16>      |   21.710|
FSB_A<30>      |FSB_D<17>      |   21.073|
FSB_A<30>      |FSB_D<18>      |   19.960|
FSB_A<30>      |FSB_D<19>      |   21.158|
FSB_A<30>      |FSB_D<20>      |   20.628|
FSB_A<30>      |FSB_D<21>      |   21.000|
FSB_A<30>      |FSB_D<22>      |   19.464|
FSB_A<30>      |FSB_D<23>      |   19.538|
FSB_A<30>      |FSB_D<24>      |   20.535|
FSB_A<30>      |FSB_D<25>      |   21.149|
FSB_A<30>      |FSB_D<26>      |   19.917|
FSB_A<30>      |FSB_D<27>      |   21.149|
FSB_A<30>      |FSB_D<28>      |   19.987|
FSB_A<30>      |FSB_D<29>      |   20.799|
FSB_A<30>      |FSB_D<30>      |   20.893|
FSB_A<30>      |FSB_D<31>      |   20.435|
---------------+---------------+---------+



Table of Timegroups:
-------------------
TimeGroup cg_pll_clkout0:
Blocks
 cg/pll/clkout1_buf                                                                
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW   
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH  
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW   
 cg/CPUCLKr                                                                

Pins
 cg\/FPUCLK_inst.CK0                                                                
 cg\/FPUCLK_inst.CK1                                                                
 cg\/CPUCLK_inst.CK0                                                                
 cg\/CPUCLK_inst.CK1                                                                
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[3].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKA  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[3].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKB  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[2].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKA  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[2].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKB  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[1].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKA  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[1].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKB  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKA  
 prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKB  
 cg\/RAMCLK0_inst.CK0                                                                
 cg\/RAMCLK0_inst.CK1                                                                
 cg\/RAMCLK1_inst.CK0                                                                
 cg\/RAMCLK1_inst.CK1                                                                


TimeGroup cg_pll_clkfbout:
Blocks
 cg/pll/clkfbout_bufg  
Pins
 cg\/pll\/clkfbout_oddr.CK0  cg\/pll\/clkfbout_oddr.CK1  

TimeGroup FSB_A:
Blocks
 prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram     
 prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram     
 prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram     
 prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram     
 cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<1>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<1>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<1>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<2>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<2>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<2>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<3>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<3>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<3>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<4>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<4>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<4>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<5>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<5>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<5>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<6>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<6>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<6>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<7>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<7>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 cache/Way<7>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram  
 CPU_nSTERM                                                                
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW                                                      
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW                                                     
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH                                                    
 prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW                                                     
 FSB_D<10>                                                                
 FSB_D<11>                                                                
 FSB_D<0>                                                                
 FSB_D<12>                                                                
 FSB_D<20>                                                                
 FSB_D<1>                                                                
 FSB_D<13>                                                                
 FSB_D<21>                                                                
 FSB_D<2>                                                                
 FSB_D<14>                                                                
 FSB_D<22>                                                                
 FSB_D<30>                                                                
 FSB_D<3>                                                                
 FSB_D<15>                                                                
 FSB_D<23>                                                                
 FSB_D<31>                                                                
 FSB_D<4>                                                                
 FSB_D<16>                                                                
 FSB_D<24>                                                                
 FSB_D<5>                                                                
 FSB_D<17>                                                                
 FSB_D<25>                                                                
 FSB_D<6>                                                                
 FSB_D<18>                                                                
 FSB_D<26>                                                                
 FSB_D<7>                                                                
 FSB_D<19>                                                                
 FSB_D<27>                                                                
 FSB_D<8>                                                                
 FSB_D<28>                                                                
 FSB_D<9>                                                                
 FSB_D<29>                                                                


TimeGroup CPU_nSTERM:
Blocks
 CPU_nSTERM  

TimeGroup CLKIN:
Pins
 cg\/pll\/pll_base_inst\/PLL_ADV.CLKIN1     SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0.DIVCLK  


Analysis completed Tue Nov 02 00:29:20 2021 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 167 MB



