INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
WARNING:sim - A core named 'PrefetchTagRAM' already exists in the project.
   Output products for this core may be overwritten.
Resolving generics for 'PrefetchTagRAM'...
WARNING:sim - A core named 'PrefetchTagRAM' already exists in the project.
   Output products for this core may be overwritten.
Applying external generics to 'PrefetchTagRAM'...
Delivering associated files for 'PrefetchTagRAM'...
Delivering EJava files for 'PrefetchTagRAM'...
Generating implementation netlist for 'PrefetchTagRAM'...
INFO:sim - Pre-processing HDL files for 'PrefetchTagRAM'...
Running synthesis for 'PrefetchTagRAM'
Running ngcbuild...
Writing VEO instantiation template for 'PrefetchTagRAM'...
Writing Verilog behavioral simulation model for 'PrefetchTagRAM'...
WARNING:sim - Overwriting existing file
   C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM/
   doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation
Delivered 2 files into directory
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'PrefetchTagRAM'...
Generating metadata file...
Regenerating ISE project file for 'PrefetchTagRAM'...
Generating ISE project...
XCO file found: PrefetchTagRAM.xco
XMDF file found: PrefetchTagRAM_xmdf.tcl
Adding
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.asy
-view all -origin_type imported
Adding
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ngc
-view all -origin_type created
Checking file
"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ng
c" for project device match ...
File
"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ng
c" device information matches project device.
Adding
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.sym
-view all -origin_type imported
Adding
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.v
-view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM
   .v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.veo
-view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/PrefetchTagRAM"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'PrefetchTagRAM'.
