Release 14.7 par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

DOG-PC::  Tue Nov 02 00:29:08 2021

par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf 


Constraints file: WarpLC.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
   "WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2
INFO:Par:338 - 
   Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
   not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
   speed improvements are possible.  This can result in very long runtimes since the tools will continue improving the
   design even if the time specs can not be met. If you are looking for the best possible design speed available from a
   long but reasonable runtime use Extra Effort Level "n"ormal.  It will stop iterating on the design when the design
   speed improvements have shrunk to the point that the time specs are not expected to be met.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                     1 out of  11,440    1%
    Number used as Flip Flops:                   1
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        294 out of   5,720    5%
    Number used as logic:                      214 out of   5,720    3%
      Number using O6 output only:             183
      Number using O5 output only:               5
      Number using O5 and O6:                   26
      Number used as ROM:                        0
    Number used as Memory:                      80 out of   1,440    5%
      Number used as Dual Port RAM:             80
        Number using O6 output only:            80
        Number using O5 output only:             0
        Number using O5 and O6:                  0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             0

Slice Logic Distribution:
  Number of occupied Slices:                   113 out of   1,430    7%
  Number of MUXCYs used:                        72 out of   2,860    2%
  Number of LUT Flip Flop pairs used:          295
    Number with an unused Flip Flop:           294 out of     295   99%
    Number with an unused LUT:                   1 out of     295    1%
    Number of fully used LUT-FF pairs:           0 out of     295    0%
    Number of slice register sites lost
      to control set restrictions:               0 out of  11,440    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        66 out of     186   35%
    IOB Flip Flops:                              5

Specific Feature Utilization:
  Number of RAMB16BWERs:                        28 out of      32   87%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             1 out of      32    3%
    Number used as BUFIO2FBs:                    1
    Number used as BUFIO2FB_2CLKs:               0
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   5 out of     200    2%
    Number used as OLOGIC2s:                     5
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       2   50%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

PAR will use up to 4 processors
Starting Multi-threaded Router


Phase  1  : 5140 unrouted;      REAL time: 3 secs 

Phase  2  : 1769 unrouted;      REAL time: 3 secs 

Phase  3  : 1550 unrouted;      REAL time: 4 secs 

Phase  4  : 1550 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 4 secs 

Updating file: WarpLC.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 

Phase 11  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 secs 
Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion (all processors): 7 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cg/pll/clkfb_bufg_ou |              |      |      |            |             |
|                   t |  BUFGMUX_X2Y3| No   |    2 |  0.062     |  2.139      |
+---------------------+--------------+------+------+------------+-------------+
|              FSBCLK | BUFGMUX_X3Y13| No   |   37 |  0.652     |  2.088      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion (all processors): 8 secs 

Peak Memory Usage:  258 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file WarpLC.ncd



PAR done!
