Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
 
--> Reading design: WarpLC.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "WarpLC.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "WarpLC"
Output Format                      : NGC
Target Device                      : xc6slx9-2-ftg256

---- Source Options
Top Module Name                    : WarpLC
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : Inpad_To_Outpad
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work
Parsing module <PLL>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\L2WayRAM.v" into library work
Parsing module <L2WayRAM>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" into library work
Parsing module <L2CacheWay>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work
Parsing module <PrefetchTagRAM>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" into library work
Parsing module <PrefetchDataRAM>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work
Parsing module <SizeDecode>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" into library work
Parsing module <L2Prefetch>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2Cache.v" into library work
Parsing module <L2Cache>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\CS.v" into library work
Parsing module <CS>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work
Parsing module <ClkGen>.
Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work
Parsing module <WarpLC>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 92: Port LoMemCacheCS is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Port RDFixed7k5SEL is not connected to this instance

Elaborating module <WarpLC>.
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance

Elaborating module <ClkGen>.

Elaborating module <PLL>.

Elaborating module <IBUFG>.

Elaborating module <BUFIO2FB(DIVIDE_BYPASS="TRUE")>.

Elaborating module <PLL_BASE(BANDWIDTH="HIGH",CLK_FEEDBACK="CLKFBOUT",COMPENSATION="EXTERNAL",DIVCLK_DIVIDE=1,CLKFBOUT_MULT=28,CLKFBOUT_PHASE=0.0,CLKOUT0_DIVIDE=14,CLKOUT0_PHASE=0.0,CLKOUT0_DUTY_CYCLE=0.5,CLKIN_PERIOD=30.0,REF_JITTER=0.01)>.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used

Elaborating module <BUFG>.

Elaborating module <ODDR2>.

Elaborating module <ODDR2(DDR_ALIGNMENT="C0",INIT=1'b0,SRTYPE="ASYNC")>.

Elaborating module <CS>.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_SEL_RAM ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 95: Assignment to FSB_SEL_ROM ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 96: Assignment to FSB_VRAM ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 97: Assignment to FSB_SEL_Cache ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 98: Assignment to FSB_CA ignored, since the identifier is never used

Elaborating module <SizeDecode>.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 104: Assignment to FSB_B ignored, since the identifier is never used
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 49: Port doutb is not connected to this instance

Elaborating module <L2Prefetch>.

Elaborating module <PrefetchTagRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.

Elaborating module <PrefetchDataRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <PrefetchDataRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 116: Size mismatch in connection of port <WRA>. Formal port size is 26-bit while actual signal size is 28-bit.

Elaborating module <L2Cache>.

Elaborating module <L2CacheWay>.

Elaborating module <L2WayRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\L2WayRAM.v" Line 39: Empty module <L2WayRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 43: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 44: Size mismatch in connection of port <dina>. Formal port size is 47-bit while actual signal size is 50-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 45: Size mismatch in connection of port <douta>. Formal port size is 47-bit while actual signal size is 49-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 49: Size mismatch in connection of port <addrb>. Formal port size is 10-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 50: Size mismatch in connection of port <dinb>. Formal port size is 47-bit while actual signal size is 49-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Size mismatch in connection of port <doutb>. Formal port size is 47-bit while actual signal size is 49-bit.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Assignment to TSD ignored, since the identifier is never used
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 132: Size mismatch in connection of port <WRA>. Formal port size is 26-bit while actual signal size is 28-bit.
WARNING:HDLCompiler:634 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 125: Net <CLK> does not have a driver.
WARNING:HDLCompiler:552 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Input port RDFixed7k5SEL is not connected on this instance
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92. All outputs of instance <cs> of block <CS> are unconnected in block <WarpLC>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 101. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <WarpLC>.
    Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v".
    Set property "IOSTANDARD = LVCMOS33" for signal <FSB_A>.
    Set property "IOBDELAY = NONE" for signal <FSB_A>.
    Set property "IOSTANDARD = LVCMOS33" for signal <FSB_SIZ>.
    Set property "IOBDELAY = NONE" for signal <FSB_SIZ>.
    Set property "IOSTANDARD = LVCMOS33" for signal <FSB_D>.
    Set property "DRIVE = 8" for signal <FSB_D>.
    Set property "SLEW = SLOW" for signal <FSB_D>.
    Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nAS>.
    Set property "IOBDELAY = NONE" for signal <CPU_nAS>.
    Set property "IOSTANDARD = LVCMOS33" for signal <CPU_nSTERM>.
    Set property "DRIVE = 24" for signal <CPU_nSTERM>.
    Set property "SLEW = FAST" for signal <CPU_nSTERM>.
    Set property "IOSTANDARD = LVCMOS33" for signal <CPUCLK>.
    Set property "DRIVE = 24" for signal <CPUCLK>.
    Set property "SLEW = FAST" for signal <CPUCLK>.
    Set property "IOSTANDARD = LVCMOS33" for signal <FPUCLK>.
    Set property "DRIVE = 24" for signal <FPUCLK>.
    Set property "SLEW = FAST" for signal <FPUCLK>.
    Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK0>.
    Set property "DRIVE = 24" for signal <RAMCLK0>.
    Set property "SLEW = FAST" for signal <RAMCLK0>.
    Set property "IOSTANDARD = LVCMOS33" for signal <RAMCLK1>.
    Set property "DRIVE = 24" for signal <RAMCLK1>.
    Set property "SLEW = FAST" for signal <RAMCLK1>.
    Set property "IOSTANDARD = LVCMOS33" for signal <CLKIN>.
    Set property "IOBDELAY = NONE" for signal <CLKIN>.
    Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_IN>.
    Set property "IOBDELAY = NONE" for signal <CLKFB_IN>.
    Set property "IOSTANDARD = LVCMOS33" for signal <CLKFB_OUT>.
    Set property "DRIVE = 24" for signal <CLKFB_OUT>.
    Set property "SLEW = FAST" for signal <CLKFB_OUT>.
WARNING:Xst:2898 - Port 'RDFixed7k5SEL', unconnected in block instance 'prefetch', is tied to GND.
WARNING:Xst:647 - Input <CPU_nAS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <CA> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <RAMCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <ROMCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <VRAMCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <CacheCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <LoMemCacheCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 101: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <CLK> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   2 Multiplexer(s).
Unit <WarpLC> synthesized.

Synthesizing Unit <ClkGen>.
    Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <CPUCLKr>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ClkGen> synthesized.

Synthesizing Unit <PLL>.
    Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v".
    Summary:
	no macro.
Unit <PLL> synthesized.

Synthesizing Unit <L2Prefetch>.
    Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v".
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" line 49: Output port <doutb> of the instance <data> is unconnected or connected to loadless signal.
    Found 19-bit comparator equal for signal <RDTag[18]_RDATag[18]_equal_5_o> created at line 35
    Summary:
	inferred   1 Comparator(s).
Unit <L2Prefetch> synthesized.

Synthesizing Unit <L2Cache>.
    Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2Cache.v".
    Summary:
	inferred   8 Multiplexer(s).
Unit <L2Cache> synthesized.

Synthesizing Unit <L2CacheWay>.
    Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v".
WARNING:Xst:647 - Input <RDA<27:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRM> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <TS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ALL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" line 39: Output port <doutb> of the instance <way> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <L2CacheWay> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 1-bit register                                        : 1
# Comparators                                          : 1
 19-bit comparator equal                               : 1
# Multiplexers                                         : 10
 32-bit 2-to-1 multiplexer                             : 10

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <ipcore_dir/PrefetchTagRAM.ngc>.
Reading core <ipcore_dir/PrefetchDataRAM.ngc>.
Reading core <ipcore_dir/L2WayRAM.ngc>.
Loading core <PrefetchTagRAM> for timing and area information for instance <tag>.
Loading core <PrefetchDataRAM> for timing and area information for instance <data>.
Loading core <L2WayRAM> for timing and area information for instance <way>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1
# Comparators                                          : 1
 19-bit comparator equal                               : 1
# Multiplexers                                         : 10
 32-bit 2-to-1 multiplexer                             : 10

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:1901 - Instance pll_base_inst in unit pll_base_inst of type PLL_BASE has been replaced by PLL_ADV

Optimizing unit <WarpLC> ...

Optimizing unit <ClkGen> ...

Optimizing unit <PLL> ...

Optimizing unit <L2Cache> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 1.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : WarpLC.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 62
#      GND                         : 10
#      INV                         : 3
#      LUT1                        : 1
#      LUT2                        : 1
#      LUT3                        : 32
#      LUT6                        : 6
#      MUXCY                       : 8
#      VCC                         : 1
# FlipFlops/Latches                : 46
#      FD                          : 40
#      FDR                         : 1
#      ODDR2                       : 5
# RAMS                             : 48
#      RAM128X1D                   : 20
#      RAMB16BWER                  : 28
# Clock Buffers                    : 2
#      BUFG                        : 2
# IO Buffers                       : 66
#      IBUF                        : 26
#      IBUFG                       : 2
#      OBUF                        : 38
# Others                           : 2
#      BUFIO2FB                    : 1
#      PLL_ADV                     : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9ftg256-2 


Slice Logic Utilization: 
 Number of Slice Registers:              46  out of  11440     0%  
 Number of Slice LUTs:                  123  out of   5720     2%  
    Number used as Logic:                43  out of   5720     0%  
    Number used as Memory:               80  out of   1440     5%  
       Number used as RAM:               80

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    169
   Number with an unused Flip Flop:     123  out of    169    72%  
   Number with an unused LUT:            46  out of    169    27%  
   Number of fully used LUT-FF pairs:     0  out of    169     0%  
   Number of unique control sets:         2

IO Utilization: 
 Number of IOs:                          75
 Number of bonded IOBs:                  66  out of    186    35%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:               28  out of     32    87%  
    Number using Block RAM only:         28
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  
 Number of PLL_ADVs:                      1  out of      2    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)                                                                                                                     | Load  |
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------+
cg/pll/pll_base_inst/CLKOUT0       | BUFG                                                                                                                                      | 73    |
cg/pll/pll_base_inst/CLKFBOUT      | BUFG                                                                                                                                      | 2     |
CLK                                | NONE(cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram)| 24    |
-----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 6.137ns (Maximum Frequency: 162.941MHz)
   Minimum input arrival time before clock: 3.180ns
   Maximum output required time after clock: 6.838ns
   Maximum combinational path delay: 8.932ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'cg/pll/pll_base_inst/CLKOUT0'
  Clock period: 6.137ns (frequency: 162.941MHz)
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Delay:               3.069ns (Levels of Logic = 1)
  Source:            cg/CPUCLKr (FF)
  Destination:       cg/CPUCLK_inst (FF)
  Source Clock:      cg/pll/pll_base_inst/CLKOUT0 rising
  Destination Clock: cg/pll/pll_base_inst/CLKOUT0 falling

  Data Path: cg/CPUCLKr to cg/CPUCLK_inst
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              4   0.525   0.803  cg/CPUCLKr (cg/CPUCLKr)
     INV:I->O             30   0.255   1.486  prefetch/CPUCLKr_INV_17_o1_INV_0 (prefetch/CPUCLKr_INV_17_o)
     ODDR2:D1                  0.000          cg/CPUCLK_inst
    ----------------------------------------
    Total                      3.069ns (0.780ns logic, 2.289ns route)
                                       (25.4% logic, 74.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cg/pll/pll_base_inst/CLKOUT0'
  Total number of paths / destination ports: 28 / 28
-------------------------------------------------------------------------
Offset:              3.180ns (Levels of Logic = 2)
  Source:            FSB_A<8> (PAD)
  Destination:       prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
  Destination Clock: cg/pll/pll_base_inst/CLKOUT0 rising

  Data Path: FSB_A<8> to prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            28   1.328   1.452  FSB_A_8_IBUF (FSB_A_8_IBUF)
     begin scope: 'prefetch/data:addra<6>'
     RAMB16BWER:ADDRA9         0.400          U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
    ----------------------------------------
    Total                      3.180ns (1.728ns logic, 1.452ns route)
                                       (54.3% logic, 45.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 240 / 240
-------------------------------------------------------------------------
Offset:              3.180ns (Levels of Logic = 2)
  Source:            FSB_A<8> (PAD)
  Destination:       cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
  Destination Clock: CLK rising

  Data Path: FSB_A<8> to cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            28   1.328   1.452  FSB_A_8_IBUF (FSB_A_8_IBUF)
     begin scope: 'cache/Way<0>/way:addra<6>'
     RAMB16BWER:ADDRA10        0.400          U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
    ----------------------------------------
    Total                      3.180ns (1.728ns logic, 1.452ns route)
                                       (54.3% logic, 45.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cg/pll/pll_base_inst/CLKOUT0'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              6.838ns (Levels of Logic = 3)
  Source:            prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
  Destination:       FSB_D<31> (PAD)
  Source Clock:      cg/pll/pll_base_inst/CLKOUT0 rising

  Data Path: prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram to FSB_D<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB16BWER:CLKA->DOA7    1   2.100   0.910  U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (douta<31>)
     end scope: 'prefetch/data:douta<31>'
     LUT3:I0->O            1   0.235   0.681  Mmux_FSB_D251 (FSB_D_31_OBUF)
     OBUF:I->O                 2.912          FSB_D_31_OBUF (FSB_D<31>)
    ----------------------------------------
    Total                      6.838ns (5.247ns logic, 1.591ns route)
                                       (76.7% logic, 23.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 628 / 34
-------------------------------------------------------------------------
Delay:               8.932ns (Levels of Logic = 11)
  Source:            FSB_A<11> (PAD)
  Destination:       FSB_D<31> (PAD)

  Data Path: FSB_A<11> to FSB_D<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            25   1.328   1.631  FSB_A_11_IBUF (FSB_A_11_IBUF)
     LUT6:I3->O            1   0.235   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_lut<0>)
     MUXCY:S->O            1   0.215   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<0>)
     MUXCY:CI->O           1   0.023   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<1>)
     MUXCY:CI->O           1   0.023   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<2>)
     MUXCY:CI->O           1   0.023   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<3>)
     MUXCY:CI->O           1   0.023   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<4>)
     MUXCY:CI->O           1   0.023   0.000  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5> (prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<5>)
     MUXCY:CI->O          33   0.023   1.537  prefetch/Mcompar_RDTag[18]_RDATag[18]_equal_5_o_cy<6> (prefetch/RDTag[18]_RDATag[18]_equal_5_o)
     LUT3:I2->O            1   0.254   0.681  Mmux_FSB_D321 (FSB_D_9_OBUF)
     OBUF:I->O                 2.912          FSB_D_9_OBUF (FSB_D<9>)
    ----------------------------------------
    Total                      8.932ns (5.084ns logic, 3.849ns route)
                                       (56.9% logic, 43.1% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock CLK
----------------------------+---------+---------+---------+---------+
                            | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
cg/pll/pll_base_inst/CLKOUT0|    3.289|         |         |         |
----------------------------+---------+---------+---------+---------+

Clock to Setup on destination clock cg/pll/pll_base_inst/CLKOUT0
----------------------------+---------+---------+---------+---------+
                            | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock                |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------------------+---------+---------+---------+---------+
cg/pll/pll_base_inst/CLKOUT0|    3.289|         |    3.069|         |
----------------------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 6.14 secs
 
--> 

Total memory usage is 216628 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   40 (   0 filtered)
Number of infos    :   12 (   0 filtered)

