Warp-LC/fpga/L2Cache.v

49 lines
1.0 KiB
Coq
Raw Permalink Normal View History

2021-10-31 19:39:28 +00:00
module L2Cache(
2021-11-01 16:12:16 +00:00
input CLK,
input CPUCLKr,
input [27:2] RDA,
output [31:0] RDD,
output Match,
input [27:2] WRA,
input [31:0] WRD,
input [3:0] WRM,
input TS,
input WR,
input CLR,
input ALL);
/* Cache ways */
2021-11-02 04:38:46 +00:00
wire [255:0] WayRDD;
wire [7:0] WayRDMatch;
2021-11-01 16:12:16 +00:00
L2CacheWay Way[7:0] (
.CLK(CLK),
.CPUCLKr(CPUCLKr),
.RDA(RDA),
.RDD(WayRDD),
.RDMatch(WayRDMatch),
.WRA(WRA),
.WRD(WRD),
.WRM(WRM),
.TS(TS),
.WR(WR),
.CLR(CLR),
.ALL(ALL));
2021-10-31 19:39:28 +00:00
2021-11-02 04:38:46 +00:00
assign Match = WayRDMatch[0] || WayRDMatch[1] ||
WayRDMatch[2] || WayRDMatch[3] ||
WayRDMatch[4] || WayRDMatch[5] ||
WayRDMatch[6] || WayRDMatch[7];
2021-11-01 16:12:16 +00:00
2021-11-02 04:38:46 +00:00
assign RDD[31:0] = WayRDMatch[0] ? WayRDD[31:00] :
WayRDMatch[1] ? WayRDD[63:32] :
WayRDMatch[2] ? WayRDD[95:64] :
WayRDMatch[3] ? WayRDD[127:96] :
WayRDMatch[4] ? WayRDD[159:128] :
WayRDMatch[5] ? WayRDD[191:160] :
WayRDMatch[6] ? WayRDD[223:192] :
WayRDMatch[7] ? WayRDD[255:224] : 0;
2021-10-31 19:39:28 +00:00
endmodule