WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_SEL_RAM ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 95: Assignment to FSB_SEL_ROM ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 96: Assignment to FSB_VRAM ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 97: Assignment to FSB_SEL_Cache ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 98: Assignment to FSB_CA ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 104: Assignment to FSB_B ignored, since the identifier is never used
WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" Line 49: Port doutb is not connected to this instance
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box.
Elaborating module <PrefetchDataRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <PrefetchDataRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 116: Size mismatch in connection of port <WRA>. Formal port size is 26-bit while actual signal size is 28-bit.
Elaborating module <L2Cache>.
Elaborating module <L2CacheWay>.
Elaborating module <L2WayRAM>.
WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\L2WayRAM.v" Line 39: Empty module <L2WayRAM> remains a black box.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 43: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 44: Size mismatch in connection of port <dina>. Formal port size is 47-bit while actual signal size is 50-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 45: Size mismatch in connection of port <douta>. Formal port size is 47-bit while actual signal size is 49-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 49: Size mismatch in connection of port <addrb>. Formal port size is 10-bit while actual signal size is 12-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 50: Size mismatch in connection of port <dinb>. Formal port size is 47-bit while actual signal size is 49-bit.
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Size mismatch in connection of port <doutb>. Formal port size is 47-bit while actual signal size is 49-bit.
WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" Line 51: Assignment to TSD ignored, since the identifier is never used
WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 132: Size mismatch in connection of port <WRA>. Formal port size is 26-bit while actual signal size is 28-bit.
WARNING:HDLCompiler:634 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 125: Net <CLK> does not have a driver.
WARNING:HDLCompiler:552 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 108: Input port RDFixed7k5SEL is not connected on this instance
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92. All outputs of instance <cs> of block <CS> are unconnected in block <WarpLC>. Underlying logic will be removed.
WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 101. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed.
WARNING:Xst:647 - Input <CPU_nAS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <CA> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <RAMCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <ROMCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <VRAMCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <CacheCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 92: Output port <LoMemCacheCS> of the instance <cs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 101: Output port <B> of the instance <sd> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <CLK> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v".
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v".
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\Prefetch.v" line 49: Output port <doutb> of the instance <data> is unconnected or connected to loadless signal.
Found 19-bit comparator equal for signal <RDTag[18]_RDATag[18]_equal_5_o> created at line 35
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2Cache.v".
Summary:
inferred 8 Multiplexer(s).
Unit <L2Cache> synthesized.
Synthesizing Unit <L2CacheWay>.
Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v".
WARNING:Xst:647 - Input <RDA<27:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WRM> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <TS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ALL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\L2CacheWay.v" line 39: Output port <doutb> of the instance <way> is unconnected or connected to loadless signal.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Data Path: FSB_A<8> to prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
Data Path: FSB_A<8> to cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
Data Path: prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram to FSB_D<31>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)