diff --git a/.gitignore b/.gitignore index 6e3284d..a2a4867 100644 --- a/.gitignore +++ b/.gitignore @@ -15,15 +15,5 @@ _autosave-* *-save.kicad_pcb fp-info-cache -# Netlist files (exported from Eeschema) -*.net - -# Autorouter files (exported from Pcbnew) -*.dsn -*.ses - -# Exported BOM files -*.xml -*.csv *.DS_Store diff --git a/fpga/CLKGEN.v b/fpga/CLKGEN.v index b902839..b2a22e6 100644 --- a/fpga/CLKGEN.v +++ b/fpga/CLKGEN.v @@ -18,7 +18,7 @@ // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// -module CLKGEN( +module ClkGen( input CLKIN, input CLKFB_IN, output CLKFB_OUT, @@ -29,7 +29,7 @@ module CLKGEN( output RAMCLK0, output RAMCLK1); - CLK instance_name ( + PLL pll ( .CLKIN(CLKIN), .CLKFB_IN(CLKFB_IN), .CLKFB_OUT(CLKFB_OUT), diff --git a/fpga/ClkGen_summary.html b/fpga/ClkGen_summary.html new file mode 100644 index 0000000..563643a --- /dev/null +++ b/fpga/ClkGen_summary.html @@ -0,0 +1,82 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ClkGen Project Status (10/31/2021 - 15:38:40)
Project File:WarpLC.xiseParser Errors: No Errors
Module Name:ClkGenImplementation State:Placed and Routed
Target Device:xc6slx9-2ftg256
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + + + +
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateSun Oct 31 14:40:54 2021
Physical Synthesis ReportOut of DateSun Oct 31 15:38:26 2021
+ + +
Date Generated: 10/31/2021 - 15:38:40
+ \ No newline at end of file diff --git a/fpga/L2Cache.v b/fpga/L2Cache.v new file mode 100644 index 0000000..c39d3b8 --- /dev/null +++ b/fpga/L2Cache.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09:44:08 10/31/2021 +// Design Name: +// Module Name: L2Cache +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module L2Cache( + ); + + +endmodule diff --git a/fpga/PLL.ucf b/fpga/PLL.ucf index 5372472..7f5c518 100644 --- a/fpga/PLL.ucf +++ b/fpga/PLL.ucf @@ -1,39 +1,44 @@ +NET "CLKIN" TNM_NET = CLKIN; +#NET "FSB_A[31]" TNM_NET = FSB_A; +#NET "FSB_A[30]" TNM_NET = FSB_A; +#NET "FSB_A[29]" TNM_NET = FSB_A; +#NET "FSB_A[28]" TNM_NET = FSB_A; +NET "FSB_A[27]" TNM_NET = FSB_A; +NET "FSB_A[26]" TNM_NET = FSB_A; +NET "FSB_A[25]" TNM_NET = FSB_A; +NET "FSB_A[24]" TNM_NET = FSB_A; +NET "FSB_A[23]" TNM_NET = FSB_A; +NET "FSB_A[22]" TNM_NET = FSB_A; +NET "FSB_A[21]" TNM_NET = FSB_A; +NET "FSB_A[20]" TNM_NET = FSB_A; +NET "FSB_A[19]" TNM_NET = FSB_A; +NET "FSB_A[18]" TNM_NET = FSB_A; +NET "FSB_A[17]" TNM_NET = FSB_A; +NET "FSB_A[16]" TNM_NET = FSB_A; +NET "FSB_A[15]" TNM_NET = FSB_A; +NET "FSB_A[14]" TNM_NET = FSB_A; +NET "FSB_A[13]" TNM_NET = FSB_A; +NET "FSB_A[12]" TNM_NET = FSB_A; +NET "FSB_A[11]" TNM_NET = FSB_A; +NET "FSB_A[10]" TNM_NET = FSB_A; +NET "FSB_A[9]" TNM_NET = FSB_A; +NET "FSB_A[8]" TNM_NET = FSB_A; +NET "FSB_A[7]" TNM_NET = FSB_A; +NET "FSB_A[6]" TNM_NET = FSB_A; +NET "FSB_A[5]" TNM_NET = FSB_A; +NET "FSB_A[4]" TNM_NET = FSB_A; +NET "FSB_A[3]" TNM_NET = FSB_A; +NET "FSB_A[2]" TNM_NET = FSB_A; +#NET "FSB_A[1]" TNM_NET = FSB_A; +#NET "FSB_A[0]" TNM_NET = FSB_A; +NET "CPU_nSTERM" TNM_NET = CPU_nSTERM; + NET CLKFB_OUT FEEDBACK = 160ps NET CLKFB_IN; -NET CLKIN PERIOD = 30ns HIGH; +TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 ns HIGH 50%; -NET INt OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[31] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[30] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[29] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[28] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[27] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[26] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[25] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[24] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[23] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[22] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[21] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[20] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[19] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[18] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[17] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[16] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[15] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[14] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[13] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[12] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[11] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[10] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[9] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[8] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[7] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[6] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[5] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[4] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[3] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[2] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[1] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET FSB_A[0] OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET CPU_nAS OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; -NET OUTt OFFSET = OUT 5ns AFTER CLKIN; \ No newline at end of file +#NET "FSB_A[*]" OFFSET = IN 12ns VALID 12ns BEFORE CLKIN; +#NET "CPU_nAS" OFFSET = IN 15ns VALID 15ns BEFORE CLKIN; + +TIMESPEC TS_CPU_nSTERM_A = FROM "FSB_A" TO "CPU_nSTERM" 15ns; +#Created by Constraints Editor (xc6slx9-ftg256-2) - 2021/10/31 diff --git a/fpga/PrefetchBuf.v b/fpga/PrefetchBuf.v index b41fc18..7e90fee 100644 --- a/fpga/PrefetchBuf.v +++ b/fpga/PrefetchBuf.v @@ -1,41 +1,53 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 19:13:46 10/30/2021 -// Design Name: -// Module Name: PrefetchBuf -// Project Name: -// Target Devices: -// Tool versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// -module PrefetchBuf( - input [31:0] RDA, - output [31:0] RDD, - output Match, - input CLK, - input [31:0] WRA, - input [31:0] WRDin, - output [31:0] WRDout, - input [3:0] WE, - input TS); - - RAM128X1D Way0[55:0] ( - .DPO(WRDout), - .SPO(RDD), - .A(WRA[10:2]), - .D({A[WRDin[7:0]), - .DPRA(RDA), - .WCLK(CLK), - .WE(WE)); +module L2Prefetch( + input CLK, + input CPUCLKr, + input [28:2] RDA, + output [31:0] RDD, + output Match, + + input [28:2] WRA, + input [31:0] WRD, + input WR, + input [3:0] WRM, + input CLR); + + /* Read Address */ + wire [20:0] RDATag = RDA[28:7]; + wire [4:0] RDAIndex = RDA[6:2]; + + /* Write Address */ + wire [20:0] WRATag = WRA[28:7]; + wire [4:0] WRAIndex = WRA[6:2]; + + /* Way 0 Tag & Valid */ + wire [20:0] RDTag; + wire [20:0] TSTag; + wire RDValid; + wire TSValid; + wire RDMatch = RDValid && RDTag==RDATag; + wire TSMatch = TSValid && TSTag==RDATag; + PrefetchTagRAM Way0Tag ( + .clk(CLK), + .we(WR && (WRM[3:0]==4'b1111 || TSMatch)), + .a(WRA[8:2]), + .d({~CLR, WRATag[20:0]}), + .spo({TSValid, TSTag[20:0]}), + .dpra(RDA[8:2]), + .dpo({RDValid, RDTag[20:0]})); + + /* Way 0 Data */ + PrefetchDataRAM Way0Data ( + .clka(CLK), + .ena(WR && (WRM[3:0]==4'b1111 || TSMatch)), + .wea(WRM[3:0]), + .addra(WRAIndex[4:0]), + .dina(WRD[31:0]), + .clkb(CLK), + .enb(~CPUCLKr), + .addrb({2'b00, RDAIndex[4:0]}), + .doutb(RDD[31:0])); + + assign Match = RDMatch; + endmodule diff --git a/fpga/SizeDecode.v b/fpga/SizeDecode.v new file mode 100644 index 0000000..bccc5fa --- /dev/null +++ b/fpga/SizeDecode.v @@ -0,0 +1,16 @@ +module SizeDecode( + input [1:0] A, + input [1:0] SIZ, + output [3:0] B); + + assign B[3] = (A[1:0]==2'b00); + assign B[2] = (A[1:0]==2'b01) || + (A[1:0]==2'b00 && SIZ[1:0]!=2'b01); // Not 8-bit + assign B[1] = (A[1:0]==2'b10) || + (A[1:0]==2'b01 && SIZ[1:0]!=2'b01) || // Not 8-bit + (A[1:0]==2'b00 && SIZ[1:0]!=2'b01 && SIZ[1:0]!=2'b10); // Not 8-bit or 16-bit + assign B[0] = (A[1:0]==2'b11) || + (A[1:0]==2'b01 && SIZ[1:0]!=2'b01) || // Not 8-bit + (A[1:0]==2'b00 && SIZ[1:0]!=2'b01 && SIZ[1:0]!=2'b10) || + (A[1:0]==2'b00 && SIZ[1:0]==2'b00); // 32-bit +endmodule diff --git a/fpga/WarpLC.bld b/fpga/WarpLC.bld index bd2c5de..b79a9cd 100644 --- a/fpga/WarpLC.bld +++ b/fpga/WarpLC.bld @@ -1,20 +1,75 @@ -Release 14.7 ngdbuild P.20131013 (nt) +Release 14.7 ngdbuild P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle -ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 -WarpLC.ngc WarpLC.ngd +Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe +-intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p +xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd -Reading NGO file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ... +Reading NGO file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.ngc" ... +Loading design module "ipcore_dir/PrefetchTagRAM.ngc"... +Loading design module "ipcore_dir/PrefetchDataRAM.ngc"... Gathering constraint information from source properties... Done. Annotating constraints to design from ucf file "PLL.ucf" ... Resolving constraint associations... Checking Constraint Associations... -INFO:ConstraintSystem - The Period constraint - [PLL.ucf(3)], is specified using the Net Period method which is not - recommended. Please use the Timespec PERIOD method. +WARNING:ConstraintSystem:119 - Constraint : This + constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/CPU_nAS' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: + This constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: + This constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: This + constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_A<0>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: This + constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_A<1>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: + This constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_A<28>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: + This constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_A<29>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: + This constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_A<30>' because those design objects do not + contain or drive any instances of the correct type. + +WARNING:ConstraintSystem:119 - Constraint " IOBDELAY = NONE>: + This constraint cannot be distributed from the design objects matching 'NET: + UniqueName: /WarpLC/EXPANDED/FSB_A<31>' because those design objects do not + contain or drive any instances of the correct type. + +INFO:ConstraintSystem:178 - TNM 'CLKIN', used in period specification + 'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM + groups and period specifications were generated at the PLL_ADV output(s): + CLKFBOUT: + +INFO:ConstraintSystem:178 - TNM 'CLKIN', used in period specification + 'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM + groups and period specifications were generated at the PLL_ADV output(s): + CLKOUT0: Done... @@ -29,12 +84,12 @@ Partition Implementation Status NGDBUILD Design Results Summary: Number of errors: 0 - Number of warnings: 0 + Number of warnings: 9 -Total memory usage is 133904 kilobytes +Total memory usage is 163932 kilobytes Writing NGD file "WarpLC.ngd" ... -Total REAL time to NGDBUILD completion: 1 sec -Total CPU time to NGDBUILD completion: 1 sec +Total REAL time to NGDBUILD completion: 3 sec +Total CPU time to NGDBUILD completion: 3 sec Writing NGDBUILD log file "WarpLC.bld"... diff --git a/fpga/WarpLC.cmd_log b/fpga/WarpLC.cmd_log index 56dfdb6..982878b 100644 --- a/fpga/WarpLC.cmd_log +++ b/fpga/WarpLC.cmd_log @@ -501,3 +501,145 @@ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6s map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-3 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt off -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +xst -intstyle ise -ifn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.xst" -ofn "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.syr" +ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc PLL.ucf -p xc6slx9-ftg256-2 WarpLC.ngc WarpLC.ngd +map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high -xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 -ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +trce -intstyle ise -v 3 -timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf diff --git a/fpga/WarpLC.gise b/fpga/WarpLC.gise index 9606dec..04accc2 100644 --- a/fpga/WarpLC.gise +++ b/fpga/WarpLC.gise @@ -48,6 +48,7 @@ + @@ -72,45 +73,45 @@ - + - + - + - + + + + + - + - + - + - + - + - - - - @@ -120,48 +121,47 @@ + - + - + + - - + - - - + + + - + - - - + @@ -170,30 +170,31 @@ - - + - - + + - - - - + + + + + + diff --git a/fpga/WarpLC.ncd b/fpga/WarpLC.ncd index 1b83494..80ae536 100644 --- a/fpga/WarpLC.ncd +++ b/fpga/WarpLC.ncd @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 -###6700:XlxV32DM 3fff 1a14eNqVW/t32zay/ld09uSHZre2CYAvEduc8iWZNxKlkJRj955bHoqUUu06ttd2tu2J07/9Dl58iHDiOBUx82HmwwAYAiClvsIO+YwM+irb/ffwcLi98Sbo1Jy8wvQEb+nJh+vbbXVd3t49TunJ4ebx4fHP611ddfLk8LCbnNxN/qjth+s/pif7xw/Ysk/w5OT3ycn17YdDzZwnt/v95OT2evLb4cNvk5PHCZqc/PE4MSYn97sPh4fH3X3ZfLq7PtTVI4QgrO8n5qTXvgA/yvJwL8o7WV7XUr/9fSeh28n76v5uEZYfq7vTm7qR6unNh1a8q/cTAn25h8s161UbMAAf2eX22qaCFJS7e2RRbcQwWo+mQ1mfhwPTdlkG/kxI9SCkhp4Fm9l8ubksL/EV2fVUcoXInuvJCs+C8tK4wqRRQKuuFqt5EjLVNIeqNVTtoeoM1alDz9Z+hExLCbYSHCW4UrCQErASiBJMJSgeS/FYisdqeVSjtqEExWwrZlsx24rZVsy2YrYVs62YbcXsKGZHMTuK2VHMjmJ2FLOjmB3F7ChmRzG7itlVzK5idhWzq5hdxewqZlcxu4rZncKMrBeL0o8u2JSgmp7liySMuWIPNGeguQNt2tewMdAGnBgPNDLQzL5m9eoQcCKKCEWnBqHkFLELRiYl2EvS9abwZnlQ+v8kyDPeVNT60fiRWD9ibDLZ/JEQJlsG9Sd1dX//56T+rTrcTB4eq/vHw82Hye+Hx99kzcdPf0z+tqxvP95V9yUn/V+C/q/0M17s/vMJVgtc3pb1n/803vwNUx/BB8OHwMeEjwUf26Q+3E4gvbOon4GlzQqkSiRLLEsiS1OWlixtWTqydGU5fcNpJQ2WtFjpkhZLWixpsaTFkhZLWixpsaSV7kTSEiRgIgpTFJYobFE4onBFMX0D/c9Kg1+Rxa+GKKSGRUFEYYrCEoUtCkcUriimnEu4YcGFBReWoODCggsLLiy4sODCggsLLmFPBBdBHDP51eJXm18dfnX5dQrzCXMawIwHMOMBzHgAMx7AjAfQULBYhW8dUVxewZYXLOdZ6RdFlgSbIs6pCQhLiuDdlLIFl6+6DRVLq1xhEaJq7W0XYUa1SRZRWfjZPIZLeO4CkpdJOlsB3WVNg931w8Q4JbDvrXdc8xh5yS7IbgGxpre8uF8h4a3AQj/LruDu4cpsVuaZlM/9LEKNkJNVUCbQpV1PTYFm3+mrTQHAVACLTWF1oq3aFxsCZrazmSswvvRLUa5OspQBZvEcgsI0BJYQZiOE2QhhNkKYjdCGIQv9qLxI4vflRZzlySq1KO8T1MaEhkkKwlsQ3hrsgkyDXZ+iCGZskczTZZwWXmh4PKbiah17UOXlWZImRbl65xkgM5jJfn6Vhk9PJtJQpKs0fhGJ4IBYFm9NdjH4FVZ5uM6CJHWFAFRSgqGeSgnAXSeWKxhx4TiP0/Jw8/B4Fq43oHIZEU3NPap0aHlX1f+Gm/YrlfiZyvuHx7vbR4y+UomgCxelcRTqrBeqO6jJ/CUbmOerEFfwsIpdqpt6V95UH3dn9fW/99ty+2n/obz99Ij3LzaVQ/Ey8sMt3m9x803TA9ji1t56kf0HXH3b7oZFwXuIv2XMjJwXGPGReJnlbdPcY+PrlocbhM1vmrBGj3JoZAYtGt8aO7ARXF+b8Lvr63JbPexEnVxuSPO9HuVyUaaw7kTJBXjywJLUFoXIdbhJ2e0NKyfciysCt/FquUyKIo5gald5AQt9sIjBAgzBkd8QW1nyu9uRyqFWQpkouLzxczRVUv8Ik0YlKW9h8X6+Do41aPe1+utPj3Vbz9qE/HoH7WaxD+GDcgkBX7EFDpqBQ1S7K1VC5dtS3cmw4+wG2iyYSh22D8mhdgilyoFWNPyMuBhol4hCMBHsDRHcARHsDRHsDRHsDZFNaJQY7ILYBbMLsamYLZNGfIuO3sEH9tV4NltlRbmIL+KFRWf+Io9tOpMTMusmBMA8AKWRpVwtXCqOpcabqZRQT0SdiDuRdKLZiVYn2p3odKLbidM3qt2uBdy1i3to1y7u2sVdu7hrF3ft4q5d3LWLu3Y7WjhEbmnvbN7iqDUmrWS2ktVKdis5reS20vRNLaTS4NnYSA0dqWio4qFKhqo5VK2hanMVDhgDvbx/bC2cIwtnZOEeWbgji+mRxVRZqP4Oe4SH/cVHtcP+4mF/8bC/eNhfbA9VZ6i6Q1WEqWIcNkuGMRI0sCUDzRxo1kCzB5oz0NyBNpUNzherwF+UfBEx4Fg50NUZRwtjPUyGnGg/VE+NY+CYHil6mmCaGPBJCXweXXbhUYO0Cs7Y6XoqJHawrrgoztQOl+GcDPtHksdFuYyXQZyV/PmjhBNjlKTzM/HW5yyBTeU8iTP27HAFx9P5KlylOSSGSVlV+5BSrtlhOS/g6Fqus9W6zKEinUMeMjNJWrIzK6xtz5HCqjus4vY2B5O0iLMUhmG9KDM/ncdGw/F0FcXCTjhn8SzO4hSe/dkZ3qaLlR/FkUPZI8SZj5VgcsE+85ESsBKIElobSwk2rPxLf12Gy2iRpHD8XhfwgJBXHFyuos0ibrhcJMs4L/zlestV+SQBztUdHARf+pYAT19oCpvDi2nRy03xy03Jy03Nl5taLze1X27qvNzUfbnp9IXTBQchNrXVS22R8R3E6Dts8XfYku+wNb/D1voOW/s7bJ3vsHW/w3YKh5LUgEX/NLRgSRAKPo2Y4tA0Lt6vsreIrjBdwZFxBUfGVQhLgjyGnvHnecDfAb4pTHaBlZtdT2E9nnKJHwsruj7FBiIIPlO6JrDq+WEcwXKqZLX22HTth2/jiFD25oNds+PlCVl0HeVyfZ/DgVwux3DY1+JsDWVMbR1vkL2V2PfATe7P4wH1RRhqqXs4pz72YU0v5xnacjxawRYiHgvKTbrJ46hcJ2kumoYRLjMYJaCqW4Ct/pXQ5lGZRMJ0HS3VugtbA0eStPTzPJmnJSzKMgwGxpewb8EuIfYRQczfAPUH5SIOefSoq2bNsdcvfZd+Z5WL1asWEZVsf5NjPMAzNvUQUrDJk+hyq+TUX7Iuvi3hgW9d+POtkNO8gMSDIwJoUcx7ls6XZb7aZGEs4Fnmz/OyWJVBDEcI2CH3DAWr3hYFAEui4jzb7Kh8Rjrjj53w2Kt0WcJ2fPReTVqygbm/fbxlD1PGKXtaO13BXt9i6FQ8p52KByaWym2VccrOK2yajiA4/xANaGhRvS3WokSLmlrU0qK2FnW0qKtFp7oOa8PF2g5jbYexnkHbYaztMNZ2GGs7jLUdxtoOY22HtYERbYeJtsNE22Gi59V2mGg7TGxduKYOtHSg1t3Rga4OnLL79xiEpY+tJgrGp+rdB9xr2w4np/LePFXvflH1TC17pdRvyT4Vb2FgHWO3ugYe3pOu2AlPV9YQjRRK3zlUvoCtlSDfRcmXrwpGHCY0ywtMc3i2yWFccgwfUtE8WcISd5GE8ZSK9zZwdu9E3ImkE81OtOtOhMjaiqAjCTqSoCMJOpLA6sSOLxjwhR1f2PGFHV/Y8YVW3YkDko49ZOxNq/FvV2DtVLqalNY16tqPuvajrv2oaz/q2o8G7Udd+xFrv2q12UwaXcKYb1vRms3qTuk8QJvNWrOgbxYMzIKeWdg3CwdmYa/9yGw9or5HvyuXXVcuB125ZF1hqbW25fdX8ISZx1nBdjXE3sRK1HDBxs8KP7XBOnNo/lt1tyuNHS3aQww7Nuy5Ljdhfo4wjxE4MsUZpLSAWSrzbReOUfshlsGE94ElTHhPz9cxPwoW8viSLNfQpaQQLMXg3FOoAwYPYJEE+ZZCGHDK2gSLOLOpeM7f0f7vPz58RPSyopfRuehg7nIZuhIKND/317FEGfGWS6rVhl4mcP68PLmMgolxiiZ5sRGCn4dJYtPLZlsmDTg1H8vgcNMcbj5Ad5i2rP51e3+xu2e/91HQ4aaD6JVD64/N9eFmZ1Pxix6Tst+xEHp42BF6u98TCud4lz7A9bG6sR0qfwC0bQz6FPhp9D6JinOPnY2XyS9x5LG3rjMY0QDmwlPrpccOWnGa++wE7bEDInv5IF8gR+Ui9tm8eVggFwAxhzKPC4mFCzhalcHVGk6cHn//24PhUAimCw9J7K2xvPQMpaC+gvsK6StmX7H6SrCBJbQM0+IYilP2/YBXZBsVzVuwyhad3SzoE/GhwGUczYdOEk9X4WoDrYyqnvGA9gdDIVEdDduWxiwCPSLh4DMcSMuBdBzoOQ6s5cA6DvwcB9FyEB0HeY7D1HKYOg7zOQ5Ly2HpOCwtR7lgXzNFcRGHRd9lrXIZcj7xYRXKErgbzpNZ350l/nrRWWZxLnMtSjIghKWvOC9FRrZe4nHhKG4JjiKMNHfioG9xWkaLq84B9OG9DEDBbsiBCUPQCMEjhAyQi3BlDJsGBI0QPELICDFHiDVC7BHijBA2cEiL2l3oSVrMAjkxyYrNep6FUl/MzmceESLb+mYBH88ewtY2BlkcWvowwDM2By19GhTJAFjPIjnpbqszBpEn6/cZVM/mvajZTzjEj7daDpZKwh7W1RK2+HXUc8jfwg7YX+mKmL9SLt/Dk/rqfc+S5Q9bmYXZBXQ3mcPOl+S8qaendtFabhaFh3C7YZTrcx84jFPDE1/YsjfiySryiATwEOCrFox7EsWe3QGb4qoMr8IFY7JaeMDN1yrpiTpA54lGnvjYE+s98ciTHHsSvScZeZrHnqbe0xx5Wseelt7T6nnKpaF1HG5ZEeyJ/O8IP5f4sf1Ciz9D8wzLcyTrpddjEPN/zMvRES1HF1p0RIq0pEhLirSkaEyKtaRYS4q1pHhMSrSkREtKtKRkTGpqSU0tqaklNceklpbU0pJaWlKrT6pSdsApwSGlBIeMsIjLta39Q+KD4M/gBbsYhkSQrEdIGEjJQMpVXHrBJHzbLJeXYnE8xtlmO3TgWwE7gWJsdgAcp0u2oHrYkttDkode6wRncvbLrv4obNKWaWp7bG/5H/Z7l4zd6oaLG/rU3uhCUEduvjMkjA4e6sQC//QED8RPOjNuJLaUXNkSxp0lFzH7jjNYXXrQkXwRs80iL7x8A09hKSzmeeEXYA2nIni08LPIW1yEy1VOCIHHjYVfhOflKitnMw/+Ez/gk4XBf7nHv0FVPwTEiD59y8ah0Jj1k/HkCsG3npyaifZPP/zwl4/+zq4Yrj75+S/ffv13UM2//+Vbr1+//scP4xpewas0rs96do6vn0glm/ftf4jaAY/1GjjMIQVgDAJntBs5+6QX2dNU1APwhCyQn5KjkcaWHifky88/39k7l/788x/Y3HszOJKgzzkysIfcnYe2UBLTtiAVibl1q8832Ko8RKHYejZ9hS0X8tShX/K9pfWoaY5c5GEbw3GhX7GnzGWET9GzeMMCBNDDXwkQQjLB3YTYqh3QEHqD3NqzkVPbuwbRV8jdchiEhrmDUO+hDwb9b4G20An+b7v9Rhu1x97aodqF4foCpc1KoCKeBZS1w6rBbCrawiYMEzyFg+BAWzsm8GFEDVKxYfonqiuPwGSAMOXCAm1N6O4rhBpw29ObPbRDv5yjLYE6t/K2n2EKGo8xQwPQJIHCoK9soTmisERRi6ISxVYUU078Cjj2jLh26C/YhNY+I8Pytshjje1ZII5HRGO71snlFF+2bGJgWraeaXgu+vwftG0oXKYUfHf0lwpqP1vE+3JApIYZhGGqYUS30P166xn0HJtb+gnVEKZBKRhVIyM0NnJHRnhs5IyMyNjIHhmZYyNrZGSNjcyRkT02IiMjZ2yER0bu2AiNjKZjI2NkVI2M8H5ktB0bNSOjemw0nuBmbLQdGe3GRuMs2I+NpuNUGScUHucKGmcUHicLGqcUHmcLGucUHqcLGicVHucLGmeVOU4YNE4rc5wxaJxX5jhl0DixzHHOIE1mjZMGjVOL7MZW49wi49xC4+QimtnWZJemRU16aUZ1lF97ls3Hng4Zg/tKgxljrLFG2C2q9mNw72oMkcYQG7YO1Lg3Y8PtjtlhvqfCEMCyD+P5Cm0rdhfBHmVCabMus7RhkTLz1gv695kbV3wAsUemwgl21WOfLw87dnvhzz+BM9TRX9nlywPiUUm4cgGGyxe2pRjHke1kZFhF5rAhYSnBWjN4ZMqtC60WoVV8O4bNXNCwzc+WwZojGgi2ElExPgBZtAaP1unhcE/8yi4Q7o4cR7uX0SIVrdvSd+NIjoJt5DhWKkZHxkhGzhCjKUeODELc7zq4N6A7BrPjjSUjhPnnjZpERbiF/CS8jcbkw7GXqwVUNoQlJeYwNioRvqBsw0eNKQebJY8BpyoTqY5YsiP7r7VhjdqAXu5ld3beHrJmz5JmZ7cYxPUrfL48YMPoDDEYYj4YnTcE9yt8ALTdFoRm6K/swkaoOZpDjMQI7b92KzTP3Aru126FWgbQ6G+FZjBzaEpYWI0HhzoZGnJcOXmOiq2mB8tRQ8l+JQo6b+5gTTvYZHDV6WxNsrbCrO5gmOzDdM/hyuhgB+AKdbrLdNzpW6aTTreZLqa5sjp4CvCWJ/Oh7tgwa7Tu2Ph6WRNhZnbeDYN7bDum250bYknkiNvZILLcd/WsdXiO74CKA71AGg70InE5ILlQFwt2eEXNMwFN2bg6XSqw/4WS5wLG6i5oZFIMJgu5tm6ykDsdTBZyzePJ+n86J0N2###4300:XlxV32DM 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df8eNrtW8uu2zYQ/ZnuurHIISnayK8Y4EtANu0iy4v8e/mYI9MyaThtARtoEST0JSWdOTMj6fhc5nw6X376xa7n03nJf09fvwm9nIV0lz+Etud1ufwmYjx7e/ldqHguh/9oh8uvb4tfz0Ktl29lJi9fruWffIAvBwg+QKoyLy4/M5ArIKL8+fpDGHGmaC8NMTWgFC/f88EFCIB+Ce2sLjzbwpO6nC3O0mwcp8ynS1VO+zNHdm70KuqInrEjevXwQi/jNnpuuaPX4uED7uiFIz3X6Cn3jF6Y0CP7Gr0wq14Y0gugF0Av3NMLoBfu6Vl7pOe5eusTet7OqhdfoldRh/ROw+a0aE6L5rT3zWnRnPZQPXGkFxo9uTyrnpjRU69VT8yacx1WT6B6AtUT99UTqJ440ItHerHRW8IzenHWnOtr9OKsen5IL4JeBL14Ty+CXjw0pzvSS9yc9llzuln1wmvN6WbV24bN6dCcDs3p7pvToTndoXrySG/j5hTPqidn9Oi16skZPTOsnkT1JKon76snUT15oJcO9NKJm9M/o5dmzWleo5dmzemG9BLoJdBL9/QS6KVDc/ojvYWb89mLwftZ9fxrzeln1UvD5vRoTo/m9PfN6dGc/lA9OtIT3JzyWfVoRk++Vj2a0dPD6hGqR6ge3VePUD060NuO9CQ359PX+jZrzhdVyzZrzrFq2UBvA73tnt4GetuBnjrSI64ePaOnZtUTr9FTs+qpIT0Fegr01D09BXrqnp4/Hekprl58Qi+eZtV77bVeUYfVG77W6+GFXsZt9Pzpjl6Lhw+4q54+0tNcPfWsenpWveW16ulZ9WhYPY3qaVRP31dPo3r6jp5U27lc/Vy+SDSCyjNBxfXbxOVPU14sl+9GtUG3wbRhbYNtg6uDbYysaUNbs7zm2xDaENuQ2rDVwZ3qefWZcvnu25pva+HUhqUNog0twNAiCy2k0E7YWtRbW9ta1Fs7ZGuRbS2yrUW2UD3GS1liS10ZQmplaOogl3H/Bqdfyg4iilzvFrVIK4+WR8ej5zHwmFp/SKpfuU59ZBtHBtW/snDx5lfqhgATB0i/GGA8BCrtIYPxxHH692ZQmmMG48KR2c/KYPkQ+zhFi7NJuH+Ywb/Te+WO2/qAJCcu/XuJ+ycJc8eEEccX3pMwuR4Tpjgg9wEJ+7FQuY79+lYed/kx8q08XeqYb942Gh4Trwv+2fG4lvGa//78ITW/ScvZ+fa8XB0VkJXVb5nOX73rRfN4teX9JE4JJ5nzlvI5p3Iptd1m842UD7b1Ura7lOFLmbwa6pu80PONTc5Jo9M+lIgSY/OHhGMEZlxRSHXkiZUn1jpx3VRFYROnnFgCDmud9bdM5vwCOwE7ATsBOwE7ATMBq1xV16s68E3FUqsn5PEaREndYrpVzav6cvVbPTf12bCIyCIii4gsIrKIyHI2NCKznA2NCHMMm64xrF0MhmPIFQmnuqq7VcWrWYP4VKtpumpqrmaO3/q6GrtVDrZwt/XcaLsrcxlLU4WlrKby6FWN+xYb4zYmHl0Zr/l1Xw8X6La1lnSrAaSlT2BAAgMSGJDAgAQGJDBwAi0SGDiBFgkMGaW2dDr1KB4oHigeKB4oHiieUVageEZZgeIzSmvPrUdxQHFAcUBxQHFAcYxigOIYxQDFZZSax1V1JVNcslxu62oMEjfOUrNsVX1o0G223ulG1um9JLE9S2xDCECIfEMstSlMezy4bpXv/9IUpuZgXbtVw6u5VU27su5WNa/mZjT1RlypW1W8mpkZVdu8fX2/Gk6scXW2PSiulh+kPNtstmuQ3LRtttys+uu6Ibl7iSIqE1GQiLzHquN1eNDxDuZ4+s/reKUmOj6YN+t4M9PxQX2WCl0mOj7IN2dwm+n4sHxUBpWe6PiwvknHrxMdH/Rn6Hgx0fGB3pMwdZro+CA+S8fnx13T6dDtrOfzAXXMrdh+Xnmd9XwmeNPxKuLdu4x1/MJv122k4/PsTcfrcJsd6viFX8XbSMdnNqzRd9UOQV+uVz9kRjyz4hjB4gPCPpOrE3kc6vh1pOMrdgJ2AnYCdgJ2AnYCZgLWo47PZzTZso50fFnVvPqo42tEFhFZRGQRkUVEFhFZzoZGZJazoRHho44vMRiO4VHHl1XFqwMdv3D821DHL8x9G+n4cmUu40DHZ+5Nty9tzEe3n8VQx2duAx1fExiQwIAEBiQwIIEBCQycQIsEBk6gRQIfdXxF8UDxQPFA8UDxQPGMsgLFM8oKlEcdX1EcUBxQHFAcUBxQHKMYoDhGMUAZ6PiFy70Ndbzpdfx6m+11PL7Il4AHOj5PG+7pgY4vq3z/D3R8WTW8+qjjy6rm1UcdX1YVr950/NbreCh2cep0fMlEm116Hb9iVnQ6viR3L1FEZSIKEpF31vHxUcfzL9rV9r+ONzMd/2Y/Xvmpjv8sP74yHOr4N/vxapnq+M/y4+vv6EY6Pr7Jj1dhpuM/w4+vGR/q+Df58UrMdPyH+fGK9Xt+urRR8sh6XrF+zx3QRuJR9H48JLmSQx2fp5vEWEY6Xi29jo+32ZGOL5cyfKmBjod8z3T4g8QHCHoF+Z4p8Qdi2U6YYGGvxFDH5xNHOh7yvWInYCdgJ2AnYCdgJmANdDx7ufmEkY5nq7ysDnQ85HuNyCIii4gsIrKIyHI2NCKznA2NCAc6nh3aEsNAx/OvNsrqo44v1dRczUcdX1Y52JGOZ/+5XHmg4w3rd8njyiONdbwY6njI95rAgAQGJDAggQEJDJxAiwQGTqBFAgc6HvK9onigeKB4oHigeEZZgeIZZQXKQMdDvlcUBxQHFAcUBxTHKAYojlEMUB51fCmZ4pI96vgMfdPxRtxmOx1v8Lu9EvBIxxtOph/qeMNJ8EMdbzh4P9TxhpvRD3W8YWa+0/FCdjq+rDRtTp2OV3Dphep0fGnaNqt7HS/OZi9RRGUiChKRd9bx8nFfDfvx+vSf1/E08+PTu/14OdPx6bP8eJrtq0lv9uPl1I9Pn+XH08yPT+/y42mi49Nn+PE021eT3uTH08yPTx/mxxP8eNbvhH017McT/HjW78T7aqj347WBtTbeV0PYVzP04+WdHy9vsyMdT9hXM/TjaffjId9p31cDP552Px6ynXhfDWFfDbEfTxM/nkY6nnY/HvKd9n018ONp9+Mh3wn7amjsxxP8eBrpeIIfTyMdT7sfD/lO+74a+PG0+/GQ7cT7agj7aoj9eBr78QQ/nkY6nuDH00jHE/bVDP14wr6aoR9P8ONppOOJ/XjifTXEfjyN99XQ0I+n3Y+HfKd9Xw38eNr9eMh24n01hH01xH48jf142v14yHfa99XAj6fdj4dsJ95XQ9hXQ+zH09iPp92Ph3ynfV8N/Hja/XjIduJ9NYR9NcR+PI39eMK+mrEfL3s/Xt1mez9eY3rsxxP8eDnS8QQ/Xo50PMGPlyMdT/Dj5UjHE/x42et40/vxEtp87ffV7H687f14wqzrdDzBj5fYRbP78YQPNz/eLI86nv/zjV7+3x/vZ/vj36zj63+oGO+P/7B9NTM/Pr5Zxys73R//WTpehpkf/yYdLzVk6V/t/62r###5404:XlxV32DM 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4042l:0b<8=:018yvef2909wSmn;<057?7402F:n:4>{%4f>7552z\`=>;5>:0:?:5C1c595~"1m3887p*>628f4>h6>;0:96s|e983>7}Ym116>;=51448H4d028q/:h4=3:'535=m91e=;<5179~w`1=838pRh94=340>4323E;i;7?t$7g966=z,8<86h>4n041>4186B>b682!0b2;90q)?93;g3?k71:3;37p}j5;296~Xb=279:>4>529O5g1=9r.=i7<<;|&2269:pa1<72;qUi9522719504{#9?91i=5a17095d=z{l91<77?l;|qga?6=:rToi63=62820f=K9k=1=v*9e;00?x"6>:0n<6`>6382`>{tl:0;6?uQd29>635=9=;0@<5;<86<=9;M3a3?7|,?o1>>5r$040>`65<5s48=?7hi;<40>``7A?m7;3x 3c=k2wvqpsr@AAx7=5=:82>>|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A6|FSB_D<4>|IOB|IO_L4N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A7|FSB_D<6>|IOB|IO_L6N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A8|FSB_D<12>|IOB|IO_L33N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A9|FSB_D<14>|IOB|IO_L34N_GCLK18_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A10|FSB_D<16>|IOB|IO_L35N_GCLK16_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A11|FSB_D<22>|IOB|IO_L39N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A12|FSB_D<28>|IOB|IO_L62N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A13|FSB_D<30>|IOB|IO_L63N_SCP6_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +A14|RAMCLK0|IOB|IO_L65N_SCP2_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE| A15|||TMS|||||||||||| A16|||GND|||||||||||| -B1|CPUCLK|IOB|IO_L50N_M3BA2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE| +B1||IOBS|IO_L50N_M3BA2_3|UNUSED||3||||||||| B2||IOBM|IO_L52P_M3A8_3|UNUSED||3||||||||| B3||IOBM|IO_L83P_3|UNUSED||3||||||||| -B4|||VCCO_0|||0|||||any******|||| -B5||IOBM|IO_L2P_0|UNUSED||0||||||||| -B6||IOBM|IO_L4P_0|UNUSED||0||||||||| +B4|||VCCO_0|||0|||||3.30|||| +B5|CPUCLK|IOB|IO_L2P_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE| +B6|FSB_D<3>|IOB|IO_L4P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| B7|||GND|||||||||||| -B8||IOBM|IO_L33P_0|UNUSED||0||||||||| -B9|||VCCO_0|||0|||||any******|||| -B10||IOBM|IO_L35P_GCLK17_0|UNUSED||0||||||||| +B8|FSB_D<11>|IOB|IO_L33P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +B9|||VCCO_0|||0|||||3.30|||| +B10|FSB_D<15>|IOB|IO_L35P_GCLK17_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| B11|||GND|||||||||||| -B12||IOBM|IO_L62P_0|UNUSED||0||||||||| -B13|||VCCO_0|||0|||||any******|||| -B14||IOBM|IO_L65P_SCP3_0|UNUSED||0||||||||| -B15||IOBM|IO_L29P_A23_M1A13_1|UNUSED||1||||||||| -B16||IOBS|IO_L29N_A22_M1A14_1|UNUSED||1||||||||| -C1|FPUCLK|IOB|IO_L50P_M3WE_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE| -C2|INt|IOB|IO_L48N_M3BA1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -C3|OUTt|IOB|IO_L48P_M3BA0_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|NO|NONE| -C4||IOBM|IO_L1P_HSWAPEN_0|UNUSED||0||||||||| -C5||IOBS|IO_L3N_0|UNUSED||0||||||||| -C6||IOBS|IO_L7N_0|UNUSED||0||||||||| -C7||IOBM|IO_L6P_0|UNUSED||0||||||||| -C8||IOBS|IO_L38N_VREF_0|UNUSED||0||||||||| -C9||IOBM|IO_L34P_GCLK19_0|UNUSED||0||||||||| -C10||IOBS|IO_L37N_GCLK12_0|UNUSED||0||||||||| -C11||IOBM|IO_L39P_0|UNUSED||0||||||||| +B12|FSB_D<27>|IOB|IO_L62P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +B13|||VCCO_0|||0|||||3.30|||| +B14|FSB_A<2>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE| +B15|FSB_A<6>|IOB|IO_L29P_A23_M1A13_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +B16|FSB_A<7>|IOB|IO_L29N_A22_M1A14_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +C1||IOBM|IO_L50P_M3WE_3|UNUSED||3||||||||| +C2||IOBS|IO_L48N_M3BA1_3|UNUSED||3||||||||| +C3||IOBM|IO_L48P_M3BA0_3|UNUSED||3||||||||| +C4|RAMCLK1|IOB|IO_L1P_HSWAPEN_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE| +C5|FSB_D<2>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +C6|FSB_D<10>|IOB|IO_L7N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +C7|FSB_D<7>|IOB|IO_L6P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +C8|FSB_D<24>|IOB|IO_L38N_VREF_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +C9|FSB_D<13>|IOB|IO_L34P_GCLK19_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +C10|FSB_D<20>|IOB|IO_L37N_GCLK12_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +C11|FSB_D<23>|IOB|IO_L39P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| C12|||TDI|||||||||||| -C13||IOBM|IO_L63P_SCP7_0|UNUSED||0||||||||| +C13|FSB_D<29>|IOB|IO_L63P_SCP7_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| C14|||TCK|||||||||||| -C15||IOBM|IO_L33P_A15_M1A10_1|UNUSED||1||||||||| -C16||IOBS|IO_L33N_A14_M1A4_1|UNUSED||1||||||||| -D1|RAMCLK0|IOB|IO_L49N_M3A2_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE| -D2|||VCCO_3|||3|||||3.30|||| -D3|RAMCLK1|IOB|IO_L49P_M3A7_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE| +C15|FSB_A<14>|IOB|IO_L33P_A15_M1A10_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +C16|FSB_A<20>|IOB|IO_L33N_A14_M1A4_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +D1||IOBS|IO_L49N_M3A2_3|UNUSED||3||||||||| +D2|||VCCO_3|||3|||||any******|||| +D3||IOBM|IO_L49P_M3A7_3|UNUSED||3||||||||| D4|||GND|||||||||||| -D5||IOBM|IO_L3P_0|UNUSED||0||||||||| -D6||IOBM|IO_L7P_0|UNUSED||0||||||||| -D7|||VCCO_0|||0|||||any******|||| -D8||IOBM|IO_L38P_0|UNUSED||0||||||||| -D9||IOBS|IO_L40N_0|UNUSED||0||||||||| -D10|||VCCO_0|||0|||||any******|||| -D11||IOBM|IO_L66P_SCP1_0|UNUSED||0||||||||| -D12||IOBS|IO_L66N_SCP0_0|UNUSED||0||||||||| +D5|FSB_D<1>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +D6|FSB_D<9>|IOB|IO_L7P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +D7|||VCCO_0|||0|||||3.30|||| +D8|FSB_D<21>|IOB|IO_L38P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +D9|FSB_D<26>|IOB|IO_L40N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +D10|||VCCO_0|||0|||||3.30|||| +D11|FPUCLK|IOB|IO_L66P_SCP1_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|YES|NONE| +D12|CPU_nSTERM|IOB|IO_L66N_SCP0_0|OUTPUT|LVCMOS33|0|24|FAST||||UNLOCATED|NO|NONE| D13|||GND|||||||||||| -D14||IOBM|IO_L31P_A19_M1CKE_1|UNUSED||1||||||||| +D14|FSB_A<10>|IOB|IO_L31P_A19_M1CKE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| D15|||VCCO_1|||1|||||any******|||| -D16||IOBS|IO_L31N_A18_M1A12_1|UNUSED||1||||||||| -E1|FSB_A<27>|IOB|IO_L46N_M3CLKN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -E2|FSB_A<24>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +D16|FSB_A<11>|IOB|IO_L31N_A18_M1A12_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +E1||IOBS|IO_L46N_M3CLKN_3|UNUSED||3||||||||| +E2||IOBM|IO_L46P_M3CLK_3|UNUSED||3||||||||| E3||IOBS|IO_L54N_M3A11_3|UNUSED||3||||||||| E4||IOBM|IO_L54P_M3RESET_3|UNUSED||3||||||||| E5|||VCCAUX||||||||2.5|||| -E6||IOBS|IO_L5N_0|UNUSED||0||||||||| -E7||IOBM|IO_L36P_GCLK15_0|UNUSED||0||||||||| -E8||IOBS|IO_L36N_GCLK14_0|UNUSED||0||||||||| +E6|FSB_D<8>|IOB|IO_L5N_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +E7|FSB_D<17>|IOB|IO_L36P_GCLK15_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +E8|FSB_D<18>|IOB|IO_L36N_GCLK14_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| E9|||GND|||||||||||| -E10||IOBM|IO_L37P_GCLK13_0|UNUSED||0||||||||| -E11||IOBS|IO_L64N_SCP4_0|UNUSED||0||||||||| -E12||IOBS|IO_L1N_A24_VREF_1|UNUSED||1||||||||| -E13||IOBM|IO_L1P_A25_1|UNUSED||1||||||||| +E10|FSB_D<19>|IOB|IO_L37P_GCLK13_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +E11|FSB_A<3>|IOB|IO_L64N_SCP4_0|INPUT|LVCMOS33|0||||NONE||UNLOCATED|NO|NONE| +E12|FSB_A<5>|IOB|IO_L1N_A24_VREF_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +E13|FSB_A<4>|IOB|IO_L1P_A25_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| E14|||TDO|||||||||||| -E15||IOBM|IO_L34P_A13_M1WE_1|UNUSED||1||||||||| -E16||IOBS|IO_L34N_A12_M1BA2_1|UNUSED||1||||||||| -F1|FSB_A<23>|IOB|IO_L41N_GCLK26_M3DQ5_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -F2|FSB_A<22>|IOB|IO_L41P_GCLK27_M3DQ4_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +E15|FSB_A<21>|IOB|IO_L34P_A13_M1WE_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +E16|FSB_A<22>|IOB|IO_L34N_A12_M1BA2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +F1||IOBS|IO_L41N_GCLK26_M3DQ5_3|UNUSED||3||||||||| +F2||IOBM|IO_L41P_GCLK27_M3DQ4_3|UNUSED||3||||||||| F3||IOBS|IO_L53N_M3A12_3|UNUSED||3||||||||| F4||IOBM|IO_L53P_M3CKE_3|UNUSED||3||||||||| F5||IOBS|IO_L55N_M3A14_3|UNUSED||3||||||||| F6||IOBM|IO_L55P_M3A13_3|UNUSED||3||||||||| -F7||IOBM|IO_L5P_0|UNUSED||0||||||||| +F7|FSB_D<5>|IOB|IO_L5P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| F8|||VCCAUX||||||||2.5|||| -F9||IOBM|IO_L40P_0|UNUSED||0||||||||| -F10||IOBM|IO_L64P_SCP5_0|UNUSED||0||||||||| +F9|FSB_D<25>|IOB|IO_L40P_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| +F10|FSB_D<31>|IOB|IO_L64P_SCP5_0|OUTPUT|LVCMOS33|0|8|SLOW||||UNLOCATED|NO|NONE| F11|||VCCAUX||||||||2.5|||| -F12||IOBM|IO_L30P_A21_M1RESET_1|UNUSED||1||||||||| -F13||IOBM|IO_L32P_A17_M1A8_1|UNUSED||1||||||||| -F14||IOBS|IO_L32N_A16_M1A9_1|UNUSED||1||||||||| -F15||IOBM|IO_L35P_A11_M1A7_1|UNUSED||1||||||||| -F16||IOBS|IO_L35N_A10_M1A2_1|UNUSED||1||||||||| -G1|FSB_A<29>|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +F12|FSB_A<8>|IOB|IO_L30P_A21_M1RESET_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +F13|FSB_A<12>|IOB|IO_L32P_A17_M1A8_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +F14|FSB_A<13>|IOB|IO_L32N_A16_M1A9_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +F15|FSB_A<23>|IOB|IO_L35P_A11_M1A7_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +F16|FSB_A<19>|IOB|IO_L35N_A10_M1A2_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +G1||IOBS|IO_L40N_M3DQ7_3|UNUSED||3||||||||| G2|||GND|||||||||||| -G3|FSB_A<19>|IOB|IO_L40P_M3DQ6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -G4|||VCCO_3|||3|||||3.30|||| +G3||IOBM|IO_L40P_M3DQ6_3|UNUSED||3||||||||| +G4|||VCCO_3|||3|||||any******|||| G5||IOBS|IO_L51N_M3A4_3|UNUSED||3||||||||| -G6|CLKFB_OUT|IOB|IO_L51P_M3A10_3|OUTPUT|LVCMOS33|3|24|FAST||||UNLOCATED|YES|NONE| +G6||IOBM|IO_L51P_M3A10_3|UNUSED||3||||||||| G7|||VCCINT||||||||1.2|||| G8|||GND|||||||||||| G9|||VCCINT||||||||1.2|||| G10|||VCCAUX||||||||2.5|||| -G11||IOBS|IO_L30N_A20_M1A11_1|UNUSED||1||||||||| -G12||IOBM|IO_L38P_A5_M1CLK_1|UNUSED||1||||||||| +G11|FSB_A<9>|IOB|IO_L30N_A20_M1A11_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +G12|FSB_A<24>|IOB|IO_L38P_A5_M1CLK_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| G13|||VCCO_1|||1|||||any******|||| -G14||IOBM|IO_L36P_A9_M1BA0_1|UNUSED||1||||||||| +G14|FSB_A<15>|IOB|IO_L36P_A9_M1BA0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| G15|||GND|||||||||||| -G16||IOBS|IO_L36N_A8_M1BA1_1|UNUSED||1||||||||| -H1|FSB_A<26>|IOB|IO_L39N_M3LDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -H2|FSB_A<25>|IOB|IO_L39P_M3LDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -H3|CPU_nAS|IOB|IO_L44N_GCLK20_M3A6_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +G16|FSB_A<16>|IOB|IO_L36N_A8_M1BA1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +H1||IOBS|IO_L39N_M3LDQSN_3|UNUSED||3||||||||| +H2||IOBM|IO_L39P_M3LDQS_3|UNUSED||3||||||||| +H3||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3||||||||| H4|CLKFB_IN|IOB|IO_L44P_GCLK21_M3A5_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE| -H5|FSB_A<30>|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +H5||IOBS|IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED||3||||||||| H6|||VCCAUX||||||||2.5|||| H7|||GND|||||||||||| H8|||VCCINT||||||||1.2|||| H9|||GND|||||||||||| H10|||VCCINT||||||||1.2|||| -H11||IOBS|IO_L38N_A4_M1CLKN_1|UNUSED||1||||||||| +H11|FSB_A<25>|IOB|IO_L38N_A4_M1CLKN_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| H12|||GND|||||||||||| -H13||IOBM|IO_L39P_M1A3_1|UNUSED||1||||||||| -H14||IOBS|IO_L39N_M1ODT_1|UNUSED||1||||||||| -H15||IOBM|IO_L37P_A7_M1A0_1|UNUSED||1||||||||| -H16||IOBS|IO_L37N_A6_M1A1_1|UNUSED||1||||||||| -J1|FSB_A<17>|IOB|IO_L38N_M3DQ3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -J2|||VCCO_3|||3|||||3.30|||| -J3|FSB_A<16>|IOB|IO_L38P_M3DQ2_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +H13|FSB_A<26>|IOB|IO_L39P_M1A3_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +H14|FSB_A<27>|IOB|IO_L39N_M1ODT_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +H15|FSB_A<17>|IOB|IO_L37P_A7_M1A0_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +H16|FSB_A<18>|IOB|IO_L37N_A6_M1A1_1|INPUT|LVCMOS33|1||||NONE||UNLOCATED|NO|NONE| +J1||IOBS|IO_L38N_M3DQ3_3|UNUSED||3||||||||| +J2|||VCCO_3|||3|||||any******|||| +J3||IOBM|IO_L38P_M3DQ2_3|UNUSED||3||||||||| J4|CLKIN|IOB|IO_L42N_GCLK24_M3LDM_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE| J5|||GND|||||||||||| -J6|FSB_A<21>|IOB|IO_L43P_GCLK23_M3RASN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +J6||IOBM|IO_L43P_GCLK23_M3RASN_3|UNUSED||3||||||||| J7|||VCCINT||||||||1.2|||| J8|||GND|||||||||||| J9|||VCCINT||||||||1.2|||| @@ -163,12 +163,12 @@ J13||IOBM|IO_L41P_GCLK9_IRDY1_M1RASN_1|UNUSED||1||||||||| J14||IOBM|IO_L43P_GCLK5_M1DQ4_1|UNUSED||1||||||||| J15|||VCCO_1|||1|||||any******|||| J16||IOBS|IO_L43N_GCLK4_M1DQ5_1|UNUSED||1||||||||| -K1|FSB_A<5>|IOB|IO_L37N_M3DQ1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -K2|FSB_A<14>|IOB|IO_L37P_M3DQ0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -K3|FSB_A<28>|IOB|IO_L42P_GCLK25_TRDY2_M3UDM_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -K4|||VCCO_3|||3|||||3.30|||| -K5|CPUCLKi|IOB|IO_L47P_M3A0_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -K6|FSB_A<18>|IOB|IO_L47N_M3A1_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +K1||IOBS|IO_L37N_M3DQ1_3|UNUSED||3||||||||| +K2||IOBM|IO_L37P_M3DQ0_3|UNUSED||3||||||||| +K3||IOBM|IO_L42P_GCLK25_TRDY2_M3UDM_3|UNUSED||3||||||||| +K4|||VCCO_3|||3|||||any******|||| +K5||IOBM|IO_L47P_M3A0_3|UNUSED||3||||||||| +K6||IOBS|IO_L47N_M3A1_3|UNUSED||3||||||||| K7|||GND|||||||||||| K8|||VCCINT||||||||1.2|||| K9|||GND|||||||||||| @@ -179,11 +179,11 @@ K13|||VCCO_1|||1|||||any******|||| K14||IOBS|IO_L41N_GCLK8_M1CASN_1|UNUSED||1||||||||| K15||IOBM|IO_L44P_A3_M1DQ6_1|UNUSED||1||||||||| K16||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1||||||||| -L1|FSB_A<11>|IOB|IO_L36N_M3DQ9_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +L1||IOBS|IO_L36N_M3DQ9_3|UNUSED||3||||||||| L2|||GND|||||||||||| -L3|FSB_A<4>|IOB|IO_L36P_M3DQ8_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -L4|FSB_A<31>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -L5|FSB_A<20>|IOB|IO_L45N_M3ODT_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +L3||IOBM|IO_L36P_M3DQ8_3|UNUSED||3||||||||| +L4||IOBM|IO_L45P_M3A3_3|UNUSED||3||||||||| +L5||IOBS|IO_L45N_M3ODT_3|UNUSED||3||||||||| L6|||VCCAUX||||||||2.5|||| L7||IOBS|IO_L62N_D6_2|UNUSED||2||||||||| L8||IOBM|IO_L62P_D5_2|UNUSED||2||||||||| @@ -195,11 +195,11 @@ L13||IOBS|IO_L53N_VREF_1|UNUSED||1||||||||| L14||IOBM|IO_L47P_FWE_B_M1DQ0_1|UNUSED||1||||||||| L15|||GND|||||||||||| L16||IOBS|IO_L47N_LDC_M1DQ1_1|UNUSED||1||||||||| -M1|FSB_A<1>|IOB|IO_L35N_M3DQ11_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -M2|FSB_A<2>|IOB|IO_L35P_M3DQ10_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -M3|FSB_A<6>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -M4|FSB_A<8>|IOB|IO_L1P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -M5|FSB_A<15>|IOB|IO_L2P_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +M1||IOBS|IO_L35N_M3DQ11_3|UNUSED||3||||||||| +M2||IOBM|IO_L35P_M3DQ10_3|UNUSED||3||||||||| +M3||IOBS|IO_L1N_VREF_3|UNUSED||3||||||||| +M4||IOBM|IO_L1P_3|UNUSED||3||||||||| +M5||IOBM|IO_L2P_3|UNUSED||3||||||||| M6||IOBM|IO_L64P_D8_2|UNUSED||2||||||||| M7||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2||||||||| M8|||GND|||||||||||| @@ -211,10 +211,10 @@ M13||IOBM|IO_L74P_AWAKE_1|UNUSED||1||||||||| M14||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1||||||||| M15||IOBM|IO_L46P_FCS_B_M1DQ2_1|UNUSED||1||||||||| M16||IOBS|IO_L46N_FOE_B_M1DQ3_1|UNUSED||1||||||||| -N1|FSB_A<10>|IOB|IO_L34N_M3UDQSN_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -N2|||VCCO_3|||3|||||3.30|||| -N3|FSB_A<13>|IOB|IO_L34P_M3UDQS_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -N4|FSB_A<0>|IOB|IO_L2N_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +N1||IOBS|IO_L34N_M3UDQSN_3|UNUSED||3||||||||| +N2|||VCCO_3|||3|||||any******|||| +N3||IOBM|IO_L34P_M3UDQS_3|UNUSED||3||||||||| +N4||IOBS|IO_L2N_3|UNUSED||3||||||||| N5||IOBM|IO_L49P_D3_2|UNUSED||2||||||||| N6||IOBS|IO_L64N_D9_2|UNUSED||2||||||||| N7|||VCCO_2|||2|||||any******|||| @@ -227,8 +227,8 @@ N13|||GND|||||||||||| N14||IOBM|IO_L45P_A1_M1LDQS_1|UNUSED||1||||||||| N15|||VCCO_1|||1|||||any******|||| N16||IOBS|IO_L45N_A0_M1LDQSN_1|UNUSED||1||||||||| -P1|FSB_A<7>|IOB|IO_L33N_M3DQ13_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -P2|FSB_A<12>|IOB|IO_L33P_M3DQ12_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +P1||IOBS|IO_L33N_M3DQ13_3|UNUSED||3||||||||| +P2||IOBM|IO_L33P_M3DQ12_3|UNUSED||3||||||||| P3|||GND|||||||||||| P4||IOBM|IO_L63P_2|UNUSED||2||||||||| P5||IOBS|IO_L49N_D4_2|UNUSED||2||||||||| @@ -243,8 +243,8 @@ P13|||DONE_2|||||||||||| P14|||SUSPEND|||||||||||| P15||IOBM|IO_L48P_HDC_M1DQ8_1|UNUSED||1||||||||| P16||IOBS|IO_L48N_M1DQ9_1|UNUSED||1||||||||| -R1|FSB_A<9>|IOB|IO_L32N_M3DQ15_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| -R2|FSB_A<3>|IOB|IO_L32P_M3DQ14_3|INPUT|LVCMOS33|3||||NONE||UNLOCATED|NO|NONE| +R1||IOBS|IO_L32N_M3DQ15_3|UNUSED||3||||||||| +R2||IOBM|IO_L32P_M3DQ14_3|UNUSED||3||||||||| R3||IOBM|IO_L65P_INIT_B_2|UNUSED||2||||||||| R4|||VCCO_2|||2|||||any******|||| R5||IOBM|IO_L48P_D7_2|UNUSED||2||||||||| diff --git a/fpga/WarpLC.par b/fpga/WarpLC.par index 616deb5..3a97d4e 100644 --- a/fpga/WarpLC.par +++ b/fpga/WarpLC.par @@ -1,28 +1,21 @@ -Release 14.7 par P.20131013 (nt) +Release 14.7 par P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -ZANEPC:: Fri Oct 29 17:59:50 2021 +DOG-PC:: Sun Oct 31 15:38:29 2021 -par -w -intstyle ise -ol high -mt off WarpLC_map.ncd WarpLC.ncd WarpLC.pcf +par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf Constraints file: WarpLC.pcf. Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. "WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set. -INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to -'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'. -INFO:Security:54 - 'xc6slx9' is a WebPack part. -INFO:Security:66 - Your license for 'ISE' is for evaluation use only. -WARNING:Security:43 - No license file was found in the standard Xilinx license directory. -WARNING:Security:44 - Since no license file was found, - please run the Xilinx License Configuration Manager - (xlcm or "Manage Xilinx Licenses") - to assist in obtaining a license. -WARNING:Security:40 - Your license for 'ISE' expires in 4 days. - ----------------------------------------------------------------------- +INFO:Par:338 - + Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are + not meeting timing but where the designer wants the tools to continue iterating on the design until no further design + speed improvements are possible. This can result in very long runtimes since the tools will continue improving the + design even if the time specs can not be met. If you are looking for the best possible design speed available from a + long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design + speed improvements have shrunk to the point that the time specs are not expected to be met. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) @@ -35,30 +28,32 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13". Device Utilization Summary: Slice Logic Utilization: - Number of Slice Registers: 34 out of 11,440 1% - Number used as Flip Flops: 34 + Number of Slice Registers: 1 out of 11,440 1% + Number used as Flip Flops: 1 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 - Number of Slice LUTs: 17 out of 5,720 1% - Number used as logic: 13 out of 5,720 1% - Number using O6 output only: 11 - Number using O5 output only: 0 - Number using O5 and O6: 2 + Number of Slice LUTs: 33 out of 5,720 1% + Number used as logic: 9 out of 5,720 1% + Number using O6 output only: 8 + Number using O5 output only: 1 + Number using O5 and O6: 0 Number used as ROM: 0 - Number used as Memory: 0 out of 1,440 0% - Number used exclusively as route-thrus: 4 - Number with same-slice register load: 4 - Number with same-slice carry load: 0 - Number with other load: 0 + Number used as Memory: 24 out of 1,440 1% + Number used as Dual Port RAM: 24 + Number using O6 output only: 4 + Number using O5 output only: 0 + Number using O5 and O6: 20 + Number used as Single Port RAM: 0 + Number used as Shift Register: 0 Slice Logic Distribution: - Number of occupied Slices: 11 out of 1,430 1% - Number of MUXCYs used: 12 out of 2,860 1% - Number of LUT Flip Flop pairs used: 41 - Number with an unused Flip Flop: 11 out of 41 26% - Number with an unused LUT: 24 out of 41 58% - Number of fully used LUT-FF pairs: 6 out of 41 14% + Number of occupied Slices: 9 out of 1,430 1% + Number of MUXCYs used: 8 out of 2,860 1% + Number of LUT Flip Flop pairs used: 33 + Number with an unused Flip Flop: 32 out of 33 96% + Number with an unused LUT: 0 out of 33 0% + Number of fully used LUT-FF pairs: 1 out of 33 3% Number of slice register sites lost to control set restrictions: 0 out of 11,440 0% @@ -69,12 +64,12 @@ Slice Logic Distribution: over-mapped for a non-slice resource or if Placement fails. IO Utilization: - Number of bonded IOBs: 43 out of 186 23% + Number of bonded IOBs: 66 out of 186 35% IOB Flip Flops: 5 Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% - Number of RAMB8BWERs: 0 out of 64 0% + Number of RAMB8BWERs: 1 out of 64 1% Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3% Number used as BUFIO2s: 1 Number used as BUFIO2_2CLKs: 0 @@ -107,42 +102,35 @@ Specific Feature Utilization: Overall effort level (-ol): High Router effort level (-rl): High -Starting initial Timing Analysis. REAL time: 2 secs -Finished initial Timing Analysis. REAL time: 2 secs - -Starting Router +PAR will use up to 4 processors +Starting Multi-threaded Router -Phase 1 : 164 unrouted; REAL time: 2 secs +Phase 1 : 386 unrouted; REAL time: 3 secs -Phase 2 : 120 unrouted; REAL time: 2 secs +Phase 2 : 172 unrouted; REAL time: 3 secs -Phase 3 : 68 unrouted; REAL time: 2 secs +Phase 3 : 110 unrouted; REAL time: 3 secs -Phase 4 : 68 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs +Phase 4 : 110 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs Updating file: WarpLC.ncd with current fully routed design. -Phase 5 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs +Phase 5 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs -Phase 6 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs +Phase 6 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs -Phase 7 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs +Phase 7 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs -Phase 8 : 0 unrouted; (Setup:0, Hold:367, Component Switching Limit:0) REAL time: 2 secs +Phase 8 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs -Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs +Phase 9 : 0 unrouted; (Setup:0, Hold:285, Component Switching Limit:0) REAL time: 4 secs -Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 secs -Total REAL time to Router completion: 2 secs -Total CPU time to Router completion: 2 secs +Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- +Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs +Total REAL time to Router completion: 4 secs +Total CPU time to Router completion (all processors): 4 secs Generating "PAR" statistics. @@ -153,11 +141,10 @@ Generating Clock Report +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ -|CLKGEN_inst/instance | | | | | | -|_name/clkfb_bufg_out | | | | | | -| | BUFGMUX_X3Y13| No | 2 | 0.000 | 2.077 | +| FSBCLK | BUFGMUX_X3Y13| No | 17 | 0.625 | 2.088 | +---------------------+--------------+------+------+------------+-------------+ -| FSBCLK | BUFGMUX_X2Y3| No | 17 | 0.700 | 2.135 | +|cg/pll/clkfb_bufg_ou | | | | | | +| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.139 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing @@ -179,123 +166,17 @@ Asterisk (*) preceding a constraint indicates it was not met. Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ---------------------------------------------------------------------------------------------------------- - COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.520ns| 10.480ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.772ns| | 0| 0 + TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP " | MAXDELAY | 7.121ns| 7.879ns| 0| 0 + FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns | | | | | ---------------------------------------------------------------------------------------------------------- - COMP "FSB_A<27>" OFFSET = IN 12 ns VALID | SETUP | 1.666ns| 10.334ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.698ns| | 0| 0 + TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pl | SETUP | 11.311ns| 3.689ns| 0| 0 + l_clkout0" TS_CLKIN / 2 HIGH 50% | HOLD | 0.458ns| | 0| 0 ---------------------------------------------------------------------------------------------------------- - COMP "INt" OFFSET = IN 12 ns VALID 12 ns | SETUP | 1.668ns| 10.332ns| 0| 0 - BEFORE COMP "CLKIN" | HOLD | 4.292ns| | 0| 0 + TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns H | MINLOWPULSE | 20.000ns| 10.000ns| 0| 0 + IGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- - COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.713ns| 10.287ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.756ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<21>" OFFSET = IN 12 ns VALID | SETUP | 1.725ns| 10.275ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.718ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<28>" OFFSET = IN 12 ns VALID | SETUP | 1.739ns| 10.261ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.510ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<31>" OFFSET = IN 12 ns VALID | SETUP | 1.753ns| 10.247ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.707ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<15>" OFFSET = IN 12 ns VALID | SETUP | 1.904ns| 10.096ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.834ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<20>" OFFSET = IN 12 ns VALID | SETUP | 1.936ns| 10.064ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.578ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.972ns| 10.028ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.706ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<24>" OFFSET = IN 12 ns VALID | SETUP | 1.974ns| 10.026ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.679ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<13>" OFFSET = IN 12 ns VALID | SETUP | 1.989ns| 10.011ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.709ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 1 | SETUP | 1.991ns| 10.009ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.618ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<19>" OFFSET = IN 12 ns VALID | SETUP | 2.005ns| 9.995ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.722ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.081ns| 9.919ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.621ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<22>" OFFSET = IN 12 ns VALID | SETUP | 2.093ns| 9.907ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.637ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<25>" OFFSET = IN 12 ns VALID | SETUP | 2.117ns| 9.883ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.244ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.124ns| 9.876ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.242ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<18>" OFFSET = IN 12 ns VALID | SETUP | 2.132ns| 9.868ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.829ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<29>" OFFSET = IN 12 ns VALID | SETUP | 2.136ns| 9.864ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.448ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<30>" OFFSET = IN 12 ns VALID | SETUP | 2.153ns| 9.847ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.725ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.158ns| 9.842ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.237ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<12>" OFFSET = IN 12 ns VALID | SETUP | 2.179ns| 9.821ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.605ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.234ns| 9.766ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.288ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.243ns| 9.757ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.464ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<23>" OFFSET = IN 12 ns VALID | SETUP | 2.263ns| 9.737ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.472ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<26>" OFFSET = IN 12 ns VALID | SETUP | 2.343ns| 9.657ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.292ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 | SETUP | 2.359ns| 9.641ns| 0| 0 - ns BEFORE COMP "CLKIN" | HOLD | 3.896ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<16>" OFFSET = IN 12 ns VALID | SETUP | 2.435ns| 9.565ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.493ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<10>" OFFSET = IN 12 ns VALID | SETUP | 2.438ns| 9.562ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.463ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<11>" OFFSET = IN 12 ns VALID | SETUP | 2.478ns| 9.522ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.200ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 1 | SETUP | 2.735ns| 9.265ns| 0| 0 - 2 ns BEFORE COMP "CLKIN" | HOLD | 3.204ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<17>" OFFSET = IN 12 ns VALID | SETUP | 2.739ns| 9.261ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.474ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "FSB_A<14>" OFFSET = IN 12 ns VALID | SETUP | 2.916ns| 9.084ns| 0| 0 - 12 ns BEFORE COMP "CLKIN" | HOLD | 3.242ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP | MAXDELAY | 2.960ns| 2.040ns| 0| 0 - "CLKIN" | | | | | ----------------------------------------------------------------------------------------------------------- - PERIOD analysis for net "CLKGEN_inst/inst | SETUP | 12.300ns| 2.700ns| 0| 0 - ance_name/clkout0" derived from NET "CLK | HOLD | 0.457ns| | 0| 0 - GEN_inst/instance_name/clkin1" PERIOD = 3 | | | | | - 0 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - NET "CLKGEN_inst/instance_name/clkin1" PE | MINLOWPULSE | 20.000ns| 10.000ns| 0| 0 - RIOD = 30 ns HIGH 50% | | | | | ----------------------------------------------------------------------------------------------------------- - PERIOD analysis for net "CLKGEN_inst/inst | MINPERIOD | 27.334ns| 2.666ns| 0| 0 - ance_name/clkfbout" derived from NET "CL | | | | | - KGEN_inst/instance_name/clkin1" PERIOD = | | | | | - 30 ns HIGH 50% | | | | | + TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_p | MINPERIOD | 27.334ns| 2.666ns| 0| 0 + ll_clkfbout" TS_CLKIN HIGH 50% | | | | | ---------------------------------------------------------------------------------------------------------- @@ -303,18 +184,15 @@ Derived Constraint Report Review Timing Report for more details on the following derived constraints. To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" or "Run Timing Analysis" from Timing Analyzer (timingan). -Derived Constraints for CLKGEN_inst/instance_name/clkin1 +Derived Constraints for TS_CLKIN +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|CLKGEN_inst/instance_name/clkin| 30.000ns| 10.000ns| 5.400ns| 0| 0| 0| 35| -|1 | | | | | | | | -| CLKGEN_inst/instance_name/clko| 15.000ns| 2.700ns| N/A| 0| 0| 35| 0| -| ut0 | | | | | | | | -| CLKGEN_inst/instance_name/clkf| 30.000ns| 2.666ns| N/A| 0| 0| 0| 0| -| bout | | | | | | | | +|TS_CLKIN | 30.000ns| 10.000ns| 7.378ns| 0| 0| 0| 6| +| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0| +| TS_cg_pll_clkout0 | 15.000ns| 3.689ns| N/A| 0| 0| 6| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. @@ -324,10 +202,10 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 3 secs -Total CPU time to PAR completion: 3 secs +Total REAL time to PAR completion: 4 secs +Total CPU time to PAR completion (all processors): 4 secs -Peak Memory Usage: 257 MB +Peak Memory Usage: 322 MB Placer: Placement generated during map. Routing: Completed - No errors found. @@ -335,7 +213,7 @@ Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 0 -Number of info messages: 0 +Number of info messages: 1 Writing design to file WarpLC.ncd diff --git a/fpga/WarpLC.pcf b/fpga/WarpLC.pcf index e5e1a63..24212dd 100644 --- a/fpga/WarpLC.pcf +++ b/fpga/WarpLC.pcf @@ -1,44 +1,232 @@ //! ************************************************************************** -// Written by: Map P.20131013 on Fri Oct 29 17:59:48 2021 +// Written by: Map P.20131013 on Sun Oct 31 15:38:26 2021 //! ************************************************************************** SCHEMATIC START; -NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; -COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN"; +PIN + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<26> + = BEL + "l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram" + PINNAME CLKAWRCLK; +PIN + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27> + = BEL + "l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram" + PINNAME CLKBRDCLK; +PIN cg/CPUCLK_inst_pins<1> = BEL "cg/CPUCLK_inst" PINNAME CK0; +PIN cg/CPUCLK_inst_pins<2> = BEL "cg/CPUCLK_inst" PINNAME CK1; +PIN cg/FPUCLK_inst_pins<1> = BEL "cg/FPUCLK_inst" PINNAME CK0; +PIN cg/FPUCLK_inst_pins<2> = BEL "cg/FPUCLK_inst" PINNAME CK1; +PIN cg/RAMCLK0_inst_pins<1> = BEL "cg/RAMCLK0_inst" PINNAME CK0; +PIN cg/RAMCLK0_inst_pins<2> = BEL "cg/RAMCLK0_inst" PINNAME CK1; +PIN cg/RAMCLK1_inst_pins<1> = BEL "cg/RAMCLK1_inst" PINNAME CK0; +PIN cg/RAMCLK1_inst_pins<2> = BEL "cg/RAMCLK1_inst" PINNAME CK1; +TIMEGRP cg_pll_clkout0 = BEL "cg/pll/clkout1_buf" PIN + "l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<26>" + PIN + "l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>" + BEL "cg/CPUCLKr" BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP" + PIN "cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN + "cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN + "cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN + "cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN + "cg/RAMCLK0_inst_pins<1>" PIN "cg/RAMCLK0_inst_pins<2>" PIN + "cg/RAMCLK0_inst_pins<1>" PIN "cg/RAMCLK0_inst_pins<2>" PIN + "cg/RAMCLK1_inst_pins<1>" PIN "cg/RAMCLK1_inst_pins<2>" PIN + "cg/RAMCLK1_inst_pins<1>" PIN "cg/RAMCLK1_inst_pins<2>"; +PIN cg/pll/clkfbout_oddr_pins<1> = BEL "cg/pll/clkfbout_oddr" PINNAME CK0; +PIN cg/pll/clkfbout_oddr_pins<2> = BEL "cg/pll/clkfbout_oddr" PINNAME CK1; +TIMEGRP cg_pll_clkfbout = BEL "cg/pll/clkfbout_bufg" PIN + "cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>" PIN + "cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>"; +TIMEGRP CPU_nSTERM = BEL "CPU_nSTERM"; +TIMEGRP FSB_A = BEL "CPU_nSTERM" PIN + "l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram_pins<27>" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP" + BEL + "l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP"; +PIN SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0> = BEL + "SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0" PINNAME DIVCLK; +PIN cg/pll/pll_base_inst/PLL_ADV_pins<2> = BEL "cg/pll/pll_base_inst/PLL_ADV" + PINNAME CLKIN1; +TIMEGRP CLKIN = PIN "SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0>" PIN + "cg/pll/pll_base_inst/PLL_ADV_pins<2>"; +TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%; +TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns; +TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%; +TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; BEL "CLKFB_OUT" FEEDBACK = 0.16 ns BEL "CLKFB_IN"; SCHEMATIC END; diff --git a/fpga/WarpLC.prj b/fpga/WarpLC.prj index 151862d..cd94034 100644 --- a/fpga/WarpLC.prj +++ b/fpga/WarpLC.prj @@ -1,3 +1,7 @@ -verilog work "ipcore_dir/CLK.v" -verilog work "CLKGEN.v" +verilog work "ipcore_dir/PLL.v" +verilog work "ipcore_dir/PrefetchTagRAM.v" +verilog work "ipcore_dir/PrefetchDataRAM.v" +verilog work "SizeDecode.v" +verilog work "PrefetchBuf.v" +verilog work "ClkGen.v" verilog work "WarpLC.v" diff --git a/fpga/WarpLC.ptwx b/fpga/WarpLC.ptwx index 95ae8d0..c8da838 100644 --- a/fpga/WarpLC.ptwx +++ b/fpga/WarpLC.ptwx @@ -329,4 +329,4 @@ ]> -COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN"PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" derived from NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%PERIOD analysis for net "CLKGEN_inst/instance_name/clkfbout" derived from NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%0 +TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 nsTS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%0 diff --git a/fpga/WarpLC.syr b/fpga/WarpLC.syr index df9c5db..d877bc4 100644 --- a/fpga/WarpLC.syr +++ b/fpga/WarpLC.syr @@ -1,16 +1,16 @@ -Release 14.7 - xst P.20131013 (nt) +Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs +Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.08 secs +Total CPU time to Xst completion: 0.09 secs --> Reading design: WarpLC.prj @@ -81,12 +81,12 @@ Equivalent register Removal : YES ---- General Options Optimization Goal : Speed -Optimization Effort : 1 +Optimization Effort : 2 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes -Global Optimization : AllClockNets +Global Optimization : Inpad_To_Outpad Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO @@ -108,11 +108,19 @@ Cores Search Directories : {"ipcore_dir" } ========================================================================= * HDL Parsing * ========================================================================= -Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" into library work -Parsing module . -Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v" into library work -Parsing module . -Analyzing Verilog file "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" into library work +Parsing module . +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" into library work +Parsing module . +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" into library work +Parsing module . +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\SizeDecode.v" into library work +Parsing module . +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" into library work +Parsing module . +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" into library work +Parsing module . +Analyzing Verilog file "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" into library work Parsing module . ========================================================================= @@ -120,46 +128,62 @@ Parsing module . ========================================================================= Elaborating module . +WARNING:HDLCompiler:1016 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance -Elaborating module . +Elaborating module . -Elaborating module . +Elaborating module . Elaborating module . Elaborating module . -Elaborating module . -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to clkout1_unused ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to clkout2_unused ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to clkout3_unused ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to clkout4_unused ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to clkout5_unused ignored, since the identifier is never used -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to locked_unused ignored, since the identifier is never used +Elaborating module . +WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used +WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used Elaborating module . Elaborating module . Elaborating module . -WARNING:HDLCompiler:1127 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to CPUCLKr ignored, since the identifier is never used + +Elaborating module . +WARNING:HDLCompiler:1127 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_B ignored, since the identifier is never used + +Elaborating module . + +Elaborating module . +WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module remains a black box. +WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 33: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 7-bit. +WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 36: Size mismatch in connection of port . Formal port size is 5-bit while actual signal size is 7-bit. + +Elaborating module . +WARNING:HDLCompiler:1499 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module remains a black box. +WARNING:HDLCompiler:189 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 44: Size mismatch in connection of port . Formal port size is 7-bit while actual signal size is 5-bit. +WARNING:Xst:2972 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91. All outputs of instance of block are unconnected in block . Underlying logic will be removed. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . - Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v". + Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v". Set property "IOSTANDARD = LVCMOS33" for signal . Set property "IOBDELAY = NONE" for signal . + Set property "IOSTANDARD = LVCMOS33" for signal . + Set property "IOBDELAY = NONE" for signal . + Set property "IOSTANDARD = LVCMOS33" for signal . + Set property "DRIVE = 8" for signal . + Set property "SLEW = SLOW" for signal . Set property "IOSTANDARD = LVCMOS33" for signal . Set property "IOBDELAY = NONE" for signal . - Set property "IOSTANDARD = LVCMOS33" for signal . - Set property "IOBDELAY = NONE" for signal . - Set property "IOB = FALSE" for signal . - Set property "IOSTANDARD = LVCMOS33" for signal . - Set property "DRIVE = 24" for signal . - Set property "SLEW = FAST" for signal . + Set property "IOSTANDARD = LVCMOS33" for signal . + Set property "DRIVE = 24" for signal . + Set property "SLEW = FAST" for signal . Set property "IOSTANDARD = LVCMOS33" for signal . Set property "DRIVE = 24" for signal . Set property "SLEW = FAST" for signal . @@ -172,8 +196,6 @@ Synthesizing Unit . Set property "IOSTANDARD = LVCMOS33" for signal . Set property "DRIVE = 24" for signal . Set property "SLEW = FAST" for signal . - Set property "IOSTANDARD = LVCMOS33" for signal . - Set property "IOBDELAY = NONE" for signal . Set property "IOSTANDARD = LVCMOS33" for signal . Set property "IOBDELAY = NONE" for signal . Set property "IOSTANDARD = LVCMOS33" for signal . @@ -181,37 +203,44 @@ Synthesizing Unit . Set property "IOSTANDARD = LVCMOS33" for signal . Set property "DRIVE = 24" for signal . Set property "SLEW = FAST" for signal . -INFO:Xst:3210 - "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 79: Output port of the instance is unconnected or connected to loadless signal. - Found 32-bit register for signal . - Found 1-bit register for signal . - Found 32-bit comparator equal for signal created at line 92 +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91: Output port of the instance is unconnected or connected to loadless signal. Summary: - inferred 33 D-type flip-flop(s). - inferred 1 Comparator(s). + no macro. Unit synthesized. -Synthesizing Unit . - Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\CLKGEN.v". +Synthesizing Unit . + Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v". +INFO:Xst:3210 - "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port of the instance is unconnected or connected to loadless signal. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). -Unit synthesized. +Unit synthesized. -Synthesizing Unit . - Related source file is "C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v". +Synthesizing Unit . + Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v". Summary: no macro. -Unit synthesized. +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 21-bit comparator equal for signal created at line 28 + Summary: + inferred 1 Comparator(s). +Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics -# Registers : 3 - 1-bit register : 2 - 32-bit register : 1 +# Registers : 1 + 1-bit register : 1 # Comparators : 1 - 32-bit comparator equal : 1 + 21-bit comparator equal : 1 ========================================================================= @@ -219,15 +248,19 @@ Macro Statistics * Advanced HDL Synthesis * ========================================================================= +Reading core . +Reading core . +Loading core for timing and area information for instance . +Loading core for timing and area information for instance . ========================================================================= Advanced HDL Synthesis Report Macro Statistics -# Registers : 34 - Flip-Flops : 34 +# Registers : 1 + Flip-Flops : 1 # Comparators : 1 - 32-bit comparator equal : 1 + 21-bit comparator equal : 1 ========================================================================= @@ -238,11 +271,13 @@ INFO:Xst:1901 - Instance pll_base_inst in unit pll_base_inst of type PLL_BASE ha Optimizing unit ... -Optimizing unit ... +Optimizing unit ... + +Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 1. +Found area constraint ratio of 100 (+ 5) on block WarpLC, actual ratio is 0. Final Macro Processing ... @@ -250,8 +285,8 @@ Final Macro Processing ... Final Register Report Macro Statistics -# Registers : 34 - Flip-Flops : 34 +# Registers : 1 + Flip-Flops : 1 ========================================================================= @@ -274,23 +309,26 @@ Top Level Output File Name : WarpLC.ngc Primitive and Black Box Usage: ------------------------------ -# BELS : 29 -# GND : 1 +# BELS : 22 +# GND : 2 # INV : 3 -# LUT3 : 1 -# LUT4 : 1 -# LUT6 : 10 -# MUXCY : 12 +# LUT1 : 1 +# LUT6 : 7 +# MUXCY : 8 # VCC : 1 -# FlipFlops/Latches : 39 -# FD : 34 +# FlipFlops/Latches : 50 +# FD : 44 +# FDR : 1 # ODDR2 : 5 +# RAMS : 23 +# RAM32X1D : 22 +# RAMB8BWER : 1 # Clock Buffers : 2 # BUFG : 2 -# IO Buffers : 43 -# IBUF : 35 +# IO Buffers : 66 +# IBUF : 26 # IBUFG : 2 -# OBUF : 6 +# OBUF : 38 # Others : 2 # BUFIO2FB : 1 # PLL_ADV : 1 @@ -302,22 +340,26 @@ Selected Device : 6slx9ftg256-2 Slice Logic Utilization: - Number of Slice Registers: 39 out of 11440 0% - Number of Slice LUTs: 15 out of 5720 0% - Number used as Logic: 15 out of 5720 0% + Number of Slice Registers: 50 out of 11440 0% + Number of Slice LUTs: 55 out of 5720 0% + Number used as Logic: 11 out of 5720 0% + Number used as Memory: 44 out of 1440 3% + Number used as RAM: 44 Slice Logic Distribution: - Number of LUT Flip Flop pairs used: 52 - Number with an unused Flip Flop: 13 out of 52 25% - Number with an unused LUT: 37 out of 52 71% - Number of fully used LUT-FF pairs: 2 out of 52 3% - Number of unique control sets: 1 + Number of LUT Flip Flop pairs used: 105 + Number with an unused Flip Flop: 55 out of 105 52% + Number with an unused LUT: 50 out of 105 47% + Number of fully used LUT-FF pairs: 0 out of 105 0% + Number of unique control sets: 2 IO Utilization: - Number of IOs: 43 - Number of bonded IOBs: 43 out of 186 23% + Number of IOs: 75 + Number of bonded IOBs: 66 out of 186 35% Specific Feature Utilization: + Number of Block RAM/FIFO: 1 out of 32 3% + Number using Block RAM only: 1 Number of BUFG/BUFGCTRLs: 2 out of 16 12% Number of PLL_ADVs: 1 out of 2 50% @@ -339,12 +381,12 @@ NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. Clock Information: ------------------ -------------------------------------------------+------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | -------------------------------------------------+------------------------+-------+ -CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 | BUFG | 42 | -CLKGEN_inst/instance_name/pll_base_inst/CLKFBOUT| BUFG | 2 | -------------------------------------------------+------------------------+-------+ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +cg/pll/pll_base_inst/CLKOUT0 | BUFG | 76 | +cg/pll/pll_base_inst/CLKFBOUT | BUFG | 2 | +-----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- @@ -354,129 +396,141 @@ Timing Summary: --------------- Speed Grade: -2 - Minimum period: 2.580ns (Maximum Frequency: 387.597MHz) - Minimum input arrival time before clock: 3.547ns - Maximum output required time after clock: 4.118ns - Maximum combinational path delay: 1.328ns + Minimum period: 4.696ns (Maximum Frequency: 212.947MHz) + Minimum input arrival time before clock: 3.719ns + Maximum output required time after clock: 6.384ns + Maximum combinational path delay: 8.292ns Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= -Timing constraint: Default period analysis for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0' - Clock period: 2.580ns (frequency: 387.597MHz) - Total number of paths / destination ports: 35 / 4 +Timing constraint: Default period analysis for Clock 'cg/pll/pll_base_inst/CLKOUT0' + Clock period: 4.696ns (frequency: 212.947MHz) + Total number of paths / destination ports: 50 / 50 ------------------------------------------------------------------------- -Delay: 1.290ns (Levels of Logic = 0) - Source: CLKGEN_inst/CPUCLKr (FF) - Destination: CLKGEN_inst/FPUCLK_inst (FF) - Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising - Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 falling +Delay: 2.348ns (Levels of Logic = 1) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLK_inst (FF) + Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising + Destination Clock: cg/pll/pll_base_inst/CLKOUT0 falling - Data Path: CLKGEN_inst/CPUCLKr to CLKGEN_inst/FPUCLK_inst + Data Path: cg/CPUCLKr to cg/CPUCLK_inst Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FD:C->Q 3 0.525 0.765 CLKGEN_inst/CPUCLKr (CLKGEN_inst/CPUCLKr) - ODDR2:D1 0.000 CLKGEN_inst/FPUCLK_inst + FDR:C->Q 4 0.525 0.803 cg/CPUCLKr (cg/CPUCLKr) + INV:I->O 3 0.255 0.765 l2pre/CPUCLKr_INV_15_o1_INV_0 (l2pre/CPUCLKr_INV_15_o) + ODDR2:D1 0.000 cg/CPUCLK_inst ---------------------------------------- - Total 1.290ns (0.525ns logic, 0.765ns route) - (40.7% logic, 59.3% route) + Total 2.348ns (0.780ns logic, 1.568ns route) + (33.2% logic, 66.8% route) ========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0' - Total number of paths / destination ports: 67 / 33 +Timing constraint: Default OFFSET IN BEFORE for Clock 'cg/pll/pll_base_inst/CLKOUT0' + Total number of paths / destination ports: 225 / 137 ------------------------------------------------------------------------- -Offset: 3.547ns (Levels of Logic = 14) +Offset: 3.719ns (Levels of Logic = 3) Source: FSB_A<2> (PAD) - Destination: OUTt (FF) - Destination Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising + Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21 (FF) + Destination Clock: cg/pll/pll_base_inst/CLKOUT0 rising - Data Path: FSB_A<2> to OUTt + Data Path: FSB_A<2> to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 2 1.328 1.181 FSB_A_2_IBUF (FSB_A_2_IBUF) - LUT6:I0->O 1 0.254 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>) - MUXCY:S->O 1 0.215 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<0>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<1>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<2>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<4>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<5>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<6>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<8>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9> (Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<9>) - MUXCY:CI->O 1 0.023 0.000 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<10> (FSB_A[31]_AR[31]_equal_2_o) - MUXCY:CI->O 1 0.262 0.000 CPU_nAS_FSB_A[31]_AND_3_o1_cy (CPU_nAS_FSB_A[31]_AND_3_o) - FD:D 0.074 OUTt + IBUF:I->O 23 1.328 1.357 FSB_A_2_IBUF (FSB_A_2_IBUF) + begin scope: 'l2pre/Way0Tag:dpra<0>' + RAM32X1D:DPRA0->DPO 2 0.235 0.725 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>) + FD:D 0.074 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2 ---------------------------------------- - Total 3.547ns (2.366ns logic, 1.181ns route) - (66.7% logic, 33.3% route) + Total 3.719ns (1.637ns logic, 2.082ns route) + (44.0% logic, 56.0% route) ========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0' - Total number of paths / destination ports: 1 / 1 +Timing constraint: Default OFFSET OUT AFTER for Clock 'cg/pll/pll_base_inst/CLKOUT0' + Total number of paths / destination ports: 54 / 33 ------------------------------------------------------------------------- -Offset: 4.118ns (Levels of Logic = 1) - Source: OUTt (FF) - Destination: OUTt (PAD) - Source Clock: CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 rising +Offset: 6.384ns (Levels of Logic = 11) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (RAM) + Destination: CPU_nSTERM (PAD) + Source Clock: cg/pll/pll_base_inst/CLKOUT0 rising - Data Path: OUTt to OUTt + Data Path: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 to CPU_nSTERM Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - FD:C->Q 1 0.525 0.681 OUTt (OUTt_OBUF) - OBUF:I->O 2.912 OUTt_OBUF (OUTt) + RAM32X1D:WCLK->DPO 2 1.012 0.954 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>) + end scope: 'l2pre/Way0Tag:dpo<2>' + LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>) + MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6> (l2pre/RDTag[20]_RDATag[20]_equal_5_o) + MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF) + OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM) ---------------------------------------- - Total 4.118ns (3.437ns logic, 0.681ns route) - (83.5% logic, 16.5% route) + Total 6.384ns (4.749ns logic, 1.635ns route) + (74.4% logic, 25.6% route) ========================================================================= Timing constraint: Default path analysis - Total number of paths / destination ports: 1 / 1 + Total number of paths / destination ports: 132 / 2 ------------------------------------------------------------------------- -Delay: 1.328ns (Levels of Logic = 1) - Source: CLKFB_IN (PAD) - Destination: CLKGEN_inst/instance_name/clkfb_bufio2fb:I (PAD) +Delay: 8.292ns (Levels of Logic = 13) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) - Data Path: CLKFB_IN to CLKGEN_inst/instance_name/clkfb_bufio2fb:I + Data Path: FSB_A<2> to CPU_nSTERM Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUFG:I->O 0 1.328 0.000 CLKGEN_inst/instance_name/clkfb_ibufg (CLKGEN_inst/instance_name/clkfb_ibuf2bufio2fb) - BUFIO2FB:I 0.000 CLKGEN_inst/instance_name/clkfb_bufio2fb + IBUF:I->O 23 1.328 1.357 FSB_A_2_IBUF (FSB_A_2_IBUF) + begin scope: 'l2pre/Way0Tag:dpra<0>' + RAM32X1D:DPRA0->DPO 2 0.235 0.954 U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3 (dpo<2>) + end scope: 'l2pre/Way0Tag:dpo<2>' + LUT6:I3->O 1 0.235 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>) + MUXCY:S->O 1 0.215 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<0>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<1>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<2>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<4>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5> (l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<5>) + MUXCY:CI->O 1 0.023 0.000 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6> (l2pre/RDTag[20]_RDATag[20]_equal_5_o) + MUXCY:CI->O 1 0.235 0.681 CPU_nSTERM1_cy (CPU_nSTERM_OBUF) + OBUF:I->O 2.912 CPU_nSTERM_OBUF (CPU_nSTERM) ---------------------------------------- - Total 1.328ns (1.328ns logic, 0.000ns route) - (100.0% logic, 0.0% route) + Total 8.292ns (5.300ns logic, 2.992ns route) + (63.9% logic, 36.1% route) ========================================================================= Cross Clock Domains Report: -------------------------- -Clock to Setup on destination clock CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0 ------------------------------------------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ------------------------------------------------+---------+---------+---------+---------+ -CLKGEN_inst/instance_name/pll_base_inst/CLKOUT0| 2.454| | 1.290| | ------------------------------------------------+---------+---------+---------+---------+ +Clock to Setup on destination clock cg/pll/pll_base_inst/CLKOUT0 +----------------------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------------------+---------+---------+---------+---------+ +cg/pll/pll_base_inst/CLKOUT0| 2.568| | 2.348| | +----------------------------+---------+---------+---------+---------+ ========================================================================= -Total REAL time to Xst completion: 2.00 secs -Total CPU time to Xst completion: 2.72 secs +Total REAL time to Xst completion: 6.00 secs +Total CPU time to Xst completion: 6.67 secs --> -Total memory usage is 225148 kilobytes +Total memory usage is 258804 kilobytes Number of errors : 0 ( 0 filtered) -Number of warnings : 7 ( 0 filtered) -Number of infos : 2 ( 0 filtered) +Number of warnings : 17 ( 0 filtered) +Number of infos : 3 ( 0 filtered) diff --git a/fpga/WarpLC.twr b/fpga/WarpLC.twr index ed881bd..acd5657 100644 --- a/fpga/WarpLC.twr +++ b/fpga/WarpLC.twr @@ -1,32 +1,33 @@ -------------------------------------------------------------------------------- -Release 14.7 Trace (nt) +Release 14.7 Trace (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n -3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 +-timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o +WarpLC.twr WarpLC.pcf -ucf PLL.ucf Design file: WarpLC.ncd Physical constraint file: WarpLC.pcf Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13) Report level: verbose report + unconstrained path report, limited to 1000 items per endpoint, 3 endpoints per path report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- +INFO:Timing:3386 - Intersecting Constraints found and resolved. For more + information, see the TSI report. Please consult the Xilinx Command Line + Tools User Guide for information on generating a TSI report. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). -INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths - option. All paths that are not constrained will be reported in the - unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ -Timing constraint: NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH -50%; +Timing constraint: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints @@ -34,414 +35,209 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61 Minimum period is 10.000ns. -------------------------------------------------------------------------------- -Component Switching Limit Checks: NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; +Component Switching Limit Checks: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 13.948ns (period - min period limit) + Period: 15.000ns + Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax)) + Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0 + Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0 + Location pin: PLL_ADV_X0Y1.CLKOUT0 + Clock network: cg/pll/clkout0 -------------------------------------------------------------------------------- Slack: 20.000ns (period - (min low pulse limit / (low pulse / period))) Period: 30.000ns Low pulse: 15.000ns Low pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50) - Physical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Logical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKIN1 + Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 + Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 Location pin: PLL_ADV_X0Y1.CLKIN2 - Clock network: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK -------------------------------------------------------------------------------- Slack: 20.000ns (period - (min high pulse limit / (high pulse / period))) Period: 30.000ns High pulse: 15.000ns High pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50) - Physical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Logical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKIN1 + Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 + Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 Location pin: PLL_ADV_X0Y1.CLKIN2 - Clock network: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK --------------------------------------------------------------------------------- -Slack: 22.630ns (max period limit - period) - Period: 30.000ns - Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKIN) - Physical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Logical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Location pin: PLL_ADV_X0Y1.CLKIN2 - Clock network: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK -------------------------------------------------------------------------------- ================================================================================ -Timing constraint: PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" -derived from NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; -divided by 2.00 to 15 nS -For more information, see Period Analysis in the Timing Closure User Guide (UG612). +Timing constraint: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP +"CPU_nSTERM" 15 ns; +For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). - 35 paths analyzed, 12 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) - Minimum period is 2.700ns. + 22 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Maximum delay is 7.879ns. -------------------------------------------------------------------------------- -Paths for end point OUTt (SLICE_X0Y21.CIN), 24 paths +Paths for end point CPU_nSTERM (D12.PAD), 22 paths -------------------------------------------------------------------------------- -Slack (setup path): 12.300ns (requirement - (data path - clock path skew + uncertainty)) - Source: AR_5 (FF) - Destination: OUTt (FF) +Slack (slowest paths): 7.121ns (requirement - data path) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (RAM) + Destination: CPU_nSTERM (PAD) Requirement: 15.000ns - Data Path Delay: 2.534ns (Levels of Logic = 3) - Clock Path Skew: -0.018ns (0.188 - 0.206) + Data Path Delay: 7.879ns (Levels of Logic = 2) Source Clock: FSBCLK rising at 0.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.148ns - Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: AR_5 to OUTt + Maximum Data Path at Slow Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP to CPU_nSTERM Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X0Y18.BQ Tcko 0.525 AR<7> - AR_5 - SLICE_X0Y19.B1 net (fanout=1) 1.129 AR<5> - SLICE_X0Y19.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt + SLICE_X16Y51.AMUX Tshcko 1.081 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM ------------------------------------------------- --------------------------- - Total 2.534ns (1.399ns logic, 1.135ns route) - (55.2% logic, 44.8% route) + Total 7.879ns (3.711ns logic, 4.168ns route) + (47.1% logic, 52.9% route) -------------------------------------------------------------------------------- -Slack (setup path): 12.375ns (requirement - (data path - clock path skew + uncertainty)) - Source: AR_9 (FF) - Destination: OUTt (FF) +Slack (slowest paths): 7.227ns (requirement - data path) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (RAM) + Destination: CPU_nSTERM (PAD) Requirement: 15.000ns - Data Path Delay: 2.458ns (Levels of Logic = 3) - Clock Path Skew: -0.019ns (0.188 - 0.207) + Data Path Delay: 7.773ns (Levels of Logic = 2) Source Clock: FSBCLK rising at 0.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.148ns - Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: AR_9 to OUTt + Maximum Data Path at Slow Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP to CPU_nSTERM Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X0Y17.BQ Tcko 0.525 AR<11> - AR_9 - SLICE_X0Y19.D1 net (fanout=1) 1.224 AR<9> - SLICE_X0Y19.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt + SLICE_X16Y51.A Tshcko 1.012 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM ------------------------------------------------- --------------------------- - Total 2.458ns (1.228ns logic, 1.230ns route) + Total 7.773ns (3.618ns logic, 4.155ns route) + (46.5% logic, 53.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 7.243ns (requirement - data path) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP (RAM) + Destination: CPU_nSTERM (PAD) + Requirement: 15.000ns + Data Path Delay: 7.757ns (Levels of Logic = 3) + Source Clock: FSBCLK rising at 0.000ns + + Maximum Data Path at Slow Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y50.BMUX Tshcko 1.131 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 7.757ns (3.828ns logic, 3.929ns route) + (49.3% logic, 50.7% route) + +-------------------------------------------------------------------------------- +Hold Paths: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns; +-------------------------------------------------------------------------------- + +Paths for end point CPU_nSTERM (D12.PAD), 22 paths +-------------------------------------------------------------------------------- +Delay (fastest path): 3.026ns (data path) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP (RAM) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 3.026ns (Levels of Logic = 2) + Source Clock: FSBCLK rising at 0.000ns + + Minimum Data Path at Fast Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y51.AMUX Tshcko 0.490 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + SLICE_X22Y51.C6 net (fanout=1) 0.129 l2pre/n0023<18> + SLICE_X22Y51.DMUX Topcd 0.307 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 1.401 CPU_nSTERM_OBUF + D12.PAD Tioop 0.699 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 3.026ns (1.496ns logic, 1.530ns route) + (49.4% logic, 50.6% route) +-------------------------------------------------------------------------------- +Delay (fastest path): 3.039ns (data path) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP (RAM) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 3.039ns (Levels of Logic = 2) + Source Clock: FSBCLK rising at 0.000ns + + Minimum Data Path at Fast Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y51.B Tshcko 0.449 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + SLICE_X22Y51.B6 net (fanout=1) 0.119 l2pre/n0023<15> + SLICE_X22Y51.DMUX Topbd 0.371 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 1.401 CPU_nSTERM_OBUF + D12.PAD Tioop 0.699 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 3.039ns (1.519ns logic, 1.520ns route) (50.0% logic, 50.0% route) - -------------------------------------------------------------------------------- -Slack (setup path): 12.408ns (requirement - (data path - clock path skew + uncertainty)) - Source: AR_4 (FF) - Destination: OUTt (FF) - Requirement: 15.000ns - Data Path Delay: 2.426ns (Levels of Logic = 3) - Clock Path Skew: -0.018ns (0.188 - 0.206) +Delay (fastest path): 3.074ns (data path) + Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP (RAM) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 3.074ns (Levels of Logic = 2) Source Clock: FSBCLK rising at 0.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.148ns - Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: AR_4 to OUTt + Minimum Data Path at Fast Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP to CPU_nSTERM Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X0Y18.AQ Tcko 0.525 AR<7> - AR_4 - SLICE_X0Y19.B5 net (fanout=1) 1.021 AR<4> - SLICE_X0Y19.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt + SLICE_X20Y51.BMUX Tshcko 0.495 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + SLICE_X22Y51.C5 net (fanout=1) 0.172 l2pre/n0023<19> + SLICE_X22Y51.DMUX Topcd 0.307 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 1.401 CPU_nSTERM_OBUF + D12.PAD Tioop 0.699 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM ------------------------------------------------- --------------------------- - Total 2.426ns (1.399ns logic, 1.027ns route) - (57.7% logic, 42.3% route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B3), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 12.492ns (requirement - (data path - clock path skew + uncertainty)) - Source: AR_27 (FF) - Destination: OUTt (FF) - Requirement: 15.000ns - Data Path Delay: 2.348ns (Levels of Logic = 1) - Clock Path Skew: -0.012ns (0.333 - 0.345) - Source Clock: FSBCLK rising at 0.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.148ns - - Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: AR_27 to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X0Y24.DQ Tcko 0.525 AR<27> - AR_27 - SLICE_X0Y21.B3 net (fanout=1) 1.135 AR<27> - SLICE_X0Y21.CLK Tas 0.688 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.348ns (1.213ns logic, 1.135ns route) - (51.7% logic, 48.3% route) - --------------------------------------------------------------------------------- - -Paths for end point CLKGEN_inst/FPUCLK_inst (OLOGIC_X0Y47.D2), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 12.531ns (requirement - (data path - clock path skew + uncertainty)) - Source: CLKGEN_inst/CPUCLKr (FF) - Destination: CLKGEN_inst/FPUCLK_inst (FF) - Requirement: 15.000ns - Data Path Delay: 2.853ns (Levels of Logic = 0) - Clock Path Skew: 0.532ns (0.882 - 0.350) - Source Clock: FSBCLK rising at 0.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.148ns - - Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: CLKGEN_inst/CPUCLKr to CLKGEN_inst/FPUCLK_inst - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X0Y53.DQ Tcko 0.525 CLKGEN_inst/CPUCLKr - CLKGEN_inst/CPUCLKr - OLOGIC_X0Y47.D2 net (fanout=3) 1.497 CLKGEN_inst/CPUCLKr - OLOGIC_X0Y47.CLK0 Todck 0.831 FPUCLK_OBUF - CLKGEN_inst/FPUCLK_inst - ------------------------------------------------- --------------------------- - Total 2.853ns (1.356ns logic, 1.497ns route) - (47.5% logic, 52.5% route) - --------------------------------------------------------------------------------- - -Hold Paths: PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" derived from - NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; - divided by 2.00 to 15 nS - --------------------------------------------------------------------------------- - -Paths for end point CLKGEN_inst/CPUCLKr (SLICE_X0Y53.D6), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 0.457ns (requirement - (clock path skew + uncertainty - data path)) - Source: CLKGEN_inst/CPUCLKr (FF) - Destination: CLKGEN_inst/CPUCLKr (FF) - Requirement: 0.000ns - Data Path Delay: 0.457ns (Levels of Logic = 1) - Clock Path Skew: 0.000ns - Source Clock: FSBCLK rising at 15.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: CLKGEN_inst/CPUCLKr to CLKGEN_inst/CPUCLKr - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X0Y53.DQ Tcko 0.234 CLKGEN_inst/CPUCLKr - CLKGEN_inst/CPUCLKr - SLICE_X0Y53.D6 net (fanout=3) 0.026 CLKGEN_inst/CPUCLKr - SLICE_X0Y53.CLK Tah (-Th) -0.197 CLKGEN_inst/CPUCLKr - CLKGEN_inst/CPUCLKr_rstpot1_INV_0 - CLKGEN_inst/CPUCLKr - ------------------------------------------------- --------------------------- - Total 0.457ns (0.431ns logic, 0.026ns route) - (94.3% logic, 5.7% route) - --------------------------------------------------------------------------------- - -Paths for end point CLKGEN_inst/FPUCLK_inst (OLOGIC_X0Y47.D1), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 0.582ns (requirement - (clock path skew + uncertainty - data path)) - Source: CLKGEN_inst/CPUCLKr (FF) - Destination: CLKGEN_inst/FPUCLK_inst (FF) - Requirement: 0.000ns - Data Path Delay: 0.838ns (Levels of Logic = 0) - Clock Path Skew: 0.256ns (0.366 - 0.110) - Source Clock: FSBCLK rising at 15.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: CLKGEN_inst/CPUCLKr to CLKGEN_inst/FPUCLK_inst - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X0Y53.DQ Tcko 0.234 CLKGEN_inst/CPUCLKr - CLKGEN_inst/CPUCLKr - OLOGIC_X0Y47.D1 net (fanout=3) 0.274 CLKGEN_inst/CPUCLKr - OLOGIC_X0Y47.CLK0 Tockd (-Th) -0.330 FPUCLK_OBUF - CLKGEN_inst/FPUCLK_inst - ------------------------------------------------- --------------------------- - Total 0.838ns (0.564ns logic, 0.274ns route) - (67.3% logic, 32.7% route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 24 paths --------------------------------------------------------------------------------- -Slack (hold path): 0.691ns (requirement - (clock path skew + uncertainty - data path)) - Source: AR_13 (FF) - Destination: OUTt (FF) - Requirement: 0.000ns - Data Path Delay: 0.690ns (Levels of Logic = 2) - Clock Path Skew: -0.001ns (0.036 - 0.037) - Source Clock: FSBCLK rising at 15.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: AR_13 to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X1Y20.BQ Tcko 0.198 AR<15> - AR_13 - SLICE_X0Y20.A5 net (fanout=1) 0.070 AR<13> - SLICE_X0Y20.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 0.690ns (0.619ns logic, 0.071ns route) - (89.7% logic, 10.3% route) - --------------------------------------------------------------------------------- -Slack (hold path): 0.781ns (requirement - (clock path skew + uncertainty - data path)) - Source: AR_6 (FF) - Destination: OUTt (FF) - Requirement: 0.000ns - Data Path Delay: 0.776ns (Levels of Logic = 3) - Clock Path Skew: -0.005ns (0.036 - 0.041) - Source Clock: FSBCLK rising at 15.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: AR_6 to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X0Y18.CQ Tcko 0.234 AR<7> - AR_6 - SLICE_X0Y19.C5 net (fanout=1) 0.156 AR<6> - SLICE_X0Y19.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 0.776ns (0.618ns logic, 0.158ns route) - (79.6% logic, 20.4% route) - --------------------------------------------------------------------------------- -Slack (hold path): 0.863ns (requirement - (clock path skew + uncertainty - data path)) - Source: AR_15 (FF) - Destination: OUTt (FF) - Requirement: 0.000ns - Data Path Delay: 0.862ns (Levels of Logic = 2) - Clock Path Skew: -0.001ns (0.036 - 0.037) - Source Clock: FSBCLK rising at 15.000ns - Destination Clock: FSBCLK rising at 15.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: AR_15 to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X1Y20.DQ Tcko 0.198 AR<15> - AR_15 - SLICE_X0Y20.B1 net (fanout=1) 0.250 AR<15> - SLICE_X0Y20.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 0.862ns (0.611ns logic, 0.251ns route) - (70.9% logic, 29.1% route) - --------------------------------------------------------------------------------- - -Component Switching Limit Checks: PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" derived from - NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; - divided by 2.00 to 15 nS - --------------------------------------------------------------------------------- -Slack: 12.334ns (period - min period limit) - Period: 15.000ns - Min period limit: 2.666ns (375.094MHz) (Tbcper_I) - Physical resource: CLKGEN_inst/instance_name/clkout1_buf/I0 - Logical resource: CLKGEN_inst/instance_name/clkout1_buf/I0 - Location pin: BUFGMUX_X2Y3.I0 - Clock network: CLKGEN_inst/instance_name/clkout0 --------------------------------------------------------------------------------- -Slack: 12.751ns (period - min period limit) - Period: 15.000ns - Min period limit: 2.249ns (444.642MHz) (Tockper) - Physical resource: RAMCLK0_OBUF/CLK0 - Logical resource: CLKGEN_inst/RAMCLK0_inst/CK0 - Location pin: OLOGIC_X0Y44.CLK0 - Clock network: FSBCLK --------------------------------------------------------------------------------- -Slack: 12.751ns (period - min period limit) - Period: 15.000ns - Min period limit: 2.249ns (444.642MHz) (Tockper) - Physical resource: RAMCLK1_OBUF/CLK0 - Logical resource: CLKGEN_inst/RAMCLK1_inst/CK0 - Location pin: OLOGIC_X0Y45.CLK0 - Clock network: FSBCLK + Total 3.074ns (1.501ns logic, 1.573ns route) + (48.8% logic, 51.2% route) -------------------------------------------------------------------------------- ================================================================================ -Timing constraint: PERIOD analysis for net "CLKGEN_inst/instance_name/clkfbout" -derived from NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; -duty cycle corrected to 30 nS HIGH 15 nS +Timing constraint: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" +TS_CLKIN HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints @@ -449,8097 +245,5260 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61 Minimum period is 2.666ns. -------------------------------------------------------------------------------- -Component Switching Limit Checks: PERIOD analysis for net "CLKGEN_inst/instance_name/clkfbout" derived from - NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; - duty cycle corrected to 30 nS HIGH 15 nS - --------------------------------------------------------------------------------- -Slack: 22.630ns (max period limit - period) - Period: 30.000ns - Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKFB) - Physical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKFBOUT - Logical resource: CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV/CLKFBOUT - Location pin: PLL_ADV_X0Y1.CLKFBOUT - Clock network: CLKGEN_inst/instance_name/clkfbout +Component Switching Limit Checks: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%; -------------------------------------------------------------------------------- Slack: 27.334ns (period - min period limit) Period: 30.000ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) - Physical resource: CLKGEN_inst/instance_name/clkfbout_bufg/I0 - Logical resource: CLKGEN_inst/instance_name/clkfbout_bufg/I0 - Location pin: BUFGMUX_X3Y13.I0 - Clock network: CLKGEN_inst/instance_name/clkfbout + Physical resource: cg/pll/clkfbout_bufg/I0 + Logical resource: cg/pll/clkfbout_bufg/I0 + Location pin: BUFGMUX_X2Y3.I0 + Clock network: cg/pll/clkfbout -------------------------------------------------------------------------------- Slack: 27.751ns (period - min period limit) Period: 30.000ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: CLKFB_OUT_OBUF/CLK0 - Logical resource: CLKGEN_inst/instance_name/clkfbout_oddr/CK0 - Location pin: OLOGIC_X0Y49.CLK0 - Clock network: CLKGEN_inst/instance_name/clkfb_bufg_out + Logical resource: cg/pll/clkfbout_oddr/CK0 + Location pin: OLOGIC_X1Y62.CLK0 + Clock network: cg/pll/clkfb_bufg_out +-------------------------------------------------------------------------------- +Slack: 27.960ns (period - min period limit) + Period: 30.000ns + Min period limit: 2.040ns (490.196MHz) (Tockper) + Physical resource: CLKFB_OUT_OBUF/CLK1 + Logical resource: cg/pll/clkfbout_oddr/CK1 + Location pin: OLOGIC_X1Y62.CLK1 + Clock network: cg/pll/clkfb_bufg_out -------------------------------------------------------------------------------- ================================================================================ -Timing constraint: COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). +Timing constraint: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN +/ 2 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.247ns. + 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 3.689ns. -------------------------------------------------------------------------------- -Paths for end point OUTt (SLICE_X0Y21.C5), 1 path +Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y61.D1), 1 path -------------------------------------------------------------------------------- -Slack (setup path): 1.753ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<31> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.930ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<31> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L4.I Tiopi 1.557 FSB_A<31> - FSB_A<31> - FSB_A_31_IBUF - ProtoComp10.IMUX.13 - SLICE_X0Y21.C5 net (fanout=2) 3.840 FSB_A_31_IBUF - SLICE_X0Y21.CLK Tas 0.533 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.930ns (2.090ns logic, 3.840ns route) - (35.2% logic, 64.8% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_31 (SLICE_X0Y22.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.593ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<31> (PAD) - Destination: AR_31 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.087ns (Levels of Logic = 1) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<31> to AR_31 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L4.I Tiopi 1.557 FSB_A<31> - FSB_A<31> - FSB_A_31_IBUF - ProtoComp10.IMUX.13 - SLICE_X0Y22.DX net (fanout=2) 3.445 FSB_A_31_IBUF - SLICE_X0Y22.CLK Tdick 0.085 AR<31> - AR_31 - ------------------------------------------------- --------------------------- - Total 5.087ns (1.642ns logic, 3.445ns route) - (32.3% logic, 67.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_31 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_31 (SLICE_X0Y22.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.707ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<31> (PAD) - Destination: AR_31 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.421ns (Levels of Logic = 1) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<31> to AR_31 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L4.I Tiopi 0.763 FSB_A<31> - FSB_A<31> - FSB_A_31_IBUF - ProtoComp10.IMUX.13 - SLICE_X0Y22.DX net (fanout=2) 1.617 FSB_A_31_IBUF - SLICE_X0Y22.CLK Tckdi (-Th) -0.041 AR<31> - AR_31 - ------------------------------------------------- --------------------------- - Total 2.421ns (0.804ns logic, 1.617ns route) - (33.2% logic, 66.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_31 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.C5), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.160ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<31> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.877ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<31> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L4.I Tiopi 0.763 FSB_A<31> - FSB_A<31> - FSB_A_31_IBUF - ProtoComp10.IMUX.13 - SLICE_X0Y21.C5 net (fanout=2) 1.794 FSB_A_31_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.320 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.877ns (1.083ns logic, 1.794ns route) - (37.6% logic, 62.4% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.847ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.C4), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.153ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<30> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.530ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<30> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H5.I Tiopi 1.557 FSB_A<30> - FSB_A<30> - FSB_A_30_IBUF - ProtoComp10.IMUX.10 - SLICE_X0Y21.C4 net (fanout=2) 3.440 FSB_A_30_IBUF - SLICE_X0Y21.CLK Tas 0.533 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.530ns (2.090ns logic, 3.440ns route) - (37.8% logic, 62.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_30 (SLICE_X0Y22.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.628ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<30> (PAD) - Destination: AR_30 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.052ns (Levels of Logic = 1) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<30> to AR_30 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H5.I Tiopi 1.557 FSB_A<30> - FSB_A<30> - FSB_A_30_IBUF - ProtoComp10.IMUX.10 - SLICE_X0Y22.CX net (fanout=2) 3.410 FSB_A_30_IBUF - SLICE_X0Y22.CLK Tdick 0.085 AR<31> - AR_30 - ------------------------------------------------- --------------------------- - Total 5.052ns (1.642ns logic, 3.410ns route) - (32.5% logic, 67.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_30 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_30 (SLICE_X0Y22.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.725ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<30> (PAD) - Destination: AR_30 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.439ns (Levels of Logic = 1) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<30> to AR_30 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H5.I Tiopi 0.763 FSB_A<30> - FSB_A<30> - FSB_A_30_IBUF - ProtoComp10.IMUX.10 - SLICE_X0Y22.CX net (fanout=2) 1.635 FSB_A_30_IBUF - SLICE_X0Y22.CLK Tckdi (-Th) -0.041 AR<31> - AR_30 - ------------------------------------------------- --------------------------- - Total 2.439ns (0.804ns logic, 1.635ns route) - (33.0% logic, 67.0% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_30 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.C4), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.050ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<30> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.767ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<30> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H5.I Tiopi 0.763 FSB_A<30> - FSB_A<30> - FSB_A_30_IBUF - ProtoComp10.IMUX.10 - SLICE_X0Y21.C4 net (fanout=2) 1.684 FSB_A_30_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.320 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.767ns (1.083ns logic, 1.684ns route) - (39.1% logic, 60.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.864ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B4), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.136ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<29> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.547ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<29> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G1.I Tiopi 1.557 FSB_A<29> - FSB_A<29> - FSB_A_29_IBUF - ProtoComp10.IMUX.24 - SLICE_X0Y21.B4 net (fanout=2) 3.302 FSB_A_29_IBUF - SLICE_X0Y21.CLK Tas 0.688 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.547ns (2.245ns logic, 3.302ns route) - (40.5% logic, 59.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_29 (SLICE_X0Y22.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.127ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<29> (PAD) - Destination: AR_29 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.553ns (Levels of Logic = 1) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<29> to AR_29 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G1.I Tiopi 1.557 FSB_A<29> - FSB_A<29> - FSB_A_29_IBUF - ProtoComp10.IMUX.24 - SLICE_X0Y22.BX net (fanout=2) 2.911 FSB_A_29_IBUF - SLICE_X0Y22.CLK Tdick 0.085 AR<31> - AR_29 - ------------------------------------------------- --------------------------- - Total 4.553ns (1.642ns logic, 2.911ns route) - (36.1% logic, 63.9% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_29 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_29 (SLICE_X0Y22.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.448ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<29> (PAD) - Destination: AR_29 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.162ns (Levels of Logic = 1) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<29> to AR_29 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G1.I Tiopi 0.763 FSB_A<29> - FSB_A<29> - FSB_A_29_IBUF - ProtoComp10.IMUX.24 - SLICE_X0Y22.BX net (fanout=2) 1.358 FSB_A_29_IBUF - SLICE_X0Y22.CLK Tckdi (-Th) -0.041 AR<31> - AR_29 - ------------------------------------------------- --------------------------- - Total 2.162ns (0.804ns logic, 1.358ns route) - (37.2% logic, 62.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_29 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B4), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.001ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<29> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.718ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<29> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G1.I Tiopi 0.763 FSB_A<29> - FSB_A<29> - FSB_A_29_IBUF - ProtoComp10.IMUX.24 - SLICE_X0Y21.B4 net (fanout=2) 1.574 FSB_A_29_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.381 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.718ns (1.144ns logic, 1.574ns route) - (42.1% logic, 57.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.261ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B2), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.739ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<28> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.944ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<28> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K3.I Tiopi 1.557 FSB_A<28> - FSB_A<28> - FSB_A_28_IBUF - ProtoComp10.IMUX.23 - SLICE_X0Y21.B2 net (fanout=2) 3.699 FSB_A_28_IBUF - SLICE_X0Y21.CLK Tas 0.688 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.944ns (2.245ns logic, 3.699ns route) - (37.8% logic, 62.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_28 (SLICE_X0Y22.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.044ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<28> (PAD) - Destination: AR_28 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.636ns (Levels of Logic = 1) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<28> to AR_28 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K3.I Tiopi 1.557 FSB_A<28> - FSB_A<28> - FSB_A_28_IBUF - ProtoComp10.IMUX.23 - SLICE_X0Y22.AX net (fanout=2) 2.994 FSB_A_28_IBUF - SLICE_X0Y22.CLK Tdick 0.085 AR<31> - AR_28 - ------------------------------------------------- --------------------------- - Total 4.636ns (1.642ns logic, 2.994ns route) - (35.4% logic, 64.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_28 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_28 (SLICE_X0Y22.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.510ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<28> (PAD) - Destination: AR_28 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.224ns (Levels of Logic = 1) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<28> to AR_28 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K3.I Tiopi 0.763 FSB_A<28> - FSB_A<28> - FSB_A_28_IBUF - ProtoComp10.IMUX.23 - SLICE_X0Y22.AX net (fanout=2) 1.420 FSB_A_28_IBUF - SLICE_X0Y22.CLK Tckdi (-Th) -0.041 AR<31> - AR_28 - ------------------------------------------------- --------------------------- - Total 2.224ns (0.804ns logic, 1.420ns route) - (36.2% logic, 63.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_28 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B2), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.203ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<28> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.920ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<28> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K3.I Tiopi 0.763 FSB_A<28> - FSB_A<28> - FSB_A_28_IBUF - ProtoComp10.IMUX.23 - SLICE_X0Y21.B2 net (fanout=2) 1.776 FSB_A_28_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.381 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.920ns (1.144ns logic, 1.776ns route) - (39.2% logic, 60.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.334ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B6), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.666ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<27> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 6.017ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<27> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E1.I Tiopi 1.557 FSB_A<27> - FSB_A<27> - FSB_A_27_IBUF - ProtoComp10.IMUX.22 - SLICE_X0Y21.B6 net (fanout=2) 3.772 FSB_A_27_IBUF - SLICE_X0Y21.CLK Tas 0.688 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 6.017ns (2.245ns logic, 3.772ns route) - (37.3% logic, 62.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_27 (SLICE_X0Y24.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.639ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<27> (PAD) - Destination: AR_27 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.039ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<27> to AR_27 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E1.I Tiopi 1.557 FSB_A<27> - FSB_A<27> - FSB_A_27_IBUF - ProtoComp10.IMUX.22 - SLICE_X0Y24.DX net (fanout=2) 3.397 FSB_A_27_IBUF - SLICE_X0Y24.CLK Tdick 0.085 AR<27> - AR_27 - ------------------------------------------------- --------------------------- - Total 5.039ns (1.642ns logic, 3.397ns route) - (32.6% logic, 67.4% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_27 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_27 (SLICE_X0Y24.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.698ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<27> (PAD) - Destination: AR_27 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.410ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<27> to AR_27 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E1.I Tiopi 0.763 FSB_A<27> - FSB_A<27> - FSB_A_27_IBUF - ProtoComp10.IMUX.22 - SLICE_X0Y24.DX net (fanout=2) 1.606 FSB_A_27_IBUF - SLICE_X0Y24.CLK Tckdi (-Th) -0.041 AR<27> - AR_27 - ------------------------------------------------- --------------------------- - Total 2.410ns (0.804ns logic, 1.606ns route) - (33.4% logic, 66.6% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_27 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.B6), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.280ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<27> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.997ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<27> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E1.I Tiopi 0.763 FSB_A<27> - FSB_A<27> - FSB_A_27_IBUF - ProtoComp10.IMUX.22 - SLICE_X0Y21.B6 net (fanout=2) 1.853 FSB_A_27_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.381 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.997ns (1.144ns logic, 1.853ns route) - (38.2% logic, 61.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.657ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.A3), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.343ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<26> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.340ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<26> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H1.I Tiopi 1.557 FSB_A<26> - FSB_A<26> - FSB_A_26_IBUF - ProtoComp10.IMUX.19 - SLICE_X0Y21.A3 net (fanout=2) 3.104 FSB_A_26_IBUF - SLICE_X0Y21.CLK Tas 0.679 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.340ns (2.236ns logic, 3.104ns route) - (41.9% logic, 58.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_26 (SLICE_X0Y24.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.412ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<26> (PAD) - Destination: AR_26 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.266ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<26> to AR_26 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H1.I Tiopi 1.557 FSB_A<26> - FSB_A<26> - FSB_A_26_IBUF - ProtoComp10.IMUX.19 - SLICE_X0Y24.CX net (fanout=2) 2.624 FSB_A_26_IBUF - SLICE_X0Y24.CLK Tdick 0.085 AR<27> - AR_26 - ------------------------------------------------- --------------------------- - Total 4.266ns (1.642ns logic, 2.624ns route) - (38.5% logic, 61.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_26 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_26 (SLICE_X0Y24.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.292ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<26> (PAD) - Destination: AR_26 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.004ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<26> to AR_26 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H1.I Tiopi 0.763 FSB_A<26> - FSB_A<26> - FSB_A_26_IBUF - ProtoComp10.IMUX.19 - SLICE_X0Y24.CX net (fanout=2) 1.200 FSB_A_26_IBUF - SLICE_X0Y24.CLK Tckdi (-Th) -0.041 AR<27> - AR_26 - ------------------------------------------------- --------------------------- - Total 2.004ns (0.804ns logic, 1.200ns route) - (40.1% logic, 59.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_26 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.A3), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.901ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<26> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.618ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<26> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H1.I Tiopi 0.763 FSB_A<26> - FSB_A<26> - FSB_A_26_IBUF - ProtoComp10.IMUX.19 - SLICE_X0Y21.A3 net (fanout=2) 1.466 FSB_A_26_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.389 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.618ns (1.152ns logic, 1.466ns route) - (44.0% logic, 56.0% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.883ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.A2), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.117ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<25> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.566ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<25> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H2.I Tiopi 1.557 FSB_A<25> - FSB_A<25> - FSB_A_25_IBUF - ProtoComp10.IMUX.17 - SLICE_X0Y21.A2 net (fanout=2) 3.330 FSB_A_25_IBUF - SLICE_X0Y21.CLK Tas 0.679 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.566ns (2.236ns logic, 3.330ns route) - (40.2% logic, 59.8% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_25 (SLICE_X0Y24.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.388ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<25> (PAD) - Destination: AR_25 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.290ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<25> to AR_25 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H2.I Tiopi 1.557 FSB_A<25> - FSB_A<25> - FSB_A_25_IBUF - ProtoComp10.IMUX.17 - SLICE_X0Y24.BX net (fanout=2) 2.648 FSB_A_25_IBUF - SLICE_X0Y24.CLK Tdick 0.085 AR<27> - AR_25 - ------------------------------------------------- --------------------------- - Total 4.290ns (1.642ns logic, 2.648ns route) - (38.3% logic, 61.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_25 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_25 (SLICE_X0Y24.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.244ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<25> (PAD) - Destination: AR_25 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 1.956ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<25> to AR_25 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H2.I Tiopi 0.763 FSB_A<25> - FSB_A<25> - FSB_A_25_IBUF - ProtoComp10.IMUX.17 - SLICE_X0Y24.BX net (fanout=2) 1.152 FSB_A_25_IBUF - SLICE_X0Y24.CLK Tckdi (-Th) -0.041 AR<27> - AR_25 - ------------------------------------------------- --------------------------- - Total 1.956ns (0.804ns logic, 1.152ns route) - (41.1% logic, 58.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_25 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.A2), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.974ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<25> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.691ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<25> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H2.I Tiopi 0.763 FSB_A<25> - FSB_A<25> - FSB_A_25_IBUF - ProtoComp10.IMUX.17 - SLICE_X0Y21.A2 net (fanout=2) 1.539 FSB_A_25_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.389 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.691ns (1.152ns logic, 1.539ns route) - (42.8% logic, 57.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.026ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.A6), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.974ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<24> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.709ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<24> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E2.I Tiopi 1.557 FSB_A<24> - FSB_A<24> - FSB_A_24_IBUF - ProtoComp10.IMUX.15 - SLICE_X0Y21.A6 net (fanout=2) 3.473 FSB_A_24_IBUF - SLICE_X0Y21.CLK Tas 0.679 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.709ns (2.236ns logic, 3.473ns route) - (39.2% logic, 60.8% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_24 (SLICE_X0Y24.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.633ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<24> (PAD) - Destination: AR_24 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.045ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<24> to AR_24 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E2.I Tiopi 1.557 FSB_A<24> - FSB_A<24> - FSB_A_24_IBUF - ProtoComp10.IMUX.15 - SLICE_X0Y24.AX net (fanout=2) 3.403 FSB_A_24_IBUF - SLICE_X0Y24.CLK Tdick 0.085 AR<27> - AR_24 - ------------------------------------------------- --------------------------- - Total 5.045ns (1.642ns logic, 3.403ns route) - (32.5% logic, 67.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_24 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_24 (SLICE_X0Y24.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.679ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<24> (PAD) - Destination: AR_24 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.391ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<24> to AR_24 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E2.I Tiopi 0.763 FSB_A<24> - FSB_A<24> - FSB_A_24_IBUF - ProtoComp10.IMUX.15 - SLICE_X0Y24.AX net (fanout=2) 1.587 FSB_A_24_IBUF - SLICE_X0Y24.CLK Tckdi (-Th) -0.041 AR<27> - AR_24 - ------------------------------------------------- --------------------------- - Total 2.391ns (0.804ns logic, 1.587ns route) - (33.6% logic, 66.4% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_24 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y24.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.A6), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.040ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<24> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.757ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<24> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - E2.I Tiopi 0.763 FSB_A<24> - FSB_A<24> - FSB_A_24_IBUF - ProtoComp10.IMUX.15 - SLICE_X0Y21.A6 net (fanout=2) 1.605 FSB_A_24_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.389 OUTt_OBUF - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8> - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.757ns (1.152ns logic, 1.605ns route) - (41.8% logic, 58.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.737ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.263ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<23> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.420ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<23> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F1.I Tiopi 1.557 FSB_A<23> - FSB_A<23> - FSB_A_23_IBUF - ProtoComp10.IMUX.12 - SLICE_X0Y20.D5 net (fanout=2) 3.250 FSB_A_23_IBUF - SLICE_X0Y20.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.420ns (2.167ns logic, 3.253ns route) - (40.0% logic, 60.0% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_23 (SLICE_X0Y23.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.095ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<23> (PAD) - Destination: AR_23 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.583ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<23> to AR_23 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F1.I Tiopi 1.557 FSB_A<23> - FSB_A<23> - FSB_A_23_IBUF - ProtoComp10.IMUX.12 - SLICE_X0Y23.DX net (fanout=2) 2.941 FSB_A_23_IBUF - SLICE_X0Y23.CLK Tdick 0.085 AR<23> - AR_23 - ------------------------------------------------- --------------------------- - Total 4.583ns (1.642ns logic, 2.941ns route) - (35.8% logic, 64.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_23 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_23 (SLICE_X0Y23.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.472ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<23> (PAD) - Destination: AR_23 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.184ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<23> to AR_23 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F1.I Tiopi 0.763 FSB_A<23> - FSB_A<23> - FSB_A_23_IBUF - ProtoComp10.IMUX.12 - SLICE_X0Y23.DX net (fanout=2) 1.380 FSB_A_23_IBUF - SLICE_X0Y23.CLK Tckdi (-Th) -0.041 AR<23> - AR_23 - ------------------------------------------------- --------------------------- - Total 2.184ns (0.804ns logic, 1.380ns route) - (36.8% logic, 63.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_23 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.916ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<23> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.633ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<23> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F1.I Tiopi 0.763 FSB_A<23> - FSB_A<23> - FSB_A_23_IBUF - ProtoComp10.IMUX.12 - SLICE_X0Y20.D5 net (fanout=2) 1.533 FSB_A_23_IBUF - SLICE_X0Y20.COUT Topcyd 0.187 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.633ns (1.099ns logic, 1.534ns route) - (41.7% logic, 58.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.907ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.093ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<22> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.590ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<22> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F2.I Tiopi 1.557 FSB_A<22> - FSB_A<22> - FSB_A_22_IBUF - ProtoComp10.IMUX.9 - SLICE_X0Y20.D3 net (fanout=2) 3.420 FSB_A_22_IBUF - SLICE_X0Y20.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.590ns (2.167ns logic, 3.423ns route) - (38.8% logic, 61.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_22 (SLICE_X0Y23.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.712ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<22> (PAD) - Destination: AR_22 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.966ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<22> to AR_22 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F2.I Tiopi 1.557 FSB_A<22> - FSB_A<22> - FSB_A_22_IBUF - ProtoComp10.IMUX.9 - SLICE_X0Y23.CX net (fanout=2) 3.324 FSB_A_22_IBUF - SLICE_X0Y23.CLK Tdick 0.085 AR<23> - AR_22 - ------------------------------------------------- --------------------------- - Total 4.966ns (1.642ns logic, 3.324ns route) - (33.1% logic, 66.9% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_22 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_22 (SLICE_X0Y23.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.637ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<22> (PAD) - Destination: AR_22 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.349ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<22> to AR_22 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F2.I Tiopi 0.763 FSB_A<22> - FSB_A<22> - FSB_A_22_IBUF - ProtoComp10.IMUX.9 - SLICE_X0Y23.CX net (fanout=2) 1.545 FSB_A_22_IBUF - SLICE_X0Y23.CLK Tckdi (-Th) -0.041 AR<23> - AR_22 - ------------------------------------------------- --------------------------- - Total 2.349ns (0.804ns logic, 1.545ns route) - (34.2% logic, 65.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_22 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.965ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<22> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.682ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<22> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - F2.I Tiopi 0.763 FSB_A<22> - FSB_A<22> - FSB_A_22_IBUF - ProtoComp10.IMUX.9 - SLICE_X0Y20.D3 net (fanout=2) 1.582 FSB_A_22_IBUF - SLICE_X0Y20.COUT Topcyd 0.187 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.682ns (1.099ns logic, 1.583ns route) - (41.0% logic, 59.0% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.275ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.725ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<21> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.958ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<21> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J6.I Tiopi 1.557 FSB_A<21> - FSB_A<21> - FSB_A_21_IBUF - ProtoComp10.IMUX.7 - SLICE_X0Y20.D6 net (fanout=2) 3.788 FSB_A_21_IBUF - SLICE_X0Y20.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.958ns (2.167ns logic, 3.791ns route) - (36.4% logic, 63.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_21 (SLICE_X0Y23.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.601ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<21> (PAD) - Destination: AR_21 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.077ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<21> to AR_21 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J6.I Tiopi 1.557 FSB_A<21> - FSB_A<21> - FSB_A_21_IBUF - ProtoComp10.IMUX.7 - SLICE_X0Y23.BX net (fanout=2) 3.435 FSB_A_21_IBUF - SLICE_X0Y23.CLK Tdick 0.085 AR<23> - AR_21 - ------------------------------------------------- --------------------------- - Total 5.077ns (1.642ns logic, 3.435ns route) - (32.3% logic, 67.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_21 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_21 (SLICE_X0Y23.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.718ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<21> (PAD) - Destination: AR_21 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.430ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<21> to AR_21 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J6.I Tiopi 0.763 FSB_A<21> - FSB_A<21> - FSB_A_21_IBUF - ProtoComp10.IMUX.7 - SLICE_X0Y23.BX net (fanout=2) 1.626 FSB_A_21_IBUF - SLICE_X0Y23.CLK Tckdi (-Th) -0.041 AR<23> - AR_21 - ------------------------------------------------- --------------------------- - Total 2.430ns (0.804ns logic, 1.626ns route) - (33.1% logic, 66.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_21 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.203ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<21> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.920ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<21> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J6.I Tiopi 0.763 FSB_A<21> - FSB_A<21> - FSB_A_21_IBUF - ProtoComp10.IMUX.7 - SLICE_X0Y20.D6 net (fanout=2) 1.820 FSB_A_21_IBUF - SLICE_X0Y20.COUT Topcyd 0.187 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.920ns (1.099ns logic, 1.821ns route) - (37.6% logic, 62.4% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.064ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.936ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<20> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.747ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<20> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L5.I Tiopi 1.557 FSB_A<20> - FSB_A<20> - FSB_A_20_IBUF - ProtoComp10.IMUX.4 - SLICE_X0Y20.C5 net (fanout=2) 3.561 FSB_A_20_IBUF - SLICE_X0Y20.COUT Topcyc 0.328 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.747ns (2.183ns logic, 3.564ns route) - (38.0% logic, 62.0% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_20 (SLICE_X0Y23.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.969ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<20> (PAD) - Destination: AR_20 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.709ns (Levels of Logic = 1) - Clock Path Delay: -3.908ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<20> to AR_20 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L5.I Tiopi 1.557 FSB_A<20> - FSB_A<20> - FSB_A_20_IBUF - ProtoComp10.IMUX.4 - SLICE_X0Y23.AX net (fanout=2) 3.067 FSB_A_20_IBUF - SLICE_X0Y23.CLK Tdick 0.085 AR<23> - AR_20 - ------------------------------------------------- --------------------------- - Total 4.709ns (1.642ns logic, 3.067ns route) - (34.9% logic, 65.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_20 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.851 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.908ns (-6.300ns logic, 2.392ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_20 (SLICE_X0Y23.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.578ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<20> (PAD) - Destination: AR_20 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.290ns (Levels of Logic = 1) - Clock Path Delay: -1.702ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<20> to AR_20 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L5.I Tiopi 0.763 FSB_A<20> - FSB_A<20> - FSB_A_20_IBUF - ProtoComp10.IMUX.4 - SLICE_X0Y23.AX net (fanout=2) 1.486 FSB_A_20_IBUF - SLICE_X0Y23.CLK Tckdi (-Th) -0.041 AR<23> - AR_20 - ------------------------------------------------- --------------------------- - Total 2.290ns (0.804ns logic, 1.486ns route) - (35.1% logic, 64.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_20 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y23.CLK net (fanout=17) 0.793 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.702ns (-3.199ns logic, 1.497ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.126ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<20> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.843ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<20> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L5.I Tiopi 0.763 FSB_A<20> - FSB_A<20> - FSB_A_20_IBUF - ProtoComp10.IMUX.4 - SLICE_X0Y20.C5 net (fanout=2) 1.727 FSB_A_20_IBUF - SLICE_X0Y20.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.843ns (1.115ns logic, 1.728ns route) - (39.2% logic, 60.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.995ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.005ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<19> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.678ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<19> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G3.I Tiopi 1.557 FSB_A<19> - FSB_A<19> - FSB_A_19_IBUF - ProtoComp10.IMUX.21 - SLICE_X0Y20.C3 net (fanout=2) 3.492 FSB_A_19_IBUF - SLICE_X0Y20.COUT Topcyc 0.328 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.678ns (2.183ns logic, 3.495ns route) - (38.4% logic, 61.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_19 (SLICE_X0Y22.D4), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.556ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<19> (PAD) - Destination: AR_19 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.124ns (Levels of Logic = 2) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<19> to AR_19 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G3.I Tiopi 1.557 FSB_A<19> - FSB_A<19> - FSB_A_19_IBUF - ProtoComp10.IMUX.21 - SLICE_X0Y22.D4 net (fanout=2) 3.367 FSB_A_19_IBUF - SLICE_X0Y22.CLK Tas 0.200 AR<31> - FSB_A_19_IBUF_rt - AR_19 - ------------------------------------------------- --------------------------- - Total 5.124ns (1.757ns logic, 3.367ns route) - (34.3% logic, 65.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_19 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_19 (SLICE_X0Y22.D4), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.722ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<19> (PAD) - Destination: AR_19 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.436ns (Levels of Logic = 2) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<19> to AR_19 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G3.I Tiopi 0.763 FSB_A<19> - FSB_A<19> - FSB_A_19_IBUF - ProtoComp10.IMUX.21 - SLICE_X0Y22.D4 net (fanout=2) 1.542 FSB_A_19_IBUF - SLICE_X0Y22.CLK Tah (-Th) -0.131 AR<31> - FSB_A_19_IBUF_rt - AR_19 - ------------------------------------------------- --------------------------- - Total 2.436ns (0.894ns logic, 1.542ns route) - (36.7% logic, 63.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_19 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.047ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<19> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.764ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<19> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - G3.I Tiopi 0.763 FSB_A<19> - FSB_A<19> - FSB_A_19_IBUF - ProtoComp10.IMUX.21 - SLICE_X0Y20.C3 net (fanout=2) 1.648 FSB_A_19_IBUF - SLICE_X0Y20.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.764ns (1.115ns logic, 1.649ns route) - (40.3% logic, 59.7% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.868ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.132ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<18> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.551ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<18> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K6.I Tiopi 1.557 FSB_A<18> - FSB_A<18> - FSB_A_18_IBUF - ProtoComp10.IMUX.18 - SLICE_X0Y20.C6 net (fanout=2) 3.365 FSB_A_18_IBUF - SLICE_X0Y20.COUT Topcyc 0.328 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.551ns (2.183ns logic, 3.368ns route) - (39.3% logic, 60.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_18 (SLICE_X0Y22.C5), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.537ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<18> (PAD) - Destination: AR_18 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.143ns (Levels of Logic = 2) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<18> to AR_18 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K6.I Tiopi 1.557 FSB_A<18> - FSB_A<18> - FSB_A_18_IBUF - ProtoComp10.IMUX.18 - SLICE_X0Y22.C5 net (fanout=2) 3.386 FSB_A_18_IBUF - SLICE_X0Y22.CLK Tas 0.200 AR<31> - FSB_A_18_IBUF_rt - AR_18 - ------------------------------------------------- --------------------------- - Total 5.143ns (1.757ns logic, 3.386ns route) - (34.2% logic, 65.8% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_18 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_18 (SLICE_X0Y22.C5), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.829ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<18> (PAD) - Destination: AR_18 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.543ns (Levels of Logic = 2) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<18> to AR_18 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K6.I Tiopi 0.763 FSB_A<18> - FSB_A<18> - FSB_A_18_IBUF - ProtoComp10.IMUX.18 - SLICE_X0Y22.C5 net (fanout=2) 1.649 FSB_A_18_IBUF - SLICE_X0Y22.CLK Tah (-Th) -0.131 AR<31> - FSB_A_18_IBUF_rt - AR_18 - ------------------------------------------------- --------------------------- - Total 2.543ns (0.894ns logic, 1.649ns route) - (35.2% logic, 64.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_18 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.024ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<18> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.741ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<18> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K6.I Tiopi 0.763 FSB_A<18> - FSB_A<18> - FSB_A_18_IBUF - ProtoComp10.IMUX.18 - SLICE_X0Y20.C6 net (fanout=2) 1.625 FSB_A_18_IBUF - SLICE_X0Y20.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.741ns (1.115ns logic, 1.626ns route) - (40.7% logic, 59.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.261ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.739ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<17> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.944ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<17> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J1.I Tiopi 1.557 FSB_A<17> - FSB_A<17> - FSB_A_17_IBUF - ProtoComp10.IMUX.16 - SLICE_X0Y20.B5 net (fanout=2) 2.603 FSB_A_17_IBUF - SLICE_X0Y20.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 4.944ns (2.338ns logic, 2.606ns route) - (47.3% logic, 52.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_17 (SLICE_X0Y22.B5), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.107ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<17> (PAD) - Destination: AR_17 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.573ns (Levels of Logic = 2) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<17> to AR_17 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J1.I Tiopi 1.557 FSB_A<17> - FSB_A<17> - FSB_A_17_IBUF - ProtoComp10.IMUX.16 - SLICE_X0Y22.B5 net (fanout=2) 2.816 FSB_A_17_IBUF - SLICE_X0Y22.CLK Tas 0.200 AR<31> - FSB_A_17_IBUF_rt - AR_17 - ------------------------------------------------- --------------------------- - Total 4.573ns (1.757ns logic, 2.816ns route) - (38.4% logic, 61.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_17 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_17 (SLICE_X0Y22.B5), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.474ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<17> (PAD) - Destination: AR_17 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.188ns (Levels of Logic = 2) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<17> to AR_17 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J1.I Tiopi 0.763 FSB_A<17> - FSB_A<17> - FSB_A_17_IBUF - ProtoComp10.IMUX.16 - SLICE_X0Y22.B5 net (fanout=2) 1.294 FSB_A_17_IBUF - SLICE_X0Y22.CLK Tah (-Th) -0.131 AR<31> - FSB_A_17_IBUF_rt - AR_17 - ------------------------------------------------- --------------------------- - Total 2.188ns (0.894ns logic, 1.294ns route) - (40.9% logic, 59.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_17 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.642ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<17> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.359ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<17> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J1.I Tiopi 0.763 FSB_A<17> - FSB_A<17> - FSB_A_17_IBUF - ProtoComp10.IMUX.16 - SLICE_X0Y20.B5 net (fanout=2) 1.182 FSB_A_17_IBUF - SLICE_X0Y20.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.359ns (1.176ns logic, 1.183ns route) - (49.9% logic, 50.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.565ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.435ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<16> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.248ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<16> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J3.I Tiopi 1.557 FSB_A<16> - FSB_A<16> - FSB_A_16_IBUF - ProtoComp10.IMUX.14 - SLICE_X0Y20.B2 net (fanout=2) 2.907 FSB_A_16_IBUF - SLICE_X0Y20.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.248ns (2.338ns logic, 2.910ns route) - (44.6% logic, 55.4% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_16 (SLICE_X0Y22.A2), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.047ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<16> (PAD) - Destination: AR_16 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.633ns (Levels of Logic = 2) - Clock Path Delay: -3.906ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<16> to AR_16 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J3.I Tiopi 1.557 FSB_A<16> - FSB_A<16> - FSB_A_16_IBUF - ProtoComp10.IMUX.14 - SLICE_X0Y22.A2 net (fanout=2) 2.876 FSB_A_16_IBUF - SLICE_X0Y22.CLK Tas 0.200 AR<31> - FSB_A_16_IBUF_rt - AR_16 - ------------------------------------------------- --------------------------- - Total 4.633ns (1.757ns logic, 2.876ns route) - (37.9% logic, 62.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_16 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.853 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.906ns (-6.300ns logic, 2.394ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_16 (SLICE_X0Y22.A2), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.493ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<16> (PAD) - Destination: AR_16 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.207ns (Levels of Logic = 2) - Clock Path Delay: -1.700ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<16> to AR_16 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J3.I Tiopi 0.763 FSB_A<16> - FSB_A<16> - FSB_A_16_IBUF - ProtoComp10.IMUX.14 - SLICE_X0Y22.A2 net (fanout=2) 1.313 FSB_A_16_IBUF - SLICE_X0Y22.CLK Tah (-Th) -0.131 AR<31> - FSB_A_16_IBUF_rt - AR_16 - ------------------------------------------------- --------------------------- - Total 2.207ns (0.894ns logic, 1.313ns route) - (40.5% logic, 59.5% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_16 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y22.CLK net (fanout=17) 0.795 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.700ns (-3.199ns logic, 1.499ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.745ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<16> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.462ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<16> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J3.I Tiopi 0.763 FSB_A<16> - FSB_A<16> - FSB_A_16_IBUF - ProtoComp10.IMUX.14 - SLICE_X0Y20.B2 net (fanout=2) 1.285 FSB_A_16_IBUF - SLICE_X0Y20.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.462ns (1.176ns logic, 1.286ns route) - (47.8% logic, 52.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.096ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.904ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<15> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.779ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<15> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M5.I Tiopi 1.557 FSB_A<15> - FSB_A<15> - FSB_A_15_IBUF - ProtoComp10.IMUX.11 - SLICE_X0Y20.B6 net (fanout=2) 3.438 FSB_A_15_IBUF - SLICE_X0Y20.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.779ns (2.338ns logic, 3.441ns route) - (40.5% logic, 59.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_15 (SLICE_X1Y20.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.288ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<15> (PAD) - Destination: AR_15 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.398ns (Levels of Logic = 1) - Clock Path Delay: -3.900ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<15> to AR_15 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M5.I Tiopi 1.557 FSB_A<15> - FSB_A<15> - FSB_A_15_IBUF - ProtoComp10.IMUX.11 - SLICE_X1Y20.DX net (fanout=2) 3.727 FSB_A_15_IBUF - SLICE_X1Y20.CLK Tdick 0.114 AR<15> - AR_15 - ------------------------------------------------- --------------------------- - Total 5.398ns (1.671ns logic, 3.727ns route) - (31.0% logic, 69.0% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_15 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.859 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.900ns (-6.300ns logic, 2.400ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_15 (SLICE_X1Y20.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.834ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<15> (PAD) - Destination: AR_15 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.554ns (Levels of Logic = 1) - Clock Path Delay: -1.694ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<15> to AR_15 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M5.I Tiopi 0.763 FSB_A<15> - FSB_A<15> - FSB_A_15_IBUF - ProtoComp10.IMUX.11 - SLICE_X1Y20.DX net (fanout=2) 1.732 FSB_A_15_IBUF - SLICE_X1Y20.CLK Tckdi (-Th) -0.059 AR<15> - AR_15 - ------------------------------------------------- --------------------------- - Total 2.554ns (0.822ns logic, 1.732ns route) - (32.2% logic, 67.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_15 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.801 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.694ns (-3.199ns logic, 1.505ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.030ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<15> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.747ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<15> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M5.I Tiopi 0.763 FSB_A<15> - FSB_A<15> - FSB_A_15_IBUF - ProtoComp10.IMUX.11 - SLICE_X0Y20.B6 net (fanout=2) 1.570 FSB_A_15_IBUF - SLICE_X0Y20.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.747ns (1.176ns logic, 1.571ns route) - (42.8% logic, 57.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.084ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.916ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<14> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.767ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<14> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K2.I Tiopi 1.557 FSB_A<14> - FSB_A<14> - FSB_A_14_IBUF - ProtoComp10.IMUX.8 - SLICE_X0Y20.A4 net (fanout=2) 2.435 FSB_A_14_IBUF - SLICE_X0Y20.COUT Topcya 0.474 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 4.767ns (2.329ns logic, 2.438ns route) - (48.9% logic, 51.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_14 (SLICE_X1Y20.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.418ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<14> (PAD) - Destination: AR_14 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.268ns (Levels of Logic = 1) - Clock Path Delay: -3.900ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<14> to AR_14 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K2.I Tiopi 1.557 FSB_A<14> - FSB_A<14> - FSB_A_14_IBUF - ProtoComp10.IMUX.8 - SLICE_X1Y20.CX net (fanout=2) 2.597 FSB_A_14_IBUF - SLICE_X1Y20.CLK Tdick 0.114 AR<15> - AR_14 - ------------------------------------------------- --------------------------- - Total 4.268ns (1.671ns logic, 2.597ns route) - (39.2% logic, 60.8% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_14 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.859 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.900ns (-6.300ns logic, 2.400ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_14 (SLICE_X1Y20.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.242ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<14> (PAD) - Destination: AR_14 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 1.962ns (Levels of Logic = 1) - Clock Path Delay: -1.694ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<14> to AR_14 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K2.I Tiopi 0.763 FSB_A<14> - FSB_A<14> - FSB_A_14_IBUF - ProtoComp10.IMUX.8 - SLICE_X1Y20.CX net (fanout=2) 1.140 FSB_A_14_IBUF - SLICE_X1Y20.CLK Tckdi (-Th) -0.059 AR<15> - AR_14 - ------------------------------------------------- --------------------------- - Total 1.962ns (0.822ns logic, 1.140ns route) - (41.9% logic, 58.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_14 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.801 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.694ns (-3.199ns logic, 1.505ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.489ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<14> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.206ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<14> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K2.I Tiopi 0.763 FSB_A<14> - FSB_A<14> - FSB_A_14_IBUF - ProtoComp10.IMUX.8 - SLICE_X0Y20.A4 net (fanout=2) 1.021 FSB_A_14_IBUF - SLICE_X0Y20.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.206ns (1.184ns logic, 1.022ns route) - (53.7% logic, 46.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.011ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.989ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<13> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.694ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<13> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N3.I Tiopi 1.557 FSB_A<13> - FSB_A<13> - FSB_A_13_IBUF - ProtoComp10.IMUX.6 - SLICE_X0Y20.A3 net (fanout=2) 3.362 FSB_A_13_IBUF - SLICE_X0Y20.COUT Topcya 0.474 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.694ns (2.329ns logic, 3.365ns route) - (40.9% logic, 59.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_13 (SLICE_X1Y20.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.551ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<13> (PAD) - Destination: AR_13 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.135ns (Levels of Logic = 1) - Clock Path Delay: -3.900ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<13> to AR_13 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N3.I Tiopi 1.557 FSB_A<13> - FSB_A<13> - FSB_A_13_IBUF - ProtoComp10.IMUX.6 - SLICE_X1Y20.BX net (fanout=2) 3.464 FSB_A_13_IBUF - SLICE_X1Y20.CLK Tdick 0.114 AR<15> - AR_13 - ------------------------------------------------- --------------------------- - Total 5.135ns (1.671ns logic, 3.464ns route) - (32.5% logic, 67.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_13 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.859 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.900ns (-6.300ns logic, 2.400ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_13 (SLICE_X1Y20.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.709ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<13> (PAD) - Destination: AR_13 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.429ns (Levels of Logic = 1) - Clock Path Delay: -1.694ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<13> to AR_13 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N3.I Tiopi 0.763 FSB_A<13> - FSB_A<13> - FSB_A_13_IBUF - ProtoComp10.IMUX.6 - SLICE_X1Y20.BX net (fanout=2) 1.607 FSB_A_13_IBUF - SLICE_X1Y20.CLK Tckdi (-Th) -0.059 AR<15> - AR_13 - ------------------------------------------------- --------------------------- - Total 2.429ns (0.822ns logic, 1.607ns route) - (33.8% logic, 66.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_13 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.801 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.694ns (-3.199ns logic, 1.505ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.009ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<13> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.726ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<13> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N3.I Tiopi 0.763 FSB_A<13> - FSB_A<13> - FSB_A_13_IBUF - ProtoComp10.IMUX.6 - SLICE_X0Y20.A3 net (fanout=2) 1.541 FSB_A_13_IBUF - SLICE_X0Y20.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.726ns (1.184ns logic, 1.542ns route) - (43.4% logic, 56.6% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.821ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.179ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<12> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.504ns (Levels of Logic = 3) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<12> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P2.I Tiopi 1.557 FSB_A<12> - FSB_A<12> - FSB_A_12_IBUF - ProtoComp10.IMUX.3 - SLICE_X0Y20.A6 net (fanout=2) 3.172 FSB_A_12_IBUF - SLICE_X0Y20.COUT Topcya 0.474 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.504ns (2.329ns logic, 3.175ns route) - (42.3% logic, 57.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_12 (SLICE_X1Y20.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.724ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<12> (PAD) - Destination: AR_12 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.962ns (Levels of Logic = 1) - Clock Path Delay: -3.900ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<12> to AR_12 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P2.I Tiopi 1.557 FSB_A<12> - FSB_A<12> - FSB_A_12_IBUF - ProtoComp10.IMUX.3 - SLICE_X1Y20.AX net (fanout=2) 3.291 FSB_A_12_IBUF - SLICE_X1Y20.CLK Tdick 0.114 AR<15> - AR_12 - ------------------------------------------------- --------------------------- - Total 4.962ns (1.671ns logic, 3.291ns route) - (33.7% logic, 66.3% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_12 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.859 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.900ns (-6.300ns logic, 2.400ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_12 (SLICE_X1Y20.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.605ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<12> (PAD) - Destination: AR_12 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.325ns (Levels of Logic = 1) - Clock Path Delay: -1.694ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<12> to AR_12 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P2.I Tiopi 0.763 FSB_A<12> - FSB_A<12> - FSB_A_12_IBUF - ProtoComp10.IMUX.3 - SLICE_X1Y20.AX net (fanout=2) 1.503 FSB_A_12_IBUF - SLICE_X1Y20.CLK Tckdi (-Th) -0.059 AR<15> - AR_12 - ------------------------------------------------- --------------------------- - Total 2.325ns (0.822ns logic, 1.503ns route) - (35.4% logic, 64.6% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_12 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X1Y20.CLK net (fanout=17) 0.801 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.694ns (-3.199ns logic, 1.505ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.895ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<12> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.612ns (Levels of Logic = 3) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<12> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P2.I Tiopi 0.763 FSB_A<12> - FSB_A<12> - FSB_A_12_IBUF - ProtoComp10.IMUX.3 - SLICE_X0Y20.A6 net (fanout=2) 1.427 FSB_A_12_IBUF - SLICE_X0Y20.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.612ns (1.184ns logic, 1.428ns route) - (45.3% logic, 54.7% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.522ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.478ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<11> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.205ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<11> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L1.I Tiopi 1.557 FSB_A<11> - FSB_A<11> - FSB_A_11_IBUF - ProtoComp10.IMUX.2 - SLICE_X0Y19.D3 net (fanout=2) 2.939 FSB_A_11_IBUF - SLICE_X0Y19.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.205ns (2.260ns logic, 2.945ns route) - (43.4% logic, 56.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_11 (SLICE_X0Y17.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.494ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<11> (PAD) - Destination: AR_11 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.197ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<11> to AR_11 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L1.I Tiopi 1.557 FSB_A<11> - FSB_A<11> - FSB_A_11_IBUF - ProtoComp10.IMUX.2 - SLICE_X0Y17.DX net (fanout=2) 2.555 FSB_A_11_IBUF - SLICE_X0Y17.CLK Tdick 0.085 AR<11> - AR_11 - ------------------------------------------------- --------------------------- - Total 4.197ns (1.642ns logic, 2.555ns route) - (39.1% logic, 60.9% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_11 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_11 (SLICE_X0Y17.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.200ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<11> (PAD) - Destination: AR_11 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 1.925ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<11> to AR_11 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L1.I Tiopi 0.763 FSB_A<11> - FSB_A<11> - FSB_A_11_IBUF - ProtoComp10.IMUX.2 - SLICE_X0Y17.DX net (fanout=2) 1.121 FSB_A_11_IBUF - SLICE_X0Y17.CLK Tckdi (-Th) -0.041 AR<11> - AR_11 - ------------------------------------------------- --------------------------- - Total 1.925ns (0.804ns logic, 1.121ns route) - (41.8% logic, 58.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_11 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.798ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<11> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.515ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<11> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L1.I Tiopi 0.763 FSB_A<11> - FSB_A<11> - FSB_A_11_IBUF - ProtoComp10.IMUX.2 - SLICE_X0Y19.D3 net (fanout=2) 1.382 FSB_A_11_IBUF - SLICE_X0Y19.COUT Topcyd 0.187 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.515ns (1.131ns logic, 1.384ns route) - (45.0% logic, 55.0% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.562ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.438ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<10> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.245ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<10> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N1.I Tiopi 1.557 FSB_A<10> - FSB_A<10> - FSB_A_10_IBUF - ProtoComp10.IMUX - SLICE_X0Y19.D4 net (fanout=2) 2.979 FSB_A_10_IBUF - SLICE_X0Y19.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.245ns (2.260ns logic, 2.985ns route) - (43.1% logic, 56.9% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_10 (SLICE_X0Y17.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.113ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<10> (PAD) - Destination: AR_10 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.578ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<10> to AR_10 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N1.I Tiopi 1.557 FSB_A<10> - FSB_A<10> - FSB_A_10_IBUF - ProtoComp10.IMUX - SLICE_X0Y17.CX net (fanout=2) 2.936 FSB_A_10_IBUF - SLICE_X0Y17.CLK Tdick 0.085 AR<11> - AR_10 - ------------------------------------------------- --------------------------- - Total 4.578ns (1.642ns logic, 2.936ns route) - (35.9% logic, 64.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_10 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_10 (SLICE_X0Y17.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.463ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<10> (PAD) - Destination: AR_10 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.188ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<10> to AR_10 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N1.I Tiopi 0.763 FSB_A<10> - FSB_A<10> - FSB_A_10_IBUF - ProtoComp10.IMUX - SLICE_X0Y17.CX net (fanout=2) 1.384 FSB_A_10_IBUF - SLICE_X0Y17.CLK Tckdi (-Th) -0.041 AR<11> - AR_10 - ------------------------------------------------- --------------------------- - Total 2.188ns (0.804ns logic, 1.384ns route) - (36.7% logic, 63.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_10 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.800ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<10> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.517ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<10> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N1.I Tiopi 0.763 FSB_A<10> - FSB_A<10> - FSB_A_10_IBUF - ProtoComp10.IMUX - SLICE_X0Y19.D4 net (fanout=2) 1.384 FSB_A_10_IBUF - SLICE_X0Y19.COUT Topcyd 0.187 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.517ns (1.131ns logic, 1.386ns route) - (44.9% logic, 55.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.009ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.991ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<9> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.692ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<9> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R1.I Tiopi 1.557 FSB_A<9> - FSB_A<9> - FSB_A_9_IBUF - ProtoComp10.IMUX.34 - SLICE_X0Y19.D6 net (fanout=2) 3.426 FSB_A_9_IBUF - SLICE_X0Y19.COUT Topcyd 0.312 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.692ns (2.260ns logic, 3.432ns route) - (39.7% logic, 60.3% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_9 (SLICE_X0Y17.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.827ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<9> (PAD) - Destination: AR_9 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.864ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<9> to AR_9 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R1.I Tiopi 1.557 FSB_A<9> - FSB_A<9> - FSB_A_9_IBUF - ProtoComp10.IMUX.34 - SLICE_X0Y17.BX net (fanout=2) 3.222 FSB_A_9_IBUF - SLICE_X0Y17.CLK Tdick 0.085 AR<11> - AR_9 - ------------------------------------------------- --------------------------- - Total 4.864ns (1.642ns logic, 3.222ns route) - (33.8% logic, 66.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_9 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_9 (SLICE_X0Y17.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.618ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<9> (PAD) - Destination: AR_9 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.343ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<9> to AR_9 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R1.I Tiopi 0.763 FSB_A<9> - FSB_A<9> - FSB_A_9_IBUF - ProtoComp10.IMUX.34 - SLICE_X0Y17.BX net (fanout=2) 1.539 FSB_A_9_IBUF - SLICE_X0Y17.CLK Tckdi (-Th) -0.041 AR<11> - AR_9 - ------------------------------------------------- --------------------------- - Total 2.343ns (0.804ns logic, 1.539ns route) - (34.3% logic, 65.7% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_9 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.045ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<9> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.762ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<9> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R1.I Tiopi 0.763 FSB_A<9> - FSB_A<9> - FSB_A_9_IBUF - ProtoComp10.IMUX.34 - SLICE_X0Y19.D6 net (fanout=2) 1.629 FSB_A_9_IBUF - SLICE_X0Y19.COUT Topcyd 0.187 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.762ns (1.131ns logic, 1.631ns route) - (40.9% logic, 59.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.287ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.713ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<8> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.970ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<8> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M4.I Tiopi 1.557 FSB_A<8> - FSB_A<8> - FSB_A_8_IBUF - ProtoComp10.IMUX.33 - SLICE_X0Y19.C6 net (fanout=2) 3.688 FSB_A_8_IBUF - SLICE_X0Y19.COUT Topcyc 0.328 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.970ns (2.276ns logic, 3.694ns route) - (38.1% logic, 61.9% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_8 (SLICE_X0Y17.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.446ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<8> (PAD) - Destination: AR_8 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.245ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<8> to AR_8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M4.I Tiopi 1.557 FSB_A<8> - FSB_A<8> - FSB_A_8_IBUF - ProtoComp10.IMUX.33 - SLICE_X0Y17.AX net (fanout=2) 3.603 FSB_A_8_IBUF - SLICE_X0Y17.CLK Tdick 0.085 AR<11> - AR_8 - ------------------------------------------------- --------------------------- - Total 5.245ns (1.642ns logic, 3.603ns route) - (31.3% logic, 68.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_8 (SLICE_X0Y17.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.756ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<8> (PAD) - Destination: AR_8 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.481ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<8> to AR_8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M4.I Tiopi 0.763 FSB_A<8> - FSB_A<8> - FSB_A_8_IBUF - ProtoComp10.IMUX.33 - SLICE_X0Y17.AX net (fanout=2) 1.677 FSB_A_8_IBUF - SLICE_X0Y17.CLK Tckdi (-Th) -0.041 AR<11> - AR_8 - ------------------------------------------------- --------------------------- - Total 2.481ns (0.804ns logic, 1.677ns route) - (32.4% logic, 67.6% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_8 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y17.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.144ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<8> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.861ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<8> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M4.I Tiopi 0.763 FSB_A<8> - FSB_A<8> - FSB_A_8_IBUF - ProtoComp10.IMUX.33 - SLICE_X0Y19.C6 net (fanout=2) 1.712 FSB_A_8_IBUF - SLICE_X0Y19.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.861ns (1.147ns logic, 1.714ns route) - (40.1% logic, 59.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.757ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.243ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<7> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.440ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<7> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P1.I Tiopi 1.557 FSB_A<7> - FSB_A<7> - FSB_A_7_IBUF - ProtoComp10.IMUX.32 - SLICE_X0Y19.C4 net (fanout=2) 3.158 FSB_A_7_IBUF - SLICE_X0Y19.COUT Topcyc 0.328 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.440ns (2.276ns logic, 3.164ns route) - (41.8% logic, 58.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_7 (SLICE_X0Y18.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.106ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<7> (PAD) - Destination: AR_7 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.584ns (Levels of Logic = 1) - Clock Path Delay: -3.896ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<7> to AR_7 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P1.I Tiopi 1.557 FSB_A<7> - FSB_A<7> - FSB_A_7_IBUF - ProtoComp10.IMUX.32 - SLICE_X0Y18.DX net (fanout=2) 2.942 FSB_A_7_IBUF - SLICE_X0Y18.CLK Tdick 0.085 AR<7> - AR_7 - ------------------------------------------------- --------------------------- - Total 4.584ns (1.642ns logic, 2.942ns route) - (35.8% logic, 64.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_7 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.863 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.896ns (-6.300ns logic, 2.404ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_7 (SLICE_X0Y18.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.464ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<7> (PAD) - Destination: AR_7 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.188ns (Levels of Logic = 1) - Clock Path Delay: -1.690ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<7> to AR_7 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P1.I Tiopi 0.763 FSB_A<7> - FSB_A<7> - FSB_A_7_IBUF - ProtoComp10.IMUX.32 - SLICE_X0Y18.DX net (fanout=2) 1.384 FSB_A_7_IBUF - SLICE_X0Y18.CLK Tckdi (-Th) -0.041 AR<7> - AR_7 - ------------------------------------------------- --------------------------- - Total 2.188ns (0.804ns logic, 1.384ns route) - (36.7% logic, 63.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_7 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.805 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.690ns (-3.199ns logic, 1.509ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.935ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<7> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.652ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<7> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - P1.I Tiopi 0.763 FSB_A<7> - FSB_A<7> - FSB_A_7_IBUF - ProtoComp10.IMUX.32 - SLICE_X0Y19.C4 net (fanout=2) 1.503 FSB_A_7_IBUF - SLICE_X0Y19.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.652ns (1.147ns logic, 1.505ns route) - (43.3% logic, 56.7% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.919ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.081ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<6> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.602ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<6> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M3.I Tiopi 1.557 FSB_A<6> - FSB_A<6> - FSB_A_6_IBUF - ProtoComp10.IMUX.31 - SLICE_X0Y19.C3 net (fanout=2) 3.320 FSB_A_6_IBUF - SLICE_X0Y19.COUT Topcyc 0.328 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.602ns (2.276ns logic, 3.326ns route) - (40.6% logic, 59.4% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_6 (SLICE_X0Y18.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.819ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<6> (PAD) - Destination: AR_6 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.871ns (Levels of Logic = 1) - Clock Path Delay: -3.896ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<6> to AR_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M3.I Tiopi 1.557 FSB_A<6> - FSB_A<6> - FSB_A_6_IBUF - ProtoComp10.IMUX.31 - SLICE_X0Y18.CX net (fanout=2) 3.229 FSB_A_6_IBUF - SLICE_X0Y18.CLK Tdick 0.085 AR<7> - AR_6 - ------------------------------------------------- --------------------------- - Total 4.871ns (1.642ns logic, 3.229ns route) - (33.7% logic, 66.3% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.863 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.896ns (-6.300ns logic, 2.404ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_6 (SLICE_X0Y18.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.621ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<6> (PAD) - Destination: AR_6 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.345ns (Levels of Logic = 1) - Clock Path Delay: -1.690ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<6> to AR_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M3.I Tiopi 0.763 FSB_A<6> - FSB_A<6> - FSB_A_6_IBUF - ProtoComp10.IMUX.31 - SLICE_X0Y18.CX net (fanout=2) 1.541 FSB_A_6_IBUF - SLICE_X0Y18.CLK Tckdi (-Th) -0.041 AR<7> - AR_6 - ------------------------------------------------- --------------------------- - Total 2.345ns (0.804ns logic, 1.541ns route) - (34.3% logic, 65.7% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_6 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.805 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.690ns (-3.199ns logic, 1.509ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.035ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<6> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.752ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<6> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M3.I Tiopi 0.763 FSB_A<6> - FSB_A<6> - FSB_A_6_IBUF - ProtoComp10.IMUX.31 - SLICE_X0Y19.C3 net (fanout=2) 1.603 FSB_A_6_IBUF - SLICE_X0Y19.COUT Topcyc 0.203 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.752ns (1.147ns logic, 1.605ns route) - (41.7% logic, 58.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.265ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.735ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<5> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.948ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<5> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K1.I Tiopi 1.557 FSB_A<5> - FSB_A<5> - FSB_A_5_IBUF - ProtoComp10.IMUX.30 - SLICE_X0Y19.B2 net (fanout=2) 2.511 FSB_A_5_IBUF - SLICE_X0Y19.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 4.948ns (2.431ns logic, 2.517ns route) - (49.1% logic, 50.9% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_5 (SLICE_X0Y18.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.569ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<5> (PAD) - Destination: AR_5 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.121ns (Levels of Logic = 1) - Clock Path Delay: -3.896ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<5> to AR_5 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K1.I Tiopi 1.557 FSB_A<5> - FSB_A<5> - FSB_A_5_IBUF - ProtoComp10.IMUX.30 - SLICE_X0Y18.BX net (fanout=2) 2.479 FSB_A_5_IBUF - SLICE_X0Y18.CLK Tdick 0.085 AR<7> - AR_5 - ------------------------------------------------- --------------------------- - Total 4.121ns (1.642ns logic, 2.479ns route) - (39.8% logic, 60.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_5 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.863 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.896ns (-6.300ns logic, 2.404ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_5 (SLICE_X0Y18.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.204ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<5> (PAD) - Destination: AR_5 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 1.928ns (Levels of Logic = 1) - Clock Path Delay: -1.690ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<5> to AR_5 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K1.I Tiopi 0.763 FSB_A<5> - FSB_A<5> - FSB_A_5_IBUF - ProtoComp10.IMUX.30 - SLICE_X0Y18.BX net (fanout=2) 1.124 FSB_A_5_IBUF - SLICE_X0Y18.CLK Tckdi (-Th) -0.041 AR<7> - AR_5 - ------------------------------------------------- --------------------------- - Total 1.928ns (0.804ns logic, 1.124ns route) - (41.7% logic, 58.3% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_5 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.805 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.690ns (-3.199ns logic, 1.509ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.631ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<5> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.348ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<5> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - K1.I Tiopi 0.763 FSB_A<5> - FSB_A<5> - FSB_A_5_IBUF - ProtoComp10.IMUX.30 - SLICE_X0Y19.B2 net (fanout=2) 1.138 FSB_A_5_IBUF - SLICE_X0Y19.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.348ns (1.208ns logic, 1.140ns route) - (51.4% logic, 48.6% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.766ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.234ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<4> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.449ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<4> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L3.I Tiopi 1.557 FSB_A<4> - FSB_A<4> - FSB_A_4_IBUF - ProtoComp10.IMUX.29 - SLICE_X0Y19.B3 net (fanout=2) 3.012 FSB_A_4_IBUF - SLICE_X0Y19.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.449ns (2.431ns logic, 3.018ns route) - (44.6% logic, 55.4% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_4 (SLICE_X0Y18.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.246ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<4> (PAD) - Destination: AR_4 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.444ns (Levels of Logic = 1) - Clock Path Delay: -3.896ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<4> to AR_4 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L3.I Tiopi 1.557 FSB_A<4> - FSB_A<4> - FSB_A_4_IBUF - ProtoComp10.IMUX.29 - SLICE_X0Y18.AX net (fanout=2) 2.802 FSB_A_4_IBUF - SLICE_X0Y18.CLK Tdick 0.085 AR<7> - AR_4 - ------------------------------------------------- --------------------------- - Total 4.444ns (1.642ns logic, 2.802ns route) - (36.9% logic, 63.1% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_4 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.863 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.896ns (-6.300ns logic, 2.404ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_4 (SLICE_X0Y18.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.288ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<4> (PAD) - Destination: AR_4 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.012ns (Levels of Logic = 1) - Clock Path Delay: -1.690ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<4> to AR_4 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L3.I Tiopi 0.763 FSB_A<4> - FSB_A<4> - FSB_A_4_IBUF - ProtoComp10.IMUX.29 - SLICE_X0Y18.AX net (fanout=2) 1.208 FSB_A_4_IBUF - SLICE_X0Y18.CLK Tckdi (-Th) -0.041 AR<7> - AR_4 - ------------------------------------------------- --------------------------- - Total 2.012ns (0.804ns logic, 1.208ns route) - (40.0% logic, 60.0% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_4 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y18.CLK net (fanout=17) 0.805 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.690ns (-3.199ns logic, 1.509ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.832ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<4> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.549ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<4> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - L3.I Tiopi 0.763 FSB_A<4> - FSB_A<4> - FSB_A_4_IBUF - ProtoComp10.IMUX.29 - SLICE_X0Y19.B3 net (fanout=2) 1.339 FSB_A_4_IBUF - SLICE_X0Y19.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.549ns (1.208ns logic, 1.341ns route) - (47.4% logic, 52.6% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.480ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.520ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<3> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 6.163ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<3> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R2.I Tiopi 1.557 FSB_A<3> - FSB_A<3> - FSB_A_3_IBUF - ProtoComp10.IMUX.28 - SLICE_X0Y19.B6 net (fanout=2) 3.726 FSB_A_3_IBUF - SLICE_X0Y19.COUT Topcyb 0.483 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 6.163ns (2.431ns logic, 3.732ns route) - (39.4% logic, 60.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_3 (SLICE_X0Y16.DX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.439ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<3> (PAD) - Destination: AR_3 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.252ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<3> to AR_3 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R2.I Tiopi 1.557 FSB_A<3> - FSB_A<3> - FSB_A_3_IBUF - ProtoComp10.IMUX.28 - SLICE_X0Y16.DX net (fanout=2) 3.610 FSB_A_3_IBUF - SLICE_X0Y16.CLK Tdick 0.085 AR<3> - AR_3 - ------------------------------------------------- --------------------------- - Total 5.252ns (1.642ns logic, 3.610ns route) - (31.3% logic, 68.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_3 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_3 (SLICE_X0Y16.DX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.772ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<3> (PAD) - Destination: AR_3 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.497ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<3> to AR_3 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R2.I Tiopi 0.763 FSB_A<3> - FSB_A<3> - FSB_A_3_IBUF - ProtoComp10.IMUX.28 - SLICE_X0Y16.DX net (fanout=2) 1.693 FSB_A_3_IBUF - SLICE_X0Y16.CLK Tckdi (-Th) -0.041 AR<3> - AR_3 - ------------------------------------------------- --------------------------- - Total 2.497ns (0.804ns logic, 1.693ns route) - (32.2% logic, 67.8% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_3 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.244ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<3> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.961ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<3> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - R2.I Tiopi 0.763 FSB_A<3> - FSB_A<3> - FSB_A_3_IBUF - ProtoComp10.IMUX.28 - SLICE_X0Y19.B6 net (fanout=2) 1.751 FSB_A_3_IBUF - SLICE_X0Y19.COUT Topcyb 0.264 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.961ns (1.208ns logic, 1.753ns route) - (40.8% logic, 59.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.842ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.158ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<2> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.525ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<2> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M2.I Tiopi 1.557 FSB_A<2> - FSB_A<2> - FSB_A_2_IBUF - ProtoComp10.IMUX.27 - SLICE_X0Y19.A3 net (fanout=2) 3.097 FSB_A_2_IBUF - SLICE_X0Y19.COUT Topcya 0.474 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.525ns (2.422ns logic, 3.103ns route) - (43.8% logic, 56.2% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_2 (SLICE_X0Y16.CX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.407ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<2> (PAD) - Destination: AR_2 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.284ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<2> to AR_2 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M2.I Tiopi 1.557 FSB_A<2> - FSB_A<2> - FSB_A_2_IBUF - ProtoComp10.IMUX.27 - SLICE_X0Y16.CX net (fanout=2) 2.642 FSB_A_2_IBUF - SLICE_X0Y16.CLK Tdick 0.085 AR<3> - AR_2 - ------------------------------------------------- --------------------------- - Total 4.284ns (1.642ns logic, 2.642ns route) - (38.3% logic, 61.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_2 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_2 (SLICE_X0Y16.CX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.237ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<2> (PAD) - Destination: AR_2 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 1.962ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<2> to AR_2 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M2.I Tiopi 0.763 FSB_A<2> - FSB_A<2> - FSB_A_2_IBUF - ProtoComp10.IMUX.27 - SLICE_X0Y16.CX net (fanout=2) 1.158 FSB_A_2_IBUF - SLICE_X0Y16.CLK Tckdi (-Th) -0.041 AR<3> - AR_2 - ------------------------------------------------- --------------------------- - Total 1.962ns (0.804ns logic, 1.158ns route) - (41.0% logic, 59.0% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_2 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.900ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<2> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.617ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<2> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M2.I Tiopi 0.763 FSB_A<2> - FSB_A<2> - FSB_A_2_IBUF - ProtoComp10.IMUX.27 - SLICE_X0Y19.A3 net (fanout=2) 1.399 FSB_A_2_IBUF - SLICE_X0Y19.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.617ns (1.216ns logic, 1.401ns route) - (46.5% logic, 53.5% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.876ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.124ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<1> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.559ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<1> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M1.I Tiopi 1.557 FSB_A<1> - FSB_A<1> - FSB_A_1_IBUF - ProtoComp10.IMUX.26 - SLICE_X0Y19.A2 net (fanout=2) 3.131 FSB_A_1_IBUF - SLICE_X0Y19.COUT Topcya 0.474 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.559ns (2.422ns logic, 3.137ns route) - (43.6% logic, 56.4% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_1 (SLICE_X0Y16.BX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 3.520ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<1> (PAD) - Destination: AR_1 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 4.171ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<1> to AR_1 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M1.I Tiopi 1.557 FSB_A<1> - FSB_A<1> - FSB_A_1_IBUF - ProtoComp10.IMUX.26 - SLICE_X0Y16.BX net (fanout=2) 2.529 FSB_A_1_IBUF - SLICE_X0Y16.CLK Tdick 0.085 AR<3> - AR_1 - ------------------------------------------------- --------------------------- - Total 4.171ns (1.642ns logic, 2.529ns route) - (39.4% logic, 60.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_1 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_1 (SLICE_X0Y16.BX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.242ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<1> (PAD) - Destination: AR_1 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 1.967ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<1> to AR_1 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M1.I Tiopi 0.763 FSB_A<1> - FSB_A<1> - FSB_A_1_IBUF - ProtoComp10.IMUX.26 - SLICE_X0Y16.BX net (fanout=2) 1.163 FSB_A_1_IBUF - SLICE_X0Y16.CLK Tckdi (-Th) -0.041 AR<3> - AR_1 - ------------------------------------------------- --------------------------- - Total 1.967ns (0.804ns logic, 1.163ns route) - (40.9% logic, 59.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_1 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.992ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<1> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.709ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<1> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M1.I Tiopi 0.763 FSB_A<1> - FSB_A<1> - FSB_A_1_IBUF - ProtoComp10.IMUX.26 - SLICE_X0Y19.A2 net (fanout=2) 1.491 FSB_A_1_IBUF - SLICE_X0Y19.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.709ns (1.216ns logic, 1.493ns route) - (44.9% logic, 55.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 2 paths analyzed, 2 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.028ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.972ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<0> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.711ns (Levels of Logic = 4) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<0> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N4.I Tiopi 1.557 FSB_A<0> - FSB_A<0> - FSB_A_0_IBUF - ProtoComp10.IMUX.25 - SLICE_X0Y19.A6 net (fanout=2) 3.283 FSB_A_0_IBUF - SLICE_X0Y19.COUT Topcya 0.474 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.093 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.003 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tcinck 0.298 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.711ns (2.422ns logic, 3.289ns route) - (42.4% logic, 57.6% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Paths for end point AR_0 (SLICE_X0Y16.AX), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.661ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: FSB_A<0> (PAD) - Destination: AR_0 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.030ns (Levels of Logic = 1) - Clock Path Delay: -3.895ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: FSB_A<0> to AR_0 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N4.I Tiopi 1.557 FSB_A<0> - FSB_A<0> - FSB_A_0_IBUF - ProtoComp10.IMUX.25 - SLICE_X0Y16.AX net (fanout=2) 3.388 FSB_A_0_IBUF - SLICE_X0Y16.CLK Tdick 0.085 AR<3> - AR_0 - ------------------------------------------------- --------------------------- - Total 5.030ns (1.642ns logic, 3.388ns route) - (32.6% logic, 67.4% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to AR_0 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.864 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.895ns (-6.300ns logic, 2.405ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point AR_0 (SLICE_X0Y16.AX), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.706ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<0> (PAD) - Destination: AR_0 (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.431ns (Levels of Logic = 1) - Clock Path Delay: -1.689ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<0> to AR_0 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N4.I Tiopi 0.763 FSB_A<0> - FSB_A<0> - FSB_A_0_IBUF - ProtoComp10.IMUX.25 - SLICE_X0Y16.AX net (fanout=2) 1.627 FSB_A_0_IBUF - SLICE_X0Y16.CLK Tckdi (-Th) -0.041 AR<3> - AR_0 - ------------------------------------------------- --------------------------- - Total 2.431ns (0.804ns logic, 1.627ns route) - (33.1% logic, 66.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to AR_0 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y16.CLK net (fanout=17) 0.806 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.689ns (-3.199ns logic, 1.510ns route) - --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.057ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: FSB_A<0> (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.774ns (Levels of Logic = 4) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: FSB_A<0> to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N4.I Tiopi 0.763 FSB_A<0> - FSB_A<0> - FSB_A_0_IBUF - ProtoComp10.IMUX.25 - SLICE_X0Y19.A6 net (fanout=2) 1.556 FSB_A_0_IBUF - SLICE_X0Y19.COUT Topcya 0.272 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3> - SLICE_X0Y20.COUT Tbyp 0.032 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CIN net (fanout=1) 0.001 Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7> - SLICE_X0Y21.CLK Tckcin (-Th) -0.149 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.774ns (1.216ns logic, 1.558ns route) - (43.8% logic, 56.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.641ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.D4), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 2.359ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: CPU_nAS (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 5.324ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: CPU_nAS to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H3.I Tiopi 1.557 CPU_nAS - CPU_nAS - CPU_nAS_IBUF - ProtoComp10.IMUX.20 - SLICE_X0Y21.D4 net (fanout=1) 3.250 CPU_nAS_IBUF - SLICE_X0Y21.CLK Tas 0.517 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_lut - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 5.324ns (2.074ns logic, 3.250ns route) - (39.0% logic, 61.0% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.D4), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 3.896ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: CPU_nAS (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 2.613ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: CPU_nAS to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - H3.I Tiopi 0.763 CPU_nAS - CPU_nAS - CPU_nAS_IBUF - ProtoComp10.IMUX.20 - SLICE_X0Y21.D4 net (fanout=1) 1.546 CPU_nAS_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.304 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_lut - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 2.613ns (1.067ns logic, 1.546ns route) - (40.8% logic, 59.2% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 10.332ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.D5), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.668ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: INt (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 12.000ns - Data Path Delay: 6.015ns (Levels of Logic = 2) - Clock Path Delay: -3.903ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: INt to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - C2.I Tiopi 1.557 INt - INt - INt_IBUF - ProtoComp10.IMUX.35 - SLICE_X0Y21.D5 net (fanout=1) 3.941 INt_IBUF - SLICE_X0Y21.CLK Tas 0.517 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_lut - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 6.015ns (2.074ns logic, 3.941ns route) - (34.5% logic, 65.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.368 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.578 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.197 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.856 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.903ns (-6.300ns logic, 2.397ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point OUTt (SLICE_X0Y21.D5), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 4.292ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: INt (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 0.000ns - Data Path Delay: 3.009ns (Levels of Logic = 2) - Clock Path Delay: -1.697ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: INt to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - C2.I Tiopi 0.763 INt - INt - INt_IBUF - ProtoComp10.IMUX.35 - SLICE_X0Y21.D5 net (fanout=1) 1.942 INt_IBUF - SLICE_X0Y21.CLK Tah (-Th) -0.304 OUTt_OBUF - CPU_nAS_FSB_A[31]_AND_3_o1_lut - CPU_nAS_FSB_A[31]_AND_3_o1_cy - OUTt - ------------------------------------------------- --------------------------- - Total 3.009ns (1.067ns logic, 1.942ns route) - (35.5% logic, 64.5% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.230 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.759 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.063 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.798 FSBCLK - ------------------------------------------------- --------------------------- - Total -1.697ns (-3.199ns logic, 1.502ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN"; -For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). - - 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints - 0 timing errors detected. - Minimum allowable offset is 2.040ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (C3.PAD), 1 path --------------------------------------------------------------------------------- -Slack (slowest paths): 2.960ns (requirement - (clock arrival + clock path + data path + uncertainty)) - Source: OUTt (FF) - Destination: OUTt (PAD) +Slack (setup path): 11.311ns (requirement - (data path - clock path skew + uncertainty)) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLK_inst (FF) + Requirement: 15.000ns + Data Path Delay: 4.087ns (Levels of Logic = 1) + Clock Path Skew: 0.514ns (1.205 - 0.691) Source Clock: FSBCLK rising at 0.000ns - Requirement: 5.000ns - Data Path Delay: 5.799ns (Levels of Logic = 1) - Clock Path Delay: -4.173ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.116ns - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y61.DQ Tcko 0.525 cg/CPUCLKr + cg/CPUCLKr + SLICE_X20Y61.D6 net (fanout=3) 0.156 cg/CPUCLKr + SLICE_X20Y61.D Tilo 0.254 cg/CPUCLKr + ][292_3_INV_0 + OLOGIC_X1Y61.D1 net (fanout=3) 2.186 ][292_3 + OLOGIC_X1Y61.CLK0 Todck 0.966 CPUCLK_OBUF + cg/CPUCLK_inst + ------------------------------------------------- --------------------------- + Total 4.087ns (1.745ns logic, 2.342ns route) + (42.7% logic, 57.3% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y61.D2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.624ns (requirement - (data path - clock path skew + uncertainty)) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLK_inst (FF) + Requirement: 15.000ns + Data Path Delay: 3.774ns (Levels of Logic = 1) + Clock Path Skew: 0.514ns (1.205 - 0.691) + Source Clock: FSBCLK rising at 0.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.116ns + + Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y61.DQ Tcko 0.525 cg/CPUCLKr + cg/CPUCLKr + SLICE_X20Y61.D6 net (fanout=3) 0.156 cg/CPUCLKr + SLICE_X20Y61.D Tilo 0.254 cg/CPUCLKr + ][292_3_INV_0 + OLOGIC_X1Y61.D2 net (fanout=3) 2.008 ][292_3 + OLOGIC_X1Y61.CLK0 Todck 0.831 CPUCLK_OBUF + cg/CPUCLK_inst + ------------------------------------------------- --------------------------- + Total 3.774ns (1.610ns logic, 2.164ns route) + (42.7% logic, 57.3% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y61.D2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.401ns (requirement - (data path - clock path skew + uncertainty)) + Source: cg/CPUCLKr (FF) + Destination: cg/FPUCLK_inst (FF) + Requirement: 15.000ns + Data Path Delay: 2.966ns (Levels of Logic = 0) + Clock Path Skew: 0.483ns (0.800 - 0.317) + Source Clock: FSBCLK rising at 0.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.116ns + + Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/FPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y61.DQ Tcko 0.525 cg/CPUCLKr + cg/CPUCLKr + OLOGIC_X11Y61.D2 net (fanout=3) 1.610 cg/CPUCLKr + OLOGIC_X11Y61.CLK0 Todck 0.831 FPUCLK_OBUF + cg/FPUCLK_inst + ------------------------------------------------- --------------------------- + Total 2.966ns (1.356ns logic, 1.610ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; +-------------------------------------------------------------------------------- + +Paths for end point cg/CPUCLKr (SLICE_X20Y61.D6), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.458ns (requirement - (clock path skew + uncertainty - data path)) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLKr (FF) + Requirement: 0.000ns + Data Path Delay: 0.458ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 15.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/CPUCLKr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y61.DQ Tcko 0.234 cg/CPUCLKr + cg/CPUCLKr + SLICE_X20Y61.D6 net (fanout=3) 0.027 cg/CPUCLKr + SLICE_X20Y61.CLK Tah (-Th) -0.197 cg/CPUCLKr + ][292_3_INV_0 + cg/CPUCLKr + ------------------------------------------------- --------------------------- + Total 0.458ns (0.431ns logic, 0.027ns route) + (94.1% logic, 5.9% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y61.D1), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.665ns (requirement - (clock path skew + uncertainty - data path)) + Source: cg/CPUCLKr (FF) + Destination: cg/FPUCLK_inst (FF) + Requirement: 0.000ns + Data Path Delay: 0.857ns (Levels of Logic = 0) + Clock Path Skew: 0.192ns (0.269 - 0.077) + Source Clock: FSBCLK rising at 15.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/FPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y61.DQ Tcko 0.234 cg/CPUCLKr + cg/CPUCLKr + OLOGIC_X11Y61.D1 net (fanout=3) 0.293 cg/CPUCLKr + OLOGIC_X11Y61.CLK0 Tockd (-Th) -0.330 FPUCLK_OBUF + cg/FPUCLK_inst + ------------------------------------------------- --------------------------- + Total 0.857ns (0.564ns logic, 0.293ns route) + (65.8% logic, 34.2% route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ENBRDEN), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.736ns (requirement - (clock path skew + uncertainty - data path)) + Source: cg/CPUCLKr (FF) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Requirement: 0.000ns + Data Path Delay: 0.736ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 15.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: cg/CPUCLKr to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X20Y61.DQ Tcko 0.234 cg/CPUCLKr + cg/CPUCLKr + SLICE_X20Y61.D6 net (fanout=3) 0.027 cg/CPUCLKr + SLICE_X20Y61.D Tilo 0.156 cg/CPUCLKr + ][292_3_INV_0 + RAMB8_X1Y31.ENBRDEN net (fanout=3) 0.363 ][292_3 + RAMB8_X1Y31.CLKBRDCLKTrckc_ENB (-Th) 0.044 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ------------------------------------------------- --------------------------- + Total 0.736ns (0.346ns logic, 0.390ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 11.430ns (period - min period limit) + Period: 15.000ns + Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax)) + Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK + Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK + Location pin: RAMB8_X1Y31.CLKAWRCLK + Clock network: FSBCLK +-------------------------------------------------------------------------------- +Slack: 11.430ns (period - min period limit) + Period: 15.000ns + Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) + Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK + Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK + Location pin: RAMB8_X1Y31.CLKBRDCLK + Clock network: FSBCLK +-------------------------------------------------------------------------------- +Slack: 12.334ns (period - min period limit) + Period: 15.000ns + Min period limit: 2.666ns (375.094MHz) (Tbcper_I) + Physical resource: cg/pll/clkout1_buf/I0 + Logical resource: cg/pll/clkout1_buf/I0 + Location pin: BUFGMUX_X3Y13.I0 + Clock network: cg/pll/clkout0 +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Unconstrained OFFSET IN BEFORE analysis for clock "FSBCLK" + + 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 8.910ns. +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path +-------------------------------------------------------------------------------- +Offset (setup paths): 8.910ns (data path - clock path + uncertainty) + Source: FSB_A<6> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Data Path Delay: 4.600ns (Levels of Logic = 1) + Clock Path Delay: -4.014ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns - Maximum Clock Path at Slow Process Corner: CLKIN to OUTt + Maximum Data Path at Slow Process Corner: FSB_A<6> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + RAMB8_X1Y31.ADDRBRDADDR9 net (fanout=13) 2.643 FSB_A_6_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.600ns (1.957ns logic, 2.643ns route) + (42.5% logic, 57.5% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.882 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.014ns (-6.437ns logic, 2.423ns route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +-------------------------------------------------------------------------------- +Offset (setup paths): 8.905ns (data path - clock path + uncertainty) + Source: FSB_A<4> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Data Path Delay: 4.595ns (Levels of Logic = 1) + Clock Path Delay: -4.014ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Data Path at Slow Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) 2.638 FSB_A_4_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.595ns (1.957ns logic, 2.638ns route) + (42.6% logic, 57.4% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.882 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.014ns (-6.437ns logic, 2.423ns route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path +-------------------------------------------------------------------------------- +Offset (setup paths): 8.878ns (data path - clock path + uncertainty) + Source: FSB_A<5> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Data Path Delay: 4.568ns (Levels of Logic = 1) + Clock Path Delay: -4.014ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Data Path at Slow Process Corner: FSB_A<5> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + RAMB8_X1Y31.ADDRBRDADDR8 net (fanout=13) 2.611 FSB_A_5_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.568ns (1.957ns logic, 2.611ns route) + (42.8% logic, 57.2% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.882 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.014ns (-6.437ns logic, 2.423ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: Unconstrained OFFSET IN BEFORE analysis for clock "FSBCLK" + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +-------------------------------------------------------------------------------- +Offset (hold paths): 4.005ns (data path - clock path + uncertainty) + Source: FSB_A<4> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Data Path Delay: 1.886ns (Levels of Logic = 1) + Clock Path Delay: -1.823ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E13.I Tiopi 0.763 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) 1.189 FSB_A_4_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 1.886ns (0.697ns logic, 1.189ns route) + (37.0% logic, 63.0% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.824 FSBCLK + ------------------------------------------------- --------------------------- + Total -1.823ns (-3.351ns logic, 1.528ns route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path +-------------------------------------------------------------------------------- +Offset (hold paths): 4.007ns (data path - clock path + uncertainty) + Source: FSB_A<3> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Data Path Delay: 1.888ns (Levels of Logic = 1) + Clock Path Delay: -1.823ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<3> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E11.I Tiopi 0.763 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + RAMB8_X1Y31.ADDRBRDADDR6 net (fanout=13) 1.191 FSB_A_3_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 1.888ns (0.697ns logic, 1.191ns route) + (36.9% logic, 63.1% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.824 FSBCLK + ------------------------------------------------- --------------------------- + Total -1.823ns (-3.351ns logic, 1.528ns route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path +-------------------------------------------------------------------------------- +Offset (hold paths): 4.008ns (data path - clock path + uncertainty) + Source: FSB_A<2> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Data Path Delay: 1.889ns (Levels of Logic = 1) + Clock Path Delay: -1.823ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<2> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + B14.I Tiopi 0.763 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + RAMB8_X1Y31.ADDRBRDADDR5 net (fanout=13) 1.192 FSB_A_2_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 1.889ns (0.697ns logic, 1.192ns route) + (36.9% logic, 63.1% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.824 FSBCLK + ------------------------------------------------- --------------------------- + Total -1.823ns (-3.351ns logic, 1.528ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Unconstrained OFFSET OUT AFTER analysis for clock "FSBCLK" + + 36 paths analyzed, 36 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. + Maximum allowable offset is 5.139ns. +-------------------------------------------------------------------------------- + +Paths for end point FSB_D<2> (C5.PAD), 1 path +-------------------------------------------------------------------------------- +Offset (slowest paths): 5.139ns (clock path + data path + uncertainty) + Source: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination: FSB_D<2> (PAD) + Source Clock: FSBCLK rising at 0.000ns + Data Path Delay: 9.129ns (Levels of Logic = 1) + Clock Path Delay: -4.286ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- J4.I Tiopi 1.037 CLKIN CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.643 CLKGEN_inst/instance_name/clkin1 + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.643 cg/pll/clkin1 BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.039 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.505 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.209 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 1.440 FSBCLK + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.178 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.209 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 1.466 FSBCLK ------------------------------------------------- --------------------------- - Total -4.173ns (-7.603ns logic, 3.430ns route) + Total -4.286ns (-7.742ns logic, 3.456ns route) - Maximum Data Path at Slow Process Corner: OUTt to OUTt + Maximum Data Path at Slow Process Corner: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram to FSB_D<2> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X0Y21.DQ Tcko 0.525 OUTt_OBUF - OUTt - C3.O net (fanout=1) 3.292 OUTt_OBUF - C3.PAD Tioop 1.982 OUTt - OUTt_OBUF - OUTt + RAMB8_X1Y31.DOADO2 Trcko_DOA 2.100 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + C5.O net (fanout=1) 4.047 FSB_D_2_OBUF + C5.PAD Tioop 2.982 FSB_D<2> + FSB_D_2_OBUF + FSB_D<2> ------------------------------------------------- --------------------------- - Total 5.799ns (2.507ns logic, 3.292ns route) - (43.2% logic, 56.8% route) + Total 9.129ns (5.082ns logic, 4.047ns route) + (55.7% logic, 44.3% route) -------------------------------------------------------------------------------- -Fastest Paths: COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN"; +Paths for end point FSB_D<4> (A6.PAD), 1 path -------------------------------------------------------------------------------- - -Paths for end point OUTt (C3.PAD), 1 path --------------------------------------------------------------------------------- -Delay (fastest paths): 0.500ns (clock arrival + clock path + data path - uncertainty) - Source: OUTt (FF) - Destination: OUTt (PAD) +Offset (slowest paths): 5.039ns (clock path + data path + uncertainty) + Source: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination: FSB_D<4> (PAD) Source Clock: FSBCLK rising at 0.000ns - Data Path Delay: 2.520ns (Levels of Logic = 1) - Clock Path Delay: -1.606ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns + Data Path Delay: 9.029ns (Levels of Logic = 1) + Clock Path Delay: -4.286ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns - Minimum Clock Path at Fast Process Corner: CLKIN to OUTt + Maximum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - J4.I Tiopi 0.321 CLKIN + J4.I Tiopi 1.037 CLKIN CLKIN - CLKGEN_inst/instance_name/clkin1_buf - ProtoComp10.IMUX.36 - BUFIO2_X0Y23.I net (fanout=1) 0.220 CLKGEN_inst/instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.643 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.263 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.246 CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X2Y3.I0 net (fanout=1) 0.158 CLKGEN_inst/instance_name/clkout0 - BUFGMUX_X2Y3.O Tgi0o 0.059 CLKGEN_inst/instance_name/clkout1_buf - CLKGEN_inst/instance_name/clkout1_buf - SLICE_X0Y21.CLK net (fanout=17) 0.497 FSBCLK + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.178 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.209 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 1.466 FSBCLK ------------------------------------------------- --------------------------- - Total -1.606ns (-2.744ns logic, 1.138ns route) + Total -4.286ns (-7.742ns logic, 3.456ns route) - Minimum Data Path at Fast Process Corner: OUTt to OUTt + Maximum Data Path at Slow Process Corner: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram to FSB_D<4> Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - SLICE_X0Y21.DQ Tcko 0.234 OUTt_OBUF - OUTt - C3.O net (fanout=1) 1.587 OUTt_OBUF - C3.PAD Tioop 0.699 OUTt - OUTt_OBUF - OUTt + RAMB8_X1Y31.DOADO4 Trcko_DOA 2.100 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + A6.O net (fanout=1) 3.947 FSB_D_4_OBUF + A6.PAD Tioop 2.982 FSB_D<4> + FSB_D_4_OBUF + FSB_D<4> ------------------------------------------------- --------------------------- - Total 2.520ns (0.933ns logic, 1.587ns route) + Total 9.029ns (5.082ns logic, 3.947ns route) + (56.3% logic, 43.7% route) + +-------------------------------------------------------------------------------- + +Paths for end point FSB_D<0> (A5.PAD), 1 path +-------------------------------------------------------------------------------- +Offset (slowest paths): 4.996ns (clock path + data path + uncertainty) + Source: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination: FSB_D<0> (PAD) + Source Clock: FSBCLK rising at 0.000ns + Data Path Delay: 8.986ns (Levels of Logic = 1) + Clock Path Delay: -4.286ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 1.037 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.643 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.178 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.209 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 1.466 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.286ns (-7.742ns logic, 3.456ns route) + + Maximum Data Path at Slow Process Corner: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram to FSB_D<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + RAMB8_X1Y31.DOADO0 Trcko_DOA 2.100 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + A5.O net (fanout=1) 3.904 FSB_D_0_OBUF + A5.PAD Tioop 2.982 FSB_D<0> + FSB_D_0_OBUF + FSB_D<0> + ------------------------------------------------- --------------------------- + Total 8.986ns (5.082ns logic, 3.904ns route) + (56.6% logic, 43.4% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: Unconstrained OFFSET OUT AFTER analysis for clock "FSBCLK" + +-------------------------------------------------------------------------------- + +Paths for end point RAMCLK0 (A14.PAD), 1 path +-------------------------------------------------------------------------------- +Offset (fastest paths): -0.475ns (clock path + data path - uncertainty) + Source: cg/RAMCLK0_inst (FF) + Destination: RAMCLK0 (PAD) + Source Clock: FSBCLK rising at 0.000ns + Data Path Delay: 3.331ns (Levels of Logic = 1) + Clock Path Delay: -3.510ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Clock Path at Slow Process Corner: CLKIN to cg/RAMCLK0_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + OLOGIC_X11Y62.CLK0 net (fanout=17) 1.386 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.510ns (-6.437ns logic, 2.927ns route) + + Minimum Data Path at Slow Process Corner: cg/RAMCLK0_inst to RAMCLK0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X11Y62.OQ Tockq 1.090 RAMCLK0_OBUF + cg/RAMCLK0_inst + A14.O net (fanout=1) 0.375 RAMCLK0_OBUF + A14.PAD Tioop 1.866 RAMCLK0 + RAMCLK0_OBUF + RAMCLK0 + ------------------------------------------------- --------------------------- + Total 3.331ns (2.956ns logic, 0.375ns route) + (88.7% logic, 11.3% route) + +-------------------------------------------------------------------------------- + +Paths for end point RAMCLK1 (C4.PAD), 1 path +-------------------------------------------------------------------------------- +Offset (fastest paths): -0.436ns (clock path + data path - uncertainty) + Source: cg/RAMCLK1_inst (FF) + Destination: RAMCLK1 (PAD) + Source Clock: FSBCLK rising at 0.000ns + Data Path Delay: 3.331ns (Levels of Logic = 1) + Clock Path Delay: -3.471ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Clock Path at Slow Process Corner: CLKIN to cg/RAMCLK1_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + OLOGIC_X1Y63.CLK0 net (fanout=17) 1.425 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.471ns (-6.437ns logic, 2.966ns route) + + Minimum Data Path at Slow Process Corner: cg/RAMCLK1_inst to RAMCLK1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X1Y63.OQ Tockq 1.090 RAMCLK1_OBUF + cg/RAMCLK1_inst + C4.O net (fanout=1) 0.375 RAMCLK1_OBUF + C4.PAD Tioop 1.866 RAMCLK1 + RAMCLK1_OBUF + RAMCLK1 + ------------------------------------------------- --------------------------- + Total 3.331ns (2.956ns logic, 0.375ns route) + (88.7% logic, 11.3% route) + +-------------------------------------------------------------------------------- + +Paths for end point FPUCLK (D11.PAD), 1 path +-------------------------------------------------------------------------------- +Offset (fastest paths): -0.424ns (clock path + data path - uncertainty) + Source: cg/FPUCLK_inst (FF) + Destination: FPUCLK (PAD) + Source Clock: FSBCLK rising at 0.000ns + Data Path Delay: 3.382ns (Levels of Logic = 1) + Clock Path Delay: -3.510ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Clock Path at Slow Process Corner: CLKIN to cg/FPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + OLOGIC_X11Y61.CLK0 net (fanout=17) 1.386 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.510ns (-6.437ns logic, 2.927ns route) + + Minimum Data Path at Slow Process Corner: cg/FPUCLK_inst to FPUCLK + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X11Y61.OQ Tockq 1.090 FPUCLK_OBUF + cg/FPUCLK_inst + D11.O net (fanout=1) 0.426 FPUCLK_OBUF + D11.PAD Tioop 1.866 FPUCLK + FPUCLK_OBUF + FPUCLK + ------------------------------------------------- --------------------------- + Total 3.382ns (2.956ns logic, 0.426ns route) + (87.4% logic, 12.6% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Unconstrained OFFSET OUT AFTER analysis for clock +"cg/pll/clkfb_bufg_out" + + 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Maximum allowable offset is 15.120ns. +-------------------------------------------------------------------------------- + +Paths for end point CLKFB_OUT (A4.PAD), 2 paths +-------------------------------------------------------------------------------- +Offset (slowest paths): 15.120ns (clock path + data path + uncertainty) + Source: cg/pll/clkfbout_oddr (FF) + Destination: CLKFB_OUT (PAD) + Source Clock: cg/pll/clkfb_bufg_out falling at 15.000ns + Data Path Delay: 1.466ns (Levels of Logic = 1) + Clock Path Delay: -1.603ns (Levels of Logic = 4) + Clock Uncertainty: 0.257ns + + Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.141ns + Phase Error (PE): 0.182ns + + Maximum Clock Path at Fast Process Corner: CLKIN to cg/pll/clkfbout_oddr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 cg/pll/clkfbout + BUFGMUX_X2Y3.O Tgi0o 0.063 cg/pll/clkfbout_bufg + cg/pll/clkfbout_bufg + OLOGIC_X1Y62.CLK1 net (fanout=2) 1.044 cg/pll/clkfb_bufg_out + ------------------------------------------------- --------------------------- + Total -1.603ns (-3.351ns logic, 1.748ns route) + + Maximum Data Path at Fast Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X1Y62.OQ Tockq 0.451 CLKFB_OUT_OBUF + cg/pll/clkfbout_oddr + A4.O net (fanout=1) 0.273 CLKFB_OUT_OBUF + A4.PAD Tioop 0.742 CLKFB_OUT + CLKFB_OUT_OBUF + CLKFB_OUT + ------------------------------------------------- --------------------------- + Total 1.466ns (1.193ns logic, 0.273ns route) + (81.4% logic, 18.6% route) + +-------------------------------------------------------------------------------- +Offset (slowest paths): 0.189ns (clock path + data path + uncertainty) + Source: cg/pll/clkfbout_oddr (FF) + Destination: CLKFB_OUT (PAD) + Source Clock: cg/pll/clkfb_bufg_out rising at 0.000ns + Data Path Delay: 1.460ns (Levels of Logic = 1) + Clock Path Delay: -1.528ns (Levels of Logic = 4) + Clock Uncertainty: 0.257ns + + Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.141ns + Phase Error (PE): 0.182ns + + Maximum Clock Path at Fast Process Corner: CLKIN to cg/pll/clkfbout_oddr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 cg/pll/clkfbout + BUFGMUX_X2Y3.O Tgi0o 0.063 cg/pll/clkfbout_bufg + cg/pll/clkfbout_bufg + OLOGIC_X1Y62.CLK0 net (fanout=2) 1.119 cg/pll/clkfb_bufg_out + ------------------------------------------------- --------------------------- + Total -1.528ns (-3.351ns logic, 1.823ns route) + + Maximum Data Path at Fast Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X1Y62.OQ Tockq 0.445 CLKFB_OUT_OBUF + cg/pll/clkfbout_oddr + A4.O net (fanout=1) 0.273 CLKFB_OUT_OBUF + A4.PAD Tioop 0.742 CLKFB_OUT + CLKFB_OUT_OBUF + CLKFB_OUT + ------------------------------------------------- --------------------------- + Total 1.460ns (1.187ns logic, 0.273ns route) + (81.3% logic, 18.7% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: Unconstrained OFFSET OUT AFTER analysis for clock "cg/pll/clkfb_bufg_out" + +-------------------------------------------------------------------------------- + +Paths for end point CLKFB_OUT (A4.PAD), 2 paths +-------------------------------------------------------------------------------- +Offset (fastest paths): -0.348ns (clock path + data path - uncertainty) + Source: cg/pll/clkfbout_oddr (FF) + Destination: CLKFB_OUT (PAD) + Source Clock: cg/pll/clkfb_bufg_out rising at 0.000ns + Data Path Delay: 3.331ns (Levels of Logic = 1) + Clock Path Delay: -3.422ns (Levels of Logic = 4) + Clock Uncertainty: 0.257ns + + Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.141ns + Phase Error (PE): 0.182ns + + Minimum Clock Path at Slow Process Corner: CLKIN to cg/pll/clkfbout_oddr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 cg/pll/clkfbout + BUFGMUX_X2Y3.O Tgi0o 0.197 cg/pll/clkfbout_bufg + cg/pll/clkfbout_bufg + OLOGIC_X1Y62.CLK0 net (fanout=2) 1.474 cg/pll/clkfb_bufg_out + ------------------------------------------------- --------------------------- + Total -3.422ns (-6.437ns logic, 3.015ns route) + + Minimum Data Path at Slow Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X1Y62.OQ Tockq 1.090 CLKFB_OUT_OBUF + cg/pll/clkfbout_oddr + A4.O net (fanout=1) 0.375 CLKFB_OUT_OBUF + A4.PAD Tioop 1.866 CLKFB_OUT + CLKFB_OUT_OBUF + CLKFB_OUT + ------------------------------------------------- --------------------------- + Total 3.331ns (2.956ns logic, 0.375ns route) + (88.7% logic, 11.3% route) + +-------------------------------------------------------------------------------- +Offset (fastest paths): 14.592ns (clock path + data path - uncertainty) + Source: cg/pll/clkfbout_oddr (FF) + Destination: CLKFB_OUT (PAD) + Source Clock: cg/pll/clkfb_bufg_out falling at 15.000ns + Data Path Delay: 3.331ns (Levels of Logic = 1) + Clock Path Delay: -3.482ns (Levels of Logic = 4) + Clock Uncertainty: 0.257ns + + Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.141ns + Phase Error (PE): 0.182ns + + Minimum Clock Path at Slow Process Corner: CLKIN to cg/pll/clkfbout_oddr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 cg/pll/clkfbout + BUFGMUX_X2Y3.O Tgi0o 0.197 cg/pll/clkfbout_bufg + cg/pll/clkfbout_bufg + OLOGIC_X1Y62.CLK1 net (fanout=2) 1.414 cg/pll/clkfb_bufg_out + ------------------------------------------------- --------------------------- + Total -3.482ns (-6.437ns logic, 2.955ns route) + + Minimum Data Path at Slow Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X1Y62.OQ Tockq 1.090 CLKFB_OUT_OBUF + cg/pll/clkfbout_oddr + A4.O net (fanout=1) 0.375 CLKFB_OUT_OBUF + A4.PAD Tioop 1.866 CLKFB_OUT + CLKFB_OUT_OBUF + CLKFB_OUT + ------------------------------------------------- --------------------------- + Total 3.331ns (2.956ns logic, 0.375ns route) + (88.7% logic, 11.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: Unconstrained path analysis + + 188 paths analyzed, 58 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Maximum delay is 12.945ns. +-------------------------------------------------------------------------------- + +Paths for end point CPU_nSTERM (D12.PAD), 131 paths +-------------------------------------------------------------------------------- +Delay (setup path): 12.945ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.945ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X16Y51.A3 net (fanout=13) 4.264 FSB_A_4_IBUF + SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.945ns (4.513ns logic, 8.432ns route) + (34.9% logic, 65.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.836ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.836ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X16Y51.A3 net (fanout=13) 4.264 FSB_A_4_IBUF + SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.836ns (4.417ns logic, 8.419ns route) + (34.4% logic, 65.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.820ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.820ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X16Y51.A1 net (fanout=13) 4.139 FSB_A_2_IBUF + SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.820ns (4.513ns logic, 8.307ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.811ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.811ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X16Y51.B1 net (fanout=13) 4.312 FSB_A_2_IBUF + SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.811ns (4.513ns logic, 8.298ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.711ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.711ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X16Y51.A1 net (fanout=13) 4.139 FSB_A_2_IBUF + SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.711ns (4.417ns logic, 8.294ns route) + (34.7% logic, 65.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.708ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.708ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X16Y51.A2 net (fanout=13) 4.027 FSB_A_3_IBUF + SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.708ns (4.513ns logic, 8.195ns route) + (35.5% logic, 64.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.691ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.691ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X16Y51.B1 net (fanout=13) 4.312 FSB_A_2_IBUF + SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.691ns (4.350ns logic, 8.341ns route) + (34.3% logic, 65.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.659ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.659ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X16Y51.B3 net (fanout=13) 4.160 FSB_A_4_IBUF + SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.659ns (4.513ns logic, 8.146ns route) + (35.7% logic, 64.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.599ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.599ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X16Y51.A2 net (fanout=13) 4.027 FSB_A_3_IBUF + SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.599ns (4.417ns logic, 8.182ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.539ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.539ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X16Y51.B3 net (fanout=13) 4.160 FSB_A_4_IBUF + SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.539ns (4.350ns logic, 8.189ns route) + (34.7% logic, 65.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.537ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.537ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X16Y51.B2 net (fanout=13) 4.038 FSB_A_3_IBUF + SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.537ns (4.513ns logic, 8.024ns route) + (36.0% logic, 64.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.517ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.517ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y50.B1 net (fanout=13) 4.008 FSB_A_2_IBUF + SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.517ns (4.580ns logic, 7.937ns route) + (36.6% logic, 63.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.435ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.435ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X16Y51.A4 net (fanout=13) 3.754 FSB_A_5_IBUF + SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.435ns (4.513ns logic, 7.922ns route) + (36.3% logic, 63.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.417ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.417ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X16Y51.B2 net (fanout=13) 4.038 FSB_A_3_IBUF + SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.417ns (4.350ns logic, 8.067ns route) + (35.0% logic, 65.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.398ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.398ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y50.B3 net (fanout=13) 3.889 FSB_A_4_IBUF + SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.398ns (4.580ns logic, 7.818ns route) + (36.9% logic, 63.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.356ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.356ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X16Y51.A5 net (fanout=13) 3.675 FSB_A_6_IBUF + SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.356ns (4.513ns logic, 7.843ns route) + (36.5% logic, 63.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.345ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.345ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y49.A3 net (fanout=13) 4.019 FSB_A_4_IBUF + SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.345ns (4.532ns logic, 7.813ns route) + (36.7% logic, 63.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.326ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.326ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X16Y51.A4 net (fanout=13) 3.754 FSB_A_5_IBUF + SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.326ns (4.417ns logic, 7.909ns route) + (35.8% logic, 64.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.323ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.323ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X16Y51.B5 net (fanout=13) 3.824 FSB_A_6_IBUF + SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.323ns (4.513ns logic, 7.810ns route) + (36.6% logic, 63.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.274ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.274ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X16Y51.B4 net (fanout=13) 3.775 FSB_A_5_IBUF + SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.274ns (4.513ns logic, 7.761ns route) + (36.8% logic, 63.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.247ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.247ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X16Y51.A5 net (fanout=13) 3.675 FSB_A_6_IBUF + SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.247ns (4.417ns logic, 7.830ns route) + (36.1% logic, 63.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.205ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.205ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y49.A1 net (fanout=13) 3.879 FSB_A_2_IBUF + SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.205ns (4.532ns logic, 7.673ns route) + (37.1% logic, 62.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.203ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.203ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X16Y51.B5 net (fanout=13) 3.824 FSB_A_6_IBUF + SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.203ns (4.350ns logic, 7.853ns route) + (35.6% logic, 64.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.173ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.173ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y50.B1 net (fanout=13) 4.008 FSB_A_2_IBUF + SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.173ns (4.508ns logic, 7.665ns route) (37.0% logic, 63.0% route) -------------------------------------------------------------------------------- +Delay (setup path): 12.154ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.154ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X16Y51.B4 net (fanout=13) 3.775 FSB_A_5_IBUF + SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.154ns (4.350ns logic, 7.804ns route) + (35.8% logic, 64.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.141ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.141ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y49.B3 net (fanout=13) 4.080 FSB_A_4_IBUF + SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.141ns (4.604ns logic, 7.537ns route) + (37.9% logic, 62.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.113ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.113ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y49.B1 net (fanout=13) 4.052 FSB_A_2_IBUF + SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.113ns (4.604ns logic, 7.509ns route) + (38.0% logic, 62.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.072ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.072ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y49.A3 net (fanout=13) 4.019 FSB_A_4_IBUF + SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.072ns (4.580ns logic, 7.492ns route) + (37.9% logic, 62.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.054ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.054ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y50.B3 net (fanout=13) 3.889 FSB_A_4_IBUF + SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.054ns (4.508ns logic, 7.546ns route) + (37.4% logic, 62.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.014ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.014ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y49.A4 net (fanout=13) 3.688 FSB_A_5_IBUF + SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.014ns (4.532ns logic, 7.482ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 12.007ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 12.007ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y50.B4 net (fanout=13) 3.498 FSB_A_5_IBUF + SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 12.007ns (4.580ns logic, 7.427ns route) + (38.1% logic, 61.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.943ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.943ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y49.A5 net (fanout=13) 3.617 FSB_A_6_IBUF + SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.943ns (4.532ns logic, 7.411ns route) + (37.9% logic, 62.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.932ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.932ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y49.A1 net (fanout=13) 3.879 FSB_A_2_IBUF + SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.932ns (4.580ns logic, 7.352ns route) + (38.4% logic, 61.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.927ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.927ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y49.A2 net (fanout=13) 3.601 FSB_A_3_IBUF + SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.927ns (4.532ns logic, 7.395ns route) + (38.0% logic, 62.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.926ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.926ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y50.A1 net (fanout=13) 3.835 FSB_A_2_IBUF + SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.926ns (4.457ns logic, 7.469ns route) + (37.4% logic, 62.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.919ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.919ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y50.A3 net (fanout=13) 3.828 FSB_A_4_IBUF + SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.919ns (4.457ns logic, 7.462ns route) + (37.4% logic, 62.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.901ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.901ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y50.B2 net (fanout=13) 3.392 FSB_A_3_IBUF + SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.901ns (4.580ns logic, 7.321ns route) + (38.5% logic, 61.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.900ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.900ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y50.B5 net (fanout=13) 3.391 FSB_A_6_IBUF + SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.900ns (4.580ns logic, 7.320ns route) + (38.5% logic, 61.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.900ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.900ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y49.B3 net (fanout=13) 4.080 FSB_A_4_IBUF + SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.900ns (4.532ns logic, 7.368ns route) + (38.1% logic, 61.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.872ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.872ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y49.B1 net (fanout=13) 4.052 FSB_A_2_IBUF + SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.872ns (4.532ns logic, 7.340ns route) + (38.2% logic, 61.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.749ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.749ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y49.B4 net (fanout=13) 3.688 FSB_A_5_IBUF + SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.749ns (4.604ns logic, 7.145ns route) + (39.2% logic, 60.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.741ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.741ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y49.A4 net (fanout=13) 3.688 FSB_A_5_IBUF + SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.741ns (4.580ns logic, 7.161ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.720ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.720ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y52.A1 net (fanout=13) 3.666 FSB_A_2_IBUF + SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.720ns (4.350ns logic, 7.370ns route) + (37.1% logic, 62.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.705ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.705ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y50.A1 net (fanout=13) 3.835 FSB_A_2_IBUF + SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.705ns (4.385ns logic, 7.320ns route) + (37.5% logic, 62.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.698ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.698ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y50.A3 net (fanout=13) 3.828 FSB_A_4_IBUF + SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.698ns (4.385ns logic, 7.313ns route) + (37.5% logic, 62.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.696ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.696ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y51.A1 net (fanout=13) 3.660 FSB_A_2_IBUF + SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.696ns (4.417ns logic, 7.279ns route) + (37.8% logic, 62.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.673ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.673ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y49.B2 net (fanout=13) 3.612 FSB_A_3_IBUF + SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.673ns (4.604ns logic, 7.069ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.670ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.670ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y52.A3 net (fanout=13) 3.616 FSB_A_4_IBUF + SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.670ns (4.350ns logic, 7.320ns route) + (37.3% logic, 62.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.670ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.670ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y49.A5 net (fanout=13) 3.617 FSB_A_6_IBUF + SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.670ns (4.580ns logic, 7.090ns route) + (39.2% logic, 60.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.668ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.668ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y51.A3 net (fanout=13) 3.632 FSB_A_4_IBUF + SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.668ns (4.417ns logic, 7.251ns route) + (37.9% logic, 62.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.663ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.663ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y50.B4 net (fanout=13) 3.498 FSB_A_5_IBUF + SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.663ns (4.508ns logic, 7.155ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.654ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.654ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y49.A2 net (fanout=13) 3.601 FSB_A_3_IBUF + SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.654ns (4.580ns logic, 7.074ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.642ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.642ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y49.B5 net (fanout=13) 3.581 FSB_A_6_IBUF + SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.642ns (4.604ns logic, 7.038ns route) + (39.5% logic, 60.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.633ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.633ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y52.A1 net (fanout=13) 3.666 FSB_A_2_IBUF + SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.633ns (4.513ns logic, 7.120ns route) + (38.8% logic, 61.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.589ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.589ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y50.A4 net (fanout=13) 3.498 FSB_A_5_IBUF + SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.589ns (4.457ns logic, 7.132ns route) + (38.5% logic, 61.5% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.583ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.583ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y52.A3 net (fanout=13) 3.616 FSB_A_4_IBUF + SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.583ns (4.513ns logic, 7.070ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.560ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.560ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y51.B1 net (fanout=13) 3.833 FSB_A_2_IBUF + SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.560ns (4.366ns logic, 7.194ns route) + (37.8% logic, 62.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.557ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.557ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y50.B2 net (fanout=13) 3.392 FSB_A_3_IBUF + SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.557ns (4.508ns logic, 7.049ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.556ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.556ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y50.B5 net (fanout=13) 3.391 FSB_A_6_IBUF + SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3> + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.556ns (4.508ns logic, 7.048ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.553ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.553ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y52.B3 net (fanout=13) 3.496 FSB_A_4_IBUF + SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.553ns (4.422ns logic, 7.131ns route) + (38.3% logic, 61.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.518ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.518ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y50.A5 net (fanout=13) 3.427 FSB_A_6_IBUF + SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.518ns (4.457ns logic, 7.061ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.508ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.508ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y49.B4 net (fanout=13) 3.688 FSB_A_5_IBUF + SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.508ns (4.532ns logic, 6.976ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.504ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.504ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y51.B1 net (fanout=13) 3.833 FSB_A_2_IBUF + SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.504ns (4.417ns logic, 7.087ns route) + (38.4% logic, 61.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.472ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.472ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y50.A2 net (fanout=13) 3.381 FSB_A_3_IBUF + SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.472ns (4.457ns logic, 7.015ns route) + (38.9% logic, 61.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.454ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.454ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y52.B1 net (fanout=13) 3.397 FSB_A_2_IBUF + SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.454ns (4.422ns logic, 7.032ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.435ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.435ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y52.B3 net (fanout=13) 3.496 FSB_A_4_IBUF + SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.435ns (4.385ns logic, 7.050ns route) + (38.3% logic, 61.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.432ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.432ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y49.B2 net (fanout=13) 3.612 FSB_A_3_IBUF + SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.432ns (4.532ns logic, 6.900ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.424ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.424ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y52.B2 net (fanout=13) 3.367 FSB_A_3_IBUF + SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.424ns (4.422ns logic, 7.002ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.420ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.420ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y51.B3 net (fanout=13) 3.693 FSB_A_4_IBUF + SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.420ns (4.366ns logic, 7.054ns route) + (38.2% logic, 61.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.418ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.418ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y51.A2 net (fanout=13) 3.382 FSB_A_3_IBUF + SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.418ns (4.417ns logic, 7.001ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.410ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.410ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y52.A2 net (fanout=13) 3.356 FSB_A_3_IBUF + SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.410ns (4.350ns logic, 7.060ns route) + (38.1% logic, 61.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.401ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.401ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y49.B5 net (fanout=13) 3.581 FSB_A_6_IBUF + SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2> + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.401ns (4.532ns logic, 6.869ns route) + (39.8% logic, 60.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.398ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.398ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y53.B4 net (fanout=13) 3.374 FSB_A_4_IBUF + SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.398ns (4.294ns logic, 7.104ns route) + (37.7% logic, 62.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.368ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.368ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y50.A4 net (fanout=13) 3.498 FSB_A_5_IBUF + SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.368ns (4.385ns logic, 6.983ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.364ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.364ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y51.B3 net (fanout=13) 3.693 FSB_A_4_IBUF + SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.364ns (4.417ns logic, 6.947ns route) + (38.9% logic, 61.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.337ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.337ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y51.A4 net (fanout=13) 3.301 FSB_A_5_IBUF + SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.337ns (4.417ns logic, 6.920ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.336ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.336ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y52.B1 net (fanout=13) 3.397 FSB_A_2_IBUF + SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.336ns (4.385ns logic, 6.951ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.323ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.323ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y52.A2 net (fanout=13) 3.356 FSB_A_3_IBUF + SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.323ns (4.513ns logic, 6.810ns route) + (39.9% logic, 60.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.306ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.306ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y52.B2 net (fanout=13) 3.367 FSB_A_3_IBUF + SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.306ns (4.385ns logic, 6.921ns route) + (38.8% logic, 61.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.304ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.304ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y51.A1 net (fanout=13) 3.660 FSB_A_2_IBUF + SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.304ns (4.366ns logic, 6.938ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.297ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.297ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y50.A5 net (fanout=13) 3.427 FSB_A_6_IBUF + SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.297ns (4.385ns logic, 6.912ns route) + (38.8% logic, 61.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.276ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.276ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y51.A3 net (fanout=13) 3.632 FSB_A_4_IBUF + SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.276ns (4.366ns logic, 6.910ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.266ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.266ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y51.A5 net (fanout=13) 3.230 FSB_A_6_IBUF + SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.266ns (4.417ns logic, 6.849ns route) + (39.2% logic, 60.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.251ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.251ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y50.A2 net (fanout=13) 3.381 FSB_A_3_IBUF + SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.251ns (4.385ns logic, 6.866ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.245ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.245ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y53.B2 net (fanout=13) 3.221 FSB_A_2_IBUF + SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.245ns (4.294ns logic, 6.951ns route) + (38.2% logic, 61.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.209ns (data path) + Source: FSB_A<4> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.209ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + SLICE_X20Y53.A4 net (fanout=13) 3.374 FSB_A_4_IBUF + SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21> + SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF + l2pre/n0023<21>_rt + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.209ns (4.259ns logic, 6.950ns route) + (38.0% logic, 62.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.159ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.159ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y52.A4 net (fanout=13) 3.105 FSB_A_5_IBUF + SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.159ns (4.350ns logic, 6.809ns route) + (39.0% logic, 61.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.128ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.128ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y52.B4 net (fanout=13) 3.071 FSB_A_5_IBUF + SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.128ns (4.422ns logic, 6.706ns route) + (39.7% logic, 60.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.120ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.120ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y51.B2 net (fanout=13) 3.393 FSB_A_3_IBUF + SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.120ns (4.366ns logic, 6.754ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.092ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.092ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y53.B3 net (fanout=13) 3.068 FSB_A_3_IBUF + SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.092ns (4.294ns logic, 6.798ns route) + (38.7% logic, 61.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.081ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.081ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y52.A5 net (fanout=13) 3.027 FSB_A_6_IBUF + SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.081ns (4.350ns logic, 6.731ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.072ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.072ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y52.A4 net (fanout=13) 3.105 FSB_A_5_IBUF + SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.072ns (4.513ns logic, 6.559ns route) + (40.8% logic, 59.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.064ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.064ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y51.B2 net (fanout=13) 3.393 FSB_A_3_IBUF + SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.064ns (4.417ns logic, 6.647ns route) + (39.9% logic, 60.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.045ns (data path) + Source: FSB_A<2> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.045ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B14.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + SLICE_X20Y53.A2 net (fanout=13) 3.210 FSB_A_2_IBUF + SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21> + SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF + l2pre/n0023<21>_rt + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.045ns (4.259ns logic, 6.786ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.028ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.028ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y51.B4 net (fanout=13) 3.301 FSB_A_5_IBUF + SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.028ns (4.366ns logic, 6.662ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.026ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.026ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y51.A2 net (fanout=13) 3.382 FSB_A_3_IBUF + SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.026ns (4.366ns logic, 6.660ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.019ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.019ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y52.B5 net (fanout=13) 2.962 FSB_A_6_IBUF + SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9> + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.019ns (4.422ns logic, 6.597ns route) + (40.1% logic, 59.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 11.010ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 11.010ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y52.B4 net (fanout=13) 3.071 FSB_A_5_IBUF + SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 11.010ns (4.385ns logic, 6.625ns route) + (39.8% logic, 60.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.994ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.994ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y52.A5 net (fanout=13) 3.027 FSB_A_6_IBUF + SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13> + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.994ns (4.513ns logic, 6.481ns route) + (41.0% logic, 59.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.972ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.972ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y51.B4 net (fanout=13) 3.301 FSB_A_5_IBUF + SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.972ns (4.417ns logic, 6.555ns route) + (40.3% logic, 59.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.945ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.945ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y51.A4 net (fanout=13) 3.301 FSB_A_5_IBUF + SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.945ns (4.366ns logic, 6.579ns route) + (39.9% logic, 60.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.921ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.921ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y51.B5 net (fanout=13) 3.194 FSB_A_6_IBUF + SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.921ns (4.366ns logic, 6.555ns route) + (40.0% logic, 60.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.901ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.901ns (Levels of Logic = 5) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y52.B5 net (fanout=13) 2.962 FSB_A_6_IBUF + SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7> + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.901ns (4.385ns logic, 6.516ns route) + (40.2% logic, 59.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.874ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.874ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y51.A5 net (fanout=13) 3.230 FSB_A_6_IBUF + SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.874ns (4.366ns logic, 6.508ns route) + (40.2% logic, 59.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.865ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.865ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y51.B5 net (fanout=13) 3.194 FSB_A_6_IBUF + SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15> + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.865ns (4.417ns logic, 6.448ns route) + (40.7% logic, 59.3% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.842ns (data path) + Source: FSB_A<3> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.842ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E11.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + SLICE_X20Y53.A3 net (fanout=13) 3.007 FSB_A_3_IBUF + SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21> + SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF + l2pre/n0023<21>_rt + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.842ns (4.259ns logic, 6.583ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.832ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.832ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y53.B5 net (fanout=13) 2.808 FSB_A_5_IBUF + SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.832ns (4.294ns logic, 6.538ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.748ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.748ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y53.B6 net (fanout=13) 2.724 FSB_A_6_IBUF + SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20> + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.748ns (4.294ns logic, 6.454ns route) + (40.0% logic, 60.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.679ns (data path) + Source: FSB_A<5> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.679ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + SLICE_X20Y53.A5 net (fanout=13) 2.844 FSB_A_5_IBUF + SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21> + SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF + l2pre/n0023<21>_rt + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.679ns (4.259ns logic, 6.420ns route) + (39.9% logic, 60.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.629ns (data path) + Source: FSB_A<24> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.629ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<24> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + G12.I Tiopi 1.557 FSB_A<24> + FSB_A<24> + FSB_A_24_IBUF + ProtoComp0.IMUX.13 + SLICE_X22Y51.B1 net (fanout=1) 3.559 FSB_A_24_IBUF + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.629ns (4.163ns logic, 6.466ns route) + (39.2% logic, 60.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.559ns (data path) + Source: FSB_A<6> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.559ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + SLICE_X20Y53.A6 net (fanout=13) 2.724 FSB_A_6_IBUF + SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20> + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21> + SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF + l2pre/n0023<21>_rt + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.559ns (4.259ns logic, 6.300ns route) + (40.3% logic, 59.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.397ns (data path) + Source: FSB_A<26> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.397ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<26> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + H13.I Tiopi 1.557 FSB_A<26> + FSB_A<26> + FSB_A_26_IBUF + ProtoComp0.IMUX.17 + SLICE_X22Y51.C3 net (fanout=1) 3.450 FSB_A_26_IBUF + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.397ns (4.040ns logic, 6.357ns route) + (38.9% logic, 61.1% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.386ns (data path) + Source: FSB_A<15> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.386ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<15> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + G14.I Tiopi 1.557 FSB_A<15> + FSB_A<15> + FSB_A_15_IBUF + ProtoComp0.IMUX.10 + SLICE_X22Y50.C1 net (fanout=1) 3.345 FSB_A_15_IBUF + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.386ns (4.131ns logic, 6.255ns route) + (39.8% logic, 60.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.342ns (data path) + Source: FSB_A<18> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.342ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<18> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + H16.I Tiopi 1.557 FSB_A<18> + FSB_A<18> + FSB_A_18_IBUF + ProtoComp0.IMUX.16 + SLICE_X22Y50.D2 net (fanout=1) 3.336 FSB_A_18_IBUF + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.342ns (4.096ns logic, 6.246ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.341ns (data path) + Source: FSB_A<7> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.341ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<7> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + B16.I Tiopi 1.557 FSB_A<7> + FSB_A<7> + FSB_A_7_IBUF + ProtoComp0.IMUX.25 + SLICE_X22Y50.A1 net (fanout=1) 3.153 FSB_A_7_IBUF + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.341ns (4.278ns logic, 6.063ns route) + (41.4% logic, 58.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.331ns (data path) + Source: FSB_A<27> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.331ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<27> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + H14.I Tiopi 1.557 FSB_A<27> + FSB_A<27> + FSB_A_27_IBUF + ProtoComp0.IMUX.19 + SLICE_X22Y51.C1 net (fanout=1) 3.384 FSB_A_27_IBUF + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.331ns (4.040ns logic, 6.291ns route) + (39.1% logic, 60.9% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.285ns (data path) + Source: FSB_A<25> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.285ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<25> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + H11.I Tiopi 1.557 FSB_A<25> + FSB_A<25> + FSB_A_25_IBUF + ProtoComp0.IMUX.15 + SLICE_X22Y51.C2 net (fanout=1) 3.338 FSB_A_25_IBUF + SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.285ns (4.040ns logic, 6.245ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.186ns (data path) + Source: FSB_A<17> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.186ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<17> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + H15.I Tiopi 1.557 FSB_A<17> + FSB_A<17> + FSB_A_17_IBUF + ProtoComp0.IMUX.14 + SLICE_X22Y50.D6 net (fanout=1) 3.180 FSB_A_17_IBUF + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.186ns (4.096ns logic, 6.090ns route) + (40.2% logic, 59.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.091ns (data path) + Source: FSB_A<8> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.091ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<8> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + F12.I Tiopi 1.557 FSB_A<8> + FSB_A<8> + FSB_A_8_IBUF + ProtoComp0.IMUX.26 + SLICE_X22Y50.A3 net (fanout=1) 2.903 FSB_A_8_IBUF + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.091ns (4.278ns logic, 5.813ns route) + (42.4% logic, 57.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 10.036ns (data path) + Source: FSB_A<16> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 10.036ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<16> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + G16.I Tiopi 1.557 FSB_A<16> + FSB_A<16> + FSB_A_16_IBUF + ProtoComp0.IMUX.12 + SLICE_X22Y50.D5 net (fanout=1) 3.030 FSB_A_16_IBUF + SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 10.036ns (4.096ns logic, 5.940ns route) + (40.8% logic, 59.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.996ns (data path) + Source: FSB_A<9> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.996ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<9> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + G11.I Tiopi 1.557 FSB_A<9> + FSB_A<9> + FSB_A_9_IBUF + ProtoComp0.IMUX.27 + SLICE_X22Y50.A5 net (fanout=1) 2.808 FSB_A_9_IBUF + SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.996ns (4.278ns logic, 5.718ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.938ns (data path) + Source: FSB_A<11> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.938ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<11> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + D16.I Tiopi 1.557 FSB_A<11> + FSB_A<11> + FSB_A_11_IBUF + ProtoComp0.IMUX.2 + SLICE_X22Y50.B3 net (fanout=1) 2.774 FSB_A_11_IBUF + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.938ns (4.254ns logic, 5.684ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.929ns (data path) + Source: FSB_A<10> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.929ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<10> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + D14.I Tiopi 1.557 FSB_A<10> + FSB_A<10> + FSB_A_10_IBUF + ProtoComp0.IMUX.1 + SLICE_X22Y50.B5 net (fanout=1) 2.765 FSB_A_10_IBUF + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.929ns (4.254ns logic, 5.675ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.879ns (data path) + Source: FSB_A<20> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.879ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<20> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + C16.I Tiopi 1.557 FSB_A<20> + FSB_A<20> + FSB_A_20_IBUF + ProtoComp0.IMUX.4 + SLICE_X22Y51.A2 net (fanout=1) 2.785 FSB_A_20_IBUF + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.879ns (4.187ns logic, 5.692ns route) + (42.4% logic, 57.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.750ns (data path) + Source: FSB_A<14> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.750ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<14> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + C15.I Tiopi 1.557 FSB_A<14> + FSB_A<14> + FSB_A_14_IBUF + ProtoComp0.IMUX.8 + SLICE_X22Y50.C3 net (fanout=1) 2.709 FSB_A_14_IBUF + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.750ns (4.131ns logic, 5.619ns route) + (42.4% logic, 57.6% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.717ns (data path) + Source: FSB_A<23> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.717ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<23> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + F15.I Tiopi 1.557 FSB_A<23> + FSB_A<23> + FSB_A_23_IBUF + ProtoComp0.IMUX.11 + SLICE_X22Y51.B3 net (fanout=1) 2.647 FSB_A_23_IBUF + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.717ns (4.163ns logic, 5.554ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.634ns (data path) + Source: FSB_A<12> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.634ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<12> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + F13.I Tiopi 1.557 FSB_A<12> + FSB_A<12> + FSB_A_12_IBUF + ProtoComp0.IMUX.3 + SLICE_X22Y50.B6 net (fanout=1) 2.470 FSB_A_12_IBUF + SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.634ns (4.254ns logic, 5.380ns route) + (44.2% logic, 55.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.596ns (data path) + Source: FSB_A<13> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.596ns (Levels of Logic = 4) + + Maximum Data Path at Slow Process Corner: FSB_A<13> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + F14.I Tiopi 1.557 FSB_A<13> + FSB_A<13> + FSB_A_13_IBUF + ProtoComp0.IMUX.6 + SLICE_X22Y50.C6 net (fanout=1) 2.555 FSB_A_13_IBUF + SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2> + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3> + SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.596ns (4.131ns logic, 5.465ns route) + (43.0% logic, 57.0% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.567ns (data path) + Source: FSB_A<21> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.567ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<21> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E15.I Tiopi 1.557 FSB_A<21> + FSB_A<21> + FSB_A_21_IBUF + ProtoComp0.IMUX.7 + SLICE_X22Y51.A5 net (fanout=1) 2.473 FSB_A_21_IBUF + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.567ns (4.187ns logic, 5.380ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.409ns (data path) + Source: FSB_A<22> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.409ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<22> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + E16.I Tiopi 1.557 FSB_A<22> + FSB_A<22> + FSB_A_22_IBUF + ProtoComp0.IMUX.9 + SLICE_X22Y51.B5 net (fanout=1) 2.339 FSB_A_22_IBUF + SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.409ns (4.163ns logic, 5.246ns route) + (44.2% logic, 55.8% route) + +-------------------------------------------------------------------------------- +Delay (setup path): 9.160ns (data path) + Source: FSB_A<19> (PAD) + Destination: CPU_nSTERM (PAD) + Data Path Delay: 9.160ns (Levels of Logic = 3) + + Maximum Data Path at Slow Process Corner: FSB_A<19> to CPU_nSTERM + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + F16.I Tiopi 1.557 FSB_A<19> + FSB_A<19> + FSB_A_19_IBUF + ProtoComp0.IMUX.18 + SLICE_X22Y51.A6 net (fanout=1) 2.066 FSB_A_19_IBUF + SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF + l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4> + CPU_nSTERM1_cy + D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF + D12.PAD Tioop 1.982 CPU_nSTERM + CPU_nSTERM_OBUF + CPU_nSTERM + ------------------------------------------------- --------------------------- + Total 9.160ns (4.187ns logic, 4.973ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/pll/clkfbout_oddr (OLOGIC_X1Y62.CLK0), 1 path +-------------------------------------------------------------------------------- +Delay (setup path): -1.528ns (data path) + Source: CLKIN (PAD) + Destination: cg/pll/clkfbout_oddr (FF) + Data Path Delay: -1.528ns (Levels of Logic = 4) + + Maximum Data Path at Fast Process Corner: CLKIN to cg/pll/clkfbout_oddr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 cg/pll/clkfbout + BUFGMUX_X2Y3.O Tgi0o 0.063 cg/pll/clkfbout_bufg + cg/pll/clkfbout_bufg + OLOGIC_X1Y62.CLK0 net (fanout=2) 1.119 cg/pll/clkfb_bufg_out + ------------------------------------------------- --------------------------- + Total -1.528ns (-3.351ns logic, 1.823ns route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/RAMCLK1_inst (OLOGIC_X1Y63.CLK0), 1 path +-------------------------------------------------------------------------------- +Delay (setup path): -1.592ns (data path) + Source: CLKIN (PAD) + Destination: cg/RAMCLK1_inst (FF) + Data Path Delay: -1.592ns (Levels of Logic = 4) + + Maximum Data Path at Fast Process Corner: CLKIN to cg/RAMCLK1_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + OLOGIC_X1Y63.CLK0 net (fanout=17) 1.055 FSBCLK + ------------------------------------------------- --------------------------- + Total -1.592ns (-3.351ns logic, 1.759ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: Unconstrained path analysis + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (SLICE_X16Y51.CLK), 1 path +-------------------------------------------------------------------------------- +Delay (hold path): -4.017ns (data path) + Source: CLKIN (PAD) + Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (RAM) + Requirement: 0.000ns + Data Path Delay: -4.017ns (Levels of Logic = 4) + + Minimum Data Path at Slow Process Corner: CLKIN to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + SLICE_X16Y51.CLK net (fanout=17) 0.879 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.017ns (-6.437ns logic, 2.420ns route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (SLICE_X16Y51.CLK), 1 path +-------------------------------------------------------------------------------- +Delay (hold path): -4.017ns (data path) + Source: CLKIN (PAD) + Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (RAM) + Requirement: 0.000ns + Data Path Delay: -4.017ns (Levels of Logic = 4) + + Minimum Data Path at Slow Process Corner: CLKIN to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + SLICE_X16Y51.CLK net (fanout=17) 0.879 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.017ns (-6.437ns logic, 2.420ns route) + +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP (SLICE_X16Y51.CLK), 1 path +-------------------------------------------------------------------------------- +Delay (hold path): -4.017ns (data path) + Source: CLKIN (PAD) + Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP (RAM) + Requirement: 0.000ns + Data Path Delay: -4.017ns (Levels of Logic = 4) + + Minimum Data Path at Slow Process Corner: CLKIN to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + SLICE_X16Y51.CLK net (fanout=17) 0.879 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.017ns (-6.437ns logic, 2.420ns route) + +-------------------------------------------------------------------------------- Derived Constraint Report -Derived Constraints for CLKGEN_inst/instance_name/clkin1 +Derived Constraints for TS_CLKIN +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|CLKGEN_inst/instance_name/clkin| 30.000ns| 10.000ns| 5.400ns| 0| 0| 0| 35| -|1 | | | | | | | | -| CLKGEN_inst/instance_name/clko| 15.000ns| 2.700ns| N/A| 0| 0| 35| 0| -| ut0 | | | | | | | | -| CLKGEN_inst/instance_name/clkf| 30.000ns| 2.666ns| N/A| 0| 0| 0| 0| -| bout | | | | | | | | +|TS_CLKIN | 30.000ns| 10.000ns| 7.378ns| 0| 0| 0| 6| +| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0| +| TS_cg_pll_clkout0 | 15.000ns| 3.689ns| N/A| 0| 0| 6| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. @@ -8554,440 +5513,230 @@ Setup/Hold to clock CLKIN |Max Setup to| Process |Max Hold to | Process | | Clock | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | ------------+------------+------------+------------+------------+------------------+--------+ -CPU_nAS | 9.641(R)| SLOW | -3.896(R)| FAST |FSBCLK | 0.000| -FSB_A<0> | 10.028(R)| SLOW | -3.706(R)| FAST |FSBCLK | 0.000| -FSB_A<1> | 9.876(R)| SLOW | -3.242(R)| FAST |FSBCLK | 0.000| -FSB_A<2> | 9.842(R)| SLOW | -3.237(R)| FAST |FSBCLK | 0.000| -FSB_A<3> | 10.480(R)| SLOW | -3.772(R)| FAST |FSBCLK | 0.000| -FSB_A<4> | 9.766(R)| SLOW | -3.288(R)| FAST |FSBCLK | 0.000| -FSB_A<5> | 9.265(R)| SLOW | -3.204(R)| FAST |FSBCLK | 0.000| -FSB_A<6> | 9.919(R)| SLOW | -3.621(R)| FAST |FSBCLK | 0.000| -FSB_A<7> | 9.757(R)| SLOW | -3.464(R)| FAST |FSBCLK | 0.000| -FSB_A<8> | 10.287(R)| SLOW | -3.756(R)| FAST |FSBCLK | 0.000| -FSB_A<9> | 10.009(R)| SLOW | -3.618(R)| FAST |FSBCLK | 0.000| -FSB_A<10> | 9.562(R)| SLOW | -3.463(R)| FAST |FSBCLK | 0.000| -FSB_A<11> | 9.522(R)| SLOW | -3.200(R)| FAST |FSBCLK | 0.000| -FSB_A<12> | 9.821(R)| SLOW | -3.605(R)| FAST |FSBCLK | 0.000| -FSB_A<13> | 10.011(R)| SLOW | -3.709(R)| FAST |FSBCLK | 0.000| -FSB_A<14> | 9.084(R)| SLOW | -3.242(R)| FAST |FSBCLK | 0.000| -FSB_A<15> | 10.096(R)| SLOW | -3.834(R)| FAST |FSBCLK | 0.000| -FSB_A<16> | 9.565(R)| SLOW | -3.493(R)| FAST |FSBCLK | 0.000| -FSB_A<17> | 9.261(R)| SLOW | -3.474(R)| FAST |FSBCLK | 0.000| -FSB_A<18> | 9.868(R)| SLOW | -3.829(R)| FAST |FSBCLK | 0.000| -FSB_A<19> | 9.995(R)| SLOW | -3.722(R)| FAST |FSBCLK | 0.000| -FSB_A<20> | 10.064(R)| SLOW | -3.578(R)| FAST |FSBCLK | 0.000| -FSB_A<21> | 10.275(R)| SLOW | -3.718(R)| FAST |FSBCLK | 0.000| -FSB_A<22> | 9.907(R)| SLOW | -3.637(R)| FAST |FSBCLK | 0.000| -FSB_A<23> | 9.737(R)| SLOW | -3.472(R)| FAST |FSBCLK | 0.000| -FSB_A<24> | 10.026(R)| SLOW | -3.679(R)| FAST |FSBCLK | 0.000| -FSB_A<25> | 9.883(R)| SLOW | -3.244(R)| FAST |FSBCLK | 0.000| -FSB_A<26> | 9.657(R)| SLOW | -3.292(R)| FAST |FSBCLK | 0.000| -FSB_A<27> | 10.334(R)| SLOW | -3.698(R)| FAST |FSBCLK | 0.000| -FSB_A<28> | 10.261(R)| SLOW | -3.510(R)| FAST |FSBCLK | 0.000| -FSB_A<29> | 9.864(R)| SLOW | -3.448(R)| FAST |FSBCLK | 0.000| -FSB_A<30> | 9.847(R)| SLOW | -3.725(R)| FAST |FSBCLK | 0.000| -FSB_A<31> | 10.247(R)| SLOW | -3.707(R)| FAST |FSBCLK | 0.000| -INt | 10.332(R)| SLOW | -4.292(R)| FAST |FSBCLK | 0.000| +FSB_A<2> | 8.756(R)| SLOW | -3.416(R)| FAST |FSBCLK | 0.000| +FSB_A<3> | 8.745(R)| SLOW | -3.415(R)| FAST |FSBCLK | 0.000| +FSB_A<4> | 8.905(R)| SLOW | -3.413(R)| FAST |FSBCLK | 0.000| +FSB_A<5> | 8.878(R)| SLOW | -3.447(R)| FAST |FSBCLK | 0.000| +FSB_A<6> | 8.910(R)| SLOW | -3.417(R)| FAST |FSBCLK | 0.000| ------------+------------+------------+------------+------------+------------------+--------+ Clock CLKIN to Pad -------------+-----------------+------------+-----------------+------------+------------------+--------+ - |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | -Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | -------------+-----------------+------------+-----------------+------------+------------------+--------+ -OUTt | 2.040(R)| SLOW | 0.500(R)| FAST |FSBCLK | 0.000| -------------+-----------------+------------+-----------------+------------+------------------+--------+ +------------+-----------------+------------+-----------------+------------+---------------------+--------+ + |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | +Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | +------------+-----------------+------------+-----------------+------------+---------------------+--------+ +CLKFB_OUT | 0.189(R)| FAST | -0.348(R)| SLOW |cg/pll/clkfb_bufg_out| 0.000| + | 15.120(F)| FAST | 14.592(F)| SLOW |cg/pll/clkfb_bufg_out| 15.000| +CPUCLK | 0.214(R)| FAST | -0.386(R)| SLOW |FSBCLK | 0.000| +CPU_nSTERM | 3.599(R)| SLOW | 1.294(R)| FAST |FSBCLK | 0.000| +FPUCLK | 0.176(R)| FAST | -0.424(R)| SLOW |FSBCLK | 0.000| +FSB_D<0> | 4.996(R)| SLOW | 2.943(R)| FAST |FSBCLK | 0.000| +FSB_D<1> | 4.679(R)| SLOW | 2.722(R)| FAST |FSBCLK | 0.000| +FSB_D<2> | 5.139(R)| SLOW | 2.993(R)| FAST |FSBCLK | 0.000| +FSB_D<3> | 4.796(R)| SLOW | 2.838(R)| FAST |FSBCLK | 0.000| +FSB_D<4> | 5.039(R)| SLOW | 2.943(R)| FAST |FSBCLK | 0.000| +FSB_D<5> | 4.575(R)| SLOW | 2.599(R)| FAST |FSBCLK | 0.000| +FSB_D<6> | 4.192(R)| SLOW | 2.432(R)| FAST |FSBCLK | 0.000| +FSB_D<7> | 4.413(R)| SLOW | 2.551(R)| FAST |FSBCLK | 0.000| +FSB_D<8> | 4.142(R)| SLOW | 2.382(R)| FAST |FSBCLK | 0.000| +FSB_D<9> | 4.553(R)| SLOW | 2.601(R)| FAST |FSBCLK | 0.000| +FSB_D<10> | 4.549(R)| SLOW | 2.620(R)| FAST |FSBCLK | 0.000| +FSB_D<11> | 4.191(R)| SLOW | 2.462(R)| FAST |FSBCLK | 0.000| +FSB_D<12> | 4.180(R)| SLOW | 2.447(R)| FAST |FSBCLK | 0.000| +FSB_D<13> | 4.313(R)| SLOW | 2.482(R)| FAST |FSBCLK | 0.000| +FSB_D<14> | 4.442(R)| SLOW | 2.602(R)| FAST |FSBCLK | 0.000| +FSB_D<15> | 3.945(R)| SLOW | 2.313(R)| FAST |FSBCLK | 0.000| +FSB_D<16> | 3.945(R)| SLOW | 2.313(R)| FAST |FSBCLK | 0.000| +FSB_D<17> | 3.939(R)| SLOW | 2.192(R)| FAST |FSBCLK | 0.000| +FSB_D<18> | 3.964(R)| SLOW | 2.177(R)| FAST |FSBCLK | 0.000| +FSB_D<19> | 3.713(R)| SLOW | 2.080(R)| FAST |FSBCLK | 0.000| +FSB_D<20> | 4.145(R)| SLOW | 2.333(R)| FAST |FSBCLK | 0.000| +FSB_D<21> | 3.789(R)| SLOW | 2.149(R)| FAST |FSBCLK | 0.000| +FSB_D<22> | 3.647(R)| SLOW | 2.048(R)| FAST |FSBCLK | 0.000| +FSB_D<23> | 3.508(R)| SLOW | 1.976(R)| FAST |FSBCLK | 0.000| +FSB_D<24> | 3.458(R)| SLOW | 1.926(R)| FAST |FSBCLK | 0.000| +FSB_D<25> | 3.598(R)| SLOW | 2.019(R)| FAST |FSBCLK | 0.000| +FSB_D<26> | 3.393(R)| SLOW | 1.890(R)| FAST |FSBCLK | 0.000| +FSB_D<27> | 3.678(R)| SLOW | 2.094(R)| FAST |FSBCLK | 0.000| +FSB_D<28> | 3.678(R)| SLOW | 2.094(R)| FAST |FSBCLK | 0.000| +FSB_D<29> | 3.552(R)| SLOW | 2.049(R)| FAST |FSBCLK | 0.000| +FSB_D<30> | 3.552(R)| SLOW | 2.049(R)| FAST |FSBCLK | 0.000| +FSB_D<31> | 3.621(R)| SLOW | 2.113(R)| FAST |FSBCLK | 0.000| +RAMCLK0 | 0.125(R)| FAST | -0.475(R)| SLOW |FSBCLK | 0.000| +RAMCLK1 | 0.164(R)| FAST | -0.436(R)| SLOW |FSBCLK | 0.000| +------------+-----------------+------------+-----------------+------------+---------------------+--------+ Clock to Setup on destination clock CLKIN ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ -CLKIN | 2.700| | | | +CLKIN | 3.689| | | | ---------------+---------+---------+---------+---------+ -COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.540; Ideal Clock Offset To Actual Clock 0.977; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<31> | 10.247(R)| SLOW | -3.707(R)| FAST | 1.753| 3.707| -0.977| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.247| - | -3.707| - | 1.753| 3.707| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +Pad to Pad +---------------+---------------+---------+ +Source Pad |Destination Pad| Delay | +---------------+---------------+---------+ +FSB_A<2> |CPU_nSTERM | 12.820| +FSB_A<3> |CPU_nSTERM | 12.708| +FSB_A<4> |CPU_nSTERM | 12.945| +FSB_A<5> |CPU_nSTERM | 12.435| +FSB_A<6> |CPU_nSTERM | 12.356| +FSB_A<7> |CPU_nSTERM | 10.341| +FSB_A<8> |CPU_nSTERM | 10.091| +FSB_A<9> |CPU_nSTERM | 9.996| +FSB_A<10> |CPU_nSTERM | 9.929| +FSB_A<11> |CPU_nSTERM | 9.938| +FSB_A<12> |CPU_nSTERM | 9.634| +FSB_A<13> |CPU_nSTERM | 9.596| +FSB_A<14> |CPU_nSTERM | 9.750| +FSB_A<15> |CPU_nSTERM | 10.386| +FSB_A<16> |CPU_nSTERM | 10.036| +FSB_A<17> |CPU_nSTERM | 10.186| +FSB_A<18> |CPU_nSTERM | 10.342| +FSB_A<19> |CPU_nSTERM | 9.160| +FSB_A<20> |CPU_nSTERM | 9.879| +FSB_A<21> |CPU_nSTERM | 9.567| +FSB_A<22> |CPU_nSTERM | 9.409| +FSB_A<23> |CPU_nSTERM | 9.717| +FSB_A<24> |CPU_nSTERM | 10.629| +FSB_A<25> |CPU_nSTERM | 10.285| +FSB_A<26> |CPU_nSTERM | 10.397| +FSB_A<27> |CPU_nSTERM | 10.331| +---------------+---------------+---------+ -COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.122; Ideal Clock Offset To Actual Clock 0.786; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<30> | 9.847(R)| SLOW | -3.725(R)| FAST | 2.153| 3.725| -0.786| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.847| - | -3.725| - | 2.153| 3.725| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.416; Ideal Clock Offset To Actual Clock 0.656; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<29> | 9.864(R)| SLOW | -3.448(R)| FAST | 2.136| 3.448| -0.656| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.864| - | -3.448| - | 2.136| 3.448| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.751; Ideal Clock Offset To Actual Clock 0.885; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<28> | 10.261(R)| SLOW | -3.510(R)| FAST | 1.739| 3.510| -0.885| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.261| - | -3.510| - | 1.739| 3.510| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +Table of Timegroups: +------------------- +TimeGroup cg_pll_clkout0: +Blocks + cg/pll/clkout1_buf + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP + cg/CPUCLKr -COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.636; Ideal Clock Offset To Actual Clock 1.016; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<27> | 10.334(R)| SLOW | -3.698(R)| FAST | 1.666| 3.698| -1.016| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.334| - | -3.698| - | 1.666| 3.698| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +Pins + cg\/RAMCLK0_inst.CK0 + cg\/RAMCLK0_inst.CK1 + cg\/RAMCLK1_inst.CK0 + cg\/RAMCLK1_inst.CK1 + cg\/FPUCLK_inst.CK0 + cg\/FPUCLK_inst.CK1 + cg\/CPUCLK_inst.CK0 + cg\/CPUCLK_inst.CK1 + l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKAWRCLK + l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKBRDCLK -COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.365; Ideal Clock Offset To Actual Clock 0.474; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<26> | 9.657(R)| SLOW | -3.292(R)| FAST | 2.343| 3.292| -0.474| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.657| - | -3.292| - | 2.343| 3.292| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.639; Ideal Clock Offset To Actual Clock 0.564; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<25> | 9.883(R)| SLOW | -3.244(R)| FAST | 2.117| 3.244| -0.564| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.883| - | -3.244| - | 2.117| 3.244| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +TimeGroup cg_pll_clkfbout: +Blocks + cg/pll/clkfbout_bufg +Pins + cg\/pll\/clkfbout_oddr.CK0 cg\/pll\/clkfbout_oddr.CK1 -COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.347; Ideal Clock Offset To Actual Clock 0.853; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<24> | 10.026(R)| SLOW | -3.679(R)| FAST | 1.974| 3.679| -0.853| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.026| - | -3.679| - | 1.974| 3.679| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +TimeGroup CPU_nSTERM: +Blocks + CPU_nSTERM -COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.265; Ideal Clock Offset To Actual Clock 0.605; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<23> | 9.737(R)| SLOW | -3.472(R)| FAST | 2.263| 3.472| -0.605| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.737| - | -3.472| - | 2.263| 3.472| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +TimeGroup FSB_A: +Blocks + CPU_nSTERM + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP + l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP -COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.270; Ideal Clock Offset To Actual Clock 0.772; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<22> | 9.907(R)| SLOW | -3.637(R)| FAST | 2.093| 3.637| -0.772| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.907| - | -3.637| - | 2.093| 3.637| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ +Pins + l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKBRDCLK -COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.557; Ideal Clock Offset To Actual Clock 0.997; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<21> | 10.275(R)| SLOW | -3.718(R)| FAST | 1.725| 3.718| -0.997| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.275| - | -3.718| - | 1.725| 3.718| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.486; Ideal Clock Offset To Actual Clock 0.821; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<20> | 10.064(R)| SLOW | -3.578(R)| FAST | 1.936| 3.578| -0.821| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.064| - | -3.578| - | 1.936| 3.578| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.273; Ideal Clock Offset To Actual Clock 0.859; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<19> | 9.995(R)| SLOW | -3.722(R)| FAST | 2.005| 3.722| -0.859| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.995| - | -3.722| - | 2.005| 3.722| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.039; Ideal Clock Offset To Actual Clock 0.849; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<18> | 9.868(R)| SLOW | -3.829(R)| FAST | 2.132| 3.829| -0.849| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.868| - | -3.829| - | 2.132| 3.829| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 5.787; Ideal Clock Offset To Actual Clock 0.368; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<17> | 9.261(R)| SLOW | -3.474(R)| FAST | 2.739| 3.474| -0.368| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.261| - | -3.474| - | 2.739| 3.474| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.072; Ideal Clock Offset To Actual Clock 0.529; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<16> | 9.565(R)| SLOW | -3.493(R)| FAST | 2.435| 3.493| -0.529| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.565| - | -3.493| - | 2.435| 3.493| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.262; Ideal Clock Offset To Actual Clock 0.965; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<15> | 10.096(R)| SLOW | -3.834(R)| FAST | 1.904| 3.834| -0.965| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.096| - | -3.834| - | 1.904| 3.834| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 5.842; Ideal Clock Offset To Actual Clock 0.163; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<14> | 9.084(R)| SLOW | -3.242(R)| FAST | 2.916| 3.242| -0.163| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.084| - | -3.242| - | 2.916| 3.242| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.302; Ideal Clock Offset To Actual Clock 0.860; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<13> | 10.011(R)| SLOW | -3.709(R)| FAST | 1.989| 3.709| -0.860| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.011| - | -3.709| - | 1.989| 3.709| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.216; Ideal Clock Offset To Actual Clock 0.713; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<12> | 9.821(R)| SLOW | -3.605(R)| FAST | 2.179| 3.605| -0.713| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.821| - | -3.605| - | 2.179| 3.605| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.322; Ideal Clock Offset To Actual Clock 0.361; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<11> | 9.522(R)| SLOW | -3.200(R)| FAST | 2.478| 3.200| -0.361| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.522| - | -3.200| - | 2.478| 3.200| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.099; Ideal Clock Offset To Actual Clock 0.513; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<10> | 9.562(R)| SLOW | -3.463(R)| FAST | 2.438| 3.463| -0.513| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.562| - | -3.463| - | 2.438| 3.463| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.391; Ideal Clock Offset To Actual Clock 0.813; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<9> | 10.009(R)| SLOW | -3.618(R)| FAST | 1.991| 3.618| -0.813| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.009| - | -3.618| - | 1.991| 3.618| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.531; Ideal Clock Offset To Actual Clock 1.021; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<8> | 10.287(R)| SLOW | -3.756(R)| FAST | 1.713| 3.756| -1.021| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.287| - | -3.756| - | 1.713| 3.756| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.293; Ideal Clock Offset To Actual Clock 0.611; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<7> | 9.757(R)| SLOW | -3.464(R)| FAST | 2.243| 3.464| -0.611| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.757| - | -3.464| - | 2.243| 3.464| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.298; Ideal Clock Offset To Actual Clock 0.770; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<6> | 9.919(R)| SLOW | -3.621(R)| FAST | 2.081| 3.621| -0.770| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.919| - | -3.621| - | 2.081| 3.621| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.061; Ideal Clock Offset To Actual Clock 0.235; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<5> | 9.265(R)| SLOW | -3.204(R)| FAST | 2.735| 3.204| -0.235| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.265| - | -3.204| - | 2.735| 3.204| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.478; Ideal Clock Offset To Actual Clock 0.527; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<4> | 9.766(R)| SLOW | -3.288(R)| FAST | 2.234| 3.288| -0.527| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.766| - | -3.288| - | 2.234| 3.288| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.708; Ideal Clock Offset To Actual Clock 1.126; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<3> | 10.480(R)| SLOW | -3.772(R)| FAST | 1.520| 3.772| -1.126| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.480| - | -3.772| - | 1.520| 3.772| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.605; Ideal Clock Offset To Actual Clock 0.540; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<2> | 9.842(R)| SLOW | -3.237(R)| FAST | 2.158| 3.237| -0.540| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.842| - | -3.237| - | 2.158| 3.237| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.634; Ideal Clock Offset To Actual Clock 0.559; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<1> | 9.876(R)| SLOW | -3.242(R)| FAST | 2.124| 3.242| -0.559| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.876| - | -3.242| - | 2.124| 3.242| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.322; Ideal Clock Offset To Actual Clock 0.867; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -FSB_A<0> | 10.028(R)| SLOW | -3.706(R)| FAST | 1.972| 3.706| -0.867| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.028| - | -3.706| - | 1.972| 3.706| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 5.745; Ideal Clock Offset To Actual Clock 0.769; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -CPU_nAS | 9.641(R)| SLOW | -3.896(R)| FAST | 2.359| 3.896| -0.769| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.641| - | -3.896| - | 2.359| 3.896| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 6.040; Ideal Clock Offset To Actual Clock 1.312; -------------------+------------+------------+------------+------------+---------+---------+-------------+ - | | Process | | Process | Setup | Hold |Source Offset| -Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | -------------------+------------+------------+------------+------------+---------+---------+-------------+ -INt | 10.332(R)| SLOW | -4.292(R)| FAST | 1.668| 4.292| -1.312| -------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 10.332| - | -4.292| - | 1.668| 4.292| | -------------------+------------+------------+------------+------------+---------+---------+-------------+ - -COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN"; -Bus Skew: 0.000 ns; ------------------------------------------------+-------------+------------+-------------+------------+--------------+ - |Max (slowest)| Process |Min (fastest)| Process | | -PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| ------------------------------------------------+-------------+------------+-------------+------------+--------------+ -OUTt | 2.040| SLOW | 0.500| FAST | 0.000| ------------------------------------------------+-------------+------------+-------------+------------+--------------+ +TimeGroup CLKIN: +Pins + cg\/pll\/pll_base_inst\/PLL_ADV.CLKIN1 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0.DIVCLK Timing summary: @@ -8995,25 +5744,27 @@ Timing summary: Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) -Constraints cover 102 paths, 0 nets, and 122 connections +Constraints cover 259 paths, 0 nets, and 178 connections Design statistics: Minimum period: 10.000ns{1} (Maximum frequency: 100.000MHz) - Minimum input required time before clock: 10.480ns - Minimum output required time after clock: 2.040ns + Maximum combinational path delay: 12.945ns + Maximum path delay from/to any node: 7.879ns + Minimum input required time before clock: 8.910ns + Maximum output delay after clock: 15.120ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. -Analysis completed Fri Oct 29 17:59:57 2021 +Analysis completed Sun Oct 31 15:38:38 2021 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings -Peak Memory Usage: 170 MB +Peak Memory Usage: 214 MB diff --git a/fpga/WarpLC.twx b/fpga/WarpLC.twx index a5ad975..bb731a3 100644 --- a/fpga/WarpLC.twx +++ b/fpga/WarpLC.twx @@ -329,195 +329,49 @@ ]> -Release 14.7 Trace (nt)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n -3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf +Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 +-timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o +WarpLC.twr WarpLC.pcf -ucf PLL.ucf -WarpLC.ncdWarpLC.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%;000000010.000Component Switching Limit Checks: NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%;PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" derived from NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; divided by 2.00 to 15 nS 3500001202.700Paths for end point OUTt (SLICE_X0Y21.CIN), 24 paths -12.300AR_5OUTt2.5340.01815.0000.148AR_5OUTt3SLICE_X0Y18.CLKFSBCLKSLICE_X0Y18.BQTcko0.525AR<7>AR_5SLICE_X0Y19.B1net11.129AR<5>SLICE_X0Y19.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.3991.1352.534FSBCLK55.244.812.375AR_9OUTt2.4580.01915.0000.148AR_9OUTt3SLICE_X0Y17.CLKFSBCLKSLICE_X0Y17.BQTcko0.525AR<11>AR_9SLICE_X0Y19.D1net11.224AR<9>SLICE_X0Y19.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2281.2302.458FSBCLK50.050.012.408AR_4OUTt2.4260.01815.0000.148AR_4OUTt3SLICE_X0Y18.CLKFSBCLKSLICE_X0Y18.AQTcko0.525AR<7>AR_4SLICE_X0Y19.B5net11.021AR<4>SLICE_X0Y19.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.3991.0272.426FSBCLK57.742.3Paths for end point OUTt (SLICE_X0Y21.B3), 1 path -12.492AR_27OUTt2.3480.01215.0000.148AR_27OUTt1SLICE_X0Y24.CLKFSBCLKSLICE_X0Y24.DQTcko0.525AR<27>AR_27SLICE_X0Y21.B3net11.135AR<27>SLICE_X0Y21.CLKTas0.688OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2131.1352.348FSBCLK51.748.3Paths for end point CLKGEN_inst/FPUCLK_inst (OLOGIC_X0Y47.D2), 1 path -12.531CLKGEN_inst/CPUCLKrCLKGEN_inst/FPUCLK_inst2.853-0.53215.0000.148CLKGEN_inst/CPUCLKrCLKGEN_inst/FPUCLK_inst0SLICE_X0Y53.CLKFSBCLKSLICE_X0Y53.DQTcko0.525CLKGEN_inst/CPUCLKrCLKGEN_inst/CPUCLKrOLOGIC_X0Y47.D2net31.497CLKGEN_inst/CPUCLKrOLOGIC_X0Y47.CLK0Todck0.831FPUCLK_OBUFCLKGEN_inst/FPUCLK_inst1.3561.4972.853FSBCLK47.552.5Hold Paths: PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" derived from - NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; - divided by 2.00 to 15 nS +WarpLC.ncdWarpLC.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-13110003INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;000000010.000Component Switching Limit Checks: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;220000107.879Paths for end point CPU_nSTERM (D12.PAD), 22 paths +7.121l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPCPU_nSTERM7.8790.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPCPU_nSTERM2SLICE_X16Y51.CLKFSBCLKSLICE_X16Y51.AMUXTshcko1.081l2pre/n0023<11>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPSLICE_X22Y51.A1net11.261l2pre/n0023<14>SLICE_X22Y51.DMUXTopad0.648CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.7114.1687.87947.152.97.227l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DPCPU_nSTERM7.7730.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DPCPU_nSTERM2SLICE_X16Y51.CLKFSBCLKSLICE_X16Y51.ATshcko1.012l2pre/n0023<11>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DPSLICE_X22Y51.B2net11.248l2pre/n0023<16>SLICE_X22Y51.DMUXTopbd0.624CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.6184.1557.77346.553.57.243l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DPCPU_nSTERM7.7570.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DPCPU_nSTERM3SLICE_X20Y50.CLKFSBCLKSLICE_X20Y50.BMUXTshcko1.131l2pre/n0023<3>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DPSLICE_X22Y50.B1net11.019l2pre/n0023<4>SLICE_X22Y50.COUTTopcyb0.448l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.8283.9297.75749.350.7Fastest Paths: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns; +Paths for end point CPU_nSTERM (D12.PAD), 22 paths +3.026l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPCPU_nSTERM2SLICE_X20Y51.CLKFSBCLKSLICE_X20Y51.AMUXTshcko0.490l2pre/n0023<15>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPSLICE_X22Y51.C6net10.129l2pre/n0023<18>SLICE_X22Y51.DMUXTopcd0.307CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>CPU_nSTERM1_cyD12.Onet11.401CPU_nSTERM_OBUFD12.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.4961.5303.02649.450.63.039l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DPCPU_nSTERM2SLICE_X20Y51.CLKFSBCLKSLICE_X20Y51.BTshcko0.449l2pre/n0023<15>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DPSLICE_X22Y51.B6net10.119l2pre/n0023<15>SLICE_X22Y51.DMUXTopbd0.371CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>CPU_nSTERM1_cyD12.Onet11.401CPU_nSTERM_OBUFD12.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.5191.5203.03950.050.03.074l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPCPU_nSTERM2SLICE_X20Y51.CLKFSBCLKSLICE_X20Y51.BMUXTshcko0.495l2pre/n0023<15>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPSLICE_X22Y51.C5net10.172l2pre/n0023<19>SLICE_X22Y51.DMUXTopcd0.307CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>CPU_nSTERM1_cyD12.Onet11.401CPU_nSTERM_OBUFD12.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.5011.5733.07448.851.2TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;00000002.666Component Switching Limit Checks: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;60000603.689Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y61.D1), 1 path +11.311cg/CPUCLKrcg/CPUCLK_inst4.087-0.51415.0000.116cg/CPUCLKrcg/CPUCLK_inst1SLICE_X20Y61.CLKFSBCLKSLICE_X20Y61.DQTcko0.525cg/CPUCLKrcg/CPUCLKrSLICE_X20Y61.D6net30.156cg/CPUCLKrSLICE_X20Y61.DTilo0.254cg/CPUCLKr][292_3_INV_0OLOGIC_X1Y61.D1net32.186][292_3OLOGIC_X1Y61.CLK0Todck0.966CPUCLK_OBUFcg/CPUCLK_inst1.7452.3424.087FSBCLK42.757.3Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y61.D2), 1 path +11.624cg/CPUCLKrcg/CPUCLK_inst3.774-0.51415.0000.116cg/CPUCLKrcg/CPUCLK_inst1SLICE_X20Y61.CLKFSBCLKSLICE_X20Y61.DQTcko0.525cg/CPUCLKrcg/CPUCLKrSLICE_X20Y61.D6net30.156cg/CPUCLKrSLICE_X20Y61.DTilo0.254cg/CPUCLKr][292_3_INV_0OLOGIC_X1Y61.D2net32.008][292_3OLOGIC_X1Y61.CLK0Todck0.831CPUCLK_OBUFcg/CPUCLK_inst1.6102.1643.774FSBCLK42.757.3Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y61.D2), 1 path +12.401cg/CPUCLKrcg/FPUCLK_inst2.966-0.48315.0000.116cg/CPUCLKrcg/FPUCLK_inst0SLICE_X20Y61.CLKFSBCLKSLICE_X20Y61.DQTcko0.525cg/CPUCLKrcg/CPUCLKrOLOGIC_X11Y61.D2net31.610cg/CPUCLKrOLOGIC_X11Y61.CLK0Todck0.831FPUCLK_OBUFcg/FPUCLK_inst1.3561.6102.966FSBCLK45.754.3Hold Paths: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; +Paths for end point cg/CPUCLKr (SLICE_X20Y61.D6), 1 path +0.458cg/CPUCLKrcg/CPUCLKr0.4580.0000.0000.000cg/CPUCLKrcg/CPUCLKr1SLICE_X20Y61.CLKFSBCLKSLICE_X20Y61.DQTcko0.234cg/CPUCLKrcg/CPUCLKrSLICE_X20Y61.D6net30.027cg/CPUCLKrSLICE_X20Y61.CLKTah0.197cg/CPUCLKr][292_3_INV_0cg/CPUCLKr0.4310.0270.458FSBCLK94.15.9Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y61.D1), 1 path +0.665cg/CPUCLKrcg/FPUCLK_inst0.857-0.1920.0000.000cg/CPUCLKrcg/FPUCLK_inst0SLICE_X20Y61.CLKFSBCLKSLICE_X20Y61.DQTcko0.234cg/CPUCLKrcg/CPUCLKrOLOGIC_X11Y61.D1net30.293cg/CPUCLKrOLOGIC_X11Y61.CLK0Tockd0.330FPUCLK_OBUFcg/FPUCLK_inst0.5640.2930.857FSBCLK65.834.2Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ENBRDEN), 1 path +0.736cg/CPUCLKrl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.7360.0000.0000.000cg/CPUCLKrl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1SLICE_X20Y61.CLKFSBCLKSLICE_X20Y61.DQTcko0.234cg/CPUCLKrcg/CPUCLKrSLICE_X20Y61.D6net30.027cg/CPUCLKrSLICE_X20Y61.DTilo0.156cg/CPUCLKr][292_3_INV_0RAMB8_X1Y31.ENBRDENnet30.363][292_3RAMB8_X1Y31.CLKBRDCLKTrckc_ENB-0.044l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.3460.3900.736FSBCLK47.053.0Component Switching Limit Checks: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;Unconstrained OFFSET IN BEFORE analysis for clock "FSBCLK" 50000508.910Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path +8.910FSB_A<6>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.296FSB_A<6>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1B15.PADB15.ITiopi1.557FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp0.IMUX.24RAMB8_X1Y31.ADDRBRDADDR9net132.643FSB_A_6_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.6434.600FSBCLK42.557.5CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet170.882FSBCLK-6.4372.423-4.014Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +8.905FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.296FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E13.PADE13.ITiopi1.557FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp0.IMUX.22RAMB8_X1Y31.ADDRBRDADDR7net132.638FSB_A_4_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.6384.595FSBCLK42.657.4CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet170.882FSBCLK-6.4372.423-4.014Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path +8.878FSB_A<5>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.296FSB_A<5>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E12.PADE12.ITiopi1.557FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp0.IMUX.23RAMB8_X1Y31.ADDRBRDADDR8net132.611FSB_A_5_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.6114.568FSBCLK42.857.2CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet170.882FSBCLK-6.4372.423-4.014Hold Paths: Unconstrained OFFSET IN BEFORE analysis for clock "FSBCLK" -Paths for end point CLKGEN_inst/CPUCLKr (SLICE_X0Y53.D6), 1 path -0.457CLKGEN_inst/CPUCLKrCLKGEN_inst/CPUCLKr0.4570.0000.0000.000CLKGEN_inst/CPUCLKrCLKGEN_inst/CPUCLKr1SLICE_X0Y53.CLKFSBCLKSLICE_X0Y53.DQTcko0.234CLKGEN_inst/CPUCLKrCLKGEN_inst/CPUCLKrSLICE_X0Y53.D6net30.026CLKGEN_inst/CPUCLKrSLICE_X0Y53.CLKTah0.197CLKGEN_inst/CPUCLKrCLKGEN_inst/CPUCLKr_rstpot1_INV_0CLKGEN_inst/CPUCLKr0.4310.0260.457FSBCLK94.35.7Paths for end point CLKGEN_inst/FPUCLK_inst (OLOGIC_X0Y47.D1), 1 path -0.582CLKGEN_inst/CPUCLKrCLKGEN_inst/FPUCLK_inst0.838-0.2560.0000.000CLKGEN_inst/CPUCLKrCLKGEN_inst/FPUCLK_inst0SLICE_X0Y53.CLKFSBCLKSLICE_X0Y53.DQTcko0.234CLKGEN_inst/CPUCLKrCLKGEN_inst/CPUCLKrOLOGIC_X0Y47.D1net30.274CLKGEN_inst/CPUCLKrOLOGIC_X0Y47.CLK0Tockd0.330FPUCLK_OBUFCLKGEN_inst/FPUCLK_inst0.5640.2740.838FSBCLK67.332.7Paths for end point OUTt (SLICE_X0Y21.CIN), 24 paths -0.691AR_13OUTt0.6900.0010.0000.000AR_13OUTt2SLICE_X1Y20.CLKFSBCLKSLICE_X1Y20.BQTcko0.198AR<15>AR_13SLICE_X0Y20.A5net10.070AR<13>SLICE_X0Y20.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt0.6190.0710.690FSBCLK89.710.30.781AR_6OUTt0.7760.0050.0000.000AR_6OUTt3SLICE_X0Y18.CLKFSBCLKSLICE_X0Y18.CQTcko0.234AR<7>AR_6SLICE_X0Y19.C5net10.156AR<6>SLICE_X0Y19.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt0.6180.1580.776FSBCLK79.620.40.863AR_15OUTt0.8620.0010.0000.000AR_15OUTt2SLICE_X1Y20.CLKFSBCLKSLICE_X1Y20.DQTcko0.198AR<15>AR_15SLICE_X0Y20.B1net10.250AR<15>SLICE_X0Y20.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt0.6110.2510.862FSBCLK70.929.1Component Switching Limit Checks: PERIOD analysis for net "CLKGEN_inst/instance_name/clkout0" derived from - NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; - divided by 2.00 to 15 nS -PERIOD analysis for net "CLKGEN_inst/instance_name/clkfbout" derived from NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; duty cycle corrected to 30 nS HIGH 15 nS 00000002.666Component Switching Limit Checks: PERIOD analysis for net "CLKGEN_inst/instance_name/clkfbout" derived from - NET "CLKGEN_inst/instance_name/clkin1" PERIOD = 30 ns HIGH 50%; - duty cycle corrected to 30 nS HIGH 15 nS -COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.247Paths for end point OUTt (SLICE_X0Y21.C5), 1 path -1.753FSB_A<31>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<31>CLKIN0.414FSB_A<31>OUTt2L4.PADL4.ITiopi1.557FSB_A<31>FSB_A<31>FSB_A_31_IBUFProtoComp10.IMUX.13SLICE_X0Y21.C5net23.840FSB_A_31_IBUFSLICE_X0Y21.CLKTas0.533OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.0903.8405.930FSBCLK35.264.8CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_31 (SLICE_X0Y22.DX), 1 path -2.593FSB_A<31>AR_31-3.906CLKINAR<31>12.000FSB_A<31>CLKIN0.414FSB_A<31>AR_311L4.PADL4.ITiopi1.557FSB_A<31>FSB_A<31>FSB_A_31_IBUFProtoComp10.IMUX.13SLICE_X0Y22.DXnet23.445FSB_A_31_IBUFSLICE_X0Y22.CLKTdick0.085AR<31>AR_311.6423.4455.087FSBCLK32.367.7CLKINAR_314J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_31 (SLICE_X0Y22.DX), 1 path -3.707FSB_A<31>AR_31-1.700CLKINAR<31>0.000FSB_A<31>CLKIN0.414FSB_A<31>AR_311L4.PADL4.ITiopi0.763FSB_A<31>FSB_A<31>FSB_A_31_IBUFProtoComp10.IMUX.13SLICE_X0Y22.DXnet21.617FSB_A_31_IBUFSLICE_X0Y22.CLKTckdi0.041AR<31>AR_310.8041.6172.421FSBCLK33.266.8CLKINAR_314J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.C5), 1 path -4.160FSB_A<31>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<31>CLKIN0.414FSB_A<31>OUTt2L4.PADL4.ITiopi0.763FSB_A<31>FSB_A<31>FSB_A_31_IBUFProtoComp10.IMUX.13SLICE_X0Y21.C5net21.794FSB_A_31_IBUFSLICE_X0Y21.CLKTah0.320OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0831.7942.877FSBCLK37.662.4CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.847Paths for end point OUTt (SLICE_X0Y21.C4), 1 path -2.153FSB_A<30>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<30>CLKIN0.414FSB_A<30>OUTt2H5.PADH5.ITiopi1.557FSB_A<30>FSB_A<30>FSB_A_30_IBUFProtoComp10.IMUX.10SLICE_X0Y21.C4net23.440FSB_A_30_IBUFSLICE_X0Y21.CLKTas0.533OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.0903.4405.530FSBCLK37.862.2CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_30 (SLICE_X0Y22.CX), 1 path -2.628FSB_A<30>AR_30-3.906CLKINAR<31>12.000FSB_A<30>CLKIN0.414FSB_A<30>AR_301H5.PADH5.ITiopi1.557FSB_A<30>FSB_A<30>FSB_A_30_IBUFProtoComp10.IMUX.10SLICE_X0Y22.CXnet23.410FSB_A_30_IBUFSLICE_X0Y22.CLKTdick0.085AR<31>AR_301.6423.4105.052FSBCLK32.567.5CLKINAR_304J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_30 (SLICE_X0Y22.CX), 1 path -3.725FSB_A<30>AR_30-1.700CLKINAR<31>0.000FSB_A<30>CLKIN0.414FSB_A<30>AR_301H5.PADH5.ITiopi0.763FSB_A<30>FSB_A<30>FSB_A_30_IBUFProtoComp10.IMUX.10SLICE_X0Y22.CXnet21.635FSB_A_30_IBUFSLICE_X0Y22.CLKTckdi0.041AR<31>AR_300.8041.6352.439FSBCLK33.067.0CLKINAR_304J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.C4), 1 path -4.050FSB_A<30>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<30>CLKIN0.414FSB_A<30>OUTt2H5.PADH5.ITiopi0.763FSB_A<30>FSB_A<30>FSB_A_30_IBUFProtoComp10.IMUX.10SLICE_X0Y21.C4net21.684FSB_A_30_IBUFSLICE_X0Y21.CLKTah0.320OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<10>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0831.6842.767FSBCLK39.160.9CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.864Paths for end point OUTt (SLICE_X0Y21.B4), 1 path -2.136FSB_A<29>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<29>CLKIN0.414FSB_A<29>OUTt2G1.PADG1.ITiopi1.557FSB_A<29>FSB_A<29>FSB_A_29_IBUFProtoComp10.IMUX.24SLICE_X0Y21.B4net23.302FSB_A_29_IBUFSLICE_X0Y21.CLKTas0.688OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2453.3025.547FSBCLK40.559.5CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_29 (SLICE_X0Y22.BX), 1 path -3.127FSB_A<29>AR_29-3.906CLKINAR<31>12.000FSB_A<29>CLKIN0.414FSB_A<29>AR_291G1.PADG1.ITiopi1.557FSB_A<29>FSB_A<29>FSB_A_29_IBUFProtoComp10.IMUX.24SLICE_X0Y22.BXnet22.911FSB_A_29_IBUFSLICE_X0Y22.CLKTdick0.085AR<31>AR_291.6422.9114.553FSBCLK36.163.9CLKINAR_294J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_29 (SLICE_X0Y22.BX), 1 path -3.448FSB_A<29>AR_29-1.700CLKINAR<31>0.000FSB_A<29>CLKIN0.414FSB_A<29>AR_291G1.PADG1.ITiopi0.763FSB_A<29>FSB_A<29>FSB_A_29_IBUFProtoComp10.IMUX.24SLICE_X0Y22.BXnet21.358FSB_A_29_IBUFSLICE_X0Y22.CLKTckdi0.041AR<31>AR_290.8041.3582.162FSBCLK37.262.8CLKINAR_294J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.B4), 1 path -4.001FSB_A<29>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<29>CLKIN0.414FSB_A<29>OUTt2G1.PADG1.ITiopi0.763FSB_A<29>FSB_A<29>FSB_A_29_IBUFProtoComp10.IMUX.24SLICE_X0Y21.B4net21.574FSB_A_29_IBUFSLICE_X0Y21.CLKTah0.381OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1441.5742.718FSBCLK42.157.9CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.261Paths for end point OUTt (SLICE_X0Y21.B2), 1 path -1.739FSB_A<28>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<28>CLKIN0.414FSB_A<28>OUTt2K3.PADK3.ITiopi1.557FSB_A<28>FSB_A<28>FSB_A_28_IBUFProtoComp10.IMUX.23SLICE_X0Y21.B2net23.699FSB_A_28_IBUFSLICE_X0Y21.CLKTas0.688OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2453.6995.944FSBCLK37.862.2CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_28 (SLICE_X0Y22.AX), 1 path -3.044FSB_A<28>AR_28-3.906CLKINAR<31>12.000FSB_A<28>CLKIN0.414FSB_A<28>AR_281K3.PADK3.ITiopi1.557FSB_A<28>FSB_A<28>FSB_A_28_IBUFProtoComp10.IMUX.23SLICE_X0Y22.AXnet22.994FSB_A_28_IBUFSLICE_X0Y22.CLKTdick0.085AR<31>AR_281.6422.9944.636FSBCLK35.464.6CLKINAR_284J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_28 (SLICE_X0Y22.AX), 1 path -3.510FSB_A<28>AR_28-1.700CLKINAR<31>0.000FSB_A<28>CLKIN0.414FSB_A<28>AR_281K3.PADK3.ITiopi0.763FSB_A<28>FSB_A<28>FSB_A_28_IBUFProtoComp10.IMUX.23SLICE_X0Y22.AXnet21.420FSB_A_28_IBUFSLICE_X0Y22.CLKTckdi0.041AR<31>AR_280.8041.4202.224FSBCLK36.263.8CLKINAR_284J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.B2), 1 path -4.203FSB_A<28>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<28>CLKIN0.414FSB_A<28>OUTt2K3.PADK3.ITiopi0.763FSB_A<28>FSB_A<28>FSB_A_28_IBUFProtoComp10.IMUX.23SLICE_X0Y21.B2net21.776FSB_A_28_IBUFSLICE_X0Y21.CLKTah0.381OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1441.7762.920FSBCLK39.260.8CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.334Paths for end point OUTt (SLICE_X0Y21.B6), 1 path -1.666FSB_A<27>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<27>CLKIN0.414FSB_A<27>OUTt2E1.PADE1.ITiopi1.557FSB_A<27>FSB_A<27>FSB_A_27_IBUFProtoComp10.IMUX.22SLICE_X0Y21.B6net23.772FSB_A_27_IBUFSLICE_X0Y21.CLKTas0.688OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2453.7726.017FSBCLK37.362.7CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_27 (SLICE_X0Y24.DX), 1 path -2.639FSB_A<27>AR_27-3.908CLKINAR<27>12.000FSB_A<27>CLKIN0.414FSB_A<27>AR_271E1.PADE1.ITiopi1.557FSB_A<27>FSB_A<27>FSB_A_27_IBUFProtoComp10.IMUX.22SLICE_X0Y24.DXnet23.397FSB_A_27_IBUFSLICE_X0Y24.CLKTdick0.085AR<27>AR_271.6423.3975.039FSBCLK32.667.4CLKINAR_274J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_27 (SLICE_X0Y24.DX), 1 path -3.698FSB_A<27>AR_27-1.702CLKINAR<27>0.000FSB_A<27>CLKIN0.414FSB_A<27>AR_271E1.PADE1.ITiopi0.763FSB_A<27>FSB_A<27>FSB_A_27_IBUFProtoComp10.IMUX.22SLICE_X0Y24.DXnet21.606FSB_A_27_IBUFSLICE_X0Y24.CLKTckdi0.041AR<27>AR_270.8041.6062.410FSBCLK33.466.6CLKINAR_274J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.B6), 1 path -4.280FSB_A<27>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<27>CLKIN0.414FSB_A<27>OUTt2E1.PADE1.ITiopi0.763FSB_A<27>FSB_A<27>FSB_A_27_IBUFProtoComp10.IMUX.22SLICE_X0Y21.B6net21.853FSB_A_27_IBUFSLICE_X0Y21.CLKTah0.381OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<9>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1441.8532.997FSBCLK38.261.8CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.657Paths for end point OUTt (SLICE_X0Y21.A3), 1 path -2.343FSB_A<26>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<26>CLKIN0.414FSB_A<26>OUTt2H1.PADH1.ITiopi1.557FSB_A<26>FSB_A<26>FSB_A_26_IBUFProtoComp10.IMUX.19SLICE_X0Y21.A3net23.104FSB_A_26_IBUFSLICE_X0Y21.CLKTas0.679OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2363.1045.340FSBCLK41.958.1CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_26 (SLICE_X0Y24.CX), 1 path -3.412FSB_A<26>AR_26-3.908CLKINAR<27>12.000FSB_A<26>CLKIN0.414FSB_A<26>AR_261H1.PADH1.ITiopi1.557FSB_A<26>FSB_A<26>FSB_A_26_IBUFProtoComp10.IMUX.19SLICE_X0Y24.CXnet22.624FSB_A_26_IBUFSLICE_X0Y24.CLKTdick0.085AR<27>AR_261.6422.6244.266FSBCLK38.561.5CLKINAR_264J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_26 (SLICE_X0Y24.CX), 1 path -3.292FSB_A<26>AR_26-1.702CLKINAR<27>0.000FSB_A<26>CLKIN0.414FSB_A<26>AR_261H1.PADH1.ITiopi0.763FSB_A<26>FSB_A<26>FSB_A_26_IBUFProtoComp10.IMUX.19SLICE_X0Y24.CXnet21.200FSB_A_26_IBUFSLICE_X0Y24.CLKTckdi0.041AR<27>AR_260.8041.2002.004FSBCLK40.159.9CLKINAR_264J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.A3), 1 path -3.901FSB_A<26>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<26>CLKIN0.414FSB_A<26>OUTt2H1.PADH1.ITiopi0.763FSB_A<26>FSB_A<26>FSB_A_26_IBUFProtoComp10.IMUX.19SLICE_X0Y21.A3net21.466FSB_A_26_IBUFSLICE_X0Y21.CLKTah0.389OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1521.4662.618FSBCLK44.056.0CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.883Paths for end point OUTt (SLICE_X0Y21.A2), 1 path -2.117FSB_A<25>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<25>CLKIN0.414FSB_A<25>OUTt2H2.PADH2.ITiopi1.557FSB_A<25>FSB_A<25>FSB_A_25_IBUFProtoComp10.IMUX.17SLICE_X0Y21.A2net23.330FSB_A_25_IBUFSLICE_X0Y21.CLKTas0.679OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2363.3305.566FSBCLK40.259.8CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_25 (SLICE_X0Y24.BX), 1 path -3.388FSB_A<25>AR_25-3.908CLKINAR<27>12.000FSB_A<25>CLKIN0.414FSB_A<25>AR_251H2.PADH2.ITiopi1.557FSB_A<25>FSB_A<25>FSB_A_25_IBUFProtoComp10.IMUX.17SLICE_X0Y24.BXnet22.648FSB_A_25_IBUFSLICE_X0Y24.CLKTdick0.085AR<27>AR_251.6422.6484.290FSBCLK38.361.7CLKINAR_254J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_25 (SLICE_X0Y24.BX), 1 path -3.244FSB_A<25>AR_25-1.702CLKINAR<27>0.000FSB_A<25>CLKIN0.414FSB_A<25>AR_251H2.PADH2.ITiopi0.763FSB_A<25>FSB_A<25>FSB_A_25_IBUFProtoComp10.IMUX.17SLICE_X0Y24.BXnet21.152FSB_A_25_IBUFSLICE_X0Y24.CLKTckdi0.041AR<27>AR_250.8041.1521.956FSBCLK41.158.9CLKINAR_254J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.A2), 1 path -3.974FSB_A<25>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<25>CLKIN0.414FSB_A<25>OUTt2H2.PADH2.ITiopi0.763FSB_A<25>FSB_A<25>FSB_A_25_IBUFProtoComp10.IMUX.17SLICE_X0Y21.A2net21.539FSB_A_25_IBUFSLICE_X0Y21.CLKTah0.389OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1521.5392.691FSBCLK42.857.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.026Paths for end point OUTt (SLICE_X0Y21.A6), 1 path -1.974FSB_A<24>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<24>CLKIN0.414FSB_A<24>OUTt2E2.PADE2.ITiopi1.557FSB_A<24>FSB_A<24>FSB_A_24_IBUFProtoComp10.IMUX.15SLICE_X0Y21.A6net23.473FSB_A_24_IBUFSLICE_X0Y21.CLKTas0.679OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2363.4735.709FSBCLK39.260.8CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_24 (SLICE_X0Y24.AX), 1 path -2.633FSB_A<24>AR_24-3.908CLKINAR<27>12.000FSB_A<24>CLKIN0.414FSB_A<24>AR_241E2.PADE2.ITiopi1.557FSB_A<24>FSB_A<24>FSB_A_24_IBUFProtoComp10.IMUX.15SLICE_X0Y24.AXnet23.403FSB_A_24_IBUFSLICE_X0Y24.CLKTdick0.085AR<27>AR_241.6423.4035.045FSBCLK32.567.5CLKINAR_244J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_24 (SLICE_X0Y24.AX), 1 path -3.679FSB_A<24>AR_24-1.702CLKINAR<27>0.000FSB_A<24>CLKIN0.414FSB_A<24>AR_241E2.PADE2.ITiopi0.763FSB_A<24>FSB_A<24>FSB_A_24_IBUFProtoComp10.IMUX.15SLICE_X0Y24.AXnet21.587FSB_A_24_IBUFSLICE_X0Y24.CLKTckdi0.041AR<27>AR_240.8041.5872.391FSBCLK33.666.4CLKINAR_244J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y24.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.A6), 1 path -4.040FSB_A<24>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<24>CLKIN0.414FSB_A<24>OUTt2E2.PADE2.ITiopi0.763FSB_A<24>FSB_A<24>FSB_A_24_IBUFProtoComp10.IMUX.15SLICE_X0Y21.A6net21.605FSB_A_24_IBUFSLICE_X0Y21.CLKTah0.389OUTt_OBUFMcompar_FSB_A[31]_AR[31]_equal_2_o_lut<8>CPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1521.6052.757FSBCLK41.858.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.737Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.263FSB_A<23>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<23>CLKIN0.414FSB_A<23>OUTt3F1.PADF1.ITiopi1.557FSB_A<23>FSB_A<23>FSB_A_23_IBUFProtoComp10.IMUX.12SLICE_X0Y20.D5net23.250FSB_A_23_IBUFSLICE_X0Y20.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.1673.2535.420FSBCLK40.060.0CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_23 (SLICE_X0Y23.DX), 1 path -3.095FSB_A<23>AR_23-3.908CLKINAR<23>12.000FSB_A<23>CLKIN0.414FSB_A<23>AR_231F1.PADF1.ITiopi1.557FSB_A<23>FSB_A<23>FSB_A_23_IBUFProtoComp10.IMUX.12SLICE_X0Y23.DXnet22.941FSB_A_23_IBUFSLICE_X0Y23.CLKTdick0.085AR<23>AR_231.6422.9414.583FSBCLK35.864.2CLKINAR_234J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_23 (SLICE_X0Y23.DX), 1 path -3.472FSB_A<23>AR_23-1.702CLKINAR<23>0.000FSB_A<23>CLKIN0.414FSB_A<23>AR_231F1.PADF1.ITiopi0.763FSB_A<23>FSB_A<23>FSB_A_23_IBUFProtoComp10.IMUX.12SLICE_X0Y23.DXnet21.380FSB_A_23_IBUFSLICE_X0Y23.CLKTckdi0.041AR<23>AR_230.8041.3802.184FSBCLK36.863.2CLKINAR_234J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.916FSB_A<23>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<23>CLKIN0.414FSB_A<23>OUTt3F1.PADF1.ITiopi0.763FSB_A<23>FSB_A<23>FSB_A_23_IBUFProtoComp10.IMUX.12SLICE_X0Y20.D5net21.533FSB_A_23_IBUFSLICE_X0Y20.COUTTopcyd0.187Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0991.5342.633FSBCLK41.758.3CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.907Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.093FSB_A<22>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<22>CLKIN0.414FSB_A<22>OUTt3F2.PADF2.ITiopi1.557FSB_A<22>FSB_A<22>FSB_A_22_IBUFProtoComp10.IMUX.9SLICE_X0Y20.D3net23.420FSB_A_22_IBUFSLICE_X0Y20.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.1673.4235.590FSBCLK38.861.2CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_22 (SLICE_X0Y23.CX), 1 path -2.712FSB_A<22>AR_22-3.908CLKINAR<23>12.000FSB_A<22>CLKIN0.414FSB_A<22>AR_221F2.PADF2.ITiopi1.557FSB_A<22>FSB_A<22>FSB_A_22_IBUFProtoComp10.IMUX.9SLICE_X0Y23.CXnet23.324FSB_A_22_IBUFSLICE_X0Y23.CLKTdick0.085AR<23>AR_221.6423.3244.966FSBCLK33.166.9CLKINAR_224J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_22 (SLICE_X0Y23.CX), 1 path -3.637FSB_A<22>AR_22-1.702CLKINAR<23>0.000FSB_A<22>CLKIN0.414FSB_A<22>AR_221F2.PADF2.ITiopi0.763FSB_A<22>FSB_A<22>FSB_A_22_IBUFProtoComp10.IMUX.9SLICE_X0Y23.CXnet21.545FSB_A_22_IBUFSLICE_X0Y23.CLKTckdi0.041AR<23>AR_220.8041.5452.349FSBCLK34.265.8CLKINAR_224J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.965FSB_A<22>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<22>CLKIN0.414FSB_A<22>OUTt3F2.PADF2.ITiopi0.763FSB_A<22>FSB_A<22>FSB_A_22_IBUFProtoComp10.IMUX.9SLICE_X0Y20.D3net21.582FSB_A_22_IBUFSLICE_X0Y20.COUTTopcyd0.187Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0991.5832.682FSBCLK41.059.0CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.275Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.725FSB_A<21>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<21>CLKIN0.414FSB_A<21>OUTt3J6.PADJ6.ITiopi1.557FSB_A<21>FSB_A<21>FSB_A_21_IBUFProtoComp10.IMUX.7SLICE_X0Y20.D6net23.788FSB_A_21_IBUFSLICE_X0Y20.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.1673.7915.958FSBCLK36.463.6CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_21 (SLICE_X0Y23.BX), 1 path -2.601FSB_A<21>AR_21-3.908CLKINAR<23>12.000FSB_A<21>CLKIN0.414FSB_A<21>AR_211J6.PADJ6.ITiopi1.557FSB_A<21>FSB_A<21>FSB_A_21_IBUFProtoComp10.IMUX.7SLICE_X0Y23.BXnet23.435FSB_A_21_IBUFSLICE_X0Y23.CLKTdick0.085AR<23>AR_211.6423.4355.077FSBCLK32.367.7CLKINAR_214J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_21 (SLICE_X0Y23.BX), 1 path -3.718FSB_A<21>AR_21-1.702CLKINAR<23>0.000FSB_A<21>CLKIN0.414FSB_A<21>AR_211J6.PADJ6.ITiopi0.763FSB_A<21>FSB_A<21>FSB_A_21_IBUFProtoComp10.IMUX.7SLICE_X0Y23.BXnet21.626FSB_A_21_IBUFSLICE_X0Y23.CLKTckdi0.041AR<23>AR_210.8041.6262.430FSBCLK33.166.9CLKINAR_214J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.203FSB_A<21>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<21>CLKIN0.414FSB_A<21>OUTt3J6.PADJ6.ITiopi0.763FSB_A<21>FSB_A<21>FSB_A_21_IBUFProtoComp10.IMUX.7SLICE_X0Y20.D6net21.820FSB_A_21_IBUFSLICE_X0Y20.COUTTopcyd0.187Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0991.8212.920FSBCLK37.662.4CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.064Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.936FSB_A<20>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<20>CLKIN0.414FSB_A<20>OUTt3L5.PADL5.ITiopi1.557FSB_A<20>FSB_A<20>FSB_A_20_IBUFProtoComp10.IMUX.4SLICE_X0Y20.C5net23.561FSB_A_20_IBUFSLICE_X0Y20.COUTTopcyc0.328Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.1833.5645.747FSBCLK38.062.0CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_20 (SLICE_X0Y23.AX), 1 path -2.969FSB_A<20>AR_20-3.908CLKINAR<23>12.000FSB_A<20>CLKIN0.414FSB_A<20>AR_201L5.PADL5.ITiopi1.557FSB_A<20>FSB_A<20>FSB_A_20_IBUFProtoComp10.IMUX.4SLICE_X0Y23.AXnet23.067FSB_A_20_IBUFSLICE_X0Y23.CLKTdick0.085AR<23>AR_201.6423.0674.709FSBCLK34.965.1CLKINAR_204J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.851FSBCLK-6.3002.392-3.908Hold Paths: COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_20 (SLICE_X0Y23.AX), 1 path -3.578FSB_A<20>AR_20-1.702CLKINAR<23>0.000FSB_A<20>CLKIN0.414FSB_A<20>AR_201L5.PADL5.ITiopi0.763FSB_A<20>FSB_A<20>FSB_A_20_IBUFProtoComp10.IMUX.4SLICE_X0Y23.AXnet21.486FSB_A_20_IBUFSLICE_X0Y23.CLKTckdi0.041AR<23>AR_200.8041.4862.290FSBCLK35.164.9CLKINAR_204J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y23.CLKnet170.793FSBCLK-3.1991.497-1.702Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.126FSB_A<20>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<20>CLKIN0.414FSB_A<20>OUTt3L5.PADL5.ITiopi0.763FSB_A<20>FSB_A<20>FSB_A_20_IBUFProtoComp10.IMUX.4SLICE_X0Y20.C5net21.727FSB_A_20_IBUFSLICE_X0Y20.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1151.7282.843FSBCLK39.260.8CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.995Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.005FSB_A<19>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<19>CLKIN0.414FSB_A<19>OUTt3G3.PADG3.ITiopi1.557FSB_A<19>FSB_A<19>FSB_A_19_IBUFProtoComp10.IMUX.21SLICE_X0Y20.C3net23.492FSB_A_19_IBUFSLICE_X0Y20.COUTTopcyc0.328Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.1833.4955.678FSBCLK38.461.6CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_19 (SLICE_X0Y22.D4), 1 path -2.556FSB_A<19>AR_19-3.906CLKINAR<31>12.000FSB_A<19>CLKIN0.414FSB_A<19>AR_192G3.PADG3.ITiopi1.557FSB_A<19>FSB_A<19>FSB_A_19_IBUFProtoComp10.IMUX.21SLICE_X0Y22.D4net23.367FSB_A_19_IBUFSLICE_X0Y22.CLKTas0.200AR<31>FSB_A_19_IBUF_rtAR_191.7573.3675.124FSBCLK34.365.7CLKINAR_194J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_19 (SLICE_X0Y22.D4), 1 path -3.722FSB_A<19>AR_19-1.700CLKINAR<31>0.000FSB_A<19>CLKIN0.414FSB_A<19>AR_192G3.PADG3.ITiopi0.763FSB_A<19>FSB_A<19>FSB_A_19_IBUFProtoComp10.IMUX.21SLICE_X0Y22.D4net21.542FSB_A_19_IBUFSLICE_X0Y22.CLKTah0.131AR<31>FSB_A_19_IBUF_rtAR_190.8941.5422.436FSBCLK36.763.3CLKINAR_194J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.047FSB_A<19>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<19>CLKIN0.414FSB_A<19>OUTt3G3.PADG3.ITiopi0.763FSB_A<19>FSB_A<19>FSB_A_19_IBUFProtoComp10.IMUX.21SLICE_X0Y20.C3net21.648FSB_A_19_IBUFSLICE_X0Y20.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1151.6492.764FSBCLK40.359.7CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.868Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.132FSB_A<18>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<18>CLKIN0.414FSB_A<18>OUTt3K6.PADK6.ITiopi1.557FSB_A<18>FSB_A<18>FSB_A_18_IBUFProtoComp10.IMUX.18SLICE_X0Y20.C6net23.365FSB_A_18_IBUFSLICE_X0Y20.COUTTopcyc0.328Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.1833.3685.551FSBCLK39.360.7CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_18 (SLICE_X0Y22.C5), 1 path -2.537FSB_A<18>AR_18-3.906CLKINAR<31>12.000FSB_A<18>CLKIN0.414FSB_A<18>AR_182K6.PADK6.ITiopi1.557FSB_A<18>FSB_A<18>FSB_A_18_IBUFProtoComp10.IMUX.18SLICE_X0Y22.C5net23.386FSB_A_18_IBUFSLICE_X0Y22.CLKTas0.200AR<31>FSB_A_18_IBUF_rtAR_181.7573.3865.143FSBCLK34.265.8CLKINAR_184J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_18 (SLICE_X0Y22.C5), 1 path -3.829FSB_A<18>AR_18-1.700CLKINAR<31>0.000FSB_A<18>CLKIN0.414FSB_A<18>AR_182K6.PADK6.ITiopi0.763FSB_A<18>FSB_A<18>FSB_A_18_IBUFProtoComp10.IMUX.18SLICE_X0Y22.C5net21.649FSB_A_18_IBUFSLICE_X0Y22.CLKTah0.131AR<31>FSB_A_18_IBUF_rtAR_180.8941.6492.543FSBCLK35.264.8CLKINAR_184J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.024FSB_A<18>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<18>CLKIN0.414FSB_A<18>OUTt3K6.PADK6.ITiopi0.763FSB_A<18>FSB_A<18>FSB_A_18_IBUFProtoComp10.IMUX.18SLICE_X0Y20.C6net21.625FSB_A_18_IBUFSLICE_X0Y20.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<6>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1151.6262.741FSBCLK40.759.3CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.261Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.739FSB_A<17>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<17>CLKIN0.414FSB_A<17>OUTt3J1.PADJ1.ITiopi1.557FSB_A<17>FSB_A<17>FSB_A_17_IBUFProtoComp10.IMUX.16SLICE_X0Y20.B5net22.603FSB_A_17_IBUFSLICE_X0Y20.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.3382.6064.944FSBCLK47.352.7CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_17 (SLICE_X0Y22.B5), 1 path -3.107FSB_A<17>AR_17-3.906CLKINAR<31>12.000FSB_A<17>CLKIN0.414FSB_A<17>AR_172J1.PADJ1.ITiopi1.557FSB_A<17>FSB_A<17>FSB_A_17_IBUFProtoComp10.IMUX.16SLICE_X0Y22.B5net22.816FSB_A_17_IBUFSLICE_X0Y22.CLKTas0.200AR<31>FSB_A_17_IBUF_rtAR_171.7572.8164.573FSBCLK38.461.6CLKINAR_174J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_17 (SLICE_X0Y22.B5), 1 path -3.474FSB_A<17>AR_17-1.700CLKINAR<31>0.000FSB_A<17>CLKIN0.414FSB_A<17>AR_172J1.PADJ1.ITiopi0.763FSB_A<17>FSB_A<17>FSB_A_17_IBUFProtoComp10.IMUX.16SLICE_X0Y22.B5net21.294FSB_A_17_IBUFSLICE_X0Y22.CLKTah0.131AR<31>FSB_A_17_IBUF_rtAR_170.8941.2942.188FSBCLK40.959.1CLKINAR_174J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.642FSB_A<17>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<17>CLKIN0.414FSB_A<17>OUTt3J1.PADJ1.ITiopi0.763FSB_A<17>FSB_A<17>FSB_A_17_IBUFProtoComp10.IMUX.16SLICE_X0Y20.B5net21.182FSB_A_17_IBUFSLICE_X0Y20.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1761.1832.359FSBCLK49.950.1CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.565Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.435FSB_A<16>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<16>CLKIN0.414FSB_A<16>OUTt3J3.PADJ3.ITiopi1.557FSB_A<16>FSB_A<16>FSB_A_16_IBUFProtoComp10.IMUX.14SLICE_X0Y20.B2net22.907FSB_A_16_IBUFSLICE_X0Y20.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.3382.9105.248FSBCLK44.655.4CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_16 (SLICE_X0Y22.A2), 1 path -3.047FSB_A<16>AR_16-3.906CLKINAR<31>12.000FSB_A<16>CLKIN0.414FSB_A<16>AR_162J3.PADJ3.ITiopi1.557FSB_A<16>FSB_A<16>FSB_A_16_IBUFProtoComp10.IMUX.14SLICE_X0Y22.A2net22.876FSB_A_16_IBUFSLICE_X0Y22.CLKTas0.200AR<31>FSB_A_16_IBUF_rtAR_161.7572.8764.633FSBCLK37.962.1CLKINAR_164J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.853FSBCLK-6.3002.394-3.906Hold Paths: COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_16 (SLICE_X0Y22.A2), 1 path -3.493FSB_A<16>AR_16-1.700CLKINAR<31>0.000FSB_A<16>CLKIN0.414FSB_A<16>AR_162J3.PADJ3.ITiopi0.763FSB_A<16>FSB_A<16>FSB_A_16_IBUFProtoComp10.IMUX.14SLICE_X0Y22.A2net21.313FSB_A_16_IBUFSLICE_X0Y22.CLKTah0.131AR<31>FSB_A_16_IBUF_rtAR_160.8941.3132.207FSBCLK40.559.5CLKINAR_164J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y22.CLKnet170.795FSBCLK-3.1991.499-1.700Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.745FSB_A<16>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<16>CLKIN0.414FSB_A<16>OUTt3J3.PADJ3.ITiopi0.763FSB_A<16>FSB_A<16>FSB_A_16_IBUFProtoComp10.IMUX.14SLICE_X0Y20.B2net21.285FSB_A_16_IBUFSLICE_X0Y20.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1761.2862.462FSBCLK47.852.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.096Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.904FSB_A<15>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<15>CLKIN0.414FSB_A<15>OUTt3M5.PADM5.ITiopi1.557FSB_A<15>FSB_A<15>FSB_A_15_IBUFProtoComp10.IMUX.11SLICE_X0Y20.B6net23.438FSB_A_15_IBUFSLICE_X0Y20.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.3383.4415.779FSBCLK40.559.5CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_15 (SLICE_X1Y20.DX), 1 path -2.288FSB_A<15>AR_15-3.900CLKINAR<15>12.000FSB_A<15>CLKIN0.414FSB_A<15>AR_151M5.PADM5.ITiopi1.557FSB_A<15>FSB_A<15>FSB_A_15_IBUFProtoComp10.IMUX.11SLICE_X1Y20.DXnet23.727FSB_A_15_IBUFSLICE_X1Y20.CLKTdick0.114AR<15>AR_151.6713.7275.398FSBCLK31.069.0CLKINAR_154J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.859FSBCLK-6.3002.400-3.900Hold Paths: COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_15 (SLICE_X1Y20.DX), 1 path -3.834FSB_A<15>AR_15-1.694CLKINAR<15>0.000FSB_A<15>CLKIN0.414FSB_A<15>AR_151M5.PADM5.ITiopi0.763FSB_A<15>FSB_A<15>FSB_A_15_IBUFProtoComp10.IMUX.11SLICE_X1Y20.DXnet21.732FSB_A_15_IBUFSLICE_X1Y20.CLKTckdi0.059AR<15>AR_150.8221.7322.554FSBCLK32.267.8CLKINAR_154J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.801FSBCLK-3.1991.505-1.694Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.030FSB_A<15>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<15>CLKIN0.414FSB_A<15>OUTt3M5.PADM5.ITiopi0.763FSB_A<15>FSB_A<15>FSB_A_15_IBUFProtoComp10.IMUX.11SLICE_X0Y20.B6net21.570FSB_A_15_IBUFSLICE_X0Y20.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<5>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1761.5712.747FSBCLK42.857.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.084Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.916FSB_A<14>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<14>CLKIN0.414FSB_A<14>OUTt3K2.PADK2.ITiopi1.557FSB_A<14>FSB_A<14>FSB_A_14_IBUFProtoComp10.IMUX.8SLICE_X0Y20.A4net22.435FSB_A_14_IBUFSLICE_X0Y20.COUTTopcya0.474Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.3292.4384.767FSBCLK48.951.1CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_14 (SLICE_X1Y20.CX), 1 path -3.418FSB_A<14>AR_14-3.900CLKINAR<15>12.000FSB_A<14>CLKIN0.414FSB_A<14>AR_141K2.PADK2.ITiopi1.557FSB_A<14>FSB_A<14>FSB_A_14_IBUFProtoComp10.IMUX.8SLICE_X1Y20.CXnet22.597FSB_A_14_IBUFSLICE_X1Y20.CLKTdick0.114AR<15>AR_141.6712.5974.268FSBCLK39.260.8CLKINAR_144J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.859FSBCLK-6.3002.400-3.900Hold Paths: COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_14 (SLICE_X1Y20.CX), 1 path -3.242FSB_A<14>AR_14-1.694CLKINAR<15>0.000FSB_A<14>CLKIN0.414FSB_A<14>AR_141K2.PADK2.ITiopi0.763FSB_A<14>FSB_A<14>FSB_A_14_IBUFProtoComp10.IMUX.8SLICE_X1Y20.CXnet21.140FSB_A_14_IBUFSLICE_X1Y20.CLKTckdi0.059AR<15>AR_140.8221.1401.962FSBCLK41.958.1CLKINAR_144J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.801FSBCLK-3.1991.505-1.694Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.489FSB_A<14>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<14>CLKIN0.414FSB_A<14>OUTt3K2.PADK2.ITiopi0.763FSB_A<14>FSB_A<14>FSB_A_14_IBUFProtoComp10.IMUX.8SLICE_X0Y20.A4net21.021FSB_A_14_IBUFSLICE_X0Y20.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1841.0222.206FSBCLK53.746.3CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.011Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.989FSB_A<13>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<13>CLKIN0.414FSB_A<13>OUTt3N3.PADN3.ITiopi1.557FSB_A<13>FSB_A<13>FSB_A_13_IBUFProtoComp10.IMUX.6SLICE_X0Y20.A3net23.362FSB_A_13_IBUFSLICE_X0Y20.COUTTopcya0.474Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.3293.3655.694FSBCLK40.959.1CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_13 (SLICE_X1Y20.BX), 1 path -2.551FSB_A<13>AR_13-3.900CLKINAR<15>12.000FSB_A<13>CLKIN0.414FSB_A<13>AR_131N3.PADN3.ITiopi1.557FSB_A<13>FSB_A<13>FSB_A_13_IBUFProtoComp10.IMUX.6SLICE_X1Y20.BXnet23.464FSB_A_13_IBUFSLICE_X1Y20.CLKTdick0.114AR<15>AR_131.6713.4645.135FSBCLK32.567.5CLKINAR_134J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.859FSBCLK-6.3002.400-3.900Hold Paths: COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_13 (SLICE_X1Y20.BX), 1 path -3.709FSB_A<13>AR_13-1.694CLKINAR<15>0.000FSB_A<13>CLKIN0.414FSB_A<13>AR_131N3.PADN3.ITiopi0.763FSB_A<13>FSB_A<13>FSB_A_13_IBUFProtoComp10.IMUX.6SLICE_X1Y20.BXnet21.607FSB_A_13_IBUFSLICE_X1Y20.CLKTckdi0.059AR<15>AR_130.8221.6072.429FSBCLK33.866.2CLKINAR_134J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.801FSBCLK-3.1991.505-1.694Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.009FSB_A<13>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<13>CLKIN0.414FSB_A<13>OUTt3N3.PADN3.ITiopi0.763FSB_A<13>FSB_A<13>FSB_A_13_IBUFProtoComp10.IMUX.6SLICE_X0Y20.A3net21.541FSB_A_13_IBUFSLICE_X0Y20.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1841.5422.726FSBCLK43.456.6CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.821Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.179FSB_A<12>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<12>CLKIN0.414FSB_A<12>OUTt3P2.PADP2.ITiopi1.557FSB_A<12>FSB_A<12>FSB_A_12_IBUFProtoComp10.IMUX.3SLICE_X0Y20.A6net23.172FSB_A_12_IBUFSLICE_X0Y20.COUTTopcya0.474Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.3293.1755.504FSBCLK42.357.7CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_12 (SLICE_X1Y20.AX), 1 path -2.724FSB_A<12>AR_12-3.900CLKINAR<15>12.000FSB_A<12>CLKIN0.414FSB_A<12>AR_121P2.PADP2.ITiopi1.557FSB_A<12>FSB_A<12>FSB_A_12_IBUFProtoComp10.IMUX.3SLICE_X1Y20.AXnet23.291FSB_A_12_IBUFSLICE_X1Y20.CLKTdick0.114AR<15>AR_121.6713.2914.962FSBCLK33.766.3CLKINAR_124J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.859FSBCLK-6.3002.400-3.900Hold Paths: COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_12 (SLICE_X1Y20.AX), 1 path -3.605FSB_A<12>AR_12-1.694CLKINAR<15>0.000FSB_A<12>CLKIN0.414FSB_A<12>AR_121P2.PADP2.ITiopi0.763FSB_A<12>FSB_A<12>FSB_A_12_IBUFProtoComp10.IMUX.3SLICE_X1Y20.AXnet21.503FSB_A_12_IBUFSLICE_X1Y20.CLKTckdi0.059AR<15>AR_120.8221.5032.325FSBCLK35.464.6CLKINAR_124J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X1Y20.CLKnet170.801FSBCLK-3.1991.505-1.694Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.895FSB_A<12>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<12>CLKIN0.414FSB_A<12>OUTt3P2.PADP2.ITiopi0.763FSB_A<12>FSB_A<12>FSB_A_12_IBUFProtoComp10.IMUX.3SLICE_X0Y20.A6net21.427FSB_A_12_IBUFSLICE_X0Y20.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<4>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1841.4282.612FSBCLK45.354.7CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.522Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.478FSB_A<11>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<11>CLKIN0.414FSB_A<11>OUTt4L1.PADL1.ITiopi1.557FSB_A<11>FSB_A<11>FSB_A_11_IBUFProtoComp10.IMUX.2SLICE_X0Y19.D3net22.939FSB_A_11_IBUFSLICE_X0Y19.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2602.9455.205FSBCLK43.456.6CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_11 (SLICE_X0Y17.DX), 1 path -3.494FSB_A<11>AR_11-3.895CLKINAR<11>12.000FSB_A<11>CLKIN0.414FSB_A<11>AR_111L1.PADL1.ITiopi1.557FSB_A<11>FSB_A<11>FSB_A_11_IBUFProtoComp10.IMUX.2SLICE_X0Y17.DXnet22.555FSB_A_11_IBUFSLICE_X0Y17.CLKTdick0.085AR<11>AR_111.6422.5554.197FSBCLK39.160.9CLKINAR_114J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_11 (SLICE_X0Y17.DX), 1 path -3.200FSB_A<11>AR_11-1.689CLKINAR<11>0.000FSB_A<11>CLKIN0.414FSB_A<11>AR_111L1.PADL1.ITiopi0.763FSB_A<11>FSB_A<11>FSB_A_11_IBUFProtoComp10.IMUX.2SLICE_X0Y17.DXnet21.121FSB_A_11_IBUFSLICE_X0Y17.CLKTckdi0.041AR<11>AR_110.8041.1211.925FSBCLK41.858.2CLKINAR_114J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.798FSB_A<11>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<11>CLKIN0.414FSB_A<11>OUTt4L1.PADL1.ITiopi0.763FSB_A<11>FSB_A<11>FSB_A_11_IBUFProtoComp10.IMUX.2SLICE_X0Y19.D3net21.382FSB_A_11_IBUFSLICE_X0Y19.COUTTopcyd0.187Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1311.3842.515FSBCLK45.055.0CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.562Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.438FSB_A<10>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<10>CLKIN0.414FSB_A<10>OUTt4N1.PADN1.ITiopi1.557FSB_A<10>FSB_A<10>FSB_A_10_IBUFProtoComp10.IMUXSLICE_X0Y19.D4net22.979FSB_A_10_IBUFSLICE_X0Y19.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2602.9855.245FSBCLK43.156.9CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_10 (SLICE_X0Y17.CX), 1 path -3.113FSB_A<10>AR_10-3.895CLKINAR<11>12.000FSB_A<10>CLKIN0.414FSB_A<10>AR_101N1.PADN1.ITiopi1.557FSB_A<10>FSB_A<10>FSB_A_10_IBUFProtoComp10.IMUXSLICE_X0Y17.CXnet22.936FSB_A_10_IBUFSLICE_X0Y17.CLKTdick0.085AR<11>AR_101.6422.9364.578FSBCLK35.964.1CLKINAR_104J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_10 (SLICE_X0Y17.CX), 1 path -3.463FSB_A<10>AR_10-1.689CLKINAR<11>0.000FSB_A<10>CLKIN0.414FSB_A<10>AR_101N1.PADN1.ITiopi0.763FSB_A<10>FSB_A<10>FSB_A_10_IBUFProtoComp10.IMUXSLICE_X0Y17.CXnet21.384FSB_A_10_IBUFSLICE_X0Y17.CLKTckdi0.041AR<11>AR_100.8041.3842.188FSBCLK36.763.3CLKINAR_104J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.800FSB_A<10>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<10>CLKIN0.414FSB_A<10>OUTt4N1.PADN1.ITiopi0.763FSB_A<10>FSB_A<10>FSB_A_10_IBUFProtoComp10.IMUXSLICE_X0Y19.D4net21.384FSB_A_10_IBUFSLICE_X0Y19.COUTTopcyd0.187Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1311.3862.517FSBCLK44.955.1CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.009Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.991FSB_A<9>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<9>CLKIN0.414FSB_A<9>OUTt4R1.PADR1.ITiopi1.557FSB_A<9>FSB_A<9>FSB_A_9_IBUFProtoComp10.IMUX.34SLICE_X0Y19.D6net23.426FSB_A_9_IBUFSLICE_X0Y19.COUTTopcyd0.312Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2603.4325.692FSBCLK39.760.3CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_9 (SLICE_X0Y17.BX), 1 path -2.827FSB_A<9>AR_9-3.895CLKINAR<11>12.000FSB_A<9>CLKIN0.414FSB_A<9>AR_91R1.PADR1.ITiopi1.557FSB_A<9>FSB_A<9>FSB_A_9_IBUFProtoComp10.IMUX.34SLICE_X0Y17.BXnet23.222FSB_A_9_IBUFSLICE_X0Y17.CLKTdick0.085AR<11>AR_91.6423.2224.864FSBCLK33.866.2CLKINAR_94J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_9 (SLICE_X0Y17.BX), 1 path -3.618FSB_A<9>AR_9-1.689CLKINAR<11>0.000FSB_A<9>CLKIN0.414FSB_A<9>AR_91R1.PADR1.ITiopi0.763FSB_A<9>FSB_A<9>FSB_A_9_IBUFProtoComp10.IMUX.34SLICE_X0Y17.BXnet21.539FSB_A_9_IBUFSLICE_X0Y17.CLKTckdi0.041AR<11>AR_90.8041.5392.343FSBCLK34.365.7CLKINAR_94J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.045FSB_A<9>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<9>CLKIN0.414FSB_A<9>OUTt4R1.PADR1.ITiopi0.763FSB_A<9>FSB_A<9>FSB_A_9_IBUFProtoComp10.IMUX.34SLICE_X0Y19.D6net21.629FSB_A_9_IBUFSLICE_X0Y19.COUTTopcyd0.187Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1311.6312.762FSBCLK40.959.1CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.287Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.713FSB_A<8>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<8>CLKIN0.414FSB_A<8>OUTt4M4.PADM4.ITiopi1.557FSB_A<8>FSB_A<8>FSB_A_8_IBUFProtoComp10.IMUX.33SLICE_X0Y19.C6net23.688FSB_A_8_IBUFSLICE_X0Y19.COUTTopcyc0.328Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2763.6945.970FSBCLK38.161.9CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_8 (SLICE_X0Y17.AX), 1 path -2.446FSB_A<8>AR_8-3.895CLKINAR<11>12.000FSB_A<8>CLKIN0.414FSB_A<8>AR_81M4.PADM4.ITiopi1.557FSB_A<8>FSB_A<8>FSB_A_8_IBUFProtoComp10.IMUX.33SLICE_X0Y17.AXnet23.603FSB_A_8_IBUFSLICE_X0Y17.CLKTdick0.085AR<11>AR_81.6423.6035.245FSBCLK31.368.7CLKINAR_84J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_8 (SLICE_X0Y17.AX), 1 path -3.756FSB_A<8>AR_8-1.689CLKINAR<11>0.000FSB_A<8>CLKIN0.414FSB_A<8>AR_81M4.PADM4.ITiopi0.763FSB_A<8>FSB_A<8>FSB_A_8_IBUFProtoComp10.IMUX.33SLICE_X0Y17.AXnet21.677FSB_A_8_IBUFSLICE_X0Y17.CLKTckdi0.041AR<11>AR_80.8041.6772.481FSBCLK32.467.6CLKINAR_84J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y17.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.144FSB_A<8>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<8>CLKIN0.414FSB_A<8>OUTt4M4.PADM4.ITiopi0.763FSB_A<8>FSB_A<8>FSB_A_8_IBUFProtoComp10.IMUX.33SLICE_X0Y19.C6net21.712FSB_A_8_IBUFSLICE_X0Y19.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1471.7142.861FSBCLK40.159.9CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.757Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.243FSB_A<7>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<7>CLKIN0.414FSB_A<7>OUTt4P1.PADP1.ITiopi1.557FSB_A<7>FSB_A<7>FSB_A_7_IBUFProtoComp10.IMUX.32SLICE_X0Y19.C4net23.158FSB_A_7_IBUFSLICE_X0Y19.COUTTopcyc0.328Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2763.1645.440FSBCLK41.858.2CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_7 (SLICE_X0Y18.DX), 1 path -3.106FSB_A<7>AR_7-3.896CLKINAR<7>12.000FSB_A<7>CLKIN0.414FSB_A<7>AR_71P1.PADP1.ITiopi1.557FSB_A<7>FSB_A<7>FSB_A_7_IBUFProtoComp10.IMUX.32SLICE_X0Y18.DXnet22.942FSB_A_7_IBUFSLICE_X0Y18.CLKTdick0.085AR<7>AR_71.6422.9424.584FSBCLK35.864.2CLKINAR_74J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.863FSBCLK-6.3002.404-3.896Hold Paths: COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_7 (SLICE_X0Y18.DX), 1 path -3.464FSB_A<7>AR_7-1.690CLKINAR<7>0.000FSB_A<7>CLKIN0.414FSB_A<7>AR_71P1.PADP1.ITiopi0.763FSB_A<7>FSB_A<7>FSB_A_7_IBUFProtoComp10.IMUX.32SLICE_X0Y18.DXnet21.384FSB_A_7_IBUFSLICE_X0Y18.CLKTckdi0.041AR<7>AR_70.8041.3842.188FSBCLK36.763.3CLKINAR_74J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.805FSBCLK-3.1991.509-1.690Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.935FSB_A<7>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<7>CLKIN0.414FSB_A<7>OUTt4P1.PADP1.ITiopi0.763FSB_A<7>FSB_A<7>FSB_A_7_IBUFProtoComp10.IMUX.32SLICE_X0Y19.C4net21.503FSB_A_7_IBUFSLICE_X0Y19.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1471.5052.652FSBCLK43.356.7CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.919Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.081FSB_A<6>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<6>CLKIN0.414FSB_A<6>OUTt4M3.PADM3.ITiopi1.557FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp10.IMUX.31SLICE_X0Y19.C3net23.320FSB_A_6_IBUFSLICE_X0Y19.COUTTopcyc0.328Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.2763.3265.602FSBCLK40.659.4CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_6 (SLICE_X0Y18.CX), 1 path -2.819FSB_A<6>AR_6-3.896CLKINAR<7>12.000FSB_A<6>CLKIN0.414FSB_A<6>AR_61M3.PADM3.ITiopi1.557FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp10.IMUX.31SLICE_X0Y18.CXnet23.229FSB_A_6_IBUFSLICE_X0Y18.CLKTdick0.085AR<7>AR_61.6423.2294.871FSBCLK33.766.3CLKINAR_64J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.863FSBCLK-6.3002.404-3.896Hold Paths: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_6 (SLICE_X0Y18.CX), 1 path -3.621FSB_A<6>AR_6-1.690CLKINAR<7>0.000FSB_A<6>CLKIN0.414FSB_A<6>AR_61M3.PADM3.ITiopi0.763FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp10.IMUX.31SLICE_X0Y18.CXnet21.541FSB_A_6_IBUFSLICE_X0Y18.CLKTckdi0.041AR<7>AR_60.8041.5412.345FSBCLK34.365.7CLKINAR_64J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.805FSBCLK-3.1991.509-1.690Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.035FSB_A<6>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<6>CLKIN0.414FSB_A<6>OUTt4M3.PADM3.ITiopi0.763FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp10.IMUX.31SLICE_X0Y19.C3net21.603FSB_A_6_IBUFSLICE_X0Y19.COUTTopcyc0.203Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<2>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.1471.6052.752FSBCLK41.758.3CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.265Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.735FSB_A<5>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<5>CLKIN0.414FSB_A<5>OUTt4K1.PADK1.ITiopi1.557FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp10.IMUX.30SLICE_X0Y19.B2net22.511FSB_A_5_IBUFSLICE_X0Y19.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.4312.5174.948FSBCLK49.150.9CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_5 (SLICE_X0Y18.BX), 1 path -3.569FSB_A<5>AR_5-3.896CLKINAR<7>12.000FSB_A<5>CLKIN0.414FSB_A<5>AR_51K1.PADK1.ITiopi1.557FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp10.IMUX.30SLICE_X0Y18.BXnet22.479FSB_A_5_IBUFSLICE_X0Y18.CLKTdick0.085AR<7>AR_51.6422.4794.121FSBCLK39.860.2CLKINAR_54J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.863FSBCLK-6.3002.404-3.896Hold Paths: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_5 (SLICE_X0Y18.BX), 1 path -3.204FSB_A<5>AR_5-1.690CLKINAR<7>0.000FSB_A<5>CLKIN0.414FSB_A<5>AR_51K1.PADK1.ITiopi0.763FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp10.IMUX.30SLICE_X0Y18.BXnet21.124FSB_A_5_IBUFSLICE_X0Y18.CLKTckdi0.041AR<7>AR_50.8041.1241.928FSBCLK41.758.3CLKINAR_54J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.805FSBCLK-3.1991.509-1.690Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.631FSB_A<5>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<5>CLKIN0.414FSB_A<5>OUTt4K1.PADK1.ITiopi0.763FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp10.IMUX.30SLICE_X0Y19.B2net21.138FSB_A_5_IBUFSLICE_X0Y19.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2081.1402.348FSBCLK51.448.6CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.766Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.234FSB_A<4>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<4>CLKIN0.414FSB_A<4>OUTt4L3.PADL3.ITiopi1.557FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp10.IMUX.29SLICE_X0Y19.B3net23.012FSB_A_4_IBUFSLICE_X0Y19.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.4313.0185.449FSBCLK44.655.4CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_4 (SLICE_X0Y18.AX), 1 path -3.246FSB_A<4>AR_4-3.896CLKINAR<7>12.000FSB_A<4>CLKIN0.414FSB_A<4>AR_41L3.PADL3.ITiopi1.557FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp10.IMUX.29SLICE_X0Y18.AXnet22.802FSB_A_4_IBUFSLICE_X0Y18.CLKTdick0.085AR<7>AR_41.6422.8024.444FSBCLK36.963.1CLKINAR_44J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.863FSBCLK-6.3002.404-3.896Hold Paths: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_4 (SLICE_X0Y18.AX), 1 path -3.288FSB_A<4>AR_4-1.690CLKINAR<7>0.000FSB_A<4>CLKIN0.414FSB_A<4>AR_41L3.PADL3.ITiopi0.763FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp10.IMUX.29SLICE_X0Y18.AXnet21.208FSB_A_4_IBUFSLICE_X0Y18.CLKTckdi0.041AR<7>AR_40.8041.2082.012FSBCLK40.060.0CLKINAR_44J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y18.CLKnet170.805FSBCLK-3.1991.509-1.690Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.832FSB_A<4>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<4>CLKIN0.414FSB_A<4>OUTt4L3.PADL3.ITiopi0.763FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp10.IMUX.29SLICE_X0Y19.B3net21.339FSB_A_4_IBUFSLICE_X0Y19.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2081.3412.549FSBCLK47.452.6CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.480Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.520FSB_A<3>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<3>CLKIN0.414FSB_A<3>OUTt4R2.PADR2.ITiopi1.557FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp10.IMUX.28SLICE_X0Y19.B6net23.726FSB_A_3_IBUFSLICE_X0Y19.COUTTopcyb0.483Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.4313.7326.163FSBCLK39.460.6CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_3 (SLICE_X0Y16.DX), 1 path -2.439FSB_A<3>AR_3-3.895CLKINAR<3>12.000FSB_A<3>CLKIN0.414FSB_A<3>AR_31R2.PADR2.ITiopi1.557FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp10.IMUX.28SLICE_X0Y16.DXnet23.610FSB_A_3_IBUFSLICE_X0Y16.CLKTdick0.085AR<3>AR_31.6423.6105.252FSBCLK31.368.7CLKINAR_34J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_3 (SLICE_X0Y16.DX), 1 path -3.772FSB_A<3>AR_3-1.689CLKINAR<3>0.000FSB_A<3>CLKIN0.414FSB_A<3>AR_31R2.PADR2.ITiopi0.763FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp10.IMUX.28SLICE_X0Y16.DXnet21.693FSB_A_3_IBUFSLICE_X0Y16.CLKTckdi0.041AR<3>AR_30.8041.6932.497FSBCLK32.267.8CLKINAR_34J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.244FSB_A<3>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<3>CLKIN0.414FSB_A<3>OUTt4R2.PADR2.ITiopi0.763FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp10.IMUX.28SLICE_X0Y19.B6net21.751FSB_A_3_IBUFSLICE_X0Y19.COUTTopcyb0.264Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<1>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2081.7532.961FSBCLK40.859.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.842Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.158FSB_A<2>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<2>CLKIN0.414FSB_A<2>OUTt4M2.PADM2.ITiopi1.557FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp10.IMUX.27SLICE_X0Y19.A3net23.097FSB_A_2_IBUFSLICE_X0Y19.COUTTopcya0.474Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.4223.1035.525FSBCLK43.856.2CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_2 (SLICE_X0Y16.CX), 1 path -3.407FSB_A<2>AR_2-3.895CLKINAR<3>12.000FSB_A<2>CLKIN0.414FSB_A<2>AR_21M2.PADM2.ITiopi1.557FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp10.IMUX.27SLICE_X0Y16.CXnet22.642FSB_A_2_IBUFSLICE_X0Y16.CLKTdick0.085AR<3>AR_21.6422.6424.284FSBCLK38.361.7CLKINAR_24J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_2 (SLICE_X0Y16.CX), 1 path -3.237FSB_A<2>AR_2-1.689CLKINAR<3>0.000FSB_A<2>CLKIN0.414FSB_A<2>AR_21M2.PADM2.ITiopi0.763FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp10.IMUX.27SLICE_X0Y16.CXnet21.158FSB_A_2_IBUFSLICE_X0Y16.CLKTckdi0.041AR<3>AR_20.8041.1581.962FSBCLK41.059.0CLKINAR_24J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.900FSB_A<2>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<2>CLKIN0.414FSB_A<2>OUTt4M2.PADM2.ITiopi0.763FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp10.IMUX.27SLICE_X0Y19.A3net21.399FSB_A_2_IBUFSLICE_X0Y19.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2161.4012.617FSBCLK46.553.5CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";20000209.876Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -2.124FSB_A<1>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<1>CLKIN0.414FSB_A<1>OUTt4M1.PADM1.ITiopi1.557FSB_A<1>FSB_A<1>FSB_A_1_IBUFProtoComp10.IMUX.26SLICE_X0Y19.A2net23.131FSB_A_1_IBUFSLICE_X0Y19.COUTTopcya0.474Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.4223.1375.559FSBCLK43.656.4CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_1 (SLICE_X0Y16.BX), 1 path -3.520FSB_A<1>AR_1-3.895CLKINAR<3>12.000FSB_A<1>CLKIN0.414FSB_A<1>AR_11M1.PADM1.ITiopi1.557FSB_A<1>FSB_A<1>FSB_A_1_IBUFProtoComp10.IMUX.26SLICE_X0Y16.BXnet22.529FSB_A_1_IBUFSLICE_X0Y16.CLKTdick0.085AR<3>AR_11.6422.5294.171FSBCLK39.460.6CLKINAR_14J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_1 (SLICE_X0Y16.BX), 1 path -3.242FSB_A<1>AR_1-1.689CLKINAR<3>0.000FSB_A<1>CLKIN0.414FSB_A<1>AR_11M1.PADM1.ITiopi0.763FSB_A<1>FSB_A<1>FSB_A_1_IBUFProtoComp10.IMUX.26SLICE_X0Y16.BXnet21.163FSB_A_1_IBUFSLICE_X0Y16.CLKTckdi0.041AR<3>AR_10.8041.1631.967FSBCLK40.959.1CLKINAR_14J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -3.992FSB_A<1>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<1>CLKIN0.414FSB_A<1>OUTt4M1.PADM1.ITiopi0.763FSB_A<1>FSB_A<1>FSB_A_1_IBUFProtoComp10.IMUX.26SLICE_X0Y19.A2net21.491FSB_A_1_IBUFSLICE_X0Y19.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2161.4932.709FSBCLK44.955.1CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";200002010.028Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -1.972FSB_A<0>OUTt-3.903CLKINOUTt_OBUF12.000FSB_A<0>CLKIN0.414FSB_A<0>OUTt4N4.PADN4.ITiopi1.557FSB_A<0>FSB_A<0>FSB_A_0_IBUFProtoComp10.IMUX.25SLICE_X0Y19.A6net23.283FSB_A_0_IBUFSLICE_X0Y19.COUTTopcya0.474Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.093Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.003Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTcinck0.298OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.4223.2895.711FSBCLK42.457.6CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Paths for end point AR_0 (SLICE_X0Y16.AX), 1 path -2.661FSB_A<0>AR_0-3.895CLKINAR<3>12.000FSB_A<0>CLKIN0.414FSB_A<0>AR_01N4.PADN4.ITiopi1.557FSB_A<0>FSB_A<0>FSB_A_0_IBUFProtoComp10.IMUX.25SLICE_X0Y16.AXnet23.388FSB_A_0_IBUFSLICE_X0Y16.CLKTdick0.085AR<3>AR_01.6423.3885.030FSBCLK32.667.4CLKINAR_04J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.864FSBCLK-6.3002.405-3.895Hold Paths: COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point AR_0 (SLICE_X0Y16.AX), 1 path -3.706FSB_A<0>AR_0-1.689CLKINAR<3>0.000FSB_A<0>CLKIN0.414FSB_A<0>AR_01N4.PADN4.ITiopi0.763FSB_A<0>FSB_A<0>FSB_A_0_IBUFProtoComp10.IMUX.25SLICE_X0Y16.AXnet21.627FSB_A_0_IBUFSLICE_X0Y16.CLKTckdi0.041AR<3>AR_00.8041.6272.431FSBCLK33.166.9CLKINAR_04J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y16.CLKnet170.806FSBCLK-3.1991.510-1.689Paths for end point OUTt (SLICE_X0Y21.CIN), 1 path -4.057FSB_A<0>OUTt-1.697CLKINOUTt_OBUF0.000FSB_A<0>CLKIN0.414FSB_A<0>OUTt4N4.PADN4.ITiopi0.763FSB_A<0>FSB_A<0>FSB_A_0_IBUFProtoComp10.IMUX.25SLICE_X0Y19.A6net21.556FSB_A_0_IBUFSLICE_X0Y19.COUTTopcya0.272Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>Mcompar_FSB_A[31]_AR[31]_equal_2_o_lut<0>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<3>SLICE_X0Y20.COUTTbyp0.032Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CINnet10.001Mcompar_FSB_A[31]_AR[31]_equal_2_o_cy<7>SLICE_X0Y21.CLKTckcin0.149OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.2161.5582.774FSBCLK43.856.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";10000109.641Paths for end point OUTt (SLICE_X0Y21.D4), 1 path -2.359CPU_nASOUTt-3.903CLKINOUTt_OBUF12.000CPU_nASCLKIN0.414CPU_nASOUTt2H3.PADH3.ITiopi1.557CPU_nASCPU_nASCPU_nAS_IBUFProtoComp10.IMUX.20SLICE_X0Y21.D4net13.250CPU_nAS_IBUFSLICE_X0Y21.CLKTas0.517OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_lutCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.0743.2505.324FSBCLK39.061.0CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Hold Paths: COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point OUTt (SLICE_X0Y21.D4), 1 path -3.896CPU_nASOUTt-1.697CLKINOUTt_OBUF0.000CPU_nASCLKIN0.414CPU_nASOUTt2H3.PADH3.ITiopi0.763CPU_nASCPU_nASCPU_nAS_IBUFProtoComp10.IMUX.20SLICE_X0Y21.D4net11.546CPU_nAS_IBUFSLICE_X0Y21.CLKTah0.304OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_lutCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0671.5462.613FSBCLK40.859.2CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";100001010.332Paths for end point OUTt (SLICE_X0Y21.D5), 1 path -1.668INtOUTt-3.903CLKINOUTt_OBUF12.000INtCLKIN0.414INtOUTt2C2.PADC2.ITiopi1.557INtINtINt_IBUFProtoComp10.IMUX.35SLICE_X0Y21.D5net13.941INt_IBUFSLICE_X0Y21.CLKTas0.517OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_lutCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt2.0743.9416.015FSBCLK34.565.5CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.368CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.578CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.197CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.856FSBCLK-6.3002.397-3.903Hold Paths: COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -Paths for end point OUTt (SLICE_X0Y21.D5), 1 path -4.292INtOUTt-1.697CLKINOUTt_OBUF0.000INtCLKIN0.414INtOUTt2C2.PADC2.ITiopi0.763INtINtINt_IBUFProtoComp10.IMUX.35SLICE_X0Y21.D5net11.942INt_IBUFSLICE_X0Y21.CLKTah0.304OUTt_OBUFCPU_nAS_FSB_A[31]_AND_3_o1_lutCPU_nAS_FSB_A[31]_AND_3_o1_cyOUTt1.0671.9423.009FSBCLK35.564.5CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.230CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.759CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.063CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.798FSBCLK-3.1991.502-1.697COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN";10000102.040Paths for end point OUTt (C3.PAD), 1 path -2.960OUTtOUTt-4.173CLKINOUTt_OBUF5.799OUTt_OBUFOUTt5.000CLKINOUTt0.414CLKINOUTt4J4.PADJ4.ITiopi1.037CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.643CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.190SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.842CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-9.039CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.505CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.209CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet171.440FSBCLK-7.6033.430-4.173OUTtOUTt1SLICE_X0Y21.CLKFSBCLKSLICE_X0Y21.DQTcko0.525OUTt_OBUFOUTtC3.Onet13.292OUTt_OBUFC3.PADTioop1.982OUTtOUTt_OBUFOUTt2.5073.2925.79943.256.8Fastest Paths: COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN"; -Paths for end point OUTt (C3.PAD), 1 path -0.500OUTtOUTt-1.606CLKINOUTt_OBUF2.520OUTt_OBUFOUTt5.000CLKINOUTt0.414CLKINOUTt4J4.PADJ4.ITiopi0.321CLKINCLKINCLKGEN_inst/instance_name/clkin1_bufProtoComp10.IMUX.36BUFIO2_X0Y23.Inet10.220CLKGEN_inst/instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.263CLKGEN_inst/instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.246CLKGEN_inst/instance_name/pll_base_inst/PLL_ADVCLKGEN_inst/instance_name/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.158CLKGEN_inst/instance_name/clkout0BUFGMUX_X2Y3.OTgi0o0.059CLKGEN_inst/instance_name/clkout1_bufCLKGEN_inst/instance_name/clkout1_bufSLICE_X0Y21.CLKnet170.497FSBCLK-2.7441.138-1.606OUTtOUTt1SLICE_X0Y21.CLKFSBCLKSLICE_X0Y21.DQTcko0.234OUTt_OBUFOUTtC3.Onet11.587OUTt_OBUFC3.PADTioop0.699OUTtOUTt_OBUFOUTt0.9331.5872.52037.063.00CLKINCPU_nAS9.641-3.896FSB_A<0>10.028-3.706FSB_A<1>9.876-3.242FSB_A<2>9.842-3.237FSB_A<3>10.480-3.772FSB_A<4>9.766-3.288FSB_A<5>9.265-3.204FSB_A<6>9.919-3.621FSB_A<7>9.757-3.464FSB_A<8>10.287-3.756FSB_A<9>10.009-3.618FSB_A<10>9.562-3.463FSB_A<11>9.522-3.200FSB_A<12>9.821-3.605FSB_A<13>10.011-3.709FSB_A<14>9.084-3.242FSB_A<15>10.096-3.834FSB_A<16>9.565-3.493FSB_A<17>9.261-3.474FSB_A<18>9.868-3.829FSB_A<19>9.995-3.722FSB_A<20>10.064-3.578FSB_A<21>10.275-3.718FSB_A<22>9.907-3.637FSB_A<23>9.737-3.472FSB_A<24>10.026-3.679FSB_A<25>9.883-3.244FSB_A<26>9.657-3.292FSB_A<27>10.334-3.698FSB_A<28>10.261-3.510FSB_A<29>9.864-3.448FSB_A<30>9.847-3.725FSB_A<31>10.247-3.707INt10.332-4.292CLKINCLKINCLKIN2.700COMP "FSB_A<31>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<31>10.247-3.707COMP "FSB_A<30>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<30>9.847-3.725COMP "FSB_A<29>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<29>9.864-3.448COMP "FSB_A<28>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<28>10.261-3.510COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<27>10.334-3.698COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<26>9.657-3.292COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<25>9.883-3.244COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<24>10.026-3.679COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<23>9.737-3.472COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<22>9.907-3.637COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<21>10.275-3.718COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<20>10.064-3.578COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<19>9.995-3.722COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<18>9.868-3.829COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<17>9.261-3.474COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<16>9.565-3.493COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<15>10.096-3.834COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<14>9.084-3.242COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<13>10.011-3.709COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<12>9.821-3.605COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<11>9.522-3.200COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<10>9.562-3.463COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<9>10.009-3.618COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<8>10.287-3.756COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<7>9.757-3.464COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<6>9.919-3.621COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<5>9.265-3.204COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<4>9.766-3.288COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<3>10.480-3.772COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<2>9.842-3.237COMP "FSB_A<1>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<1>9.876-3.242COMP "FSB_A<0>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<0>10.028-3.706COMP "CPU_nAS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";CPU_nAS9.641-3.896COMP "INt" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";INt10.332-4.292COMP "OUTt" OFFSET = OUT 5 ns AFTER COMP "CLKIN";0000102012210.000100.00010.4802.040Fri Oct 29 17:59:57 2021 TraceTrace Settings +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +4.005FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.296FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E13.PADE13.ITiopi0.763FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp0.IMUX.22RAMB8_X1Y31.ADDRBRDADDR7net131.189FSB_A_4_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6971.1891.886FSBCLK37.063.0CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.178cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet170.824FSBCLK-3.3511.528-1.823Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path +4.007FSB_A<3>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.296FSB_A<3>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E11.PADE11.ITiopi0.763FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp0.IMUX.21RAMB8_X1Y31.ADDRBRDADDR6net131.191FSB_A_3_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6971.1911.888FSBCLK36.963.1CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.178cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet170.824FSBCLK-3.3511.528-1.823Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path +4.008FSB_A<2>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.296FSB_A<2>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1B14.PADB14.ITiopi0.763FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp0.IMUX.20RAMB8_X1Y31.ADDRBRDADDR5net131.192FSB_A_2_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6971.1921.889FSBCLK36.963.1CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.178cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet170.824FSBCLK-3.3511.528-1.823Unconstrained OFFSET OUT AFTER analysis for clock "FSBCLK" 3600003605.139Paths for end point FSB_D<2> (C5.PAD), 1 path +5.139l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramFSB_D<2>0.296CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi1.037CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.643cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.190SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.842cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-9.178cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.209cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.466FSBCLK-7.7423.456-4.286l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramFSB_D<2>1RAMB8_X1Y31.CLKBRDCLKFSBCLKRAMB8_X1Y31.DOADO2Trcko_DOA2.100l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramC5.Onet14.047FSB_D_2_OBUFC5.PADTioop2.982FSB_D<2>FSB_D_2_OBUFFSB_D<2>5.0824.0479.12955.744.3Paths for end point FSB_D<4> (A6.PAD), 1 path +5.039l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramFSB_D<4>0.296CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi1.037CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.643cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.190SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.842cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-9.178cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.209cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.466FSBCLK-7.7423.456-4.286l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramFSB_D<4>1RAMB8_X1Y31.CLKBRDCLKFSBCLKRAMB8_X1Y31.DOADO4Trcko_DOA2.100l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramA6.Onet13.947FSB_D_4_OBUFA6.PADTioop2.982FSB_D<4>FSB_D_4_OBUFFSB_D<4>5.0823.9479.02956.343.7Paths for end point FSB_D<0> (A5.PAD), 1 path +4.996l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramFSB_D<0>0.296CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi1.037CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.643cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.190SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.842cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-9.178cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.209cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.466FSBCLK-7.7423.456-4.286l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramFSB_D<0>1RAMB8_X1Y31.CLKBRDCLKFSBCLKRAMB8_X1Y31.DOADO0Trcko_DOA2.100l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ramA5.Onet13.904FSB_D_0_OBUFA5.PADTioop2.982FSB_D<0>FSB_D_0_OBUFFSB_D<0>5.0823.9048.98656.643.4Fastest Paths: Unconstrained OFFSET OUT AFTER analysis for clock "FSBCLK" -Peak Memory Usage: 170 MB +Paths for end point RAMCLK0 (A14.PAD), 1 path +-0.475cg/RAMCLK0_instRAMCLK00.296CLKINcg/RAMCLK0_inst4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufOLOGIC_X11Y62.CLK0net171.386FSBCLK-6.4372.927-3.510cg/RAMCLK0_instRAMCLK01OLOGIC_X11Y62.CLK0FSBCLKOLOGIC_X11Y62.OQTockq1.090RAMCLK0_OBUFcg/RAMCLK0_instA14.Onet10.375RAMCLK0_OBUFA14.PADTioop1.866RAMCLK0RAMCLK0_OBUFRAMCLK02.9560.3753.33188.711.3Paths for end point RAMCLK1 (C4.PAD), 1 path +-0.436cg/RAMCLK1_instRAMCLK10.296CLKINcg/RAMCLK1_inst4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufOLOGIC_X1Y63.CLK0net171.425FSBCLK-6.4372.966-3.471cg/RAMCLK1_instRAMCLK11OLOGIC_X1Y63.CLK0FSBCLKOLOGIC_X1Y63.OQTockq1.090RAMCLK1_OBUFcg/RAMCLK1_instC4.Onet10.375RAMCLK1_OBUFC4.PADTioop1.866RAMCLK1RAMCLK1_OBUFRAMCLK12.9560.3753.33188.711.3Paths for end point FPUCLK (D11.PAD), 1 path +-0.424cg/FPUCLK_instFPUCLK0.296CLKINcg/FPUCLK_inst4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufOLOGIC_X11Y61.CLK0net171.386FSBCLK-6.4372.927-3.510cg/FPUCLK_instFPUCLK1OLOGIC_X11Y61.CLK0FSBCLKOLOGIC_X11Y61.OQTockq1.090FPUCLK_OBUFcg/FPUCLK_instD11.Onet10.426FPUCLK_OBUFD11.PADTioop1.866FPUCLKFPUCLK_OBUFFPUCLK2.9560.4263.38287.412.6Unconstrained OFFSET OUT AFTER analysis for clock "cg/pll/clkfb_bufg_out" 200001015.120Paths for end point CLKFB_OUT (A4.PAD), 2 paths +15.120cg/pll/clkfbout_oddrCLKFB_OUT0.257CLKINcg/pll/clkfbout_oddr4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178cg/pll/clkfboutBUFGMUX_X2Y3.OTgi0o0.063cg/pll/clkfbout_bufgcg/pll/clkfbout_bufgOLOGIC_X1Y62.CLK1net21.044cg/pll/clkfb_bufg_out-3.3511.748-1.603cg/pll/clkfbout_oddrCLKFB_OUT1OLOGIC_X1Y62.CLK1cg/pll/clkfb_bufg_outOLOGIC_X1Y62.OQTockq0.451CLKFB_OUT_OBUFcg/pll/clkfbout_oddrA4.Onet10.273CLKFB_OUT_OBUFA4.PADTioop0.742CLKFB_OUTCLKFB_OUT_OBUFCLKFB_OUT1.1930.2731.46681.418.60.189cg/pll/clkfbout_oddrCLKFB_OUT0.257CLKINcg/pll/clkfbout_oddr4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178cg/pll/clkfboutBUFGMUX_X2Y3.OTgi0o0.063cg/pll/clkfbout_bufgcg/pll/clkfbout_bufgOLOGIC_X1Y62.CLK0net21.119cg/pll/clkfb_bufg_out-3.3511.823-1.528cg/pll/clkfbout_oddrCLKFB_OUT1OLOGIC_X1Y62.CLK0cg/pll/clkfb_bufg_outOLOGIC_X1Y62.OQTockq0.445CLKFB_OUT_OBUFcg/pll/clkfbout_oddrA4.Onet10.273CLKFB_OUT_OBUFA4.PADTioop0.742CLKFB_OUTCLKFB_OUT_OBUFCLKFB_OUT1.1870.2731.46081.318.7Fastest Paths: Unconstrained OFFSET OUT AFTER analysis for clock "cg/pll/clkfb_bufg_out" + +Paths for end point CLKFB_OUT (A4.PAD), 2 paths +-0.348cg/pll/clkfbout_oddrCLKFB_OUT0.257CLKINcg/pll/clkfbout_oddr4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440cg/pll/clkfboutBUFGMUX_X2Y3.OTgi0o0.197cg/pll/clkfbout_bufgcg/pll/clkfbout_bufgOLOGIC_X1Y62.CLK0net21.474cg/pll/clkfb_bufg_out-6.4373.015-3.422cg/pll/clkfbout_oddrCLKFB_OUT1OLOGIC_X1Y62.CLK0cg/pll/clkfb_bufg_outOLOGIC_X1Y62.OQTockq1.090CLKFB_OUT_OBUFcg/pll/clkfbout_oddrA4.Onet10.375CLKFB_OUT_OBUFA4.PADTioop1.866CLKFB_OUTCLKFB_OUT_OBUFCLKFB_OUT2.9560.3753.33188.711.314.592cg/pll/clkfbout_oddrCLKFB_OUT0.257CLKINcg/pll/clkfbout_oddr4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.440cg/pll/clkfboutBUFGMUX_X2Y3.OTgi0o0.197cg/pll/clkfbout_bufgcg/pll/clkfbout_bufgOLOGIC_X1Y62.CLK1net21.414cg/pll/clkfb_bufg_out-6.4372.955-3.482cg/pll/clkfbout_oddrCLKFB_OUT1OLOGIC_X1Y62.CLK1cg/pll/clkfb_bufg_outOLOGIC_X1Y62.OQTockq1.090CLKFB_OUT_OBUFcg/pll/clkfbout_oddrA4.Onet10.375CLKFB_OUT_OBUFA4.PADTioop1.866CLKFB_OUTCLKFB_OUT_OBUFCLKFB_OUT2.9560.3753.33188.711.3Unconstrained path analysis 188000058012.945Paths for end point CPU_nSTERM (D12.PAD), 131 paths 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.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0406.35710.39738.961.110.386FSB_A<15>CPU_nSTERM10.386FSB_A<15>CPU_nSTERM4G14.PADG14.ITiopi1.557FSB_A<15>FSB_A<15>FSB_A_15_IBUFProtoComp0.IMUX.10SLICE_X22Y50.C1net13.345FSB_A_15_IBUFSLICE_X22Y50.COUTTopcyc0.325l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1316.25510.38639.860.210.342FSB_A<18>CPU_nSTERM10.342FSB_A<18>CPU_nSTERM4H16.PADH16.ITiopi1.557FSB_A<18>FSB_A<18>FSB_A_18_IBUFProtoComp0.IMUX.16SLICE_X22Y50.D2net13.336FSB_A_18_IBUFSLICE_X22Y50.COUTTopcyd0.290l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0966.24610.34239.660.410.341FSB_A<7>CPU_nSTERM10.341FSB_A<7>CPU_nSTERM4B16.PADB16.ITiopi1.557FSB_A<7>FSB_A<7>FSB_A_7_IBUFProtoComp0.IMUX.25SLICE_X22Y50.A1net13.153FSB_A_7_IBUFSLICE_X22Y50.COUTTopcya0.472l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.2786.06310.34141.458.610.331FSB_A<27>CPU_nSTERM10.331FSB_A<27>CPU_nSTERM3H14.PADH14.ITiopi1.557FSB_A<27>FSB_A<27>FSB_A_27_IBUFProtoComp0.IMUX.19SLICE_X22Y51.C1net13.384FSB_A_27_IBUFSLICE_X22Y51.DMUXTopcd0.501CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0406.29110.33139.160.910.285FSB_A<25>CPU_nSTERM10.285FSB_A<25>CPU_nSTERM3H11.PADH11.ITiopi1.557FSB_A<25>FSB_A<25>FSB_A_25_IBUFProtoComp0.IMUX.15SLICE_X22Y51.C2net13.338FSB_A_25_IBUFSLICE_X22Y51.DMUXTopcd0.501CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0406.24510.28539.360.710.186FSB_A<17>CPU_nSTERM10.186FSB_A<17>CPU_nSTERM4H15.PADH15.ITiopi1.557FSB_A<17>FSB_A<17>FSB_A_17_IBUFProtoComp0.IMUX.14SLICE_X22Y50.D6net13.180FSB_A_17_IBUFSLICE_X22Y50.COUTTopcyd0.290l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0966.09010.18640.259.810.091FSB_A<8>CPU_nSTERM10.091FSB_A<8>CPU_nSTERM4F12.PADF12.ITiopi1.557FSB_A<8>FSB_A<8>FSB_A_8_IBUFProtoComp0.IMUX.26SLICE_X22Y50.A3net12.903FSB_A_8_IBUFSLICE_X22Y50.COUTTopcya0.472l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.2785.81310.09142.457.610.036FSB_A<16>CPU_nSTERM10.036FSB_A<16>CPU_nSTERM4G16.PADG16.ITiopi1.557FSB_A<16>FSB_A<16>FSB_A_16_IBUFProtoComp0.IMUX.12SLICE_X22Y50.D5net13.030FSB_A_16_IBUFSLICE_X22Y50.COUTTopcyd0.290l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0965.94010.03640.859.29.996FSB_A<9>CPU_nSTERM9.996FSB_A<9>CPU_nSTERM4G11.PADG11.ITiopi1.557FSB_A<9>FSB_A<9>FSB_A_9_IBUFProtoComp0.IMUX.27SLICE_X22Y50.A5net12.808FSB_A_9_IBUFSLICE_X22Y50.COUTTopcya0.472l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.2785.7189.99642.857.29.938FSB_A<11>CPU_nSTERM9.938FSB_A<11>CPU_nSTERM4D16.PADD16.ITiopi1.557FSB_A<11>FSB_A<11>FSB_A_11_IBUFProtoComp0.IMUX.2SLICE_X22Y50.B3net12.774FSB_A_11_IBUFSLICE_X22Y50.COUTTopcyb0.448l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.2545.6849.93842.857.29.929FSB_A<10>CPU_nSTERM9.929FSB_A<10>CPU_nSTERM4D14.PADD14.ITiopi1.557FSB_A<10>FSB_A<10>FSB_A_10_IBUFProtoComp0.IMUX.1SLICE_X22Y50.B5net12.765FSB_A_10_IBUFSLICE_X22Y50.COUTTopcyb0.448l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.2545.6759.92942.857.29.879FSB_A<20>CPU_nSTERM9.879FSB_A<20>CPU_nSTERM3C16.PADC16.ITiopi1.557FSB_A<20>FSB_A<20>FSB_A_20_IBUFProtoComp0.IMUX.4SLICE_X22Y51.A2net12.785FSB_A_20_IBUFSLICE_X22Y51.DMUXTopad0.648CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1875.6929.87942.457.69.750FSB_A<14>CPU_nSTERM9.750FSB_A<14>CPU_nSTERM4C15.PADC15.ITiopi1.557FSB_A<14>FSB_A<14>FSB_A_14_IBUFProtoComp0.IMUX.8SLICE_X22Y50.C3net12.709FSB_A_14_IBUFSLICE_X22Y50.COUTTopcyc0.325l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1315.6199.75042.457.69.717FSB_A<23>CPU_nSTERM9.717FSB_A<23>CPU_nSTERM3F15.PADF15.ITiopi1.557FSB_A<23>FSB_A<23>FSB_A_23_IBUFProtoComp0.IMUX.11SLICE_X22Y51.B3net12.647FSB_A_23_IBUFSLICE_X22Y51.DMUXTopbd0.624CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1635.5549.71742.857.29.634FSB_A<12>CPU_nSTERM9.634FSB_A<12>CPU_nSTERM4F13.PADF13.ITiopi1.557FSB_A<12>FSB_A<12>FSB_A_12_IBUFProtoComp0.IMUX.3SLICE_X22Y50.B6net12.470FSB_A_12_IBUFSLICE_X22Y50.COUTTopcyb0.448l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.2545.3809.63444.255.89.596FSB_A<13>CPU_nSTERM9.596FSB_A<13>CPU_nSTERM4F14.PADF14.ITiopi1.557FSB_A<13>FSB_A<13>FSB_A_13_IBUFProtoComp0.IMUX.6SLICE_X22Y50.C6net12.555FSB_A_13_IBUFSLICE_X22Y50.COUTTopcyc0.325l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X22Y51.DMUXTcind0.267CPU_nSTERM_OBUFCPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1315.4659.59643.057.09.567FSB_A<21>CPU_nSTERM9.567FSB_A<21>CPU_nSTERM3E15.PADE15.ITiopi1.557FSB_A<21>FSB_A<21>FSB_A_21_IBUFProtoComp0.IMUX.7SLICE_X22Y51.A5net12.473FSB_A_21_IBUFSLICE_X22Y51.DMUXTopad0.648CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1875.3809.56743.856.29.409FSB_A<22>CPU_nSTERM9.409FSB_A<22>CPU_nSTERM3E16.PADE16.ITiopi1.557FSB_A<22>FSB_A<22>FSB_A_22_IBUFProtoComp0.IMUX.9SLICE_X22Y51.B5net12.339FSB_A_22_IBUFSLICE_X22Y51.DMUXTopbd0.624CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1635.2469.40944.255.89.160FSB_A<19>CPU_nSTERM9.160FSB_A<19>CPU_nSTERM3F16.PADF16.ITiopi1.557FSB_A<19>FSB_A<19>FSB_A_19_IBUFProtoComp0.IMUX.18SLICE_X22Y51.A6net12.066FSB_A_19_IBUFSLICE_X22Y51.DMUXTopad0.648CPU_nSTERM_OBUFl2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>CPU_nSTERM1_cyD12.Onet12.907CPU_nSTERM_OBUFD12.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.1874.9739.16045.754.3Paths for end point cg/pll/clkfbout_oddr (OLOGIC_X1Y62.CLK0), 1 path +-1.528CLKINcg/pll/clkfbout_oddr-1.528CLKINcg/pll/clkfbout_oddr4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X2Y3.I0net10.178cg/pll/clkfboutBUFGMUX_X2Y3.OTgi0o0.063cg/pll/clkfbout_bufgcg/pll/clkfbout_bufgOLOGIC_X1Y62.CLK0net21.119cg/pll/clkfb_bufg_out-3.3511.823-1.528Paths for end point cg/RAMCLK1_inst (OLOGIC_X1Y63.CLK0), 1 path +-1.592CLKINcg/RAMCLK1_inst-1.592CLKINcg/RAMCLK1_inst4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.230cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.296cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-3.911cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.178cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufOLOGIC_X1Y63.CLK0net171.055FSBCLK-3.3511.759-1.592Hold Paths: Unconstrained path analysis + +Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (SLICE_X16Y51.CLK), 1 path +-4.017CLKINl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP0.000-4.017CLKINl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufSLICE_X16Y51.CLKnet170.879FSBCLK-6.4372.420-4.017Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (SLICE_X16Y51.CLK), 1 path +-4.017CLKINl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP0.000-4.017CLKINl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufSLICE_X16Y51.CLKnet170.879FSBCLK-6.4372.420-4.017Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP (SLICE_X16Y51.CLK), 1 path +-4.017CLKINl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP0.000-4.017CLKINl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.368cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN2net10.733cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-7.715cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.440cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufSLICE_X16Y51.CLKnet170.879FSBCLK-6.4372.420-4.0170CLKINFSB_A<2>8.756-3.416FSB_A<3>8.745-3.415FSB_A<4>8.905-3.413FSB_A<5>8.878-3.447FSB_A<6>8.910-3.417CLKINCLKINCLKIN3.689FSB_A<2>CPU_nSTERM12.820FSB_A<3>CPU_nSTERM12.708FSB_A<4>CPU_nSTERM12.945FSB_A<5>CPU_nSTERM12.435FSB_A<6>CPU_nSTERM12.356FSB_A<7>CPU_nSTERM10.341FSB_A<8>CPU_nSTERM10.091FSB_A<9>CPU_nSTERM9.996FSB_A<10>CPU_nSTERM9.929FSB_A<11>CPU_nSTERM9.938FSB_A<12>CPU_nSTERM9.634FSB_A<13>CPU_nSTERM9.596FSB_A<14>CPU_nSTERM9.750FSB_A<15>CPU_nSTERM10.386FSB_A<16>CPU_nSTERM10.036FSB_A<17>CPU_nSTERM10.186FSB_A<18>CPU_nSTERM10.342FSB_A<19>CPU_nSTERM9.160FSB_A<20>CPU_nSTERM9.879FSB_A<21>CPU_nSTERM9.567FSB_A<22>CPU_nSTERM9.409FSB_A<23>CPU_nSTERM9.717FSB_A<24>CPU_nSTERM10.629FSB_A<25>CPU_nSTERM10.285FSB_A<26>CPU_nSTERM10.397FSB_A<27>CPU_nSTERM10.331cg_pll_clkout0cg/pll/clkout1_bufl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SPcg/CPUCLKrcg\/RAMCLK0_inst.CK0cg\/RAMCLK0_inst.CK1cg\/RAMCLK1_inst.CK0cg\/RAMCLK1_inst.CK1cg\/FPUCLK_inst.CK0cg\/FPUCLK_inst.CK1cg\/CPUCLK_inst.CK0cg\/CPUCLK_inst.CK1l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKAWRCLKl2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKBRDCLKcg_pll_clkfboutcg/pll/clkfbout_bufgcg\/pll\/clkfbout_oddr.CK0cg\/pll\/clkfbout_oddr.CK1CPU_nSTERMCPU_nSTERMFSB_ACPU_nSTERMl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SPl2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SPl2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKBRDCLKCLKINcg\/pll\/pll_base_inst\/PLL_ADV.CLKIN1SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0.DIVCLK0000259017810.000100.00012.9457.8798.91015.120Sun Oct 31 15:38:38 2021 TraceTrace Settings + +Peak Memory Usage: 214 MB diff --git a/fpga/WarpLC.unroutes b/fpga/WarpLC.unroutes index c7dcea2..588fd33 100644 --- a/fpga/WarpLC.unroutes +++ b/fpga/WarpLC.unroutes @@ -1,7 +1,7 @@ -Release 14.7 - par P.20131013 (nt) +Release 14.7 - par P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -Fri Oct 29 17:59:53 2021 +Sun Oct 31 15:38:33 2021 All signals are completely routed. diff --git a/fpga/WarpLC.v b/fpga/WarpLC.v index d3b21ee..421e6ac 100644 --- a/fpga/WarpLC.v +++ b/fpga/WarpLC.v @@ -29,13 +29,17 @@ module WarpLC( (* IOSTANDARD = "LVCMOS33" *) (* IOBDELAY = "NONE" *) - input INt, + input [1:0] FSB_SIZ, + + (* IOSTANDARD = "LVCMOS33" *) + (* DRIVE = "8" *) + (* SLEW = "SLOW" *) + output [31:0] FSB_D, - (* IOB = "FALSE" *) (* IOSTANDARD = "LVCMOS33" *) (* DRIVE = "24" *) (* SLEW = "FAST" *) - output reg OUTt, + output CPU_nSTERM, (* IOSTANDARD = "LVCMOS33" *) (* DRIVE = "24" *) @@ -56,11 +60,7 @@ module WarpLC( (* DRIVE = "24" *) (* SLEW = "FAST" *) output RAMCLK1, - - (* IOSTANDARD = "LVCMOS33" *) - (* IOBDELAY = "NONE" *) - input CPUCLKi, - + (* IOSTANDARD = "LVCMOS33" *) (* IOBDELAY = "NONE" *) input CLKIN, @@ -76,7 +76,7 @@ module WarpLC( wire FSBCLK; wire CPUCLKr; - CLKGEN CLKGEN_inst( + ClkGen cg ( .CLKIN(CLKIN), .CLKFB_IN(CLKFB_IN), .CLKFB_OUT(CLKFB_OUT), @@ -86,11 +86,28 @@ module WarpLC( .FPUCLK(FPUCLK), .RAMCLK0(RAMCLK0), .RAMCLK1(RAMCLK1)); + + wire [3:0] FSB_B; + SizeDecode sd ( + .A(FSB_A[1:0]), + .SIZ(FSB_SIZ[1:0]), + .B(FSB_B[3:0])); - reg [31:0] AR; - always @(posedge FSBCLK) begin - OUTt <= ~CPU_nAS && INt && CPUCLKi && FSB_A[31:0]==AR[31:0]; - AR[31:0] <= FSB_A[31:0]; - end + wire L2PrefetchMatch; + L2Prefetch l2pre ( + .CLK(FSBCLK), + .CPUCLKr(CPUCLKr), + .RDA(FSB_A[28:2]), + .RDD(FSB_D[31:0]), + .Match(L2PrefetchMatch), + + .WRA(27'b0), + .WRD(32'b0), + .WR(1'b0), + .WRM(4'b0), + .CLR(1'b0)); + + assign CPU_nSTERM = ~(L2PrefetchMatch); + endmodule diff --git a/fpga/WarpLC.xise b/fpga/WarpLC.xise index 254c57d..707d724 100644 --- a/fpga/WarpLC.xise +++ b/fpga/WarpLC.xise @@ -17,28 +17,46 @@ - - - - - + - - - - - - - - - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -67,7 +85,7 @@ - + @@ -108,8 +126,8 @@ - - + + @@ -121,7 +139,7 @@ - + @@ -147,10 +165,10 @@ - + - - + + @@ -201,7 +219,7 @@ - + @@ -222,7 +240,7 @@ - + @@ -234,12 +252,12 @@ - + - - - - + + + + @@ -255,7 +273,7 @@ - + @@ -270,7 +288,7 @@ - + diff --git a/fpga/WarpLC.xst b/fpga/WarpLC.xst index 90f1a5e..9b582c4 100644 --- a/fpga/WarpLC.xst +++ b/fpga/WarpLC.xst @@ -7,13 +7,13 @@ run -p xc6slx9-2-ftg256 -top WarpLC -opt_mode Speed --opt_level 1 +-opt_level 2 -power NO -iuc NO -keep_hierarchy No -netlist_hierarchy As_Optimized -rtlview Yes --glob_opt AllClockNets +-glob_opt Inpad_To_Outpad -read_cores YES -sd {"ipcore_dir" } -write_timing_constraints NO diff --git a/fpga/WarpLC_2021-10-31-15-23-24.twx b/fpga/WarpLC_2021-10-31-15-23-24.twx new file mode 100644 index 0000000..f7d9371 --- /dev/null +++ b/fpga/WarpLC_2021-10-31-15-23-24.twx @@ -0,0 +1,342 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 +-n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf +PLL.ucf + +WarpLC.ncdWarpLC.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;220000108.586Paths for end point CPU_nSTERM (E11.PAD), 22 paths +6.414l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPCPU_nSTERM8.5860.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPCPU_nSTERM4SLICE_X16Y51.CLKFSBCLKSLICE_X16Y51.AMUXTshcko1.081l2pre/n0023<14>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPSLICE_X20Y50.D3net11.014l2pre/n0023<11>SLICE_X20Y50.COUTTopcyd0.312l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CMUXTcinc0.302l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.640l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.254CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet12.998CPU_nSTERM_OBUFE11.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.9314.6558.58645.854.26.422l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPCPU_nSTERM8.5780.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPCPU_nSTERM3SLICE_X16Y51.CLKFSBCLKSLICE_X16Y51.BTshcko1.106l2pre/n0023<14>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPSLICE_X20Y51.A4net10.968l2pre/n0023<14>SLICE_X20Y51.CMUXTopac0.630l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.640l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.254CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet12.998CPU_nSTERM_OBUFE11.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.9724.6068.57846.353.76.445l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPCPU_nSTERM8.5550.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPCPU_nSTERM4SLICE_X20Y55.CLKFSBCLKSLICE_X20Y55.AMUXTshcko1.081l2pre/n0023<21>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPSLICE_X20Y50.A3net10.821l2pre/n0023<2>SLICE_X20Y50.COUTTopcya0.474l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CMUXTcinc0.302l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.640l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.254CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet12.998CPU_nSTERM_OBUFE11.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0934.4628.55547.852.2Fastest Paths: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns; +Paths for end point CPU_nSTERM (E11.PAD), 22 paths +3.066l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPCPU_nSTERM2SLICE_X20Y55.CLKFSBCLKSLICE_X20Y55.BTshcko0.449l2pre/n0023<21>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPSLICE_X20Y56.A5net10.194l2pre/n0023<21>SLICE_X20Y56.ATilo0.156CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet11.568CPU_nSTERM_OBUFE11.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.3041.7623.06642.557.53.557l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPCPU_nSTERM3SLICE_X20Y52.CLKFSBCLKSLICE_X20Y52.BTshcko0.449l2pre/n0023<18>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPSLICE_X20Y51.C5net10.150l2pre/n0023<18>SLICE_X20Y51.CMUXTopcc0.250l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.285l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.156CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet11.568CPU_nSTERM_OBUFE11.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.5542.0033.55743.756.33.629l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPCPU_nSTERM3SLICE_X20Y52.CLKFSBCLKSLICE_X20Y52.ATshcko0.441l2pre/n0023<18>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPSLICE_X20Y51.C4net10.230l2pre/n0023<19>SLICE_X20Y51.CMUXTopcc0.250l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.285l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.156CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet11.568CPU_nSTERM_OBUFE11.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.5462.0833.62942.657.40CLKIN0000220398.586Sun Oct 31 15:23:24 2021 TraceTrace Settings + +Peak Memory Usage: 214 MB + diff --git a/fpga/WarpLC_envsettings.html b/fpga/WarpLC_envsettings.html index 82886c9..1b93458 100644 --- a/fpga/WarpLC_envsettings.html +++ b/fpga/WarpLC_envsettings.html @@ -22,10 +22,10 @@ Path -C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files\Microchip\xc8\v2.31\bin;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files\PuTTY\;
C:\Program Files\WinMerge;
C:\Program Files\dotnet\;
C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;
C:\Users\zanek\AppData\Local\GitHubDesktop\bin;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\Users\zanek\.dotnet\tools;
C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin -C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files\Microchip\xc8\v2.31\bin;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files\PuTTY\;
C:\Program Files\WinMerge;
C:\Program Files\dotnet\;
C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;
C:\Users\zanek\AppData\Local\GitHubDesktop\bin;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\Users\zanek\.dotnet\tools;
C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin -C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files\Microchip\xc8\v2.31\bin;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files\PuTTY\;
C:\Program Files\WinMerge;
C:\Program Files\dotnet\;
C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;
C:\Users\zanek\AppData\Local\GitHubDesktop\bin;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\Users\zanek\.dotnet\tools;
C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin -C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files\Microchip\xc8\v2.31\bin;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files\PuTTY\;
C:\Program Files\WinMerge;
C:\Program Files\dotnet\;
C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;
C:\Users\zanek\AppData\Local\GitHubDesktop\bin;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\Users\zanek\.dotnet\tools;
C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin +C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
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C:\Users\Dog\AppData\Local\GitHubDesktop\bin XILINX @@ -106,7 +106,7 @@ -opt_level Optimization Effort -1 +2 1 @@ -142,7 +142,7 @@ -glob_opt Global Optimization Goal -AllClockNets +Inpad_To_Outpad AllClockNets @@ -410,18 +410,42 @@ high +-xe +Placer Extra Effort Map +CONTINUE +  + + -xt Extra Cost Tables 0 0 +-global_opt +Global Optimization map +TRUE +FALSE + + -ir Use RLOC Constraints OFF OFF +-logic_opt +Combinatorial Logic Optimization +TRUE +FALSE + + +-mt +Enable Multi-Threading +2 +0 + + -t Starting Placer Cost Table (1-100) Map 1 @@ -434,6 +458,12 @@ 4 +-equivalent_register_removal +Equivalent Register Removal +TRUE +TRUE + + -intstyle   ise @@ -482,6 +512,12 @@ Default Value +-xe +  +c +None + + -intstyle   ise @@ -490,7 +526,7 @@ -mt Enable Multi-Threading -off +4 off @@ -520,31 +556,31 @@ CPU Architecture/Speed -Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz -Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz -Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz -Intel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz +Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz +Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz +Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz +Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3316 MHz Host -ZanePC -ZanePC -ZanePC -ZanePC +Dog-PC +Dog-PC +Dog-PC +Dog-PC OS Name -Microsoft , 64-bit -Microsoft , 64-bit -Microsoft , 64-bit -Microsoft , 64-bit +Microsoft Windows 7 , 64-bit +Microsoft Windows 7 , 64-bit +Microsoft Windows 7 , 64-bit +Microsoft Windows 7 , 64-bit OS Release -major release (build 9200) -major release (build 9200) -major release (build 9200) -major release (build 9200) +Service Pack 1 (build 7601) +Service Pack 1 (build 7601) +Service Pack 1 (build 7601) +Service Pack 1 (build 7601) \ No newline at end of file diff --git a/fpga/WarpLC_guide.ncd b/fpga/WarpLC_guide.ncd index 1b83494..80ae536 100644 --- a/fpga/WarpLC_guide.ncd +++ b/fpga/WarpLC_guide.ncd @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 -###6700:XlxV32DM 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df8eNrtW8uu2zYQ/ZnuurHIISnayK8Y4EtANu0iy4v8e/mYI9MyaThtARtoEST0JSWdOTMj6fhc5nw6X376xa7n03nJf09fvwm9nIV0lz+Etud1ufwmYjx7e/ldqHguh/9oh8uvb4tfz0Ktl29lJi9fruWffIAvBwg+QKoyLy4/M5ArIKL8+fpDGHGmaC8NMTWgFC/f88EFCIB+Ce2sLjzbwpO6nC3O0mwcp8ynS1VO+zNHdm70KuqInrEjevXwQi/jNnpuuaPX4uED7uiFIz3X6Cn3jF6Y0CP7Gr0wq14Y0gugF0Av3NMLoBfu6Vl7pOe5eusTet7OqhdfoldRh/ROw+a0aE6L5rT3zWnRnPZQPXGkFxo9uTyrnpjRU69VT8yacx1WT6B6AtUT99UTqJ440ItHerHRW8IzenHWnOtr9OKsen5IL4JeBL14Ty+CXjw0pzvSS9yc9llzuln1wmvN6WbV24bN6dCcDs3p7pvToTndoXrySG/j5hTPqidn9Oi16skZPTOsnkT1JKon76snUT15oJcO9NKJm9M/o5dmzWleo5dmzemG9BLoJdBL9/QS6KVDc/ojvYWb89mLwftZ9fxrzeln1UvD5vRoTo/m9PfN6dGc/lA9OtIT3JzyWfVoRk++Vj2a0dPD6hGqR6ge3VePUD060NuO9CQ359PX+jZrzhdVyzZrzrFq2UBvA73tnt4GetuBnjrSI64ePaOnZtUTr9FTs+qpIT0Fegr01D09BXrqnp4/Hekprl58Qi+eZtV77bVeUYfVG77W6+GFXsZt9Pzpjl6Lhw+4q54+0tNcPfWsenpWveW16ulZ9WhYPY3qaVRP31dPo3r6jp5U27lc/Vy+SDSCyjNBxfXbxOVPU14sl+9GtUG3wbRhbYNtg6uDbYysaUNbs7zm2xDaENuQ2rDVwZ3qefWZcvnu25pva+HUhqUNog0twNAiCy2k0E7YWtRbW9ta1Fs7ZGuRbS2yrUW2UD3GS1liS10ZQmplaOogl3H/Bqdfyg4iilzvFrVIK4+WR8ej5zHwmFp/SKpfuU59ZBtHBtW/snDx5lfqhgATB0i/GGA8BCrtIYPxxHH692ZQmmMG48KR2c/KYPkQ+zhFi7NJuH+Ywb/Te+WO2/qAJCcu/XuJ+ycJc8eEEccX3pMwuR4Tpjgg9wEJ+7FQuY79+lYed/kx8q08XeqYb942Gh4Trwv+2fG4lvGa//78ITW/ScvZ+fa8XB0VkJXVb5nOX73rRfN4teX9JE4JJ5nzlvI5p3Iptd1m842UD7b1Ura7lOFLmbwa6pu80PONTc5Jo9M+lIgSY/OHhGMEZlxRSHXkiZUn1jpx3VRFYROnnFgCDmud9bdM5vwCOwE7ATsBOwE7ATMBq1xV16s68E3FUqsn5PEaREndYrpVzav6cvVbPTf12bCIyCIii4gsIrKIyHI2NCKznA2NCHMMm64xrF0MhmPIFQmnuqq7VcWrWYP4VKtpumpqrmaO3/q6GrtVDrZwt/XcaLsrcxlLU4WlrKby6FWN+xYb4zYmHl0Zr/l1Xw8X6La1lnSrAaSlT2BAAgMSGJDAgAQGJDBwAi0SGDiBFgkMGaW2dDr1KB4oHigeKB4oHiieUVageEZZgeIzSmvPrUdxQHFAcUBxQHFAcYxigOIYxQDFZZSax1V1JVNcslxu62oMEjfOUrNsVX1o0G223ulG1um9JLE9S2xDCECIfEMstSlMezy4bpXv/9IUpuZgXbtVw6u5VU27su5WNa/mZjT1RlypW1W8mpkZVdu8fX2/Gk6scXW2PSiulh+kPNtstmuQ3LRtttys+uu6Ibl7iSIqE1GQiLzHquN1eNDxDuZ4+s/reKUmOj6YN+t4M9PxQX2WCl0mOj7IN2dwm+n4sHxUBpWe6PiwvknHrxMdH/Rn6Hgx0fGB3pMwdZro+CA+S8fnx13T6dDtrOfzAXXMrdh+Xnmd9XwmeNPxKuLdu4x1/MJv122k4/PsTcfrcJsd6viFX8XbSMdnNqzRd9UOQV+uVz9kRjyz4hjB4gPCPpOrE3kc6vh1pOMrdgJ2AnYCdgJ2AnYCZgLWo47PZzTZso50fFnVvPqo42tEFhFZRGQRkUVEFhFZzoZGZJazoRHho44vMRiO4VHHl1XFqwMdv3D821DHL8x9G+n4cmUu40DHZ+5Nty9tzEe3n8VQx2duAx1fExiQwIAEBiQwIIEBCQycQIsEBk6gRQIfdXxF8UDxQPFA8UDxQPGMsgLFM8oKlEcdX1EcUBxQHFAcUBxQHKMYoDhGMUAZ6PiFy70Ndbzpdfx6m+11PL7Il4AHOj5PG+7pgY4vq3z/D3R8WTW8+qjjy6rm1UcdX1YVr950/NbreCh2cep0fMlEm116Hb9iVnQ6viR3L1FEZSIKEpF31vHxUcfzL9rV9r+ONzMd/2Y/Xvmpjv8sP74yHOr4N/vxapnq+M/y4+vv6EY6Pr7Jj1dhpuM/w4+vGR/q+Df58UrMdPyH+fGK9Xt+urRR8sh6XrF+zx3QRuJR9H48JLmSQx2fp5vEWEY6Xi29jo+32ZGOL5cyfKmBjod8z3T4g8QHCHoF+Z4p8Qdi2U6YYGGvxFDH5xNHOh7yvWInYCdgJ2AnYCdgJmANdDx7ufmEkY5nq7ysDnQ85HuNyCIii4gsIrKIyHI2NCKznA2NCAc6nh3aEsNAx/OvNsrqo44v1dRczUcdX1Y52JGOZ/+5XHmg4w3rd8njyiONdbwY6njI95rAgAQGJDAggQEJDJxAiwQGTqBFAgc6HvK9onigeKB4oHigeEZZgeIZZQXKQMdDvlcUBxQHFAcUBxTHKAYojlEMUB51fCmZ4pI96vgMfdPxRtxmOx1v8Lu9EvBIxxtOph/qeMNJ8EMdbzh4P9TxhpvRD3W8YWa+0/FCdjq+rDRtTp2OV3Dphep0fGnaNqt7HS/OZi9RRGUiChKRd9bx8nFfDfvx+vSf1/E08+PTu/14OdPx6bP8eJrtq0lv9uPl1I9Pn+XH08yPT+/y42mi49Nn+PE021eT3uTH08yPTx/mxxP8eNbvhH017McT/HjW78T7aqj347WBtTbeV0PYVzP04+WdHy9vsyMdT9hXM/TjaffjId9p31cDP552Px6ynXhfDWFfDbEfTxM/nkY6nnY/HvKd9n018ONp9+Mh3wn7amjsxxP8eBrpeIIfTyMdT7sfD/lO+74a+PG0+/GQ7cT7agj7aoj9eBr78QQ/nkY6nuDH00jHE/bVDP14wr6aoR9P8ONppOOJ/XjifTXEfjyN99XQ0I+n3Y+HfKd9Xw38eNr9eMh24n01hH01xH48jf142v14yHfa99XAj6fdj4dsJ95XQ9hXQ+zH09iPp92Ph3ynfV8N/Hja/XjIduJ9NYR9NcR+PI39eMK+mrEfL3s/Xt1mez9eY3rsxxP8eDnS8QQ/Xo50PMGPlyMdT/Dj5UjHE/x42et40/vxEtp87ffV7H687f14wqzrdDzBj5fYRbP78YQPNz/eLI86nv/zjV7+3x/vZ/vj36zj63+oGO+P/7B9NTM/Pr5Zxys73R//WTpehpkf/yYdLzVk6V/t/62r###5404:XlxV32DM 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\ No newline at end of file diff --git a/fpga/WarpLC_map.map b/fpga/WarpLC_map.map index 0600e9b..bd3f726 100644 --- a/fpga/WarpLC_map.map +++ b/fpga/WarpLC_map.map @@ -1,32 +1,18 @@ -Release 14.7 Map P.20131013 (nt) +Release 14.7 Map P.20131013 (nt64) Xilinx Map Application Log File for Design 'WarpLC' Design Information ------------------ -Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol -high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off --pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high +-xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 +-ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf Target Device : xc6slx9 Target Package : ftg256 Target Speed : -2 Mapper Version : spartan6 -- $Revision: 1.55 $ -Mapped Date : Fri Oct 29 17:59:44 2021 +Mapped Date : Sun Oct 31 15:38:01 2021 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set. -INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to -'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license -.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'. -INFO:Security:54 - 'xc6slx9' is a WebPack part. -INFO:Security:66 - Your license for 'ISE' is for evaluation use only. -WARNING:Security:43 - No license file was found in the standard Xilinx license -directory. -WARNING:Security:44 - Since no license file was found, - please run the Xilinx License Configuration Manager - (xlcm or "Manage Xilinx Licenses") - to assist in obtaining a license. -WARNING:Security:40 - Your license for 'ISE' expires in 4 days. ----------------------------------------------------------------------- +Running global optimization... Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... @@ -34,94 +20,103 @@ Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... -Total REAL time at the beginning of Placer: 2 secs -Total CPU time at the beginning of Placer: 2 secs +Total REAL time at the beginning of Placer: 10 secs +Total CPU time at the beginning of Placer: 10 secs Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:18bd) REAL time: 2 secs +Phase 1.1 Initial Placement Analysis (Checksum:283d) REAL time: 10 secs Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:18bd) REAL time: 2 secs +Phase 2.7 Design Feasibility Check (Checksum:283d) REAL time: 11 secs Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:18bd) REAL time: 2 secs +Phase 3.31 Local Placement Optimization (Checksum:283d) REAL time: 11 secs Phase 4.2 Initial Placement for Architecture Specific Features ... +.... Phase 4.2 Initial Placement for Architecture Specific Features -(Checksum:4099679c) REAL time: 3 secs +(Checksum:8c2c3f8) REAL time: 15 secs Phase 5.36 Local Placement Optimization -Phase 5.36 Local Placement Optimization (Checksum:4099679c) REAL time: 3 secs +Phase 5.36 Local Placement Optimization (Checksum:8c2c3f8) REAL time: 15 secs Phase 6.30 Global Clock Region Assignment -Phase 6.30 Global Clock Region Assignment (Checksum:4099679c) REAL time: 3 secs +Phase 6.30 Global Clock Region Assignment (Checksum:8c2c3f8) REAL time: 15 secs Phase 7.3 Local Placement Optimization ... -Phase 7.3 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs +.... +Phase 7.3 Local Placement Optimization (Checksum:f4c788ab) REAL time: 21 secs Phase 8.5 Local Placement Optimization -Phase 8.5 Local Placement Optimization (Checksum:432b55c8) REAL time: 3 secs +Phase 8.5 Local Placement Optimization (Checksum:f4c788ab) REAL time: 21 secs Phase 9.8 Global Placement -.. -................ ................ .. -Phase 9.8 Global Placement (Checksum:8bf5099b) REAL time: 3 secs +Phase 9.8 Global Placement (Checksum:67f9eb6e) REAL time: 21 secs Phase 10.5 Local Placement Optimization -Phase 10.5 Local Placement Optimization (Checksum:8bf5099b) REAL time: 3 secs +Phase 10.5 Local Placement Optimization (Checksum:67f9eb6e) REAL time: 21 secs Phase 11.18 Placement Optimization -Phase 11.18 Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs +Phase 11.18 Placement Optimization (Checksum:32dd77c2) REAL time: 22 secs Phase 12.5 Local Placement Optimization -Phase 12.5 Local Placement Optimization (Checksum:8bd6219d) REAL time: 3 secs +Phase 12.5 Local Placement Optimization (Checksum:32dd77c2) REAL time: 22 secs Phase 13.34 Placement Validation -Phase 13.34 Placement Validation (Checksum:8bd2a88c) REAL time: 3 secs +Phase 13.34 Placement Validation (Checksum:32dd77c2) REAL time: 22 secs -Total REAL time to Placer completion: 3 secs -Total CPU time to Placer completion: 3 secs +Total REAL time to Placer completion: 22 secs +Total CPU time to Placer completion: 22 secs +Running physical synthesis... + +Physical synthesis completed. Running post-placement packing... Writing output files... +WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs + (RAMB8BWER). 9K Block RAM initialization data, both user defined and + default, may be incorrect and should not be used. For more information, + please reference Xilinx Answer Record 39999. Design Summary -------------- Design Summary: Number of errors: 0 -Number of warnings: 0 +Number of warnings: 1 Slice Logic Utilization: - Number of Slice Registers: 34 out of 11,440 1% - Number used as Flip Flops: 34 + Number of Slice Registers: 1 out of 11,440 1% + Number used as Flip Flops: 1 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 - Number of Slice LUTs: 17 out of 5,720 1% - Number used as logic: 13 out of 5,720 1% - Number using O6 output only: 11 - Number using O5 output only: 0 - Number using O5 and O6: 2 + Number of Slice LUTs: 33 out of 5,720 1% + Number used as logic: 9 out of 5,720 1% + Number using O6 output only: 8 + Number using O5 output only: 1 + Number using O5 and O6: 0 Number used as ROM: 0 - Number used as Memory: 0 out of 1,440 0% - Number used exclusively as route-thrus: 4 - Number with same-slice register load: 4 - Number with same-slice carry load: 0 - Number with other load: 0 + Number used as Memory: 24 out of 1,440 1% + Number used as Dual Port RAM: 24 + Number using O6 output only: 4 + Number using O5 output only: 0 + Number using O5 and O6: 20 + Number used as Single Port RAM: 0 + Number used as Shift Register: 0 Slice Logic Distribution: - Number of occupied Slices: 11 out of 1,430 1% - Number of MUXCYs used: 12 out of 2,860 1% - Number of LUT Flip Flop pairs used: 41 - Number with an unused Flip Flop: 11 out of 41 26% - Number with an unused LUT: 24 out of 41 58% - Number of fully used LUT-FF pairs: 6 out of 41 14% - Number of unique control sets: 1 + Number of occupied Slices: 9 out of 1,430 1% + Number of MUXCYs used: 8 out of 2,860 1% + Number of LUT Flip Flop pairs used: 33 + Number with an unused Flip Flop: 32 out of 33 96% + Number with an unused LUT: 0 out of 33 0% + Number of fully used LUT-FF pairs: 1 out of 33 3% + Number of unique control sets: 2 Number of slice register sites lost - to control set restrictions: 6 out of 11,440 1% + to control set restrictions: 11 out of 11,440 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of @@ -130,12 +125,12 @@ Slice Logic Distribution: over-mapped for a non-slice resource or if Placement fails. IO Utilization: - Number of bonded IOBs: 43 out of 186 23% + Number of bonded IOBs: 66 out of 186 35% IOB Flip Flops: 5 Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% - Number of RAMB8BWERs: 0 out of 64 0% + Number of RAMB8BWERs: 1 out of 64 1% Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3% Number used as BUFIO2s: 1 Number used as BUFIO2_2CLKs: 0 @@ -164,11 +159,11 @@ Specific Feature Utilization: Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% -Average Fanout of Non-Clock Nets: 1.41 +Average Fanout of Non-Clock Nets: 1.67 -Peak Memory Usage: 276 MB -Total REAL time to MAP completion: 3 secs -Total CPU time to MAP completion: 3 secs +Peak Memory Usage: 368 MB +Total REAL time to MAP completion: 25 secs +Total CPU time to MAP completion (all processors): 25 secs Mapping completed. See MAP report file "WarpLC_map.mrp" for details. diff --git a/fpga/WarpLC_map.mrp b/fpga/WarpLC_map.mrp index 0b66442..a8fb292 100644 --- a/fpga/WarpLC_map.mrp +++ b/fpga/WarpLC_map.mrp @@ -1,49 +1,51 @@ -Release 14.7 Map P.20131013 (nt) +Release 14.7 Map P.20131013 (nt64) Xilinx Mapping Report File for Design 'WarpLC' Design Information ------------------ -Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt off -ol -high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off --pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf +Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high +-xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2 +-ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf Target Device : xc6slx9 Target Package : ftg256 Target Speed : -2 Mapper Version : spartan6 -- $Revision: 1.55 $ -Mapped Date : Fri Oct 29 17:59:44 2021 +Mapped Date : Sun Oct 31 15:38:01 2021 Design Summary -------------- Number of errors: 0 -Number of warnings: 0 +Number of warnings: 1 Slice Logic Utilization: - Number of Slice Registers: 34 out of 11,440 1% - Number used as Flip Flops: 34 + Number of Slice Registers: 1 out of 11,440 1% + Number used as Flip Flops: 1 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 - Number of Slice LUTs: 17 out of 5,720 1% - Number used as logic: 13 out of 5,720 1% - Number using O6 output only: 11 - Number using O5 output only: 0 - Number using O5 and O6: 2 + Number of Slice LUTs: 33 out of 5,720 1% + Number used as logic: 9 out of 5,720 1% + Number using O6 output only: 8 + Number using O5 output only: 1 + Number using O5 and O6: 0 Number used as ROM: 0 - Number used as Memory: 0 out of 1,440 0% - Number used exclusively as route-thrus: 4 - Number with same-slice register load: 4 - Number with same-slice carry load: 0 - Number with other load: 0 + Number used as Memory: 24 out of 1,440 1% + Number used as Dual Port RAM: 24 + Number using O6 output only: 4 + Number using O5 output only: 0 + Number using O5 and O6: 20 + Number used as Single Port RAM: 0 + Number used as Shift Register: 0 Slice Logic Distribution: - Number of occupied Slices: 11 out of 1,430 1% - Number of MUXCYs used: 12 out of 2,860 1% - Number of LUT Flip Flop pairs used: 41 - Number with an unused Flip Flop: 11 out of 41 26% - Number with an unused LUT: 24 out of 41 58% - Number of fully used LUT-FF pairs: 6 out of 41 14% - Number of unique control sets: 1 + Number of occupied Slices: 9 out of 1,430 1% + Number of MUXCYs used: 8 out of 2,860 1% + Number of LUT Flip Flop pairs used: 33 + Number with an unused Flip Flop: 32 out of 33 96% + Number with an unused LUT: 0 out of 33 0% + Number of fully used LUT-FF pairs: 1 out of 33 3% + Number of unique control sets: 2 Number of slice register sites lost - to control set restrictions: 6 out of 11,440 1% + to control set restrictions: 11 out of 11,440 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of @@ -52,12 +54,12 @@ Slice Logic Distribution: over-mapped for a non-slice resource or if Placement fails. IO Utilization: - Number of bonded IOBs: 43 out of 186 23% + Number of bonded IOBs: 66 out of 186 35% IOB Flip Flops: 5 Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% - Number of RAMB8BWERs: 0 out of 64 0% + Number of RAMB8BWERs: 1 out of 64 1% Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3% Number used as BUFIO2s: 1 Number used as BUFIO2_2CLKs: 0 @@ -86,11 +88,11 @@ Specific Feature Utilization: Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% -Average Fanout of Non-Clock Nets: 1.41 +Average Fanout of Non-Clock Nets: 1.67 -Peak Memory Usage: 276 MB -Total REAL time to MAP completion: 3 secs -Total CPU time to MAP completion: 3 secs +Peak Memory Usage: 368 MB +Total REAL time to MAP completion: 25 secs +Total CPU time to MAP completion (all processors): 25 secs Table of Contents ----------------- @@ -113,22 +115,26 @@ Section 1 - Errors Section 2 - Warnings -------------------- -WARNING:Security:43 - No license file was found in the standard Xilinx license -directory. -WARNING:Security:44 - Since no license file was found, -WARNING:Security:40 - Your license for 'ISE' expires in 4 days. +WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs + (RAMB8BWER). 9K Block RAM initialization data, both user defined and + default, may be incorrect and should not be used. For more information, + please reference Xilinx Answer Record 39999. Section 3 - Informational ------------------------- -INFO:Security:51 - The XILINXD_LICENSE_FILE environment variable is not set. -INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to -'C:\ispLEVER_Classic2_0\license\license.dat;C:\lscc\diamond\3.12\license\license -.dat;C:\Xilinx\14.7\ISE_DS\Xilinx.lic'. -INFO:Security:54 - 'xc6slx9' is a WebPack part. -INFO:Security:66 - Your license for 'ISE' is for evaluation use only. +INFO:Map:284 - Map is running with the multi-threading option on. Map currently + supports the use of up to 2 processors. Based on the the user options and + machine load, Map will use 2 processors during this run. +INFO:LIT:243 - Logical network FSB_A<31> has no load. +INFO:LIT:395 - The above info message is repeated 54 more times for the + following (max. 5 shown): + FSB_A<30>, + FSB_A<29>, + FSB_A<28>, + FSB_A<1>, + FSB_A<0> + To see the details of these info messages, please use the -detail switch. INFO:MapLib:562 - No environment variables are currently set. -INFO:MapLib:159 - Net Timing constraints on signal CLKIN are pushed forward - through input buffer. INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to @@ -139,11 +145,314 @@ INFO:Pack:1650 - Map created a placed design. Section 4 - Removed Logic Summary --------------------------------- + 46 block(s) removed 2 block(s) optimized away + 68 signal(s) removed Section 5 - Removed Logic ------------------------- +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<0>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_0" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<1>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_1" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<2>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_2" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<3>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_3" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<4>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_4" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<5>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_5" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<6>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_6" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<7>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_7" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<8>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_8" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<9>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_9" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<10>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_10" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<11>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_11" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<12>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_12" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<13>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_13" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<14>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_14" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<15>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_15" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<16>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_16" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<17>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_17" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<18>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_18" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<19>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_19" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<20>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_20" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int<21>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qdpo_int_21" +(FF) removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<0>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_0" +(FF) removed. + The signal "l2pre/Way0Tag/spo<0>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<1>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_1" +(FF) removed. + The signal "l2pre/Way0Tag/spo<1>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<2>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_2" +(FF) removed. + The signal "l2pre/Way0Tag/spo<2>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<3>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_3" +(FF) removed. + The signal "l2pre/Way0Tag/spo<3>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<4>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_4" +(FF) removed. + The signal "l2pre/Way0Tag/spo<4>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<5>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_5" +(FF) removed. + The signal "l2pre/Way0Tag/spo<5>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<6>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_6" +(FF) removed. + The signal "l2pre/Way0Tag/spo<6>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<7>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_7" +(FF) removed. + The signal "l2pre/Way0Tag/spo<7>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<8>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_8" +(FF) removed. + The signal "l2pre/Way0Tag/spo<8>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<9>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_9" +(FF) removed. + The signal "l2pre/Way0Tag/spo<9>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<10>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_10" +(FF) removed. + The signal "l2pre/Way0Tag/spo<10>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<11>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_11" +(FF) removed. + The signal "l2pre/Way0Tag/spo<11>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<12>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_12" +(FF) removed. + The signal "l2pre/Way0Tag/spo<12>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<13>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_13" +(FF) removed. + The signal "l2pre/Way0Tag/spo<13>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<14>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_14" +(FF) removed. + The signal "l2pre/Way0Tag/spo<14>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<15>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_15" +(FF) removed. + The signal "l2pre/Way0Tag/spo<15>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<16>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_16" +(FF) removed. + The signal "l2pre/Way0Tag/spo<16>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<17>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_17" +(FF) removed. + The signal "l2pre/Way0Tag/spo<17>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<18>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_18" +(FF) removed. + The signal "l2pre/Way0Tag/spo<18>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<19>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_19" +(FF) removed. + The signal "l2pre/Way0Tag/spo<19>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<20>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_20" +(FF) removed. + The signal "l2pre/Way0Tag/spo<20>" is loadless and has been removed. +The signal +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int<21>" +is loadless and has been removed. + Loadless block +"l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/qspo_int_21" +(FF) removed. + The signal "l2pre/Way0Tag/spo<21>" is loadless and has been removed. +The signal "cg/pll/pll_base_inst/N2" is sourceless and has been removed. +The signal "cg/pll/pll_base_inst/N3" is sourceless and has been removed. +Unused block "cg/pll/pll_base_inst/XST_GND" (ZERO) removed. +Unused block "cg/pll/pll_base_inst/XST_VCC" (ONE) removed. + Optimized Block(s): TYPE BLOCK GND XST_GND @@ -163,11 +472,8 @@ Section 6 - IOB Properties | CLKFB_OUT | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | | | CLKIN | IOB | INPUT | LVCMOS25 | | | | | | | | CPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | | -| CPUCLKi | IOB | INPUT | LVCMOS33 | | | | | | | -| CPU_nAS | IOB | INPUT | LVCMOS33 | | | | | | | +| CPU_nSTERM | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | | | FPUCLK | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | | -| FSB_A<0> | IOB | INPUT | LVCMOS33 | | | | | | | -| FSB_A<1> | IOB | INPUT | LVCMOS33 | | | | | | | | FSB_A<2> | IOB | INPUT | LVCMOS33 | | | | | | | | FSB_A<3> | IOB | INPUT | LVCMOS33 | | | | | | | | FSB_A<4> | IOB | INPUT | LVCMOS33 | | | | | | | @@ -194,12 +500,38 @@ Section 6 - IOB Properties | FSB_A<25> | IOB | INPUT | LVCMOS33 | | | | | | | | FSB_A<26> | IOB | INPUT | LVCMOS33 | | | | | | | | FSB_A<27> | IOB | INPUT | LVCMOS33 | | | | | | | -| FSB_A<28> | IOB | INPUT | LVCMOS33 | | | | | | | -| FSB_A<29> | IOB | INPUT | LVCMOS33 | | | | | | | -| FSB_A<30> | IOB | INPUT | LVCMOS33 | | | | | | | -| FSB_A<31> | IOB | INPUT | LVCMOS33 | | | | | | | -| INt | IOB | INPUT | LVCMOS33 | | | | | | | -| OUTt | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | | | | +| FSB_D<0> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<1> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<2> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<3> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<4> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<5> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<6> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<7> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<8> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<9> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<10> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<11> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<12> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<13> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<14> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<15> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<16> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<17> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<18> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<19> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<20> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<21> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<22> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<23> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<24> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<25> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<26> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<27> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<28> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<29> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<30> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | +| FSB_D<31> | IOB | OUTPUT | LVCMOS33 | | 8 | SLOW | | | | | RAMCLK0 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | | | RAMCLK1 | IOB | OUTPUT | LVCMOS33 | | 24 | FAST | ODDR | | | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ diff --git a/fpga/WarpLC_map.ncd b/fpga/WarpLC_map.ncd index 5f44d38..37cdd4e 100644 --- a/fpga/WarpLC_map.ncd +++ b/fpga/WarpLC_map.ncd @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 -###6672:XlxV32DM 3fff 19f8eNqtW2tz3Day/StTW/oQZyOZAPjGxhXOkCPxel4mObKUWzcsDodU5q4sKZK8Scpyfvs2XkNyANlyVZwl0X3QOGgAzQZIzR5h2/2E6THe0OOr69tNdV3e3j0G9Hh38/jw+Od1U1edPNo9NKPju9Eftftw/Udw3D5eYcc9xqPj30fH17dXu5o1Ht227ej49nr06+7q19Hx4wiNjv94HFmj4/vmavfw2NyX249317u6etzd3gjr+5E96vUvwA+y3N2L8k6W17XUb39vJHQ7el/d380m5Yfq7uSm3kr15OZqL97V7YjAWO7hds1GtXcYgNtrlwo+UO7ukUONzsJEPW7p6/F6ejpfX5QX+JI0PZVcItJyPV3i6bi8sC4x2Spgry5ny9N0wlTbHqrOUHWHqjdUA4++XkUxsh0luErwlOBLwUFKwEogSrCVoHgcxeMoHmfPozp1LSUoZlcxu4rZVcyuYnYVs6uYXcXsKmZPMXuK2VPMnmL2FLOnmD3F7ClmTzF7itlXzL5i9hWzr5h9xewrZl8x+4rZV8x+ACuyms3KKD5nS4Jq+jqfpZOEK+5A8waaP9CCvoatgTbgxHigkYFm9zWnV4eAE1FEKDqxCCUniN0wsinBYbpYrYtwmo/L6F8Ehdabijo/WD8Q5weMbSbbPxDCZMei0aiu7u//HNW/Vrub0cNjdf+4u7ka/b57/FXWfPj4x+gf8/r2w111X3LS/yXo/8oo40Xz20d4vHF5W9Z//st68w9MIwQXhovAZcPlwOXaNILHCaR3Do0ysHRZgVSJZIllSWRpy9KRpStLT5a+LIM3nFbSYEmLlS5psaTFkhZLWixpsaTFkhZLWtmcSFqCBExEYYvCEYUrCk8UviiCNzD+rLT4HTn8bolCalgURBS2KBxRuKLwROGLIuBcohkWXFhwYQkKLiy4sODCggsLLiy4sOAS9kRwEcQxm98dfnf53eN3n98DWE9Y0zGs+BhWfAwrPoYVH8OKj6Gj8Ww5eeuJ4uISWXQ8P83KqCiydLwukpzagLCgGL8LKEu4POtuqUitMsMiRFXu3SdhRrVOZ3FZRNlpArfJmQ9IXqaL6RLoLmo6bq4fRtYJgY1q1XAtZOQluyF3D4icvufF/QoJbwQ2ibLsEp4erkynZZ5J+SzKYrQVcroclykMqempC6BpO325LgAIBDBbF04nuqp/sSFgZjud+gLjqV+KMjvJUjqYJafgFKYTYJnAakxgNSawGhNYjYkLUzaJ4vI8Td6X50mWp8uFQ/mYoDYhdJIuQHgLwluL3ZBtsftTHMOKzdLTxTxZFOHECrlPxeUqCaEqzLN0kRbl8l1ogcxgJkf55WLy9GQjA8ViuUheRCI4wJfZW5vdLH6HLA/36Thd+EIAKinBVAdSArDpxHIJMy4aniaLcnfz8Ph6slqDymVEDDX3qDKh5V1V/xse2i9U4mcq7x8e724fMfpCJYIhnJfWgavTnqv+oCaL5mxinq9CXMHDKnarbuqmvKk+NK/r63+3m3Lzsb0qbz8+4vbFpnIqXka+u8XtBm+/aroDW7y3d15kf4Wrr9vdMC/4CPHXjJmR9wIjPhMvs7zdbu+x9WXL3Q3C9ldNWKcHMaSZQY/W1+YObATXlxb87vq63FQPjaiT6YZsv7VFOZ+VC8g7cXoOLblj6cIVhYh1eEjZ4w2ZE57FJYHHeDmfp0WRxLC0y7yARD+eJWABhtCQPxAbWfKn25PKrlZCmSq4vIlyFCipf4RZxCUpbyF5P18HxxrUfKn++uNjva9nfUJ8vYN+syQC90G5AIcvWYKDbuAQtd+VKqHybanuZNhxmoE2HQdSh+1DcqgdQqlyohUNPyPOBtoFouBMDHtDDE9ADHtDDHtDDHtD7BIapxa7IXbD7EZcKlbLpjHfouN3cMG+mkyny6woZ8l5MnPoNJrliUunckGm3YIAmI9B2cpSZgufimOp9SaQEuqJqBNxJ5JOtDvR6US3E71O9DsxeKP67XrAXb+4h3b94q5f3PWLu35x1y/u+sVdv7jrt6OFQ+SG9s7mexztjclesveSs5fcveTtJX8vBW9qIZUWj8at1NCBioYqHqpkqNpD1RmqLlfhgDHQy/vHvYV3YOFpFv6Bha9ZBAcWgbJQ4x2OCA/Hiw9qh+PFw/Hi4XjxcLzYHareUPWHqnBT+Tjslgx9JGhgSwaaPdCcgeYONG+g+QMtkB2ezpbjaFbyJGLBsXKgqzOOEcZmmAw5UTtUT6xD4JAeKXqaYppacC0IXI8+u3GvQVqOX7PTdSAkdrCuuCjO1B6X4ZwM+0eaJ0U5T+bjJCv5+0cJJ8Y4XZy+Fl+OXqewqZylScbeHS7heHq6nCwXOQSGTVnV/iWlXLHDcl7A0bVcZctVmUPF4hTikJlJ0pKdWSG3PUcKWXdYxe1dDqaLIskWMA2rWZlFi9PE2nJ8sYwTYScaZ8k0yZIFvPuzMzxk6nm0KifzeJYu4Li8KuBAn1ccnC/j9SzZcrlI50leRPPVhqvy5A+Nqzs4uL30rR4HLzSFZP5iWvRyU/xyU/JyU/vlps7LTd2Xm3ovN/Vfbhq8cLng4MKWtnqpLbK+gRh9gy3+BlvyDbb2N9g632DrfoOt9w22/jfYBnCIWFiQpE8mzmxdCAWfxEzx6CIp3i+zt4guMV3CEW8JR7zlBFKCPDa+5u/fgL8DfF3Y7AaZlt1PIH8GXOLHuIquTrCFCIIroCsCWSqaJDGkPyWr3OPSVTR5m8SE8m/KdBXnMvOewlFZJko4hhtxlt0gpXV1nJp9L2h74DqPTpMB9flkYqTu4Zz6sA3ren6a1RyG2eKJthLaaVymseh2Fc9VypQUq3RRJhewG8RJLLKz4ODfVfoDOk8mvGfUVTNm9lGj36TvqGri9KpF5yXbNeT8DPCMLRC4NF7naXyxUfIimrPRvC3hNWpVRKcbIS/yAsIDNl7Q4iRPTxfg07zMl+tskgh4mkWneVksy3ECGzPsOy1Dwaq3kQDAlro4y9ZQK9481KseG+/97eMte/OwTtirzckSNsY9hk7ES82JeLtgcbSvsk7Y5g7b3SEEhwViAC0jarbFRpQYUduIOkbUNaKeEfWNaGAasNFdbBwwNg4YmxmMA8bGAWPjgLFxwNg4YGwcMDYO2OgYMQ6YGAdMjAMmZl7jgIlxwMQ1uWubQMcEGpt7JtA3gQF7LA9ByM4sSSgYn6gPBfCsbTqcnMiH8kR9KEXVM7Xs+0u/J/dEfLKA9ATHVBM8fCZ9sQ2dLJ0hGiuUvvOo/FpZK0F+uJFfKhWMOExolheY5vAikMO85BguUtE8nUPmOk8nSU3FR47XkQtd7LXxQONOdRqr2+41/j0fEpDS1cj29vGgdcxaV3ttOt0I+eJ15Eyndad0ZqD1zMZ9s/HAbNwzm/TNJgOzSc8s7pv1Pb0YeHrBPGWTt3LlnzPghSNPsoL98QCxD3MStXywibIiWrhgnXk0/7W6a0qrocV+52T7Xct1uXvwDdA+RGCfTjJYNAGzxeL7Bezd7RDLYDX6wBxWo6fnq4SfNAq576bzFQwpLQRL0dubRV98Z+QOzNJxvqHgRhkv1+NZkrlUvPY1tP+TgqsPiF5U9CI+EwPMfS7DUCYCzc+iVSJRRrzhkup1Sy9SePu6OL6IxyPrBI3yYi2EKJ+kqUsvtpsy3UKj7YdyvLvZ7m6uYDhMm1f/f3t/3tw/7G5vFLS76SB66dH6w/Z6d9O4VPwiw6bspxeE7h4aQm/b1qcPcE58rG5cj8rfbmy2Fn0aR4v4fRoXZyE7mM3Tn5M4ZN/fpjCZY1iGUCWDkB0OkkUeseNbyA417DVUfkqMy1kSsSULsUDOAWINSnixlthkBseBcny5ivI85F8CezAcZMB0FiKJvbXmF6GlFNRXcF8hfcXuK05fGa8hP5STRXEIJQv2pTgssrXy5i1YZbPObjruE/GpwGUSnw4bSXwBb/Br6EWreqYF9D+YComaaFjO1VkEekDCwWc4kJEDmTjQcxzYyIFNHPg5DmLkICYO8hyHbeSwTRz2cxyOkcMxcThGjnLG/uAQJ0UyKfpNViqWIebTCBJQlsLTcJZO+81Z4K9mnWWW5DLW4jQDQsh6xVkpInLfSpyFD/yWoOZhbHgSB2NLFmU8u+wagD58lgEo2AM5MGEI0hCsIWSAnE+W1rBrQJCGYA0hGmJriKMhroZ4GsImDhlRt3M9XRTTsVyYdMlWPc8mUp9Nz6YhESLb9aZjPp89hOU2BjkcmkcwwVO2Bnv6xbhIB8BqGstF9/c6YxBxsnqfQfX0tOc1+2O++BnPnoOFkrCHvFrC7r6Kew3yt7D59TNdkfCPi+V7eLtcvu9ZsvhhmVmYncNw01PY9NKcd/X0tE9a8/WsCBHebxjl6iwCDuvECsWf7ti30XQZh0QCeAjwrAXznsZJ6HbAurgsJ5eTGWNy9vCAm+cq2RJ1gKkl0lriw5bY3BJrLclhS2JuSbSW9mFL29zS1lo6hy0dc0un11Kmhn3D4ZYVw57I/x3gZxI/tJ8Z8WdonmF5jmQ1D3sMYv0PeTmq0XJ0ZkQ1UmQkRUZSZCRFOik2kmIjKTaSYp2UGEmJkZQYSYlOahtJbSOpbSS1dVLHSOoYSR0jqdMnVSE74JTgkFKCQ0ZI4jK37f8hcSH4Z/GC3SxLIkjWIyQMpGQh1VTces6kfNss5xciOR7ibLMdNuBbATuBYmx3ABynS5ZQQ+zI7SHNJ+G+EZzJ2W98+rOwXuyZAjdke8v/sF8+ZOxRt3y8pU/7B10I6sjNd4aU0cH7nEjwT084UPZDM24ktpRc2RLGnaXnCftr13h5EcJA8lnCNou8CPM1vIAtIJnnRVSANZyK4NUiyuJwdj6ZL3NCCLxuzKJiclYus3I6DeF/4qdcsrD4b7j439LUT8Iwok9fs/EodOb8aD35QoicJ69movvjd9/9FaHv2R3DPSI//RW5r74H1f7+r8h59erVP7/Ta3gFrzI0fbZl1/DVE6lk95H7T1E74HFeAYc9pACMQdAYNVrjiPQ8ewpEPQBPyAH5KT2YaeyYcUI+//TTndvY9Kef/sAYzlRwwkOf8rYNkQ9S5YaI2K4DkUjsjV99usG4CRGFog1deoRxDcG7oZ/zFhtb1HTLaC0IPfw8LRChIGQ/ezuqNiEmLr1BvhW6yKvdZovoEfJaDh8hH7HmIGxa9tjQ/xSoCoCd/bfZfLELbIV2Q9+hjQ9D/Ayly0pgskO7pUe1zarBk63oCiMYG/GYwHzCTGhCC1yrkXIN0z/RpgpJ4zMh4MIMVT4M9gihCpoRetMSmLHPZ6jyoM5rws2nI0xQSGAQIfuJ7RGGwqZHjtBcUdiiqEThiyIQhceJjzahXTPijUd/xpjNMLJwWDXh5w2bdADAwgp99Ok3tLHob6iqKVgj+nNVw9AdK/y8QySA1YFJAIT4MLjNBsZ4hlFLP6INuGRRCkaeZoR0I0czwrqRrRkR3YhoRrZuhDUjRzdCmpGrG1makacZQcAfGvm6UaMZBbrRVjOqdKNaM9roRpVmVOtG+gJvdSNfM2p0Iz0KWt3I1UNFDyisxwrSIwrrwYL0kMJ6tCA9prAeLkgPKqzHC9KjytYDBhnCSo8YpMcV0UMG6YFF9JhBemQRPWiQHlpko1vpsUX02EJ6cBHDahuiy9CjIbwMs6rFV8ui+bClZ+lg6+lYs9WxLdawW1QRHWwdgyGqDWBrm0BXB7d6N5uGdYP5fglTAHsRzOcRqrbw0MIGBFuXRWDELosaYA1Y//tGMA2fuG3F54+EJBCNqlZr8/mhYW7iTz9CY6ijv7Db5wdU9+CgBhhun2FHQfahY41wrFWO2WxC2DBZZ1vumGrVeRYIzyrEdmSgg9CDigZ2NOkr7E+HNOCrJ5xifAAyZ7fcWaeHwzP4C7uBt4116GwrnG2Us86evZtF68DXSs5ipVyspIuW1hhcRHLerIGHTd3Bvels2CMBMxw60kFYfN6pbSkPfQhOi/exRXw2GrGATSvmpvWF14Jp7zWqiZxixtiysTvKf1/6X7+IGsaknIftACKkYQHSkD22tegvcLFRNp1hC4YtB7edJQJLxEDX2YPQDcwH3Nh8VAcLhpGYj/pLYV89E/b+l8I+kA5U5rCvBuuEfI+5tQ3hWCZdQ54vl8pWvgV059h86hxHFCJ+HU8UvigCXghHdsFWFI0oxMxXlijEqlRYFMJyIyw3wrIWlrWwrIVlTfhYW+ELvKDKspblVpaNLOVyI2mHkCy5ozB2Zuf1QqttxARjLCNKRevmW2YA1oI7ALMbWIc9tLIH++/qAQ17YP+nR9GD+zf14LPqqt8Dpj8jWB/7E/LhGO7DY+7DuwbYfeY9t+KfTEUbDAsmJ95SC4BlSWQpFxQ58vkMZFnJciPLWvrEH2TU94nI3iBJ28oqwIdz48i58f+WuXkQcwNPFRNayAGtzdBApkomgC3l1TAIqPP8rsoJ6C+QzAAMeiDkjBozsOqBHoAivbhdh+wHBr9UPAvzOOPGVr/HivE4XRXrseLkbg+EHitG7nk9EHqseOpzmh4KO1DAc5/T9lAHUJ5k3J4bjg3otp8Shc8Y4JrPnSIGoedzAHVO3VUxnx0Gul4PBJ/hAp9xDwSf4QJqG/VQ8Bku5rPy7r/82EJd###4200:XlxV32DM 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\ No newline at end of file diff --git a/fpga/WarpLC_map.psr b/fpga/WarpLC_map.psr new file mode 100644 index 0000000..322f250 --- /dev/null +++ b/fpga/WarpLC_map.psr @@ -0,0 +1,145 @@ +Release 14.7 Physical Synthesis Report P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +TABLE OF CONTENTS + 1) Physical Synthesis Options Summary + 2) Optimizations statistics and details + + +========================================================================= +* Physical Synthesis Options Summary * +========================================================================= +---- Options +Global Optimization : ON + Retiming : OFF + Equivalent Register Removal : ON +Timing-Driven Packing and Placement : ON + Logic Optimization : ON + Register Duplication : OFF + +---- Intelligent clock gating : OFF + +---- Target Parameters +Target Device : 6slx9ftg256-2 + +========================================================================= + + +========================================================================= +* Optimizations * +========================================================================= +---- Statistics + Number of registers added by Synchronous Optimization | 1 + Number of LUTs removed by SmartOpt Trimming | 95 + + Overall change in number of design objects | -94 + + +---- Details + +New or modified components | Optimization | Objective +-------------------------------------------------------|--------------------------|---------------------- +cg/CPUCLKr | Synchronous Optimization | Performance + + +Removed components | Optimization +-------------------------------------------------------|-------------------------- +][288_1 | SmartOpt Trimming +][291_2 | SmartOpt Trimming +][293_4 | SmartOpt Trimming +][294_5 | SmartOpt Trimming +][297_7 | SmartOpt Trimming +][73_8 | SmartOpt Trimming +][const_101_66 | SmartOpt Trimming +][const_102_67 | SmartOpt Trimming +][const_104_68 | SmartOpt Trimming +][const_105_69 | SmartOpt Trimming +][const_107_70 | SmartOpt Trimming +][const_108_71 | SmartOpt Trimming +][const_110_72 | SmartOpt Trimming +][const_111_73 | SmartOpt Trimming +][const_113_74 | SmartOpt Trimming +][const_114_75 | SmartOpt Trimming +][const_116_76 | SmartOpt Trimming +][const_117_77 | SmartOpt Trimming +][const_119_78 | SmartOpt Trimming +][const_120_79 | SmartOpt Trimming +][const_122_80 | SmartOpt Trimming +][const_123_81 | SmartOpt Trimming +][const_125_82 | SmartOpt Trimming +][const_126_83 | SmartOpt Trimming +][const_128_84 | SmartOpt Trimming +][const_129_85 | SmartOpt Trimming +][const_131_86 | SmartOpt Trimming +][const_132_87 | SmartOpt Trimming +][const_134_88 | SmartOpt Trimming +][const_135_89 | SmartOpt Trimming +][const_137_90 | SmartOpt Trimming +][const_138_91 | SmartOpt Trimming +][const_140_92 | SmartOpt Trimming +][const_141_93 | SmartOpt Trimming +][const_143_94 | SmartOpt Trimming +][const_144_95 | SmartOpt Trimming +][const_146_96 | SmartOpt Trimming +][const_147_97 | SmartOpt Trimming +][const_15_9 | SmartOpt Trimming +][const_17_10 | SmartOpt Trimming +][const_18_11 | SmartOpt Trimming +][const_20_12 | SmartOpt Trimming +][const_21_13 | SmartOpt Trimming +][const_23_14 | SmartOpt Trimming +][const_24_15 | SmartOpt Trimming +][const_26_16 | SmartOpt Trimming +][const_27_17 | SmartOpt Trimming +][const_29_18 | SmartOpt Trimming +][const_30_19 | SmartOpt Trimming +][const_32_20 | SmartOpt Trimming +][const_33_21 | SmartOpt Trimming +][const_35_22 | SmartOpt Trimming +][const_36_23 | SmartOpt Trimming +][const_38_24 | SmartOpt Trimming +][const_39_25 | SmartOpt Trimming +][const_41_26 | SmartOpt Trimming +][const_42_27 | SmartOpt Trimming +][const_44_28 | SmartOpt Trimming +][const_45_29 | SmartOpt Trimming +][const_47_30 | SmartOpt Trimming +][const_48_31 | SmartOpt Trimming +][const_50_32 | SmartOpt Trimming +][const_51_33 | SmartOpt Trimming +][const_53_34 | SmartOpt Trimming +][const_54_35 | SmartOpt Trimming +][const_56_36 | SmartOpt Trimming +][const_57_37 | SmartOpt Trimming +][const_59_38 | SmartOpt Trimming +][const_60_39 | SmartOpt Trimming +][const_62_40 | SmartOpt Trimming +][const_63_41 | SmartOpt Trimming +][const_65_42 | SmartOpt Trimming +][const_66_43 | SmartOpt Trimming +][const_68_44 | SmartOpt Trimming +][const_69_45 | SmartOpt Trimming +][const_71_46 | SmartOpt Trimming +][const_72_47 | SmartOpt Trimming +][const_74_48 | SmartOpt Trimming +][const_75_49 | SmartOpt Trimming +][const_77_50 | SmartOpt Trimming +][const_78_51 | SmartOpt Trimming +][const_80_52 | SmartOpt Trimming +][const_81_53 | SmartOpt Trimming +][const_83_54 | SmartOpt Trimming +][const_84_55 | SmartOpt Trimming +][const_86_56 | SmartOpt Trimming +][const_87_57 | SmartOpt Trimming +][const_89_58 | SmartOpt Trimming +][const_90_59 | SmartOpt Trimming +][const_92_60 | SmartOpt Trimming +][const_93_61 | SmartOpt Trimming +][const_95_62 | SmartOpt Trimming +][const_96_63 | SmartOpt Trimming +][const_98_64 | SmartOpt Trimming +][const_99_65 | SmartOpt Trimming + + + Flops added for Enable Generation +------------------------- diff --git a/fpga/WarpLC_map.xrpt b/fpga/WarpLC_map.xrpt index 96cf758..4e37397 100644 --- a/fpga/WarpLC_map.xrpt +++ b/fpga/WarpLC_map.xrpt @@ -1,18 +1,18 @@ - + - +
- + @@ -36,26 +36,31 @@
- - + + - + - - + +
+ + + + + @@ -65,22 +70,22 @@
- - + + - - - - + + + + - - + + @@ -94,7 +99,7 @@ - + @@ -116,28 +121,28 @@
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- - + + - - - - + + + + - - + + @@ -145,25 +150,25 @@ - + - + - - - - + + + + - - - - + + + +
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@@ -249,18 +254,14 @@ - + - + + + - - - - - - @@ -269,213 +270,419 @@ - - - - - - - - - - - - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -484,7 +691,7 @@ - + @@ -505,7 +712,7 @@
- + @@ -531,7 +738,7 @@
- + @@ -544,7 +751,7 @@
- +
@@ -568,7 +775,7 @@ - + diff --git a/fpga/WarpLC_ngdbuild.xrpt b/fpga/WarpLC_ngdbuild.xrpt index 676acbb..f6cee5d 100644 --- a/fpga/WarpLC_ngdbuild.xrpt +++ b/fpga/WarpLC_ngdbuild.xrpt @@ -1,18 +1,18 @@ - + - +
- + @@ -36,16 +36,16 @@
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diff --git a/fpga/WarpLC_pad.csv b/fpga/WarpLC_pad.csv new file mode 100644 index 0000000..e1b208e --- /dev/null +++ b/fpga/WarpLC_pad.csv @@ -0,0 +1,287 @@ +#Release 14.7 - par P.20131013 (nt64) +#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +#Sun Oct 31 15:38:33 2021 + +# +## NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +#INPUT FILE: WarpLC_map.ncd +#OUTPUT FILE: WarpLC_pad.csv +#PART TYPE: xc6slx9 +#SPEED GRADE: -2 +#PACKAGE: ftg256 +# +# Pinout by Pin Number: +# +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, +A1,,,GND,,,,,,,,,,,, +A2,,IOBS,IO_L52N_M3A9_3,UNUSED,,3,,,,,,,,, +A3,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,, +A4,CLKFB_OUT,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, +A5,FSB_D<0>,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A6,FSB_D<4>,IOB,IO_L4N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A7,FSB_D<6>,IOB,IO_L6N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A8,FSB_D<12>,IOB,IO_L33N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A9,FSB_D<14>,IOB,IO_L34N_GCLK18_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A10,FSB_D<16>,IOB,IO_L35N_GCLK16_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A11,FSB_D<22>,IOB,IO_L39N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A12,FSB_D<28>,IOB,IO_L62N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A13,FSB_D<30>,IOB,IO_L63N_SCP6_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +A14,RAMCLK0,IOB,IO_L65N_SCP2_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, +A15,,,TMS,,,,,,,,,,,, +A16,,,GND,,,,,,,,,,,, +B1,,IOBS,IO_L50N_M3BA2_3,UNUSED,,3,,,,,,,,, +B2,,IOBM,IO_L52P_M3A8_3,UNUSED,,3,,,,,,,,, +B3,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,, +B4,,,VCCO_0,,,0,,,,,3.30,,,, +B5,CPUCLK,IOB,IO_L2P_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, +B6,FSB_D<3>,IOB,IO_L4P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +B7,,,GND,,,,,,,,,,,, +B8,FSB_D<11>,IOB,IO_L33P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +B9,,,VCCO_0,,,0,,,,,3.30,,,, +B10,FSB_D<15>,IOB,IO_L35P_GCLK17_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +B11,,,GND,,,,,,,,,,,, +B12,FSB_D<27>,IOB,IO_L62P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +B13,,,VCCO_0,,,0,,,,,3.30,,,, +B14,FSB_A<2>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE, +B15,FSB_A<6>,IOB,IO_L29P_A23_M1A13_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +B16,FSB_A<7>,IOB,IO_L29N_A22_M1A14_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +C1,,IOBM,IO_L50P_M3WE_3,UNUSED,,3,,,,,,,,, +C2,,IOBS,IO_L48N_M3BA1_3,UNUSED,,3,,,,,,,,, +C3,,IOBM,IO_L48P_M3BA0_3,UNUSED,,3,,,,,,,,, +C4,RAMCLK1,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, +C5,FSB_D<2>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C6,FSB_D<10>,IOB,IO_L7N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C7,FSB_D<7>,IOB,IO_L6P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C8,FSB_D<24>,IOB,IO_L38N_VREF_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C9,FSB_D<13>,IOB,IO_L34P_GCLK19_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C10,FSB_D<20>,IOB,IO_L37N_GCLK12_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C11,FSB_D<23>,IOB,IO_L39P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C12,,,TDI,,,,,,,,,,,, +C13,FSB_D<29>,IOB,IO_L63P_SCP7_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +C14,,,TCK,,,,,,,,,,,, +C15,FSB_A<14>,IOB,IO_L33P_A15_M1A10_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +C16,FSB_A<20>,IOB,IO_L33N_A14_M1A4_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +D1,,IOBS,IO_L49N_M3A2_3,UNUSED,,3,,,,,,,,, +D2,,,VCCO_3,,,3,,,,,any******,,,, +D3,,IOBM,IO_L49P_M3A7_3,UNUSED,,3,,,,,,,,, +D4,,,GND,,,,,,,,,,,, +D5,FSB_D<1>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +D6,FSB_D<9>,IOB,IO_L7P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +D7,,,VCCO_0,,,0,,,,,3.30,,,, +D8,FSB_D<21>,IOB,IO_L38P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +D9,FSB_D<26>,IOB,IO_L40N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +D10,,,VCCO_0,,,0,,,,,3.30,,,, +D11,FPUCLK,IOB,IO_L66P_SCP1_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,YES,NONE, +D12,CPU_nSTERM,IOB,IO_L66N_SCP0_0,OUTPUT,LVCMOS33,0,24,FAST,,,,UNLOCATED,NO,NONE, +D13,,,GND,,,,,,,,,,,, +D14,FSB_A<10>,IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +D15,,,VCCO_1,,,1,,,,,any******,,,, +D16,FSB_A<11>,IOB,IO_L31N_A18_M1A12_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +E1,,IOBS,IO_L46N_M3CLKN_3,UNUSED,,3,,,,,,,,, +E2,,IOBM,IO_L46P_M3CLK_3,UNUSED,,3,,,,,,,,, +E3,,IOBS,IO_L54N_M3A11_3,UNUSED,,3,,,,,,,,, +E4,,IOBM,IO_L54P_M3RESET_3,UNUSED,,3,,,,,,,,, +E5,,,VCCAUX,,,,,,,,2.5,,,, +E6,FSB_D<8>,IOB,IO_L5N_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +E7,FSB_D<17>,IOB,IO_L36P_GCLK15_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +E8,FSB_D<18>,IOB,IO_L36N_GCLK14_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +E9,,,GND,,,,,,,,,,,, +E10,FSB_D<19>,IOB,IO_L37P_GCLK13_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +E11,FSB_A<3>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS33,0,,,,NONE,,UNLOCATED,NO,NONE, +E12,FSB_A<5>,IOB,IO_L1N_A24_VREF_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +E13,FSB_A<4>,IOB,IO_L1P_A25_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +E14,,,TDO,,,,,,,,,,,, +E15,FSB_A<21>,IOB,IO_L34P_A13_M1WE_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +E16,FSB_A<22>,IOB,IO_L34N_A12_M1BA2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +F1,,IOBS,IO_L41N_GCLK26_M3DQ5_3,UNUSED,,3,,,,,,,,, +F2,,IOBM,IO_L41P_GCLK27_M3DQ4_3,UNUSED,,3,,,,,,,,, +F3,,IOBS,IO_L53N_M3A12_3,UNUSED,,3,,,,,,,,, +F4,,IOBM,IO_L53P_M3CKE_3,UNUSED,,3,,,,,,,,, +F5,,IOBS,IO_L55N_M3A14_3,UNUSED,,3,,,,,,,,, +F6,,IOBM,IO_L55P_M3A13_3,UNUSED,,3,,,,,,,,, +F7,FSB_D<5>,IOB,IO_L5P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +F8,,,VCCAUX,,,,,,,,2.5,,,, +F9,FSB_D<25>,IOB,IO_L40P_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +F10,FSB_D<31>,IOB,IO_L64P_SCP5_0,OUTPUT,LVCMOS33,0,8,SLOW,,,,UNLOCATED,NO,NONE, +F11,,,VCCAUX,,,,,,,,2.5,,,, +F12,FSB_A<8>,IOB,IO_L30P_A21_M1RESET_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +F13,FSB_A<12>,IOB,IO_L32P_A17_M1A8_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +F14,FSB_A<13>,IOB,IO_L32N_A16_M1A9_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +F15,FSB_A<23>,IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +F16,FSB_A<19>,IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +G1,,IOBS,IO_L40N_M3DQ7_3,UNUSED,,3,,,,,,,,, +G2,,,GND,,,,,,,,,,,, +G3,,IOBM,IO_L40P_M3DQ6_3,UNUSED,,3,,,,,,,,, +G4,,,VCCO_3,,,3,,,,,any******,,,, +G5,,IOBS,IO_L51N_M3A4_3,UNUSED,,3,,,,,,,,, +G6,,IOBM,IO_L51P_M3A10_3,UNUSED,,3,,,,,,,,, +G7,,,VCCINT,,,,,,,,1.2,,,, +G8,,,GND,,,,,,,,,,,, +G9,,,VCCINT,,,,,,,,1.2,,,, +G10,,,VCCAUX,,,,,,,,2.5,,,, +G11,FSB_A<9>,IOB,IO_L30N_A20_M1A11_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +G12,FSB_A<24>,IOB,IO_L38P_A5_M1CLK_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +G13,,,VCCO_1,,,1,,,,,any******,,,, +G14,FSB_A<15>,IOB,IO_L36P_A9_M1BA0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +G15,,,GND,,,,,,,,,,,, +G16,FSB_A<16>,IOB,IO_L36N_A8_M1BA1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +H1,,IOBS,IO_L39N_M3LDQSN_3,UNUSED,,3,,,,,,,,, +H2,,IOBM,IO_L39P_M3LDQS_3,UNUSED,,3,,,,,,,,, +H3,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,, +H4,CLKFB_IN,IOB,IO_L44P_GCLK21_M3A5_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, +H5,,IOBS,IO_L43N_GCLK22_IRDY2_M3CASN_3,UNUSED,,3,,,,,,,,, +H6,,,VCCAUX,,,,,,,,2.5,,,, +H7,,,GND,,,,,,,,,,,, +H8,,,VCCINT,,,,,,,,1.2,,,, +H9,,,GND,,,,,,,,,,,, +H10,,,VCCINT,,,,,,,,1.2,,,, +H11,FSB_A<25>,IOB,IO_L38N_A4_M1CLKN_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +H12,,,GND,,,,,,,,,,,, +H13,FSB_A<26>,IOB,IO_L39P_M1A3_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +H14,FSB_A<27>,IOB,IO_L39N_M1ODT_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +H15,FSB_A<17>,IOB,IO_L37P_A7_M1A0_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +H16,FSB_A<18>,IOB,IO_L37N_A6_M1A1_1,INPUT,LVCMOS33,1,,,,NONE,,UNLOCATED,NO,NONE, +J1,,IOBS,IO_L38N_M3DQ3_3,UNUSED,,3,,,,,,,,, +J2,,,VCCO_3,,,3,,,,,any******,,,, +J3,,IOBM,IO_L38P_M3DQ2_3,UNUSED,,3,,,,,,,,, +J4,CLKIN,IOB,IO_L42N_GCLK24_M3LDM_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE, +J5,,,GND,,,,,,,,,,,, +J6,,IOBM,IO_L43P_GCLK23_M3RASN_3,UNUSED,,3,,,,,,,,, +J7,,,VCCINT,,,,,,,,1.2,,,, +J8,,,GND,,,,,,,,,,,, +J9,,,VCCINT,,,,,,,,1.2,,,, +J10,,,VCCAUX,,,,,,,,2.5,,,, +J11,,IOBM,IO_L40P_GCLK11_M1A5_1,UNUSED,,1,,,,,,,,, +J12,,IOBS,IO_L40N_GCLK10_M1A6_1,UNUSED,,1,,,,,,,,, +J13,,IOBM,IO_L41P_GCLK9_IRDY1_M1RASN_1,UNUSED,,1,,,,,,,,, +J14,,IOBM,IO_L43P_GCLK5_M1DQ4_1,UNUSED,,1,,,,,,,,, +J15,,,VCCO_1,,,1,,,,,any******,,,, +J16,,IOBS,IO_L43N_GCLK4_M1DQ5_1,UNUSED,,1,,,,,,,,, +K1,,IOBS,IO_L37N_M3DQ1_3,UNUSED,,3,,,,,,,,, +K2,,IOBM,IO_L37P_M3DQ0_3,UNUSED,,3,,,,,,,,, +K3,,IOBM,IO_L42P_GCLK25_TRDY2_M3UDM_3,UNUSED,,3,,,,,,,,, +K4,,,VCCO_3,,,3,,,,,any******,,,, +K5,,IOBM,IO_L47P_M3A0_3,UNUSED,,3,,,,,,,,, +K6,,IOBS,IO_L47N_M3A1_3,UNUSED,,3,,,,,,,,, +K7,,,GND,,,,,,,,,,,, +K8,,,VCCINT,,,,,,,,1.2,,,, +K9,,,GND,,,,,,,,,,,, +K10,,,VCCINT,,,,,,,,1.2,,,, +K11,,IOBS,IO_L42N_GCLK6_TRDY1_M1LDM_1,UNUSED,,1,,,,,,,,, +K12,,IOBM,IO_L42P_GCLK7_M1UDM_1,UNUSED,,1,,,,,,,,, +K13,,,VCCO_1,,,1,,,,,any******,,,, +K14,,IOBS,IO_L41N_GCLK8_M1CASN_1,UNUSED,,1,,,,,,,,, +K15,,IOBM,IO_L44P_A3_M1DQ6_1,UNUSED,,1,,,,,,,,, +K16,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,, +L1,,IOBS,IO_L36N_M3DQ9_3,UNUSED,,3,,,,,,,,, +L2,,,GND,,,,,,,,,,,, +L3,,IOBM,IO_L36P_M3DQ8_3,UNUSED,,3,,,,,,,,, +L4,,IOBM,IO_L45P_M3A3_3,UNUSED,,3,,,,,,,,, +L5,,IOBS,IO_L45N_M3ODT_3,UNUSED,,3,,,,,,,,, +L6,,,VCCAUX,,,,,,,,2.5,,,, +L7,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,, +L8,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,, +L9,,,VCCAUX,,,,,,,,2.5,,,, +L10,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,, +L11,,,CMPCS_B_2,,,,,,,,,,,, +L12,,IOBM,IO_L53P_1,UNUSED,,1,,,,,,,,, +L13,,IOBS,IO_L53N_VREF_1,UNUSED,,1,,,,,,,,, +L14,,IOBM,IO_L47P_FWE_B_M1DQ0_1,UNUSED,,1,,,,,,,,, +L15,,,GND,,,,,,,,,,,, +L16,,IOBS,IO_L47N_LDC_M1DQ1_1,UNUSED,,1,,,,,,,,, +M1,,IOBS,IO_L35N_M3DQ11_3,UNUSED,,3,,,,,,,,, +M2,,IOBM,IO_L35P_M3DQ10_3,UNUSED,,3,,,,,,,,, +M3,,IOBS,IO_L1N_VREF_3,UNUSED,,3,,,,,,,,, +M4,,IOBM,IO_L1P_3,UNUSED,,3,,,,,,,,, +M5,,IOBM,IO_L2P_3,UNUSED,,3,,,,,,,,, +M6,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,, +M7,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,, +M8,,,GND,,,,,,,,,,,, +M9,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,, +M10,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,, +M11,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,, +M12,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,, +M13,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,, +M14,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,, +M15,,IOBM,IO_L46P_FCS_B_M1DQ2_1,UNUSED,,1,,,,,,,,, +M16,,IOBS,IO_L46N_FOE_B_M1DQ3_1,UNUSED,,1,,,,,,,,, +N1,,IOBS,IO_L34N_M3UDQSN_3,UNUSED,,3,,,,,,,,, +N2,,,VCCO_3,,,3,,,,,any******,,,, +N3,,IOBM,IO_L34P_M3UDQS_3,UNUSED,,3,,,,,,,,, +N4,,IOBS,IO_L2N_3,UNUSED,,3,,,,,,,,, +N5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,, +N6,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,, +N7,,,VCCO_2,,,2,,,,,any******,,,, +N8,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,, +N9,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,, +N10,,,VCCO_2,,,2,,,,,any******,,,, +N11,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,, +N12,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,, +N13,,,GND,,,,,,,,,,,, +N14,,IOBM,IO_L45P_A1_M1LDQS_1,UNUSED,,1,,,,,,,,, +N15,,,VCCO_1,,,1,,,,,any******,,,, +N16,,IOBS,IO_L45N_A0_M1LDQSN_1,UNUSED,,1,,,,,,,,, +P1,,IOBS,IO_L33N_M3DQ13_3,UNUSED,,3,,,,,,,,, +P2,,IOBM,IO_L33P_M3DQ12_3,UNUSED,,3,,,,,,,,, +P3,,,GND,,,,,,,,,,,, +P4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,, +P5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,, +P6,,IOBM,IO_L47P_2,UNUSED,,2,,,,,,,,, +P7,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,, +P8,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,, +P9,,IOBS,IO_L14N_D12_2,UNUSED,,2,,,,,,,,, +P10,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,, +P11,,IOBS,IO_L13N_D10_2,UNUSED,,2,,,,,,,,, +P12,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,, +P13,,,DONE_2,,,,,,,,,,,, +P14,,,SUSPEND,,,,,,,,,,,, +P15,,IOBM,IO_L48P_HDC_M1DQ8_1,UNUSED,,1,,,,,,,,, +P16,,IOBS,IO_L48N_M1DQ9_1,UNUSED,,1,,,,,,,,, +R1,,IOBS,IO_L32N_M3DQ15_3,UNUSED,,3,,,,,,,,, +R2,,IOBM,IO_L32P_M3DQ14_3,UNUSED,,3,,,,,,,,, +R3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,, +R4,,,VCCO_2,,,2,,,,,any******,,,, +R5,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,, +R6,,,GND,,,,,,,,,,,, +R7,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,, +R8,,,VCCO_2,,,2,,,,,any******,,,, +R9,,IOBM,IO_L23P_2,UNUSED,,2,,,,,,,,, +R10,,,GND,,,,,,,,,,,, +R11,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,, +R12,,IOBM,IO_L52P_M1DQ14_1,UNUSED,,1,,,,,,,,, +R13,,,VCCO_1,,,1,,,,,any******,,,, +R14,,IOBM,IO_L50P_M1UDQS_1,UNUSED,,1,,,,,,,,, +R15,,IOBM,IO_L49P_M1DQ10_1,UNUSED,,1,,,,,,,,, +R16,,IOBS,IO_L49N_M1DQ11_1,UNUSED,,1,,,,,,,,, +T1,,,GND,,,,,,,,,,,, +T2,,,PROGRAM_B_2,,,,,,,,,,,, +T3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,, +T4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,, +T5,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,, +T6,,IOBS,IO_L47N_2,UNUSED,,2,,,,,,,,, +T7,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,, +T8,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,, +T9,,IOBS,IO_L23N_2,UNUSED,,2,,,,,,,,, +T10,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,, +T11,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,, +T12,,IOBS,IO_L52N_M1DQ15_1,UNUSED,,1,,,,,,,,, +T13,,IOBS,IO_L51N_M1DQ13_1,UNUSED,,1,,,,,,,,, +T14,,IOBM,IO_L51P_M1DQ12_1,UNUSED,,1,,,,,,,,, +T15,,IOBS,IO_L50N_M1UDQSN_1,UNUSED,,1,,,,,,,,, +T16,,,GND,,,,,,,,,,,, + +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +# +#* Default value. +#** This default Pullup/Pulldown value can be overridden in Bitgen. +#****** Special VCCO requirements may apply. Please consult the device +# family datasheet for specific guideline on VCCO requirements. +# +# +# \ No newline at end of file diff --git a/fpga/WarpLC_pad.txt b/fpga/WarpLC_pad.txt index 4ea2cec..441ce29 100644 --- a/fpga/WarpLC_pad.txt +++ b/fpga/WarpLC_pad.txt @@ -1,7 +1,7 @@ -Release 14.7 - par P.20131013 (nt) +Release 14.7 - par P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -Fri Oct 29 17:59:53 2021 +Sun Oct 31 15:38:33 2021 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: @@ -23,137 +23,137 @@ Pinout by Pin Number: |A1 | | |GND | | | | | | | | | | | | |A2 | |IOBS |IO_L52N_M3A9_3 |UNUSED | |3 | | | | | | | | | |A3 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | | -|A4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | | -|A5 | |IOBS |IO_L2N_0 |UNUSED | |0 | | | | | | | | | -|A6 | |IOBS |IO_L4N_0 |UNUSED | |0 | | | | | | | | | -|A7 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | | -|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | | -|A9 | |IOBS |IO_L34N_GCLK18_0 |UNUSED | |0 | | | | | | | | | -|A10 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | | -|A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | | -|A12 | |IOBS |IO_L62N_VREF_0 |UNUSED | |0 | | | | | | | | | -|A13 | |IOBS |IO_L63N_SCP6_0 |UNUSED | |0 | | | | | | | | | -|A14 | |IOBS |IO_L65N_SCP2_0 |UNUSED | |0 | | | | | | | | | +|A4 |CLKFB_OUT |IOB |IO_L1N_VREF_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE | +|A5 |FSB_D<0> |IOB |IO_L2N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A6 |FSB_D<4> |IOB |IO_L4N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A7 |FSB_D<6> |IOB |IO_L6N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A8 |FSB_D<12> |IOB |IO_L33N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A9 |FSB_D<14> |IOB |IO_L34N_GCLK18_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A10 |FSB_D<16> |IOB |IO_L35N_GCLK16_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A11 |FSB_D<22> |IOB |IO_L39N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A12 |FSB_D<28> |IOB |IO_L62N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A13 |FSB_D<30> |IOB |IO_L63N_SCP6_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|A14 |RAMCLK0 |IOB |IO_L65N_SCP2_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE | |A15 | | |TMS | | | | | | | | | | | | |A16 | | |GND | | | | | | | | | | | | -|B1 |CPUCLK |IOB |IO_L50N_M3BA2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE | +|B1 | |IOBS |IO_L50N_M3BA2_3 |UNUSED | |3 | | | | | | | | | |B2 | |IOBM |IO_L52P_M3A8_3 |UNUSED | |3 | | | | | | | | | |B3 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | | -|B4 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B5 | |IOBM |IO_L2P_0 |UNUSED | |0 | | | | | | | | | -|B6 | |IOBM |IO_L4P_0 |UNUSED | |0 | | | | | | | | | +|B4 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|B5 |CPUCLK |IOB |IO_L2P_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE | +|B6 |FSB_D<3> |IOB |IO_L4P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |B7 | | |GND | | | | | | | | | | | | -|B8 | |IOBM |IO_L33P_0 |UNUSED | |0 | | | | | | | | | -|B9 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B10 | |IOBM |IO_L35P_GCLK17_0 |UNUSED | |0 | | | | | | | | | +|B8 |FSB_D<11> |IOB |IO_L33P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|B9 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|B10 |FSB_D<15> |IOB |IO_L35P_GCLK17_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |B11 | | |GND | | | | | | | | | | | | -|B12 | |IOBM |IO_L62P_0 |UNUSED | |0 | | | | | | | | | -|B13 | | |VCCO_0 | | |0 | | | | |any******| | | | -|B14 | |IOBM |IO_L65P_SCP3_0 |UNUSED | |0 | | | | | | | | | -|B15 | |IOBM |IO_L29P_A23_M1A13_1 |UNUSED | |1 | | | | | | | | | -|B16 | |IOBS |IO_L29N_A22_M1A14_1 |UNUSED | |1 | | | | | | | | | -|C1 |FPUCLK |IOB |IO_L50P_M3WE_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE | -|C2 |INt |IOB |IO_L48N_M3BA1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|C3 |OUTt |IOB |IO_L48P_M3BA0_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |NO |NONE | -|C4 | |IOBM |IO_L1P_HSWAPEN_0 |UNUSED | |0 | | | | | | | | | -|C5 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | | -|C6 | |IOBS |IO_L7N_0 |UNUSED | |0 | | | | | | | | | -|C7 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | | -|C8 | |IOBS |IO_L38N_VREF_0 |UNUSED | |0 | | | | | | | | | -|C9 | |IOBM |IO_L34P_GCLK19_0 |UNUSED | |0 | | | | | | | | | -|C10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | | -|C11 | |IOBM |IO_L39P_0 |UNUSED | |0 | | | | | | | | | +|B12 |FSB_D<27> |IOB |IO_L62P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|B13 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|B14 |FSB_A<2> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE | +|B15 |FSB_A<6> |IOB |IO_L29P_A23_M1A13_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|B16 |FSB_A<7> |IOB |IO_L29N_A22_M1A14_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|C1 | |IOBM |IO_L50P_M3WE_3 |UNUSED | |3 | | | | | | | | | +|C2 | |IOBS |IO_L48N_M3BA1_3 |UNUSED | |3 | | | | | | | | | +|C3 | |IOBM |IO_L48P_M3BA0_3 |UNUSED | |3 | | | | | | | | | +|C4 |RAMCLK1 |IOB |IO_L1P_HSWAPEN_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE | +|C5 |FSB_D<2> |IOB |IO_L3N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|C6 |FSB_D<10> |IOB |IO_L7N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|C7 |FSB_D<7> |IOB |IO_L6P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|C8 |FSB_D<24> |IOB |IO_L38N_VREF_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|C9 |FSB_D<13> |IOB |IO_L34P_GCLK19_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|C10 |FSB_D<20> |IOB |IO_L37N_GCLK12_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|C11 |FSB_D<23> |IOB |IO_L39P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |C12 | | |TDI | | | | | | | | | | | | -|C13 | |IOBM |IO_L63P_SCP7_0 |UNUSED | |0 | | | | | | | | | +|C13 |FSB_D<29> |IOB |IO_L63P_SCP7_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |C14 | | |TCK | | | | | | | | | | | | -|C15 | |IOBM |IO_L33P_A15_M1A10_1 |UNUSED | |1 | | | | | | | | | -|C16 | |IOBS |IO_L33N_A14_M1A4_1 |UNUSED | |1 | | | | | | | | | -|D1 |RAMCLK0 |IOB |IO_L49N_M3A2_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE | -|D2 | | |VCCO_3 | | |3 | | | | |3.30 | | | | -|D3 |RAMCLK1 |IOB |IO_L49P_M3A7_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE | +|C15 |FSB_A<14> |IOB |IO_L33P_A15_M1A10_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|C16 |FSB_A<20> |IOB |IO_L33N_A14_M1A4_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|D1 | |IOBS |IO_L49N_M3A2_3 |UNUSED | |3 | | | | | | | | | +|D2 | | |VCCO_3 | | |3 | | | | |any******| | | | +|D3 | |IOBM |IO_L49P_M3A7_3 |UNUSED | |3 | | | | | | | | | |D4 | | |GND | | | | | | | | | | | | -|D5 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | | -|D6 | |IOBM |IO_L7P_0 |UNUSED | |0 | | | | | | | | | -|D7 | | |VCCO_0 | | |0 | | | | |any******| | | | -|D8 | |IOBM |IO_L38P_0 |UNUSED | |0 | | | | | | | | | -|D9 | |IOBS |IO_L40N_0 |UNUSED | |0 | | | | | | | | | -|D10 | | |VCCO_0 | | |0 | | | | |any******| | | | -|D11 | |IOBM |IO_L66P_SCP1_0 |UNUSED | |0 | | | | | | | | | -|D12 | |IOBS |IO_L66N_SCP0_0 |UNUSED | |0 | | | | | | | | | +|D5 |FSB_D<1> |IOB |IO_L3P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|D6 |FSB_D<9> |IOB |IO_L7P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|D7 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|D8 |FSB_D<21> |IOB |IO_L38P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|D9 |FSB_D<26> |IOB |IO_L40N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|D10 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|D11 |FPUCLK |IOB |IO_L66P_SCP1_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |YES |NONE | +|D12 |CPU_nSTERM |IOB |IO_L66N_SCP0_0 |OUTPUT |LVCMOS33 |0 |24 |FAST | | | |UNLOCATED |NO |NONE | |D13 | | |GND | | | | | | | | | | | | -|D14 | |IOBM |IO_L31P_A19_M1CKE_1 |UNUSED | |1 | | | | | | | | | +|D14 |FSB_A<10> |IOB |IO_L31P_A19_M1CKE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | |D15 | | |VCCO_1 | | |1 | | | | |any******| | | | -|D16 | |IOBS |IO_L31N_A18_M1A12_1 |UNUSED | |1 | | | | | | | | | -|E1 |FSB_A<27> |IOB |IO_L46N_M3CLKN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|E2 |FSB_A<24> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|D16 |FSB_A<11> |IOB |IO_L31N_A18_M1A12_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|E1 | |IOBS |IO_L46N_M3CLKN_3 |UNUSED | |3 | | | | | | | | | +|E2 | |IOBM |IO_L46P_M3CLK_3 |UNUSED | |3 | | | | | | | | | |E3 | |IOBS |IO_L54N_M3A11_3 |UNUSED | |3 | | | | | | | | | |E4 | |IOBM |IO_L54P_M3RESET_3 |UNUSED | |3 | | | | | | | | | |E5 | | |VCCAUX | | | | | | | |2.5 | | | | -|E6 | |IOBS |IO_L5N_0 |UNUSED | |0 | | | | | | | | | -|E7 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | | -|E8 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | | +|E6 |FSB_D<8> |IOB |IO_L5N_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|E7 |FSB_D<17> |IOB |IO_L36P_GCLK15_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|E8 |FSB_D<18> |IOB |IO_L36N_GCLK14_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |E9 | | |GND | | | | | | | | | | | | -|E10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | | -|E11 | |IOBS |IO_L64N_SCP4_0 |UNUSED | |0 | | | | | | | | | -|E12 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | | -|E13 | |IOBM |IO_L1P_A25_1 |UNUSED | |1 | | | | | | | | | +|E10 |FSB_D<19> |IOB |IO_L37P_GCLK13_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|E11 |FSB_A<3> |IOB |IO_L64N_SCP4_0 |INPUT |LVCMOS33 |0 | | | |NONE | |UNLOCATED |NO |NONE | +|E12 |FSB_A<5> |IOB |IO_L1N_A24_VREF_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|E13 |FSB_A<4> |IOB |IO_L1P_A25_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | |E14 | | |TDO | | | | | | | | | | | | -|E15 | |IOBM |IO_L34P_A13_M1WE_1 |UNUSED | |1 | | | | | | | | | -|E16 | |IOBS |IO_L34N_A12_M1BA2_1 |UNUSED | |1 | | | | | | | | | -|F1 |FSB_A<23> |IOB |IO_L41N_GCLK26_M3DQ5_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|F2 |FSB_A<22> |IOB |IO_L41P_GCLK27_M3DQ4_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|E15 |FSB_A<21> |IOB |IO_L34P_A13_M1WE_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|E16 |FSB_A<22> |IOB |IO_L34N_A12_M1BA2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|F1 | |IOBS |IO_L41N_GCLK26_M3DQ5_3 |UNUSED | |3 | | | | | | | | | +|F2 | |IOBM |IO_L41P_GCLK27_M3DQ4_3 |UNUSED | |3 | | | | | | | | | |F3 | |IOBS |IO_L53N_M3A12_3 |UNUSED | |3 | | | | | | | | | |F4 | |IOBM |IO_L53P_M3CKE_3 |UNUSED | |3 | | | | | | | | | |F5 | |IOBS |IO_L55N_M3A14_3 |UNUSED | |3 | | | | | | | | | |F6 | |IOBM |IO_L55P_M3A13_3 |UNUSED | |3 | | | | | | | | | -|F7 | |IOBM |IO_L5P_0 |UNUSED | |0 | | | | | | | | | +|F7 |FSB_D<5> |IOB |IO_L5P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |F8 | | |VCCAUX | | | | | | | |2.5 | | | | -|F9 | |IOBM |IO_L40P_0 |UNUSED | |0 | | | | | | | | | -|F10 | |IOBM |IO_L64P_SCP5_0 |UNUSED | |0 | | | | | | | | | +|F9 |FSB_D<25> |IOB |IO_L40P_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | +|F10 |FSB_D<31> |IOB |IO_L64P_SCP5_0 |OUTPUT |LVCMOS33 |0 |8 |SLOW | | | |UNLOCATED |NO |NONE | |F11 | | |VCCAUX | | | | | | | |2.5 | | | | -|F12 | |IOBM |IO_L30P_A21_M1RESET_1 |UNUSED | |1 | | | | | | | | | -|F13 | |IOBM |IO_L32P_A17_M1A8_1 |UNUSED | |1 | | | | | | | | | -|F14 | |IOBS |IO_L32N_A16_M1A9_1 |UNUSED | |1 | | | | | | | | | -|F15 | |IOBM |IO_L35P_A11_M1A7_1 |UNUSED | |1 | | | | | | | | | -|F16 | |IOBS |IO_L35N_A10_M1A2_1 |UNUSED | |1 | | | | | | | | | -|G1 |FSB_A<29> |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|F12 |FSB_A<8> |IOB |IO_L30P_A21_M1RESET_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|F13 |FSB_A<12> |IOB |IO_L32P_A17_M1A8_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|F14 |FSB_A<13> |IOB |IO_L32N_A16_M1A9_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|F15 |FSB_A<23> |IOB |IO_L35P_A11_M1A7_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|F16 |FSB_A<19> |IOB |IO_L35N_A10_M1A2_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|G1 | |IOBS |IO_L40N_M3DQ7_3 |UNUSED | |3 | | | | | | | | | |G2 | | |GND | | | | | | | | | | | | -|G3 |FSB_A<19> |IOB |IO_L40P_M3DQ6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|G4 | | |VCCO_3 | | |3 | | | | |3.30 | | | | +|G3 | |IOBM |IO_L40P_M3DQ6_3 |UNUSED | |3 | | | | | | | | | +|G4 | | |VCCO_3 | | |3 | | | | |any******| | | | |G5 | |IOBS |IO_L51N_M3A4_3 |UNUSED | |3 | | | | | | | | | -|G6 |CLKFB_OUT |IOB |IO_L51P_M3A10_3 |OUTPUT |LVCMOS33 |3 |24 |FAST | | | |UNLOCATED |YES |NONE | +|G6 | |IOBM |IO_L51P_M3A10_3 |UNUSED | |3 | | | | | | | | | |G7 | | |VCCINT | | | | | | | |1.2 | | | | |G8 | | |GND | | | | | | | | | | | | |G9 | | |VCCINT | | | | | | | |1.2 | | | | |G10 | | |VCCAUX | | | | | | | |2.5 | | | | -|G11 | |IOBS |IO_L30N_A20_M1A11_1 |UNUSED | |1 | | | | | | | | | -|G12 | |IOBM |IO_L38P_A5_M1CLK_1 |UNUSED | |1 | | | | | | | | | +|G11 |FSB_A<9> |IOB |IO_L30N_A20_M1A11_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|G12 |FSB_A<24> |IOB |IO_L38P_A5_M1CLK_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | |G13 | | |VCCO_1 | | |1 | | | | |any******| | | | -|G14 | |IOBM |IO_L36P_A9_M1BA0_1 |UNUSED | |1 | | | | | | | | | +|G14 |FSB_A<15> |IOB |IO_L36P_A9_M1BA0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | |G15 | | |GND | | | | | | | | | | | | -|G16 | |IOBS |IO_L36N_A8_M1BA1_1 |UNUSED | |1 | | | | | | | | | -|H1 |FSB_A<26> |IOB |IO_L39N_M3LDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|H2 |FSB_A<25> |IOB |IO_L39P_M3LDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|H3 |CPU_nAS |IOB |IO_L44N_GCLK20_M3A6_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|G16 |FSB_A<16> |IOB |IO_L36N_A8_M1BA1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|H1 | |IOBS |IO_L39N_M3LDQSN_3 |UNUSED | |3 | | | | | | | | | +|H2 | |IOBM |IO_L39P_M3LDQS_3 |UNUSED | |3 | | | | | | | | | +|H3 | |IOBS |IO_L44N_GCLK20_M3A6_3 |UNUSED | |3 | | | | | | | | | |H4 |CLKFB_IN |IOB |IO_L44P_GCLK21_M3A5_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | -|H5 |FSB_A<30> |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|H5 | |IOBS |IO_L43N_GCLK22_IRDY2_M3CASN_3|UNUSED | |3 | | | | | | | | | |H6 | | |VCCAUX | | | | | | | |2.5 | | | | |H7 | | |GND | | | | | | | | | | | | |H8 | | |VCCINT | | | | | | | |1.2 | | | | |H9 | | |GND | | | | | | | | | | | | |H10 | | |VCCINT | | | | | | | |1.2 | | | | -|H11 | |IOBS |IO_L38N_A4_M1CLKN_1 |UNUSED | |1 | | | | | | | | | +|H11 |FSB_A<25> |IOB |IO_L38N_A4_M1CLKN_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | |H12 | | |GND | | | | | | | | | | | | -|H13 | |IOBM |IO_L39P_M1A3_1 |UNUSED | |1 | | | | | | | | | -|H14 | |IOBS |IO_L39N_M1ODT_1 |UNUSED | |1 | | | | | | | | | -|H15 | |IOBM |IO_L37P_A7_M1A0_1 |UNUSED | |1 | | | | | | | | | -|H16 | |IOBS |IO_L37N_A6_M1A1_1 |UNUSED | |1 | | | | | | | | | -|J1 |FSB_A<17> |IOB |IO_L38N_M3DQ3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|J2 | | |VCCO_3 | | |3 | | | | |3.30 | | | | -|J3 |FSB_A<16> |IOB |IO_L38P_M3DQ2_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|H13 |FSB_A<26> |IOB |IO_L39P_M1A3_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|H14 |FSB_A<27> |IOB |IO_L39N_M1ODT_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|H15 |FSB_A<17> |IOB |IO_L37P_A7_M1A0_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|H16 |FSB_A<18> |IOB |IO_L37N_A6_M1A1_1 |INPUT |LVCMOS33 |1 | | | |NONE | |UNLOCATED |NO |NONE | +|J1 | |IOBS |IO_L38N_M3DQ3_3 |UNUSED | |3 | | | | | | | | | +|J2 | | |VCCO_3 | | |3 | | | | |any******| | | | +|J3 | |IOBM |IO_L38P_M3DQ2_3 |UNUSED | |3 | | | | | | | | | |J4 |CLKIN |IOB |IO_L42N_GCLK24_M3LDM_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE | |J5 | | |GND | | | | | | | | | | | | -|J6 |FSB_A<21> |IOB |IO_L43P_GCLK23_M3RASN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|J6 | |IOBM |IO_L43P_GCLK23_M3RASN_3 |UNUSED | |3 | | | | | | | | | |J7 | | |VCCINT | | | | | | | |1.2 | | | | |J8 | | |GND | | | | | | | | | | | | |J9 | | |VCCINT | | | | | | | |1.2 | | | | @@ -164,12 +164,12 @@ Pinout by Pin Number: |J14 | |IOBM |IO_L43P_GCLK5_M1DQ4_1 |UNUSED | |1 | | | | | | | | | |J15 | | |VCCO_1 | | |1 | | | | |any******| | | | |J16 | |IOBS |IO_L43N_GCLK4_M1DQ5_1 |UNUSED | |1 | | | | | | | | | -|K1 |FSB_A<5> |IOB |IO_L37N_M3DQ1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|K2 |FSB_A<14> |IOB |IO_L37P_M3DQ0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|K3 |FSB_A<28> |IOB |IO_L42P_GCLK25_TRDY2_M3UDM_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|K4 | | |VCCO_3 | | |3 | | | | |3.30 | | | | -|K5 |CPUCLKi |IOB |IO_L47P_M3A0_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|K6 |FSB_A<18> |IOB |IO_L47N_M3A1_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|K1 | |IOBS |IO_L37N_M3DQ1_3 |UNUSED | |3 | | | | | | | | | +|K2 | |IOBM |IO_L37P_M3DQ0_3 |UNUSED | |3 | | | | | | | | | +|K3 | |IOBM |IO_L42P_GCLK25_TRDY2_M3UDM_3 |UNUSED | |3 | | | | | | | | | +|K4 | | |VCCO_3 | | |3 | | | | |any******| | | | +|K5 | |IOBM |IO_L47P_M3A0_3 |UNUSED | |3 | | | | | | | | | +|K6 | |IOBS |IO_L47N_M3A1_3 |UNUSED | |3 | | | | | | | | | |K7 | | |GND | | | | | | | | | | | | |K8 | | |VCCINT | | | | | | | |1.2 | | | | |K9 | | |GND | | | | | | | | | | | | @@ -180,11 +180,11 @@ Pinout by Pin Number: |K14 | |IOBS |IO_L41N_GCLK8_M1CASN_1 |UNUSED | |1 | | | | | | | | | |K15 | |IOBM |IO_L44P_A3_M1DQ6_1 |UNUSED | |1 | | | | | | | | | |K16 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | | -|L1 |FSB_A<11> |IOB |IO_L36N_M3DQ9_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|L1 | |IOBS |IO_L36N_M3DQ9_3 |UNUSED | |3 | | | | | | | | | |L2 | | |GND | | | | | | | | | | | | -|L3 |FSB_A<4> |IOB |IO_L36P_M3DQ8_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|L4 |FSB_A<31> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|L5 |FSB_A<20> |IOB |IO_L45N_M3ODT_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|L3 | |IOBM |IO_L36P_M3DQ8_3 |UNUSED | |3 | | | | | | | | | +|L4 | |IOBM |IO_L45P_M3A3_3 |UNUSED | |3 | | | | | | | | | +|L5 | |IOBS |IO_L45N_M3ODT_3 |UNUSED | |3 | | | | | | | | | |L6 | | |VCCAUX | | | | | | | |2.5 | | | | |L7 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | | |L8 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | | @@ -196,11 +196,11 @@ Pinout by Pin Number: |L14 | |IOBM |IO_L47P_FWE_B_M1DQ0_1 |UNUSED | |1 | | | | | | | | | |L15 | | |GND | | | | | | | | | | | | |L16 | |IOBS |IO_L47N_LDC_M1DQ1_1 |UNUSED | |1 | | | | | | | | | -|M1 |FSB_A<1> |IOB |IO_L35N_M3DQ11_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|M2 |FSB_A<2> |IOB |IO_L35P_M3DQ10_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|M3 |FSB_A<6> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|M4 |FSB_A<8> |IOB |IO_L1P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|M5 |FSB_A<15> |IOB |IO_L2P_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|M1 | |IOBS |IO_L35N_M3DQ11_3 |UNUSED | |3 | | | | | | | | | +|M2 | |IOBM |IO_L35P_M3DQ10_3 |UNUSED | |3 | | | | | | | | | +|M3 | |IOBS |IO_L1N_VREF_3 |UNUSED | |3 | | | | | | | | | +|M4 | |IOBM |IO_L1P_3 |UNUSED | |3 | | | | | | | | | +|M5 | |IOBM |IO_L2P_3 |UNUSED | |3 | | | | | | | | | |M6 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | | |M7 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | | |M8 | | |GND | | | | | | | | | | | | @@ -212,10 +212,10 @@ Pinout by Pin Number: |M14 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | | |M15 | |IOBM |IO_L46P_FCS_B_M1DQ2_1 |UNUSED | |1 | | | | | | | | | |M16 | |IOBS |IO_L46N_FOE_B_M1DQ3_1 |UNUSED | |1 | | | | | | | | | -|N1 |FSB_A<10> |IOB |IO_L34N_M3UDQSN_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|N2 | | |VCCO_3 | | |3 | | | | |3.30 | | | | -|N3 |FSB_A<13> |IOB |IO_L34P_M3UDQS_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|N4 |FSB_A<0> |IOB |IO_L2N_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|N1 | |IOBS |IO_L34N_M3UDQSN_3 |UNUSED | |3 | | | | | | | | | +|N2 | | |VCCO_3 | | |3 | | | | |any******| | | | +|N3 | |IOBM |IO_L34P_M3UDQS_3 |UNUSED | |3 | | | | | | | | | +|N4 | |IOBS |IO_L2N_3 |UNUSED | |3 | | | | | | | | | |N5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | | |N6 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | | |N7 | | |VCCO_2 | | |2 | | | | |any******| | | | @@ -228,8 +228,8 @@ Pinout by Pin Number: |N14 | |IOBM |IO_L45P_A1_M1LDQS_1 |UNUSED | |1 | | | | | | | | | |N15 | | |VCCO_1 | | |1 | | | | |any******| | | | |N16 | |IOBS |IO_L45N_A0_M1LDQSN_1 |UNUSED | |1 | | | | | | | | | -|P1 |FSB_A<7> |IOB |IO_L33N_M3DQ13_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|P2 |FSB_A<12> |IOB |IO_L33P_M3DQ12_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|P1 | |IOBS |IO_L33N_M3DQ13_3 |UNUSED | |3 | | | | | | | | | +|P2 | |IOBM |IO_L33P_M3DQ12_3 |UNUSED | |3 | | | | | | | | | |P3 | | |GND | | | | | | | | | | | | |P4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | | |P5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | | @@ -244,8 +244,8 @@ Pinout by Pin Number: |P14 | | |SUSPEND | | | | | | | | | | | | |P15 | |IOBM |IO_L48P_HDC_M1DQ8_1 |UNUSED | |1 | | | | | | | | | |P16 | |IOBS |IO_L48N_M1DQ9_1 |UNUSED | |1 | | | | | | | | | -|R1 |FSB_A<9> |IOB |IO_L32N_M3DQ15_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | -|R2 |FSB_A<3> |IOB |IO_L32P_M3DQ14_3 |INPUT |LVCMOS33 |3 | | | |NONE | |UNLOCATED |NO |NONE | +|R1 | |IOBS |IO_L32N_M3DQ15_3 |UNUSED | |3 | | | | | | | | | +|R2 | |IOBM |IO_L32P_M3DQ14_3 |UNUSED | |3 | | | | | | | | | |R3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | | |R4 | | |VCCO_2 | | |2 | | | | |any******| | | | |R5 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | | diff --git a/fpga/WarpLC_par.xrpt b/fpga/WarpLC_par.xrpt index 9552a2c..e1ad349 100644 --- a/fpga/WarpLC_par.xrpt +++ b/fpga/WarpLC_par.xrpt @@ -1,18 +1,18 @@ - + - +
- + @@ -36,35 +36,36 @@
- - + + - + - - + +
+ - +
- - + + - - + +
@@ -79,22 +80,22 @@ - + - - - + + + - + - - - + + +
@@ -135,80 +136,157 @@ - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + @@ -220,17 +298,10 @@ - - + - - + - - - - - @@ -250,21 +321,35 @@ - + - + + - + + + + + + + - + + - + + + + + + + @@ -272,23 +357,37 @@ - + + - + + + + + + + - + - + + - + + + + + + + @@ -296,134 +395,195 @@ - + + - + + + + + + + - + - + + - + + + + + + - + + - + + + + + + - + + - + + + + + + - - + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + @@ -431,10 +591,17 @@ - + + - + + + + + + + @@ -442,51 +609,49 @@ - + + - + + + + + + - + + - + + + + + + - - + - - + - - - - - - + - - + - - + - - - - - @@ -494,57 +659,99 @@ - + + - + + + + + + + - + + - + + + + + + + - + - + + - + + + + + + + - + + - + + + + + + + - + - + + - + + + + + + + - + + - + + + + + + + @@ -552,10 +759,16 @@ - + + - + + + + + + @@ -565,36 +778,30 @@ - + + - + + + + + + - - + - - + - - - - - - + - - + - - - - @@ -617,24 +824,45 @@ - + + - + + + + + + + - + + - + + + + + + + - + + - + + + + + + + @@ -642,31 +870,56 @@ - + + - + + + + + + + - + + - + + + + + + - + + - + + + + + + - + + - + + + + + + @@ -674,43 +927,43 @@ - + + - + + + + + + - + + - + + + + + + - - + - - + - - - - - - + - - + - - - - @@ -742,10 +995,17 @@ - + + - + + + + + + + @@ -754,17 +1014,31 @@ - + + - + + + + + + + - + + - + + + + + + + @@ -773,74 +1047,92 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + - - + - - - - - + @@ -851,17 +1143,10 @@ - - + - - + - - - - - @@ -884,17 +1169,29 @@ - + + - + + + + + + - + + - + + + + + + @@ -904,10 +1201,16 @@ - + + - + + + + + + @@ -915,49 +1218,37 @@ - + + - + + + + + + - - + - - + - - - - - - + - - + - - - - - - + - - + - - - - @@ -974,16 +1265,10 @@ - - + - - + - - - - @@ -1010,10 +1295,16 @@ - + + - + + + + + + @@ -1021,63 +1312,75 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - + - - + - - - - @@ -1098,16 +1401,10 @@ - - + - - + - - - - @@ -1171,74 +1468,44 @@ - - + - - + - - - - - - + - - + - - - - - - + - - + - - - - - + - - + - - + - - - - - - + - - + - - - - @@ -1301,16 +1568,10 @@ - - + - - + - - - - @@ -1318,42 +1579,24 @@ - - + - - + - - - - - - + - - + - - - - - - + - - + - - - - @@ -1424,68 +1667,38 @@ - - + - - + - - - - - - + - - + - - - - - - + - - + - - - - - - + - - + - - - - - - + - - + - - - - @@ -1563,48 +1776,30 @@ - - + - - + - - - - - + - - + - - + - - - - - - + - - + - - - - @@ -1686,29 +1881,17 @@ - - + - - + - - - - - - + - - + - - - - @@ -1801,29 +1984,17 @@ - - + - - + - - - - - - + - - + - - - - @@ -2032,14 +2203,14 @@ - +
- + @@ -2063,37 +2234,37 @@
- - + + - + - - + +
- - + + - - - - + + + + - - + + @@ -2101,25 +2272,25 @@ - + - + - - - - + + + + - - - - + + + +
- + @@ -2135,7 +2306,7 @@
- +
diff --git a/fpga/WarpLC_preroute.twr b/fpga/WarpLC_preroute.twr index 4af12de..3d9dcbe 100644 --- a/fpga/WarpLC_preroute.twr +++ b/fpga/WarpLC_preroute.twr @@ -1,9 +1,9 @@ -------------------------------------------------------------------------------- -Release 14.7 Trace (nt) +Release 14.7 Trace (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n -3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr +C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 +-n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf Design file: WarpLC_map.ncd @@ -16,6 +16,69 @@ Environment Variable Effect NONE No environment variables were set -------------------------------------------------------------------------------- +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<27> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<27>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<26> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<26>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<25> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<25>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<24> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<24>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<23> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<23>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<22> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<22>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<21> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<21>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<20> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<20>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<19> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<19>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<18> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<18>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<17> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<17>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<16> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<16>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<15> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<15>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<14> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<14>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<13> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<13>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<12> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<12>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<11> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<11>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<10> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<10>" OFFSET = IN 12 ns + VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<9> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<9>" OFFSET = IN 12 ns VALID + 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<8> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<8>" OFFSET = IN 12 ns VALID + 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis +WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<7> +WARNING:Timing:3225 - Timing constraint COMP "FSB_A<7>" OFFSET = IN 12 ns VALID + 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the @@ -29,67 +92,46 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on please see the device datasheet. ================================================================================ -Timing constraint: NET "FSBCLK" PERIOD = 10 ns HIGH 50%; +Timing constraint: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) - Minimum period is 1.866ns. + Minimum period is 10.000ns. -------------------------------------------------------------------------------- -Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%; +Component Switching Limit Checks: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%; -------------------------------------------------------------------------------- -Slack: 8.134ns (period - min period limit) - Period: 10.000ns - Min period limit: 1.866ns (535.906MHz) (Tickper) - Physical resource: OUTt_OBUF/CLK0 - Logical resource: OUTt/CLK0 - Location pin: ILOGIC_X0Y5.CLK0 - Clock network: FSBCLK +Slack: 13.948ns (period - min period limit) + Period: 15.000ns + Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax)) + Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0 + Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0 + Location pin: PLL_ADV_X0Y1.CLKOUT0 + Clock network: cg/pll/clkout0 +-------------------------------------------------------------------------------- +Slack: 20.000ns (period - (min low pulse limit / (low pulse / period))) + Period: 30.000ns + Low pulse: 15.000ns + Low pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50) + Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 + Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 + Location pin: PLL_ADV_X0Y1.CLKIN1 + Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK +-------------------------------------------------------------------------------- +Slack: 20.000ns (period - (min high pulse limit / (high pulse / period))) + Period: 30.000ns + High pulse: 15.000ns + High pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50) + Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 + Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1 + Location pin: PLL_ADV_X0Y1.CLKIN1 + Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK -------------------------------------------------------------------------------- ================================================================================ -Timing constraint: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; -For more information, see Period Analysis in the Timing Closure User Guide (UG612). - - 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 component switching limit errors) - Minimum period is 5.000ns. --------------------------------------------------------------------------------- - -Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; --------------------------------------------------------------------------------- -Slack: 15.000ns (period - (min low pulse limit / (low pulse / period))) - Period: 20.000ns - Low pulse: 10.000ns - Low pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100) - Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Location pin: PLL_ADV_X0Y1.CLKIN1 - Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK --------------------------------------------------------------------------------- -Slack: 15.000ns (period - (min high pulse limit / (high pulse / period))) - Period: 20.000ns - High pulse: 10.000ns - High pulse limit: 2.500ns (Tdcmpw_CLKIN_50_100) - Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Location pin: PLL_ADV_X0Y1.CLKIN1 - Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK --------------------------------------------------------------------------------- -Slack: 17.780ns (period - min period limit) - Period: 20.000ns - Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKIN(Finmax)) - Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKIN1 - Location pin: PLL_ADV_X0Y1.CLKIN1 - Clock network: instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: PERIOD analysis for net "instance_name/clkfbout" derived -from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected -to 20 nS HIGH 10 nS +Timing constraint: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" +TS_CLKIN HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints @@ -97,449 +139,1061 @@ For more information, see Period Analysis in the Timing Closure User Guide (UG61 Minimum period is 2.666ns. -------------------------------------------------------------------------------- -Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from - NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; - duty cycle corrected to 20 nS HIGH 10 nS - +Component Switching Limit Checks: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%; -------------------------------------------------------------------------------- -Slack: 17.334ns (period - min period limit) - Period: 20.000ns +Slack: 27.334ns (period - min period limit) + Period: 30.000ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) - Physical resource: instance_name/clkfbout_bufg/I0 - Logical resource: instance_name/clkfbout_bufg/I0 + Physical resource: cg/pll/clkfbout_bufg/I0 + Logical resource: cg/pll/clkfbout_bufg/I0 Location pin: BUFGMUX_X2Y3.I0 - Clock network: instance_name/clkfbout + Clock network: cg/pll/clkfbout -------------------------------------------------------------------------------- -Slack: 17.751ns (period - min period limit) - Period: 20.000ns +Slack: 27.751ns (period - min period limit) + Period: 30.000ns Min period limit: 2.249ns (444.642MHz) (Tockper) Physical resource: CLKFB_OUT_OBUF/CLK0 - Logical resource: instance_name/clkfbout_oddr/CK0 - Location pin: OLOGIC_X0Y7.CLK0 - Clock network: instance_name/clkfb_bufg_out + Logical resource: cg/pll/clkfbout_oddr/CK0 + Location pin: OLOGIC_X1Y63.CLK0 + Clock network: cg/pll/clkfb_bufg_out -------------------------------------------------------------------------------- -Slack: 17.780ns (period - min period limit) - Period: 20.000ns - Min period limit: 2.220ns (450.450MHz) (Tpllper_CLKFB) - Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT - Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKFBOUT - Location pin: PLL_ADV_X0Y1.CLKFBOUT - Clock network: instance_name/clkfbout +Slack: 27.960ns (period - min period limit) + Period: 30.000ns + Min period limit: 2.040ns (490.196MHz) (Tockper) + Physical resource: CLKFB_OUT_OBUF/CLK1 + Logical resource: cg/pll/clkfbout_oddr/CK1 + Location pin: OLOGIC_X1Y63.CLK1 + Clock network: cg/pll/clkfb_bufg_out -------------------------------------------------------------------------------- ================================================================================ -Timing constraint: PERIOD analysis for net "instance_name/clkout0" derived from - NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS - +Timing constraint: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN +/ 2 HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). - 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 component switching limit errors) - Minimum period is 2.666ns. + 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 3.649ns. -------------------------------------------------------------------------------- -Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from - NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; - divided by 2.00 to 10 nS +Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y62.D1), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.351ns (requirement - (data path - clock path skew + uncertainty)) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLK_inst (FF) + Requirement: 15.000ns + Data Path Delay: 3.533ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 0.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.116ns + + Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y63.DQ Tcko 0.476 cg/CPUCLKr + cg/CPUCLKr + SLICE_X14Y63.D4 net (fanout=4) e 0.491 cg/CPUCLKr + SLICE_X14Y63.D Tilo 0.235 cg/CPUCLKr + l2pre/CPUCLKr_INV_15_o1_INV_0 + OLOGIC_X1Y62.D1 net (fanout=3) e 1.365 l2pre/CPUCLKr_INV_15_o + OLOGIC_X1Y62.CLK0 Todck 0.966 CPUCLK_OBUF + cg/CPUCLK_inst + ------------------------------------------------- --------------------------- + Total 3.533ns (1.677ns logic, 1.856ns route) + (47.5% logic, 52.5% route) -------------------------------------------------------------------------------- -Slack: 7.334ns (period - min period limit) - Period: 10.000ns + +Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y62.D2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.751ns (requirement - (data path - clock path skew + uncertainty)) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLK_inst (FF) + Requirement: 15.000ns + Data Path Delay: 3.133ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 0.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.116ns + + Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y63.DQ Tcko 0.476 cg/CPUCLKr + cg/CPUCLKr + SLICE_X14Y63.D4 net (fanout=4) e 0.491 cg/CPUCLKr + SLICE_X14Y63.D Tilo 0.235 cg/CPUCLKr + l2pre/CPUCLKr_INV_15_o1_INV_0 + OLOGIC_X1Y62.D2 net (fanout=3) e 1.100 l2pre/CPUCLKr_INV_15_o + OLOGIC_X1Y62.CLK0 Todck 0.831 CPUCLK_OBUF + cg/CPUCLK_inst + ------------------------------------------------- --------------------------- + Total 3.133ns (1.542ns logic, 1.591ns route) + (49.2% logic, 50.8% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D1), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.451ns (requirement - (data path - clock path skew + uncertainty)) + Source: cg/CPUCLKr (FF) + Destination: cg/FPUCLK_inst (FF) + Requirement: 15.000ns + Data Path Delay: 2.433ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 0.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.116ns + + Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/FPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y63.DQ Tcko 0.476 cg/CPUCLKr + cg/CPUCLKr + OLOGIC_X11Y63.D1 net (fanout=4) e 0.991 cg/CPUCLKr + OLOGIC_X11Y63.CLK0 Todck 0.966 FPUCLK_OBUF + cg/FPUCLK_inst + ------------------------------------------------- --------------------------- + Total 2.433ns (1.442ns logic, 0.991ns route) + (59.3% logic, 40.7% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; +-------------------------------------------------------------------------------- + +Paths for end point cg/CPUCLKr (SLICE_X14Y63.SR), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.577ns (requirement - (clock path skew + uncertainty - data path)) + Source: cg/CPUCLKr (FF) + Destination: cg/CPUCLKr (FF) + Requirement: 0.000ns + Data Path Delay: 0.577ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 15.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/CPUCLKr + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y63.DQ Tcko 0.200 cg/CPUCLKr + cg/CPUCLKr + SLICE_X14Y63.SR net (fanout=4) e 0.376 cg/CPUCLKr + SLICE_X14Y63.CLK Tcksr (-Th) -0.001 cg/CPUCLKr + cg/CPUCLKr + ------------------------------------------------- --------------------------- + Total 0.577ns (0.201ns logic, 0.376ns route) + (34.8% logic, 65.2% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D2), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.346ns (requirement - (clock path skew + uncertainty - data path)) + Source: cg/CPUCLKr (FF) + Destination: cg/FPUCLK_inst (FF) + Requirement: 0.000ns + Data Path Delay: 1.346ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 15.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/FPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y63.DQ Tcko 0.200 cg/CPUCLKr + cg/CPUCLKr + OLOGIC_X11Y63.D2 net (fanout=4) e 0.991 cg/CPUCLKr + OLOGIC_X11Y63.CLK0 Tockd (-Th) -0.155 FPUCLK_OBUF + cg/FPUCLK_inst + ------------------------------------------------- --------------------------- + Total 1.346ns (0.355ns logic, 0.991ns route) + (26.4% logic, 73.6% route) + +-------------------------------------------------------------------------------- + +Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D1), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.521ns (requirement - (clock path skew + uncertainty - data path)) + Source: cg/CPUCLKr (FF) + Destination: cg/FPUCLK_inst (FF) + Requirement: 0.000ns + Data Path Delay: 1.521ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: FSBCLK rising at 15.000ns + Destination Clock: FSBCLK rising at 15.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/FPUCLK_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y63.DQ Tcko 0.200 cg/CPUCLKr + cg/CPUCLKr + OLOGIC_X11Y63.D1 net (fanout=4) e 0.991 cg/CPUCLKr + OLOGIC_X11Y63.CLK0 Tockd (-Th) -0.330 FPUCLK_OBUF + cg/FPUCLK_inst + ------------------------------------------------- --------------------------- + Total 1.521ns (0.530ns logic, 0.991ns route) + (34.8% logic, 65.2% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 11.430ns (period - min period limit) + Period: 15.000ns + Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax)) + Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK + Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK + Location pin: RAMB8_X1Y31.CLKAWRCLK + Clock network: FSBCLK +-------------------------------------------------------------------------------- +Slack: 11.430ns (period - min period limit) + Period: 15.000ns + Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax)) + Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK + Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK + Location pin: RAMB8_X1Y31.CLKBRDCLK + Clock network: FSBCLK +-------------------------------------------------------------------------------- +Slack: 12.334ns (period - min period limit) + Period: 15.000ns Min period limit: 2.666ns (375.094MHz) (Tbcper_I) - Physical resource: instance_name/clkout1_buf/I0 - Logical resource: instance_name/clkout1_buf/I0 + Physical resource: cg/pll/clkout1_buf/I0 + Logical resource: cg/pll/clkout1_buf/I0 Location pin: BUFGMUX_X3Y13.I0 - Clock network: instance_name/clkout0 --------------------------------------------------------------------------------- -Slack: 8.948ns (period - min period limit) - Period: 10.000ns - Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax)) - Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0 - Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0 - Location pin: PLL_ADV_X0Y1.CLKOUT0 - Clock network: instance_name/clkout0 --------------------------------------------------------------------------------- -Slack: 310.000ns (max period limit - period) - Period: 10.000ns - Max period limit: 320.000ns (3.125MHz) (Tpllper_CLKOUT(Foutmin)) - Physical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0 - Logical resource: instance_name/pll_base_inst/PLL_ADV/CLKOUT0 - Location pin: PLL_ADV_X0Y1.CLKOUT0 - Clock network: instance_name/clkout0 + Clock network: cg/pll/clkout0 -------------------------------------------------------------------------------- ================================================================================ -Timing constraint: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP +Timing constraint: COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 9.880ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 0.120ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: CPU_nAS (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 10.000ns - Data Path Delay: 4.575ns (Levels of Logic = 1) - Clock Path Delay: -4.891ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: CPU_nAS to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N4.I Tiopi 1.557 CPU_nAS - CPU_nAS - CPU_nAS_IBUF - ProtoComp0.IMUX.1 - ILOGIC_X0Y5.SR net (fanout=1) e 2.043 CPU_nAS_IBUF - ILOGIC_X0Y5.CLK0 Tisrck 0.975 OUTt_OBUF - OUTt - ------------------------------------------------- --------------------------- - Total 4.575ns (2.532ns logic, 2.043ns route) - (55.3% logic, 44.7% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - instance_name/clkin1_buf - ProtoComp0.IMUX.3 - BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 instance_name/pll_base_inst/PLL_ADV - instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0 - BUFGMUX_X3Y13.O Tgi0o 0.197 instance_name/clkout1_buf - instance_name/clkout1_buf - ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK - ------------------------------------------------- --------------------------- - Total -4.891ns (-6.970ns logic, 2.079ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 6.650ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: CPU_nAS (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 1.000ns - Data Path Delay: 2.965ns (Levels of Logic = 1) - Clock Path Delay: -3.099ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: CPU_nAS to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - N4.I Tiopi 0.763 CPU_nAS - CPU_nAS - CPU_nAS_IBUF - ProtoComp0.IMUX.1 - ILOGIC_X0Y5.SR net (fanout=1) e 2.043 CPU_nAS_IBUF - ILOGIC_X0Y5.CLK0 Ticksr (-Th) -0.159 OUTt_OBUF - OUTt - ------------------------------------------------- --------------------------- - Total 2.965ns (0.922ns logic, 2.043ns route) - (31.1% logic, 68.9% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - instance_name/clkin1_buf - ProtoComp0.IMUX.3 - BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 instance_name/pll_base_inst/PLL_ADV - instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0 - BUFGMUX_X3Y13.O Tgi0o 0.063 instance_name/clkout1_buf - instance_name/clkout1_buf - ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.099ns (-5.178ns logic, 2.079ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP -"CLKIN"; -For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - - 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors) - Minimum allowable offset is 8.814ns. --------------------------------------------------------------------------------- - -Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 1.186ns (requirement - (data path - clock path - clock arrival + uncertainty)) - Source: INt (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 10.000ns - Data Path Delay: 3.509ns (Levels of Logic = 2) - Clock Path Delay: -4.891ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Maximum Data Path at Slow Process Corner: INt to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M4.I Tiopi 1.557 INt - INt - INt_IBUF - ProtoComp0.IMUX.2 - ILOGIC_X0Y5.D net (fanout=1) e 0.229 CPU_nAS_INt_AND_1_o_norst - ILOGIC_X0Y5.CLK0 Tidock 1.723 OUTt_OBUF - ProtoComp3.D2OFFBYP_SRC - OUTt - ------------------------------------------------- --------------------------- - Total 3.509ns (3.280ns logic, 0.229ns route) - (93.5% logic, 6.5% route) - - Minimum Clock Path at Slow Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.902 CLKIN - CLKIN - instance_name/clkin1_buf - ProtoComp0.IMUX.3 - BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 instance_name/pll_base_inst/PLL_ADV - instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0 - BUFGMUX_X3Y13.O Tgi0o 0.197 instance_name/clkout1_buf - instance_name/clkout1_buf - ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK - ------------------------------------------------- --------------------------- - Total -4.891ns (-6.970ns logic, 2.079ns route) - --------------------------------------------------------------------------------- - -Hold Paths: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN"; --------------------------------------------------------------------------------- - -Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 5.307ns (requirement - (clock path + clock arrival + uncertainty - data path)) - Source: INt (PAD) - Destination: OUTt (FF) - Destination Clock: FSBCLK rising at 0.000ns - Requirement: 1.000ns - Data Path Delay: 1.622ns (Levels of Logic = 2) - Clock Path Delay: -3.099ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns - - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns - - Minimum Data Path at Fast Process Corner: INt to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - M4.I Tiopi 0.763 INt - INt - INt_IBUF - ProtoComp0.IMUX.2 - ILOGIC_X0Y5.D net (fanout=1) e 0.229 CPU_nAS_INt_AND_1_o_norst - ILOGIC_X0Y5.CLK0 Tiockd (-Th) -0.630 OUTt_OBUF - ProtoComp3.D2OFFBYP_SRC - OUTt - ------------------------------------------------- --------------------------- - Total 1.622ns (1.393ns logic, 0.229ns route) - (85.9% logic, 14.1% route) - - Maximum Clock Path at Fast Process Corner: CLKIN to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - J4.I Tiopi 0.367 CLKIN - CLKIN - instance_name/clkin1_buf - ProtoComp0.IMUX.3 - BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 instance_name/pll_base_inst/PLL_ADV - instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0 - BUFGMUX_X3Y13.O Tgi0o 0.063 instance_name/clkout1_buf - instance_name/clkout1_buf - ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK - ------------------------------------------------- --------------------------- - Total -3.099ns (-5.178ns logic, 2.079ns route) - --------------------------------------------------------------------------------- - -================================================================================ -Timing constraint: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN"; -For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). - - 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. - Minimum allowable offset is 1.412ns. -------------------------------------------------------------------------------- -Paths for end point OUTt (M3.PAD), 1 path --------------------------------------------------------------------------------- -Slack (slowest paths): 2.588ns (requirement - (clock arrival + clock path + data path + uncertainty)) - Source: OUTt (FF) - Destination: OUTt (PAD) - Source Clock: FSBCLK rising at 0.000ns - Requirement: 4.000ns - Data Path Delay: 6.068ns (Levels of Logic = 1) - Clock Path Delay: -5.070ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns +================================================================================ +Timing constraint: COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 9.606ns. +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 2.394ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: FSB_A<6> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 4.419ns (Levels of Logic = 1) + Clock Path Delay: -4.891ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns - Maximum Clock Path at Slow Process Corner: CLKIN to OUTt + Maximum Data Path at Slow Process Corner: FSB_A<6> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + B15.I Tiopi 1.557 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + RAMB8_X1Y31.ADDRBRDADDR9 net (fanout=13) e 2.462 FSB_A_6_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.419ns (1.957ns logic, 2.462ns route) + (44.3% logic, 55.7% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - J4.I Tiopi 1.037 CLKIN + J4.I Tiopi 0.902 CLKIN CLKIN - instance_name/clkin1_buf - ProtoComp0.IMUX.3 - BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.585 instance_name/pll_base_inst/PLL_ADV - instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0 - BUFGMUX_X3Y13.O Tgi0o 0.209 instance_name/clkout1_buf - instance_name/clkout1_buf - ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK ------------------------------------------------- --------------------------- - Total -5.070ns (-7.149ns logic, 2.079ns route) - - Maximum Data Path at Slow Process Corner: OUTt to OUTt - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - ILOGIC_X0Y5.Q4 Tickq 1.778 OUTt_OBUF - OUTt - M3.O net (fanout=1) e 2.308 OUTt_OBUF - M3.PAD Tioop 1.982 OUTt - OUTt_OBUF - OUTt - ------------------------------------------------- --------------------------- - Total 6.068ns (3.760ns logic, 2.308ns route) - (62.0% logic, 38.0% route) + Total -4.891ns (-6.970ns logic, 2.079ns route) -------------------------------------------------------------------------------- -Fastest Paths: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN"; +Hold Paths: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; -------------------------------------------------------------------------------- -Paths for end point OUTt (M3.PAD), 1 path +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path -------------------------------------------------------------------------------- -Delay (fastest paths): 0.213ns (clock arrival + clock path + data path - uncertainty) - Source: OUTt (FF) - Destination: OUTt (PAD) - Source Clock: FSBCLK rising at 0.000ns - Data Path Delay: 3.663ns (Levels of Logic = 1) - Clock Path Delay: -3.036ns (Levels of Logic = 4) - Clock Uncertainty: 0.414ns +Slack (hold path): 5.962ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: FSB_A<6> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.159ns (Levels of Logic = 1) + Clock Path Delay: -3.099ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns - Clock Uncertainty: 0.414ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.287ns - Phase Error (PE): 0.267ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns - Minimum Clock Path at Fast Process Corner: CLKIN to OUTt + Minimum Data Path at Fast Process Corner: FSB_A<6> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + B15.I Tiopi 0.763 FSB_A<6> + FSB_A<6> + FSB_A_6_IBUF + ProtoComp0.IMUX.24 + RAMB8_X1Y31.ADDRBRDADDR9 net (fanout=13) e 2.462 FSB_A_6_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 3.159ns (0.697ns logic, 2.462ns route) + (22.1% logic, 77.9% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - J4.I Tiopi 0.321 CLKIN + J4.I Tiopi 0.367 CLKIN CLKIN - instance_name/clkin1_buf - ProtoComp0.IMUX.3 - BUFIO2_X0Y23.I net (fanout=1) e 0.000 instance_name/clkin1 - BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 - PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK - PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.617 instance_name/pll_base_inst/PLL_ADV - instance_name/pll_base_inst/PLL_ADV - BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 instance_name/clkout0 - BUFGMUX_X3Y13.O Tgi0o 0.059 instance_name/clkout1_buf - instance_name/clkout1_buf - ILOGIC_X0Y5.CLK0 net (fanout=1) e 1.574 FSBCLK + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK ------------------------------------------------- --------------------------- - Total -3.036ns (-5.115ns logic, 2.079ns route) + Total -3.099ns (-5.178ns logic, 2.079ns route) - Minimum Data Path at Fast Process Corner: OUTt to OUTt +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 9.777ns. +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 2.223ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: FSB_A<5> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 4.590ns (Levels of Logic = 1) + Clock Path Delay: -4.891ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Data Path at Slow Process Corner: FSB_A<5> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E12.I Tiopi 1.557 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + RAMB8_X1Y31.ADDRBRDADDR8 net (fanout=13) e 2.633 FSB_A_5_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.590ns (1.957ns logic, 2.633ns route) + (42.6% logic, 57.4% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- - ILOGIC_X0Y5.Q4 Tickq 0.656 OUTt_OBUF - OUTt - M3.O net (fanout=1) e 2.308 OUTt_OBUF - M3.PAD Tioop 0.699 OUTt - OUTt_OBUF - OUTt + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK ------------------------------------------------- --------------------------- - Total 3.663ns (1.355ns logic, 2.308ns route) - (37.0% logic, 63.0% route) + Total -4.891ns (-6.970ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 6.133ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: FSB_A<5> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.330ns (Levels of Logic = 1) + Clock Path Delay: -3.099ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<5> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E12.I Tiopi 0.763 FSB_A<5> + FSB_A<5> + FSB_A_5_IBUF + ProtoComp0.IMUX.23 + RAMB8_X1Y31.ADDRBRDADDR8 net (fanout=13) e 2.633 FSB_A_5_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 3.330ns (0.697ns logic, 2.633ns route) + (20.9% logic, 79.1% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.099ns (-5.178ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 9.445ns. +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 2.555ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: FSB_A<4> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 4.258ns (Levels of Logic = 1) + Clock Path Delay: -4.891ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Data Path at Slow Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E13.I Tiopi 1.557 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) e 2.301 FSB_A_4_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.258ns (1.957ns logic, 2.301ns route) + (46.0% logic, 54.0% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.891ns (-6.970ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 5.801ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: FSB_A<4> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.998ns (Levels of Logic = 1) + Clock Path Delay: -3.099ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + E13.I Tiopi 0.763 FSB_A<4> + FSB_A<4> + FSB_A_4_IBUF + ProtoComp0.IMUX.22 + RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) e 2.301 FSB_A_4_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 2.998ns (0.697ns logic, 2.301ns route) + (23.2% logic, 76.8% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.099ns (-5.178ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 9.381ns. +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 2.619ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: FSB_A<3> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 4.194ns (Levels of Logic = 1) + Clock Path Delay: -4.891ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Data Path at Slow Process Corner: FSB_A<3> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + D12.I Tiopi 1.557 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + RAMB8_X1Y31.ADDRBRDADDR6 net (fanout=13) e 2.237 FSB_A_3_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.194ns (1.957ns logic, 2.237ns route) + (46.7% logic, 53.3% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.891ns (-6.970ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 5.737ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: FSB_A<3> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.934ns (Levels of Logic = 1) + Clock Path Delay: -3.099ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<3> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + D12.I Tiopi 0.763 FSB_A<3> + FSB_A<3> + FSB_A_3_IBUF + ProtoComp0.IMUX.21 + RAMB8_X1Y31.ADDRBRDADDR6 net (fanout=13) e 2.237 FSB_A_3_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 2.934ns (0.697ns logic, 2.237ns route) + (23.8% logic, 76.2% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.099ns (-5.178ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"CLKIN"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 9.717ns. +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 2.283ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: FSB_A<2> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 4.530ns (Levels of Logic = 1) + Clock Path Delay: -4.891ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Maximum Data Path at Slow Process Corner: FSB_A<2> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + D11.I Tiopi 1.557 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + RAMB8_X1Y31.ADDRBRDADDR5 net (fanout=13) e 2.573 FSB_A_2_IBUF + RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 4.530ns (1.957ns logic, 2.573ns route) + (43.2% logic, 56.8% route) + + Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.902 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -4.891ns (-6.970ns logic, 2.079ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +-------------------------------------------------------------------------------- + +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 6.073ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: FSB_A<2> (PAD) + Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM) + Destination Clock: FSBCLK rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.270ns (Levels of Logic = 1) + Clock Path Delay: -3.099ns (Levels of Logic = 4) + Clock Uncertainty: 0.296ns + + Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.221ns + Phase Error (PE): 0.182ns + + Minimum Data Path at Fast Process Corner: FSB_A<2> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ----------------------------------------------------- ------------------- + D11.I Tiopi 0.763 FSB_A<2> + FSB_A<2> + FSB_A_2_IBUF + ProtoComp0.IMUX.20 + RAMB8_X1Y31.ADDRBRDADDR5 net (fanout=13) e 2.573 FSB_A_2_IBUF + RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + ----------------------------------------------------- --------------------------- + Total 3.270ns (0.697ns logic, 2.573ns route) + (21.3% logic, 78.7% route) + + Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + J4.I Tiopi 0.367 CLKIN + CLKIN + cg/pll/clkin1_buf + ProtoComp0.IMUX + BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1 + BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0 + PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK + PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV + cg/pll/pll_base_inst/PLL_ADV + BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0 + BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf + cg/pll/clkout1_buf + RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK + ------------------------------------------------- --------------------------- + Total -3.099ns (-5.178ns logic, 2.079ns route) -------------------------------------------------------------------------------- Derived Constraint Report -Derived Constraints for instance_name/clkin1 +Derived Constraints for TS_CLKIN +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -|instance_name/clkin1 | 20.000ns| 5.000ns| 5.332ns| 0| 0| 0| 0| -| instance_name/clkfbout | 20.000ns| 2.666ns| N/A| 0| 0| 0| 0| -| instance_name/clkout0 | 10.000ns| 2.666ns| N/A| 0| 0| 0| 0| +|TS_CLKIN | 30.000ns| 10.000ns| 7.298ns| 0| 0| 0| 6| +| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0| +| TS_cg_pll_clkout0 | 15.000ns| 3.649ns| N/A| 0| 0| 6| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. @@ -554,48 +1208,75 @@ Setup/Hold to clock CLKIN |Max Setup to| Process |Max Hold to | Process | | Clock | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | ------------+------------+------------+------------+------------+------------------+--------+ -CPU_nAS | 9.880(R)| SLOW | -5.650(R)| FAST |FSBCLK | 0.000| -INt | 8.814(R)| SLOW | -4.307(R)| FAST |FSBCLK | 0.000| +FSB_A<2> | 9.717(R)| SLOW | -6.073(R)| FAST |FSBCLK | 0.000| +FSB_A<3> | 9.381(R)| SLOW | -5.737(R)| FAST |FSBCLK | 0.000| +FSB_A<4> | 9.445(R)| SLOW | -5.801(R)| FAST |FSBCLK | 0.000| +FSB_A<5> | 9.777(R)| SLOW | -6.133(R)| FAST |FSBCLK | 0.000| +FSB_A<6> | 9.606(R)| SLOW | -5.962(R)| FAST |FSBCLK | 0.000| ------------+------------+------------+------------+------------+------------------+--------+ -Clock CLKIN to Pad -------------+-----------------+------------+-----------------+------------+------------------+--------+ - |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | -Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | -------------+-----------------+------------+-----------------+------------+------------------+--------+ -OUTt | 1.412(R)| SLOW | 0.213(R)| FAST |FSBCLK | 0.000| -------------+-----------------+------------+-----------------+------------+------------------+--------+ +Clock to Setup on destination clock CLKIN +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +CLKIN | 3.649| | | | +---------------+---------+---------+---------+---------+ -COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 4.230; Ideal Clock Offset To Actual Clock 3.265; +COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.784; ------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | ------------------+------------+------------+------------+------------+---------+---------+-------------+ -CPU_nAS | 9.880(R)| SLOW | -5.650(R)| FAST | 0.120| 6.650| -3.265| +FSB_A<6> | 9.606(R)| SLOW | -5.962(R)| FAST | 2.394| 5.962| -1.784| ------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 9.880| - | -5.650| - | 0.120| 6.650| | +Worst Case Summary| 9.606| - | -5.962| - | 2.394| 5.962| | ------------------+------------+------------+------------+------------+---------+---------+-------------+ -COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN"; -Worst Case Data Window 4.507; Ideal Clock Offset To Actual Clock 2.061; +COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.955; ------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | ------------------+------------+------------+------------+------------+---------+---------+-------------+ -INt | 8.814(R)| SLOW | -4.307(R)| FAST | 1.186| 5.307| -2.061| +FSB_A<5> | 9.777(R)| SLOW | -6.133(R)| FAST | 2.223| 6.133| -1.955| ------------------+------------+------------+------------+------------+---------+---------+-------------+ -Worst Case Summary| 8.814| - | -4.307| - | 1.186| 5.307| | +Worst Case Summary| 9.777| - | -6.133| - | 2.223| 6.133| | ------------------+------------+------------+------------+------------+---------+---------+-------------+ -COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN"; -Bus Skew: 0.000 ns; ------------------------------------------------+-------------+------------+-------------+------------+--------------+ - |Max (slowest)| Process |Min (fastest)| Process | | -PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| ------------------------------------------------+-------------+------------+-------------+------------+--------------+ -OUTt | 1.412| SLOW | 0.213| FAST | 0.000| ------------------------------------------------+-------------+------------+-------------+------------+--------------+ +COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.623; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +FSB_A<4> | 9.445(R)| SLOW | -5.801(R)| FAST | 2.555| 5.801| -1.623| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 9.445| - | -5.801| - | 2.555| 5.801| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.559; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +FSB_A<3> | 9.381(R)| SLOW | -5.737(R)| FAST | 2.619| 5.737| -1.559| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 9.381| - | -5.737| - | 2.619| 5.737| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.895; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +FSB_A<2> | 9.717(R)| SLOW | -6.073(R)| FAST | 2.283| 6.073| -1.895| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 9.717| - | -6.073| - | 2.283| 6.073| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ Timing summary: @@ -603,25 +1284,24 @@ Timing summary: Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) -Constraints cover 3 paths, 0 nets, and 12 connections +Constraints cover 11 paths, 0 nets, and 24 connections Design statistics: - Minimum period: 5.000ns{1} (Maximum frequency: 200.000MHz) - Minimum input required time before clock: 9.880ns - Minimum output required time after clock: 1.412ns + Minimum period: 10.000ns{1} (Maximum frequency: 100.000MHz) + Minimum input required time before clock: 9.777ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. -Analysis completed Fri Oct 29 10:25:28 2021 +Analysis completed Sun Oct 31 14:40:54 2021 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings -Peak Memory Usage: 167 MB +Peak Memory Usage: 213 MB diff --git a/fpga/WarpLC_preroute.twx b/fpga/WarpLC_preroute.twx index b8c79c5..abce77c 100644 --- a/fpga/WarpLC_preroute.twx +++ b/fpga/WarpLC_preroute.twx @@ -329,26 +329,33 @@ ]> -Release 14.7 Trace (nt)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n -3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr +Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 +-n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr WarpLC.pcf -ucf PLL.ucf -WarpLC_map.ncdWarpLC_map.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.NET "FSBCLK" PERIOD = 10 ns HIGH 50%;00000001.866Component Switching Limit Checks: NET "FSBCLK" PERIOD = 10 ns HIGH 50%;NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;00000005.000Component Switching Limit Checks: NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%;PERIOD analysis for net "instance_name/clkfbout" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; duty cycle corrected to 20 nS HIGH 10 nS 00000002.666Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkfbout" derived from - NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; - duty cycle corrected to 20 nS HIGH 10 nS -PERIOD analysis for net "instance_name/clkout0" derived from NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; divided by 2.00 to 10 nS 00000002.666Component Switching Limit Checks: PERIOD analysis for net "instance_name/clkout0" derived from - NET "instance_name/clkin1" PERIOD = 20 ns HIGH 50%; - divided by 2.00 to 10 nS -COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";10000109.880Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path -0.120CPU_nASOUTt-4.891CLKINOUTt_OBUF10.000CPU_nASCLKIN0.414CPU_nASOUTt1N4.PADN4.ITiopi1.557CPU_nASCPU_nASCPU_nAS_IBUFProtoComp0.IMUX.1ILOGIC_X0Y5.SRnet12.043CPU_nAS_IBUFILOGIC_X0Y5.CLK0Tisrck0.975OUTt_OBUFOUTt2.5322.0434.575FSBCLK55.344.7CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINinstance_name/clkin1_bufProtoComp0.IMUX.3BUFIO2_X0Y23.Inet10.000instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248instance_name/pll_base_inst/PLL_ADVinstance_name/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505instance_name/clkout0BUFGMUX_X3Y13.OTgi0o0.197instance_name/clkout1_bufinstance_name/clkout1_bufILOGIC_X0Y5.CLK0net11.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN"; -Paths for end point OUTt (ILOGIC_X0Y5.SR), 1 path -6.650CPU_nASOUTt-3.099CLKINOUTt_OBUF1.000CPU_nASCLKIN0.414CPU_nASOUTt1N4.PADN4.ITiopi0.763CPU_nASCPU_nASCPU_nAS_IBUFProtoComp0.IMUX.1ILOGIC_X0Y5.SRnet12.043CPU_nAS_IBUFILOGIC_X0Y5.CLK0Ticksr0.159OUTt_OBUFOUTt0.9222.0432.965FSBCLK31.168.9CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINinstance_name/clkin1_bufProtoComp0.IMUX.3BUFIO2_X0Y23.Inet10.000instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738instance_name/pll_base_inst/PLL_ADVinstance_name/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505instance_name/clkout0BUFGMUX_X3Y13.OTgi0o0.063instance_name/clkout1_bufinstance_name/clkout1_bufILOGIC_X0Y5.CLK0net11.574FSBCLK-5.1782.079-3.099COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";10000108.814Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path -1.186INtOUTt-4.891CLKINOUTt_OBUF10.000INtCLKIN0.414INtOUTt2M4.PADM4.ITiopi1.557INtINtINt_IBUFProtoComp0.IMUX.2ILOGIC_X0Y5.Dnet10.229CPU_nAS_INt_AND_1_o_norstILOGIC_X0Y5.CLK0Tidock1.723OUTt_OBUFProtoComp3.D2OFFBYP_SRCOUTt3.2800.2293.509FSBCLK93.56.5CLKINOUTt4J4.PADJ4.ITiopi0.902CLKINCLKINinstance_name/clkin1_bufProtoComp0.IMUX.3BUFIO2_X0Y23.Inet10.000instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248instance_name/pll_base_inst/PLL_ADVinstance_name/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505instance_name/clkout0BUFGMUX_X3Y13.OTgi0o0.197instance_name/clkout1_bufinstance_name/clkout1_bufILOGIC_X0Y5.CLK0net11.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN"; -Paths for end point OUTt (ILOGIC_X0Y5.D), 1 path -5.307INtOUTt-3.099CLKINOUTt_OBUF1.000INtCLKIN0.414INtOUTt2M4.PADM4.ITiopi0.763INtINtINt_IBUFProtoComp0.IMUX.2ILOGIC_X0Y5.Dnet10.229CPU_nAS_INt_AND_1_o_norstILOGIC_X0Y5.CLK0Tiockd0.630OUTt_OBUFProtoComp3.D2OFFBYP_SRCOUTt1.3930.2291.622FSBCLK85.914.1CLKINOUTt4J4.PADJ4.ITiopi0.367CLKINCLKINinstance_name/clkin1_bufProtoComp0.IMUX.3BUFIO2_X0Y23.Inet10.000instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738instance_name/pll_base_inst/PLL_ADVinstance_name/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505instance_name/clkout0BUFGMUX_X3Y13.OTgi0o0.063instance_name/clkout1_bufinstance_name/clkout1_bufILOGIC_X0Y5.CLK0net11.574FSBCLK-5.1782.079-3.099COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";10000101.412Paths for end point OUTt (M3.PAD), 1 path -2.588OUTtOUTt-5.070CLKINOUTt_OBUF6.068OUTt_OBUFOUTt4.000CLKINOUTt0.414CLKINOUTt4J4.PADJ4.ITiopi1.037CLKINCLKINinstance_name/clkin1_bufProtoComp0.IMUX.3BUFIO2_X0Y23.Inet10.000instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.190SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.585instance_name/pll_base_inst/PLL_ADVinstance_name/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505instance_name/clkout0BUFGMUX_X3Y13.OTgi0o0.209instance_name/clkout1_bufinstance_name/clkout1_bufILOGIC_X0Y5.CLK0net11.574FSBCLK-7.1492.079-5.070OUTtOUTt1ILOGIC_X0Y5.CLK0FSBCLKILOGIC_X0Y5.Q4Tickq1.778OUTt_OBUFOUTtM3.Onet12.308OUTt_OBUFM3.PADTioop1.982OUTtOUTt_OBUFOUTt3.7602.3086.06862.038.0Fastest Paths: COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN"; -Paths for end point OUTt (M3.PAD), 1 path -0.213OUTtOUTt-3.036CLKINOUTt_OBUF3.663OUTt_OBUFOUTt4.000CLKINOUTt0.414CLKINOUTt4J4.PADJ4.ITiopi0.321CLKINCLKINinstance_name/clkin1_bufProtoComp0.IMUX.3BUFIO2_X0Y23.Inet10.000instance_name/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000instance_name/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.617instance_name/pll_base_inst/PLL_ADVinstance_name/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505instance_name/clkout0BUFGMUX_X3Y13.OTgi0o0.059instance_name/clkout1_bufinstance_name/clkout1_bufILOGIC_X0Y5.CLK0net11.574FSBCLK-5.1152.079-3.036OUTtOUTt1ILOGIC_X0Y5.CLK0FSBCLKILOGIC_X0Y5.Q4Tickq0.656OUTt_OBUFOUTtM3.Onet12.308OUTt_OBUFM3.PADTioop0.699OUTtOUTt_OBUFOUTt1.3552.3083.66337.063.00CLKINCPU_nAS9.880-5.650INt8.814-4.307CLKINCOMP "CPU_nAS" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";CPU_nAS9.880-5.650COMP "INt" OFFSET = IN 10 ns VALID 11 ns BEFORE COMP "CLKIN";INt8.814-4.307COMP "OUTt" OFFSET = OUT 4 ns AFTER COMP "CLKIN";000030125.000200.0009.8801.412Fri Oct 29 10:25:28 2021 TraceTrace Settings +WarpLC_map.ncdWarpLC_map.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-1313WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<27>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<26>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<25>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<24>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<23>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<22>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<21>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<20>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<19>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<18>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<17>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<16>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<15>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<14>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<13>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<12>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<11>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<10>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<9>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<8>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisWARNING:Timing:3175 - CLKIN does not clock data from FSB_A<7>WARNING:Timing:3225 - Timing constraint COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysisINFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;000000010.000Component Switching Limit Checks: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;00000002.666Component Switching Limit Checks: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;60000603.649Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y62.D1), 1 path +11.351cg/CPUCLKrcg/CPUCLK_inst3.5330.00015.0000.116cg/CPUCLKrcg/CPUCLK_inst1SLICE_X14Y63.CLKFSBCLKSLICE_X14Y63.DQTcko0.476cg/CPUCLKrcg/CPUCLKrSLICE_X14Y63.D4net40.491cg/CPUCLKrSLICE_X14Y63.DTilo0.235cg/CPUCLKrl2pre/CPUCLKr_INV_15_o1_INV_0OLOGIC_X1Y62.D1net31.365l2pre/CPUCLKr_INV_15_oOLOGIC_X1Y62.CLK0Todck0.966CPUCLK_OBUFcg/CPUCLK_inst1.6771.8563.533FSBCLK47.552.5Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y62.D2), 1 path +11.751cg/CPUCLKrcg/CPUCLK_inst3.1330.00015.0000.116cg/CPUCLKrcg/CPUCLK_inst1SLICE_X14Y63.CLKFSBCLKSLICE_X14Y63.DQTcko0.476cg/CPUCLKrcg/CPUCLKrSLICE_X14Y63.D4net40.491cg/CPUCLKrSLICE_X14Y63.DTilo0.235cg/CPUCLKrl2pre/CPUCLKr_INV_15_o1_INV_0OLOGIC_X1Y62.D2net31.100l2pre/CPUCLKr_INV_15_oOLOGIC_X1Y62.CLK0Todck0.831CPUCLK_OBUFcg/CPUCLK_inst1.5421.5913.133FSBCLK49.250.8Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D1), 1 path +12.451cg/CPUCLKrcg/FPUCLK_inst2.4330.00015.0000.116cg/CPUCLKrcg/FPUCLK_inst0SLICE_X14Y63.CLKFSBCLKSLICE_X14Y63.DQTcko0.476cg/CPUCLKrcg/CPUCLKrOLOGIC_X11Y63.D1net40.991cg/CPUCLKrOLOGIC_X11Y63.CLK0Todck0.966FPUCLK_OBUFcg/FPUCLK_inst1.4420.9912.433FSBCLK59.340.7Hold Paths: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%; +Paths for end point cg/CPUCLKr (SLICE_X14Y63.SR), 1 path +0.577cg/CPUCLKrcg/CPUCLKr0.5770.0000.0000.000cg/CPUCLKrcg/CPUCLKr0SLICE_X14Y63.CLKFSBCLKSLICE_X14Y63.DQTcko0.200cg/CPUCLKrcg/CPUCLKrSLICE_X14Y63.SRnet40.376cg/CPUCLKrSLICE_X14Y63.CLKTcksr0.001cg/CPUCLKrcg/CPUCLKr0.2010.3760.577FSBCLK34.865.2Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D2), 1 path +1.346cg/CPUCLKrcg/FPUCLK_inst1.3460.0000.0000.000cg/CPUCLKrcg/FPUCLK_inst0SLICE_X14Y63.CLKFSBCLKSLICE_X14Y63.DQTcko0.200cg/CPUCLKrcg/CPUCLKrOLOGIC_X11Y63.D2net40.991cg/CPUCLKrOLOGIC_X11Y63.CLK0Tockd0.155FPUCLK_OBUFcg/FPUCLK_inst0.3550.9911.346FSBCLK26.473.6Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D1), 1 path +1.521cg/CPUCLKrcg/FPUCLK_inst1.5210.0000.0000.000cg/CPUCLKrcg/FPUCLK_inst0SLICE_X14Y63.CLKFSBCLKSLICE_X14Y63.DQTcko0.200cg/CPUCLKrcg/CPUCLKrOLOGIC_X11Y63.D1net40.991cg/CPUCLKrOLOGIC_X11Y63.CLK0Tockd0.330FPUCLK_OBUFcg/FPUCLK_inst0.5300.9911.521FSBCLK34.865.2Component Switching Limit Checks: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";0000000COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";10000109.606Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path +2.394FSB_A<6>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-4.891CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram12.000FSB_A<6>CLKIN0.296FSB_A<6>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1B15.PADB15.ITiopi1.557FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp0.IMUX.24RAMB8_X1Y31.ADDRBRDADDR9net132.462FSB_A_6_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.4624.419FSBCLK44.355.7CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path +5.962FSB_A<6>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-3.099CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.000FSB_A<6>CLKIN0.296FSB_A<6>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1B15.PADB15.ITiopi0.763FSB_A<6>FSB_A<6>FSB_A_6_IBUFProtoComp0.IMUX.24RAMB8_X1Y31.ADDRBRDADDR9net132.462FSB_A_6_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6972.4623.159FSBCLK22.177.9CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-5.1782.079-3.099COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";10000109.777Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path +2.223FSB_A<5>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-4.891CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram12.000FSB_A<5>CLKIN0.296FSB_A<5>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E12.PADE12.ITiopi1.557FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp0.IMUX.23RAMB8_X1Y31.ADDRBRDADDR8net132.633FSB_A_5_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.6334.590FSBCLK42.657.4CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path +6.133FSB_A<5>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-3.099CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.000FSB_A<5>CLKIN0.296FSB_A<5>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E12.PADE12.ITiopi0.763FSB_A<5>FSB_A<5>FSB_A_5_IBUFProtoComp0.IMUX.23RAMB8_X1Y31.ADDRBRDADDR8net132.633FSB_A_5_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6972.6333.330FSBCLK20.979.1CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-5.1782.079-3.099COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";10000109.445Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +2.555FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-4.891CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram12.000FSB_A<4>CLKIN0.296FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E13.PADE13.ITiopi1.557FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp0.IMUX.22RAMB8_X1Y31.ADDRBRDADDR7net132.301FSB_A_4_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.3014.258FSBCLK46.054.0CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path +5.801FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-3.099CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.000FSB_A<4>CLKIN0.296FSB_A<4>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1E13.PADE13.ITiopi0.763FSB_A<4>FSB_A<4>FSB_A_4_IBUFProtoComp0.IMUX.22RAMB8_X1Y31.ADDRBRDADDR7net132.301FSB_A_4_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6972.3012.998FSBCLK23.276.8CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-5.1782.079-3.099COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";10000109.381Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path +2.619FSB_A<3>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-4.891CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram12.000FSB_A<3>CLKIN0.296FSB_A<3>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1D12.PADD12.ITiopi1.557FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp0.IMUX.21RAMB8_X1Y31.ADDRBRDADDR6net132.237FSB_A_3_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.2374.194FSBCLK46.753.3CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path +5.737FSB_A<3>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-3.099CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.000FSB_A<3>CLKIN0.296FSB_A<3>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1D12.PADD12.ITiopi0.763FSB_A<3>FSB_A<3>FSB_A_3_IBUFProtoComp0.IMUX.21RAMB8_X1Y31.ADDRBRDADDR6net132.237FSB_A_3_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6972.2372.934FSBCLK23.876.2CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-5.1782.079-3.099COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";10000109.717Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path +2.283FSB_A<2>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-4.891CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram12.000FSB_A<2>CLKIN0.296FSB_A<2>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1D11.PADD11.ITiopi1.557FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp0.IMUX.20RAMB8_X1Y31.ADDRBRDADDR5net132.573FSB_A_2_IBUFRAMB8_X1Y31.CLKBRDCLKTrcck_ADDRB0.400l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1.9572.5734.530FSBCLK43.256.8CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.902CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.179SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-8.248cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.197cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-6.9702.079-4.891Hold Paths: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN"; +Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path +6.073FSB_A<2>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram-3.099CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.000FSB_A<2>CLKIN0.296FSB_A<2>l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram1D11.PADD11.ITiopi0.763FSB_A<2>FSB_A<2>FSB_A_2_IBUFProtoComp0.IMUX.20RAMB8_X1Y31.ADDRBRDADDR5net132.573FSB_A_2_IBUFRAMB8_X1Y31.CLKBRDCLKTrckc_ADDRB-0.066l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.raml2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram0.6972.5733.270FSBCLK21.378.7CLKINl2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram4J4.PADJ4.ITiopi0.367CLKINCLKINcg/pll/clkin1_bufProtoComp0.IMUXBUFIO2_X0Y23.Inet10.000cg/pll/clkin1BUFIO2_X0Y23.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0PLL_ADV_X0Y1.CLKIN1net10.000cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLKPLL_ADV_X0Y1.CLKOUT0Tpllcko_CLK-5.738cg/pll/pll_base_inst/PLL_ADVcg/pll/pll_base_inst/PLL_ADVBUFGMUX_X3Y13.I0net10.505cg/pll/clkout0BUFGMUX_X3Y13.OTgi0o0.063cg/pll/clkout1_bufcg/pll/clkout1_bufRAMB8_X1Y31.CLKBRDCLKnet171.574FSBCLK-5.1782.079-3.0990CLKINFSB_A<2>9.717-6.073FSB_A<3>9.381-5.737FSB_A<4>9.445-5.801FSB_A<5>9.777-6.133FSB_A<6>9.606-5.962CLKINCLKIN3.649COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<6>9.606-5.962COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<5>9.777-6.133COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<4>9.445-5.801COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<3>9.381-5.737COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";FSB_A<2>9.717-6.07300001102410.000100.0009.777Sun Oct 31 14:40:54 2021 TraceTrace Settings -Peak Memory Usage: 167 MB +Peak Memory Usage: 213 MB diff --git a/fpga/WarpLC_summary.html b/fpga/WarpLC_summary.html index f5c2012..15201ee 100644 --- a/fpga/WarpLC_summary.html +++ b/fpga/WarpLC_summary.html @@ -2,7 +2,7 @@ - + @@ -19,13 +19,12 @@ - + - + @@ -60,13 +59,13 @@ System Settings - + - + @@ -90,31 +89,31 @@ System Settings - + - + - + - + - + @@ -126,87 +125,99 @@ System Settings - + - + - + + + + + + + - - - - - - - + - + + + + + + + + + + + + + - + - + - + - - - + + + - - - + + + - - - + + + - + - + - + - + @@ -222,9 +233,9 @@ System Settings - + - + @@ -390,7 +401,7 @@ System Settings - + @@ -427,20 +438,21 @@ System Settings - - - - + + + + - +
WarpLC Project Status (10/29/2021 - 17:39:15)
ClkGen Project Status (10/31/2021 - 15:38:40)
Project File: WarpLC.xiseTarget Device: xc6slx9-2ftg256
  • Errors:
 -No Errors 
Product Version:ISE 14.7
  • Warnings:
7 Warnings (0 new) 
Design Goal: Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers341 11,440 1%  
    Number used as Flip Flops341        
Number of Slice LUTs1733 5,720 1%  
    Number used as logic139 5,720 1%  
        Number using O6 output only118      
        Number using O5 output only01      
        Number using O5 and O620        
    Number used as Memory024 1,4400%1%  
    Number used exclusively as route-thrus
        Number used as Dual Port RAM24   
            Number using O6 output only 4      
        Number with same-slice register load4   
        Number with same-slice carry load
            Number using O5 output only 0      
        Number with other load
            Number using O5 and O620   
        Number used as Single Port RAM0   
        Number used as Shift Register 0      
Number of occupied Slices119 1,430 1%  
Number of MUXCYs used128 2,860 1%  
Number of LUT Flip Flop pairs used4133      
    Number with an unused Flip Flop114126%323396%  
    Number with an unused LUT244158%0330%  
    Number of fully used LUT-FF pairs64114%1333%  
    Number of unique control sets12      
    Number of slice register sites lost
        to control set restrictions		611 11,440 1%  
Number of bonded IOBs4366 18623%35%  
    IOB Flip Flops  
Number of RAMB8BWERs01 640%1%  
Number of BUFIO2/BUFIO2_2CLKs  
Average Fanout of Non-Clock Nets1.411.67      
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Oct 30 17:25:53 202107 Warnings (0 new)2 Infos (0 new)
Translation ReportCurrentSat Oct 30 17:25:53 2021001 Info (0 new)
Map ReportCurrentSat Oct 30 17:25:53 2021006 Infos (0 new)
Place and Route ReportCurrentSat Oct 30 17:25:53 2021000
Synthesis ReportCurrentSun Oct 31 15:37:53 2021017 Warnings (0 new)3 Infos (0 new)
Translation ReportCurrentSun Oct 31 15:37:59 202109 Warnings (0 new)2 Infos (0 new)
Map ReportCurrentSun Oct 31 15:38:27 2021   
Place and Route ReportCurrentSun Oct 31 15:38:33 2021001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentSat Oct 30 17:25:53 2021003 Infos (0 new)
Post-PAR Static Timing ReportCurrentSun Oct 31 15:38:38 2021003 Infos (0 new)
Bitgen Report     
 
- + +
Secondary Reports [-]
Report NameStatusGenerated
Post-Map Static Timing ReportOut of DateSat Oct 30 17:25:53 2021
Post-Map Static Timing ReportOut of DateSun Oct 31 14:40:54 2021
Physical Synthesis ReportOut of DateSun Oct 31 15:38:26 2021
-
Date Generated: 10/30/2021 - 17:26:36
+
Date Generated: 10/31/2021 - 15:38:40
\ No newline at end of file diff --git a/fpga/WarpLC_summary.xml b/fpga/WarpLC_summary.xml new file mode 100644 index 0000000..45e1373 --- /dev/null +++ b/fpga/WarpLC_summary.xml @@ -0,0 +1,10 @@ + + + + + + diff --git a/fpga/WarpLC_usage.xml b/fpga/WarpLC_usage.xml new file mode 100644 index 0000000..fdcbe3a --- /dev/null +++ b/fpga/WarpLC_usage.xml @@ -0,0 +1,73 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/WarpLC_xst.xrpt b/fpga/WarpLC_xst.xrpt index 4fe86d0..91bcdbb 100644 --- a/fpga/WarpLC_xst.xrpt +++ b/fpga/WarpLC_xst.xrpt @@ -1,18 +1,18 @@ - + - +
- + @@ -36,16 +36,16 @@
- - + + - + - - + +
@@ -56,13 +56,13 @@ - + - + @@ -109,25 +109,20 @@
- - - - - - + + +
- - - - - + + +
- - + +
@@ -140,42 +135,46 @@
- - + + - - - - + + + - - + + + + - - + + - +
- - - - - - - - - - + + + + + + + + + + + + +
@@ -183,8 +182,8 @@
- - + +
diff --git a/fpga/_ngo/netlist.lst b/fpga/_ngo/netlist.lst index 630f97b..3c69daa 100644 --- a/fpga/_ngo/netlist.lst +++ b/fpga/_ngo/netlist.lst @@ -1,2 +1,4 @@ -C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635544779 +C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.ngc 1635709073 +ipcore_dir/PrefetchTagRAM.ngc 1635704546 +ipcore_dir/PrefetchDataRAM.ngc 1635685742 OK diff --git a/fpga/_xmsgs/map.xmsgs b/fpga/_xmsgs/map.xmsgs index 3a413e8..f1db959 100644 --- a/fpga/_xmsgs/map.xmsgs +++ b/fpga/_xmsgs/map.xmsgs @@ -5,10 +5,22 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -No environment variables are currently set. +Map is running with the multi-threading option on. Map currently supports the use of up to 2 processors. Based on the the user options and machine load, Map will use 2 processors during this run. -Net Timing constraints on signal CLKIN are pushed forward through input buffer. +Logical network FSB_A<31> has no load. + + +The above info message is repeated 54 more times for the following (max. 5 shown): +FSB_A<30>, +FSB_A<29>, +FSB_A<28>, +FSB_A<1>, +FSB_A<0> +To see the details of these info messages, please use the -detail switch. + + +No environment variables are currently set. Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) @@ -23,5 +35,8 @@ Map created a placed design. +This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999. + + diff --git a/fpga/_xmsgs/ngdbuild.xmsgs b/fpga/_xmsgs/ngdbuild.xmsgs index 318499a..e3635a7 100644 --- a/fpga/_xmsgs/ngdbuild.xmsgs +++ b/fpga/_xmsgs/ngdbuild.xmsgs @@ -5,7 +5,39 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -The Period constraint <NET CLKIN PERIOD = 30ns HIGH;> [PLL.ucf(3)], is specified using the Net Period method which is not recommended. Please use the Timespec PERIOD method. +Constraint <NET "CPU_nAS" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/CPU_nAS' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_SIZ<0>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<0>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_SIZ<1>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_SIZ<1>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_A<0>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_A<0>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_A<1>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_A<1>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_A<28>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_A<28>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_A<29>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_A<29>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_A<30>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_A<30>' because those design objects do not contain or drive any instances of the correct type. + + +Constraint <NET "FSB_A<31>" IOBDELAY = NONE>: This constraint cannot be distributed from the design objects matching 'NET: UniqueName: /WarpLC/EXPANDED/FSB_A<31>' because those design objects do not contain or drive any instances of the correct type. + + +TNM 'CLKIN', used in period specification 'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM groups and period specifications were generated at the PLL_ADV output(s): +CLKFBOUT: <TIMESPEC TS_cg_pll_clkfbout = PERIOD "cg_pll_clkfbout" TS_CLKIN HIGH 50%> + + +TNM 'CLKIN', used in period specification 'TS_CLKIN', was traced into PLL_ADV instance PLL_ADV. The following new TNM groups and period specifications were generated at the PLL_ADV output(s): +CLKOUT0: <TIMESPEC TS_cg_pll_clkout0 = PERIOD "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%> diff --git a/fpga/_xmsgs/par.xmsgs b/fpga/_xmsgs/par.xmsgs index f84336a..d069575 100644 --- a/fpga/_xmsgs/par.xmsgs +++ b/fpga/_xmsgs/par.xmsgs @@ -5,5 +5,9 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> + +Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are not meeting timing but where the designer wants the tools to continue iterating on the design until no further design speed improvements are possible. This can result in very long runtimes since the tools will continue improving the design even if the time specs can not be met. If you are looking for the best possible design speed available from a long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design speed improvements have shrunk to the point that the time specs are not expected to be met. + + diff --git a/fpga/_xmsgs/pn_parser.xmsgs b/fpga/_xmsgs/pn_parser.xmsgs index 38798db..3c04736 100644 --- a/fpga/_xmsgs/pn_parser.xmsgs +++ b/fpga/_xmsgs/pn_parser.xmsgs @@ -11,8 +11,5 @@ Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/PrefetchBuf.v" into library work -"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/PrefetchBuf.v" Line 36. Syntax error near ")". - - diff --git a/fpga/_xmsgs/trce.xmsgs b/fpga/_xmsgs/trce.xmsgs index b8e4b55..551d88e 100644 --- a/fpga/_xmsgs/trce.xmsgs +++ b/fpga/_xmsgs/trce.xmsgs @@ -5,9 +5,9 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -To improve timing, see the Timing Closure User Guide (UG612). +Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report. -To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. +To improve timing, see the Timing Closure User Guide (UG612). The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. diff --git a/fpga/_xmsgs/xst.xmsgs b/fpga/_xmsgs/xst.xmsgs index f585de3..67ce101 100644 --- a/fpga/_xmsgs/xst.xmsgs +++ b/fpga/_xmsgs/xst.xmsgs @@ -5,28 +5,61 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 128: Assignment to clkout1_unused ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" Line 32: Port LOCKED is not connected to this instance -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 129: Assignment to clkout2_unused ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 129: Assignment to clkout1_unused ignored, since the identifier is never used -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 130: Assignment to clkout3_unused ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 130: Assignment to clkout2_unused ignored, since the identifier is never used -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 131: Assignment to clkout4_unused ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 131: Assignment to clkout3_unused ignored, since the identifier is never used -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 132: Assignment to clkout5_unused ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 132: Assignment to clkout4_unused ignored, since the identifier is never used -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\ipcore_dir\CLK.v" Line 133: Assignment to locked_unused ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PLL.v" Line 133: Assignment to clkout5_unused ignored, since the identifier is never used -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 84: Assignment to CPUCLKr ignored, since the identifier is never used +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" Line 94: Assignment to FSB_B ignored, since the identifier is never used -"C:\Users\zanek\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 79: Output port <CPUCLKr> of the instance <CLKGEN_inst> is unconnected or connected to loadless signal. +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchTagRAM.v" Line 39: Empty module <PrefetchTagRAM> remains a black box. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 33: Size mismatch in connection of port <a>. Formal port size is 5-bit while actual signal size is 7-bit. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 36: Size mismatch in connection of port <dpra>. Formal port size is 5-bit while actual signal size is 7-bit. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\PrefetchDataRAM.v" Line 39: Empty module <PrefetchDataRAM> remains a black box. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\PrefetchBuf.v" Line 44: Size mismatch in connection of port <addra>. Formal port size is 7-bit while actual signal size is 5-bit. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91. All outputs of instance <sd> of block <SizeDecode> are unconnected in block <WarpLC>. Underlying logic will be removed. + + +Input <FSB_A<31:29>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <CPU_nAS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\WarpLC.v" line 91: Output port <B> of the instance <sd> is unconnected or connected to loadless signal. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ClkGen.v" line 32: Output port <LOCKED> of the instance <pll> is unconnected or connected to loadless signal. + + +Input <RDA<28:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <WRA<28:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Instance pll_base_inst in unit pll_base_inst of type PLL_BASE has been replaced by PLL_ADV diff --git a/fpga/ipcore_dir/CLK/implement/xst.prj b/fpga/ipcore_dir/CLK/implement/xst.prj deleted file mode 100644 index 5f6e4f5..0000000 --- a/fpga/ipcore_dir/CLK/implement/xst.prj +++ /dev/null @@ -1,2 +0,0 @@ -verilog work ../../CLK.v -verilog work ../example_design/CLK_exdes.v diff --git a/fpga/ipcore_dir/CLK/simulation/functional/vcs_session.tcl b/fpga/ipcore_dir/CLK/simulation/functional/vcs_session.tcl deleted file mode 100644 index d96eeac..0000000 --- a/fpga/ipcore_dir/CLK/simulation/functional/vcs_session.tcl +++ /dev/null @@ -1,15 +0,0 @@ -gui_open_window Wave -gui_sg_create CLK_group -gui_list_add_group -id Wave.1 {CLK_group} -gui_sg_addsignal -group CLK_group {CLK_tb.test_phase} -gui_set_radix -radix {ascii} -signals {CLK_tb.test_phase} -gui_sg_addsignal -group CLK_group {{Input_clocks}} -divider -gui_sg_addsignal -group CLK_group {CLK_tb.CLK_IN1} -gui_sg_addsignal -group CLK_group {{Output_clocks}} -divider -gui_sg_addsignal -group CLK_group {CLK_tb.dut.clk} -gui_list_expand -id Wave.1 CLK_tb.dut.clk -gui_sg_addsignal -group CLK_group {{Counters}} -divider -gui_sg_addsignal -group CLK_group {CLK_tb.COUNT} -gui_sg_addsignal -group CLK_group {CLK_tb.dut.counter} -gui_list_expand -id Wave.1 CLK_tb.dut.counter -gui_zoom -window Wave.1 -full diff --git a/fpga/ipcore_dir/CLK_flist.txt b/fpga/ipcore_dir/CLK_flist.txt deleted file mode 100644 index b82c289..0000000 --- a/fpga/ipcore_dir/CLK_flist.txt +++ /dev/null @@ -1,55 +0,0 @@ -# Output products list for -CLK.asy -CLK.gise -CLK.sym -CLK.ucf -CLK.v -CLK.veo -CLK.xco -CLK.xdc -CLK.xise -CLK\clk_wiz_v3_6_readme.txt -CLK\doc\clk_wiz_v3_6_readme.txt -CLK\doc\clk_wiz_v3_6_vinfo.html -CLK\doc\pg065_clk_wiz.pdf -CLK\example_design\CLK_exdes.ucf -CLK\example_design\CLK_exdes.v -CLK\example_design\CLK_exdes.xdc -CLK\implement\implement.bat -CLK\implement\implement.sh -CLK\implement\planAhead_ise.bat -CLK\implement\planAhead_ise.sh -CLK\implement\planAhead_ise.tcl -CLK\implement\planAhead_rdn.bat -CLK\implement\planAhead_rdn.sh -CLK\implement\planAhead_rdn.tcl -CLK\implement\xst.prj -CLK\implement\xst.scr -CLK\simulation\CLK_tb.v -CLK\simulation\functional\simcmds.tcl -CLK\simulation\functional\simulate_isim.bat -CLK\simulation\functional\simulate_isim.sh -CLK\simulation\functional\simulate_mti.bat -CLK\simulation\functional\simulate_mti.do -CLK\simulation\functional\simulate_mti.sh -CLK\simulation\functional\simulate_ncsim.sh -CLK\simulation\functional\simulate_vcs.sh -CLK\simulation\functional\ucli_commands.key -CLK\simulation\functional\vcs_session.tcl -CLK\simulation\functional\wave.do -CLK\simulation\functional\wave.sv -CLK\simulation\timing\CLK_tb.v -CLK\simulation\timing\sdf_cmd_file -CLK\simulation\timing\simcmds.tcl -CLK\simulation\timing\simulate_isim.sh -CLK\simulation\timing\simulate_mti.bat -CLK\simulation\timing\simulate_mti.do -CLK\simulation\timing\simulate_mti.sh -CLK\simulation\timing\simulate_ncsim.sh -CLK\simulation\timing\simulate_vcs.sh -CLK\simulation\timing\ucli_commands.key -CLK\simulation\timing\vcs_session.tcl -CLK\simulation\timing\wave.do -CLK_flist.txt -CLK_xmdf.tcl -_xmsgs\pn_parser.xmsgs diff --git a/fpga/ipcore_dir/CLK.asy b/fpga/ipcore_dir/PLL.asy similarity index 78% rename from fpga/ipcore_dir/CLK.asy rename to fpga/ipcore_dir/PLL.asy index 97dcfae..ad71efa 100644 --- a/fpga/ipcore_dir/CLK.asy +++ b/fpga/ipcore_dir/PLL.asy @@ -1,6 +1,6 @@ Version 4 SymbolType BLOCK -TEXT 32 32 LEFT 4 CLK +TEXT 32 32 LEFT 4 PLL RECTANGLE Normal 32 32 576 1088 LINE Normal 0 80 32 80 PIN 0 80 LEFT 36 @@ -18,4 +18,8 @@ LINE Normal 608 752 576 752 PIN 608 752 RIGHT 36 PINATTR PinName clkfb_out PINATTR Polarity OUT +LINE Normal 608 976 576 976 +PIN 608 976 RIGHT 36 +PINATTR PinName locked +PINATTR Polarity OUT diff --git a/fpga/ipcore_dir/CLK.gise b/fpga/ipcore_dir/PLL.gise similarity index 65% rename from fpga/ipcore_dir/CLK.gise rename to fpga/ipcore_dir/PLL.gise index a69e8d8..8855d57 100644 --- a/fpga/ipcore_dir/CLK.gise +++ b/fpga/ipcore_dir/PLL.gise @@ -19,31 +19,31 @@ 11.1 - + - - + + - + - + - + - + - + diff --git a/fpga/ipcore_dir/CLK.ncf b/fpga/ipcore_dir/PLL.ncf similarity index 96% rename from fpga/ipcore_dir/CLK.ncf rename to fpga/ipcore_dir/PLL.ncf index 664a529..e28b9c4 100644 --- a/fpga/ipcore_dir/CLK.ncf +++ b/fpga/ipcore_dir/PLL.ncf @@ -1,4 +1,4 @@ -# file: CLK.ucf +# file: PLL.ucf # # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. # @@ -51,7 +51,7 @@ # input clocks. You can use these to time your system #---------------------------------------------------------------- NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.000 ns HIGH 50% INPUT_JITTER 300.0ps; # Constraints for external feedback. diff --git a/fpga/ipcore_dir/CLK.sym b/fpga/ipcore_dir/PLL.sym similarity index 73% rename from fpga/ipcore_dir/CLK.sym rename to fpga/ipcore_dir/PLL.sym index 894b463..6d53c0a 100644 --- a/fpga/ipcore_dir/CLK.sym +++ b/fpga/ipcore_dir/PLL.sym @@ -1,13 +1,14 @@ - + BLOCK - 2021-10-29T21:49:45 + 2021-10-31T17:58:31 + - CLK + PLL @@ -17,5 +18,7 @@ + + diff --git a/fpga/ipcore_dir/CLK.ucf b/fpga/ipcore_dir/PLL.ucf similarity index 96% rename from fpga/ipcore_dir/CLK.ucf rename to fpga/ipcore_dir/PLL.ucf index 3a57aec..e43ec9b 100644 --- a/fpga/ipcore_dir/CLK.ucf +++ b/fpga/ipcore_dir/PLL.ucf @@ -1,4 +1,4 @@ -# file: CLK.ucf +# file: PLL.ucf # # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. # @@ -51,7 +51,7 @@ # input clocks. You can use these to time your system #---------------------------------------------------------------- NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.000 ns HIGH 50% INPUT_JITTER 300.0ps; # Constraints for external feedback. diff --git a/fpga/ipcore_dir/CLK.v b/fpga/ipcore_dir/PLL.v similarity index 84% rename from fpga/ipcore_dir/CLK.v rename to fpga/ipcore_dir/PLL.v index be673fe..57d41cd 100644 --- a/fpga/ipcore_dir/CLK.v +++ b/fpga/ipcore_dir/PLL.v @@ -1,4 +1,4 @@ -// file: CLK.v +// file: PLL.v // // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. // @@ -55,23 +55,25 @@ // "Output Output Phase Duty Pk-to-Pk Phase" // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" //---------------------------------------------------------------------------- -// CLK_OUT1____66.667______0.000______50.0______300.590____267.927 +// CLK_OUT1____66.667______0.000______50.0______252.559____182.342 // //---------------------------------------------------------------------------- // "Input Clock Freq (MHz) Input Jitter (UI)" //---------------------------------------------------------------------------- -// __primary_________33.3333___________0.00833333333333 +// __primary_________33.3333____________0.010 `timescale 1ps/1ps -(* CORE_GENERATION_INFO = "CLK,clk_wiz_v3_6,{component_name=CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=30.0,clkin2_period=30.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *) -module CLK +(* CORE_GENERATION_INFO = "PLL,clk_wiz_v3_6,{component_name=PLL,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=30.000,clkin2_period=30.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *) +module PLL (// Clock in ports input CLKIN, input CLKFB_IN, // Clock out ports output FSBCLK, - output CLKFB_OUT + output CLKFB_OUT, + // Status and control signals + output LOCKED ); // Input buffering @@ -100,7 +102,6 @@ module CLK // * Unused outputs are labeled unused wire [15:0] do_unused; wire drdy_unused; - wire locked_unused; wire clkfbout; wire clkfbout_buf; wire clkout1_unused; @@ -110,17 +111,17 @@ module CLK wire clkout5_unused; PLL_BASE - #(.BANDWIDTH ("OPTIMIZED"), + #(.BANDWIDTH ("HIGH"), .CLK_FEEDBACK ("CLKFBOUT"), .COMPENSATION ("EXTERNAL"), .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT (12), + .CLKFBOUT_MULT (28), .CLKFBOUT_PHASE (0.000), - .CLKOUT0_DIVIDE (6), + .CLKOUT0_DIVIDE (14), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), - .CLKIN_PERIOD (30.0), - .REF_JITTER (0.008)) + .CLKIN_PERIOD (30.000), + .REF_JITTER (0.010)) pll_base_inst // Output clocks (.CLKFBOUT (clkfbout), @@ -130,7 +131,8 @@ module CLK .CLKOUT3 (clkout3_unused), .CLKOUT4 (clkout4_unused), .CLKOUT5 (clkout5_unused), - .LOCKED (locked_unused), + // Status and control signals + .LOCKED (LOCKED), .RST (1'b0), // Input clock control .CLKFBIN (clkfb_in_buf_out), diff --git a/fpga/ipcore_dir/CLK.veo b/fpga/ipcore_dir/PLL.veo similarity index 93% rename from fpga/ipcore_dir/CLK.veo rename to fpga/ipcore_dir/PLL.veo index 0f5e37c..13bc9d8 100644 --- a/fpga/ipcore_dir/CLK.veo +++ b/fpga/ipcore_dir/PLL.veo @@ -54,12 +54,12 @@ // "Output Output Phase Duty Pk-to-Pk Phase" // "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" //---------------------------------------------------------------------------- -// CLK_OUT1____66.667______0.000______50.0______300.590____267.927 +// CLK_OUT1____66.667______0.000______50.0______252.559____182.342 // //---------------------------------------------------------------------------- // "Input Clock Freq (MHz) Input Jitter (UI)" //---------------------------------------------------------------------------- -// __primary_________33.3333___________0.00833333333333 +// __primary_________33.3333____________0.010 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections @@ -67,11 +67,13 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG - CLK instance_name + PLL instance_name (// Clock in ports .CLKIN(CLKIN), // IN .CLKFB_IN(CLKFB_IN), // IN // Clock out ports .FSBCLK(FSBCLK), // OUT - .CLKFB_OUT(CLKFB_OUT)); // OUT + .CLKFB_OUT(CLKFB_OUT), // OUT + // Status and control signals + .LOCKED(LOCKED)); // OUT // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/fpga/ipcore_dir/CLK.xco b/fpga/ipcore_dir/PLL.xco similarity index 83% rename from fpga/ipcore_dir/CLK.xco rename to fpga/ipcore_dir/PLL.xco index 69a24b6..b81c18e 100644 --- a/fpga/ipcore_dir/CLK.xco +++ b/fpga/ipcore_dir/PLL.xco @@ -1,7 +1,7 @@ ############################################################## # # Xilinx Core Generator version 14.7 -# Date: Fri Oct 29 21:49:29 2021 +# Date: Sun Oct 31 17:58:14 2021 # ############################################################## # @@ -43,13 +43,13 @@ CSET calc_done=DONE CSET clk_in_sel_port=CLK_IN_SEL CSET clk_out1_port=FSBCLK CSET clk_out1_use_fine_ps_gui=false -CSET clk_out2_port=RAMCLK +CSET clk_out2_port=CLK_OUT2 CSET clk_out2_use_fine_ps_gui=false -CSET clk_out3_port=CPUCLK +CSET clk_out3_port=CLK_OUT3 CSET clk_out3_use_fine_ps_gui=false -CSET clk_out4_port=C80M +CSET clk_out4_port=CLK_OUT4 CSET clk_out4_use_fine_ps_gui=false -CSET clk_out5_port=C50M +CSET clk_out5_port=CLK_OUT5 CSET clk_out5_use_fine_ps_gui=false CSET clk_out6_port=CLK_OUT6 CSET clk_out6_use_fine_ps_gui=false @@ -64,66 +64,66 @@ CSET clkfb_out_n_port=CLKFB_OUT_N CSET clkfb_out_p_port=CLKFB_OUT_P CSET clkfb_out_port=CLKFB_OUT CSET clkfb_stopped_port=CLKFB_STOPPED -CSET clkin1_jitter_ps=250.0 -CSET clkin1_ui_jitter=250.000 -CSET clkin2_jitter_ps=40.0 -CSET clkin2_ui_jitter=100.000 +CSET clkin1_jitter_ps=300.0 +CSET clkin1_ui_jitter=0.010 +CSET clkin2_jitter_ps=100.0 +CSET clkin2_ui_jitter=0.010 CSET clkout1_drives=BUFG CSET clkout1_requested_duty_cycle=50.0 CSET clkout1_requested_out_freq=66.667 CSET clkout1_requested_phase=0.000 CSET clkout2_drives=BUFG CSET clkout2_requested_duty_cycle=50.0 -CSET clkout2_requested_out_freq=33.3333 -CSET clkout2_requested_phase=0 +CSET clkout2_requested_out_freq=33.333 +CSET clkout2_requested_phase=0.000 CSET clkout2_used=false CSET clkout3_drives=BUFG CSET clkout3_requested_duty_cycle=50.0 -CSET clkout3_requested_out_freq=33.3333 -CSET clkout3_requested_phase=-72 +CSET clkout3_requested_out_freq=100.000 +CSET clkout3_requested_phase=0.000 CSET clkout3_used=false CSET clkout4_drives=BUFG CSET clkout4_requested_duty_cycle=50.0 -CSET clkout4_requested_out_freq=33.3333 -CSET clkout4_requested_phase=0 +CSET clkout4_requested_out_freq=100.000 +CSET clkout4_requested_phase=0.000 CSET clkout4_used=false CSET clkout5_drives=BUFG CSET clkout5_requested_duty_cycle=50.0 -CSET clkout5_requested_out_freq=33.3333 +CSET clkout5_requested_out_freq=100.000 CSET clkout5_requested_phase=0.000 CSET clkout5_used=false CSET clkout6_drives=BUFG CSET clkout6_requested_duty_cycle=50.0 -CSET clkout6_requested_out_freq=33.3333 +CSET clkout6_requested_out_freq=100.000 CSET clkout6_requested_phase=0.000 CSET clkout6_used=false CSET clkout7_drives=BUFG CSET clkout7_requested_duty_cycle=50.0 -CSET clkout7_requested_out_freq=33.3333 +CSET clkout7_requested_out_freq=100.000 CSET clkout7_requested_phase=0.000 CSET clkout7_used=false CSET clock_mgr_type=MANUAL -CSET component_name=CLK +CSET component_name=PLL CSET daddr_port=DADDR CSET dclk_port=DCLK -CSET dcm_clk_feedback=1X -CSET dcm_clk_out1_port=CLK0 -CSET dcm_clk_out2_port=CLK2X +CSET dcm_clk_feedback=2X +CSET dcm_clk_out1_port=CLK2X +CSET dcm_clk_out2_port=CLK0 CSET dcm_clk_out3_port=CLKFX -CSET dcm_clk_out4_port=CLKFX -CSET dcm_clk_out5_port=CLKFX +CSET dcm_clk_out4_port=CLK0 +CSET dcm_clk_out5_port=CLK0 CSET dcm_clk_out6_port=CLK0 CSET dcm_clkdv_divide=2.0 CSET dcm_clkfx_divide=1 CSET dcm_clkfx_multiply=4 CSET dcm_clkgen_clk_out1_port=CLKFX CSET dcm_clkgen_clk_out2_port=CLKFX -CSET dcm_clkgen_clk_out3_port=CLKFX180 -CSET dcm_clkgen_clkfx_divide=2 +CSET dcm_clkgen_clk_out3_port=CLKFX +CSET dcm_clkgen_clkfx_divide=1 CSET dcm_clkgen_clkfx_md_max=0.000 -CSET dcm_clkgen_clkfx_multiply=2 +CSET dcm_clkgen_clkfx_multiply=4 CSET dcm_clkgen_clkfxdv_divide=2 -CSET dcm_clkgen_clkin_period=30.303 +CSET dcm_clkgen_clkin_period=10.000 CSET dcm_clkgen_notes=None CSET dcm_clkgen_spread_spectrum=NONE CSET dcm_clkgen_startup_wait=false @@ -144,10 +144,10 @@ CSET feedback_source=FDBK_AUTO_OFFCHIP CSET in_freq_units=Units_MHz CSET in_jitter_units=Units_UI CSET input_clk_stopped_port=INPUT_CLK_STOPPED -CSET jitter_options=PS -CSET jitter_sel=No_Jitter +CSET jitter_options=UI +CSET jitter_sel=Min_O_Jitter CSET locked_port=LOCKED -CSET mmcm_bandwidth=OPTIMIZED +CSET mmcm_bandwidth=HIGH CSET mmcm_clkfbout_mult_f=4.000 CSET mmcm_clkfbout_phase=0.000 CSET mmcm_clkfbout_use_fine_ps=false @@ -195,24 +195,24 @@ CSET override_dcm_clkgen=false CSET override_mmcm=false CSET override_pll=false CSET platform=nt -CSET pll_bandwidth=OPTIMIZED +CSET pll_bandwidth=HIGH CSET pll_clk_feedback=CLKFBOUT -CSET pll_clkfbout_mult=12 +CSET pll_clkfbout_mult=28 CSET pll_clkfbout_phase=0.000 -CSET pll_clkin_period=30.0 -CSET pll_clkout0_divide=6 +CSET pll_clkin_period=30.000 +CSET pll_clkout0_divide=14 CSET pll_clkout0_duty_cycle=0.500 CSET pll_clkout0_phase=0.000 -CSET pll_clkout1_divide=10 +CSET pll_clkout1_divide=12 CSET pll_clkout1_duty_cycle=0.500 CSET pll_clkout1_phase=0.000 -CSET pll_clkout2_divide=10 +CSET pll_clkout2_divide=4 CSET pll_clkout2_duty_cycle=0.500 -CSET pll_clkout2_phase=-72.000 -CSET pll_clkout3_divide=10 +CSET pll_clkout2_phase=0.000 +CSET pll_clkout3_divide=1 CSET pll_clkout3_duty_cycle=0.500 CSET pll_clkout3_phase=0.000 -CSET pll_clkout4_divide=16 +CSET pll_clkout4_divide=1 CSET pll_clkout4_duty_cycle=0.500 CSET pll_clkout4_phase=0.000 CSET pll_clkout5_divide=1 @@ -221,10 +221,10 @@ CSET pll_clkout5_phase=0.000 CSET pll_compensation=EXTERNAL CSET pll_divclk_divide=1 CSET pll_notes=None -CSET pll_ref_jitter=0.008 +CSET pll_ref_jitter=0.010 CSET power_down_port=POWER_DOWN CSET prim_in_freq=33.3333 -CSET prim_in_jitter=0.00833333333333 +CSET prim_in_jitter=0.010 CSET prim_source=Single_ended_clock_capable_pin CSET primary_port=CLKIN CSET primitive=MMCM @@ -236,7 +236,7 @@ CSET psincdec_port=PSINCDEC CSET relative_inclk=REL_PRIMARY CSET reset_port=RESET CSET secondary_in_freq=100.000 -CSET secondary_in_jitter=0.004 +CSET secondary_in_jitter=0.010 CSET secondary_port=CLK_IN2 CSET secondary_source=Single_ended_clock_capable_pin CSET ss_mod_freq=250 @@ -251,7 +251,7 @@ CSET use_freeze=false CSET use_freq_synth=true CSET use_inclk_stopped=false CSET use_inclk_switchover=false -CSET use_locked=false +CSET use_locked=true CSET use_max_i_jitter=false CSET use_min_o_jitter=false CSET use_min_power=false @@ -266,4 +266,4 @@ CSET use_status=false MISC pkg_timestamp=2012-05-10T12:44:55Z # END Extra information GENERATE -# CRC: 51d6f701 +# CRC: 8225559f diff --git a/fpga/ipcore_dir/CLK.xdc b/fpga/ipcore_dir/PLL.xdc similarity index 96% rename from fpga/ipcore_dir/CLK.xdc rename to fpga/ipcore_dir/PLL.xdc index e693d26..7f6c3e0 100644 --- a/fpga/ipcore_dir/CLK.xdc +++ b/fpga/ipcore_dir/PLL.xdc @@ -1,4 +1,4 @@ -# file: CLK.xdc +# file: PLL.xdc # # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. # @@ -50,9 +50,9 @@ # Input clock periods. These duplicate the values entered for the # input clocks. You can use these to time your system #---------------------------------------------------------------- -create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1] +create_clock -name CLK_IN1 -period 30.000 [get_ports CLK_IN1] set_propagated_clock CLK_IN1 -set_input_jitter CLK_IN1 0.25 +set_input_jitter CLK_IN1 0.3 # Derived clock periods. These are commented out because they are diff --git a/fpga/ipcore_dir/PLL.xise b/fpga/ipcore_dir/PLL.xise new file mode 100644 index 0000000..8a82be7 --- /dev/null +++ b/fpga/ipcore_dir/PLL.xise @@ -0,0 +1,403 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ipcore_dir/CLK/clk_wiz_v3_6_readme.txt b/fpga/ipcore_dir/PLL/clk_wiz_v3_6_readme.txt similarity index 100% rename from fpga/ipcore_dir/CLK/clk_wiz_v3_6_readme.txt rename to fpga/ipcore_dir/PLL/clk_wiz_v3_6_readme.txt diff --git a/fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_readme.txt b/fpga/ipcore_dir/PLL/doc/clk_wiz_v3_6_readme.txt similarity index 100% rename from fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_readme.txt rename to fpga/ipcore_dir/PLL/doc/clk_wiz_v3_6_readme.txt diff --git a/fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_vinfo.html b/fpga/ipcore_dir/PLL/doc/clk_wiz_v3_6_vinfo.html similarity index 100% rename from fpga/ipcore_dir/CLK/doc/clk_wiz_v3_6_vinfo.html rename to fpga/ipcore_dir/PLL/doc/clk_wiz_v3_6_vinfo.html diff --git a/fpga/ipcore_dir/CLK/doc/pg065_clk_wiz.pdf b/fpga/ipcore_dir/PLL/doc/pg065_clk_wiz.pdf similarity index 100% rename from fpga/ipcore_dir/CLK/doc/pg065_clk_wiz.pdf rename to fpga/ipcore_dir/PLL/doc/pg065_clk_wiz.pdf diff --git a/fpga/ipcore_dir/CLK/example_design/CLK_exdes.ucf b/fpga/ipcore_dir/PLL/example_design/PLL_exdes.ucf similarity index 96% rename from fpga/ipcore_dir/CLK/example_design/CLK_exdes.ucf rename to fpga/ipcore_dir/PLL/example_design/PLL_exdes.ucf index e0a36c3..3483ae7 100644 --- a/fpga/ipcore_dir/CLK/example_design/CLK_exdes.ucf +++ b/fpga/ipcore_dir/PLL/example_design/PLL_exdes.ucf @@ -1,4 +1,4 @@ -# file: CLK_exdes.ucf +# file: PLL_exdes.ucf # # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. # @@ -51,7 +51,7 @@ # input clocks. You can use these to time your system #---------------------------------------------------------------- NET "CLK_IN1" TNM_NET = "CLK_IN1"; -TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.0 ns HIGH 50% INPUT_JITTER 250.0ps; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 30.000 ns HIGH 50% INPUT_JITTER 300.0ps; # Constraints for external feedback. diff --git a/fpga/ipcore_dir/CLK/example_design/CLK_exdes.v b/fpga/ipcore_dir/PLL/example_design/PLL_exdes.v similarity index 92% rename from fpga/ipcore_dir/CLK/example_design/CLK_exdes.v rename to fpga/ipcore_dir/PLL/example_design/PLL_exdes.v index 53802a9..9f0cfd4 100644 --- a/fpga/ipcore_dir/CLK/example_design/CLK_exdes.v +++ b/fpga/ipcore_dir/PLL/example_design/PLL_exdes.v @@ -1,4 +1,4 @@ -// file: CLK_exdes.v +// file: PLL_exdes.v // // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. // @@ -56,7 +56,7 @@ `timescale 1ps/1ps -module CLK_exdes +module PLL_exdes #( parameter TCQ = 100 ) @@ -68,15 +68,17 @@ module CLK_exdes output [1:1] CLK_OUT, // High bits of counters driven by clocks output COUNT, - output CLKFB_OUT + output CLKFB_OUT, + // Status and control signals + output LOCKED ); // Parameters for the counters //------------------------------- // Counter width localparam C_W = 16; - // Create reset for the counters - wire reset_int = COUNTER_RESET; + // When the clock goes out of lock, reset the counters + wire reset_int = !LOCKED || COUNTER_RESET; reg rst_sync; reg rst_sync_int; @@ -93,13 +95,15 @@ module CLK_exdes // Instantiation of the clocking network //-------------------------------------- - CLK clknetwork + PLL clknetwork (// Clock in ports .CLKIN (CLK_IN1), .CLKFB_IN (CLKFB_IN), // Clock out ports .FSBCLK (clk_int), - .CLKFB_OUT (CLKFB_OUT)); + .CLKFB_OUT (CLKFB_OUT), + // Status and control signals + .LOCKED (LOCKED)); assign clk_n = ~clk; diff --git a/fpga/ipcore_dir/CLK/example_design/CLK_exdes.xdc b/fpga/ipcore_dir/PLL/example_design/PLL_exdes.xdc similarity index 96% rename from fpga/ipcore_dir/CLK/example_design/CLK_exdes.xdc rename to fpga/ipcore_dir/PLL/example_design/PLL_exdes.xdc index ec862c5..f453214 100644 --- a/fpga/ipcore_dir/CLK/example_design/CLK_exdes.xdc +++ b/fpga/ipcore_dir/PLL/example_design/PLL_exdes.xdc @@ -1,4 +1,4 @@ -# file: CLK_exdes.xdc +# file: PLL_exdes.xdc # # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. # @@ -50,9 +50,9 @@ # Input clock periods. These duplicate the values entered for the # input clocks. You can use these to time your system #---------------------------------------------------------------- -create_clock -name CLK_IN1 -period 30.0 [get_ports CLK_IN1] +create_clock -name CLK_IN1 -period 30.000 [get_ports CLK_IN1] set_propagated_clock CLK_IN1 -set_input_jitter CLK_IN1 0.25 +set_input_jitter CLK_IN1 0.3 # FALSE PATH constraint added on COUNTER_RESET set_false_path -from [get_ports "COUNTER_RESET"] diff --git a/fpga/ipcore_dir/CLK/implement/implement.bat b/fpga/ipcore_dir/PLL/implement/implement.bat similarity index 93% rename from fpga/ipcore_dir/CLK/implement/implement.bat rename to fpga/ipcore_dir/PLL/implement/implement.bat index a520f3b..f7a4610 100644 --- a/fpga/ipcore_dir/CLK/implement/implement.bat +++ b/fpga/ipcore_dir/PLL/implement/implement.bat @@ -61,19 +61,19 @@ copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\ REM Synthesize the Verilog Wrapper Files echo 'Synthesizing Clocking Wizard design with XST' xst -ifn xst.scr -move CLK_exdes.ngc results\ +move PLL_exdes.ngc results\ REM Copy the constraints files generated by Coregen echo 'Copying files from constraints directory to results directory' -copy ..\example_design\CLK_exdes.ucf results\ +copy ..\example_design\PLL_exdes.ucf results\ cd results echo 'Running ngdbuild' -ngdbuild -uc CLK_exdes.ucf CLK_exdes +ngdbuild -uc PLL_exdes.ucf PLL_exdes echo 'Running map' -map -timing -pr b CLK_exdes -o mapped.ncd +map -timing -pr b PLL_exdes -o mapped.ncd echo 'Running par' par -w mapped.ncd routed mapped.pcf @@ -85,6 +85,6 @@ echo 'Running design through bitgen' bitgen -w routed echo 'Running netgen to create gate level model for the clocking wizard example design' -netgen -ofmt verilog -sim -sdf_anno false -tm CLK_exdes -w routed.ncd routed.v +netgen -ofmt verilog -sim -sdf_anno false -tm PLL_exdes -w routed.ncd routed.v cd .. diff --git a/fpga/ipcore_dir/CLK/implement/implement.sh b/fpga/ipcore_dir/PLL/implement/implement.sh similarity index 93% rename from fpga/ipcore_dir/CLK/implement/implement.sh rename to fpga/ipcore_dir/PLL/implement/implement.sh index 1d78066..08e5f51 100644 --- a/fpga/ipcore_dir/CLK/implement/implement.sh +++ b/fpga/ipcore_dir/PLL/implement/implement.sh @@ -62,19 +62,19 @@ cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/ # Synthesize the Verilog Wrapper Files echo 'Synthesizing Clocking Wizard design with XST' xst -ifn xst.scr -mv CLK_exdes.ngc results/ +mv PLL_exdes.ngc results/ # Copy the constraints files generated by Coregen echo 'Copying files from constraints directory to results directory' -cp ../example_design/CLK_exdes.ucf results/ +cp ../example_design/PLL_exdes.ucf results/ cd results echo 'Running ngdbuild' -ngdbuild -uc CLK_exdes.ucf CLK_exdes +ngdbuild -uc PLL_exdes.ucf PLL_exdes echo 'Running map' -map -timing CLK_exdes -o mapped.ncd +map -timing PLL_exdes -o mapped.ncd echo 'Running par' par -w mapped.ncd routed mapped.pcf @@ -86,6 +86,6 @@ echo 'Running design through bitgen' bitgen -w routed echo 'Running netgen to create gate level model for the clocking wizard example design' -netgen -ofmt verilog -sim -sdf_anno false -tm CLK_exdes -w routed.ncd routed.v +netgen -ofmt verilog -sim -sdf_anno false -tm PLL_exdes -w routed.ncd routed.v cd .. diff --git a/fpga/ipcore_dir/CLK/implement/planAhead_ise.bat b/fpga/ipcore_dir/PLL/implement/planAhead_ise.bat similarity index 100% rename from fpga/ipcore_dir/CLK/implement/planAhead_ise.bat rename to fpga/ipcore_dir/PLL/implement/planAhead_ise.bat diff --git a/fpga/ipcore_dir/CLK/implement/planAhead_ise.sh b/fpga/ipcore_dir/PLL/implement/planAhead_ise.sh similarity index 100% rename from fpga/ipcore_dir/CLK/implement/planAhead_ise.sh rename to fpga/ipcore_dir/PLL/implement/planAhead_ise.sh diff --git a/fpga/ipcore_dir/CLK/implement/planAhead_ise.tcl b/fpga/ipcore_dir/PLL/implement/planAhead_ise.tcl similarity index 95% rename from fpga/ipcore_dir/CLK/implement/planAhead_ise.tcl rename to fpga/ipcore_dir/PLL/implement/planAhead_ise.tcl index 0c78784..37642dc 100644 --- a/fpga/ipcore_dir/CLK/implement/planAhead_ise.tcl +++ b/fpga/ipcore_dir/PLL/implement/planAhead_ise.tcl @@ -48,8 +48,8 @@ # set projDir [file dirname [info script]] -set projName CLK -set topName CLK_exdes +set projName PLL +set topName PLL_exdes set device xc6slx9ftg256-2 create_project $projName $projDir/results/$projName -part $device @@ -58,12 +58,12 @@ set_property design_mode RTL [get_filesets sources_1] ## Source files #set verilogSources [glob $srcDir/*.v] -import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/CLK_exdes.v -import_files -fileset [get_filesets sources_1] -force -norecurse ../../../CLK.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/PLL_exdes.v +import_files -fileset [get_filesets sources_1] -force -norecurse ../../../PLL.v #UCF file -import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/CLK_exdes.ucf +import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/PLL_exdes.ucf set_property top $topName [get_property srcset [current_run]] diff --git a/fpga/ipcore_dir/CLK/implement/planAhead_rdn.bat b/fpga/ipcore_dir/PLL/implement/planAhead_rdn.bat similarity index 100% rename from fpga/ipcore_dir/CLK/implement/planAhead_rdn.bat rename to fpga/ipcore_dir/PLL/implement/planAhead_rdn.bat diff --git a/fpga/ipcore_dir/CLK/implement/planAhead_rdn.sh b/fpga/ipcore_dir/PLL/implement/planAhead_rdn.sh similarity index 100% rename from fpga/ipcore_dir/CLK/implement/planAhead_rdn.sh rename to fpga/ipcore_dir/PLL/implement/planAhead_rdn.sh diff --git a/fpga/ipcore_dir/CLK/implement/planAhead_rdn.tcl b/fpga/ipcore_dir/PLL/implement/planAhead_rdn.tcl similarity index 88% rename from fpga/ipcore_dir/CLK/implement/planAhead_rdn.tcl rename to fpga/ipcore_dir/PLL/implement/planAhead_rdn.tcl index 350f5b3..f41b391 100644 --- a/fpga/ipcore_dir/CLK/implement/planAhead_rdn.tcl +++ b/fpga/ipcore_dir/PLL/implement/planAhead_rdn.tcl @@ -48,22 +48,22 @@ # set device xc6slx9ftg256-2 -set projName CLK -set design CLK +set projName PLL +set design PLL set projDir [file dirname [info script]] create_project $projName $projDir/results/$projName -part $device -force set_property design_mode RTL [current_fileset -srcset] -set top_module CLK_exdes -set_property top CLK_exdes [get_property srcset [current_run]] -add_files -norecurse {../../../CLK.v} -add_files -norecurse {../../example_design/CLK_exdes.v} -import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/CLK_exdes.xdc} +set top_module PLL_exdes +set_property top PLL_exdes [get_property srcset [current_run]] +add_files -norecurse {../../../PLL.v} +add_files -norecurse {../../example_design/PLL_exdes.v} +import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/PLL_exdes.xdc} synth_design opt_design place_design route_design -write_sdf -rename_top_module CLK_exdes -file routed.sdf -write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module CLK_exdes -file routed.v +write_sdf -rename_top_module PLL_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module PLL_exdes -file routed.v report_timing -nworst 30 -path_type full -file routed.twr report_drc -file report.drc write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit diff --git a/fpga/ipcore_dir/PLL/implement/xst.prj b/fpga/ipcore_dir/PLL/implement/xst.prj new file mode 100644 index 0000000..ef5e701 --- /dev/null +++ b/fpga/ipcore_dir/PLL/implement/xst.prj @@ -0,0 +1,2 @@ +verilog work ../../PLL.v +verilog work ../example_design/PLL_exdes.v diff --git a/fpga/ipcore_dir/CLK/implement/xst.scr b/fpga/ipcore_dir/PLL/implement/xst.scr similarity index 80% rename from fpga/ipcore_dir/CLK/implement/xst.scr rename to fpga/ipcore_dir/PLL/implement/xst.scr index da9dce2..94b103e 100644 --- a/fpga/ipcore_dir/CLK/implement/xst.scr +++ b/fpga/ipcore_dir/PLL/implement/xst.scr @@ -1,9 +1,9 @@ run -ifmt MIXED --top CLK_exdes +-top PLL_exdes -p xc6slx9-ftg256-2 -ifn xst.prj --ofn CLK_exdes +-ofn PLL_exdes -keep_hierarchy soft -equivalent_register_removal no -max_fanout 65535 diff --git a/fpga/ipcore_dir/CLK/simulation/CLK_tb.v b/fpga/ipcore_dir/PLL/simulation/PLL_tb.v similarity index 94% rename from fpga/ipcore_dir/CLK/simulation/CLK_tb.v rename to fpga/ipcore_dir/PLL/simulation/PLL_tb.v index 5843f60..d09b379 100644 --- a/fpga/ipcore_dir/CLK/simulation/CLK_tb.v +++ b/fpga/ipcore_dir/PLL/simulation/PLL_tb.v @@ -1,4 +1,4 @@ -// file: CLK_tb.v +// file: PLL_tb.v // // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. // @@ -57,9 +57,9 @@ `timescale 1ps/1ps -`define wait_lock @(posedge dut.clknetwork.pll_base_inst.LOCKED) +`define wait_lock @(posedge LOCKED) -module CLK_tb (); +module PLL_tb (); // Clock to Q delay of 100ps localparam TCQ = 100; @@ -71,7 +71,7 @@ module CLK_tb (); // how many cycles to run localparam COUNT_PHASE = 1024; // we'll be using the period in many locations - localparam time PER1 = 30.0*ONE_NS; + localparam time PER1 = 30.000*ONE_NS; localparam time PER1_1 = PER1/2; localparam time PER1_2 = PER1 - PER1/2; @@ -83,6 +83,8 @@ module CLK_tb (); // Connect the feedback wire CLKFB_OUT; wire CLKFB_IN = CLKFB_OUT; + // Status and control signals + wire LOCKED; reg COUNTER_RESET = 0; wire [1:1] CLK_OUT; //Freq Check using the M & D values setting and actual Frequency generated @@ -119,7 +121,7 @@ wire [1:1] CLK_OUT; // Instantiation of the example design containing the clock // network and sampling counters //--------------------------------------------------------- - CLK_exdes + PLL_exdes #( .TCQ (TCQ) ) dut @@ -131,7 +133,9 @@ wire [1:1] CLK_OUT; .CLK_OUT (CLK_OUT), // High bits of the counters .COUNT (COUNT), - .CLKFB_OUT (CLKFB_OUT)); + .CLKFB_OUT (CLKFB_OUT), + // Status and control signals + .LOCKED (LOCKED)); // Freq Check diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simcmds.tcl b/fpga/ipcore_dir/PLL/simulation/functional/simcmds.tcl similarity index 77% rename from fpga/ipcore_dir/CLK/simulation/functional/simcmds.tcl rename to fpga/ipcore_dir/PLL/simulation/functional/simcmds.tcl index 4998299..4494d25 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simcmds.tcl +++ b/fpga/ipcore_dir/PLL/simulation/functional/simcmds.tcl @@ -2,7 +2,7 @@ # create the simulation script vcd dumpfile isim.vcd -vcd dumpvars -m /CLK_tb -l 0 +vcd dumpvars -m /PLL_tb -l 0 wave add / run 50000ns quit diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.bat b/fpga/ipcore_dir/PLL/simulation/functional/simulate_isim.bat similarity index 91% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.bat rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_isim.bat index 9a7e252..5df66f8 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.bat +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_isim.bat @@ -48,12 +48,12 @@ REM PART OF THIS FILE AT ALL TIMES. REM vlogcomp -work work %XILINX%\verilog\src\glbl.v -vlogcomp -work work ..\..\..\CLK.v -vlogcomp -work work ..\..\example_design\CLK_exdes.v -vlogcomp -work work ..\CLK_tb.v +vlogcomp -work work ..\..\..\PLL.v +vlogcomp -work work ..\..\example_design\PLL_exdes.v +vlogcomp -work work ..\PLL_tb.v REM compile the project -fuse work.CLK_tb work.glbl -L unisims_ver -o CLK_isim.exe +fuse work.PLL_tb work.glbl -L unisims_ver -o PLL_isim.exe REM run the simulation script -.\CLK_isim.exe -gui -tclbatch simcmds.tcl +.\PLL_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.sh b/fpga/ipcore_dir/PLL/simulation/functional/simulate_isim.sh similarity index 91% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.sh rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_isim.sh index 91882e9..66d0ff6 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_isim.sh +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_isim.sh @@ -50,12 +50,12 @@ # nt # create the project vlogcomp -work work ${XILINX}/verilog/src/glbl.v -vlogcomp -work work ../../../CLK.v -vlogcomp -work work ../../example_design/CLK_exdes.v -vlogcomp -work work ../CLK_tb.v +vlogcomp -work work ../../../PLL.v +vlogcomp -work work ../../example_design/PLL_exdes.v +vlogcomp -work work ../PLL_tb.v # compile the project -fuse work.CLK_tb work.glbl -L unisims_ver -o CLK_isim.exe +fuse work.PLL_tb work.glbl -L unisims_ver -o PLL_isim.exe # run the simulation script -./CLK_isim.exe -gui -tclbatch simcmds.tcl +./PLL_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.bat b/fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.bat similarity index 92% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.bat rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.bat index 5ef414c..7a1ba59 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.bat +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.bat @@ -52,10 +52,10 @@ vlib work REM compile all of the files vlog -work work %XILINX%\verilog\src\glbl.v -vlog -work work ..\..\..\CLK.v -vlog -work work ..\..\example_design\CLK_exdes.v -vlog -work work ..\CLK_tb.v +vlog -work work ..\..\..\PLL.v +vlog -work work ..\..\example_design\PLL_exdes.v +vlog -work work ..\PLL_tb.v REM run the simulation -vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.CLK_tb work.glbl +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.PLL_tb work.glbl diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.do b/fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.do similarity index 92% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.do rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.do index d093124..1577984 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.do +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.do @@ -53,13 +53,13 @@ vlib work # compile all of the files vlog -work work $env(XILINX)/verilog/src/glbl.v -vlog -work work ../../../CLK.v -vlog -work work ../../example_design/CLK_exdes.v -vlog -work work ../CLK_tb.v +vlog -work work ../../../PLL.v +vlog -work work ../../example_design/PLL_exdes.v +vlog -work work ../PLL_tb.v # run the simulation -vsim -t ps -voptargs="+acc" -L unisims_ver work.CLK_tb work.glbl +vsim -t ps -voptargs="+acc" -L unisims_ver work.PLL_tb work.glbl do wave.do -log CLK_tb/dut/counter +log PLL_tb/dut/counter log -r /* run 50000ns diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.sh b/fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.sh similarity index 92% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.sh rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.sh index 8ea4efb..91906b1 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_mti.sh +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_mti.sh @@ -53,9 +53,9 @@ vlib work # compile all of the files vlog -work work $XILINX/verilog/src/glbl.v -vlog -work work ../../../CLK.v -vlog -work work ../../example_design/CLK_exdes.v -vlog -work work ../CLK_tb.v +vlog -work work ../../../PLL.v +vlog -work work ../../example_design/PLL_exdes.v +vlog -work work ../PLL_tb.v # run the simulation -vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.CLK_tb work.glbl +vsim -c -t ps -voptargs="+acc" -L secureip -L unisims_ver work.PLL_tb work.glbl diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_ncsim.sh b/fpga/ipcore_dir/PLL/simulation/functional/simulate_ncsim.sh similarity index 91% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_ncsim.sh rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_ncsim.sh index 54cc86a..95675c3 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_ncsim.sh +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_ncsim.sh @@ -53,10 +53,10 @@ mkdir work # compile all of the files ncvlog -work work ${XILINX}/verilog/src/glbl.v -ncvlog -work work ../../../CLK.v -ncvlog -work work ../../example_design/CLK_exdes.v -ncvlog -work work ../CLK_tb.v +ncvlog -work work ../../../PLL.v +ncvlog -work work ../../example_design/PLL_exdes.v +ncvlog -work work ../PLL_tb.v # elaborate and run the simulation -ncelab -work work -access +wc work.CLK_tb work.glbl -ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.CLK_tb +ncelab -work work -access +wc work.PLL_tb work.glbl +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.PLL_tb diff --git a/fpga/ipcore_dir/CLK/simulation/functional/simulate_vcs.sh b/fpga/ipcore_dir/PLL/simulation/functional/simulate_vcs.sh similarity index 95% rename from fpga/ipcore_dir/CLK/simulation/functional/simulate_vcs.sh rename to fpga/ipcore_dir/PLL/simulation/functional/simulate_vcs.sh index b7b3716..37d55b3 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/simulate_vcs.sh +++ b/fpga/ipcore_dir/PLL/simulation/functional/simulate_vcs.sh @@ -58,12 +58,12 @@ rm -rf simv* csrc DVEfiles AN.DB # [63:0] from time vlogan -sverilog \ ${XILINX}/verilog/src/glbl.v \ - ../../../CLK.v \ - ../../example_design/CLK_exdes.v \ - ../CLK_tb.v + ../../../PLL.v \ + ../../example_design/PLL_exdes.v \ + ../PLL_tb.v # prepare the simulation -vcs +vcs+lic+wait -debug CLK_tb glbl +vcs +vcs+lic+wait -debug PLL_tb glbl # run the simulation ./simv -ucli -i ucli_commands.key diff --git a/fpga/ipcore_dir/CLK/simulation/functional/ucli_commands.key b/fpga/ipcore_dir/PLL/simulation/functional/ucli_commands.key similarity index 53% rename from fpga/ipcore_dir/CLK/simulation/functional/ucli_commands.key rename to fpga/ipcore_dir/PLL/simulation/functional/ucli_commands.key index ce8b641..85fccfd 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/ucli_commands.key +++ b/fpga/ipcore_dir/PLL/simulation/functional/ucli_commands.key @@ -1,5 +1,5 @@ call {$vcdpluson} -call {$vcdplusmemon(CLK_tb.dut.counter)} +call {$vcdplusmemon(PLL_tb.dut.counter)} run call {$vcdplusclose} quit diff --git a/fpga/ipcore_dir/PLL/simulation/functional/vcs_session.tcl b/fpga/ipcore_dir/PLL/simulation/functional/vcs_session.tcl new file mode 100644 index 0000000..e251b46 --- /dev/null +++ b/fpga/ipcore_dir/PLL/simulation/functional/vcs_session.tcl @@ -0,0 +1,17 @@ +gui_open_window Wave +gui_sg_create PLL_group +gui_list_add_group -id Wave.1 {PLL_group} +gui_sg_addsignal -group PLL_group {PLL_tb.test_phase} +gui_set_radix -radix {ascii} -signals {PLL_tb.test_phase} +gui_sg_addsignal -group PLL_group {{Input_clocks}} -divider +gui_sg_addsignal -group PLL_group {PLL_tb.CLK_IN1} +gui_sg_addsignal -group PLL_group {{Output_clocks}} -divider +gui_sg_addsignal -group PLL_group {PLL_tb.dut.clk} +gui_list_expand -id Wave.1 PLL_tb.dut.clk +gui_sg_addsignal -group PLL_group {{Status_control}} -divider +gui_sg_addsignal -group PLL_group {PLL_tb.LOCKED} +gui_sg_addsignal -group PLL_group {{Counters}} -divider +gui_sg_addsignal -group PLL_group {PLL_tb.COUNT} +gui_sg_addsignal -group PLL_group {PLL_tb.dut.counter} +gui_list_expand -id Wave.1 PLL_tb.dut.counter +gui_zoom -window Wave.1 -full diff --git a/fpga/ipcore_dir/CLK/simulation/functional/wave.do b/fpga/ipcore_dir/PLL/simulation/functional/wave.do similarity index 85% rename from fpga/ipcore_dir/CLK/simulation/functional/wave.do rename to fpga/ipcore_dir/PLL/simulation/functional/wave.do index a402293..fcd5332 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/wave.do +++ b/fpga/ipcore_dir/PLL/simulation/functional/wave.do @@ -47,11 +47,13 @@ # PART OF THIS FILE AT ALL TIMES. # -add wave -noupdate -format Literal -radix ascii /CLK_tb/test_phase +add wave -noupdate -format Literal -radix ascii /PLL_tb/test_phase add wave -noupdate -divider {Input clocks} -add wave -noupdate -format Logic /CLK_tb/CLK_IN1 +add wave -noupdate -format Logic /PLL_tb/CLK_IN1 add wave -noupdate -divider {Output clocks} -add wave -noupdate -format Logic /CLK_tb/dut/clk +add wave -noupdate -format Logic /PLL_tb/dut/clk +add wave -noupdate -divider Status/control +add wave -noupdate -format Logic /PLL_tb/LOCKED add wave -noupdate -divider Counters -add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/COUNT -add wave -noupdate -format Literal -radix hexadecimal /CLK_tb/dut/counter +add wave -noupdate -format Literal -radix hexadecimal /PLL_tb/COUNT +add wave -noupdate -format Literal -radix hexadecimal /PLL_tb/dut/counter diff --git a/fpga/ipcore_dir/CLK/simulation/functional/wave.sv b/fpga/ipcore_dir/PLL/simulation/functional/wave.sv similarity index 89% rename from fpga/ipcore_dir/CLK/simulation/functional/wave.sv rename to fpga/ipcore_dir/PLL/simulation/functional/wave.sv index cfbe893..e928f63 100644 --- a/fpga/ipcore_dir/CLK/simulation/functional/wave.sv +++ b/fpga/ipcore_dir/PLL/simulation/functional/wave.sv @@ -54,8 +54,8 @@ if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536 window target "Design Browser 1" on browser using {Design Browser 1} browser set \ - -scope nc::CLK_tb -browser yview see nc::CLK_tb + -scope nc::PLL_tb +browser yview see nc::PLL_tb browser timecontrol set -lock 0 if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} { @@ -81,7 +81,7 @@ catch {group new -name {Output clocks} -overlay 0} catch {group new -name {Status/control} -overlay 0} catch {group new -name {Counters} -overlay 0} -set id [waveform add -signals [list {nc::CLK_tb.CLK_IN1}]] +set id [waveform add -signals [list {nc::PLL_tb.CLK_IN1}]] group using {Output clocks} group set -overlay 0 @@ -89,7 +89,7 @@ group set -comment {} group clear 0 end group insert \ - {CLK_tb.dut.clk} \ + {PLL_tb.dut.clk} \ group using {Counters} group set -overlay 0 @@ -97,12 +97,20 @@ group set -comment {} group clear 0 end group insert \ - {CLK_tb.dut.counter} \ + {PLL_tb.dut.counter} \ + +group using {Status/control} +group set -overlay 0 +group set -comment {} +group clear 0 end + +group insert \ + {nc::PLL_tb.LOCKED} -set id [waveform add -signals [list {nc::CLK_tb.COUNT} ]] +set id [waveform add -signals [list {nc::PLL_tb.COUNT} ]] -set id [waveform add -signals [list {nc::CLK_tb.test_phase} ]] +set id [waveform add -signals [list {nc::PLL_tb.test_phase} ]] waveform format $id -radix %a set groupId [waveform add -groups {{Input clocks}}] diff --git a/fpga/ipcore_dir/CLK/simulation/timing/CLK_tb.v b/fpga/ipcore_dir/PLL/simulation/timing/PLL_tb.v similarity index 88% rename from fpga/ipcore_dir/CLK/simulation/timing/CLK_tb.v rename to fpga/ipcore_dir/PLL/simulation/timing/PLL_tb.v index e5533f3..a344f75 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/CLK_tb.v +++ b/fpga/ipcore_dir/PLL/simulation/timing/PLL_tb.v @@ -1,4 +1,4 @@ -// file: CLK_tb.v +// file: PLL_tb.v // // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. // @@ -57,8 +57,9 @@ `timescale 1ps/1ps +`define wait_lock @(posedge LOCKED) -module CLK_tb (); +module PLL_tb (); // Clock to Q delay of 100ps localparam TCQ = 100; @@ -70,7 +71,7 @@ module CLK_tb (); // how many cycles to run localparam COUNT_PHASE = 1024; // we'll be using the period in many locations - localparam time PER1 = 30.0*ONE_NS; + localparam time PER1 = 30.000*ONE_NS; localparam time PER1_1 = PER1/2; localparam time PER1_2 = PER1 - PER1/2; @@ -82,6 +83,8 @@ module CLK_tb (); // Connect the feedback wire CLKFB_OUT; wire CLKFB_IN = CLKFB_OUT; + // Status and control signals + wire LOCKED; reg COUNTER_RESET = 0; wire [1:1] CLK_OUT; //Freq Check using the M & D values setting and actual Frequency generated @@ -103,7 +106,7 @@ wire [1:1] CLK_OUT; $display ("Timing checks are not valid"); COUNTER_RESET = 0; test_phase = "wait lock"; - #(PER1*50); + `wait_lock; #(PER1*6); COUNTER_RESET = 1; #(PER1*19.5) @@ -119,11 +122,21 @@ wire [1:1] CLK_OUT; end + always@(posedge CLK_IN1) begin + timeout_counter <= timeout_counter + 1'b1; + if (timeout_counter == 14'b10000000000000) begin + if (LOCKED != 1'b1) begin + $display("ERROR : NO LOCK signal"); + $display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1); + $finish; + end + end + end // Instantiation of the example design containing the clock // network and sampling counters //--------------------------------------------------------- - CLK_exdes + PLL_exdes dut (// Clock in ports .CLK_IN1 (CLK_IN1), @@ -133,7 +146,9 @@ wire [1:1] CLK_OUT; .CLK_OUT (CLK_OUT), // High bits of the counters .COUNT (COUNT), - .CLKFB_OUT (CLKFB_OUT)); + .CLKFB_OUT (CLKFB_OUT), + // Status and control signals + .LOCKED (LOCKED)); // Freq Check diff --git a/fpga/ipcore_dir/CLK/simulation/timing/sdf_cmd_file b/fpga/ipcore_dir/PLL/simulation/timing/sdf_cmd_file similarity index 75% rename from fpga/ipcore_dir/CLK/simulation/timing/sdf_cmd_file rename to fpga/ipcore_dir/PLL/simulation/timing/sdf_cmd_file index 3402a10..d970635 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/sdf_cmd_file +++ b/fpga/ipcore_dir/PLL/simulation/timing/sdf_cmd_file @@ -1,2 +1,2 @@ COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X", -SCOPE = CLK_tb.dut; +SCOPE = PLL_tb.dut; diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simcmds.tcl b/fpga/ipcore_dir/PLL/simulation/timing/simcmds.tcl similarity index 78% rename from fpga/ipcore_dir/CLK/simulation/timing/simcmds.tcl rename to fpga/ipcore_dir/PLL/simulation/timing/simcmds.tcl index b70cdac..f18f562 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simcmds.tcl +++ b/fpga/ipcore_dir/PLL/simulation/timing/simcmds.tcl @@ -2,7 +2,7 @@ # create the simulation script vcd dumpfile isim.vcd -vcd dumpvars -m /CLK_tb -l 0 +vcd dumpvars -m /PLL_tb -l 0 wave add / run 50000ns quit diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simulate_isim.sh b/fpga/ipcore_dir/PLL/simulation/timing/simulate_isim.sh similarity index 92% rename from fpga/ipcore_dir/CLK/simulation/timing/simulate_isim.sh rename to fpga/ipcore_dir/PLL/simulation/timing/simulate_isim.sh index 93a7233..44e7ab6 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simulate_isim.sh +++ b/fpga/ipcore_dir/PLL/simulation/timing/simulate_isim.sh @@ -50,13 +50,13 @@ # create the project vlogcomp -work work ${XILINX}/verilog/src/glbl.v vlogcomp -work work ../../implement/results/routed.v -vlogcomp -work work CLK_tb.v +vlogcomp -work work PLL_tb.v # compile the project -fuse work.CLK_tb work.glbl -L secureip -L simprims_ver -o CLK_isim.exe +fuse work.PLL_tb work.glbl -L secureip -L simprims_ver -o PLL_isim.exe # run the simulation script -./CLK_isim.exe -tclbatch simcmds.tcl -sdfmax /CLK_tb/dut=../../implement/results/routed.sdf +./PLL_isim.exe -tclbatch simcmds.tcl -sdfmax /PLL_tb/dut=../../implement/results/routed.sdf # run the simulation script -#./CLK_isim.exe -gui -tclbatch simcmds.tcl +#./PLL_isim.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.bat b/fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.bat similarity index 95% rename from fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.bat rename to fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.bat index ecf6c94..5add906 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.bat +++ b/fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.bat @@ -53,7 +53,7 @@ vlib work REM compile all of the files vlog -work work %XILINX%\verilog\src\glbl.v vlog -work work ..\..\implement\results\routed.v -vlog -work work CLK_tb.v +vlog -work work PLL_tb.v REM run the simulation -vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.CLK_tb work.glbl +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax PLL_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.PLL_tb work.glbl diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.do b/fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.do similarity index 95% rename from fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.do rename to fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.do index d28ed7b..e4eb9d1 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.do +++ b/fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.do @@ -54,10 +54,10 @@ vlib work # compile all of the files vlog -work work $env(XILINX)/verilog/src/glbl.v vlog -work work ../../implement/results/routed.v -vlog -work work CLK_tb.v +vlog -work work PLL_tb.v # run the simulation -vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb/dut=../../implement/results/routed.sdf +no_notifier work.CLK_tb work.glbl +vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax PLL_tb/dut=../../implement/results/routed.sdf +no_notifier work.PLL_tb work.glbl #do wave.do #log -r /* run 50000ns diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.sh b/fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.sh similarity index 94% rename from fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.sh rename to fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.sh index a02888d..63b1cf7 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simulate_mti.sh +++ b/fpga/ipcore_dir/PLL/simulation/timing/simulate_mti.sh @@ -55,7 +55,7 @@ vlib work # compile all of the files vlog -work work $XILINX/verilog/src/glbl.v vlog -work work ../../implement/results/routed.v -vlog -work work CLK_tb.v +vlog -work work PLL_tb.v # run the simulation -vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax CLK_tb/dut=../../implement/results/routed.sdf +no_notifier work.CLK_tb work.glbl +vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprims_ver -sdfmax PLL_tb/dut=../../implement/results/routed.sdf +no_notifier work.PLL_tb work.glbl diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simulate_ncsim.sh b/fpga/ipcore_dir/PLL/simulation/timing/simulate_ncsim.sh similarity index 94% rename from fpga/ipcore_dir/CLK/simulation/timing/simulate_ncsim.sh rename to fpga/ipcore_dir/PLL/simulation/timing/simulate_ncsim.sh index b00eac4..eabc738 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simulate_ncsim.sh +++ b/fpga/ipcore_dir/PLL/simulation/timing/simulate_ncsim.sh @@ -54,11 +54,11 @@ mkdir work # compile all of the files ncvlog -work work ${XILINX}/verilog/src/glbl.v ncvlog -work work ../../implement/results/routed.v -ncvlog -work work CLK_tb.v +ncvlog -work work PLL_tb.v # elaborate and run the simulation ncsdfc ../../implement/results/routed.sdf -ncelab -work work -access +wc -pulse_r 10 -nonotifier work.CLK_tb work.glbl -sdf_cmd_file sdf_cmd_file -ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.CLK_tb +ncelab -work work -access +wc -pulse_r 10 -nonotifier work.PLL_tb work.glbl -sdf_cmd_file sdf_cmd_file +ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.PLL_tb diff --git a/fpga/ipcore_dir/CLK/simulation/timing/simulate_vcs.sh b/fpga/ipcore_dir/PLL/simulation/timing/simulate_vcs.sh similarity index 94% rename from fpga/ipcore_dir/CLK/simulation/timing/simulate_vcs.sh rename to fpga/ipcore_dir/PLL/simulation/timing/simulate_vcs.sh index bb19a19..b8c3ddb 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/simulate_vcs.sh +++ b/fpga/ipcore_dir/PLL/simulation/timing/simulate_vcs.sh @@ -57,13 +57,13 @@ rm -rf simv* csrc DVEfiles AN.DB # localparam for the periods in the testbench file to # [63:0] from time vlogan -sverilog \ - CLK_tb.v \ + PLL_tb.v \ ../../implement/results/routed.v # prepare the simulation -vcs -sdf max:CLK_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ - +libext+.v -debug CLK_tb.v ../../implement/results/routed.v +vcs -sdf max:PLL_exdes:../../implement/results/routed.sdf +v2k -y $XILINX/verilog/src/simprims \ + +libext+.v -debug PLL_tb.v ../../implement/results/routed.v # run the simulation ./simv -ucli -i ucli_commands.key diff --git a/fpga/ipcore_dir/CLK/simulation/timing/ucli_commands.key b/fpga/ipcore_dir/PLL/simulation/timing/ucli_commands.key similarity index 100% rename from fpga/ipcore_dir/CLK/simulation/timing/ucli_commands.key rename to fpga/ipcore_dir/PLL/simulation/timing/ucli_commands.key diff --git a/fpga/ipcore_dir/CLK/simulation/timing/vcs_session.tcl b/fpga/ipcore_dir/PLL/simulation/timing/vcs_session.tcl similarity index 100% rename from fpga/ipcore_dir/CLK/simulation/timing/vcs_session.tcl rename to fpga/ipcore_dir/PLL/simulation/timing/vcs_session.tcl diff --git a/fpga/ipcore_dir/CLK/simulation/timing/wave.do b/fpga/ipcore_dir/PLL/simulation/timing/wave.do similarity index 96% rename from fpga/ipcore_dir/CLK/simulation/timing/wave.do rename to fpga/ipcore_dir/PLL/simulation/timing/wave.do index 1dab840..55f29d8 100644 --- a/fpga/ipcore_dir/CLK/simulation/timing/wave.do +++ b/fpga/ipcore_dir/PLL/simulation/timing/wave.do @@ -49,8 +49,9 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate /CLK_tb/CLK_IN1 -add wave -noupdate /CLK_tb/COUNT +add wave -noupdate /PLL_tb/CLK_IN1 +add wave -noupdate /PLL_tb/COUNT +add wave -noupdate /PLL_tb/LOCKED TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {3223025 ps} 0} configure wave -namecolwidth 238 diff --git a/fpga/ipcore_dir/PLL_flist.txt b/fpga/ipcore_dir/PLL_flist.txt new file mode 100644 index 0000000..e7ff659 --- /dev/null +++ b/fpga/ipcore_dir/PLL_flist.txt @@ -0,0 +1,55 @@ +# Output products list for +PLL.asy +PLL.gise +PLL.sym +PLL.ucf +PLL.v +PLL.veo +PLL.xco +PLL.xdc +PLL.xise +PLL\clk_wiz_v3_6_readme.txt +PLL\doc\clk_wiz_v3_6_readme.txt +PLL\doc\clk_wiz_v3_6_vinfo.html +PLL\doc\pg065_clk_wiz.pdf +PLL\example_design\PLL_exdes.ucf +PLL\example_design\PLL_exdes.v +PLL\example_design\PLL_exdes.xdc +PLL\implement\implement.bat +PLL\implement\implement.sh +PLL\implement\planAhead_ise.bat +PLL\implement\planAhead_ise.sh +PLL\implement\planAhead_ise.tcl +PLL\implement\planAhead_rdn.bat +PLL\implement\planAhead_rdn.sh +PLL\implement\planAhead_rdn.tcl +PLL\implement\xst.prj +PLL\implement\xst.scr +PLL\simulation\PLL_tb.v +PLL\simulation\functional\simcmds.tcl +PLL\simulation\functional\simulate_isim.bat +PLL\simulation\functional\simulate_isim.sh +PLL\simulation\functional\simulate_mti.bat +PLL\simulation\functional\simulate_mti.do +PLL\simulation\functional\simulate_mti.sh +PLL\simulation\functional\simulate_ncsim.sh +PLL\simulation\functional\simulate_vcs.sh +PLL\simulation\functional\ucli_commands.key +PLL\simulation\functional\vcs_session.tcl +PLL\simulation\functional\wave.do +PLL\simulation\functional\wave.sv +PLL\simulation\timing\PLL_tb.v +PLL\simulation\timing\sdf_cmd_file +PLL\simulation\timing\simcmds.tcl +PLL\simulation\timing\simulate_isim.sh +PLL\simulation\timing\simulate_mti.bat +PLL\simulation\timing\simulate_mti.do +PLL\simulation\timing\simulate_mti.sh +PLL\simulation\timing\simulate_ncsim.sh +PLL\simulation\timing\simulate_vcs.sh +PLL\simulation\timing\ucli_commands.key +PLL\simulation\timing\vcs_session.tcl +PLL\simulation\timing\wave.do +PLL_flist.txt +PLL_xmdf.tcl +_xmsgs\pn_parser.xmsgs diff --git a/fpga/ipcore_dir/CLK_xmdf.tcl b/fpga/ipcore_dir/PLL_xmdf.tcl similarity index 82% rename from fpga/ipcore_dir/CLK_xmdf.tcl rename to fpga/ipcore_dir/PLL_xmdf.tcl index 00fb124..14e8193 100644 --- a/fpga/ipcore_dir/CLK_xmdf.tcl +++ b/fpga/ipcore_dir/PLL_xmdf.tcl @@ -1,29 +1,29 @@ # The package naming convention is _xmdf -package provide CLK_xmdf 1.0 +package provide PLL_xmdf 1.0 # This includes some utilities that support common XMDF operations package require utilities_xmdf # Define a namespace for this package. The name of the name space # is _xmdf -namespace eval ::CLK_xmdf { +namespace eval ::PLL_xmdf { # Use this to define any statics } # Function called by client to rebuild the params and port arrays # Optional when the use context does not require the param or ports # arrays to be available. -proc ::CLK_xmdf::xmdfInit { instance } { +proc ::PLL_xmdf::xmdfInit { instance } { # Variable containg name of library into which module is compiled # Recommendation: # Required -utilities_xmdf::xmdfSetData $instance Module Attributes Name CLK +utilities_xmdf::xmdfSetData $instance Module Attributes Name PLL } -# ::CLK_xmdf::xmdfInit +# ::PLL_xmdf::xmdfInit # Function called by client to fill in all the xmdf* data variables # based on the current settings of the parameters -proc ::CLK_xmdf::xmdfApplyParams { instance } { +proc ::PLL_xmdf::xmdfApplyParams { instance } { set fcount 0 # Array containing libraries that are assumed to exist @@ -36,103 +36,103 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/clk_wiz_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/clk_wiz_readme.txt utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/doc/clk_wiz_ds709.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/doc/clk_wiz_ds709.pdf utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/doc/clk_wiz_gsg521.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/doc/clk_wiz_gsg521.pdf utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/implement/implement.bat utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/implement/implement.sh utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/implement/xst.prj utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/implement/xst.scr utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/CLK_tb.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/PLL_tb.v utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/simcmds.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_isim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/simulate_isim.sh utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/simulate_mti.do utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/simulate_ncsim.sh utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/simulate_vcs.sh utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/ucli_commands.key utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/vcs_session.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/wave.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/wave.do utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK/simulation/functional/wave.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL/simulation/functional/wave.sv utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL.asy utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.ejp +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL.ejp utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL.ucf utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL.v utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL.veo utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL.xco utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path CLK_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PLL_xmdf.tcl utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView incr fcount -utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module CLK +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module PLL incr fcount } diff --git a/fpga/ipcore_dir/PrefetchDataRAM.asy b/fpga/ipcore_dir/PrefetchDataRAM.asy new file mode 100644 index 0000000..6a17ea8 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.asy @@ -0,0 +1,41 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 PrefetchDataRAM +RECTANGLE Normal 32 32 544 1376 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName addra[6:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName dina[31:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName ena +PINATTR Polarity IN +LINE Wide 0 208 32 208 +PIN 0 208 LEFT 36 +PINATTR PinName wea[3:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName clka +PINATTR Polarity IN +LINE Wide 0 432 32 432 +PIN 0 432 LEFT 36 +PINATTR PinName addrb[6:0] +PINATTR Polarity IN +LINE Normal 0 496 32 496 +PIN 0 496 LEFT 36 +PINATTR PinName enb +PINATTR Polarity IN +LINE Normal 0 624 32 624 +PIN 0 624 LEFT 36 +PINATTR PinName clkb +PINATTR Polarity IN +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName doutb[31:0] +PINATTR Polarity OUT + diff --git a/fpga/ipcore_dir/PrefetchDataRAM.gise b/fpga/ipcore_dir/PrefetchDataRAM.gise new file mode 100644 index 0000000..09f5798 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/CLKGEN.ucf b/fpga/ipcore_dir/PrefetchDataRAM.ncf similarity index 100% rename from fpga/CLKGEN.ucf rename to fpga/ipcore_dir/PrefetchDataRAM.ncf diff --git a/fpga/ipcore_dir/PrefetchDataRAM.ngc b/fpga/ipcore_dir/PrefetchDataRAM.ngc new file mode 100644 index 0000000..d38f8f2 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/fpga/ipcore_dir/PrefetchDataRAM.sym b/fpga/ipcore_dir/PrefetchDataRAM.sym new file mode 100644 index 0000000..cf7b267 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.sym @@ -0,0 +1,36 @@ + + + BLOCK + 2021-10-31T13:9:7 + + + + + + + + + + + PrefetchDataRAM + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ipcore_dir/PrefetchDataRAM.v b/fpga/ipcore_dir/PrefetchDataRAM.v new file mode 100644 index 0000000..6b16f4f --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.v @@ -0,0 +1,188 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2021 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file PrefetchDataRAM.v when simulating +// the core, PrefetchDataRAM. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module PrefetchDataRAM( + clka, + ena, + wea, + addra, + dina, + clkb, + enb, + addrb, + doutb +); + +input clka; +input ena; +input [3 : 0] wea; +input [6 : 0] addra; +input [31 : 0] dina; +input clkb; +input enb; +input [6 : 0] addrb; +output [31 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V7_3 #( + .C_ADDRA_WIDTH(7), + .C_ADDRB_WIDTH(7), + .C_ALGORITHM(1), + .C_AXI_ID_WIDTH(4), + .C_AXI_SLAVE_TYPE(0), + .C_AXI_TYPE(1), + .C_BYTE_SIZE(8), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_FAMILY("spartan6"), + .C_HAS_AXI_ID(0), + .C_HAS_ENA(1), + .C_HAS_ENB(1), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INIT_FILE("BlankString"), + .C_INIT_FILE_NAME("no_coe_file_loaded"), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INTERFACE_TYPE(0), + .C_LOAD_INIT_FILE(0), + .C_MEM_TYPE(1), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(128), + .C_READ_DEPTH_B(128), + .C_READ_WIDTH_A(32), + .C_READ_WIDTH_B(32), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BRAM_BLOCK(0), + .C_USE_BYTE_WEA(1), + .C_USE_BYTE_WEB(1), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(4), + .C_WEB_WIDTH(4), + .C_WRITE_DEPTH_A(128), + .C_WRITE_DEPTH_B(128), + .C_WRITE_MODE_A("READ_FIRST"), + .C_WRITE_MODE_B("READ_FIRST"), + .C_WRITE_WIDTH_A(32), + .C_WRITE_WIDTH_B(32), + .C_XDEVICEFAMILY("spartan6") + ) + inst ( + .CLKA(clka), + .ENA(ena), + .WEA(wea), + .ADDRA(addra), + .DINA(dina), + .CLKB(clkb), + .ENB(enb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .REGCEA(), + .DOUTA(), + .RSTB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC(), + .S_ACLK(), + .S_ARESETN(), + .S_AXI_AWID(), + .S_AXI_AWADDR(), + .S_AXI_AWLEN(), + .S_AXI_AWSIZE(), + .S_AXI_AWBURST(), + .S_AXI_AWVALID(), + .S_AXI_AWREADY(), + .S_AXI_WDATA(), + .S_AXI_WSTRB(), + .S_AXI_WLAST(), + .S_AXI_WVALID(), + .S_AXI_WREADY(), + .S_AXI_BID(), + .S_AXI_BRESP(), + .S_AXI_BVALID(), + .S_AXI_BREADY(), + .S_AXI_ARID(), + .S_AXI_ARADDR(), + .S_AXI_ARLEN(), + .S_AXI_ARSIZE(), + .S_AXI_ARBURST(), + .S_AXI_ARVALID(), + .S_AXI_ARREADY(), + .S_AXI_RID(), + .S_AXI_RDATA(), + .S_AXI_RRESP(), + .S_AXI_RLAST(), + .S_AXI_RVALID(), + .S_AXI_RREADY(), + .S_AXI_INJECTSBITERR(), + .S_AXI_INJECTDBITERR(), + .S_AXI_SBITERR(), + .S_AXI_DBITERR(), + .S_AXI_RDADDRECC() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/ipcore_dir/PrefetchDataRAM.veo b/fpga/ipcore_dir/PrefetchDataRAM.veo new file mode 100644 index 0000000..ab93229 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.veo @@ -0,0 +1,67 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2021 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.3 * +* * +* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port * +* Block Memory and Single Port Block Memory LogiCOREs, but is not a * +* direct drop-in replacement. It should be used in all new Xilinx * +* designs. The core supports RAM and ROM functions over a wide range of * +* widths and depths. Use this core to generate block memories with * +* symmetric or asymmetric read and write port widths, as well as cores * +* which can perform simultaneous write operations to separate * +* locations, and simultaneous read operations from the same location. * +* For more information on differences in interface and feature support * +* between this core and the Dual Port Block Memory and Single Port * +* Block Memory LogiCOREs, please consult the data sheet. * +*******************************************************************************/ + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +PrefetchDataRAM your_instance_name ( + .clka(clka), // input clka + .ena(ena), // input ena + .wea(wea), // input [3 : 0] wea + .addra(addra), // input [6 : 0] addra + .dina(dina), // input [31 : 0] dina + .clkb(clkb), // input clkb + .enb(enb), // input enb + .addrb(addrb), // input [6 : 0] addrb + .doutb(doutb) // output [31 : 0] doutb +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file PrefetchDataRAM.v when simulating +// the core, PrefetchDataRAM. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/ipcore_dir/PrefetchDataRAM.xco b/fpga/ipcore_dir/PrefetchDataRAM.xco new file mode 100644 index 0000000..5be7920 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM.xco @@ -0,0 +1,108 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Sun Oct 31 13:08:26 2021 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:blk_mem_gen:7.3 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = ftg256 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 +# END Select +# BEGIN Parameters +CSET additional_inputs_for_power_estimation=false +CSET algorithm=Minimum_Area +CSET assume_synchronous_clk=true +CSET axi_id_width=4 +CSET axi_slave_type=Memory_Slave +CSET axi_type=AXI4_Full +CSET byte_size=8 +CSET coe_file=no_coe_file_loaded +CSET collision_warnings=ALL +CSET component_name=PrefetchDataRAM +CSET disable_collision_warnings=false +CSET disable_out_of_range_warnings=false +CSET ecc=false +CSET ecctype=No_ECC +CSET enable_32bit_address=false +CSET enable_a=Use_ENA_Pin +CSET enable_b=Use_ENB_Pin +CSET error_injection_type=Single_Bit_Error_Injection +CSET fill_remaining_memory_locations=false +CSET interface_type=Native +CSET load_init_file=false +CSET mem_file=no_Mem_file_loaded +CSET memory_type=Simple_Dual_Port_RAM +CSET operating_mode_a=READ_FIRST +CSET operating_mode_b=READ_FIRST +CSET output_reset_value_a=0 +CSET output_reset_value_b=0 +CSET pipeline_stages=0 +CSET port_a_clock=100 +CSET port_a_enable_rate=100 +CSET port_a_write_rate=50 +CSET port_b_clock=100 +CSET port_b_enable_rate=100 +CSET port_b_write_rate=0 +CSET primitive=8kx2 +CSET read_width_a=32 +CSET read_width_b=32 +CSET register_porta_input_of_softecc=false +CSET register_porta_output_of_memory_core=false +CSET register_porta_output_of_memory_primitives=false +CSET register_portb_output_of_memory_core=false +CSET register_portb_output_of_memory_primitives=false +CSET register_portb_output_of_softecc=false +CSET remaining_memory_locations=0 +CSET reset_memory_latch_a=false +CSET reset_memory_latch_b=false +CSET reset_priority_a=CE +CSET reset_priority_b=CE +CSET reset_type=SYNC +CSET softecc=false +CSET use_axi_id=false +CSET use_bram_block=Stand_Alone +CSET use_byte_write_enable=true +CSET use_error_injection_pins=false +CSET use_regcea_pin=false +CSET use_regceb_pin=false +CSET use_rsta_pin=false +CSET use_rstb_pin=false +CSET write_depth_a=128 +CSET write_width_a=32 +CSET write_width_b=32 +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-19T16:22:25Z +# END Extra information +GENERATE +# CRC: 748d0e4 diff --git a/fpga/ipcore_dir/CLK.xise b/fpga/ipcore_dir/PrefetchDataRAM.xise similarity index 82% rename from fpga/ipcore_dir/CLK.xise rename to fpga/ipcore_dir/PrefetchDataRAM.xise index 3949e06..a3e0a8c 100644 --- a/fpga/ipcore_dir/CLK.xise +++ b/fpga/ipcore_dir/PrefetchDataRAM.xise @@ -15,15 +15,16 @@ - - + + + - - - - - - + + + + + + @@ -33,9 +34,9 @@ - - - + + + @@ -48,17 +49,15 @@ - + - - + + - - - + diff --git a/fpga/ipcore_dir/PrefetchDataRAM/blk_mem_gen_v7_3_readme.txt b/fpga/ipcore_dir/PrefetchDataRAM/blk_mem_gen_v7_3_readme.txt new file mode 100644 index 0000000..80625fa --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/blk_mem_gen_v7_3_readme.txt @@ -0,0 +1,213 @@ + Core name: Xilinx LogiCORE Block Memory Generator + Version: 7.3 Rev 1 + Release: ISE 14.4 / Vivado 2012.4 + Release Date: October 16, 2012 + +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURES HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm + + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + All 7 Series devices + Zynq-7000 devices + +................................................................................ + +3. NEW FEATURES HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + + +................................................................................ + + +4. RESOLVED ISSUES + + +The following issues are resolved in Block Memory Generator v7.3: + + 4.1 ISE + + + 4.2 Vivado + + +................................................................................ + + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + The following are known issues for v7.3 of this core at time of release: + + 1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3. + + 3. Core does not generate for large memories. Depending on the + machine the ISE CORE Generator software runs on, the maximum size of the memory that + can be generated will vary. For example, a Dual Pentium-4 server + with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes + - CR 415768 + - AR 24034 + + + 5.2 Vivado + + The following are known issues for v7.3 of this core at time of release: + + The most recent information, including known issues, workarounds, and resolutions for + this version is provided in the IP Release Notes User Guide located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + + + +7. CORE RELEASE HISTORY + +Date By Version Description +================================================================================ +12/16/2012 Xilinx, Inc. 7.3 Rev 1 ISE 14.4 and Vivado 2012.4 support; +10/16/2012 Xilinx, Inc. 7.3 ISE 14.3 and Vivado 2012.3 support; +07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support; +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2011 Xilinx, Inc. 6.3 ISE 13.4 support;Artix7L*, AArtix-7* device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support; +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support +09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support +07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support +04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support +03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue +12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power + Device support; Automotive Spartan 3A + DSP device support +09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3 +06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2 +04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1 +09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8 +03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7 +10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6 +07/2007 Xilinx, Inc. 2.5 Revised to v2.5 +04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1 +02/2007 Xilinx, Inc. 2.4 Revised to v2.4 +11/2006 Xilinx, Inc. 2.3 Revised to v2.3 +09/2006 Xilinx, Inc. 2.2 Revised to v2.2 +06/2006 Xilinx, Inc. 2.1 Revised to v2.1 +01/2006 Xilinx, Inc. 1.1 Initial release +================================================================================ + +8. Legal Disclaimer + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/ipcore_dir/PrefetchDataRAM/doc/blk_mem_gen_v7_3_vinfo.html b/fpga/ipcore_dir/PrefetchDataRAM/doc/blk_mem_gen_v7_3_vinfo.html new file mode 100644 index 0000000..01edd02 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/doc/blk_mem_gen_v7_3_vinfo.html @@ -0,0 +1,224 @@ + + +blk_mem_gen_v7_3_vinfo + + + +

+                Core name: Xilinx LogiCORE Block Memory Generator
+                Version: 7.3 Rev 1
+                Release: ISE 14.4 / Vivado 2012.4
+                Release Date: October 16, 2012
+
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURES HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v7.3 
+solution. For the latest core updates, see the product page at:
+ 
+ www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
+
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+  Zynq-7000 devices
+  All Virtex-6 devices
+  All Spartan-6 devices
+  All Virtex-5 devices
+  All Spartan-3 devices
+  All Virtex-4 devices
+  
+
+  2.2 Vivado 
+  All 7 Series devices
+  Zynq-7000 devices
+
+................................................................................
+
+3. NEW FEATURES HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+
+  3.2 Vivado
+  
+    - 2012.4 software support
+
+
+................................................................................
+
+
+4. RESOLVED ISSUES
+
+
+The following issues are resolved in Block Memory Generator v7.3: 
+  
+  4.1 ISE 
+  
+
+  4.2 Vivado
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+
+    The following are known issues for v7.3 of this core at time of release:
+  
+    1. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
+  
+    3. Core does not generate for large memories. Depending on the
+       machine the ISE CORE Generator software runs on, the maximum size of the memory that
+       can be generated will vary.  For example, a Dual Pentium-4 server 
+       with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
+      - CR 415768
+      - AR 24034
+    
+
+  5.2 Vivado 
+
+    The following are known issues for v7.3 of this core at time of release:
+     
+  The most recent information, including known issues, workarounds, and resolutions for 
+  this version is provided in the IP Release Notes User Guide located at
+    
+         www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/16/2012  Xilinx, Inc.  7.3 Rev 1    ISE 14.4 and Vivado 2012.4 support;
+10/16/2012  Xilinx, Inc.  7.3          ISE 14.3 and Vivado 2012.3 support;
+07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support;
+04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2011  Xilinx, Inc.  6.3          ISE 13.4 support;Artix7L*, AArtix-7* device support 
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
+09/21/2010  Xilinx, Inc.  4.3          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  4.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  4.1          ISE 12.1 support
+03/09/2010  Xilinx, Inc.  3.3 rev 2    Fix for V6 Memory collision issue 
+12/02/2009  Xilinx, Inc.  3.3 rev 1    ISE 11.4 support; Spartan-6 Low Power
+                                       Device support; Automotive Spartan 3A
+                                       DSP device support
+09/16/2009  Xilinx, Inc.  3.3          Revised to v3.3
+06/24/2009  Xilinx, Inc.  3.2          Revised to v3.2
+04/24/2009  Xilinx, Inc.  3.1          Revised to v3.1
+09/19/2008  Xilinx, Inc.  2.8          Revised to v2.8
+03/24/2008  Xilinx, Inc.  2.7          10.1 support; Revised to v2.7
+10/03/2007  Xilinx, Inc.  2.6          Revised to v2.6
+07/2007     Xilinx, Inc.  2.5          Revised to v2.5
+04/2007     Xilinx, Inc.  2.4          Revised to v2.4 rev 1
+02/2007     Xilinx, Inc.  2.4          Revised to v2.4
+11/2006     Xilinx, Inc.  2.3          Revised to v2.3
+09/2006     Xilinx, Inc.  2.2          Revised to v2.2
+06/2006     Xilinx, Inc.  2.1          Revised to v2.1
+01/2006     Xilinx, Inc.  1.1          Initial release
+================================================================================
+
+8. Legal Disclaimer
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/ipcore_dir/PrefetchDataRAM/doc/pg058-blk-mem-gen.pdf b/fpga/ipcore_dir/PrefetchDataRAM/doc/pg058-blk-mem-gen.pdf new file mode 100644 index 0000000..54dbe43 Binary files /dev/null and b/fpga/ipcore_dir/PrefetchDataRAM/doc/pg058-blk-mem-gen.pdf differ diff --git a/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.ucf b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.ucf new file mode 100644 index 0000000..3762632 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.ucf @@ -0,0 +1,61 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +NET "CLKB" TNM_NET = "CLKB"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ; + +################################################################################ diff --git a/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.vhd b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.vhd new file mode 100644 index 0000000..61da4b6 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.vhd @@ -0,0 +1,185 @@ + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchDataRAM_exdes.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY PrefetchDataRAM_exdes IS + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + CLKA : IN STD_LOGIC; + + + --Inputs - Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END PrefetchDataRAM_exdes; + + +ARCHITECTURE xilinx OF PrefetchDataRAM_exdes IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT PrefetchDataRAM IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + bufg_B : BUFG + PORT MAP ( + I => CLKB, + O => CLKB_buf + ); + + + bmg0 : PrefetchDataRAM + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA_buf, + + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB_buf + + ); + +END xilinx; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.xdc b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.xdc new file mode 100644 index 0000000..62e72c7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.xdc @@ -0,0 +1,56 @@ +################################################################################ +# +# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ] + +create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ] +################################################################################ diff --git a/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_prod.vhd b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_prod.vhd new file mode 100644 index 0000000..1c71153 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/example_design/PrefetchDataRAM_prod.vhd @@ -0,0 +1,279 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchDataRAM_prod.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan6 +-- C_XDEVICEFAMILY : spartan6 +-- C_INTERFACE_TYPE : 0 +-- C_ENABLE_32BIT_ADDRESS : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 1 +-- C_BYTE_SIZE : 8 +-- C_ALGORITHM : 1 +-- C_PRIM_TYPE : 1 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 0 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 1 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 1 +-- C_WEA_WIDTH : 4 +-- C_WRITE_MODE_A : READ_FIRST +-- C_WRITE_WIDTH_A : 32 +-- C_READ_WIDTH_A : 32 +-- C_WRITE_DEPTH_A : 128 +-- C_READ_DEPTH_A : 128 +-- C_ADDRA_WIDTH : 7 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 1 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 1 +-- C_WEB_WIDTH : 4 +-- C_WRITE_MODE_B : READ_FIRST +-- C_WRITE_WIDTH_B : 32 +-- C_READ_WIDTH_B : 32 +-- C_WRITE_DEPTH_B : 128 +-- C_READ_DEPTH_B : 128 +-- C_ADDRB_WIDTH : 7 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 1 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY PrefetchDataRAM_prod IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END PrefetchDataRAM_prod; + + +ARCHITECTURE xilinx OF PrefetchDataRAM_prod IS + + COMPONENT PrefetchDataRAM_exdes IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + CLKB : IN STD_LOGIC + + + + ); + END COMPONENT; + +BEGIN + + bmg0 : PrefetchDataRAM_exdes + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA, + + --Port B + ENB => ENB, + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB + + + + ); +END xilinx; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/implement.bat b/fpga/ipcore_dir/PrefetchDataRAM/implement/implement.bat new file mode 100644 index 0000000..aae34df --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/implement.bat @@ -0,0 +1,48 @@ + + + + + + + + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy PrefetchDataRAM_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\PrefetchDataRAM.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\PrefetchDataRAM_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx9-ftg256-2 PrefetchDataRAM_exdes + +echo 'Running map' +map PrefetchDataRAM_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm PrefetchDataRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/implement.sh b/fpga/ipcore_dir/PrefetchDataRAM/implement/implement.sh new file mode 100644 index 0000000..07f4f4b --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/implement.sh @@ -0,0 +1,48 @@ + + + + + + + + +#!/bin/sh + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp PrefetchDataRAM_exdes.ngc ./results/ + + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../PrefetchDataRAM.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/PrefetchDataRAM_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx9-ftg256-2 PrefetchDataRAM_exdes + +echo 'Running map' +map PrefetchDataRAM_exdes -o mapped.ncd -pr i + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm PrefetchDataRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.bat b/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.bat new file mode 100644 index 0000000..e7c019e --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.bat @@ -0,0 +1,55 @@ +#!/bin/sh +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\PrefetchDataRAM.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.sh b/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.sh new file mode 100644 index 0000000..f0072bd --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../PrefetchDataRAM.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.tcl b/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.tcl new file mode 100644 index 0000000..f54632c --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/planAhead_ise.tcl @@ -0,0 +1,67 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + +set device xc6slx9ftg256-2 +set projName PrefetchDataRAM +set design PrefetchDataRAM +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module PrefetchDataRAM_exdes +add_files -norecurse {../../example_design/PrefetchDataRAM_exdes.vhd} +add_files -norecurse {./PrefetchDataRAM.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/PrefetchDataRAM_exdes.xdc} +set_property top PrefetchDataRAM_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module PrefetchDataRAM_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module PrefetchDataRAM_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/xst.prj b/fpga/ipcore_dir/PrefetchDataRAM/implement/xst.prj new file mode 100644 index 0000000..f595de5 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/xst.prj @@ -0,0 +1 @@ +work ../example_design/PrefetchDataRAM_exdes.vhd diff --git a/fpga/ipcore_dir/PrefetchDataRAM/implement/xst.scr b/fpga/ipcore_dir/PrefetchDataRAM/implement/xst.scr new file mode 100644 index 0000000..d0d8a75 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/implement/xst.scr @@ -0,0 +1,13 @@ +run +-ifmt VHDL +-ent PrefetchDataRAM_exdes +-p xc6slx9-ftg256-2 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn PrefetchDataRAM_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/PrefetchDataRAM_synth.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/PrefetchDataRAM_synth.vhd new file mode 100644 index 0000000..d17ff8c --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/PrefetchDataRAM_synth.vhd @@ -0,0 +1,336 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchDataRAM_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY PrefetchDataRAM_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + CLKB_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE PrefetchDataRAM_synth_ARCH OF PrefetchDataRAM_synth IS + + +COMPONENT PrefetchDataRAM_exdes + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + WEA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CLKA : IN STD_LOGIC; + + --Inputs - Port B + ENB : IN STD_LOGIC; --opt port + ADDRB : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL ENA: STD_LOGIC := '0'; + SIGNAL ENA_R: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CLKB: STD_LOGIC := '0'; + SIGNAL RSTB: STD_LOGIC := '0'; + SIGNAL ENB: STD_LOGIC := '0'; + SIGNAL ENB_R: STD_LOGIC := '0'; + SIGNAL ADDRB: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRB_R: STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTB: STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL clkb_in_i: STD_LOGIC; + SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; + SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; + SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + +-- clkb_buf: bufg +-- PORT map( +-- i => CLKB_IN, +-- o => clkb_in_i +-- ); + clkb_in_i <= CLKB_IN; + CLKB <= clkb_in_i; + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + RSTB <= RESETB_SYNC_R3 AFTER 50 ns; + + PROCESS(clkb_in_i) + BEGIN + IF(RISING_EDGE(clkb_in_i)) THEN + RESETB_SYNC_R1 <= RESET_IN; + RESETB_SYNC_R2 <= RESETB_SYNC_R1; + RESETB_SYNC_R3 <= RESETB_SYNC_R2; + END IF; + END PROCESS; + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 32, + READ_WIDTH => 32 ) + PORT MAP ( + CLK => clkb_in_i, + RST => RSTB, + EN => CHECKER_EN_R, + DATA_IN => DOUTB, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(clkb_in_i) + BEGIN + IF(RISING_EDGE(clkb_in_i)) THEN + IF(RSTB='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLKA => clk_in_i, + CLKB => clkb_in_i, + TB_RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + ENA => ENA, + WEA => WEA, + ADDRB => ADDRB, + ENB => ENB, + CHECK_DATA => CHECKER_EN + ); + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ENA_R <= '0' AFTER 50 ns; + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + ENB_R <= '0' AFTER 50 ns; + + + ELSE + ENA_R <= ENA AFTER 50 ns; + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + ENB_R <= ENB AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + ADDRB_R <= ADDRB AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: PrefetchDataRAM_exdes PORT MAP ( + --Port A + ENA => ENA_R, + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + CLKA => CLKA, + --Port B + ENB => ENB_R, + ADDRB => ADDRB_R, + DOUTB => DOUTB, + CLKB => CLKB + + ); +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/PrefetchDataRAM_tb.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/PrefetchDataRAM_tb.vhd new file mode 100644 index 0000000..ab2657e --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/PrefetchDataRAM_tb.vhd @@ -0,0 +1,142 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: PrefetchDataRAM_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY PrefetchDataRAM_tb IS +END ENTITY; + + +ARCHITECTURE PrefetchDataRAM_tb_ARCH OF PrefetchDataRAM_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL CLKB : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + CLKB_GEN: PROCESS BEGIN + CLKB <= NOT CLKB; + WAIT FOR 100 NS; + CLKB <= NOT CLKB; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Test Completed Successfully" + SEVERITY NOTE; + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "TEST PASS" + SEVERITY NOTE; + REPORT "Test Completed Successfully" + SEVERITY FAILURE; + END IF; + +END PROCESS; + + PrefetchDataRAM_synth_inst:ENTITY work.PrefetchDataRAM_synth + PORT MAP( + CLK_IN => CLK, + CLKB_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/addr_gen.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/addr_gen.vhd new file mode 100644 index 0000000..62706ca --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/addr_gen.vhd @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/bmg_stim_gen.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/bmg_stim_gen.vhd new file mode 100644 index 0000000..65f34ea --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/bmg_stim_gen.vhd @@ -0,0 +1,437 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SDP Configuration +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + + LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS +SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLKA : IN STD_LOGIC; + CLKB : IN STD_LOGIC; + TB_RST : IN STD_LOGIC; + ADDRA: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + ENA : OUT STD_LOGIC :='0'; + WEA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0'); + ADDRB: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0'); + ENB : OUT STD_LOGIC :='0'; + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + +CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL DO_WRITE : STD_LOGIC := '0'; +SIGNAL DO_READ : STD_LOGIC := '0'; +SIGNAL DO_READ_R : STD_LOGIC := '0'; +SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0'); +SIGNAL PORTA_WR : STD_LOGIC:='0'; +SIGNAL COUNT : INTEGER :=0; +SIGNAL INCR_WR_CNT : STD_LOGIC:='0'; +SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTB_RD : STD_LOGIC:='0'; +SIGNAL COUNT_RD : INTEGER :=0; +SIGNAL INCR_RD_CNT : STD_LOGIC:='0'; +SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0'; +SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0'; +SIGNAL PORTA_WR_L1 :STD_LOGIC := '0'; +SIGNAL PORTA_WR_L2 :STD_LOGIC := '0'; +SIGNAL PORTB_RD_R2 :STD_LOGIC := '0'; +SIGNAL PORTB_RD_R1 :STD_LOGIC := '0'; +SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0'; +SIGNAL PORTB_RD_L1 : STD_LOGIC := '0'; +SIGNAL PORTB_RD_L2 : STD_LOGIC := '0'; +SIGNAL PORTA_WR_R2 : STD_LOGIC := '0'; +SIGNAL PORTA_WR_R1 : STD_LOGIC := '0'; + +CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8; +CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((7 <= 7),WR_RD_DEEP_COUNT, + ((32/32)*WR_RD_DEEP_COUNT)); +CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((7 <= 7),WR_RD_DEEP_COUNT, + ((32/32)*WR_RD_DEEP_COUNT)); + +BEGIN + + ADDRA <= WRITE_ADDR(6 DOWNTO 0) ; + DINA <= DINA_INT ; + ADDRB <= READ_ADDR(6 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0'); + CHECK_DATA <= DO_READ; + + RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 128 , + RST_INC => 1 ) + PORT MAP( + CLK => CLKB, + RST => TB_RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + + WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 128, + RST_INC => 1 ) + PORT MAP( + CLK => CLKA, + RST => TB_RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + + WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 32, + DOUT_WIDTH => 32 , + DATA_PART_CNT => 1, + SEED => 2) + PORT MAP ( + CLK => CLKA, + RST => TB_RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + + + PORTA_WR_PROCESS: PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTA_WR<='1'; + ELSE + PORTA_WR<=PORTB_RD_COMPLETE; + END IF; + END IF; + END PROCESS; + + PORTB_RD_PROCESS: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTB_RD<='0'; + ELSE + PORTB_RD<=PORTA_WR_L2; + END IF; + END IF; + END PROCESS; + + PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + LATCH_PORTB_RD_COMPLETE<='0'; + ELSIF(PORTB_RD_COMPLETE='1') THEN + LATCH_PORTB_RD_COMPLETE <='1'; + ELSIF(PORTA_WR_HAPPENED='1') THEN + LATCH_PORTB_RD_COMPLETE<='0'; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTB_RD_L1 <='0'; + PORTB_RD_L2 <='0'; + ELSE + PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE; + PORTB_RD_L2 <= PORTB_RD_L1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTA_WR_R1 <='0'; + PORTA_WR_R2 <='0'; + ELSE + PORTA_WR_R1 <= PORTA_WR; + PORTA_WR_R2 <= PORTA_WR_R1; + END IF; + END IF; + END PROCESS; + + PORTA_WR_HAPPENED <= PORTA_WR_R2; + + PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + LATCH_PORTA_WR_COMPLETE<='0'; + ELSIF(PORTA_WR_COMPLETE='1') THEN + LATCH_PORTA_WR_COMPLETE <='1'; + --ELSIF(PORTB_RD_HAPPENED='1') THEN + ELSE + LATCH_PORTA_WR_COMPLETE<='0'; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTA_WR_L1 <='0'; + PORTA_WR_L2 <='0'; + ELSE + PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE; + PORTA_WR_L2 <= PORTA_WR_L1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTB_RD_R1 <='0'; + PORTB_RD_R2 <='0'; + ELSE + PORTB_RD_R1 <= PORTB_RD; + PORTB_RD_R2 <= PORTB_RD_R1; + END IF; + END IF; + END PROCESS; + + PORTB_RD_HAPPENED <= PORTB_RD_R2; + + PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0'; + + start_rd_counter: process(clkb) + begin + if(rising_edge(clkb)) then + if(tb_rst='1') then + incr_rd_cnt <= '0'; + elsif(portb_rd ='1') then + incr_rd_cnt <='1'; + elsif(portb_rd_complete='1') then + incr_rd_cnt <='0'; + end if; + end if; + end process; + + RD_COUNTER: process(clkb) + begin + if(rising_edge(clkb)) then + if(tb_rst='1') then + count_rd <= 0; + elsif(incr_rd_cnt='1') then + count_rd<=count_rd+1; + end if; + --if(count_rd=(wr_rd_deep_count)) then + if(count_rd=(RD_DEEP_COUNT)) then + count_rd<=0; + end if; + end if; + end process; + + DO_READ<='1' when (count_rd DO_READ_REG(0), + CLK => CLKB, + RST => TB_RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + + DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC + PORT MAP( + Q => DO_READ_REG(I), + CLK =>CLKB, + RST =>TB_RST, + D =>DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; + END GENERATE BEGIN_SHIFT_REG; + + REGCE_PROCESS: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + DO_READ_R <= '0'; + ELSE + DO_READ_R <= DO_READ; + END IF; + END IF; + END PROCESS; + + + ENB <= DO_READ; + ENA <= DO_WRITE ; + WEA <= ( OTHERS => '1') ; + + +END ARCHITECTURE; + + + + + diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/bmg_tb_pkg.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/bmg_tb_pkg.vhd new file mode 100644 index 0000000..4928909 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/bmg_tb_pkg.vhd @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/checker.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/checker.vhd new file mode 100644 index 0000000..15a2753 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/checker.vhd @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + + diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/data_gen.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/data_gen.vhd new file mode 100644 index 0000000..fe3dca7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/data_gen.vhd @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simcmds.tcl b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simcmds.tcl new file mode 100644 index 0000000..eba16e7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simcmds.tcl @@ -0,0 +1,66 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /PrefetchDataRAM_tb/status + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/CLKA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ADDRA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/DINA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/WEA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ENA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/CLKB + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ADDRB + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ENB + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/DOUTB +run all +quit diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_isim.bat b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_isim.bat new file mode 100644 index 0000000..5ccf5b6 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_isim.bat @@ -0,0 +1,69 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogcomp -work work ..\..\..\PrefetchDataRAM.v +vhpcomp -work work ..\..\example_design\PrefetchDataRAM_exdes.vhd + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\PrefetchDataRAM_synth.vhd +vhpcomp -work work ..\PrefetchDataRAM_tb.vhd + + +vlogcomp -work work $XILINX\verilog\src\glbl.v +fuse work.PrefetchDataRAM_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o PrefetchDataRAM_tb.exe + +.\PrefetchDataRAM_tb.exe -gui -tclbatch simcmds.tcl diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.bat b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.bat new file mode 100644 index 0000000..5964f52 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.bat @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.do b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.do new file mode 100644 index 0000000..b5a36f1 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.do @@ -0,0 +1,76 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../PrefetchDataRAM.v +vcom -work work ../../example_design/PrefetchDataRAM_exdes.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../PrefetchDataRAM_synth.vhd +vcom -work work ../PrefetchDataRAM_tb.vhd + + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.PrefetchDataRAM_tb + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.sh b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.sh new file mode 100644 index 0000000..5964f52 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_mti.sh @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_ncsim.sh b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_ncsim.sh new file mode 100644 index 0000000..7b2be68 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_ncsim.sh @@ -0,0 +1,71 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + + +mkdir work +echo "Compiling Core Verilog UNISIM/Behavioral model" +ncvlog -work work ../../../PrefetchDataRAM.v +ncvhdl -v93 -work work ../../example_design/PrefetchDataRAM_exdes.vhd + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../PrefetchDataRAM_synth.vhd +ncvhdl -v93 -work work ../PrefetchDataRAM_tb.vhd + +echo "Elaborating Design" +ncvlog -work work $XILINX/verilog/src/glbl.v +ncelab -access +rwc glbl work.PrefetchDataRAM_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" work.PrefetchDataRAM_tb diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_vcs.sh b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_vcs.sh new file mode 100644 index 0000000..d5475a2 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/simulate_vcs.sh @@ -0,0 +1,70 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../../PrefetchDataRAM.v +vhdlan ../../example_design/PrefetchDataRAM_exdes.vhd + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../PrefetchDataRAM_synth.vhd +vhdlan ../PrefetchDataRAM_tb.vhd + +echo "Elaborating Design" +vlogan +v2k $XILINX/verilog/src/glbl.v +vcs +vcs+lic+wait -debug PrefetchDataRAM_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/ucli_commands.key b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/ucli_commands.key new file mode 100644 index 0000000..6990cc7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add PrefetchDataRAM_tb +run +quit diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/vcs_session.tcl b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/vcs_session.tcl new file mode 100644 index 0000000..725c748 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/vcs_session.tcl @@ -0,0 +1,86 @@ + + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create PrefetchDataRAM_Group +gui_list_add_group -id Wave.1 {PrefetchDataRAM_Group} + + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/status + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DINA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/WEA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKB + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRB + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENB + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DOUTB + +gui_zoom -window Wave.1 -full diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/wave_mti.do b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/wave_mti.do new file mode 100644 index 0000000..af1de45 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/wave_mti.do @@ -0,0 +1,39 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + add wave -noupdate /PrefetchDataRAM_tb/status + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DINA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/WEA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKB + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRB + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENB + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DOUTB + +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 197 +configure wave -valuecolwidth 106 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/wave_ncsim.sv b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/wave_ncsim.sv new file mode 100644 index 0000000..9353190 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/functional/wave_ncsim.sv @@ -0,0 +1,24 @@ + + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + waveform add -signals /PrefetchDataRAM_tb/status + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DINA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/WEA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKB + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRB + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENB + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DOUTB + +console submit -using simulator -wait no "run" diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/random.vhd b/fpga/ipcore_dir/PrefetchDataRAM/simulation/random.vhd new file mode 100644 index 0000000..b0d417c --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/random.vhd @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simcmds.tcl b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simcmds.tcl new file mode 100644 index 0000000..eba16e7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simcmds.tcl @@ -0,0 +1,66 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + + + + + + + +wcfg new +isim set radix hex +wave add /PrefetchDataRAM_tb/status + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/CLKA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ADDRA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/DINA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/WEA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ENA + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/CLKB + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ADDRB + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/ENB + wave add /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/BMG_PORT/DOUTB +run all +quit diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_isim.bat b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_isim.bat new file mode 100644 index 0000000..11e7872 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_isim.bat @@ -0,0 +1,65 @@ +:: (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +:: +:: This file contains confidential and proprietary information +:: of Xilinx, Inc. and is protected under U.S. and +:: international copyright and other intellectual property +:: laws. +:: +:: DISCLAIMER +:: This disclaimer is not a license and does not grant any +:: rights to the materials distributed herewith. Except as +:: otherwise provided in a valid license issued to you by +:: Xilinx, and to the maximum extent permitted by applicable +:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +:: (2) Xilinx shall not be liable (whether in contract or tort, +:: including negligence, or under any other theory of +:: liability) for any loss or damage of any kind or nature +:: related to, arising under or in connection with these +:: materials, including for any direct, or any indirect, +:: special, incidental, or consequential loss or damage +:: (including loss of data, profits, goodwill, or any type of +:: loss or damage suffered as a result of any action brought +:: by a third party) even if such damage or loss was +:: reasonably foreseeable or Xilinx had been advised of the +:: possibility of the same. +:: +:: CRITICAL APPLICATIONS +:: Xilinx products are not designed or intended to be fail- +:: safe, or for use in any application requiring fail-safe +:: performance, such as life-support or safety devices or +:: systems, Class III medical devices, nuclear facilities, +:: applications related to the deployment of airbags, or any +:: other applications that could lead to death, personal +:: injury, or severe property or environmental damage +:: (individually and collectively, "Critical +:: Applications"). Customer assumes the sole risk and +:: liability of any use of Xilinx products in Critical +:: Applications, subject only to applicable laws and +:: regulations governing limitations on product liability. +:: +:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +:: PART OF THIS FILE AT ALL TIMES. +::-------------------------------------------------------------------------------- + + + +vlogcomp -work work ..\..\implement\results\routed.v + +echo "Compiling Test Bench Files" + +vhpcomp -work work ..\bmg_tb_pkg.vhd +vhpcomp -work work ..\random.vhd +vhpcomp -work work ..\data_gen.vhd +vhpcomp -work work ..\addr_gen.vhd +vhpcomp -work work ..\checker.vhd +vhpcomp -work work ..\bmg_stim_gen.vhd +vhpcomp -work work ..\PrefetchDataRAM_synth.vhd +vhpcomp -work work ..\PrefetchDataRAM_tb.vhd + + fuse -L simprims_ver work.PrefetchDataRAM_tb work.glbl -o PrefetchDataRAM_tb.exe + +.\PrefetchDataRAM_tb.exe -sdftyp /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port=..\..\implement\results\routed.sdf -gui -tclbatch simcmds.tcl diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.bat b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.bat new file mode 100644 index 0000000..5964f52 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.bat @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.do b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.do new file mode 100644 index 0000000..a49d8fc --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.do @@ -0,0 +1,75 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- + +vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" + +vcom -work work ../bmg_tb_pkg.vhd +vcom -work work ../random.vhd +vcom -work work ../data_gen.vhd +vcom -work work ../addr_gen.vhd +vcom -work work ../checker.vhd +vcom -work work ../bmg_stim_gen.vhd +vcom -work work ../PrefetchDataRAM_synth.vhd +vcom -work work ../PrefetchDataRAM_tb.vhd + + vsim -novopt -t ps -L simprims_ver +transport_int_delays -sdftyp /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port=../../implement/results/routed.sdf $work.PrefetchDataRAM_tb $work.glbl -novopt + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.sh b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.sh new file mode 100644 index 0000000..5964f52 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_mti.sh @@ -0,0 +1,3 @@ +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_ncsim.sh b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_ncsim.sh new file mode 100644 index 0000000..dcce8c7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_ncsim.sh @@ -0,0 +1,78 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- +mkdir work + + +ncvlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" + +ncvhdl -v93 -work work ../bmg_tb_pkg.vhd +ncvhdl -v93 -work work ../random.vhd +ncvhdl -v93 -work work ../data_gen.vhd +ncvhdl -v93 -work work ../addr_gen.vhd +ncvhdl -v93 -work work ../checker.vhd +ncvhdl -v93 -work work ../bmg_stim_gen.vhd +ncvhdl -v93 -work work ../PrefetchDataRAM_synth.vhd +ncvhdl -v93 -work work ../PrefetchDataRAM_tb.vhd + +echo "Compiling SDF file" +ncsdfc ../../implement/results/routed.sdf -output ./routed.sdf.X + +echo "Generating SDF command file" +echo 'COMPILED_SDF_FILE = "routed.sdf.X",' > sdf.cmd +echo 'SCOPE = :PrefetchDataRAM_synth_inst:BMG_PORT,' >> sdf.cmd +echo 'MTM_CONTROL = "MAXIMUM";' >> sdf.cmd + + +echo "Elaborating Design" +ncelab -access +rwc glbl -sdf_cmd_file sdf.cmd $work.PrefetchDataRAM_tb + +echo "Simulating Design" +ncsim -gui -input @"simvision -input wave_ncsim.sv" $work.PrefetchDataRAM_tb diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_vcs.sh b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_vcs.sh new file mode 100644 index 0000000..119b301 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/simulate_vcs.sh @@ -0,0 +1,70 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- +#!/bin/sh + +rm -rf simv* csrc DVEfiles AN.DB + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlogan +v2k ../../implement/results/routed.v + +echo "Compiling Test Bench Files" +vhdlan ../bmg_tb_pkg.vhd +vhdlan ../random.vhd +vhdlan ../data_gen.vhd +vhdlan ../addr_gen.vhd +vhdlan ../checker.vhd +vhdlan ../bmg_stim_gen.vhd +vhdlan ../PrefetchDataRAM_synth.vhd +vhdlan ../PrefetchDataRAM_tb.vhd + + +echo "Elaborating Design" +vcs +neg_tchk +vcs+lic+wait -debug PrefetchDataRAM_tb glbl + +echo "Simulating Design" +./simv -ucli -i ucli_commands.key +dve -session vcs_session.tcl diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/ucli_commands.key b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/ucli_commands.key new file mode 100644 index 0000000..6990cc7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/ucli_commands.key @@ -0,0 +1,4 @@ +dump -file bmg_vcs.vpd -type VPD +dump -add PrefetchDataRAM_tb +run +quit diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/vcs_session.tcl b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/vcs_session.tcl new file mode 100644 index 0000000..e24cbb1 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/vcs_session.tcl @@ -0,0 +1,86 @@ + + + + + + + +#-------------------------------------------------------------------------------- +#-- +#-- BMG Generator v8.4 Core Demo Testbench +#-- +#-------------------------------------------------------------------------------- +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# Filename: vcs_session.tcl +# +# Description: +# This is the VCS wave form file. +# +#-------------------------------------------------------------------------------- + +if { ![gui_is_db_opened -db {bmg_vcs.vpd}] } { + gui_open_db -design V1 -file bmg_vcs.vpd -nosource +} +gui_set_precision 1ps +gui_set_time_units 1ps + +gui_open_window Wave +gui_sg_create PrefetchDataRAM_Group +gui_list_add_group -id Wave.1 {PrefetchDataRAM_Group} + + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/status + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DINA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/WEA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENA + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKB + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRB + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENB + gui_sg_addsignal -group PrefetchDataRAM_Group /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DOUTB + +gui_zoom -window Wave.1 -full diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/wave_mti.do b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/wave_mti.do new file mode 100644 index 0000000..2677ed7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/wave_mti.do @@ -0,0 +1,39 @@ + + + + + + + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + + add wave -noupdate /PrefetchDataRAM_tb/status + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DINA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/WEA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENA + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKB + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRB + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENB + add wave -noupdate /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DOUTB +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {9464063 ps} diff --git a/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/wave_ncsim.sv b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/wave_ncsim.sv new file mode 100644 index 0000000..d137e66 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM/simulation/timing/wave_ncsim.sv @@ -0,0 +1,23 @@ + + + + + + + + +window new WaveWindow -name "Waves for BMG Example Design" +waveform using "Waves for BMG Example Design" + + + waveform add -signals /PrefetchDataRAM_tb/status + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DINA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/WEA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENA + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/CLKB + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ADDRB + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/ENB + waveform add -signals /PrefetchDataRAM_tb/PrefetchDataRAM_synth_inst/bmg_port/DOUTB +console submit -using simulator -wait no "run" diff --git a/fpga/ipcore_dir/PrefetchDataRAM_flist.txt b/fpga/ipcore_dir/PrefetchDataRAM_flist.txt new file mode 100644 index 0000000..9f48edb --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM_flist.txt @@ -0,0 +1,57 @@ +# Output products list for +PrefetchDataRAM.asy +PrefetchDataRAM.gise +PrefetchDataRAM.ngc +PrefetchDataRAM.sym +PrefetchDataRAM.v +PrefetchDataRAM.veo +PrefetchDataRAM.xco +PrefetchDataRAM.xise +PrefetchDataRAM\blk_mem_gen_v7_3_readme.txt +PrefetchDataRAM\doc\blk_mem_gen_v7_3_vinfo.html +PrefetchDataRAM\doc\pg058-blk-mem-gen.pdf +PrefetchDataRAM\example_design\PrefetchDataRAM_exdes.ucf +PrefetchDataRAM\example_design\PrefetchDataRAM_exdes.vhd +PrefetchDataRAM\example_design\PrefetchDataRAM_exdes.xdc +PrefetchDataRAM\example_design\PrefetchDataRAM_prod.vhd +PrefetchDataRAM\implement\implement.bat +PrefetchDataRAM\implement\implement.sh +PrefetchDataRAM\implement\planAhead_ise.bat +PrefetchDataRAM\implement\planAhead_ise.sh +PrefetchDataRAM\implement\planAhead_ise.tcl +PrefetchDataRAM\implement\xst.prj +PrefetchDataRAM\implement\xst.scr +PrefetchDataRAM\simulation\PrefetchDataRAM_synth.vhd +PrefetchDataRAM\simulation\PrefetchDataRAM_tb.vhd +PrefetchDataRAM\simulation\addr_gen.vhd +PrefetchDataRAM\simulation\bmg_stim_gen.vhd +PrefetchDataRAM\simulation\bmg_tb_pkg.vhd +PrefetchDataRAM\simulation\checker.vhd +PrefetchDataRAM\simulation\data_gen.vhd +PrefetchDataRAM\simulation\functional\simcmds.tcl +PrefetchDataRAM\simulation\functional\simulate_isim.bat +PrefetchDataRAM\simulation\functional\simulate_mti.bat +PrefetchDataRAM\simulation\functional\simulate_mti.do +PrefetchDataRAM\simulation\functional\simulate_mti.sh +PrefetchDataRAM\simulation\functional\simulate_ncsim.sh +PrefetchDataRAM\simulation\functional\simulate_vcs.sh +PrefetchDataRAM\simulation\functional\ucli_commands.key +PrefetchDataRAM\simulation\functional\vcs_session.tcl +PrefetchDataRAM\simulation\functional\wave_mti.do +PrefetchDataRAM\simulation\functional\wave_ncsim.sv +PrefetchDataRAM\simulation\random.vhd +PrefetchDataRAM\simulation\timing\simcmds.tcl +PrefetchDataRAM\simulation\timing\simulate_isim.bat +PrefetchDataRAM\simulation\timing\simulate_mti.bat +PrefetchDataRAM\simulation\timing\simulate_mti.do +PrefetchDataRAM\simulation\timing\simulate_mti.sh +PrefetchDataRAM\simulation\timing\simulate_ncsim.sh +PrefetchDataRAM\simulation\timing\simulate_vcs.sh +PrefetchDataRAM\simulation\timing\ucli_commands.key +PrefetchDataRAM\simulation\timing\vcs_session.tcl +PrefetchDataRAM\simulation\timing\wave_mti.do +PrefetchDataRAM\simulation\timing\wave_ncsim.sv +PrefetchDataRAM_flist.txt +PrefetchDataRAM_xmdf.tcl +_xmsgs\pn_parser.xmsgs +summary.log diff --git a/fpga/ipcore_dir/PrefetchDataRAM_xmdf.tcl b/fpga/ipcore_dir/PrefetchDataRAM_xmdf.tcl new file mode 100644 index 0000000..3d54214 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchDataRAM_xmdf.tcl @@ -0,0 +1,251 @@ +# The package naming convention is _xmdf +package provide PrefetchDataRAM_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::PrefetchDataRAM_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::PrefetchDataRAM_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name PrefetchDataRAM +} +# ::PrefetchDataRAM_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::PrefetchDataRAM_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/blk_mem_gen_v7_3_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/doc/blk_mem_gen_v7_3_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/doc/pg058-blk-mem-gen.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/example_design/PrefetchDataRAM_exdes.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/example_design/PrefetchDataRAM_prod.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/PrefetchDataRAM_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/PrefetchDataRAM_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/addr_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/bmg_stim_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/bmg_tb_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/checker.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/data_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/functional/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/random.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simcmds.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simulate_isim.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simulate_ncsim.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/simulate_vcs.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/ucli_commands.key +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/vcs_session.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/wave_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM/simulation/timing/wave_ncsim.sv +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchDataRAM_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module PrefetchDataRAM +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/ipcore_dir/PrefetchTagRAM.asy b/fpga/ipcore_dir/PrefetchTagRAM.asy new file mode 100644 index 0000000..f5ad40f --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.asy @@ -0,0 +1,33 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 PrefetchTagRAM +RECTANGLE Normal 32 32 256 544 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName a[4:0] +PINATTR Polarity IN +LINE Wide 0 112 32 112 +PIN 0 112 LEFT 36 +PINATTR PinName d[21:0] +PINATTR Polarity IN +LINE Wide 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName dpra[4:0] +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName we +PINATTR Polarity IN +LINE Normal 0 304 32 304 +PIN 0 304 LEFT 36 +PINATTR PinName clk +PINATTR Polarity IN +LINE Wide 288 80 256 80 +PIN 288 80 RIGHT 36 +PINATTR PinName spo[21:0] +PINATTR Polarity OUT +LINE Wide 288 144 256 144 +PIN 288 144 RIGHT 36 +PINATTR PinName dpo[21:0] +PINATTR Polarity OUT + diff --git a/fpga/ipcore_dir/PrefetchTagRAM.gise b/fpga/ipcore_dir/PrefetchTagRAM.gise new file mode 100644 index 0000000..ce69694 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ipcore_dir/PrefetchTagRAM.ncf b/fpga/ipcore_dir/PrefetchTagRAM.ncf new file mode 100644 index 0000000..e69de29 diff --git a/fpga/ipcore_dir/PrefetchTagRAM.ngc b/fpga/ipcore_dir/PrefetchTagRAM.ngc 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\ No newline at end of file diff --git a/fpga/ipcore_dir/PrefetchTagRAM.sym b/fpga/ipcore_dir/PrefetchTagRAM.sym new file mode 100644 index 0000000..d00381d --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.sym @@ -0,0 +1,30 @@ + + + BLOCK + 2021-10-31T18:22:27 + + + + + + + + + PrefetchTagRAM + + + + + + + + + + + + + + + + + diff --git a/fpga/ipcore_dir/PrefetchTagRAM.v b/fpga/ipcore_dir/PrefetchTagRAM.v new file mode 100644 index 0000000..497711d --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.v @@ -0,0 +1,116 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2021 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// You must compile the wrapper file PrefetchTagRAM.v when simulating +// the core, PrefetchTagRAM. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +`timescale 1ns/1ps + +module PrefetchTagRAM( + a, + d, + dpra, + clk, + we, + spo, + dpo +); + +input [4 : 0] a; +input [21 : 0] d; +input [4 : 0] dpra; +input clk; +input we; +output [21 : 0] spo; +output [21 : 0] dpo; + +// synthesis translate_off + + DIST_MEM_GEN_V7_2 #( + .C_ADDR_WIDTH(5), + .C_DEFAULT_DATA("0"), + .C_DEPTH(32), + .C_FAMILY("spartan6"), + .C_HAS_CLK(1), + .C_HAS_D(1), + .C_HAS_DPO(1), + .C_HAS_DPRA(1), + .C_HAS_I_CE(0), + .C_HAS_QDPO(0), + .C_HAS_QDPO_CE(0), + .C_HAS_QDPO_CLK(0), + .C_HAS_QDPO_RST(0), + .C_HAS_QDPO_SRST(0), + .C_HAS_QSPO(0), + .C_HAS_QSPO_CE(0), + .C_HAS_QSPO_RST(0), + .C_HAS_QSPO_SRST(0), + .C_HAS_SPO(1), + .C_HAS_SPRA(0), + .C_HAS_WE(1), + .C_MEM_INIT_FILE("no_coe_file_loaded"), + .C_MEM_TYPE(2), + .C_PARSER_TYPE(1), + .C_PIPELINE_STAGES(0), + .C_QCE_JOINED(0), + .C_QUALIFY_WE(0), + .C_READ_MIF(0), + .C_REG_A_D_INPUTS(0), + .C_REG_DPRA_INPUT(0), + .C_SYNC_ENABLE(1), + .C_WIDTH(22) + ) + inst ( + .A(a), + .D(d), + .DPRA(dpra), + .CLK(clk), + .WE(we), + .SPO(spo), + .DPO(dpo), + .SPRA(), + .I_CE(), + .QSPO_CE(), + .QDPO_CE(), + .QDPO_CLK(), + .QSPO_RST(), + .QDPO_RST(), + .QSPO_SRST(), + .QDPO_SRST(), + .QSPO(), + .QDPO() + ); + +// synthesis translate_on + +endmodule diff --git a/fpga/ipcore_dir/PrefetchTagRAM.veo b/fpga/ipcore_dir/PrefetchTagRAM.veo new file mode 100644 index 0000000..1e7760b --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.veo @@ -0,0 +1,60 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used solely * +* for design, simulation, implementation and creation of design files * +* limited to Xilinx devices or technologies. Use with non-Xilinx * +* devices or technologies is expressly prohibited and immediately * +* terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY * +* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY * +* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE * +* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS * +* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY * +* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY * +* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY * +* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support appliances, * +* devices, or systems. Use in such applications are expressly * +* prohibited. * +* * +* (c) Copyright 1995-2021 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ + +/******************************************************************************* +* Generated from core with identifier: xilinx.com:ip:dist_mem_gen:7.2 * +* * +* Rev 1. The LogiCORE Xilinx Distributed Memory Generator creates area * +* and performance optimized ROM blocks, single and dual port * +* distributed memories, and SRL16-based memories for Xilinx FPGAs. The * +* core supersedes the previously released LogiCORE Distributed Memory * +* core. Use this core in all new designs for supported families * +* wherever a distributed memory is required. * +*******************************************************************************/ + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +PrefetchTagRAM your_instance_name ( + .a(a), // input [4 : 0] a + .d(d), // input [21 : 0] d + .dpra(dpra), // input [4 : 0] dpra + .clk(clk), // input clk + .we(we), // input we + .spo(spo), // output [21 : 0] spo + .dpo(dpo) // output [21 : 0] dpo +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file PrefetchTagRAM.v when simulating +// the core, PrefetchTagRAM. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/fpga/ipcore_dir/PrefetchTagRAM.xco b/fpga/ipcore_dir/PrefetchTagRAM.xco new file mode 100644 index 0000000..6d94e20 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.xco @@ -0,0 +1,73 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Sun Oct 31 18:22:04 2021 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:dist_mem_gen:7.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx9 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = ftg256 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2 +# END Select +# BEGIN Parameters +CSET ce_overrides=ce_overrides_sync_controls +CSET coefficient_file=no_coe_file_loaded +CSET common_output_ce=false +CSET common_output_clk=false +CSET component_name=PrefetchTagRAM +CSET data_width=22 +CSET default_data=0 +CSET default_data_radix=16 +CSET depth=32 +CSET dual_port_address=non_registered +CSET dual_port_output_clock_enable=false +CSET input_clock_enable=false +CSET input_options=non_registered +CSET memory_type=dual_port_ram +CSET output_options=non_registered +CSET pipeline_stages=0 +CSET qualify_we_with_i_ce=false +CSET reset_qdpo=false +CSET reset_qsdpo=false +CSET reset_qspo=false +CSET simple_dual_port_address=non_registered +CSET simple_dual_port_output_clock_enable=false +CSET single_port_output_clock_enable=false +CSET sync_reset_qdpo=false +CSET sync_reset_qsdpo=false +CSET sync_reset_qspo=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2012-11-21T20:07:40Z +# END Extra information +GENERATE +# CRC: 91d9be1 diff --git a/fpga/ipcore_dir/PrefetchTagRAM.xise b/fpga/ipcore_dir/PrefetchTagRAM.xise new file mode 100644 index 0000000..920473f --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM.xise @@ -0,0 +1,402 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/ipcore_dir/PrefetchTagRAM/dist_mem_gen_v7_2_readme.txt b/fpga/ipcore_dir/PrefetchTagRAM/dist_mem_gen_v7_2_readme.txt new file mode 100644 index 0000000..3072310 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/dist_mem_gen_v7_2_readme.txt @@ -0,0 +1,205 @@ +CHANGE LOG for LogiCORE Distributed Memory Generator V7.2 Rev 1 + + Release Date: December 18, 2012 +-------------------------------------------------------------------------------- + +Table of Contents + +1. INTRODUCTION +2. DEVICE SUPPORT +3. NEW FEATURE HISTORY +4. RESOLVED ISSUES +5. KNOWN ISSUES & LIMITATIONS +6. TECHNICAL SUPPORT & FEEDBACK +7. CORE RELEASE HISTORY +8. LEGAL DISCLAIMER + +-------------------------------------------------------------------------------- + + +1. INTRODUCTION + +For installation instructions for this release, please go to: + + http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm + +For system requirements: + + http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm + +This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator v7.2 Rev 1 +solution. For the latest core updates, see the product page at: + + http://www.xilinx.com/products/ipcenter/DIST_MEM_GEN.htm + +................................................................................ + + +2. DEVICE SUPPORT + + + 2.1 ISE + + The following device families are supported by the core for this release. + + + All 7 Series devices + Zynq-7000 devices + All Virtex-6 devices + All Spartan-6 devices + All Virtex-5 devices + All Spartan-3 devices + All Virtex-4 devices + + + 2.2 Vivado + + All 7 Series devices + Zynq-7000 devices + +................................................................................ + + +3. NEW FEATURE HISTORY + + + 3.1 ISE + + - ISE 14.4 software support + + + 3.2 Vivado + + - 2012.4 software support + +................................................................................ + + +4. RESOLVED ISSUES + + + 4.1 ISE + + - N/A + + + 4.2 Vivado + + - N/A + + +................................................................................ + +5. KNOWN ISSUES & LIMITATIONS + + + 5.1 ISE + + There are not known issues for v7.2 Rev 1 of this core at time of release: + + 5.2 Vivado + + The following are known issues for v7.2 Rev 1 of this core at time of release: + + 1. Description: When Trying to upgrade to latest version of DMG from older verions, following error message is seen + ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work. + + CR 665836 + +The most recent information, including known issues, workarounds, and +resolutions for this version is provided in the IP Release Notes Guide +located at + + www.xilinx.com/support/documentation/user_guides/xtp025.pdf + +................................................................................ + + +6. TECHNICAL SUPPORT & FEEDBACK + + +To obtain technical support, create a WebCase at www.xilinx.com/support. +Questions are routed to a team with expertise using this product. + +Xilinx provides technical support for use of this product when used +according to the guidelines described in the core documentation, and +cannot guarantee timing, functionality, or support of this product for +designs that do not follow specified guidelines. + +................................................................................ + + +7. CORE RELEASE HISTORY + + +Date By Version Description +================================================================================ +12/18/2012 Xilinx, Inc. 7.2 Rev 1 ISE 14.4 and Vivado 2012.4 support +07/25/2012 Xilinx, Inc. 7.2 ISE 14.2 and Vivado 2012.2 support; Example test bench support +04/24/2012 Xilinx, Inc. 7.1 ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support +01/18/2012 Xilinx, Inc. 6.3 ISE 13.4 support; Artix-7L and Automotive Artix-7 device support +06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support +03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support +04/19/2010 Xilinx, Inc. 5.1 ISE 12.1 support +12/02/2009 Xilinx, Inc. 4.3 ISE 11.4 support; Spartan-6 Lower Power and Automotive Spartan-6 device support +09/16/2009 Xilinx, Inc. 4.2 11.3 support; Virtex-6 Lower Power and Virtex-6 HXT device support +06/24/2009 Xilinx, Inc. 4.1.1 11.2 support; Virtex-6 CXT device support +04/24/2009 Xilinx, Inc. 4.1 11.1 support; Revised to v4.1; Virtex-6 and Spartan-6 support +03/24/2008 Xilinx, Inc. 3.4 10.1 support; Revised to v3.4. +04/02/2007 Xilinx, Inc. 3.3 9.1i support; Revised to v3.3; Spartan-3AN and Spartan-3A DSP support +09/21/2006 Xilinx, Inc. 3.2 8.2i support; Revised to v3.2; Spartan-3A support +07/13/2006 Xilinx, Inc. 3.1 8.2i support; Revised to v3.1 +01/18/2006 Xilinx, Inc. 2.1 8.1i support; Revised to v2.1 +04/28/2005 Xilinx, Inc. 1.1 7.1i Service Pack 1 support; First release +================================================================================ + +................................................................................ + + +8. LEGAL DISCLAIMER + +(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved. + + This file contains confidential and proprietary information + of Xilinx, Inc. and is protected under U.S. and + international copyright and other intellectual property + laws. + + DISCLAIMER + This disclaimer is not a license and does not grant any + rights to the materials distributed herewith. Except as + otherwise provided in a valid license issued to you by + Xilinx, and to the maximum extent permitted by applicable + law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + (2) Xilinx shall not be liable (whether in contract or tort, + including negligence, or under any other theory of + liability) for any loss or damage of any kind or nature + related to, arising under or in connection with these + materials, including for any direct, or any indirect, + special, incidental, or consequential loss or damage + (including loss of data, profits, goodwill, or any type of + loss or damage suffered as a result of any action brought + by a third party) even if such damage or loss was + reasonably foreseeable or Xilinx had been advised of the + possibility of the same. + + CRITICAL APPLICATIONS + Xilinx products are not designed or intended to be fail- + safe, or for use in any application requiring fail-safe + performance, such as life-support or safety devices or + systems, Class III medical devices, nuclear facilities, + applications related to the deployment of airbags, or any + other applications that could lead to death, personal + injury, or severe property or environmental damage + (individually and collectively, "Critical + Applications"). Customer assumes the sole risk and + liability of any use of Xilinx products in Critical + Applications, subject only to applicable laws and + regulations governing limitations on product liability. + + THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + PART OF THIS FILE AT ALL TIMES. diff --git a/fpga/ipcore_dir/PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html b/fpga/ipcore_dir/PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html new file mode 100644 index 0000000..a385482 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html @@ -0,0 +1,216 @@ + + +dist_mem_gen_v7_2_vinfo + + + +

+CHANGE LOG for LogiCORE Distributed Memory Generator V7.2 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator v7.2 Rev 1
+solution. For the latest core updates, see the product page at:
+
+   www.xilinx.com/products/ipcenter/DIST_MEM_GEN.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+
+    The following device families are supported by the core for this release.
+
+
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+
+
+  2.2 Vivado 
+
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+
+  3.2 Vivado
+  
+    - 2012.4 software support
+
+................................................................................
+
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+
+    There are not known issues for v7.2 Rev 1 of this core at time of release:
+
+  5.2 Vivado 
+
+    The following are known issues for v7.2 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of DMG from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836 
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes Guide
+located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  7.2 Rev 1    ISE 14.4 and Vivado 2012.4 support
+07/25/2012  Xilinx, Inc.  7.2          ISE 14.2 and Vivado 2012.2 support; Example test bench support
+04/24/2012  Xilinx, Inc.  7.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+01/18/2012  Xilinx, Inc.  6.3          ISE 13.4 support; Artix-7L and Automotive Artix-7 device support
+06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  6.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support
+04/19/2010  Xilinx, Inc.  5.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  4.3          ISE 11.4 support; Spartan-6 Lower Power and Automotive Spartan-6 device support
+09/16/2009  Xilinx, Inc.  4.2          11.3 support; Virtex-6 Lower Power and Virtex-6 HXT device support
+06/24/2009  Xilinx, Inc.  4.1.1        11.2 support; Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  4.1          11.1 support; Revised to v4.1; Virtex-6 and Spartan-6 support
+03/24/2008  Xilinx, Inc.  3.4          10.1 support; Revised to v3.4.
+04/02/2007  Xilinx, Inc.  3.3          9.1i support; Revised to v3.3; Spartan-3AN and Spartan-3A DSP support
+09/21/2006  Xilinx, Inc.  3.2          8.2i support; Revised to v3.2; Spartan-3A support
+07/13/2006  Xilinx, Inc.  3.1          8.2i support; Revised to v3.1
+01/18/2006  Xilinx, Inc.  2.1          8.1i support; Revised to v2.1
+04/28/2005  Xilinx, Inc.  1.1          7.1i Service Pack 1 support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.
+
+
+ + diff --git a/fpga/ipcore_dir/PrefetchTagRAM/doc/pg063-dist-mem-gen.pdf b/fpga/ipcore_dir/PrefetchTagRAM/doc/pg063-dist-mem-gen.pdf new file mode 100644 index 0000000..7235b34 Binary files /dev/null and b/fpga/ipcore_dir/PrefetchTagRAM/doc/pg063-dist-mem-gen.pdf differ diff --git a/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.ucf b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.ucf new file mode 100644 index 0000000..2bee852 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.ucf @@ -0,0 +1,56 @@ +################################################################################ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLK" TNM_NET = "CLK"; +TIMESPEC "TS_CLK" = PERIOD "CLK" 50 MHZ; + + +################################################################################ diff --git a/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.vhd b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.vhd new file mode 100644 index 0000000..e43d958 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.vhd @@ -0,0 +1,135 @@ + + +-------------------------------------------------------------------------------- +-- +-- Distributed Memory Generator Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- +-- Description: +-- This is the actual DMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity PrefetchTagRAM_exdes is + PORT ( + DPRA : IN STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + CLK : IN STD_LOGIC := '0'; + WE : IN STD_LOGIC := '0'; + SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + A : IN STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0) + := (OTHERS => '0'); + D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0') + ); + +end PrefetchTagRAM_exdes; + + + +architecture xilinx of PrefetchTagRAM_exdes is + + SIGNAL CLK_i : std_logic; + + component PrefetchTagRAM is + PORT ( + + DPRA : IN STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + CLK : IN STD_LOGIC; + WE : IN STD_LOGIC; + SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + A : IN STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0) + := (OTHERS => '0'); + D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0') + +); + end component; + + +begin + + dmg0 : PrefetchTagRAM + port map ( + + DPRA => DPRA, + CLK => CLK_i, + WE => WE, + SPO => SPO, + DPO => DPO, + A => A, + D => D + + ); + +clk_buf: bufg + PORT MAP( + i => CLK, + o => CLK_i + ); + + + +end xilinx; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.xdc b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.xdc new file mode 100644 index 0000000..3b5eb12 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.xdc @@ -0,0 +1,56 @@ +################################################################################ +# +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +create_clock -name "TS_CLK" -period 20.0 [ get_ports CLK ] + + +################################################################################ diff --git a/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_prod_exdes.vhd b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_prod_exdes.vhd new file mode 100644 index 0000000..e7cd2d7 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/example_design/PrefetchTagRAM_prod_exdes.vhd @@ -0,0 +1,146 @@ + + +-------------------------------------------------------------------------------- +-- +-- Distributed Memory Generator v6.3 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- +-- Description: +-- This is the actual DMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.vcomponents.all; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +entity PrefetchTagRAM_exdes is + PORT ( + A : IN STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0) + := (OTHERS => '0'); + D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0'); + DPRA : IN STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + SPRA : IN STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + CLK : IN STD_LOGIC := '0'; + WE : IN STD_LOGIC := '0'; + I_CE : IN STD_LOGIC := '1'; + QSPO_CE : IN STD_LOGIC := '1'; + QDPO_CE : IN STD_LOGIC := '1'; + QDPO_CLK : IN STD_LOGIC := '0'; + QSPO_RST : IN STD_LOGIC := '0'; + QDPO_RST : IN STD_LOGIC := '0'; + QSPO_SRST : IN STD_LOGIC := '0'; + QDPO_SRST : IN STD_LOGIC := '0'; + SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + QSPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + QDPO : OUT STD_LOGIC_VECTOR(22-1 downto 0) + ); + +end PrefetchTagRAM_exdes; + + + +architecture xilinx of PrefetchTagRAM_exdes is + + SIGNAL CLK_i : std_logic; + + component PrefetchTagRAM is + PORT ( + + DPRA : IN STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + CLK : IN STD_LOGIC; + WE : IN STD_LOGIC; + SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + A : IN STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0) + := (OTHERS => '0'); + D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0') + +); + end component; + + +begin + + dmg0 : PrefetchTagRAM + port map ( + + DPRA => DPRA, + CLK => CLK_i, + WE => WE, + SPO => SPO, + DPO => DPO, + A => A, + D => D + + ); + +clk_buf: bufg + PORT map( + i => CLK, + o => CLK_i + ); + + + +end xilinx; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/implement.bat b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement.bat new file mode 100644 index 0000000..241e13a --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement.bat @@ -0,0 +1,85 @@ +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +copy PrefetchTagRAM_exdes.ngc .\results\ + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\PrefetchTagRAM.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\PrefetchTagRAM_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx9-ftg256-2 -sd ../../../ PrefetchTagRAM_exdes + +echo 'Running map' +map PrefetchTagRAM_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm PrefetchTagRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/implement.sh b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement.sh new file mode 100644 index 0000000..f0cb8ea --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement.sh @@ -0,0 +1,85 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with XST'; +xst -ifn xst.scr +cp PrefetchTagRAM_exdes.ngc ./results/ + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../PrefetchTagRAM.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/PrefetchTagRAM_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx9-ftg256-2 -sd ../../../ PrefetchTagRAM_exdes + +echo 'Running map' +map PrefetchTagRAM_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm PrefetchTagRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/implement_synplify.bat b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement_synplify.bat new file mode 100644 index 0000000..ac507e2 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement_synplify.bat @@ -0,0 +1,84 @@ +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem Clean up the results directory +rmdir /S /Q results +mkdir results + +rem Synthesize the VHDL Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + + +rem Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +copy ..\..\PrefetchTagRAM.ngc results\ + + +rem Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +copy ..\example_design\PrefetchTagRAM_exdes.ucf results\ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx9-ftg256-2 -sd ../../../ PrefetchTagRAM_exdes + +echo 'Running map' +map PrefetchTagRAM_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm PrefetchTagRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/implement_synplify.sh b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement_synplify.sh new file mode 100644 index 0000000..ae4ad23 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/implement_synplify.sh @@ -0,0 +1,84 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +# Clean up the results directory +rm -rf results +mkdir results + +#Synthesize the Wrapper Files + +echo 'Synthesizing example design with Synplify' +synplify_pro -batch synplify.prj -licensetype synplifypro_xilinx + +# Copy the netlist generated by Coregen +echo 'Copying files from the netlist directory to the results directory' +cp ../../PrefetchTagRAM.ngc results/ + +# Copy the constraints files generated by Coregen +echo 'Copying files from constraints directory to results directory' +cp ../example_design/PrefetchTagRAM_exdes.ucf results/ + +cd results + +echo 'Running ngdbuild' +ngdbuild -p xc6slx9-ftg256-2 -sd ../../../ PrefetchTagRAM_exdes + +echo 'Running map' +map PrefetchTagRAM_exdes -o mapped.ncd + +echo 'Running par' +par mapped.ncd routed.ncd + +echo 'Running trce' +trce -e 10 routed.ncd mapped.pcf -o routed + +echo 'Running design through bitgen' +bitgen -w routed + +echo 'Running netgen to create gate level Verilog model' +netgen -ofmt verilog -sim -tm PrefetchTagRAM_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v + diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.bat b/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.bat new file mode 100644 index 0000000..1852044 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.bat @@ -0,0 +1,54 @@ +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. + +rem ----------------------------------------------------------------------------- +rem Script to synthesize and implement the Coregen FIFO Generator +rem ----------------------------------------------------------------------------- +rmdir /S /Q results +mkdir results +cd results +copy ..\..\..\PrefetchTagRAM.ngc . +planAhead -mode batch -source ..\planAhead_ise.tcl diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.sh b/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.sh new file mode 100644 index 0000000..50eb20d --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.sh @@ -0,0 +1,55 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +#----------------------------------------------------------------------------- +# Script to synthesize and implement the Coregen FIFO Generator +#----------------------------------------------------------------------------- +rm -rf results +mkdir results +cd results +cp ../../../PrefetchTagRAM.ngc . +planAhead -mode batch -source ../planAhead_ise.tcl diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.tcl b/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.tcl new file mode 100644 index 0000000..b0718c8 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/planAhead_ise.tcl @@ -0,0 +1,66 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. + +set device xc6slx9ftg256-2 +set projName PrefetchTagRAM +set design PrefetchTagRAM +set projDir [file dirname [info script]] +create_project $projName $projDir/results/$projName -part $device -force +set_property design_mode RTL [current_fileset -srcset] +set top_module PrefetchTagRAM_exdes +add_files -norecurse {../../example_design/PrefetchTagRAM_exdes.vhd} +add_files -norecurse {./PrefetchTagRAM.ngc} +import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/PrefetchTagRAM_exdes.xdc} +set_property top PrefetchTagRAM_exdes [get_property srcset [current_run]] +synth_design +opt_design +place_design +route_design +write_sdf -rename_top_module PrefetchTagRAM_exdes -file routed.sdf +write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module PrefetchTagRAM_exdes routed.v +report_timing -nworst 30 -path_type full -file routed.twr +report_drc -file report.drc +write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/xst.prj b/fpga/ipcore_dir/PrefetchTagRAM/implement/xst.prj new file mode 100644 index 0000000..26a1312 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/xst.prj @@ -0,0 +1,2 @@ + +work ../example_design/PrefetchTagRAM_exdes.vhd diff --git a/fpga/ipcore_dir/PrefetchTagRAM/implement/xst.scr b/fpga/ipcore_dir/PrefetchTagRAM/implement/xst.scr new file mode 100644 index 0000000..0efd65e --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/implement/xst.scr @@ -0,0 +1,14 @@ + +run +-ifmt VHDL +-ent PrefetchTagRAM_exdes +-p xc6slx9-ftg256-2 +-ifn xst.prj +-write_timing_constraints No +-iobuf YES +-max_fanout 100 +-ofn PrefetchTagRAM_exdes +-ofmt NGC +-bus_delimiter () +-hierarchy_separator / +-case Maintain diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb.vhd new file mode 100644 index 0000000..6814859 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb.vhd @@ -0,0 +1,130 @@ +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: PrefetchTagRAM_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY PrefetchTagRAM_tb IS +END ENTITY; + + +ARCHITECTURE PrefetchTagRAM_tb_ARCH OF PrefetchTagRAM_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "Test Completed Successfully" + SEVERITY FAILURE; + END IF; +END PROCESS; + + PrefetchTagRAM_tb_synth_inst:ENTITY work.PrefetchTagRAM_tb_synth + GENERIC MAP (C_ROM_SYNTH => 0) + PORT MAP( + CLK_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_agen.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_agen.vhd new file mode 100644 index 0000000..2bbeb45 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_agen.vhd @@ -0,0 +1,118 @@ + +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_agen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY PrefetchTagRAM_TB_AGEN IS + GENERIC ( + C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END PrefetchTagRAM_TB_AGEN; + +ARCHITECTURE BEHAVIORAL OF PrefetchTagRAM_TB_AGEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_checker.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_checker.vhd new file mode 100644 index 0000000..dfaeabe --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_checker.vhd @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.PrefetchTagRAM_TB_PKG.ALL; + +ENTITY PrefetchTagRAM_TB_CHECKER IS + GENERIC ( + WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END PrefetchTagRAM_TB_CHECKER; + +ARCHITECTURE CHECKER_ARCH OF PrefetchTagRAM_TB_CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DGEN_INST:ENTITY work.PrefetchTagRAM_TB_DGEN + GENERIC MAP ( + DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_dgen.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_dgen.vhd new file mode 100644 index 0000000..b5336ae --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_dgen.vhd @@ -0,0 +1,141 @@ + +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_dgen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.PrefetchTagRAM_TB_PKG.ALL; + +ENTITY PrefetchTagRAM_TB_DGEN IS + GENERIC ( + DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END PrefetchTagRAM_TB_DGEN; + +ARCHITECTURE DATA_GEN_ARCH OF PrefetchTagRAM_TB_DGEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.PrefetchTagRAM_TB_RNG + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_pkg.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_pkg.vhd new file mode 100644 index 0000000..bb7cd5a --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_pkg.vhd @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_pkg.vhd +-- +-- Description: +-- DMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE PrefetchTagRAM_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END PrefetchTagRAM_TB_PKG; + +PACKAGE BODY PrefetchTagRAM_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END PrefetchTagRAM_TB_PKG; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_rng.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_rng.vhd new file mode 100644 index 0000000..69a37af --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_rng.vhd @@ -0,0 +1,113 @@ + +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_rng.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY PrefetchTagRAM_TB_RNG IS + GENERIC ( + WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END PrefetchTagRAM_TB_RNG; + +ARCHITECTURE BEHAVIORAL OF PrefetchTagRAM_TB_RNG IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_stim_gen.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_stim_gen.vhd new file mode 100644 index 0000000..820b0fc --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_stim_gen.vhd @@ -0,0 +1,491 @@ +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Stimulus Generator For Dual Port RAM Configuration +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For ROM +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; + +USE work.PrefetchTagRAM_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC_DRAM IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC_DRAM; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_DRAM IS + SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.PrefetchTagRAM_TB_PKG.ALL; + +ENTITY PrefetchTagRAM_TB_STIM_GEN IS + PORT( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + A : OUT STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + D : OUT STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0'); + DPRA : OUT STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + WE : OUT STD_LOGIC := '0'; + DATA_IN : IN STD_LOGIC_VECTOR (21 DOWNTO 0); --OUTPUT VECTOR + DATA_IN_B : IN STD_LOGIC_VECTOR (21 DOWNTO 0); --OUTPUT VECTOR + + + CHECK_DATA : OUT STD_LOGIC_VECTOR(1 downto 0) := (OTHERS => '0') + ); +END PrefetchTagRAM_TB_STIM_GEN; + +ARCHITECTURE BEHAVIORAL OF PrefetchTagRAM_TB_STIM_GEN IS + CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + CONSTANT DATA_PART_CNT_A: INTEGER:=1; + CONSTANT DATA_PART_CNT_B: INTEGER:=1; + SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DO_READ_REG_A : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); + SIGNAL DO_READ_REG_B : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); + SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); + SIGNAL D_INT_A : STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL D_INT_B : STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DO_WRITE_A : STD_LOGIC := '0'; + SIGNAL DO_WRITE_B : STD_LOGIC := '0'; + SIGNAL DO_WRITE : STD_LOGIC := '0'; + SIGNAL DO_READ_A : STD_LOGIC := '0'; + SIGNAL DO_READ_B : STD_LOGIC := '0'; + SIGNAL COUNT : integer := 0; + SIGNAL COUNT_B : integer := 0; + CONSTANT WRITE_CNT_A : integer := 8; + CONSTANT READ_CNT_A : integer := 8; + CONSTANT WRITE_CNT_B : integer := 8; + CONSTANT READ_CNT_B : integer := 8; + + signal porta_wr_rd : std_logic:='0'; + signal portb_wr_rd : std_logic:='0'; + signal porta_wr_rd_complete: std_logic:='0'; + signal portb_wr_rd_complete: std_logic:='0'; + signal incr_cnt : std_logic :='0'; + signal incr_cnt_b : std_logic :='0'; + + SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0'; + SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0'; + SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0'; + SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0'; + SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0'; + SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0'; + SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0'; + SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0'; + SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0'; + SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0'; + SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0'; + SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0'; +BEGIN + WRITE_ADDR_INT_A(4 DOWNTO 0) <= WRITE_ADDR_A(4 DOWNTO 0); + READ_ADDR_INT_A(4 DOWNTO 0) <= READ_ADDR_A(4 DOWNTO 0); + WRITE_ADDR_INT_B(4 DOWNTO 0) <= WRITE_ADDR_B(4 DOWNTO 0); + READ_ADDR_INT_B(4 DOWNTO 0) <= READ_ADDR_B(4 DOWNTO 0); + A <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A); + D <= IF_THEN_ELSE(DO_WRITE_A='1',D_INT_A,D_INT_B); + DPRA <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B); + CHECK_DATA(0) <= DO_READ_A; + CHECK_DATA(1) <= DO_READ_B; + DO_WRITE <= DO_WRITE_A OR DO_WRITE_B; + +RD_GEN_INST_A:ENTITY work.PrefetchTagRAM_TB_AGEN + GENERIC MAP( + C_MAX_DEPTH => 32 + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_READ_A, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR_A + ); + +WR_AGEN_INST_A:ENTITY work.PrefetchTagRAM_TB_AGEN + GENERIC MAP( + C_MAX_DEPTH => 32 ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_WRITE_A, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR_A + ); + +WR_DGEN_INST_A:ENTITY work.PrefetchTagRAM_TB_DGEN + GENERIC MAP ( + DATA_GEN_WIDTH => 22, + DOUT_WIDTH => 22, + DATA_PART_CNT => DATA_PART_CNT_A, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => DO_WRITE_A, + DATA_OUT => D_INT_A + ); + +RD_AGEN_INST_B:ENTITY work.PrefetchTagRAM_TB_AGEN + GENERIC MAP( + C_MAX_DEPTH => 32 + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_READ_B, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR_B + ); + +WR_AGEN_INST_B:ENTITY work.PrefetchTagRAM_TB_AGEN + GENERIC MAP( + C_MAX_DEPTH => 32 ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DO_WRITE_B, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR_B + ); + +WR_DGEN_INST_B:ENTITY work.PrefetchTagRAM_TB_DGEN + GENERIC MAP ( + DATA_GEN_WIDTH => 22, + DOUT_WIDTH => 22, + DATA_PART_CNT => DATA_PART_CNT_B, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => DO_WRITE_B, + DATA_OUT => D_INT_B + ); + +PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + LATCH_PORTB_WR_RD_COMPLETE<='0'; + ELSIF(PORTB_WR_RD_COMPLETE='1') THEN + LATCH_PORTB_WR_RD_COMPLETE <='1'; + ELSIF(PORTA_WR_RD_HAPPENED='1') THEN + LATCH_PORTB_WR_RD_COMPLETE<='0'; + END IF; + END IF; +END PROCESS; + +PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + PORTB_WR_RD_L1 <='0'; + PORTB_WR_RD_L2 <='0'; + ELSE + PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE; + PORTB_WR_RD_L2 <= PORTB_WR_RD_L1; + END IF; + END IF; +END PROCESS; + +PORTA_WR_RD_EN: PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + PORTA_WR_RD <='1'; + ELSE + PORTA_WR_RD <= PORTB_WR_RD_L2; + END IF; + END IF; +END PROCESS; + +PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + PORTA_WR_RD_R1 <='0'; + PORTA_WR_RD_R2 <='0'; + ELSE + PORTA_WR_RD_R1 <=PORTA_WR_RD; + PORTA_WR_RD_R2 <=PORTA_WR_RD_R1; + END IF; + END IF; +END PROCESS; + +PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2; + +PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + LATCH_PORTA_WR_RD_COMPLETE<='0'; + ELSIF(PORTA_WR_RD_COMPLETE='1') THEN + LATCH_PORTA_WR_RD_COMPLETE <='1'; + ELSIF(PORTB_WR_RD_HAPPENED='1') THEN + LATCH_PORTA_WR_RD_COMPLETE<='0'; + END IF; + END IF; +END PROCESS; + +PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + PORTA_WR_RD_L1 <='0'; + PORTA_WR_RD_L2 <='0'; + ELSE + PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE; + PORTA_WR_RD_L2 <= PORTA_WR_RD_L1; + END IF; + END IF; +END PROCESS; + + +PORTB_EN: PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + PORTB_WR_RD <='0'; + ELSE + PORTB_WR_RD <= PORTA_WR_RD_L2; + END IF; + END IF; +END PROCESS; + +PROCESS(CLK) +BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + PORTB_WR_RD_R1 <='0'; + PORTB_WR_RD_R2 <='0'; + ELSE + PORTB_WR_RD_R1 <=PORTB_WR_RD; + PORTB_WR_RD_R2 <=PORTB_WR_RD_R1; + END IF; + END IF; +END PROCESS; + +---double registered of porta complete on portb clk +PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2; + +PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0'; + +start_counter: process(CLK) +begin + if(rising_edge(CLK)) then + if(RST='1') then + incr_cnt <= '0'; + elsif(porta_wr_rd ='1') then + incr_cnt <='1'; + elsif(porta_wr_rd_complete='1') then + incr_cnt <='0'; + end if; + end if; +end process; + +COUNTER: process(CLK) +begin + if(rising_edge(CLK)) then + if(RST='1') then + count <= 0; + elsif(incr_cnt='1') then + count<=count+1; + end if; + if(count=(WRITE_CNT_A+READ_CNT_A)) then + count<=0; + end if; + end if; +end process; + +DO_WRITE_A<='1' when (count WRITE_CNT_A and incr_cnt='1') else '0'; + +PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0'; + +startb_counter: process(CLK) +begin + if(rising_edge(CLK)) then + if(RST='1') then + incr_cnt_b <= '0'; + elsif(portb_wr_rd ='1') then + incr_cnt_b <='1'; + elsif(portb_wr_rd_complete='1') then + incr_cnt_b <='0'; + end if; + end if; +end process; + +COUNTER_B: process(CLK) +begin + if(rising_edge(CLK)) then + if(RST='1') then + count_b <= 0; + elsif(incr_cnt_b='1') then + count_b<=count_b+1; + end if; + if(count_b=WRITE_CNT_B+READ_CNT_B) then + count_b<=0; + end if; + end if; +end process; + +DO_WRITE_B<='1' when (count_b WRITE_CNT_B and incr_cnt_b='1') else '0'; + +BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE +BEGIN + DFF_RIGHT: IF I=0 GENERATE + BEGIN + SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_DRAM + PORT MAP( + Q => DO_READ_REG_A(0), + CLK => CLK, + RST => RST, + D => DO_READ_A + ); + END GENERATE DFF_RIGHT; + DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC_DRAM + PORT MAP( + Q => DO_READ_REG_A(I), + CLK => CLK, + RST => RST, + D => DO_READ_REG_A(I-1) + ); + END GENERATE DFF_OTHERS; +END GENERATE BEGIN_SHIFT_REG; + +BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE +BEGIN + DFF_RIGHT: IF I=0 GENERATE + BEGIN + SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_DRAM + PORT MAP( + Q => DO_READ_REG_B(0), + CLK => CLK, + RST => RST, + D => DO_READ_B + ); + END GENERATE DFF_RIGHT; + DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC_DRAM + PORT MAP( + Q => DO_READ_REG_B(I), + CLK => CLK, + RST => RST, + D => DO_READ_REG_B(I-1) + ); + END GENERATE DFF_OTHERS; +END GENERATE BEGIN_SHIFT_REG_B; + + + + WE <= IF_THEN_ELSE(DO_WRITE='1','1','0') ; + +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_synth.vhd b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_synth.vhd new file mode 100644 index 0000000..4bde059 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/PrefetchTagRAM_tb_synth.vhd @@ -0,0 +1,301 @@ + +-------------------------------------------------------------------------------- +-- +-- DIST MEM GEN Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: PrefetchTagRAM_tb_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.PrefetchTagRAM_TB_PKG.ALL; + +ENTITY PrefetchTagRAM_tb_synth IS +GENERIC ( + C_ROM_SYNTH : INTEGER := 0 + ); +PORT( + CLK_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END PrefetchTagRAM_tb_synth; + +ARCHITECTURE PrefetchTagRAM_synth_ARCH OF PrefetchTagRAM_tb_synth IS + +COMPONENT PrefetchTagRAM_exdes + PORT ( + DPRA : IN STD_LOGIC_VECTOR(5-1 downto 0) := (OTHERS => '0'); + CLK : IN STD_LOGIC := '0'; + WE : IN STD_LOGIC := '0'; + SPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + DPO : OUT STD_LOGIC_VECTOR(22-1 downto 0); + A : IN STD_LOGIC_VECTOR(5-1-(4*0*boolean'pos(5>4)) downto 0) + := (OTHERS => '0'); + D : IN STD_LOGIC_VECTOR(22-1 downto 0) := (OTHERS => '0') + ); + +END COMPONENT; + + CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22); + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i : STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL ADDR: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDR_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DPRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DPRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WE : STD_LOGIC:='0'; + SIGNAL WE_R : STD_LOGIC:='0'; + SIGNAL SPO: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL SPO_R: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DPO: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DPO_R: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL D: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL D_R: STD_LOGIC_VECTOR(21 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CHECKER_EN_R: STD_LOGIC:='0'; + SIGNAL CHECKER_ENB_R : STD_LOGIC := '0'; + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + +BEGIN + + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + PrefetchTagRAM_TB_STIM_GEN_INST:ENTITY work.PrefetchTagRAM_TB_STIM_GEN + PORT MAP( + CLK => clk_in_i, + RST => RSTA, + A => ADDR, + D => D, + DPRA => DPRA, + WE => WE, + DATA_IN => SPO_R, + DATA_IN_B => DPO_R, + CHECK_DATA => CHECK_DATA_TDP + ); + + + DMG_DATA_CHECKER_INST_A: ENTITY work.PrefetchTagRAM_TB_CHECKER + GENERIC MAP ( + WRITE_WIDTH => 22, + READ_WIDTH => 22 ) + PORT MAP ( + CLK => CLKA, + RST => RSTA, + EN => CHECKER_EN_R, + DATA_IN => SPO_R, + STATUS => ISSUE_FLAG(0) + ); + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RSTA='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + DMG_DATA_CHECKER_INST_B: ENTITY work.PrefetchTagRAM_TB_CHECKER + GENERIC MAP ( + WRITE_WIDTH => 22, + READ_WIDTH => 22 ) + PORT MAP ( + CLK => CLKA, + RST => RSTA, + EN => CHECKER_ENB_R, + DATA_IN => DPO_R, + STATUS => ISSUE_FLAG(1) + ); + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RSTA='1') THEN + CHECKER_ENB_R <= '0'; + ELSE + CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(STIM_CNT); + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(ADDR(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW + 1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + DPRA_R <= (OTHERS=>'0') AFTER 50 ns; + WE_R <= '0' AFTER 50 ns; + SPO_R <= (OTHERS=>'0') AFTER 50 ns; + DPO_R <= (OTHERS=>'0') AFTER 50 ns; + D_R <= (OTHERS=>'0') AFTER 50 ns; + ELSE + DPRA_R <= DPRA AFTER 50 ns; + WE_R <= WE AFTER 50 ns; + SPO_R <= SPO AFTER 50 ns; + DPO_R <= DPO AFTER 50 ns; + D_R <= D AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDR_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDR_R <= ADDR AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + DMG_PORT: PrefetchTagRAM_exdes PORT MAP ( + DPRA => DPRA_R, + CLK => CLKA, + WE => WE_R, + SPO => SPO, + DPO => DPO, + A => ADDR_R, + D => D_R + + ); +END ARCHITECTURE; diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.bat b/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.bat new file mode 100644 index 0000000..8d2992e --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.bat @@ -0,0 +1,48 @@ +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.do b/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.do new file mode 100644 index 0000000..284f099 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.do @@ -0,0 +1,76 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../../PrefetchTagRAM.v +vcom -work work ../../example_design/PrefetchTagRAM_exdes.vhd + +echo "Compiling Test Bench Files" + +vcom -work work ../PrefetchTagRAM_tb_pkg.vhd +vcom -work work ../PrefetchTagRAM_tb_rng.vhd +vcom -work work ../PrefetchTagRAM_tb_dgen.vhd +vcom -work work ../PrefetchTagRAM_tb_agen.vhd +vcom -work work ../PrefetchTagRAM_tb_checker.vhd +vcom -work work ../PrefetchTagRAM_tb_stim_gen.vhd +vcom -work work ../PrefetchTagRAM_tb_synth.vhd +vcom -work work ../PrefetchTagRAM_tb.vhd + + +vlog -work work $env(XILINX)/verilog/src/glbl.v +vsim -novopt -t ps -L XilinxCoreLib_ver -L unisims_ver glbl work.PrefetchTagRAM_tb + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.sh b/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.sh new file mode 100644 index 0000000..edb1b0d --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/functional/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.bat b/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.bat new file mode 100644 index 0000000..8d2992e --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.bat @@ -0,0 +1,48 @@ +rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +rem +rem This file contains confidential and proprietary information +rem of Xilinx, Inc. and is protected under U.S. and +rem international copyright and other intellectual property +rem laws. +rem +rem DISCLAIMER +rem This disclaimer is not a license and does not grant any +rem rights to the materials distributed herewith. Except as +rem otherwise provided in a valid license issued to you by +rem Xilinx, and to the maximum extent permitted by applicable +rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +rem (2) Xilinx shall not be liable (whether in contract or tort, +rem including negligence, or under any other theory of +rem liability) for any loss or damage of any kind or nature +rem related to, arising under or in connection with these +rem materials, including for any direct, or any indirect, +rem special, incidental, or consequential loss or damage +rem (including loss of data, profits, goodwill, or any type of +rem loss or damage suffered as a result of any action brought +rem by a third party) even if such damage or loss was +rem reasonably foreseeable or Xilinx had been advised of the +rem possibility of the same. +rem +rem CRITICAL APPLICATIONS +rem Xilinx products are not designed or intended to be fail- +rem safe, or for use in any application requiring fail-safe +rem performance, such as life-support or safety devices or +rem systems, Class III medical devices, nuclear facilities, +rem applications related to the deployment of airbags, or any +rem other applications that could lead to death, personal +rem injury, or severe property or environmental damage +rem (individually and collectively, "Critical +rem Applications"). Customer assumes the sole risk and +rem liability of any use of Xilinx products in Critical +rem Applications, subject only to applicable laws and +rem regulations governing limitations on product liability. +rem +rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +rem PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.do b/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.do new file mode 100644 index 0000000..c56b226 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.do @@ -0,0 +1,76 @@ +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +set work work +#-------------------------------------------------------------------------------- + vlib work +vmap work work + +echo "Compiling Core Verilog UNISIM/Behavioral model" +vlog -work work ../../implement/results/routed.v + +echo "Compiling Test Bench Files" + +vcom -work work ../PrefetchTagRAM_tb_pkg.vhd +vcom -work work ../PrefetchTagRAM_tb_rng.vhd +vcom -work work ../PrefetchTagRAM_tb_dgen.vhd +vcom -work work ../PrefetchTagRAM_tb_agen.vhd +vcom -work work ../PrefetchTagRAM_tb_checker.vhd +vcom -work work ../PrefetchTagRAM_tb_stim_gen.vhd +vcom -work work ../PrefetchTagRAM_tb_synth.vhd +vcom -work work ../PrefetchTagRAM_tb.vhd + + +vlog -work work $env(XILINX)/verilog/src/glbl.v + vsim -novopt -t ps -L simprims_ver +transport_int_delays -sdftyp /PrefetchTagRAM_tb/PrefetchTagRAM_tb_synth_inst/dmg_port=../../implement/results/routed.sdf $work.PrefetchTagRAM_tb $work.glbl -novopt + +#Disabled waveform to save the disk space +add log -r /* +#Ignore integer warnings at time 0 +set StdArithNoWarnings 1 +run 0 +set StdArithNoWarnings 0 + +run -all diff --git a/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.sh b/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.sh new file mode 100644 index 0000000..edb1b0d --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM/simulation/timing/simulate_mti.sh @@ -0,0 +1,49 @@ +#!/bin/sh +# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +#-------------------------------------------------------------------------------- + +vsim -c -do simulate_mti.do diff --git a/fpga/ipcore_dir/PrefetchTagRAM_flist.txt b/fpga/ipcore_dir/PrefetchTagRAM_flist.txt new file mode 100644 index 0000000..a82bfe3 --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM_flist.txt @@ -0,0 +1,42 @@ +# Output products list for +PrefetchTagRAM.asy +PrefetchTagRAM.gise +PrefetchTagRAM.ngc +PrefetchTagRAM.sym +PrefetchTagRAM.v +PrefetchTagRAM.veo +PrefetchTagRAM.xco +PrefetchTagRAM.xise +PrefetchTagRAM\dist_mem_gen_v7_2_readme.txt +PrefetchTagRAM\doc\dist_mem_gen_v7_2_vinfo.html +PrefetchTagRAM\doc\pg063-dist-mem-gen.pdf +PrefetchTagRAM\example_design\PrefetchTagRAM_exdes.ucf +PrefetchTagRAM\example_design\PrefetchTagRAM_exdes.vhd +PrefetchTagRAM\example_design\PrefetchTagRAM_exdes.xdc +PrefetchTagRAM\example_design\PrefetchTagRAM_prod_exdes.vhd +PrefetchTagRAM\implement\implement.bat +PrefetchTagRAM\implement\implement.sh +PrefetchTagRAM\implement\implement_synplify.bat +PrefetchTagRAM\implement\implement_synplify.sh +PrefetchTagRAM\implement\planAhead_ise.bat +PrefetchTagRAM\implement\planAhead_ise.sh +PrefetchTagRAM\implement\planAhead_ise.tcl +PrefetchTagRAM\implement\xst.prj +PrefetchTagRAM\implement\xst.scr +PrefetchTagRAM\simulation\PrefetchTagRAM_tb.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_agen.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_checker.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_dgen.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_pkg.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_rng.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_stim_gen.vhd +PrefetchTagRAM\simulation\PrefetchTagRAM_tb_synth.vhd +PrefetchTagRAM\simulation\functional\simulate_mti.bat +PrefetchTagRAM\simulation\functional\simulate_mti.do +PrefetchTagRAM\simulation\functional\simulate_mti.sh +PrefetchTagRAM\simulation\timing\simulate_mti.bat +PrefetchTagRAM\simulation\timing\simulate_mti.do +PrefetchTagRAM\simulation\timing\simulate_mti.sh +PrefetchTagRAM_flist.txt +PrefetchTagRAM_xmdf.tcl +_xmsgs\pn_parser.xmsgs diff --git a/fpga/ipcore_dir/PrefetchTagRAM_xmdf.tcl b/fpga/ipcore_dir/PrefetchTagRAM_xmdf.tcl new file mode 100644 index 0000000..0f5fc4c --- /dev/null +++ b/fpga/ipcore_dir/PrefetchTagRAM_xmdf.tcl @@ -0,0 +1,191 @@ +# The package naming convention is _xmdf +package provide PrefetchTagRAM_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is _xmdf +namespace eval ::PrefetchTagRAM_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::PrefetchTagRAM_xmdf::xmdfInit { instance } { +# Variable containing name of library into which module is compiled +# Recommendation: +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name PrefetchTagRAM +} +# ::PrefetchTagRAM_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::PrefetchTagRAM_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/dist_mem_gen_v7_2_readme.txt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/doc/pg063-dist-mem-gen.pdf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.ucf +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/example_design/PrefetchTagRAM_exdes.xdc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/example_design/PrefetchTagRAM_prod_exdes.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/implement.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/implement.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/implement_synplify.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/implement_synplify.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/planAhead_ise.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/planAhead_ise.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/planAhead_ise.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/xst.prj +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/implement/xst.scr +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_agen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_checker.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_dgen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_pkg.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_rng.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_stim_gen.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/PrefetchTagRAM_tb_synth.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/functional/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/functional/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/functional/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/timing/simulate_mti.bat +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/timing/simulate_mti.do +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM/simulation/timing/simulate_mti.sh +utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path PrefetchTagRAM_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module PrefetchTagRAM +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/fpga/ipcore_dir/_xmsgs/cg.xmsgs b/fpga/ipcore_dir/_xmsgs/cg.xmsgs index ff7e1b9..eaaae9a 100644 --- a/fpga/ipcore_dir/_xmsgs/cg.xmsgs +++ b/fpga/ipcore_dir/_xmsgs/cg.xmsgs @@ -8,13 +8,16 @@ Generating IP... -A core named 'CLK' already exists in the project. Output products for this core may be overwritten. +A core named 'PrefetchTagRAM' already exists in the project. Output products for this core may be overwritten. -A core named 'CLK' already exists in the project. Output products for this core may be overwritten. +A core named 'PrefetchTagRAM' already exists in the project. Output products for this core may be overwritten. -Component clk_wiz_v3_6 does not have a valid model name for Verilog synthesis +Pre-processing HDL files for 'PrefetchTagRAM'... + + +Overwriting existing file C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation Finished generation of ASY schematic symbol. diff --git a/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs b/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs index d66d577..1a5f4a5 100644 --- a/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs +++ b/fpga/ipcore_dir/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ -Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/CLK.v" into library work +Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/PrefetchTagRAM.v" into library work diff --git a/fpga/ipcore_dir/coregen.log b/fpga/ipcore_dir/coregen.log index 3f47a42..a6be0e2 100644 --- a/fpga/ipcore_dir/coregen.log +++ b/fpga/ipcore_dir/coregen.log @@ -1,49 +1,67 @@ INFO:sim:172 - Generating IP... Applying current project options... Finished applying current project options. -WARNING:sim - A core named 'CLK' already exists in the project. Output products - for this core may be overwritten. -Resolving generics for 'CLK'... -WARNING:sim - A core named 'CLK' already exists in the project. Output products - for this core may be overwritten. -Applying external generics to 'CLK'... -Delivering associated files for 'CLK'... -WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for - Verilog synthesis -Delivering EJava files for 'CLK'... -Delivered 3 files into directory -C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK -Delivered 1 file into directory -C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK +WARNING:sim - A core named 'PrefetchTagRAM' already exists in the project. + Output products for this core may be overwritten. +Resolving generics for 'PrefetchTagRAM'... +WARNING:sim - A core named 'PrefetchTagRAM' already exists in the project. + Output products for this core may be overwritten. +Applying external generics to 'PrefetchTagRAM'... +Delivering associated files for 'PrefetchTagRAM'... +Delivering EJava files for 'PrefetchTagRAM'... +Generating implementation netlist for 'PrefetchTagRAM'... +INFO:sim - Pre-processing HDL files for 'PrefetchTagRAM'... +Running synthesis for 'PrefetchTagRAM' +Running ngcbuild... +Writing VEO instantiation template for 'PrefetchTagRAM'... +Writing Verilog behavioral simulation model for 'PrefetchTagRAM'... +WARNING:sim - Overwriting existing file + C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM/ + doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation +Delivered 2 files into directory +C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM Generating ASY schematic symbol... -Loading device for application Rf_Device from file '6slx9.nph' in environment -C:\Xilinx\14.7\ISE_DS\ISE\. INFO:sim:949 - Finished generation of ASY schematic symbol. -Generating SYM schematic symbol for 'CLK'... +Generating SYM schematic symbol for 'PrefetchTagRAM'... +Generating metadata file... +Regenerating ISE project file for 'PrefetchTagRAM'... Generating ISE project... -XCO file found: CLK.xco -XMDF file found: CLK_xmdf.tcl -Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.asy +XCO file found: PrefetchTagRAM.xco +XMDF file found: PrefetchTagRAM_xmdf.tcl +Adding +C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.asy -view all -origin_type imported -Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.ucf +Adding +C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ngc -view all -origin_type created -Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.v +Checking file +"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ng +c" for project device match ... +File +"C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.ng +c" device information matches project device. +Adding +C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.sym +-view all -origin_type imported +Adding +C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.v -view all -origin_type created INFO:HDLCompiler:1845 - Analyzing Verilog file - "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.v" into - library work + "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM + .v" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. -Adding C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/CLK.veo +Adding +C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM.veo -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. -Top level has been set to "/CLK" +Top level has been set to "/PrefetchTagRAM" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory -Wrote CGP file for project 'CLK'. +Wrote CGP file for project 'PrefetchTagRAM'. diff --git a/fpga/ipcore_dir/create_PLL.tcl b/fpga/ipcore_dir/create_PLL.tcl new file mode 100644 index 0000000..7c6c434 --- /dev/null +++ b/fpga/ipcore_dir/create_PLL.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "PLL" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result diff --git a/fpga/ipcore_dir/create_PrefetchDataRAM.tcl b/fpga/ipcore_dir/create_PrefetchDataRAM.tcl new file mode 100644 index 0000000..965c135 --- /dev/null +++ b/fpga/ipcore_dir/create_PrefetchDataRAM.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:7.3" "PrefetchDataRAM" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:7.3) generated by Project Navigator" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result diff --git a/fpga/ipcore_dir/create_PrefetchTagRAM.tcl b/fpga/ipcore_dir/create_PrefetchTagRAM.tcl new file mode 100644 index 0000000..2da63f0 --- /dev/null +++ b/fpga/ipcore_dir/create_PrefetchTagRAM.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator create command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_create "xilinx.com:ip:dist_mem_gen:7.2" "PrefetchTagRAM" "Distributed Memory Generator" "Distributed Memory Generator (xilinx.com:ip:dist_mem_gen:7.2) generated by Project Navigator" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator create command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator create command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator create cancelled." +} +exit $result diff --git a/fpga/ipcore_dir/edit_PLL.tcl b/fpga/ipcore_dir/edit_PLL.tcl new file mode 100644 index 0000000..1358aa9 --- /dev/null +++ b/fpga/ipcore_dir/edit_PLL.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "PLL" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/fpga/ipcore_dir/edit_PrefetchDataRAM.tcl b/fpga/ipcore_dir/edit_PrefetchDataRAM.tcl new file mode 100644 index 0000000..f2d86d0 --- /dev/null +++ b/fpga/ipcore_dir/edit_PrefetchDataRAM.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "PrefetchDataRAM" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/fpga/ipcore_dir/edit_PrefetchTagRAM.tcl b/fpga/ipcore_dir/edit_PrefetchTagRAM.tcl new file mode 100644 index 0000000..1e49177 --- /dev/null +++ b/fpga/ipcore_dir/edit_PrefetchTagRAM.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator edit command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_edit "PrefetchTagRAM" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator edit command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator edit command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator edit cancelled." +} +exit $result diff --git a/fpga/ipcore_dir/summary.log b/fpga/ipcore_dir/summary.log new file mode 100644 index 0000000..4a8dbad --- /dev/null +++ b/fpga/ipcore_dir/summary.log @@ -0,0 +1,19 @@ + +User Configuration +------------------------------------- +Algorithm : Minimum_Area +Memory Type : Simple_Dual_Port_RAM +Port A Write Width : 32 +Port B Read Width : 32 +Memory Depth : 128 +-------------------------------------------------------------- + +Block RAM resource(s) (9K BRAMs) : 1 +Block RAM resource(s) (18K BRAMs) : 0 +-------------------------------------------------------------- +Clock A Frequency : 100 +Port A Enable Rate : 100 +Port A Write Rate : 50 +---------------------------------------------------------- +Estimated Power for IP : 2.910696 mW +---------------------------------------------------------- diff --git a/fpga/ipcore_dir/tmp/PrefetchDataRAM.lso b/fpga/ipcore_dir/tmp/PrefetchDataRAM.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/fpga/ipcore_dir/tmp/PrefetchDataRAM.lso @@ -0,0 +1 @@ +work diff --git a/fpga/ipcore_dir/tmp/PrefetchTagRAM.lso b/fpga/ipcore_dir/tmp/PrefetchTagRAM.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/fpga/ipcore_dir/tmp/PrefetchTagRAM.lso @@ -0,0 +1 @@ +work diff --git a/fpga/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs b/fpga/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs index b74367f..6e78afb 100644 --- a/fpga/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs +++ b/fpga/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ -Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/Warp-LC/fpga/ipcore_dir/CLK.v" into library work +Analyzing Verilog file "C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/PLL.v" into library work diff --git a/fpga/ipcore_dir/tmp/_xmsgs/xst.xmsgs b/fpga/ipcore_dir/tmp/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..bc13429 --- /dev/null +++ b/fpga/ipcore_dir/tmp/_xmsgs/xst.xmsgs @@ -0,0 +1,105 @@ + + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 142: Comparison between arrays of unequal length always returns FALSE. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2_xst.vhd" Line 164: Assignment to gnd_bus ignored, since the identifier is never used + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 164: Net <gnd> does not have a driver. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 165: Net <gnd_bus[4]> does not have a driver. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\dist_mem_gen_v7_2\dist_mem_gen_v7_2.vhd" Line 166: Net <vcc> does not have a driver. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchTagRAM.vhd" line 121: Output port <qspo> of the instance <U0> is unconnected or connected to loadless signal. + + +"C:\Users\Dog\Documents\GitHub\Warp-LC\fpga\ipcore_dir\tmp\_cg\_dbg\PrefetchTagRAM.vhd" line 121: Output port <qdpo> of the instance <U0> is unconnected or connected to loadless signal. + + +Input <spra> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <i_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qspo_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qspo_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qspo_srst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_srst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <gnd_bus<4:0>> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <gnd> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <vcc> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Input <spra> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <i_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qspo_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qspo_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qspo_srst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_ce> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_rst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <qdpo_srst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Signal <qspo> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +Signal <qdpo> is used but never assigned. This sourceless signal will be automatically connected to value GND. + + +HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_ram>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + + + diff --git a/fpga/ipcore_dir/tmp/customization_gui.0.701401314093.out b/fpga/ipcore_dir/tmp/customization_gui.0.701401314093.out new file mode 100644 index 0000000..c18b30d --- /dev/null +++ b/fpga/ipcore_dir/tmp/customization_gui.0.701401314093.out @@ -0,0 +1,505 @@ +SET_FLAG DEBUG FALSE +SET_FLAG MODE BATCH +SET_FLAG STANDALONE_MODE FALSE +SET_PREFERENCE devicefamily spartan6 +SET_PREFERENCE device xc6slx9 +SET_PREFERENCE speedgrade -2 +SET_PREFERENCE package ftg256 +SET_PREFERENCE verilogsim true +SET_PREFERENCE vhdlsim false +SET_PREFERENCE simulationfiles Behavioral +SET_PREFERENCE busformat BusFormatAngleBracketNotRipped +SET_PREFERENCE outputdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/ +SET_PREFERENCE workingdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/ +SET_PREFERENCE subworkingdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/ +SET_PREFERENCE transientdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/ +SET_PREFERENCE designentry Verilog +SET_PREFERENCE flowvendor Other +SET_PREFERENCE addpads false +SET_PREFERENCE projectname coregen +SET_PREFERENCE formalverification false +SET_PREFERENCE asysymbol false +SET_PREFERENCE implementationfiletype Ngc +SET_PREFERENCE foundationsym false +SET_PREFERENCE createndf false +SET_PREFERENCE removerpms false +SET_PARAMETER Component_Name PLL +SET_PARAMETER Use_Freq_Synth true +SET_PARAMETER Use_Phase_Alignment true +SET_PARAMETER Use_Min_Power false +SET_PARAMETER Use_Dyn_Phase_Shift false +SET_PARAMETER Use_Dyn_Reconfig false +SET_PARAMETER Jitter_Sel Min_O_Jitter +SET_PARAMETER Use_Spread_Spectrum false +SET_PARAMETER Use_Spread_Spectrum_1 false +SET_PARAMETER Prim_In_Freq 33.3333 +SET_PARAMETER In_Freq_Units Units_MHz +SET_PARAMETER In_Jitter_Units Units_UI +SET_PARAMETER Relative_Inclk REL_PRIMARY +SET_PARAMETER Secondary_In_Freq 100.000 +SET_PARAMETER Jitter_Options UI +SET_PARAMETER Clkin1_UI_Jitter 0.010 +SET_PARAMETER Clkin2_UI_Jitter 0.010 +SET_PARAMETER Prim_In_Jitter 0.010 +SET_PARAMETER Secondary_In_Jitter 0.010 +SET_PARAMETER Clkin1_Jitter_Ps 300.0 +SET_PARAMETER Clkin2_Jitter_Ps 100.0 +SET_PARAMETER Clkout2_Used false +SET_PARAMETER Clkout3_Used false +SET_PARAMETER Clkout4_Used false +SET_PARAMETER Clkout5_Used false +SET_PARAMETER Clkout6_Used false +SET_PARAMETER Clkout7_Used false +SET_PARAMETER Num_Out_Clks 1 +SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false +SET_PARAMETER primary_port CLKIN +SET_PARAMETER CLK_OUT1_port FSBCLK +SET_PARAMETER CLK_OUT2_port CLK_OUT2 +SET_PARAMETER CLK_OUT3_port CLK_OUT3 +SET_PARAMETER CLK_OUT4_port CLK_OUT4 +SET_PARAMETER CLK_OUT5_port CLK_OUT5 +SET_PARAMETER CLK_OUT6_port CLK_OUT6 +SET_PARAMETER CLK_OUT7_port CLK_OUT7 +SET_PARAMETER DADDR_port DADDR +SET_PARAMETER DCLK_port DCLK +SET_PARAMETER DRDY_port DRDY +SET_PARAMETER DWE_port DWE +SET_PARAMETER DIN_port DIN +SET_PARAMETER DOUT_port DOUT +SET_PARAMETER DEN_port DEN +SET_PARAMETER PSCLK_port PSCLK +SET_PARAMETER PSEN_port PSEN +SET_PARAMETER PSINCDEC_port PSINCDEC +SET_PARAMETER PSDONE_port PSDONE +SET_PARAMETER Clkout1_Requested_Out_Freq 66.667 +SET_PARAMETER Clkout1_Requested_Phase 0.000 +SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout2_Requested_Out_Freq 33.333 +SET_PARAMETER Clkout2_Requested_Phase 0.000 +SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout3_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout3_Requested_Phase 0.000 +SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout4_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout4_Requested_Phase 0.000 +SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout5_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout5_Requested_Phase 0.000 +SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout6_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout6_Requested_Phase 0.000 +SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout7_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout7_Requested_Phase 0.000 +SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0 +SET_PARAMETER Use_Max_I_Jitter false +SET_PARAMETER Use_Min_O_Jitter false +SET_PARAMETER Prim_Source Single_ended_clock_capable_pin +SET_PARAMETER Use_Inclk_Switchover false +SET_PARAMETER secondary_port CLK_IN2 +SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin +SET_PARAMETER Clkout1_Drives BUFG +SET_PARAMETER Clkout2_Drives BUFG +SET_PARAMETER Clkout3_Drives BUFG +SET_PARAMETER Clkout4_Drives BUFG +SET_PARAMETER Clkout5_Drives BUFG +SET_PARAMETER Clkout6_Drives BUFG +SET_PARAMETER Clkout7_Drives BUFG +SET_PARAMETER Feedback_Source FDBK_AUTO_OFFCHIP +SET_PARAMETER Clkfb_In_Signaling SINGLE +SET_PARAMETER CLKFB_IN_port CLKFB_IN +SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P +SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N +SET_PARAMETER CLKFB_OUT_port CLKFB_OUT +SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P +SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N +SET_PARAMETER Platform nt +SET_PARAMETER Summary_Strings empty +SET_PARAMETER Use_Locked true +SET_PARAMETER calc_done DONE +SET_PARAMETER Use_Reset false +SET_PARAMETER Use_Power_Down false +SET_PARAMETER Use_Status false +SET_PARAMETER Use_Freeze false +SET_PARAMETER Use_Clk_Valid false +SET_PARAMETER Use_Inclk_Stopped false +SET_PARAMETER Use_Clkfb_Stopped false +SET_PARAMETER RESET_port RESET +SET_PARAMETER LOCKED_port LOCKED +SET_PARAMETER Power_Down_port POWER_DOWN +SET_PARAMETER CLK_VALID_port CLK_VALID +SET_PARAMETER STATUS_port STATUS +SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL +SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED +SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED +SET_PARAMETER Override_Mmcm false +SET_PARAMETER Mmcm_Notes None +SET_PARAMETER Mmcm_Divclk_Divide 1 +SET_PARAMETER Mmcm_Bandwidth HIGH +SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000 +SET_PARAMETER Mmcm_Clkfbout_Phase 0.000 +SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkin1_Period 10.000 +SET_PARAMETER Mmcm_Clkin2_Period 10.000 +SET_PARAMETER Mmcm_Clkout4_Cascade false +SET_PARAMETER Mmcm_Clock_Hold false +SET_PARAMETER Mmcm_Compensation ZHOLD +SET_PARAMETER Mmcm_Ref_Jitter1 0.010 +SET_PARAMETER Mmcm_Ref_Jitter2 0.010 +SET_PARAMETER Mmcm_Startup_Wait false +SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000 +SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout0_Phase 0.000 +SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout1_Divide 1 +SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout1_Phase 0.000 +SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout2_Divide 1 +SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout2_Phase 0.000 +SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout3_Divide 1 +SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout3_Phase 0.000 +SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout4_Divide 1 +SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout4_Phase 0.000 +SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout5_Divide 1 +SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout5_Phase 0.000 +SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout6_Divide 1 +SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout6_Phase 0.000 +SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false +SET_PARAMETER Override_Dcm false +SET_PARAMETER Dcm_Notes None +SET_PARAMETER Dcm_Clkdv_Divide 2.0 +SET_PARAMETER Dcm_Clkfx_Divide 1 +SET_PARAMETER Dcm_Clkfx_Multiply 4 +SET_PARAMETER Dcm_Clkin_Divide_By_2 false +SET_PARAMETER Dcm_Clkin_Period 30.000 +SET_PARAMETER Dcm_Clkout_Phase_Shift NONE +SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS +SET_PARAMETER Dcm_Phase_Shift 0 +SET_PARAMETER Dcm_Clk_Feedback 2X +SET_PARAMETER Dcm_Startup_Wait false +SET_PARAMETER Dcm_Clk_Out1_Port CLK2X +SET_PARAMETER Dcm_Clk_Out2_Port CLK0 +SET_PARAMETER Dcm_Clk_Out3_Port CLKFX +SET_PARAMETER Dcm_Clk_Out4_Port CLK0 +SET_PARAMETER Dcm_Clk_Out5_Port CLK0 +SET_PARAMETER Dcm_Clk_Out6_Port CLK0 +SET_PARAMETER Override_Dcm_Clkgen false +SET_PARAMETER Dcm_Clkgen_Notes None +SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1 +SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4 +SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2 +SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000 +SET_PARAMETER Dcm_Clkgen_Startup_Wait false +SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000 +SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE +SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX +SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX +SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX +SET_PARAMETER Override_Pll false +SET_PARAMETER Pll_Notes None +SET_PARAMETER Pll_Bandwidth HIGH +SET_PARAMETER Pll_Clkfbout_Mult 28 +SET_PARAMETER Pll_Clkfbout_Phase 0.000 +SET_PARAMETER Pll_Clk_Feedback CLKFBOUT +SET_PARAMETER Pll_Divclk_Divide 1 +SET_PARAMETER Pll_Clkin_Period 30.000 +SET_PARAMETER Pll_Compensation EXTERNAL +SET_PARAMETER Pll_Ref_Jitter 0.010 +SET_PARAMETER Pll_Clkout0_Divide 14 +SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout0_Phase 0.000 +SET_PARAMETER Pll_Clkout1_Divide 12 +SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout1_Phase 0.000 +SET_PARAMETER Pll_Clkout2_Divide 4 +SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout2_Phase 0.000 +SET_PARAMETER Pll_Clkout3_Divide 1 +SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout3_Phase 0.000 +SET_PARAMETER Pll_Clkout4_Divide 1 +SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout4_Phase 0.000 +SET_PARAMETER Pll_Clkout5_Divide 1 +SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout5_Phase 0.000 +SET_PARAMETER dcm_pll_cascade NONE +SET_PARAMETER clock_mgr_type MANUAL +SET_PARAMETER primtype_sel PLL_BASE +SET_PARAMETER primitive MMCM +SET_PARAMETER SS_Mode CENTER_HIGH +SET_PARAMETER SS_Mod_Freq 250 +SET_SIM_PARAMETER c_clkout2_used 0 +SET_SIM_PARAMETER c_clkout3_used 0 +SET_SIM_PARAMETER c_clkout4_used 0 +SET_SIM_PARAMETER c_clkout5_used 0 +SET_SIM_PARAMETER c_clkout6_used 0 +SET_SIM_PARAMETER c_clkout7_used 0 +SET_SIM_PARAMETER c_use_clkout1_bar 0 +SET_SIM_PARAMETER c_use_clkout2_bar 0 +SET_SIM_PARAMETER c_use_clkout3_bar 0 +SET_SIM_PARAMETER c_use_clkout4_bar 0 +SET_SIM_PARAMETER c_component_name PLL +SET_SIM_PARAMETER c_platform nt +SET_SIM_PARAMETER c_use_freq_synth 1 +SET_SIM_PARAMETER c_use_phase_alignment 1 +SET_SIM_PARAMETER c_prim_in_jitter 0.010 +SET_SIM_PARAMETER c_secondary_in_jitter 0.010 +SET_SIM_PARAMETER c_jitter_sel Min_O_Jitter +SET_SIM_PARAMETER c_use_min_power 0 +SET_SIM_PARAMETER c_use_min_o_jitter 1 +SET_SIM_PARAMETER c_use_max_i_jitter 0 +SET_SIM_PARAMETER c_use_dyn_phase_shift 0 +SET_SIM_PARAMETER c_use_inclk_switchover 0 +SET_SIM_PARAMETER c_use_dyn_reconfig 0 +SET_SIM_PARAMETER c_use_spread_spectrum 0 +SET_SIM_PARAMETER c_use_spread_spectrum_1 0 +SET_SIM_PARAMETER c_primtype_sel PLL_BASE +SET_SIM_PARAMETER c_use_clk_valid 0 +SET_SIM_PARAMETER c_prim_in_freq 33.3333 +SET_SIM_PARAMETER c_in_freq_units Units_MHz +SET_SIM_PARAMETER c_secondary_in_freq 100.000 +SET_SIM_PARAMETER c_feedback_source FDBK_AUTO_OFFCHIP +SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin +SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin +SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE +SET_SIM_PARAMETER c_use_reset 0 +SET_SIM_PARAMETER c_use_locked 1 +SET_SIM_PARAMETER c_use_inclk_stopped 0 +SET_SIM_PARAMETER c_use_clkfb_stopped 0 +SET_SIM_PARAMETER c_use_power_down 0 +SET_SIM_PARAMETER c_use_status 0 +SET_SIM_PARAMETER c_use_freeze 0 +SET_SIM_PARAMETER c_num_out_clks 1 +SET_SIM_PARAMETER c_clkout1_drives BUFG +SET_SIM_PARAMETER c_clkout2_drives BUFG +SET_SIM_PARAMETER c_clkout3_drives BUFG +SET_SIM_PARAMETER c_clkout4_drives BUFG +SET_SIM_PARAMETER c_clkout5_drives BUFG +SET_SIM_PARAMETER c_clkout6_drives BUFG +SET_SIM_PARAMETER c_clkout7_drives BUFG +SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)" +SET_SIM_PARAMETER c_inclk_sum_row1 __primary_________33.3333____________0.010 +SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock +SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase" +SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______252.559____182.342 +SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output +SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output +SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output +SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output +SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output +SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output +SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667 +SET_SIM_PARAMETER c_clkout2_requested_out_freq 33.333 +SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout1_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout2_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout3_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout4_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout5_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout6_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout7_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout1_out_freq 66.667 +SET_SIM_PARAMETER c_clkout2_out_freq N/A +SET_SIM_PARAMETER c_clkout3_out_freq N/A +SET_SIM_PARAMETER c_clkout4_out_freq N/A +SET_SIM_PARAMETER c_clkout5_out_freq N/A +SET_SIM_PARAMETER c_clkout6_out_freq N/A +SET_SIM_PARAMETER c_clkout7_out_freq N/A +SET_SIM_PARAMETER c_clkout1_phase 0.000 +SET_SIM_PARAMETER c_clkout2_phase N/A +SET_SIM_PARAMETER c_clkout3_phase N/A +SET_SIM_PARAMETER c_clkout4_phase N/A +SET_SIM_PARAMETER c_clkout5_phase N/A +SET_SIM_PARAMETER c_clkout6_phase N/A +SET_SIM_PARAMETER c_clkout7_phase N/A +SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout2_duty_cycle N/A +SET_SIM_PARAMETER c_clkout3_duty_cycle N/A +SET_SIM_PARAMETER c_clkout4_duty_cycle N/A +SET_SIM_PARAMETER c_clkout5_duty_cycle N/A +SET_SIM_PARAMETER c_clkout6_duty_cycle N/A +SET_SIM_PARAMETER c_clkout7_duty_cycle N/A +SET_SIM_PARAMETER c_mmcm_notes None +SET_SIM_PARAMETER c_mmcm_bandwidth HIGH +SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000 +SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000 +SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000 +SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE +SET_SIM_PARAMETER c_mmcm_clock_hold FALSE +SET_SIM_PARAMETER c_mmcm_compensation ZHOLD +SET_SIM_PARAMETER c_mmcm_divclk_divide 1 +SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010 +SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010 +SET_SIM_PARAMETER c_mmcm_startup_wait FALSE +SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000 +SET_SIM_PARAMETER c_mmcm_clkout1_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout2_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout3_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout4_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout5_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout6_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE +SET_SIM_PARAMETER c_pll_notes None +SET_SIM_PARAMETER c_pll_bandwidth HIGH +SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT +SET_SIM_PARAMETER c_pll_clkfbout_mult 28 +SET_SIM_PARAMETER c_pll_clkin_period 30.000 +SET_SIM_PARAMETER c_pll_compensation EXTERNAL +SET_SIM_PARAMETER c_pll_divclk_divide 1 +SET_SIM_PARAMETER c_pll_ref_jitter 0.010 +SET_SIM_PARAMETER c_pll_clkout0_divide 14 +SET_SIM_PARAMETER c_pll_clkout1_divide 12 +SET_SIM_PARAMETER c_pll_clkout2_divide 4 +SET_SIM_PARAMETER c_pll_clkout3_divide 1 +SET_SIM_PARAMETER c_pll_clkout4_divide 1 +SET_SIM_PARAMETER c_pll_clkout5_divide 1 +SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout0_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout1_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout2_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout3_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout4_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout5_phase 0.000 +SET_SIM_PARAMETER c_dcm_notes None +SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000 +SET_SIM_PARAMETER c_dcm_clkfx_divide 1 +SET_SIM_PARAMETER c_dcm_clkfx_multiply 4 +SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE +SET_SIM_PARAMETER c_dcm_clkin_period 30.0 +SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE +SET_SIM_PARAMETER c_dcm_clk_feedback 2X +SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1 +SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS +SET_SIM_PARAMETER c_dcm_phase_shift 0 +SET_SIM_PARAMETER c_dcm_startup_wait FALSE +SET_SIM_PARAMETER c_dcm_clk_out1_port CLK2X +SET_SIM_PARAMETER c_dcm_clk_out2_port NONE +SET_SIM_PARAMETER c_dcm_clk_out3_port NONE +SET_SIM_PARAMETER c_dcm_clk_out4_port NONE +SET_SIM_PARAMETER c_dcm_clk_out5_port NONE +SET_SIM_PARAMETER c_dcm_clk_out6_port NONE +SET_SIM_PARAMETER c_dcm_clkgen_notes None +SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2 +SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1 +SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4 +SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED +SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED +SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0 +SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000 +SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE +SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE +SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX +SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE +SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE +SET_SIM_PARAMETER c_clock_mgr_type MANUAL +SET_SIM_PARAMETER c_override_mmcm 0 +SET_SIM_PARAMETER c_override_pll 0 +SET_SIM_PARAMETER c_override_dcm 0 +SET_SIM_PARAMETER c_override_dcm_clkgen 0 +SET_SIM_PARAMETER c_dcm_pll_cascade NONE +SET_SIM_PARAMETER c_primary_port CLKIN +SET_SIM_PARAMETER c_secondary_port CLK_IN2 +SET_SIM_PARAMETER c_clk_out1_port FSBCLK +SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2 +SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3 +SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4 +SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5 +SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6 +SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7 +SET_SIM_PARAMETER c_reset_port RESET +SET_SIM_PARAMETER c_locked_port LOCKED +SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN +SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P +SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N +SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT +SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P +SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N +SET_SIM_PARAMETER c_power_down_port POWER_DOWN +SET_SIM_PARAMETER c_daddr_port DADDR +SET_SIM_PARAMETER c_dclk_port DCLK +SET_SIM_PARAMETER c_drdy_port DRDY +SET_SIM_PARAMETER c_dwe_port DWE +SET_SIM_PARAMETER c_din_port DIN +SET_SIM_PARAMETER c_dout_port DOUT +SET_SIM_PARAMETER c_den_port DEN +SET_SIM_PARAMETER c_psclk_port PSCLK +SET_SIM_PARAMETER c_psen_port PSEN +SET_SIM_PARAMETER c_psincdec_port PSINCDEC +SET_SIM_PARAMETER c_psdone_port PSDONE +SET_SIM_PARAMETER c_clk_valid_port CLK_VALID +SET_SIM_PARAMETER c_status_port STATUS +SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL +SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED +SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED +SET_SIM_PARAMETER c_clkin1_jitter_ps 300.0 +SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0 +SET_SIM_PARAMETER c_primitive MMCM +SET_SIM_PARAMETER c_ss_mode CENTER_HIGH +SET_SIM_PARAMETER c_ss_mod_period 4000 +SET_CORE_NAME Clocking Wizard +SET_CORE_VERSION 3.6 +SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6 +SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6 +SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6 +SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl +SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT diff --git a/fpga/ipcore_dir/tmp/customization_gui.0.768202455141.out b/fpga/ipcore_dir/tmp/customization_gui.0.768202455141.out new file mode 100644 index 0000000..713f309 --- /dev/null +++ b/fpga/ipcore_dir/tmp/customization_gui.0.768202455141.out @@ -0,0 +1,505 @@ +SET_FLAG DEBUG FALSE +SET_FLAG MODE BATCH +SET_FLAG STANDALONE_MODE FALSE +SET_PREFERENCE devicefamily spartan6 +SET_PREFERENCE device xc6slx9 +SET_PREFERENCE speedgrade -2 +SET_PREFERENCE package ftg256 +SET_PREFERENCE verilogsim true +SET_PREFERENCE vhdlsim false +SET_PREFERENCE simulationfiles Behavioral +SET_PREFERENCE busformat BusFormatAngleBracketNotRipped +SET_PREFERENCE outputdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/ +SET_PREFERENCE workingdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/ +SET_PREFERENCE subworkingdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/ +SET_PREFERENCE transientdirectory C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/_dbg/ +SET_PREFERENCE designentry Verilog +SET_PREFERENCE flowvendor Other +SET_PREFERENCE addpads false +SET_PREFERENCE projectname coregen +SET_PREFERENCE formalverification false +SET_PREFERENCE asysymbol false +SET_PREFERENCE implementationfiletype Ngc +SET_PREFERENCE foundationsym false +SET_PREFERENCE createndf false +SET_PREFERENCE removerpms false +SET_PARAMETER Component_Name PLL +SET_PARAMETER Use_Freq_Synth true +SET_PARAMETER Use_Phase_Alignment true +SET_PARAMETER Use_Min_Power false +SET_PARAMETER Use_Dyn_Phase_Shift false +SET_PARAMETER Use_Dyn_Reconfig false +SET_PARAMETER Jitter_Sel Min_O_Jitter +SET_PARAMETER Use_Spread_Spectrum false +SET_PARAMETER Use_Spread_Spectrum_1 false +SET_PARAMETER Prim_In_Freq 33.3333 +SET_PARAMETER In_Freq_Units Units_MHz +SET_PARAMETER In_Jitter_Units Units_UI +SET_PARAMETER Relative_Inclk REL_PRIMARY +SET_PARAMETER Secondary_In_Freq 100.000 +SET_PARAMETER Jitter_Options UI +SET_PARAMETER Clkin1_UI_Jitter 0.010 +SET_PARAMETER Clkin2_UI_Jitter 0.010 +SET_PARAMETER Prim_In_Jitter 0.010 +SET_PARAMETER Secondary_In_Jitter 0.010 +SET_PARAMETER Clkin1_Jitter_Ps 300.0 +SET_PARAMETER Clkin2_Jitter_Ps 100.0 +SET_PARAMETER Clkout2_Used false +SET_PARAMETER Clkout3_Used false +SET_PARAMETER Clkout4_Used false +SET_PARAMETER Clkout5_Used false +SET_PARAMETER Clkout6_Used false +SET_PARAMETER Clkout7_Used false +SET_PARAMETER Num_Out_Clks 1 +SET_PARAMETER Clk_Out1_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out2_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out3_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out4_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out5_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out6_Use_Fine_Ps_GUI false +SET_PARAMETER Clk_Out7_Use_Fine_Ps_GUI false +SET_PARAMETER primary_port CLKIN +SET_PARAMETER CLK_OUT1_port FSBCLK +SET_PARAMETER CLK_OUT2_port CLK_OUT2 +SET_PARAMETER CLK_OUT3_port CLK_OUT3 +SET_PARAMETER CLK_OUT4_port CLK_OUT4 +SET_PARAMETER CLK_OUT5_port CLK_OUT5 +SET_PARAMETER CLK_OUT6_port CLK_OUT6 +SET_PARAMETER CLK_OUT7_port CLK_OUT7 +SET_PARAMETER DADDR_port DADDR +SET_PARAMETER DCLK_port DCLK +SET_PARAMETER DRDY_port DRDY +SET_PARAMETER DWE_port DWE +SET_PARAMETER DIN_port DIN +SET_PARAMETER DOUT_port DOUT +SET_PARAMETER DEN_port DEN +SET_PARAMETER PSCLK_port PSCLK +SET_PARAMETER PSEN_port PSEN +SET_PARAMETER PSINCDEC_port PSINCDEC +SET_PARAMETER PSDONE_port PSDONE +SET_PARAMETER Clkout1_Requested_Out_Freq 66.667 +SET_PARAMETER Clkout1_Requested_Phase 0.000 +SET_PARAMETER Clkout1_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout2_Requested_Out_Freq 33.333 +SET_PARAMETER Clkout2_Requested_Phase 0.000 +SET_PARAMETER Clkout2_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout3_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout3_Requested_Phase 0.000 +SET_PARAMETER Clkout3_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout4_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout4_Requested_Phase 0.000 +SET_PARAMETER Clkout4_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout5_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout5_Requested_Phase 0.000 +SET_PARAMETER Clkout5_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout6_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout6_Requested_Phase 0.000 +SET_PARAMETER Clkout6_Requested_Duty_Cycle 50.0 +SET_PARAMETER Clkout7_Requested_Out_Freq 100.000 +SET_PARAMETER Clkout7_Requested_Phase 0.000 +SET_PARAMETER Clkout7_Requested_Duty_Cycle 50.0 +SET_PARAMETER Use_Max_I_Jitter false +SET_PARAMETER Use_Min_O_Jitter false +SET_PARAMETER Prim_Source Single_ended_clock_capable_pin +SET_PARAMETER Use_Inclk_Switchover false +SET_PARAMETER secondary_port CLK_IN2 +SET_PARAMETER Secondary_Source Single_ended_clock_capable_pin +SET_PARAMETER Clkout1_Drives BUFG +SET_PARAMETER Clkout2_Drives BUFG +SET_PARAMETER Clkout3_Drives BUFG +SET_PARAMETER Clkout4_Drives BUFG +SET_PARAMETER Clkout5_Drives BUFG +SET_PARAMETER Clkout6_Drives BUFG +SET_PARAMETER Clkout7_Drives BUFG +SET_PARAMETER Feedback_Source FDBK_AUTO +SET_PARAMETER Clkfb_In_Signaling SINGLE +SET_PARAMETER CLKFB_IN_port CLKFB_IN +SET_PARAMETER CLKFB_IN_P_port CLKFB_IN_P +SET_PARAMETER CLKFB_IN_N_port CLKFB_IN_N +SET_PARAMETER CLKFB_OUT_port CLKFB_OUT +SET_PARAMETER CLKFB_OUT_P_port CLKFB_OUT_P +SET_PARAMETER CLKFB_OUT_N_port CLKFB_OUT_N +SET_PARAMETER Platform nt +SET_PARAMETER Summary_Strings empty +SET_PARAMETER Use_Locked true +SET_PARAMETER calc_done DONE +SET_PARAMETER Use_Reset false +SET_PARAMETER Use_Power_Down false +SET_PARAMETER Use_Status false +SET_PARAMETER Use_Freeze false +SET_PARAMETER Use_Clk_Valid false +SET_PARAMETER Use_Inclk_Stopped false +SET_PARAMETER Use_Clkfb_Stopped false +SET_PARAMETER RESET_port RESET +SET_PARAMETER LOCKED_port LOCKED +SET_PARAMETER Power_Down_port POWER_DOWN +SET_PARAMETER CLK_VALID_port CLK_VALID +SET_PARAMETER STATUS_port STATUS +SET_PARAMETER CLK_IN_SEL_port CLK_IN_SEL +SET_PARAMETER INPUT_CLK_STOPPED_port INPUT_CLK_STOPPED +SET_PARAMETER CLKFB_STOPPED_port CLKFB_STOPPED +SET_PARAMETER Override_Mmcm false +SET_PARAMETER Mmcm_Notes None +SET_PARAMETER Mmcm_Divclk_Divide 1 +SET_PARAMETER Mmcm_Bandwidth HIGH +SET_PARAMETER Mmcm_Clkfbout_Mult_F 4.000 +SET_PARAMETER Mmcm_Clkfbout_Phase 0.000 +SET_PARAMETER Mmcm_Clkfbout_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkin1_Period 10.000 +SET_PARAMETER Mmcm_Clkin2_Period 10.000 +SET_PARAMETER Mmcm_Clkout4_Cascade false +SET_PARAMETER Mmcm_Clock_Hold false +SET_PARAMETER Mmcm_Compensation ZHOLD +SET_PARAMETER Mmcm_Ref_Jitter1 0.010 +SET_PARAMETER Mmcm_Ref_Jitter2 0.010 +SET_PARAMETER Mmcm_Startup_Wait false +SET_PARAMETER Mmcm_Clkout0_Divide_F 4.000 +SET_PARAMETER Mmcm_Clkout0_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout0_Phase 0.000 +SET_PARAMETER Mmcm_Clkout0_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout1_Divide 1 +SET_PARAMETER Mmcm_Clkout1_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout1_Phase 0.000 +SET_PARAMETER Mmcm_Clkout1_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout2_Divide 1 +SET_PARAMETER Mmcm_Clkout2_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout2_Phase 0.000 +SET_PARAMETER Mmcm_Clkout2_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout3_Divide 1 +SET_PARAMETER Mmcm_Clkout3_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout3_Phase 0.000 +SET_PARAMETER Mmcm_Clkout3_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout4_Divide 1 +SET_PARAMETER Mmcm_Clkout4_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout4_Phase 0.000 +SET_PARAMETER Mmcm_Clkout4_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout5_Divide 1 +SET_PARAMETER Mmcm_Clkout5_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout5_Phase 0.000 +SET_PARAMETER Mmcm_Clkout5_Use_Fine_Ps false +SET_PARAMETER Mmcm_Clkout6_Divide 1 +SET_PARAMETER Mmcm_Clkout6_Duty_Cycle 0.500 +SET_PARAMETER Mmcm_Clkout6_Phase 0.000 +SET_PARAMETER Mmcm_Clkout6_Use_Fine_Ps false +SET_PARAMETER Override_Dcm false +SET_PARAMETER Dcm_Notes None +SET_PARAMETER Dcm_Clkdv_Divide 2.0 +SET_PARAMETER Dcm_Clkfx_Divide 1 +SET_PARAMETER Dcm_Clkfx_Multiply 4 +SET_PARAMETER Dcm_Clkin_Divide_By_2 false +SET_PARAMETER Dcm_Clkin_Period 30.000 +SET_PARAMETER Dcm_Clkout_Phase_Shift NONE +SET_PARAMETER Dcm_Deskew_Adjust SYSTEM_SYNCHRONOUS +SET_PARAMETER Dcm_Phase_Shift 0 +SET_PARAMETER Dcm_Clk_Feedback 2X +SET_PARAMETER Dcm_Startup_Wait false +SET_PARAMETER Dcm_Clk_Out1_Port CLK2X +SET_PARAMETER Dcm_Clk_Out2_Port CLK0 +SET_PARAMETER Dcm_Clk_Out3_Port CLKFX +SET_PARAMETER Dcm_Clk_Out4_Port CLK0 +SET_PARAMETER Dcm_Clk_Out5_Port CLK0 +SET_PARAMETER Dcm_Clk_Out6_Port CLK0 +SET_PARAMETER Override_Dcm_Clkgen false +SET_PARAMETER Dcm_Clkgen_Notes None +SET_PARAMETER Dcm_Clkgen_Clkfx_Divide 1 +SET_PARAMETER Dcm_Clkgen_Clkfx_Multiply 4 +SET_PARAMETER Dcm_Clkgen_Clkfxdv_Divide 2 +SET_PARAMETER Dcm_Clkgen_Clkfx_Md_Max 0.000 +SET_PARAMETER Dcm_Clkgen_Startup_Wait false +SET_PARAMETER Dcm_Clkgen_Clkin_Period 10.000 +SET_PARAMETER Dcm_Clkgen_Spread_Spectrum NONE +SET_PARAMETER Dcm_Clkgen_Clk_Out1_Port CLKFX +SET_PARAMETER Dcm_Clkgen_Clk_Out2_Port CLKFX +SET_PARAMETER Dcm_Clkgen_Clk_Out3_Port CLKFX +SET_PARAMETER Override_Pll false +SET_PARAMETER Pll_Notes None +SET_PARAMETER Pll_Bandwidth HIGH +SET_PARAMETER Pll_Clkfbout_Mult 28 +SET_PARAMETER Pll_Clkfbout_Phase 0.000 +SET_PARAMETER Pll_Clk_Feedback CLKFBOUT +SET_PARAMETER Pll_Divclk_Divide 1 +SET_PARAMETER Pll_Clkin_Period 30.000 +SET_PARAMETER Pll_Compensation SYSTEM_SYNCHRONOUS +SET_PARAMETER Pll_Ref_Jitter 0.010 +SET_PARAMETER Pll_Clkout0_Divide 14 +SET_PARAMETER Pll_Clkout0_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout0_Phase 0.000 +SET_PARAMETER Pll_Clkout1_Divide 12 +SET_PARAMETER Pll_Clkout1_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout1_Phase 0.000 +SET_PARAMETER Pll_Clkout2_Divide 4 +SET_PARAMETER Pll_Clkout2_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout2_Phase 0.000 +SET_PARAMETER Pll_Clkout3_Divide 1 +SET_PARAMETER Pll_Clkout3_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout3_Phase 0.000 +SET_PARAMETER Pll_Clkout4_Divide 1 +SET_PARAMETER Pll_Clkout4_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout4_Phase 0.000 +SET_PARAMETER Pll_Clkout5_Divide 1 +SET_PARAMETER Pll_Clkout5_Duty_Cycle 0.500 +SET_PARAMETER Pll_Clkout5_Phase 0.000 +SET_PARAMETER dcm_pll_cascade NONE +SET_PARAMETER clock_mgr_type MANUAL +SET_PARAMETER primtype_sel PLL_BASE +SET_PARAMETER primitive MMCM +SET_PARAMETER SS_Mode CENTER_HIGH +SET_PARAMETER SS_Mod_Freq 250 +SET_SIM_PARAMETER c_clkout2_used 0 +SET_SIM_PARAMETER c_clkout3_used 0 +SET_SIM_PARAMETER c_clkout4_used 0 +SET_SIM_PARAMETER c_clkout5_used 0 +SET_SIM_PARAMETER c_clkout6_used 0 +SET_SIM_PARAMETER c_clkout7_used 0 +SET_SIM_PARAMETER c_use_clkout1_bar 0 +SET_SIM_PARAMETER c_use_clkout2_bar 0 +SET_SIM_PARAMETER c_use_clkout3_bar 0 +SET_SIM_PARAMETER c_use_clkout4_bar 0 +SET_SIM_PARAMETER c_component_name PLL +SET_SIM_PARAMETER c_platform nt +SET_SIM_PARAMETER c_use_freq_synth 1 +SET_SIM_PARAMETER c_use_phase_alignment 1 +SET_SIM_PARAMETER c_prim_in_jitter 0.010 +SET_SIM_PARAMETER c_secondary_in_jitter 0.010 +SET_SIM_PARAMETER c_jitter_sel Min_O_Jitter +SET_SIM_PARAMETER c_use_min_power 0 +SET_SIM_PARAMETER c_use_min_o_jitter 1 +SET_SIM_PARAMETER c_use_max_i_jitter 0 +SET_SIM_PARAMETER c_use_dyn_phase_shift 0 +SET_SIM_PARAMETER c_use_inclk_switchover 0 +SET_SIM_PARAMETER c_use_dyn_reconfig 0 +SET_SIM_PARAMETER c_use_spread_spectrum 0 +SET_SIM_PARAMETER c_use_spread_spectrum_1 0 +SET_SIM_PARAMETER c_primtype_sel PLL_BASE +SET_SIM_PARAMETER c_use_clk_valid 0 +SET_SIM_PARAMETER c_prim_in_freq 33.3333 +SET_SIM_PARAMETER c_in_freq_units Units_MHz +SET_SIM_PARAMETER c_secondary_in_freq 100.000 +SET_SIM_PARAMETER c_feedback_source FDBK_AUTO +SET_SIM_PARAMETER c_prim_source Single_ended_clock_capable_pin +SET_SIM_PARAMETER c_secondary_source Single_ended_clock_capable_pin +SET_SIM_PARAMETER c_clkfb_in_signaling SINGLE +SET_SIM_PARAMETER c_use_reset 0 +SET_SIM_PARAMETER c_use_locked 1 +SET_SIM_PARAMETER c_use_inclk_stopped 0 +SET_SIM_PARAMETER c_use_clkfb_stopped 0 +SET_SIM_PARAMETER c_use_power_down 0 +SET_SIM_PARAMETER c_use_status 0 +SET_SIM_PARAMETER c_use_freeze 0 +SET_SIM_PARAMETER c_num_out_clks 1 +SET_SIM_PARAMETER c_clkout1_drives BUFG +SET_SIM_PARAMETER c_clkout2_drives BUFG +SET_SIM_PARAMETER c_clkout3_drives BUFG +SET_SIM_PARAMETER c_clkout4_drives BUFG +SET_SIM_PARAMETER c_clkout5_drives BUFG +SET_SIM_PARAMETER c_clkout6_drives BUFG +SET_SIM_PARAMETER c_clkout7_drives BUFG +SET_SIM_PARAMETER c_inclk_sum_row0 "Input Clock Freq (MHz) Input Jitter (UI)" +SET_SIM_PARAMETER c_inclk_sum_row1 __primary_________33.3333____________0.010 +SET_SIM_PARAMETER c_inclk_sum_row2 no_secondary_input_clock +SET_SIM_PARAMETER c_outclk_sum_row0a "Output Output Phase Duty Pk-to-Pk Phase" +SET_SIM_PARAMETER c_outclk_sum_row0b "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +SET_SIM_PARAMETER c_outclk_sum_row1 CLK_OUT1____66.667______0.000______50.0______252.559____182.342 +SET_SIM_PARAMETER c_outclk_sum_row2 no_CLK_OUT2_output +SET_SIM_PARAMETER c_outclk_sum_row3 no_CLK_OUT3_output +SET_SIM_PARAMETER c_outclk_sum_row4 no_CLK_OUT4_output +SET_SIM_PARAMETER c_outclk_sum_row5 no_CLK_OUT5_output +SET_SIM_PARAMETER c_outclk_sum_row6 no_CLK_OUT6_output +SET_SIM_PARAMETER c_outclk_sum_row7 no_CLK_OUT7_output +SET_SIM_PARAMETER c_clkout1_requested_out_freq 66.667 +SET_SIM_PARAMETER c_clkout2_requested_out_freq 33.333 +SET_SIM_PARAMETER c_clkout3_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout4_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout5_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout6_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout7_requested_out_freq 100.000 +SET_SIM_PARAMETER c_clkout1_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout2_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout3_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout4_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout5_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout6_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout7_requested_phase 0.000 +SET_SIM_PARAMETER c_clkout1_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout2_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout3_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout4_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout5_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout6_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout7_requested_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout1_out_freq 66.667 +SET_SIM_PARAMETER c_clkout2_out_freq N/A +SET_SIM_PARAMETER c_clkout3_out_freq N/A +SET_SIM_PARAMETER c_clkout4_out_freq N/A +SET_SIM_PARAMETER c_clkout5_out_freq N/A +SET_SIM_PARAMETER c_clkout6_out_freq N/A +SET_SIM_PARAMETER c_clkout7_out_freq N/A +SET_SIM_PARAMETER c_clkout1_phase 0.000 +SET_SIM_PARAMETER c_clkout2_phase N/A +SET_SIM_PARAMETER c_clkout3_phase N/A +SET_SIM_PARAMETER c_clkout4_phase N/A +SET_SIM_PARAMETER c_clkout5_phase N/A +SET_SIM_PARAMETER c_clkout6_phase N/A +SET_SIM_PARAMETER c_clkout7_phase N/A +SET_SIM_PARAMETER c_clkout1_duty_cycle 50.0 +SET_SIM_PARAMETER c_clkout2_duty_cycle N/A +SET_SIM_PARAMETER c_clkout3_duty_cycle N/A +SET_SIM_PARAMETER c_clkout4_duty_cycle N/A +SET_SIM_PARAMETER c_clkout5_duty_cycle N/A +SET_SIM_PARAMETER c_clkout6_duty_cycle N/A +SET_SIM_PARAMETER c_clkout7_duty_cycle N/A +SET_SIM_PARAMETER c_mmcm_notes None +SET_SIM_PARAMETER c_mmcm_bandwidth HIGH +SET_SIM_PARAMETER c_mmcm_clkfbout_mult_f 4.000 +SET_SIM_PARAMETER c_mmcm_clkin1_period 10.000 +SET_SIM_PARAMETER c_mmcm_clkin2_period 10.000 +SET_SIM_PARAMETER c_mmcm_clkout4_cascade FALSE +SET_SIM_PARAMETER c_mmcm_clock_hold FALSE +SET_SIM_PARAMETER c_mmcm_compensation ZHOLD +SET_SIM_PARAMETER c_mmcm_divclk_divide 1 +SET_SIM_PARAMETER c_mmcm_ref_jitter1 0.010 +SET_SIM_PARAMETER c_mmcm_ref_jitter2 0.010 +SET_SIM_PARAMETER c_mmcm_startup_wait FALSE +SET_SIM_PARAMETER c_mmcm_clkout0_divide_f 4.000 +SET_SIM_PARAMETER c_mmcm_clkout1_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout2_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout3_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout4_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout5_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout6_divide 1 +SET_SIM_PARAMETER c_mmcm_clkout0_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout1_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout2_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout3_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout4_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout5_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkout6_duty_cycle 0.500 +SET_SIM_PARAMETER c_mmcm_clkfbout_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout0_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout1_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout2_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout3_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout4_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout5_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkout6_phase 0.000 +SET_SIM_PARAMETER c_mmcm_clkfbout_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout0_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout1_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout2_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout3_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout4_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout5_use_fine_ps FALSE +SET_SIM_PARAMETER c_mmcm_clkout6_use_fine_ps FALSE +SET_SIM_PARAMETER c_pll_notes None +SET_SIM_PARAMETER c_pll_bandwidth HIGH +SET_SIM_PARAMETER c_pll_clk_feedback CLKFBOUT +SET_SIM_PARAMETER c_pll_clkfbout_mult 28 +SET_SIM_PARAMETER c_pll_clkin_period 30.000 +SET_SIM_PARAMETER c_pll_compensation SYSTEM_SYNCHRONOUS +SET_SIM_PARAMETER c_pll_divclk_divide 1 +SET_SIM_PARAMETER c_pll_ref_jitter 0.010 +SET_SIM_PARAMETER c_pll_clkout0_divide 14 +SET_SIM_PARAMETER c_pll_clkout1_divide 12 +SET_SIM_PARAMETER c_pll_clkout2_divide 4 +SET_SIM_PARAMETER c_pll_clkout3_divide 1 +SET_SIM_PARAMETER c_pll_clkout4_divide 1 +SET_SIM_PARAMETER c_pll_clkout5_divide 1 +SET_SIM_PARAMETER c_pll_clkout0_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout1_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout2_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout3_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout4_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkout5_duty_cycle 0.500 +SET_SIM_PARAMETER c_pll_clkfbout_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout0_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout1_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout2_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout3_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout4_phase 0.000 +SET_SIM_PARAMETER c_pll_clkout5_phase 0.000 +SET_SIM_PARAMETER c_dcm_notes None +SET_SIM_PARAMETER c_dcm_clkdv_divide 2.000 +SET_SIM_PARAMETER c_dcm_clkfx_divide 1 +SET_SIM_PARAMETER c_dcm_clkfx_multiply 4 +SET_SIM_PARAMETER c_dcm_clkin_divide_by_2 FALSE +SET_SIM_PARAMETER c_dcm_clkin_period 30.0 +SET_SIM_PARAMETER c_dcm_clkout_phase_shift NONE +SET_SIM_PARAMETER c_dcm_clk_feedback 2X +SET_SIM_PARAMETER c_dcm_clk_feedback_port CLKOUT1 +SET_SIM_PARAMETER c_dcm_deskew_adjust SYSTEM_SYNCHRONOUS +SET_SIM_PARAMETER c_dcm_phase_shift 0 +SET_SIM_PARAMETER c_dcm_startup_wait FALSE +SET_SIM_PARAMETER c_dcm_clk_out1_port CLK2X +SET_SIM_PARAMETER c_dcm_clk_out2_port NONE +SET_SIM_PARAMETER c_dcm_clk_out3_port NONE +SET_SIM_PARAMETER c_dcm_clk_out4_port NONE +SET_SIM_PARAMETER c_dcm_clk_out5_port NONE +SET_SIM_PARAMETER c_dcm_clk_out6_port NONE +SET_SIM_PARAMETER c_dcm_clkgen_notes None +SET_SIM_PARAMETER c_dcm_clkgen_clkfxdv_divide 2 +SET_SIM_PARAMETER c_dcm_clkgen_clkfx_divide 1 +SET_SIM_PARAMETER c_dcm_clkgen_clkfx_multiply 4 +SET_SIM_PARAMETER c_dcm_clkgen_dfs_bandwidth OPTIMIZED +SET_SIM_PARAMETER c_dcm_clkgen_prog_md_bandwidth OPTIMIZED +SET_SIM_PARAMETER c_dcm_clkgen_clkin_period 30.0 +SET_SIM_PARAMETER c_dcm_clkgen_clkfx_md_max 0.000 +SET_SIM_PARAMETER c_dcm_clkgen_spread_spectrum NONE +SET_SIM_PARAMETER c_dcm_clkgen_startup_wait FALSE +SET_SIM_PARAMETER c_dcm_clkgen_clk_out1_port CLKFX +SET_SIM_PARAMETER c_dcm_clkgen_clk_out2_port NONE +SET_SIM_PARAMETER c_dcm_clkgen_clk_out3_port NONE +SET_SIM_PARAMETER c_clock_mgr_type MANUAL +SET_SIM_PARAMETER c_override_mmcm 0 +SET_SIM_PARAMETER c_override_pll 0 +SET_SIM_PARAMETER c_override_dcm 0 +SET_SIM_PARAMETER c_override_dcm_clkgen 0 +SET_SIM_PARAMETER c_dcm_pll_cascade NONE +SET_SIM_PARAMETER c_primary_port CLKIN +SET_SIM_PARAMETER c_secondary_port CLK_IN2 +SET_SIM_PARAMETER c_clk_out1_port FSBCLK +SET_SIM_PARAMETER c_clk_out2_port CLK_OUT2 +SET_SIM_PARAMETER c_clk_out3_port CLK_OUT3 +SET_SIM_PARAMETER c_clk_out4_port CLK_OUT4 +SET_SIM_PARAMETER c_clk_out5_port CLK_OUT5 +SET_SIM_PARAMETER c_clk_out6_port CLK_OUT6 +SET_SIM_PARAMETER c_clk_out7_port CLK_OUT7 +SET_SIM_PARAMETER c_reset_port RESET +SET_SIM_PARAMETER c_locked_port LOCKED +SET_SIM_PARAMETER c_clkfb_in_port CLKFB_IN +SET_SIM_PARAMETER c_clkfb_in_p_port CLKFB_IN_P +SET_SIM_PARAMETER c_clkfb_in_n_port CLKFB_IN_N +SET_SIM_PARAMETER c_clkfb_out_port CLKFB_OUT +SET_SIM_PARAMETER c_clkfb_out_p_port CLKFB_OUT_P +SET_SIM_PARAMETER c_clkfb_out_n_port CLKFB_OUT_N +SET_SIM_PARAMETER c_power_down_port POWER_DOWN +SET_SIM_PARAMETER c_daddr_port DADDR +SET_SIM_PARAMETER c_dclk_port DCLK +SET_SIM_PARAMETER c_drdy_port DRDY +SET_SIM_PARAMETER c_dwe_port DWE +SET_SIM_PARAMETER c_din_port DIN +SET_SIM_PARAMETER c_dout_port DOUT +SET_SIM_PARAMETER c_den_port DEN +SET_SIM_PARAMETER c_psclk_port PSCLK +SET_SIM_PARAMETER c_psen_port PSEN +SET_SIM_PARAMETER c_psincdec_port PSINCDEC +SET_SIM_PARAMETER c_psdone_port PSDONE +SET_SIM_PARAMETER c_clk_valid_port CLK_VALID +SET_SIM_PARAMETER c_status_port STATUS +SET_SIM_PARAMETER c_clk_in_sel_port CLK_IN_SEL +SET_SIM_PARAMETER c_input_clk_stopped_port INPUT_CLK_STOPPED +SET_SIM_PARAMETER c_clkfb_stopped_port CLKFB_STOPPED +SET_SIM_PARAMETER c_clkin1_jitter_ps 300.0 +SET_SIM_PARAMETER c_clkin2_jitter_ps 100.0 +SET_SIM_PARAMETER c_primitive MMCM +SET_SIM_PARAMETER c_ss_mode CENTER_HIGH +SET_SIM_PARAMETER c_ss_mod_period 4000 +SET_CORE_NAME Clocking Wizard +SET_CORE_VERSION 3.6 +SET_CORE_VLNV xilinx.com:ip:clk_wiz:3.6 +SET_CORE_CLASS com.xilinx.ip.clk_wiz_v3_6.clk_wiz_v3_6 +SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6 +SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/clk_wiz_v3_6/gui/clk_wiz_v3_6.tcl +SET_CORE_DATASHEET C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\clk_wiz_v3_6\doc\pg065_clk_wiz.pdf +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT +ADD_CORE_DOCUMENT diff --git a/fpga/ipcore_dir/update_PrefetchDataRAM.tcl b/fpga/ipcore_dir/update_PrefetchDataRAM.tcl new file mode 100644 index 0000000..f7781b3 --- /dev/null +++ b/fpga/ipcore_dir/update_PrefetchDataRAM.tcl @@ -0,0 +1,37 @@ +## +## Core Generator Run Script, generator for Project Navigator update command +## + +proc findRtfPath { relativePath } { + set xilenv "" + if { [info exists ::env(XILINX) ] } { + if { [info exists ::env(MYXILINX)] } { + set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ] + } else { + set xilenv $::env(XILINX) + } + } + foreach path [ split $xilenv $::xilinx::path_sep ] { + set fullPath [ file join $path $relativePath ] + if { [ file exists $fullPath ] } { + return $fullPath + } + } + return "" +} + +source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ] + +set result [ run_cg_update "PrefetchDataRAM" xc6slx9-2ftg256 Verilog ] + +if { $result == 0 } { + puts "Core Generator update command completed successfully." +} elseif { $result == 1 } { + puts "Core Generator update command failed." +} elseif { $result == 3 || $result == 4 } { + # convert 'version check' result to real return range, bypassing any messages. + set result [ expr $result - 3 ] +} else { + puts "Core Generator update cancelled." +} +exit $result diff --git a/fpga/iseconfig/ClkGen.xreport b/fpga/iseconfig/ClkGen.xreport new file mode 100644 index 0000000..3be29a1 --- /dev/null +++ b/fpga/iseconfig/ClkGen.xreport @@ -0,0 +1,215 @@ + + +
+ 2021-10-31T14:26:13 + WarpLC + 2021-10-31T14:24:19 + C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/iseconfig/ClkGen.xreport + C:/Users/Dog/Documents/GitHub/Warp-LC/fpga + 2021-10-31T13:53:00 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/iseconfig/WarpLC.projectmgr b/fpga/iseconfig/WarpLC.projectmgr index 8c41bed..44cfd8b 100644 --- a/fpga/iseconfig/WarpLC.projectmgr +++ b/fpga/iseconfig/WarpLC.projectmgr @@ -7,13 +7,14 @@ 2 + /ClkGen C:|Users|Dog|Documents|GitHub|Warp-LC|fpga|ClkGen.v WarpLC (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v) 0 0 - 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000110000000020000000000000000000000000200000064ffffffff000000810000000300000002000001100000000100000003000000000000000100000003 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000187000000020000000000000000000000000200000064ffffffff000000810000000300000002000001870000000100000003000000000000000100000003 true WarpLC (C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/WarpLC.v) @@ -27,13 +28,13 @@ User Constraints - + 0 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000 false - + @@ -86,40 +87,40 @@ Synthesize - XST - + Analyze Post-Place & Route Static Timing - 0 + 11 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000142000000010000000100000000000000000000000064ffffffff000000810000000000000001000001420000000100000000 false - + Analyze Post-Place & Route Static Timing 1 - + 0 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000 false - + 1 - + 0 0 - 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000153000000010000000100000000000000000000000064ffffffff000000810000000000000001000001530000000100000000 false - + - 000000ff00000000000000020000011b0000011b01000000050100000002 + 000000ff00000000000000020000012e0000011301000000050100000002 Implementation diff --git a/fpga/iseconfig/WarpLC.xreport b/fpga/iseconfig/WarpLC.xreport index 6ba9ce7..ddebb1a 100644 --- a/fpga/iseconfig/WarpLC.xreport +++ b/fpga/iseconfig/WarpLC.xreport @@ -1,7 +1,7 @@
- 2021-10-30T17:26:12 + 2021-10-31T07:31:41 WarpLC 2021-10-29T17:39:15 C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/iseconfig/WarpLC.xreport diff --git a/fpga/par_usage_statistics.html b/fpga/par_usage_statistics.html index bd140bd..6e00415 100644 --- a/fpga/par_usage_statistics.html +++ b/fpga/par_usage_statistics.html @@ -1,32 +1,33 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - + - +
Par Statistics
Total Non-vccgnd Signals=84
Total Non-vccgnd Design Pins=135
Total Non-vccgnd Conns=135
Total Non-vccgnd Timing Constrained Conns=122
Phase 1 CPU=2.1 sec
Phase 2 CPU=2.3 sec
Phase 3 CPU=2.5 sec
Phase 4 CPU=2.7 sec
Phase 5 CPU=2.9 sec
Phase 6 CPU=2.9 sec
Phase 7 CPU=2.9 sec
Phase 8 CPU=2.9 sec
Phase 9 CPU=2.9 sec
Phase 10 CPU=2.9 sec
AvgWirelenPerPin Fanout 1=5.0
AvgWirelenPerPin Fanout 2=10.5
AvgWirelenPerPin Fanout 3=0.7
Total Non-vccgnd Signals=97
Total Non-vccgnd Design Pins=178
Total Non-vccgnd Conns=178
Total Non-vccgnd Timing Constrained Conns=48
Phase 1 CPU=3.4 sec
Phase 2 CPU=3.7 sec
Phase 3 CPU=3.8 sec
Phase 4 CPU=4.2 sec
Phase 5 CPU=4.3 sec
Phase 6 CPU=4.3 sec
Phase 7 CPU=4.3 sec
Phase 8 CPU=4.3 sec
Phase 9 CPU=4.3 sec
Phase 10 CPU=4.3 sec
Phase 11 CPU=4.3 sec
AvgWirelenPerPin Fanout 1=7.0
AvgWirelenPerPin Fanout 2=40.0
AvgWirelenPerPin Fanout 3=6.7
AvgWirelenPerPin Fanout 4=0.0
AvgWirelenPerPin Fanout 10=0.0
AvgWirelenPerPin Fanout 50=9.1
AvgWirelenPerPin Fanout 50=4.5
AvgWirelenPerPin Fanout 100=0.0
AvgWirelenPerPin Fanout 500=0.0
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.0090
IRR Gamma=1.0257
diff --git a/fpga/sterminator.v b/fpga/sterminator.v deleted file mode 100644 index 1ba2706..0000000 --- a/fpga/sterminator.v +++ /dev/null @@ -1,88 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 17:33:01 10/30/2021 -// Design Name: -// Module Name: sterminator -// Project Name: -// Target Devices: -// Tool versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -// SDRAM addressing for RAM -// A[25:13] - Row[12:0] -// A[12:4] - Column[8:0] -// A[3:2] - Bank[1:0] -// A[1:0] - SDRAM word size - -module sterminator( - input CLK, - input [31:2] A, - input nWE, - input SEL, - input STERMin, - output nSTERM, - input RESET, - input [2:0] CMD); - - reg [3:0] BankActive; - reg [12:0] Bank0Row; - reg [12:0] Bank1Row; - reg [12:0] Bank2Row; - reg [12:0] Bank3Row; - reg SpecRDActive; - reg [30:2] SpecRDAddr; - - wire [12:0] A_Row = A[25:13]; - wire [8:0] A_Column = A[12:4]; - wire [1:0] A_Bank = A[3:2]; - - wire A_CurBankRow = A_Bank==0 ? Bank0Row : - A_Bank==1 ? Bank1Row : - A_Bank==2 ? Bank2Row : - A_Bank==3 ? Bank3Row : 0; - - wire SpecRDSEL = SEL && nWE && ~A[31] && A[30:2]==SpecRDAddr[30:2]; - wire FastWRSEL = SEL && ~nWE && ~A[31] && A_CurBankRow==A_Row; - - assign nSTERM = ~(STERMin || SpecRDSEL || FastWRSEL); - - always @(posedge CLK) begin - case (CMD) - 3'b000: begin // Reset - BankActive <= 0; - SpecRDActive <= 0; - end 3'b001: begin // Row activate - BankActive[A_Bank] <= 1; - case (A_Bank) - 0: Bank0Row <= A_Row; - 1: Bank1Row <= A_Row; - 2: Bank2Row <= A_Row; - 3: Bank3Row <= A_Row; - endcase - end 3'b010: begin // Row precharge - BankActive[A_Bank] <= 0; - end 3'b011: begin // Precharge all - BankActive <= 0; - end 3'b100: begin // NOP - end 3'b101: begin // Speculative read - SpecRDAddr <= A[30:2]; - SpecRDActive <= 1; - end 3'b110: begin // Clear speculation - SpecRDActive <= 0; - end 3'b111: begin // Reserved (NOP) - end - endcase - end - -endmodule diff --git a/fpga/webtalk_pn.xml b/fpga/webtalk_pn.xml new file mode 100644 index 0000000..abecbd7 --- /dev/null +++ b/fpga/webtalk_pn.xml @@ -0,0 +1,62 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/fpga/xlnx_auto_0_xdb/cst.xbcd b/fpga/xlnx_auto_0_xdb/cst.xbcd index 025e9d1..2868365 100644 Binary files a/fpga/xlnx_auto_0_xdb/cst.xbcd and b/fpga/xlnx_auto_0_xdb/cst.xbcd differ diff --git a/fpga/xst/work/work.sdbl b/fpga/xst/work/work.sdbl index 8e4e257..2e269d2 100644 Binary files a/fpga/xst/work/work.sdbl and b/fpga/xst/work/work.sdbl differ diff --git a/fpga/xst/work/work.sdbx b/fpga/xst/work/work.sdbx index 4863cc7..82d1cc6 100644 Binary files a/fpga/xst/work/work.sdbx and b/fpga/xst/work/work.sdbx differ