From 55c77e7fba7a49f18c6e00f6dbf119b7af7b3346 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Fri, 29 Oct 2021 06:04:52 -0400 Subject: [PATCH] add from other repo --- .gitignore | 29 + CPUBuf.sch | 1825 +++ Control.sch | 1270 ++ Docs/index.html | 151 + MC68k.sch | 1139 ++ PDS.sch | 642 + PDSBuf.sch | 1881 +++ RAM.sch | 560 + SE-030-cache.lib | 856 + SE-030.kicad_pcb | 13378 ++++++++++++++++ SE-030.pro | 269 + SE-030.sch | 529 + fp-lib-table | 3 + sterminator/STERMINATOR.v | 67 + sterminator/XC9572XL/STERMINATOR.bld | 36 + sterminator/XC9572XL/STERMINATOR.cmd_log | 110 + sterminator/XC9572XL/STERMINATOR.gise | 130 + sterminator/XC9572XL/STERMINATOR.gyd | 61 + sterminator/XC9572XL/STERMINATOR.jed | 1685 ++ sterminator/XC9572XL/STERMINATOR.lso | 1 + sterminator/XC9572XL/STERMINATOR.mfd | 670 + sterminator/XC9572XL/STERMINATOR.nga | 3 + sterminator/XC9572XL/STERMINATOR.ngc | 3 + sterminator/XC9572XL/STERMINATOR.ngd | 3 + sterminator/XC9572XL/STERMINATOR.ngr | 3 + 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Garrett's Workshop Warp-LC 33 MHz 68030 Accelerator Documentation

+ +

1. Three consecutive reads - row activate, row hit, row miss, next hit

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+ +

1. Three consecutive reads - non-prefeteched read, two next hits, next hit after idle, row hit

+

+ +

2. Three consecutive writes - row activate, row hit, row miss

+

+ +

3. MC68030 read row hit, then MC68030 changes its mind -- read, row activate, row hit, row miss

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+ +

4. MC68030 read row hit, then MC68030 changes its mind -- write, row miss

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+ +

5. MC68030 idle afte read

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6. MC68030 idle afte write

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Line + 4600 4500 4600 4400 +$Comp +L power:GND #PWR0129 +U 1 1 63274829 +P 4600 4500 +F 0 "#PWR0129" H 4600 4250 50 0001 C CNN +F 1 "GND" H 4600 4350 50 0000 C CNN +F 2 "" H 4600 4500 50 0001 C CNN +F 3 "" H 4600 4500 50 0001 C CNN + 1 4600 4500 + 1 0 0 -1 +$EndComp +Text HLabel 4600 4200 0 50 Input ~ 0 +CLK23 +Text HLabel 4600 4100 0 50 Input ~ 0 +CKE +Text HLabel 5600 4500 2 50 Input ~ 0 +~RAS~ +Text HLabel 5600 4400 2 50 Input ~ 0 +~CAS~ +Text HLabel 5600 4300 2 50 Input ~ 0 +~WE~ +Text HLabel 5600 4200 2 50 Input ~ 0 +~CS~ +Text Label 5600 3700 0 50 ~ 0 +D31 +Text Label 5600 3600 0 50 ~ 0 +D30 +Text Label 5600 3500 0 50 ~ 0 +D29 +Text Label 5600 3400 0 50 ~ 0 +D28 +Text Label 5600 3300 0 50 ~ 0 +D27 +Text Label 5600 3200 0 50 ~ 0 +D26 +Text Label 5600 3100 0 50 ~ 0 +D25 +Text Label 5600 3000 0 50 ~ 0 +D24 +Text Label 5600 2900 0 50 ~ 0 +D23 +Text Label 5600 2800 0 50 ~ 0 +D22 +Text Label 5600 2700 0 50 ~ 0 +D21 +Text Label 5600 2600 0 50 ~ 0 +D20 +Text Label 5600 2500 0 50 ~ 0 +D19 +Text Label 5600 2400 0 50 ~ 0 +D18 +Text Label 5600 2300 0 50 ~ 0 +D17 +Text Label 5600 2200 0 50 ~ 0 +D16 +Text Label 5600 3900 0 50 ~ 0 +DQM3 +Text Label 5600 3800 0 50 ~ 0 +DQM2 +Text Label 4600 3900 2 50 ~ 0 +BA1 +Text Label 4600 3800 2 50 ~ 0 +BA0 +Text Label 4600 3700 2 50 ~ 0 +RA12 +Text Label 4600 3600 2 50 ~ 0 +RA11 +Text Label 4600 3500 2 50 ~ 0 +RA10 +Text Label 4600 3400 2 50 ~ 0 +RA9 +Text Label 4600 3300 2 50 ~ 0 +RA8 +Text Label 4600 3200 2 50 ~ 0 +RA7 +Text Label 4600 3100 2 50 ~ 0 +RA6 +Text Label 4600 3000 2 50 ~ 0 +RA5 +Text Label 4600 2800 2 50 ~ 0 +RA3 +Text Label 4600 2900 2 50 ~ 0 +RA4 +Text Label 4600 2700 2 50 ~ 0 +RA2 +Text Label 4600 2600 2 50 ~ 0 +RA1 +Text Label 4600 2500 2 50 ~ 0 +RA0 +Text HLabel 2050 2600 0 50 Input ~ 0 +RA[12..0] +Text HLabel 2050 3900 0 50 Input ~ 0 +BA[1..0] +Text HLabel 4250 3900 0 50 Input ~ 0 +BA[1..0] +Wire Bus Line + 3700 4000 3750 4000 +Wire Bus Line + 5900 4000 5950 4000 +Text HLabel 3750 4000 2 50 Input ~ 0 +DQM[3..0] +Text HLabel 5950 4000 2 50 Input ~ 0 +DQM[3..0] +$Comp +L GW_RAM:SDRAM-16Mx16-TSOP2-54 U5 +U 1 1 6327223F +P 5100 3200 +F 0 "U5" H 5100 4350 50 0000 C CNN +F 1 "W9825G6KH-6" V 5100 3200 50 0000 C CNN +F 2 "stdpads:Winbond_TSOPII-54" H 5100 1550 50 0001 C CIN +F 3 "" H 5100 2950 50 0001 C CNN + 1 5100 3200 + 1 0 0 -1 +$EndComp +Wire Bus Line + 3700 2300 3700 3800 +Wire Bus Line + 2100 2600 2100 3800 +Wire Bus Line + 4300 2600 4300 3800 +Wire Bus Line + 5900 2300 5900 3800 +$EndSCHEMATC diff --git a/SE-030-cache.lib b/SE-030-cache.lib new file mode 100644 index 0000000..78d9d8b --- /dev/null +++ b/SE-030-cache.lib @@ -0,0 +1,856 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Device_C_Small +# +DEF Device_C_Small C 0 10 N N 1 F N +F0 "C" 10 70 50 H V L CNN +F1 "Device_C_Small" 10 -80 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 13 -60 -20 60 -20 N +P 2 0 1 12 -60 20 60 20 N +X ~ 1 0 100 80 D 50 50 1 1 P +X ~ 2 0 -100 80 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_R_Small +# +DEF Device_R_Small R 0 10 N N 1 F N +F0 "R" 30 20 50 H V L CNN +F1 "Device_R_Small" 30 -40 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -30 70 30 -70 0 1 8 N +X ~ 1 0 100 30 D 50 50 1 1 P +X ~ 2 0 -100 30 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# FPGA_Xilinx_Spartan6_XC6SLX9-FTG256 +# +DEF FPGA_Xilinx_Spartan6_XC6SLX9-FTG256 U 0 40 Y Y 4 L N +F0 "U" 0 50 50 H V C CNN +F1 "FPGA_Xilinx_Spartan6_XC6SLX9-FTG256" 0 -50 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H V C CNN +DRAW +S -1750 2850 1750 -3100 1 1 10 f +S -1750 2850 1750 -3100 2 1 10 f +S -1250 600 1250 -600 3 1 10 f +S -750 1200 750 -1200 4 1 10 f +X IO_L35N_GCLK16_0 A10 -2000 400 250 R 50 50 1 1 B +X IO_L39N_0 A11 -2000 -400 250 R 50 50 1 1 B +X IO_L62N_VREF_0 A12 -2000 -800 250 R 50 50 1 1 B +X IO_L63N_SCP6_0 A13 -2000 -1000 250 R 50 50 1 1 B +X IO_L65N_SCP2_0 A14 -2000 -1400 250 R 50 50 1 1 B +X IO_L1N_VREF_0 A4 -2000 2200 250 R 50 50 1 1 B +X IO_L2N_0 A5 -2000 2000 250 R 50 50 1 1 B +X IO_L4N_0 A6 -2000 1600 250 R 50 50 1 1 B +X IO_L6N_0 A7 -2000 1200 250 R 50 50 1 1 B +X IO_L33N_0 A8 -2000 800 250 R 50 50 1 1 B +X IO_L34N_GCLK18_0 A9 -2000 600 250 R 50 50 1 1 B +X IO_L35P_GCLK17_0 B10 -2000 500 250 R 50 50 1 1 B +X IO_L62P_0 B12 -2000 -700 250 R 50 50 1 1 B +X VCCO_0 B13 -1400 3100 250 D 50 50 1 1 W +X IO_L65P_SCP3_0 B14 -2000 -1300 250 R 50 50 1 1 B +X IO_L29P_A23_M1A13_1 B15 2000 2100 250 L 50 50 1 1 B +X IO_L29N_A22_M1A14_1 B16 2000 2000 250 L 50 50 1 1 B +X VCCO_0 B4 -1600 3100 250 D 50 50 1 1 W +X IO_L2P_0 B5 -2000 2100 250 R 50 50 1 1 B +X IO_L4P_0 B6 -2000 1700 250 R 50 50 1 1 B +X IO_L33P_0 B8 -2000 900 250 R 50 50 1 1 B +X VCCO_0 B9 -1500 3100 250 D 50 50 1 1 W +X IO_L37N_GCLK12_0 C10 -2000 0 250 R 50 50 1 1 B +X IO_L39P_0 C11 -2000 -300 250 R 50 50 1 1 B +X IO_L63P_SCP7_0 C13 -2000 -900 250 R 50 50 1 1 B +X IO_L33P_A15_M1A10_1 C15 2000 1300 250 L 50 50 1 1 B +X IO_L33N_A14_M1A4_1 C16 2000 1200 250 L 50 50 1 1 B +X IO_L1P_HSWAPEN_0 C4 -2000 2300 250 R 50 50 1 1 B +X IO_L3N_0 C5 -2000 1800 250 R 50 50 1 1 B +X IO_L7N_0 C6 -2000 1000 250 R 50 50 1 1 B +X IO_L6P_0 C7 -2000 1300 250 R 50 50 1 1 B +X IO_L38N_VREF_0 C8 -2000 -200 250 R 50 50 1 1 B +X IO_L34P_GCLK19_0 C9 -2000 700 250 R 50 50 1 1 B +X VCCO_0 D10 -1200 3100 250 D 50 50 1 1 W +X IO_L66P_SCP1_0 D11 -2000 -1500 250 R 50 50 1 1 B +X IO_L66N_SCP0_0 D12 -2000 -1600 250 R 50 50 1 1 B +X IO_L31P_A19_M1CKE_1 D14 2000 1700 250 L 50 50 1 1 B +X VCCO_1 D15 1100 3100 250 D 50 50 1 1 W +X IO_L31N_A18_M1A12_1 D16 2000 1600 250 L 50 50 1 1 B +X IO_L3P_0 D5 -2000 1900 250 R 50 50 1 1 B +X IO_L7P_0 D6 -2000 1100 250 R 50 50 1 1 B +X VCCO_0 D7 -1300 3100 250 D 50 50 1 1 W +X IO_L38P_0 D8 -2000 -100 250 R 50 50 1 1 B +X IO_L40N_0 D9 -2000 -600 250 R 50 50 1 1 B +X IO_L37P_GCLK13_0 E10 -2000 100 250 R 50 50 1 1 B +X IO_L64N_SCP4_0 E11 -2000 -1200 250 R 50 50 1 1 B +X IO_L1N_A24_VREF_1 E12 2000 2200 250 L 50 50 1 1 B +X IO_L1P_A25_1 E13 2000 2300 250 L 50 50 1 1 B +X IO_L34P_A13_M1WE_1 E15 2000 1100 250 L 50 50 1 1 B +X IO_L34N_A12_M1BA2_1 E16 2000 1000 250 L 50 50 1 1 B +X IO_L5N_0 E6 -2000 1400 250 R 50 50 1 1 B +X IO_L36P_GCLK15_0 E7 -2000 300 250 R 50 50 1 1 B +X IO_L36N_GCLK14_0 E8 -2000 200 250 R 50 50 1 1 B +X IO_L64P_SCP5_0 F10 -2000 -1100 250 R 50 50 1 1 B +X IO_L30P_A21_M1RESET_1 F12 2000 1900 250 L 50 50 1 1 B +X IO_L32P_A17_M1A8_1 F13 2000 1500 250 L 50 50 1 1 B +X IO_L32N_A16_M1A9_1 F14 2000 1400 250 L 50 50 1 1 B +X IO_L35P_A11_M1A7_1 F15 2000 900 250 L 50 50 1 1 B +X IO_L35N_A10_M1A2_1 F16 2000 800 250 L 50 50 1 1 B +X IO_L5P_0 F7 -2000 1500 250 R 50 50 1 1 B +X IO_L40P_0 F9 -2000 -500 250 R 50 50 1 1 B +X IO_L30N_A20_M1A11_1 G11 2000 1800 250 L 50 50 1 1 B +X IO_L38P_A5_M1CLK_1 G12 2000 300 250 L 50 50 1 1 B +X VCCO_1 G13 1200 3100 250 D 50 50 1 1 W +X IO_L36P_A9_M1BA0_1 G14 2000 700 250 L 50 50 1 1 B +X IO_L36N_A8_M1BA1_1 G16 2000 600 250 L 50 50 1 1 B +X IO_L38N_A4_M1CLKN_1 H11 2000 200 250 L 50 50 1 1 B +X IO_L39P_M1A3_1 H13 2000 100 250 L 50 50 1 1 B +X IO_L39N_M1ODT_1 H14 2000 0 250 L 50 50 1 1 B +X IO_L37P_A7_M1A0_1 H15 2000 500 250 L 50 50 1 1 B +X IO_L37N_A6_M1A1_1 H16 2000 400 250 L 50 50 1 1 B +X IO_L40P_GCLK11_M1A5_1 J11 2000 -100 250 L 50 50 1 1 B +X IO_L40N_GCLK10_M1A6_1 J12 2000 -200 250 L 50 50 1 1 B +X IO_L41P_GCLK9_IRDY1_M1RASN_1 J13 2000 -300 250 L 50 50 1 1 B +X IO_L43P_GCLK5_M1DQ4_1 J14 2000 -700 250 L 50 50 1 1 B +X VCCO_1 J15 1300 3100 250 D 50 50 1 1 W +X IO_L43N_GCLK4_M1DQ5_1 J16 2000 -800 250 L 50 50 1 1 B +X IO_L42N_GCLK6_TRDY1_M1LDM_1 K11 2000 -600 250 L 50 50 1 1 B +X IO_L42P_GCLK7_M1UDM_1 K12 2000 -500 250 L 50 50 1 1 B +X VCCO_1 K13 1400 3100 250 D 50 50 1 1 W +X IO_L41N_GCLK8_M1CASN_1 K14 2000 -400 250 L 50 50 1 1 B +X IO_L44P_A3_M1DQ6_1 K15 2000 -900 250 L 50 50 1 1 B +X IO_L44N_A2_M1DQ7_1 K16 2000 -1000 250 L 50 50 1 1 B +X IO_L53P_1 L12 2000 -2700 250 L 50 50 1 1 B +X IO_L53N_VREF_1 L13 2000 -2800 250 L 50 50 1 1 B +X IO_L47P_FWE_B_M1DQ0_1 L14 2000 -1500 250 L 50 50 1 1 B +X IO_L47N_LDC_M1DQ1_1 L16 2000 -1600 250 L 50 50 1 1 B +X IO_L74P_AWAKE_1 M13 2000 -2900 250 L 50 50 1 1 B +X IO_L74N_DOUT_BUSY_1 M14 2000 -3000 250 L 50 50 1 1 B +X IO_L46P_FCS_B_M1DQ2_1 M15 2000 -1300 250 L 50 50 1 1 B +X IO_L46N_FOE_B_M1DQ3_1 M16 2000 -1400 250 L 50 50 1 1 B +X IO_L45P_A1_M1LDQS_1 N14 2000 -1100 250 L 50 50 1 1 B +X VCCO_1 N15 1500 3100 250 D 50 50 1 1 W +X IO_L45N_A0_M1LDQSN_1 N16 2000 -1200 250 L 50 50 1 1 B +X IO_L48P_HDC_M1DQ8_1 P15 2000 -1700 250 L 50 50 1 1 B +X IO_L48N_M1DQ9_1 P16 2000 -1800 250 L 50 50 1 1 B +X IO_L52P_M1DQ14_1 R12 2000 -2500 250 L 50 50 1 1 B +X VCCO_1 R13 1600 3100 250 D 50 50 1 1 W +X IO_L50P_M1UDQS_1 R14 2000 -2100 250 L 50 50 1 1 B +X IO_L49P_M1DQ10_1 R15 2000 -1900 250 L 50 50 1 1 B +X IO_L49N_M1DQ11_1 R16 2000 -2000 250 L 50 50 1 1 B +X IO_L52N_M1DQ15_1 T12 2000 -2600 250 L 50 50 1 1 B +X IO_L51N_M1DQ13_1 T13 2000 -2400 250 L 50 50 1 1 B +X IO_L51P_M1DQ12_1 T14 2000 -2300 250 L 50 50 1 1 B +X IO_L50N_M1UDQSN_1 T15 2000 -2200 250 L 50 50 1 1 B +X IO_L52N_M3A9_3 A2 2000 -2200 250 L 50 50 2 1 B +X IO_L83N_VREF_3 A3 2000 -3000 250 L 50 50 2 1 B +X IO_L50N_M3BA2_3 B1 2000 -1800 250 L 50 50 2 1 B +X IO_L52P_M3A8_3 B2 2000 -2100 250 L 50 50 2 1 B +X IO_L83P_3 B3 2000 -2900 250 L 50 50 2 1 B +X IO_L50P_M3WE_3 C1 2000 -1700 250 L 50 50 2 1 B +X IO_L48N_M3BA1_3 C2 2000 -1400 250 L 50 50 2 1 B +X IO_L48P_M3BA0_3 C3 2000 -1300 250 L 50 50 2 1 B +X IO_L49N_M3A2_3 D1 2000 -1600 250 L 50 50 2 1 B +X VCCO_3 D2 1200 3100 250 D 50 50 2 1 W +X IO_L49P_M3A7_3 D3 2000 -1500 250 L 50 50 2 1 B +X IO_L46N_M3CLKN_3 E1 2000 -1000 250 L 50 50 2 1 B +X IO_L46P_M3CLK_3 E2 2000 -900 250 L 50 50 2 1 B +X IO_L54N_M3A11_3 E3 2000 -2600 250 L 50 50 2 1 B +X IO_L54P_M3RESET_3 E4 2000 -2500 250 L 50 50 2 1 B +X IO_L41N_GCLK26_M3DQ5_3 F1 2000 0 250 L 50 50 2 1 B +X IO_L41P_GCLK27_M3DQ4_3 F2 2000 100 250 L 50 50 2 1 B +X IO_L53N_M3A12_3 F3 2000 -2400 250 L 50 50 2 1 B +X IO_L53P_M3CKE_3 F4 2000 -2300 250 L 50 50 2 1 B +X IO_L55N_M3A14_3 F5 2000 -2800 250 L 50 50 2 1 B +X IO_L55P_M3A13_3 F6 2000 -2700 250 L 50 50 2 1 B +X IO_L40N_M3DQ7_3 G1 2000 200 250 L 50 50 2 1 B +X IO_L40P_M3DQ6_3 G3 2000 300 250 L 50 50 2 1 B +X VCCO_3 G4 1300 3100 250 D 50 50 2 1 W +X IO_L51N_M3A4_3 G5 2000 -2000 250 L 50 50 2 1 B +X IO_L51P_M3A10_3 G6 2000 -1900 250 L 50 50 2 1 B +X IO_L39N_M3LDQSN_3 H1 2000 400 250 L 50 50 2 1 B +X IO_L39P_M3LDQS_3 H2 2000 500 250 L 50 50 2 1 B +X IO_L44N_GCLK20_M3A6_3 H3 2000 -600 250 L 50 50 2 1 B +X IO_L44P_GCLK21_M3A5_3 H4 2000 -500 250 L 50 50 2 1 B +X IO_L43N_GCLK22_IRDY2_M3CASN_3 H5 2000 -400 250 L 50 50 2 1 B +X IO_L38N_M3DQ3_3 J1 2000 600 250 L 50 50 2 1 B +X VCCO_3 J2 1400 3100 250 D 50 50 2 1 W +X IO_L38P_M3DQ2_3 J3 2000 700 250 L 50 50 2 1 B +X IO_L42N_GCLK24_M3LDM_3 J4 2000 -200 250 L 50 50 2 1 B +X IO_L43P_GCLK23_M3RASN_3 J6 2000 -300 250 L 50 50 2 1 B +X IO_L37N_M3DQ1_3 K1 2000 800 250 L 50 50 2 1 B +X IO_L37P_M3DQ0_3 K2 2000 900 250 L 50 50 2 1 B +X IO_L42P_GCLK25_TRDY2_M3UDM_3 K3 2000 -100 250 L 50 50 2 1 B +X VCCO_3 K4 1500 3100 250 D 50 50 2 1 W +X IO_L47P_M3A0_3 K5 2000 -1100 250 L 50 50 2 1 B +X IO_L47N_M3A1_3 K6 2000 -1200 250 L 50 50 2 1 B +X IO_L36N_M3DQ9_3 L1 2000 1000 250 L 50 50 2 1 B +X IO_L16P_2 L10 -2000 900 250 R 50 50 2 1 B +X IO_L36P_M3DQ8_3 L3 2000 1100 250 L 50 50 2 1 B +X IO_L45P_M3A3_3 L4 2000 -700 250 L 50 50 2 1 B +X IO_L45N_M3ODT_3 L5 2000 -800 250 L 50 50 2 1 B +X IO_L62N_D6_2 L7 -2000 -800 250 R 50 50 2 1 B +X IO_L62P_D5_2 L8 -2000 -700 250 R 50 50 2 1 B +X IO_L35N_M3DQ11_3 M1 2000 1200 250 L 50 50 2 1 B +X IO_L16N_VREF_2 M10 -2000 800 250 R 50 50 2 1 B +X IO_L2N_CMPMOSI_2 M11 -2000 2000 250 R 50 50 2 1 B +X IO_L2P_CMPCLK_2 M12 -2000 2100 250 R 50 50 2 1 B +X IO_L35P_M3DQ10_3 M2 2000 1300 250 L 50 50 2 1 B +X IO_L1N_VREF_3 M3 2000 2200 250 L 50 50 2 1 B +X IO_L1P_3 M4 2000 2300 250 L 50 50 2 1 B +X IO_L2P_3 M5 2000 2100 250 L 50 50 2 1 B +X IO_L64P_D8_2 M6 -2000 -1100 250 R 50 50 2 1 B +X IO_L31N_GCLK30_D15_2 M7 -2000 200 250 R 50 50 2 1 B +X IO_L29P_GCLK3_2 M9 -2000 700 250 R 50 50 2 1 B +X IO_L34N_M3UDQSN_3 N1 2000 1400 250 L 50 50 2 1 B +X VCCO_2 N10 -1500 3100 250 D 50 50 2 1 W +X IO_L13P_M1_2 N11 -2000 1500 250 R 50 50 2 1 B +X IO_L12P_D1_MISO2_2 N12 -2000 1700 250 R 50 50 2 1 B +X VCCO_3 N2 1600 3100 250 D 50 50 2 1 W +X IO_L34P_M3UDQS_3 N3 2000 1500 250 L 50 50 2 1 B +X IO_L2N_3 N4 2000 2000 250 L 50 50 2 1 B +X IO_L49P_D3_2 N5 -2000 -500 250 R 50 50 2 1 B +X IO_L64N_D9_2 N6 -2000 -1200 250 R 50 50 2 1 B +X VCCO_2 N7 -1600 3100 250 D 50 50 2 1 W +X IO_L29N_GCLK2_2 N8 -2000 600 250 R 50 50 2 1 B +X IO_L14P_D11_2 N9 -2000 1300 250 R 50 50 2 1 B +X IO_L33N_M3DQ13_3 P1 2000 1600 250 L 50 50 2 1 B +X IO_L3P_D0_DIN_MISO_MISO1_2 P10 -2000 1900 250 R 50 50 2 1 B +X IO_L13N_D10_2 P11 -2000 1400 250 R 50 50 2 1 B +X IO_L12N_D2_MISO3_2 P12 -2000 1600 250 R 50 50 2 1 B +X IO_L33P_M3DQ12_3 P2 2000 1700 250 L 50 50 2 1 B +X IO_L63P_2 P4 -2000 -900 250 R 50 50 2 1 B +X IO_L49N_D4_2 P5 -2000 -600 250 R 50 50 2 1 B +X IO_L47P_2 P6 -2000 -100 250 R 50 50 2 1 B +X IO_L31P_GCLK31_D14_2 P7 -2000 300 250 R 50 50 2 1 B +X IO_L30P_GCLK1_D13_2 P8 -2000 500 250 R 50 50 2 1 B +X IO_L14N_D12_2 P9 -2000 1200 250 R 50 50 2 1 B +X IO_L32N_M3DQ15_3 R1 2000 1800 250 L 50 50 2 1 B +X IO_L1P_CCLK_2 R11 -2000 2300 250 R 50 50 2 1 B +X IO_L32P_M3DQ14_3 R2 2000 1900 250 L 50 50 2 1 B +X IO_L65P_INIT_B_2 R3 -2000 -1300 250 R 50 50 2 1 B +X VCCO_2 R4 -1400 3100 250 D 50 50 2 1 W +X IO_L48P_D7_2 R5 -2000 -300 250 R 50 50 2 1 B +X IO_L32P_GCLK29_2 R7 -2000 100 250 R 50 50 2 1 B +X VCCO_2 R8 -1300 3100 250 D 50 50 2 1 W +X IO_L23P_2 R9 -2000 1100 250 R 50 50 2 1 B +X IO_L3N_MOSI_CSI_B_MISO0_2 T10 -2000 1800 250 R 50 50 2 1 B +X IO_L1N_M0_CMPMISO_2 T11 -2000 2200 250 R 50 50 2 1 B +X IO_L65N_CSO_B_2 T3 -2000 -1400 250 R 50 50 2 1 B +X IO_L63N_2 T4 -2000 -1000 250 R 50 50 2 1 B +X IO_L48N_RDWR_B_VREF_2 T5 -2000 -400 250 R 50 50 2 1 B +X IO_L47N_2 T6 -2000 -200 250 R 50 50 2 1 B +X IO_L32N_GCLK28_2 T7 -2000 0 250 R 50 50 2 1 B +X IO_L30N_GCLK0_USERCCLK_2 T8 -2000 400 250 R 50 50 2 1 B +X IO_L23N_2 T9 -2000 1000 250 R 50 50 2 1 B +X TMS A15 1500 300 250 L 50 50 3 1 B +X TDI C12 1500 500 250 L 50 50 3 1 B +X TCK C14 1500 200 250 L 50 50 3 1 B +X TDO E14 1500 400 250 L 50 50 3 1 B +X CMPCS_B_2 L11 1500 -500 250 L 50 50 3 1 B +X DONE_2 P13 1500 0 250 L 50 50 3 1 B +X SUSPEND P14 1500 -300 250 L 50 50 3 1 B +X PROGRAM_B_2 T2 1500 -100 250 L 50 50 3 1 B +X GND A1 -1000 100 250 R 50 50 4 1 W +X GND A16 -1000 0 250 R 50 50 4 1 W +X GND B11 -1000 -200 250 R 50 50 4 1 W +X GND B7 -1000 -100 250 R 50 50 4 1 W +X GND D13 -1000 -400 250 R 50 50 4 1 W +X GND D4 -1000 -300 250 R 50 50 4 1 W +X VCCAUX E5 -1000 1100 250 R 50 50 4 1 W +X GND E9 -1000 -500 250 R 50 50 4 1 W +X VCCAUX F11 -1000 900 250 R 50 50 4 1 W +X VCCAUX F8 -1000 1000 250 R 50 50 4 1 W +X VCCAUX G10 -1000 800 250 R 50 50 4 1 W +X GND G15 -1000 -800 250 R 50 50 4 1 W +X GND G2 -1000 -600 250 R 50 50 4 1 W +X VCCINT G7 1000 1100 250 L 50 50 4 1 W +X GND G8 -1000 -700 250 R 50 50 4 1 W +X VCCINT G9 1000 1000 250 L 50 50 4 1 W +X VCCINT H10 1000 800 250 L 50 50 4 1 W +X GND H12 -1000 -1100 250 R 50 50 4 1 W +X VCCAUX H6 -1000 700 250 R 50 50 4 1 W +X GND H7 -1000 -900 250 R 50 50 4 1 W +X VCCINT H8 1000 900 250 L 50 50 4 1 W +X GND H9 -1000 -1000 250 R 50 50 4 1 W +X VCCAUX J10 -1000 600 250 R 50 50 4 1 W +X GND J5 1000 100 250 L 50 50 4 1 W +X VCCINT J7 1000 700 250 L 50 50 4 1 W +X GND J8 1000 0 250 L 50 50 4 1 W +X VCCINT J9 1000 600 250 L 50 50 4 1 W +X VCCINT K10 1000 400 250 L 50 50 4 1 W +X GND K7 1000 -100 250 L 50 50 4 1 W +X VCCINT K8 1000 500 250 L 50 50 4 1 W +X GND K9 1000 -200 250 L 50 50 4 1 W +X GND L15 1000 -400 250 L 50 50 4 1 W +X GND L2 1000 -300 250 L 50 50 4 1 W +X VCCAUX L6 -1000 500 250 R 50 50 4 1 W +X VCCAUX L9 -1000 400 250 R 50 50 4 1 W +X GND M8 1000 -500 250 L 50 50 4 1 W +X GND N13 1000 -600 250 L 50 50 4 1 W +X GND P3 1000 -700 250 L 50 50 4 1 W +X GND R10 1000 -900 250 L 50 50 4 1 W +X GND R6 1000 -800 250 L 50 50 4 1 W +X GND T1 1000 -1000 250 L 50 50 4 1 W +X GND T16 1000 -1100 250 L 50 50 4 1 W +ENDDRAW +ENDDEF +# +# GW_CPU_MC68030FE +# +DEF GW_CPU_MC68030FE U 0 40 Y Y 1 F N +F0 "U" 50 2600 50 H V C CNN +F1 "GW_CPU_MC68030FE" 50 2500 50 H V C CNN +F2 "stdpads:Motorola_CQFP-132" 0 500 40 H I C CNN +F3 "" 0 500 50 H I C CNN +DRAW +S 1200 -2400 -1200 3250 0 1 10 f +X GND 1 -750 -2550 150 U 50 50 1 1 W +X FC1 10 -1350 2700 150 R 50 50 1 1 T +X GND 100 750 -2550 150 U 50 50 1 1 W +X D20 101 1350 550 150 L 50 50 1 1 B +X D21 102 1350 650 150 L 50 50 1 1 B +X D22 103 1350 750 150 L 50 50 1 1 B +X D23 104 1350 850 150 L 50 50 1 1 B +X Vcc 105 250 3400 150 D 50 50 1 1 W +X D24 106 1350 950 150 L 50 50 1 1 B +X D25 107 1350 1050 150 L 50 50 1 1 B +X D26 108 1350 1150 150 L 50 50 1 1 B +X D27 109 1350 1250 150 L 50 50 1 1 B +X GND 11 -450 -2550 150 U 50 50 1 1 W +X GND 110 850 -2550 150 U 50 50 1 1 W +X D28 111 1350 1350 150 L 50 50 1 1 B +X D29 112 1350 1450 150 L 50 50 1 1 B +X D30 113 1350 1550 150 L 50 50 1 1 B +X D31 114 1350 1650 150 L 50 50 1 1 B +X Vcc 115 350 3400 150 D 50 50 1 1 W +X Vcc 116 450 3400 150 D 50 50 1 1 W +X R~W~ 117 1350 1850 150 L 50 50 1 1 T +X ~ECS~ 118 1350 1950 150 L 50 50 1 1 T +X SIZ1 119 1350 2050 150 L 50 50 1 1 T +X FC0 12 -1350 2600 150 R 50 50 1 1 T +X SIZ0 120 1350 2150 150 L 50 50 1 1 T +X ~DBEN~ 121 1350 2250 150 L 50 50 1 1 O +X ~CIIN~ 122 1350 2350 150 L 50 50 1 1 I +X GND 123 950 -2550 150 U 50 50 1 1 W +X ~DS~ 124 1350 2450 150 L 50 50 1 1 T +X ~AS~ 125 1350 2550 150 L 50 50 1 1 T +X ~CBREQ~ 126 1350 2650 150 L 50 50 1 1 T +X ~CBACK~ 127 1350 2750 150 L 50 50 1 1 I +X Vcc 128 550 3400 150 D 50 50 1 1 W +X ~HALT~ 129 1350 2850 150 L 50 50 1 1 I +X ~RMC~ 13 -1350 2500 150 R 50 50 1 1 T +X ~BERR~ 130 1350 2950 150 L 50 50 1 1 I +X ~STERM~ 131 1350 3050 150 L 50 50 1 1 I +X ~DSACK~1 132 1350 3150 150 L 50 50 1 1 I +X ~OCS~ 14 -1350 2400 150 R 50 50 1 1 T +X ~CIOUT~ 15 -1350 2300 150 R 50 50 1 1 T +X ~BG~ 16 -1350 2200 150 R 50 50 1 1 O +X ~BGACK~ 17 -1350 2100 150 R 50 50 1 1 I +X Vcc 18 -350 3400 150 D 50 50 1 1 W +X GND 19 -350 -2550 150 U 50 50 1 1 W +X GND 2 -650 -2550 150 U 50 50 1 1 W +X ~BR~ 20 -1350 2000 150 R 50 50 1 1 I +X A0 21 -1350 1800 150 R 50 50 1 1 T +X A1 22 -1350 1700 150 R 50 50 1 1 T +X A31 23 -1350 1600 150 R 50 50 1 1 T +X A30 24 -1350 1500 150 R 50 50 1 1 T +X GND 25 -250 -2550 150 U 50 50 1 1 W +X A29 26 -1350 1400 150 R 50 50 1 1 T +X A28 27 -1350 1300 150 R 50 50 1 1 T +X A27 28 -1350 1200 150 R 50 50 1 1 T +X A26 29 -1350 1100 150 R 50 50 1 1 T +X ~DSACK~0 3 -1350 3100 150 R 50 50 1 1 I +X Vcc 30 -250 3400 150 D 50 50 1 1 W +X A25 31 -1350 1000 150 R 50 50 1 1 T +X A24 32 -1350 900 150 R 50 50 1 1 T +X A23 33 -1350 800 150 R 50 50 1 1 T +X A22 34 -1350 700 150 R 50 50 1 1 T +X GND 35 -150 -2550 150 U 50 50 1 1 W +X A21 36 -1350 600 150 R 50 50 1 1 T +X A20 37 -1350 500 150 R 50 50 1 1 T +X A19 38 -1350 400 150 R 50 50 1 1 T +X A18 39 -1350 300 150 R 50 50 1 1 T +X Vcc 4 -550 3400 150 D 50 50 1 1 W +X A17 40 -1350 200 150 R 50 50 1 1 T +X A16 41 -1350 100 150 R 50 50 1 1 T +X A15 42 -1350 0 150 R 50 50 1 1 T +X A14 43 -1350 -100 150 R 50 50 1 1 T +X GND 44 -50 -2550 150 U 50 50 1 1 W +X A13 45 -1350 -200 150 R 50 50 1 1 T +X A12 46 -1350 -300 150 R 50 50 1 1 T +X A11 47 -1350 -400 150 R 50 50 1 1 T +X A10 48 -1350 -500 150 R 50 50 1 1 T +X Vcc 49 -150 3400 150 D 50 50 1 1 W +X GND 5 -550 -2550 150 U 50 50 1 1 W +X A9 51 -1350 -600 150 R 50 50 1 1 T +X A8 52 -1350 -700 150 R 50 50 1 1 T +X A7 53 -1350 -800 150 R 50 50 1 1 T +X A6 54 -1350 -900 150 R 50 50 1 1 T +X A5 55 -1350 -1000 150 R 50 50 1 1 T +X A4 56 -1350 -1100 150 R 50 50 1 1 T +X GND 57 50 -2550 150 U 50 50 1 1 W +X A3 58 -1350 -1200 150 R 50 50 1 1 T +X A2 59 -1350 -1300 150 R 50 50 1 1 T +X CLK 6 -1350 3000 150 R 50 50 1 1 I +X GND 60 150 -2550 150 U 50 50 1 1 W +X ~IPEND~ 62 -1350 -1500 150 R 50 50 1 1 O +X Vcc 63 -50 3400 150 D 50 50 1 1 W +X ~RESET~ 64 -1350 -1600 150 R 50 50 1 1 C +X ~MMUDIS~ 65 -1350 -1700 150 R 50 50 1 1 I +X GND 66 250 -2550 150 U 50 50 1 1 W +X GND 67 350 -2550 150 U 50 50 1 1 W +X ~IPL~2 68 -1350 -1800 150 R 50 50 1 1 I +X ~IPL~1 69 -1350 -1900 150 R 50 50 1 1 I +X ~AVEC~ 7 -1350 2900 150 R 50 50 1 1 I +X ~IPL~0 70 -1350 -2000 150 R 50 50 1 1 I +X ~CDIS~ 71 -1350 -2100 150 R 50 50 1 1 I +X Vcc 72 50 3400 150 D 50 50 1 1 W +X ~REFILL~ 73 -1350 -2200 150 R 50 50 1 1 O +X ~STATUS~ 74 -1350 -2300 150 R 50 50 1 1 O +X D0 75 1350 -1450 150 L 50 50 1 1 B +X D1 76 1350 -1350 150 L 50 50 1 1 B +X GND 77 450 -2550 150 U 50 50 1 1 W +X D2 78 1350 -1250 150 L 50 50 1 1 B +X D3 79 1350 -1150 150 L 50 50 1 1 B +X Vcc 8 -450 3400 150 D 50 50 1 1 W +X D4 80 1350 -1050 150 L 50 50 1 1 B +X D5 81 1350 -950 150 L 50 50 1 1 B +X D6 82 1350 -850 150 L 50 50 1 1 B +X D7 83 1350 -750 150 L 50 50 1 1 B +X Vcc 85 150 3400 150 D 50 50 1 1 W +X D8 86 1350 -650 150 L 50 50 1 1 B +X D9 87 1350 -550 150 L 50 50 1 1 B +X D10 88 1350 -450 150 L 50 50 1 1 B +X D11 89 1350 -350 150 L 50 50 1 1 B +X FC2 9 -1350 2800 150 R 50 50 1 1 T +X GND 90 550 -2550 150 U 50 50 1 1 W +X D12 91 1350 -250 150 L 50 50 1 1 B +X D13 92 1350 -150 150 L 50 50 1 1 B +X D14 93 1350 -50 150 L 50 50 1 1 B +X D15 94 1350 50 150 L 50 50 1 1 B +X GND 95 650 -2550 150 U 50 50 1 1 W +X D16 96 1350 150 150 L 50 50 1 1 B +X D17 97 1350 250 150 L 50 50 1 1 B +X D18 98 1350 350 150 L 50 50 1 1 B +X D19 99 1350 450 150 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# GW_CPU_MC68882FN +# +DEF GW_CPU_MC68882FN U 0 40 Y Y 1 F N +F0 "U" 0 1200 50 H V C CNN +F1 "GW_CPU_MC68882FN" 0 1100 50 H V C CNN +F2 "stdpads:PLCC-68" -50 -900 40 H I C CNN +F3 "" -50 -900 50 H I C CNN +DRAW +S 750 -1650 -750 1650 0 1 10 f +X D2 1 900 -1350 150 L 50 50 1 1 B +X Vcc 10 -350 1800 150 D 50 50 1 1 W +X CLK 11 -900 1300 150 R 50 50 1 1 I +X GND 12 -150 -1800 150 U 50 50 1 1 W +X ~RESET~ 13 -900 -400 150 R 50 50 1 1 I +X GND 14 -50 -1800 150 U 50 50 1 1 W +X NC 15 -900 -1100 150 R 50 50 1 1 N +X Vcc 16 -250 1800 150 D 50 50 1 1 W +X Vcc 17 -150 1800 150 D 50 50 1 1 W +X SIZE 18 -900 -800 150 R 50 50 1 1 I +X GND 19 50 -1800 150 U 50 50 1 1 W +X D1 2 900 -1450 150 L 50 50 1 1 B +X ~DS~ 20 -900 1000 150 R 50 50 1 1 T +X ~AS~ 21 -900 1100 150 R 50 50 1 1 T +X A4 22 -900 600 150 R 50 50 1 1 T +X A3 23 -900 500 150 R 50 50 1 1 T +X A2 24 -900 400 150 R 50 50 1 1 T +X A1 25 -900 300 150 R 50 50 1 1 T +X A0 26 -900 100 150 R 50 50 1 1 T +X Vcc 27 -50 1800 150 D 50 50 1 1 W +X R~W~ 28 -900 800 150 R 50 50 1 1 T +X ~CS~ 29 -900 900 150 R 50 50 1 1 I +X D0 3 900 -1550 150 L 50 50 1 1 B +X GND 30 150 -1800 150 U 50 50 1 1 W +X ~DSACK~0 31 -900 -200 150 R 50 50 1 1 I +X ~DSACK~1 32 -900 -100 150 R 50 50 1 1 I +X D31 33 900 1550 150 L 50 50 1 1 B +X D30 34 900 1450 150 L 50 50 1 1 B +X D29 35 900 1350 150 L 50 50 1 1 B +X D28 36 900 1250 150 L 50 50 1 1 B +X D27 37 900 1150 150 L 50 50 1 1 B +X D26 38 900 1050 150 L 50 50 1 1 B +X D25 39 900 950 150 L 50 50 1 1 B +X ~SENSE~ 4 -900 -600 150 R 50 50 1 1 C +X D24 40 900 850 150 L 50 50 1 1 B +X GND 41 250 -1800 150 U 50 50 1 1 W +X D23 42 900 750 150 L 50 50 1 1 B +X Vcc 43 50 1800 150 D 50 50 1 1 W +X D22 44 900 650 150 L 50 50 1 1 B +X D21 45 900 550 150 L 50 50 1 1 B +X D20 46 900 450 150 L 50 50 1 1 B +X D19 47 900 350 150 L 50 50 1 1 B +X D18 48 900 250 150 L 50 50 1 1 B +X D17 49 900 150 150 L 50 50 1 1 B +X GND 5 -650 -1800 150 U 50 50 1 1 W +X D16 50 900 50 150 L 50 50 1 1 B +X GND 51 350 -1800 150 U 50 50 1 1 W +X Vcc 52 150 1800 150 D 50 50 1 1 W +X Vcc 53 250 1800 150 D 50 50 1 1 W +X D15 54 900 -50 150 L 50 50 1 1 B +X D14 55 900 -150 150 L 50 50 1 1 B +X D13 56 900 -250 150 L 50 50 1 1 B +X D12 57 900 -350 150 L 50 50 1 1 B +X D11 58 900 -450 150 L 50 50 1 1 B +X D10 59 900 -550 150 L 50 50 1 1 B +X GND 6 -550 -1800 150 U 50 50 1 1 W +X D9 60 900 -650 150 L 50 50 1 1 B +X Vcc 61 350 1800 150 D 50 50 1 1 W +X D8 62 900 -750 150 L 50 50 1 1 B +X GND 63 450 -1800 150 U 50 50 1 1 W +X D7 64 900 -850 150 L 50 50 1 1 B +X D6 65 900 -950 150 L 50 50 1 1 B +X D5 66 900 -1050 150 L 50 50 1 1 B +X D4 67 900 -1150 150 L 50 50 1 1 B +X D3 68 900 -1250 150 L 50 50 1 1 B +X GND 7 -450 -1800 150 U 50 50 1 1 W +X GND 8 -350 -1800 150 U 50 50 1 1 W +X GND 9 -250 -1800 150 U 50 50 1 1 W +ENDDRAW +ENDDEF +# +# GW_Logic_741G125GW +# +DEF GW_Logic_741G125GW U 0 40 Y Y 1 F N +F0 "U" 0 250 50 H V C CNN +F1 "GW_Logic_741G125GW" 0 -250 50 H V C CNN +F2 "stdpads:SOT-353" 0 -300 50 H I C TNN +F3 "" 0 -200 60 H I C CNN +DRAW +S 200 -200 -200 200 0 1 10 f +X ~OE~ 1 -400 100 200 R 50 50 1 1 I +X A 2 -400 0 200 R 50 50 1 1 I +X GND 3 -400 -100 200 R 50 50 1 1 W +X Y 4 400 -100 200 L 50 50 1 1 O +X Vcc 5 400 100 200 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# GW_Logic_74244 +# +DEF GW_Logic_74244 U 0 40 Y Y 1 F N +F0 "U" 0 600 50 H V C CNN +F1 "GW_Logic_74244" 0 -600 50 H V C CNN +F2 "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" 0 -650 50 H I C TNN +F3 "" 0 100 60 H I C CNN +DRAW +S -200 550 200 -550 0 1 10 f +X 1~OE~ 1 400 450 200 L 50 50 1 1 I +X GND 10 -400 -450 200 R 50 50 1 1 W +X 2A3 11 400 -350 200 L 50 50 1 1 I +X 1Y3 12 -400 350 200 R 50 50 1 1 T +X 2A2 13 400 -250 200 L 50 50 1 1 I +X 1Y2 14 -400 250 200 R 50 50 1 1 T +X 2A1 15 400 -150 200 L 50 50 1 1 I +X 1Y1 16 -400 150 200 R 50 50 1 1 T +X 2A0 17 400 -50 200 L 50 50 1 1 I +X 1Y0 18 -400 50 200 R 50 50 1 1 T +X 2~OE~ 19 400 -450 200 L 50 50 1 1 I +X 1A0 2 400 350 200 L 50 50 1 1 I +X Vcc 20 -400 450 200 R 50 50 1 1 W +X 2Y0 3 -400 -50 200 R 50 50 1 1 T +X 1A1 4 400 250 200 L 50 50 1 1 I +X 2Y1 5 -400 -150 200 R 50 50 1 1 T +X 1A2 6 400 150 200 L 50 50 1 1 I +X 2Y2 7 -400 -250 200 R 50 50 1 1 T +X 1A3 8 400 50 200 L 50 50 1 1 I +X 2Y3 9 -400 -350 200 R 50 50 1 1 T +ENDDRAW +ENDDEF +# +# GW_Logic_74245 +# +DEF GW_Logic_74245 U 0 40 Y Y 1 F N +F0 "U" 0 600 50 H V C CNN +F1 "GW_Logic_74245" 0 -600 50 H V C CNN +F2 "" 0 -650 50 H I C TNN +F3 "" 0 100 60 H I C CNN +DRAW +S -200 550 200 -550 0 1 10 f +X AtoB 1 -400 450 200 R 50 50 1 1 I +X GND 10 -400 -450 200 R 50 50 1 1 W +X B7 11 400 -450 200 L 50 50 1 1 B +X B6 12 400 -350 200 L 50 50 1 1 B +X B5 13 400 -250 200 L 50 50 1 1 B +X B4 14 400 -150 200 L 50 50 1 1 B +X B3 15 400 -50 200 L 50 50 1 1 B +X B2 16 400 50 200 L 50 50 1 1 B +X B1 17 400 150 200 L 50 50 1 1 B +X B0 18 400 250 200 L 50 50 1 1 B +X ~OE~ 19 400 350 200 L 50 50 1 1 I +X A0 2 -400 350 200 R 50 50 1 1 B +X Vcc 20 400 450 200 L 50 50 1 1 W +X A1 3 -400 250 200 R 50 50 1 1 B +X A2 4 -400 150 200 R 50 50 1 1 B +X A3 5 -400 50 200 R 50 50 1 1 B +X A4 6 -400 -50 200 R 50 50 1 1 B +X A5 7 -400 -150 200 R 50 50 1 1 B +X A6 8 -400 -250 200 R 50 50 1 1 B +X A7 9 -400 -350 200 R 50 50 1 1 B +ENDDRAW +ENDDEF +# +# GW_Logic_74573 +# +DEF GW_Logic_74573 U 0 40 Y Y 1 F N +F0 "U" 0 600 50 H V C CNN +F1 "GW_Logic_74573" 0 -600 50 H V C CNN +F2 "" 0 -650 50 H I C TNN +F3 "" 0 100 60 H I C CNN +DRAW +S -200 550 200 -550 0 1 10 f +X ~OE~ 1 -400 450 200 R 50 50 1 1 I +X GND 10 -400 -450 200 R 50 50 1 1 W +X ~LE~ 11 400 -450 200 L 50 50 1 1 I +X Q7 12 400 -350 200 L 50 50 1 1 T +X Q6 13 400 -250 200 L 50 50 1 1 T +X Q5 14 400 -150 200 L 50 50 1 1 T +X Q4 15 400 -50 200 L 50 50 1 1 T +X Q3 16 400 50 200 L 50 50 1 1 T +X Q2 17 400 150 200 L 50 50 1 1 T +X Q1 18 400 250 200 L 50 50 1 1 T +X Q0 19 400 350 200 L 50 50 1 1 T +X D0 2 -400 350 200 R 50 50 1 1 I +X Vcc 20 400 450 200 L 50 50 1 1 W +X D1 3 -400 250 200 R 50 50 1 1 I +X D2 4 -400 150 200 R 50 50 1 1 I +X D3 5 -400 50 200 R 50 50 1 1 I +X D4 6 -400 -50 200 R 50 50 1 1 I +X D5 7 -400 -150 200 R 50 50 1 1 I +X D6 8 -400 -250 200 R 50 50 1 1 I +X D7 9 -400 -350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# GW_Logic_Oscillator_4P +# +DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N +F0 "U" 0 250 50 H V C CNN +F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -250 200 250 -100 0 1 10 f +X EN 1 -350 100 100 R 50 50 1 1 I +X GND 2 -350 0 100 R 50 50 1 1 W +X Output 3 350 0 100 L 50 50 1 1 O +X Vdd 4 350 100 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# GW_RAM_SDRAM-16Mx16-TSOP2-54 +# +DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N +F0 "U" 0 1150 50 H V C CNN +F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN +F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN +F3 "" 0 -250 50 H I C CNN +DRAW +S -300 1100 300 -1400 0 1 10 f +X VDD 1 -500 1000 200 R 50 50 1 1 W +X DQ5 10 500 500 200 L 50 50 1 1 B +X DQ6 11 500 400 200 L 50 50 1 1 B +X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N +X DQ7 13 500 300 200 L 50 50 1 1 B +X VDD 14 -500 1000 200 R 50 50 1 1 W N +X DQML 15 500 -600 200 L 50 50 1 1 I +X ~WE~ 16 500 -1100 200 L 50 50 1 1 I +X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I +X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I +X ~CS~ 19 500 -1000 200 L 50 50 1 1 I +X DQ0 2 500 1000 200 L 50 50 1 1 B +X BA0 20 -500 -600 200 R 50 50 1 1 I +X BA1 21 -500 -700 200 R 50 50 1 1 I +X A10 22 -500 -300 200 R 50 50 1 1 I +X A0 23 -500 700 200 R 50 50 1 1 I +X A1 24 -500 600 200 R 50 50 1 1 I +X A2 25 -500 500 200 R 50 50 1 1 I +X A3 26 -500 400 200 R 50 50 1 1 I +X VDD 27 -500 1000 200 R 50 50 1 1 W N +X VSS 28 -500 -1200 200 R 50 50 1 1 W +X A4 29 -500 300 200 R 50 50 1 1 I +X VDDQ 3 -500 900 200 R 50 50 1 1 W +X A5 30 -500 200 200 R 50 50 1 1 I +X A6 31 -500 100 200 R 50 50 1 1 I +X A7 32 -500 0 200 R 50 50 1 1 I +X A8 33 -500 -100 200 R 50 50 1 1 I +X A9 34 -500 -200 200 R 50 50 1 1 I +X A11 35 -500 -400 200 R 50 50 1 1 I +X A12 36 -500 -500 200 R 50 50 1 1 I +X CKE 37 -500 -900 200 R 50 50 1 1 I +X CLK 38 -500 -1000 200 R 50 50 1 1 I +X DQMH 39 500 -700 200 L 50 50 1 1 I +X DQ1 4 500 900 200 L 50 50 1 1 B +X VSS 41 -500 -1200 200 R 50 50 1 1 W N +X DQ8 42 500 200 200 L 50 50 1 1 B +X VDDQ 43 -500 900 200 R 50 50 1 1 W N +X DQ9 44 500 100 200 L 50 50 1 1 B +X DQ10 45 500 0 200 L 50 50 1 1 B +X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N +X DQ11 47 500 -100 200 L 50 50 1 1 B +X DQ12 48 500 -200 200 L 50 50 1 1 B +X VDDQ 49 -500 900 200 R 50 50 1 1 W N +X DQ2 5 500 800 200 L 50 50 1 1 B +X DQ13 50 500 -300 200 L 50 50 1 1 B +X DQ14 51 500 -400 200 L 50 50 1 1 B +X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N +X DQ15 53 500 -500 200 L 50 50 1 1 B +X VSS 54 -500 -1200 200 R 50 50 1 1 W N +X VSSQ 6 -500 -1300 200 R 50 50 1 1 W +X DQ3 7 500 700 200 L 50 50 1 1 B +X DQ4 8 500 600 200 L 50 50 1 1 B +X VDDQ 9 -500 900 200 R 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Mechanical_Fiducial +# +DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N +F0 "FID" 0 200 50 H V C CNN +F1 "Mechanical_Fiducial" 0 125 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Fiducial* +$ENDFPLIST +DRAW +C 0 0 50 0 1 20 f +ENDDRAW +ENDDEF +# +# Mechanical_MountingHole_Pad +# +DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N +F0 "H" 0 250 50 H V C CNN +F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + MountingHole*Pad* +$ENDFPLIST +DRAW +C 0 50 50 0 1 50 N +X 1 1 0 -100 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# power_+12V +# +DEF power_+12V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+12V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +12V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_+1V2 +# +DEF power_+1V2 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+1V2" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +1V2 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_+3V3 +# +DEF power_+3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+3V3" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS +3.3V +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_+5V +# +DEF power_+5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+5V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_-12V +# +DEF power_-12V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 100 50 H I C CNN +F1 "power_-12V" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F +X -12V 1 0 0 0 U 50 50 0 0 W N +ENDDRAW +ENDDEF +# +# power_-5V +# +DEF power_-5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 100 50 H I C CNN +F1 "power_-5V" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F +X -5V 1 0 0 0 U 50 50 0 0 W N +ENDDRAW +ENDDEF +# +# power_GND +# +DEF power_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/SE-030.kicad_pcb b/SE-030.kicad_pcb new file mode 100644 index 0000000..f3afb30 --- /dev/null +++ b/SE-030.kicad_pcb @@ -0,0 +1,13378 @@ +(kicad_pcb (version 20171130) (host pcbnew "(5.1.10-1-10_14)") + + (general + (thickness 1.6) + (drawings 8) + (tracks 4066) + (zones 0) + (modules 165) + (nets 561) + ) + + (page A4) + (layers + (0 F.Cu signal) + (1 In1.Cu power) + (2 In2.Cu power) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.15) + (user_trace_width 0.2) + (user_trace_width 0.25) + (user_trace_width 0.3) + (user_trace_width 0.35) + (user_trace_width 0.4) + (user_trace_width 0.45) + (user_trace_width 0.5) + (user_trace_width 0.55) + (user_trace_width 0.6) + (user_trace_width 0.8) + (user_trace_width 1) + (user_trace_width 1.27) + (user_trace_width 1.524) + (trace_clearance 0.15) + (zone_clearance 0.1524) + (zone_45_only no) + (trace_min 0.15) + (via_size 0.5) + (via_drill 0.2) + (via_min_size 0.5) + (via_min_drill 0.2) + (user_via 0.6 0.3) + (user_via 0.8 0.4) + (user_via 1 0.5) + (user_via 1.524 0.762) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.15) + (segment_width 0.1524) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 0.7 0.95) + (pad_drill 0) + (pad_to_mask_clearance 0.0762) + (solder_mask_min_width 0.1) + (pad_to_paste_clearance -0.0381) + (aux_axis_origin 0 0) + (visible_elements FFFFF77F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 +5V) + (net 2 GND) + (net 3 +3V3) + (net 4 /MC68k/A0) + (net 5 /MC68k/A1) + (net 6 /MC68k/A31) + (net 7 /MC68k/A30) + (net 8 /MC68k/A29) + (net 9 /MC68k/A28) + (net 10 /MC68k/A27) + (net 11 /MC68k/A26) + (net 12 /MC68k/A25) + (net 13 /MC68k/A24) + (net 14 /MC68k/A23) + (net 15 /MC68k/A22) + (net 16 /MC68k/A21) + (net 17 /MC68k/A20) + (net 18 /MC68k/A19) + (net 19 /MC68k/A18) + (net 20 /MC68k/A17) + (net 21 /MC68k/A16) + (net 22 /MC68k/A15) + (net 23 /MC68k/A14) + (net 24 /MC68k/A13) + (net 25 /MC68k/A12) + (net 26 /MC68k/A11) + (net 27 /MC68k/A10) + (net 28 /CPUBuf.sch/CPU_D15) + (net 29 /MC68k/A9) + (net 30 /MC68k/A8) + (net 31 /MC68k/A7) + (net 32 /MC68k/A6) + (net 33 /MC68k/A5) + (net 34 /MC68k/A4) + (net 35 /MC68k/A3) + (net 36 /MC68k/A2) + (net 37 "Net-(U1-Pad62)") + (net 38 /PDSBuf/IOB_~RESET~) + (net 39 /MC68k/~IPL~2) + (net 40 /MC68k/~IPL~1) + (net 41 /MC68k/~IPL~0) + (net 42 "Net-(U1-Pad73)") + (net 43 "Net-(U1-Pad74)") + (net 44 /CPUBuf.sch/CPU_D0) + (net 45 "Net-(U1-Pad121)") + (net 46 /Control/CPU_~CIIN~) + (net 47 /Control/CPU_~CBACK~) + (net 48 /Control/CPU_~HALT~) + (net 49 /Control/CPU_~BERR~) + (net 50 /Control/CPU_~STERM~) + (net 51 /Control/CPUCLK) + (net 52 "Net-(U1-Pad14)") + (net 53 "Net-(U1-Pad16)") + (net 54 /Control/FPU~CS~) + (net 55 "Net-(U2-Pad15)") + (net 56 /Control/FPUCLK) + (net 57 "Net-(U2-Pad4)") + (net 58 "Net-(U3-PadA2)") + (net 59 "Net-(U3-PadA3)") + (net 60 "Net-(U3-PadA4)") + (net 61 "Net-(U3-PadA5)") + (net 62 "Net-(U3-PadA6)") + (net 63 "Net-(U3-PadA7)") + (net 64 "Net-(U3-PadA8)") + (net 65 "Net-(U3-PadA9)") + (net 66 "Net-(U3-PadA10)") + (net 67 "Net-(U3-PadA11)") + (net 68 "Net-(U3-PadA12)") + (net 69 "Net-(U3-PadA13)") + (net 70 "Net-(U3-PadA14)") + (net 71 "Net-(U3-PadA15)") + (net 72 "Net-(U3-PadB1)") + (net 73 "Net-(U3-PadC1)") + (net 74 "Net-(U3-PadD1)") + (net 75 "Net-(U3-PadE1)") + (net 76 "Net-(U3-PadF1)") + (net 77 "Net-(U3-PadG1)") + (net 78 "Net-(U3-PadH1)") + (net 79 "Net-(U3-PadJ1)") + (net 80 "Net-(U3-PadB16)") + (net 81 "Net-(U3-PadB15)") + (net 82 "Net-(U3-PadB14)") + (net 83 "Net-(U3-PadB12)") + (net 84 "Net-(U3-PadB10)") + (net 85 "Net-(U3-PadB8)") + (net 86 "Net-(U3-PadB6)") + (net 87 "Net-(U3-PadB5)") + (net 88 "Net-(U3-PadB2)") + (net 89 "Net-(U3-PadB3)") + (net 90 "Net-(U3-PadC2)") + (net 91 "Net-(U3-PadC3)") + (net 92 "Net-(U3-PadC5)") + (net 93 "Net-(U3-PadC6)") + (net 94 "Net-(U3-PadC7)") + (net 95 "Net-(U3-PadC8)") + (net 96 "Net-(U3-PadC9)") + (net 97 "Net-(U3-PadD3)") + (net 98 "Net-(U3-PadD5)") + (net 99 "Net-(U3-PadD6)") + (net 100 "Net-(U3-PadD8)") + (net 101 "Net-(U3-PadD9)") + (net 102 "Net-(U3-PadE2)") + (net 103 "Net-(U3-PadE3)") + (net 104 "Net-(U3-PadE4)") + (net 105 "Net-(U3-PadC10)") + (net 106 "Net-(U3-PadC11)") + (net 107 "Net-(U3-PadD11)") + (net 108 "Net-(U3-PadD12)") + (net 109 "Net-(U3-PadC12)") + (net 110 "Net-(U3-PadC13)") + (net 111 "Net-(U3-PadC14)") + (net 112 "Net-(U3-PadD14)") + (net 113 "Net-(U3-PadC15)") + (net 114 "Net-(U3-PadD16)") + (net 115 "Net-(U3-PadC16)") + (net 116 "Net-(U3-PadE13)") + (net 117 "Net-(U3-PadF13)") + (net 118 "Net-(U3-PadG14)") + (net 119 "Net-(U3-PadF14)") + (net 120 "Net-(U3-PadE14)") + (net 121 "Net-(U3-PadE15)") + (net 122 "Net-(U3-PadF15)") + (net 123 "Net-(U3-PadG16)") + (net 124 "Net-(U3-PadF16)") + (net 125 "Net-(U3-PadE16)") + (net 126 "Net-(U3-PadF2)") + (net 127 "Net-(U3-PadF3)") + (net 128 "Net-(U3-PadF4)") + (net 129 "Net-(U3-PadG3)") + (net 130 "Net-(U3-PadH2)") + (net 131 "Net-(U3-PadH3)") + (net 132 "Net-(U3-PadH4)") + (net 133 "Net-(U3-PadJ4)") + (net 134 "Net-(U3-PadJ3)") + (net 135 "Net-(U3-PadK1)") + (net 136 "Net-(U3-PadK2)") + (net 137 "Net-(U3-PadK3)") + (net 138 "Net-(U3-PadL4)") + (net 139 "Net-(U3-PadL3)") + (net 140 "Net-(U3-PadL1)") + (net 141 "Net-(U3-PadM1)") + (net 142 "Net-(U3-PadM2)") + (net 143 "Net-(U3-PadM3)") + (net 144 "Net-(U3-PadM4)") + (net 145 "Net-(U3-PadN4)") + (net 146 "Net-(U3-PadP4)") + (net 147 "Net-(U3-PadN3)") + (net 148 "Net-(U3-PadP2)") + (net 149 "Net-(U3-PadR2)") + (net 150 "Net-(U3-PadN1)") + (net 151 "Net-(U3-PadP1)") + (net 152 "Net-(U3-PadR1)") + (net 153 "Net-(U3-PadT4)") + (net 154 "Net-(U3-PadE8)") + (net 155 "Net-(U3-PadE7)") + (net 156 "Net-(U3-PadE6)") + (net 157 "Net-(U3-PadF5)") + (net 158 "Net-(U3-PadF6)") + (net 159 "Net-(U3-PadF7)") + (net 160 "Net-(U3-PadG5)") + (net 161 "Net-(U3-PadG6)") + (net 162 "Net-(U3-PadH5)") + (net 163 "Net-(U3-PadJ6)") + (net 164 "Net-(U3-PadK5)") + (net 165 "Net-(U3-PadK6)") + (net 166 "Net-(U3-PadL5)") + (net 167 "Net-(U3-PadL7)") + (net 168 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279 /RAM/D16) + (net 280 /RAM/D17) + (net 281 /RAM/D18) + (net 282 /RAM/D19) + (net 283 /RAM/D20) + (net 284 /RAM/D21) + (net 285 /RAM/D22) + (net 286 /RAM/D23) + (net 287 /RAM/DQM2) + (net 288 /RAM/CLK23) + (net 289 /RAM/DQM3) + (net 290 /RAM/D24) + (net 291 /RAM/D25) + (net 292 /RAM/D26) + (net 293 /RAM/D27) + (net 294 /RAM/D28) + (net 295 /RAM/D29) + (net 296 /RAM/D30) + (net 297 /RAM/D31) + (net 298 /PDSBuf/IOB_SIZ1) + (net 299 /PDSBuf/IOB_SIZ0) + (net 300 /PDS/A3) + (net 301 /PDS/A2) + (net 302 /PDS/A1) + (net 303 /PDS/A0) + (net 304 /PDSBuf/IOB_~AS~) + (net 305 /PDSBuf/IOB_~DS~) + (net 306 /Control/IOC_~DS~) + (net 307 /Control/IOC_~AS~) + (net 308 /PDSBuf/IOC_A0) + (net 309 /PDSBuf/IOC_A1) + (net 310 /PDSBuf/IOC_A2) + (net 311 /PDSBuf/IOC_A3) + (net 312 /PDSBuf/IOC_SIZ0) + (net 313 /PDSBuf/IOC_SIZ1) + (net 314 /PDSBuf/A~OE~) + (net 315 /PDSBuf/ADoutLE) + (net 316 /PDS/A24) + (net 317 /PDS/A25) + (net 318 /PDS/A26) + (net 319 /PDS/A27) + (net 320 /PDS/A30) + (net 321 /PDS/A31) + (net 322 /PDSBuf/IOB_R~W~) + (net 323 "Net-(U9-Pad19)") + (net 324 /PDS/A16) + (net 325 /PDS/A17) + (net 326 /PDS/A18) + (net 327 /PDS/A19) + (net 328 /PDS/A20) + (net 329 /PDS/A21) + (net 330 /PDS/A22) + (net 331 /PDS/A23) + (net 332 /PDS/A8) + (net 333 /PDS/A9) + (net 334 /PDS/A10) + (net 335 /PDS/A11) + (net 336 /PDS/A12) + (net 337 /PDS/A13) + (net 338 /PDS/A14) + (net 339 /PDS/A15) + (net 340 /PDS/A7) + (net 341 /PDS/A6) + (net 342 /PDS/A5) + (net 343 /PDS/A4) + (net 344 /PDSBuf/IOB_~RMC~) + (net 345 /PDSBuf/IOB_FC2) + (net 346 /PDSBuf/IOB_FC1) + (net 347 /PDSBuf/IOB_FC0) + (net 348 /Control/IOB_~DSACK~0) + (net 349 /PDSBuf/IOB_~DSACK~1) + (net 350 /Control/IOB_~HALT~) + (net 351 /PDS/C16M) + (net 352 /Control/IOB_~BERR~) + (net 353 /PDSBuf/FSB_~RESET~) + (net 354 "Net-(U13-Pad9)") + (net 355 /PDSBuf/IOB_~DSACK~0) + (net 356 "Net-(U13-Pad7)") + (net 357 /PDSBuf/IOB_~HALT~) + (net 358 /Control/IOB_C16M) + (net 359 /PDSBuf/IOB_~BERR~) + (net 360 /Control/IOB_~DSACK~1) + (net 361 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512 "Net-(U3-PadT10)") + (net 513 "Net-(U3-PadP12)") + (net 514 "Net-(U3-PadN12)") + (net 515 /CPUBuf/FSB_A24) + (net 516 /CPUBuf/FSB_A25) + (net 517 /CPUBuf/FSB_A26) + (net 518 /CPUBuf/FSB_A27) + (net 519 /CPUBuf/FSB_A30) + (net 520 /CPUBuf/FSB_A31) + (net 521 /CPUBuf/FSB_R~W~) + (net 522 /CPUBuf/FSB_A23) + (net 523 /CPUBuf/FSB_A22) + (net 524 /CPUBuf/FSB_A21) + (net 525 /CPUBuf/FSB_A20) + (net 526 /CPUBuf/FSB_A19) + (net 527 /CPUBuf/FSB_A18) + (net 528 /CPUBuf/FSB_A17) + (net 529 /CPUBuf/FSB_A16) + (net 530 /CPUBuf/FSB_A8) + (net 531 /CPUBuf/FSB_A9) + (net 532 /CPUBuf/FSB_A10) + (net 533 /CPUBuf/FSB_A11) + (net 534 /CPUBuf/FSB_A12) + (net 535 /CPUBuf/FSB_A13) + (net 536 /CPUBuf/FSB_A14) + (net 537 /CPUBuf/FSB_A15) + (net 538 /CPUBuf/FSB_FC0) + (net 539 /CPUBuf/FSB_FC1) + (net 540 /CPUBuf/FSB_FC2) + (net 541 /CPUBuf/FSB_A4) + (net 542 /CPUBuf/FSB_A5) + (net 543 /CPUBuf/FSB_A6) + (net 544 /CPUBuf/FSB_A7) + (net 545 /CPUBuf/A~OE~) + (net 546 /CPUBuf/FSB_A3) + (net 547 /CPUBuf/FSB_A2) + (net 548 /CPUBuf/FSB_A1) + (net 549 /CPUBuf/FSB_A0) + (net 550 /CPUBuf/FSB_A28) + (net 551 /CPUBuf/FSB_A29) + (net 552 /CPUBuf/DSACK~OE~) + (net 553 /CPUBuf/FSB_~CIOUT~) + (net 554 /CPUBuf/FSB_SIZ0) + (net 555 /CPUBuf/FSB_SIZ1) + (net 556 /CPUBuf/FSB_~AS~) + (net 557 /CPUBuf/FSB_~CBREQ~) + (net 558 /CPUBuf/FSB_~DS~) + (net 559 /CPUBuf/FSB_~ECS~) + (net 560 /CPUBuf/FSB_~RMC~) + + (net_class Default "This is the default net class." + (clearance 0.15) + (trace_width 0.15) + (via_dia 0.5) + (via_drill 0.2) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +12V) + (add_net +1V2) + (add_net +3V3) + (add_net +5V) + (add_net -12V) + (add_net -5V) + (add_net /CPUBuf.sch/CPU_D0) + (add_net /CPUBuf.sch/CPU_D15) + (add_net /CPUBuf/A~OE~) + (add_net /CPUBuf/CPU_D0) + (add_net /CPUBuf/CPU_D1) + (add_net /CPUBuf/CPU_D10) + (add_net /CPUBuf/CPU_D11) + (add_net /CPUBuf/CPU_D12) + (add_net /CPUBuf/CPU_D13) + (add_net /CPUBuf/CPU_D14) + (add_net /CPUBuf/CPU_D15) + (add_net /CPUBuf/CPU_D16) + (add_net /CPUBuf/CPU_D17) + (add_net /CPUBuf/CPU_D18) + (add_net /CPUBuf/CPU_D19) + (add_net /CPUBuf/CPU_D2) + (add_net /CPUBuf/CPU_D20) + (add_net /CPUBuf/CPU_D21) + (add_net /CPUBuf/CPU_D22) + (add_net /CPUBuf/CPU_D23) + (add_net /CPUBuf/CPU_D24) + (add_net /CPUBuf/CPU_D25) + (add_net /CPUBuf/CPU_D26) + (add_net /CPUBuf/CPU_D27) + (add_net /CPUBuf/CPU_D28) + (add_net /CPUBuf/CPU_D29) + (add_net /CPUBuf/CPU_D3) + (add_net /CPUBuf/CPU_D30) + (add_net /CPUBuf/CPU_D31) + (add_net /CPUBuf/CPU_D4) + (add_net /CPUBuf/CPU_D5) + (add_net /CPUBuf/CPU_D6) + (add_net /CPUBuf/CPU_D7) + (add_net /CPUBuf/CPU_D8) + (add_net /CPUBuf/CPU_D9) + (add_net /CPUBuf/CPU_FC0) + (add_net /CPUBuf/CPU_FC1) + (add_net /CPUBuf/CPU_FC2) + (add_net /CPUBuf/CPU_R~W~) + (add_net /CPUBuf/CPU_SIZ0) + (add_net /CPUBuf/CPU_SIZ1) + (add_net /CPUBuf/CPU_~AS~) + (add_net /CPUBuf/CPU_~CBREQ~) + (add_net /CPUBuf/CPU_~CIOUT~) + (add_net /CPUBuf/CPU_~DSACK~0) + (add_net /CPUBuf/CPU_~DSACK~1) + (add_net /CPUBuf/CPU_~DS~) + (add_net /CPUBuf/CPU_~ECS~) + (add_net /CPUBuf/CPU_~RMC~) + (add_net /CPUBuf/DSACK~OE~) + (add_net /CPUBuf/FSB_A0) + (add_net /CPUBuf/FSB_A1) + (add_net /CPUBuf/FSB_A10) + (add_net /CPUBuf/FSB_A11) + (add_net /CPUBuf/FSB_A12) + (add_net /CPUBuf/FSB_A13) + (add_net /CPUBuf/FSB_A14) + (add_net /CPUBuf/FSB_A15) + (add_net /CPUBuf/FSB_A16) + (add_net /CPUBuf/FSB_A17) + (add_net /CPUBuf/FSB_A18) + (add_net /CPUBuf/FSB_A19) + (add_net /CPUBuf/FSB_A2) + (add_net /CPUBuf/FSB_A20) + (add_net /CPUBuf/FSB_A21) + (add_net /CPUBuf/FSB_A22) + (add_net /CPUBuf/FSB_A23) + (add_net /CPUBuf/FSB_A24) + (add_net /CPUBuf/FSB_A25) + (add_net /CPUBuf/FSB_A26) + (add_net /CPUBuf/FSB_A27) + (add_net /CPUBuf/FSB_A28) + (add_net /CPUBuf/FSB_A29) + (add_net /CPUBuf/FSB_A3) + (add_net /CPUBuf/FSB_A30) + (add_net /CPUBuf/FSB_A31) + (add_net /CPUBuf/FSB_A4) + (add_net /CPUBuf/FSB_A5) + (add_net /CPUBuf/FSB_A6) + (add_net /CPUBuf/FSB_A7) + (add_net /CPUBuf/FSB_A8) + (add_net /CPUBuf/FSB_A9) + (add_net /CPUBuf/FSB_FC0) + (add_net /CPUBuf/FSB_FC1) + (add_net /CPUBuf/FSB_FC2) + (add_net /CPUBuf/FSB_R~W~) + (add_net /CPUBuf/FSB_SIZ0) + (add_net /CPUBuf/FSB_SIZ1) + (add_net /CPUBuf/FSB_~AS~) + (add_net /CPUBuf/FSB_~CBREQ~) + (add_net /CPUBuf/FSB_~CIOUT~) + (add_net /CPUBuf/FSB_~DS~) + (add_net /CPUBuf/FSB_~ECS~) + (add_net /CPUBuf/FSB_~RMC~) + (add_net /Control/CCLK_SCK) + (add_net /Control/CPUCLK) + (add_net /Control/CPU_DDIR) + (add_net /Control/CPU_D~OE~) + (add_net /Control/CPU_~BERR~) + (add_net /Control/CPU_~CBACK~) + (add_net /Control/CPU_~CIIN~) + (add_net /Control/CPU_~DSACK~0) + (add_net /Control/CPU_~DSACK~1) + (add_net /Control/CPU_~HALT~) + (add_net /Control/CPU_~STERM~) + (add_net /Control/DONE) + (add_net /Control/FPUCLK) + (add_net /Control/FPU~CS~) + (add_net /Control/HSWAPEN) + (add_net /Control/IOB_C16M) + (add_net /Control/IOB_~BERR~) + (add_net /Control/IOB_~DSACK~0) + (add_net /Control/IOB_~DSACK~1) + (add_net /Control/IOB_~HALT~) + (add_net /Control/IOC_~AS~) + (add_net /Control/IOC_~DS~) + (add_net /Control/M0) + (add_net /Control/M1) + (add_net /Control/MOSI_DIN) + (add_net /Control/RAM_~CAS~) + (add_net /Control/RAM_~CS~) + (add_net /Control/RAM_~RAS~) + (add_net /Control/RAM_~WE~) + (add_net /Control/RESET~OE~) + (add_net /Control/~INIT~) + (add_net /Control/~PROG~) + (add_net /MC68k/A0) + (add_net /MC68k/A1) + (add_net /MC68k/A10) + (add_net /MC68k/A11) + (add_net /MC68k/A12) + (add_net /MC68k/A13) + (add_net /MC68k/A14) + (add_net /MC68k/A15) + (add_net /MC68k/A16) + (add_net /MC68k/A17) + (add_net /MC68k/A18) + (add_net /MC68k/A19) + (add_net /MC68k/A2) + (add_net /MC68k/A20) + (add_net /MC68k/A21) + (add_net /MC68k/A22) + (add_net /MC68k/A23) + (add_net /MC68k/A24) + (add_net /MC68k/A25) + (add_net /MC68k/A26) + (add_net /MC68k/A27) + (add_net /MC68k/A28) + (add_net /MC68k/A29) + (add_net /MC68k/A3) + (add_net /MC68k/A30) + (add_net /MC68k/A31) + (add_net /MC68k/A4) + (add_net /MC68k/A5) + (add_net /MC68k/A6) + (add_net /MC68k/A7) + (add_net /MC68k/A8) + (add_net /MC68k/A9) + (add_net /MC68k/~IPL~0) + (add_net /MC68k/~IPL~1) + (add_net /MC68k/~IPL~2) + (add_net /PDS/A0) + (add_net /PDS/A1) + (add_net /PDS/A10) + (add_net /PDS/A11) + (add_net /PDS/A12) + (add_net /PDS/A13) + (add_net /PDS/A14) + (add_net /PDS/A15) + (add_net /PDS/A16) + (add_net /PDS/A17) + (add_net /PDS/A18) + (add_net /PDS/A19) + (add_net /PDS/A2) + (add_net /PDS/A20) + (add_net /PDS/A21) + (add_net /PDS/A22) + (add_net /PDS/A23) + (add_net /PDS/A24) + (add_net /PDS/A25) + (add_net /PDS/A26) + (add_net /PDS/A27) + (add_net /PDS/A3) + (add_net /PDS/A30) + (add_net /PDS/A31) + (add_net /PDS/A4) + (add_net /PDS/A5) + (add_net /PDS/A6) + (add_net /PDS/A7) + (add_net /PDS/A8) + (add_net /PDS/A9) + (add_net /PDS/C16M) + (add_net /PDS/D0) + (add_net /PDS/D1) + (add_net /PDS/D10) + (add_net /PDS/D11) + (add_net /PDS/D12) + (add_net /PDS/D13) + (add_net /PDS/D14) + (add_net /PDS/D15) + (add_net /PDS/D16) + (add_net /PDS/D17) + (add_net /PDS/D18) + (add_net /PDS/D19) + (add_net /PDS/D2) + (add_net /PDS/D20) + (add_net /PDS/D21) + (add_net /PDS/D22) + (add_net /PDS/D23) + (add_net /PDS/D24) + (add_net /PDS/D25) + (add_net /PDS/D26) + (add_net /PDS/D27) + (add_net /PDS/D28) + (add_net /PDS/D29) + (add_net /PDS/D3) + (add_net /PDS/D30) + (add_net /PDS/D31) + (add_net /PDS/D4) + (add_net /PDS/D5) + (add_net /PDS/D6) + (add_net /PDS/D7) + (add_net /PDS/D8) + (add_net /PDS/D9) + (add_net /PDSBuf/ADoutLE) + (add_net /PDSBuf/A~OE~) + (add_net /PDSBuf/DDIR) + (add_net /PDSBuf/D~OE~) + (add_net /PDSBuf/FSB_~RESET~) + (add_net /PDSBuf/IOB_FC0) + (add_net /PDSBuf/IOB_FC1) + (add_net /PDSBuf/IOB_FC2) + (add_net /PDSBuf/IOB_R~W~) + (add_net /PDSBuf/IOB_SIZ0) + (add_net /PDSBuf/IOB_SIZ1) + (add_net /PDSBuf/IOB_~AS~) + (add_net /PDSBuf/IOB_~BERR~) + (add_net /PDSBuf/IOB_~DSACK~0) + (add_net /PDSBuf/IOB_~DSACK~1) + (add_net /PDSBuf/IOB_~DS~) + (add_net /PDSBuf/IOB_~HALT~) + (add_net /PDSBuf/IOB_~RESET~) + (add_net /PDSBuf/IOB_~RMC~) + (add_net /PDSBuf/IOC_A0) + (add_net /PDSBuf/IOC_A1) + (add_net /PDSBuf/IOC_A2) + (add_net /PDSBuf/IOC_A3) + (add_net /PDSBuf/IOC_D0) + (add_net /PDSBuf/IOC_D1) + (add_net /PDSBuf/IOC_D10) + (add_net /PDSBuf/IOC_D11) + (add_net /PDSBuf/IOC_D12) + (add_net /PDSBuf/IOC_D13) + (add_net /PDSBuf/IOC_D14) + (add_net /PDSBuf/IOC_D15) + (add_net /PDSBuf/IOC_D16) + (add_net /PDSBuf/IOC_D17) + (add_net /PDSBuf/IOC_D18) + (add_net /PDSBuf/IOC_D19) + (add_net /PDSBuf/IOC_D2) + (add_net /PDSBuf/IOC_D20) + (add_net /PDSBuf/IOC_D21) + (add_net /PDSBuf/IOC_D22) + (add_net /PDSBuf/IOC_D23) + (add_net /PDSBuf/IOC_D24) + (add_net /PDSBuf/IOC_D25) + (add_net /PDSBuf/IOC_D26) + (add_net /PDSBuf/IOC_D27) + (add_net /PDSBuf/IOC_D28) + (add_net /PDSBuf/IOC_D29) + (add_net /PDSBuf/IOC_D3) + (add_net /PDSBuf/IOC_D30) + (add_net /PDSBuf/IOC_D31) + (add_net /PDSBuf/IOC_D4) + (add_net /PDSBuf/IOC_D5) + (add_net /PDSBuf/IOC_D6) + (add_net /PDSBuf/IOC_D7) + (add_net /PDSBuf/IOC_D8) + (add_net /PDSBuf/IOC_D9) + (add_net /PDSBuf/IOC_SIZ0) + (add_net /PDSBuf/IOC_SIZ1) + (add_net /RAM/BA0) + (add_net /RAM/BA1) + (add_net /RAM/CKE) + (add_net /RAM/CLK01) + (add_net /RAM/CLK23) + (add_net /RAM/D0) + (add_net /RAM/D1) + (add_net /RAM/D10) + (add_net /RAM/D11) + (add_net /RAM/D12) + (add_net /RAM/D13) + (add_net /RAM/D14) + (add_net /RAM/D15) + (add_net /RAM/D16) + (add_net /RAM/D17) + (add_net /RAM/D18) + (add_net /RAM/D19) + (add_net /RAM/D2) + (add_net /RAM/D20) + (add_net /RAM/D21) + (add_net /RAM/D22) + (add_net /RAM/D23) + (add_net /RAM/D24) + (add_net /RAM/D25) + (add_net /RAM/D26) + (add_net /RAM/D27) + (add_net /RAM/D28) + (add_net /RAM/D29) + (add_net /RAM/D3) + (add_net /RAM/D30) + (add_net /RAM/D31) + (add_net /RAM/D4) + (add_net /RAM/D5) + (add_net /RAM/D6) + (add_net /RAM/D7) + (add_net /RAM/D8) + (add_net /RAM/D9) + (add_net /RAM/DQM0) + (add_net /RAM/DQM1) + (add_net /RAM/DQM2) + (add_net /RAM/DQM3) + (add_net /RAM/RA0) + (add_net /RAM/RA1) + (add_net /RAM/RA10) + (add_net /RAM/RA11) + (add_net /RAM/RA12) + (add_net /RAM/RA2) + (add_net /RAM/RA3) + (add_net /RAM/RA4) + (add_net /RAM/RA5) + (add_net /RAM/RA6) + (add_net /RAM/RA7) + (add_net /RAM/RA8) + (add_net /RAM/RA9) + (add_net GND) + (add_net "Net-(R1-Pad1)") + (add_net "Net-(U1-Pad121)") + (add_net "Net-(U1-Pad14)") + (add_net "Net-(U1-Pad16)") + (add_net "Net-(U1-Pad62)") + (add_net "Net-(U1-Pad73)") + (add_net "Net-(U1-Pad74)") + (add_net "Net-(U13-Pad7)") + (add_net "Net-(U13-Pad9)") + (add_net "Net-(U2-Pad15)") + (add_net "Net-(U2-Pad4)") + (add_net "Net-(U22-Pad12)") + (add_net "Net-(U22-Pad13)") + (add_net "Net-(U22-Pad14)") + (add_net "Net-(U22-Pad15)") + (add_net "Net-(U22-Pad16)") + (add_net "Net-(U22-Pad17)") + (add_net "Net-(U22-Pad4)") + (add_net "Net-(U22-Pad5)") + (add_net "Net-(U22-Pad6)") + (add_net "Net-(U22-Pad7)") + (add_net "Net-(U22-Pad8)") + (add_net "Net-(U22-Pad9)") + (add_net "Net-(U23-Pad9)") + (add_net "Net-(U24-Pad5)") + (add_net "Net-(U24-Pad7)") + (add_net "Net-(U24-Pad9)") + (add_net "Net-(U3-PadA10)") + (add_net "Net-(U3-PadA11)") + (add_net "Net-(U3-PadA12)") + (add_net "Net-(U3-PadA13)") + (add_net "Net-(U3-PadA14)") + (add_net "Net-(U3-PadA15)") + (add_net "Net-(U3-PadA2)") + (add_net "Net-(U3-PadA3)") + (add_net "Net-(U3-PadA4)") + (add_net "Net-(U3-PadA5)") + (add_net "Net-(U3-PadA6)") + (add_net "Net-(U3-PadA7)") + (add_net "Net-(U3-PadA8)") + (add_net "Net-(U3-PadA9)") + (add_net "Net-(U3-PadB1)") + (add_net "Net-(U3-PadB10)") + (add_net "Net-(U3-PadB12)") + (add_net "Net-(U3-PadB14)") + (add_net "Net-(U3-PadB15)") + (add_net "Net-(U3-PadB16)") + (add_net "Net-(U3-PadB2)") + (add_net "Net-(U3-PadB3)") + (add_net "Net-(U3-PadB5)") + (add_net "Net-(U3-PadB6)") + (add_net "Net-(U3-PadB8)") + (add_net "Net-(U3-PadC1)") + (add_net "Net-(U3-PadC10)") + (add_net "Net-(U3-PadC11)") + (add_net "Net-(U3-PadC12)") + (add_net "Net-(U3-PadC13)") + (add_net "Net-(U3-PadC14)") + (add_net "Net-(U3-PadC15)") + (add_net "Net-(U3-PadC16)") + (add_net "Net-(U3-PadC2)") + (add_net "Net-(U3-PadC3)") + (add_net "Net-(U3-PadC5)") + (add_net "Net-(U3-PadC6)") + (add_net "Net-(U3-PadC7)") + (add_net "Net-(U3-PadC8)") + (add_net "Net-(U3-PadC9)") + (add_net "Net-(U3-PadD1)") + (add_net "Net-(U3-PadD11)") + (add_net "Net-(U3-PadD12)") + (add_net "Net-(U3-PadD14)") + (add_net "Net-(U3-PadD16)") + (add_net "Net-(U3-PadD3)") + (add_net "Net-(U3-PadD5)") + (add_net "Net-(U3-PadD6)") + (add_net "Net-(U3-PadD8)") + (add_net "Net-(U3-PadD9)") + (add_net "Net-(U3-PadE1)") + (add_net "Net-(U3-PadE10)") + (add_net "Net-(U3-PadE11)") + (add_net "Net-(U3-PadE12)") + (add_net "Net-(U3-PadE13)") + (add_net "Net-(U3-PadE14)") + (add_net "Net-(U3-PadE15)") + (add_net "Net-(U3-PadE16)") + (add_net "Net-(U3-PadE2)") + (add_net "Net-(U3-PadE3)") + (add_net "Net-(U3-PadE4)") + (add_net "Net-(U3-PadE6)") + (add_net "Net-(U3-PadE7)") + (add_net "Net-(U3-PadE8)") + (add_net "Net-(U3-PadF1)") + (add_net "Net-(U3-PadF10)") + (add_net "Net-(U3-PadF12)") + (add_net "Net-(U3-PadF13)") + (add_net "Net-(U3-PadF14)") + (add_net "Net-(U3-PadF15)") + (add_net "Net-(U3-PadF16)") + (add_net "Net-(U3-PadF2)") + (add_net "Net-(U3-PadF3)") + (add_net "Net-(U3-PadF4)") + (add_net "Net-(U3-PadF5)") + (add_net "Net-(U3-PadF6)") + (add_net "Net-(U3-PadF7)") + (add_net "Net-(U3-PadF9)") + (add_net "Net-(U3-PadG1)") + (add_net "Net-(U3-PadG11)") + (add_net "Net-(U3-PadG12)") + (add_net "Net-(U3-PadG14)") + (add_net "Net-(U3-PadG16)") + (add_net "Net-(U3-PadG3)") + (add_net "Net-(U3-PadG5)") + (add_net "Net-(U3-PadG6)") + (add_net "Net-(U3-PadH1)") + (add_net "Net-(U3-PadH11)") + (add_net "Net-(U3-PadH13)") + (add_net "Net-(U3-PadH14)") + (add_net "Net-(U3-PadH15)") + (add_net "Net-(U3-PadH16)") + (add_net "Net-(U3-PadH2)") + (add_net "Net-(U3-PadH3)") + (add_net "Net-(U3-PadH4)") + (add_net "Net-(U3-PadH5)") + (add_net "Net-(U3-PadJ1)") + (add_net "Net-(U3-PadJ11)") + (add_net "Net-(U3-PadJ12)") + (add_net "Net-(U3-PadJ13)") + (add_net "Net-(U3-PadJ14)") + (add_net "Net-(U3-PadJ16)") + (add_net "Net-(U3-PadJ3)") + (add_net "Net-(U3-PadJ4)") + (add_net "Net-(U3-PadJ6)") + (add_net "Net-(U3-PadK1)") + (add_net "Net-(U3-PadK11)") + (add_net "Net-(U3-PadK12)") + (add_net "Net-(U3-PadK14)") + (add_net "Net-(U3-PadK15)") + (add_net "Net-(U3-PadK16)") + (add_net "Net-(U3-PadK2)") + (add_net "Net-(U3-PadK3)") + (add_net "Net-(U3-PadK5)") + (add_net "Net-(U3-PadK6)") + (add_net "Net-(U3-PadL1)") + (add_net "Net-(U3-PadL10)") + (add_net "Net-(U3-PadL11)") + (add_net "Net-(U3-PadL12)") + (add_net "Net-(U3-PadL13)") + (add_net "Net-(U3-PadL14)") + (add_net "Net-(U3-PadL16)") + (add_net "Net-(U3-PadL3)") + (add_net "Net-(U3-PadL4)") + (add_net "Net-(U3-PadL5)") + (add_net "Net-(U3-PadL7)") + (add_net "Net-(U3-PadL8)") + (add_net "Net-(U3-PadM1)") + (add_net "Net-(U3-PadM10)") + (add_net "Net-(U3-PadM11)") + (add_net "Net-(U3-PadM12)") + (add_net "Net-(U3-PadM13)") + (add_net "Net-(U3-PadM14)") + (add_net "Net-(U3-PadM15)") + (add_net "Net-(U3-PadM16)") + (add_net "Net-(U3-PadM2)") + (add_net "Net-(U3-PadM3)") + (add_net "Net-(U3-PadM4)") + (add_net "Net-(U3-PadM5)") + (add_net "Net-(U3-PadM6)") + (add_net "Net-(U3-PadM7)") + (add_net "Net-(U3-PadM9)") + (add_net "Net-(U3-PadN1)") + (add_net "Net-(U3-PadN12)") + (add_net "Net-(U3-PadN14)") + (add_net "Net-(U3-PadN16)") + (add_net "Net-(U3-PadN3)") + (add_net "Net-(U3-PadN4)") + (add_net "Net-(U3-PadN5)") + (add_net "Net-(U3-PadN6)") + (add_net "Net-(U3-PadN8)") + (add_net "Net-(U3-PadN9)") + (add_net "Net-(U3-PadP1)") + (add_net "Net-(U3-PadP11)") + (add_net "Net-(U3-PadP12)") + (add_net "Net-(U3-PadP14)") + (add_net "Net-(U3-PadP15)") + (add_net "Net-(U3-PadP16)") + (add_net "Net-(U3-PadP2)") + (add_net "Net-(U3-PadP4)") + (add_net "Net-(U3-PadP5)") + (add_net "Net-(U3-PadP6)") + (add_net "Net-(U3-PadP7)") + (add_net "Net-(U3-PadP8)") + (add_net "Net-(U3-PadP9)") + (add_net "Net-(U3-PadR1)") + (add_net "Net-(U3-PadR12)") + (add_net "Net-(U3-PadR14)") + (add_net "Net-(U3-PadR15)") + (add_net "Net-(U3-PadR16)") + (add_net "Net-(U3-PadR2)") + (add_net "Net-(U3-PadR5)") + (add_net "Net-(U3-PadR7)") + (add_net "Net-(U3-PadR9)") + (add_net "Net-(U3-PadT10)") + (add_net "Net-(U3-PadT12)") + (add_net "Net-(U3-PadT13)") + (add_net "Net-(U3-PadT14)") + (add_net "Net-(U3-PadT15)") + (add_net "Net-(U3-PadT3)") + (add_net "Net-(U3-PadT4)") + (add_net "Net-(U3-PadT5)") + (add_net "Net-(U3-PadT6)") + (add_net "Net-(U3-PadT7)") + (add_net "Net-(U3-PadT8)") + (add_net "Net-(U3-PadT9)") + (add_net "Net-(U6-Pad1)") + (add_net "Net-(U6-Pad2)") + (add_net "Net-(U6-Pad3)") + (add_net "Net-(U6-Pad4)") + (add_net "Net-(U9-Pad19)") + ) + + (module stdpads:TQFP-100_14x14mm_P0.5mm (layer F.Cu) (tedit 608E5AA2) (tstamp 61BA4157) + (at 243.6 174) + (descr "TQFP, 100 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "TQFP QFP") + (solder_mask_margin 0.024) + (solder_paste_margin -0.035) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value TQFP-100_14x14mm_P0.5mm (at 1.05 0 90) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_line (start 6.4 -8.65) (end 0 -8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.4 -7.25) (end 6.4 -8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 7.25 -7.25) (end 6.4 -7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 7.25 -6.4) (end 7.25 -7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.65 -6.4) (end 7.25 -6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.65 0) (end 8.65 -6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.4 8.65) (end 0 8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.4 7.25) (end 6.4 8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start 7.25 7.25) (end 6.4 7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 7.25 6.4) (end 7.25 7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.65 6.4) (end 7.25 6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.65 0) (end 8.65 6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6.4 -8.65) (end 0 -8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6.4 -7.25) (end -6.4 -8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -7.25 -7.25) (end -6.4 -7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -7.25 -6.4) (end -7.25 -7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.65 -6.4) (end -7.25 -6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.65 0) (end -8.65 -6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6.4 8.65) (end 0 8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6.4 7.25) (end -6.4 8.65) (layer F.CrtYd) (width 0.05)) + (fp_line (start -7.25 7.25) (end -6.4 7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -7.25 6.4) (end -7.25 7.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.65 6.4) (end -7.25 6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.65 0) (end -8.65 6.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6 7) (end -7 6) (layer F.Fab) (width 0.1)) + (fp_line (start 7 7) (end -6 7) (layer F.Fab) (width 0.1)) + (fp_line (start 7 -7) (end 7 7) (layer F.Fab) (width 0.1)) + (fp_line (start -7 -7) (end 7 -7) (layer F.Fab) (width 0.1)) + (fp_line (start -7 6) (end -7 -7) (layer F.Fab) (width 0.1)) + (fp_line (start -6.41 7.11) (end -6.41 8.4) (layer F.SilkS) (width 0.12)) + (fp_line (start -7.11 7.11) (end -6.41 7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start -7.11 6.41) (end -7.11 7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start -7.11 -7.11) (end -6.41 -7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start -7.11 -6.41) (end -7.11 -7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 7.11 7.11) (end 6.41 7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 7.11 6.41) (end 7.11 7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 7.11 -7.11) (end 6.41 -7.11) (layer F.SilkS) (width 0.12)) + (fp_line (start 7.11 -6.41) (end 7.11 -7.11) (layer F.SilkS) (width 0.12)) + (pad 1 smd roundrect (at -6 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at -5.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 3 smd roundrect (at -5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 4 smd roundrect (at -4.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 5 smd roundrect (at -4 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 6 smd roundrect (at -3.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 7 smd roundrect (at -3 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 8 smd roundrect (at -2.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 9 smd roundrect (at -2 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 10 smd roundrect (at -1.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 11 smd roundrect (at -1 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 12 smd roundrect (at -0.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 13 smd roundrect (at 0 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 14 smd roundrect (at 0.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 15 smd roundrect (at 1 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 16 smd roundrect (at 1.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 17 smd roundrect (at 2 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 18 smd roundrect (at 2.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 19 smd roundrect (at 3 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 20 smd roundrect (at 3.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 21 smd roundrect (at 4 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 22 smd roundrect (at 4.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 23 smd roundrect (at 5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 24 smd roundrect (at 5.5 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 25 smd roundrect (at 6 7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 26 smd roundrect (at 7.6625 6 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 27 smd roundrect (at 7.6625 5.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 28 smd roundrect (at 7.6625 5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 29 smd roundrect (at 7.6625 4.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 30 smd roundrect (at 7.6625 4 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 31 smd roundrect (at 7.6625 3.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 32 smd roundrect (at 7.6625 3 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 33 smd roundrect (at 7.6625 2.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 34 smd roundrect (at 7.6625 2 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 35 smd roundrect (at 7.6625 1.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 36 smd roundrect (at 7.6625 1 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 37 smd roundrect (at 7.6625 0.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 38 smd roundrect (at 7.6625 0 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 39 smd roundrect (at 7.6625 -0.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 40 smd roundrect (at 7.6625 -1 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 41 smd roundrect (at 7.6625 -1.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 42 smd roundrect (at 7.6625 -2 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 43 smd roundrect (at 7.6625 -2.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 44 smd roundrect (at 7.6625 -3 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 45 smd roundrect (at 7.6625 -3.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 46 smd roundrect (at 7.6625 -4 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 47 smd roundrect (at 7.6625 -4.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 48 smd roundrect (at 7.6625 -5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 49 smd roundrect (at 7.6625 -5.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 50 smd roundrect (at 7.6625 -6 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 51 smd roundrect (at 6 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 52 smd roundrect (at 5.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 53 smd roundrect (at 5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 54 smd roundrect (at 4.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 55 smd roundrect (at 4 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 56 smd roundrect (at 3.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 57 smd roundrect (at 3 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 58 smd roundrect (at 2.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 59 smd roundrect (at 2 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 60 smd roundrect (at 1.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 61 smd roundrect (at 1 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 62 smd roundrect (at 0.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 63 smd roundrect (at 0 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 64 smd roundrect (at -0.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 65 smd roundrect (at -1 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 66 smd roundrect (at -1.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 67 smd roundrect (at -2 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 68 smd roundrect (at -2.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 69 smd roundrect (at -3 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 70 smd roundrect (at -3.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 71 smd roundrect (at -4 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 72 smd roundrect (at -4.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 73 smd roundrect (at -5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 74 smd roundrect (at -5.5 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 75 smd roundrect (at -6 -7.6625 90) (size 1.475 0.3) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 76 smd roundrect (at -7.6625 -6 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 77 smd roundrect (at -7.6625 -5.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 78 smd roundrect (at -7.6625 -5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 79 smd roundrect (at -7.6625 -4.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 80 smd roundrect (at -7.6625 -4 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 81 smd roundrect (at -7.6625 -3.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 82 smd roundrect (at -7.6625 -3 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 83 smd roundrect (at -7.6625 -2.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 84 smd roundrect (at -7.6625 -2 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 85 smd roundrect (at -7.6625 -1.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 86 smd roundrect (at -7.6625 -1 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 87 smd roundrect (at -7.6625 -0.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 88 smd roundrect (at -7.6625 0 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 89 smd roundrect (at -7.6625 0.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 90 smd roundrect (at -7.6625 1 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 91 smd roundrect (at -7.6625 1.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 92 smd roundrect (at -7.6625 2 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 93 smd roundrect (at -7.6625 2.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 94 smd roundrect (at -7.6625 3 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 95 smd roundrect (at -7.6625 3.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 96 smd roundrect (at -7.6625 4 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 97 smd roundrect (at -7.6625 4.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 98 smd roundrect (at -7.6625 5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 99 smd roundrect (at -7.6625 5.5 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 100 smd roundrect (at -7.6625 6 90) (size 0.3 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Package_QFP.3dshapes/TQFP-100_14x14mm_P0.5mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:PLCC-68_SMDSocket (layer F.Cu) (tedit 616FF780) (tstamp 617CEACC) + (at 207.5815 113.792 90) + (descr "PLCC, 68 Pin (http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131095), generated with kicad-footprint-generator ipc_plcc_jLead_generator.py") + (tags "PLCC LCC") + (path /5F72F108/63A841DD) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference U2 (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value MC68882FN (at 0 1.27 90) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_line (start -12.9 -10.71) (end -12.9 0) (layer F.CrtYd) (width 0.05)) + (fp_line (start -12.37 -10.71) (end -12.9 -10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start -12.37 -11.08) (end -12.37 -10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start -11.08 -12.37) (end -12.37 -11.08) (layer F.CrtYd) (width 0.05)) + (fp_line (start -10.71 -12.37) (end -11.08 -12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start -10.71 -12.9) (end -10.71 -12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0 -12.9) (end -10.71 -12.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start 12.9 10.71) (end 12.9 0) (layer F.CrtYd) (width 0.05)) + (fp_line (start 12.37 10.71) (end 12.9 10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start 12.37 12.37) (end 12.37 10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start 10.71 12.37) (end 12.37 12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start 10.71 12.9) (end 10.71 12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0 12.9) (end 10.71 12.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start -12.9 10.71) (end -12.9 0) (layer F.CrtYd) (width 0.05)) + (fp_line (start -12.37 10.71) (end -12.9 10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start -12.37 12.37) (end -12.37 10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start -10.71 12.37) (end -12.37 12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start -10.71 12.9) (end -10.71 12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0 12.9) (end -10.71 12.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start 12.9 -10.71) (end 12.9 0) (layer F.CrtYd) (width 0.05)) + (fp_line (start 12.37 -10.71) (end 12.9 -10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start 12.37 -12.37) (end 12.37 -10.71) (layer F.CrtYd) (width 0.05)) + (fp_line (start 10.71 -12.37) (end 12.37 -12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start 10.71 -12.9) (end 10.71 -12.37) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0 -12.9) (end 10.71 -12.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.5 -12.1158) (end 0 -11.408693) (layer F.Fab) (width 0.1)) + (fp_line (start -10.9728 -12.1158) (end -0.5 -12.1158) (layer F.Fab) (width 0.1)) + (fp_line (start -12.1158 -10.9728) (end -10.9728 -12.1158) (layer F.Fab) (width 0.1)) + (fp_line (start -12.1158 12.1158) (end -12.1158 -10.9728) (layer F.Fab) (width 0.1)) + (fp_line (start 12.1158 12.1158) (end -12.1158 12.1158) (layer F.Fab) (width 0.1)) + (fp_line (start 12.1158 -12.1158) (end 12.1158 12.1158) (layer F.Fab) (width 0.1)) + (fp_line (start 0.5 -12.1158) (end 12.1158 -12.1158) (layer F.Fab) (width 0.1)) + (fp_line (start 0 -11.408693) (end 0.5 -12.1158) (layer F.Fab) (width 0.1)) + (fp_line (start -12.2258 -11.050582) (end -12.2258 -10.72) (layer F.SilkS) (width 0.12)) + (fp_line (start -11.050582 -12.2258) (end -12.2258 -11.050582) (layer F.SilkS) (width 0.12)) + (fp_line (start -10.72 -12.2258) (end -11.050582 -12.2258) (layer F.SilkS) (width 0.12)) + (fp_line (start 12.2258 12.2258) (end 12.2258 10.72) (layer F.SilkS) (width 0.12)) + (fp_line (start 10.72 12.2258) (end 12.2258 12.2258) (layer F.SilkS) (width 0.12)) + (fp_line (start -12.2258 12.2258) (end -12.2258 10.72) (layer F.SilkS) (width 0.12)) + (fp_line (start -10.72 12.2258) (end -12.2258 12.2258) (layer F.SilkS) (width 0.12)) + (fp_line (start 12.2258 -12.2258) (end 12.2258 -10.72) (layer F.SilkS) (width 0.12)) + (fp_line (start 10.72 -12.2258) (end 12.2258 -12.2258) (layer F.SilkS) (width 0.12)) + (fp_line (start 15.625 -15.625) (end 1 -15.625) (layer F.SilkS) (width 0.12)) + (fp_line (start 15.625 15.625) (end 15.625 -15.625) (layer F.SilkS) (width 0.12)) + (fp_line (start -15.625 15.625) (end 15.625 15.625) (layer F.SilkS) (width 0.12)) + (fp_line (start -15.625 -14.625) (end -15.625 15.625) (layer F.SilkS) (width 0.12)) + (fp_line (start -14.625 -15.625) (end -15.625 -14.625) (layer F.SilkS) (width 0.12)) + (fp_line (start -1 -15.625) (end -14.625 -15.625) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -14.475) (end 0.5 -15.475) (layer F.Fab) (width 0.1)) + (fp_line (start -0.5 -15.475) (end 0 -14.475) (layer F.Fab) (width 0.1)) + (fp_line (start 14.205 -14.205) (end -14.205 -14.205) (layer F.Fab) (width 0.1)) + (fp_line (start 14.205 14.205) (end 14.205 -14.205) (layer F.Fab) (width 0.1)) + (fp_line (start -14.205 14.205) (end 14.205 14.205) (layer F.Fab) (width 0.1)) + (fp_line (start -14.205 -14.205) (end -14.205 14.205) (layer F.Fab) (width 0.1)) + (fp_line (start 15.95 -15.95) (end -15.95 -15.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 15.95 15.95) (end 15.95 -15.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -15.95 15.95) (end 15.95 15.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -15.95 -15.95) (end -15.95 15.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 15.475 -15.475) (end -14.475 -15.475) (layer F.Fab) (width 0.1)) + (fp_line (start 15.475 15.475) (end 15.475 -15.475) (layer F.Fab) (width 0.1)) + (fp_line (start -15.475 15.475) (end 15.475 15.475) (layer F.Fab) (width 0.1)) + (fp_line (start -15.475 -14.475) (end -15.475 15.475) (layer F.Fab) (width 0.1)) + (fp_line (start -14.475 -15.475) (end -15.475 -14.475) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 66 smd roundrect (at 3.81 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 492 /CPUBuf/CPU_D5)) + (pad 65 smd roundrect (at 5.08 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 493 /CPUBuf/CPU_D6)) + (pad 64 smd roundrect (at 6.35 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 494 /CPUBuf/CPU_D7)) + (pad 63 smd roundrect (at 7.62 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 62 smd roundrect (at 8.89 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 463 /CPUBuf/CPU_D8)) + (pad 61 smd roundrect (at 10.16 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 60 smd roundrect (at 11.8 -10.16 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 464 /CPUBuf/CPU_D9)) + (pad 40 smd roundrect (at 6.35 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 479 /CPUBuf/CPU_D24)) + (pad 39 smd roundrect (at 5.08 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 480 /CPUBuf/CPU_D25)) + (pad 38 smd roundrect (at 3.81 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 481 /CPUBuf/CPU_D26)) + (pad 37 smd roundrect (at 2.54 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 482 /CPUBuf/CPU_D27)) + (pad 36 smd roundrect (at 1.27 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 483 /CPUBuf/CPU_D28)) + (pad 35 smd roundrect (at 0 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 484 /CPUBuf/CPU_D29)) + (pad 34 smd roundrect (at -1.27 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 485 /CPUBuf/CPU_D30)) + (pad 33 smd roundrect (at -2.54 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 486 /CPUBuf/CPU_D31)) + (pad 32 smd roundrect (at -3.81 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 502 /CPUBuf/CPU_~DSACK~1)) + (pad 31 smd roundrect (at -5.08 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 503 /CPUBuf/CPU_~DSACK~0)) + (pad 30 smd roundrect (at -6.35 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 29 smd roundrect (at -7.62 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 54 /Control/FPU~CS~)) + (pad 28 smd roundrect (at -8.89 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 495 /CPUBuf/CPU_R~W~)) + (pad 27 smd roundrect (at -10.16 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 26 smd roundrect (at -11.8 10.16 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 25 smd roundrect (at -11.8 8.89 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 5 /MC68k/A1)) + (pad 24 smd roundrect (at -11.8 7.62 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 36 /MC68k/A2)) + (pad 23 smd roundrect (at -11.8 6.35 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 35 /MC68k/A3)) + (pad 22 smd roundrect (at -11.8 5.08 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 34 /MC68k/A4)) + (pad 21 smd roundrect (at -11.8 3.81 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 500 /CPUBuf/CPU_~AS~)) + (pad 20 smd roundrect (at -11.8 2.54 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 499 /CPUBuf/CPU_~DS~)) + (pad 19 smd roundrect (at -11.8 1.27 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 18 smd roundrect (at -11.8 0 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 17 smd roundrect (at -11.8 -1.27 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 16 smd roundrect (at -11.8 -2.54 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 15 smd roundrect (at -11.8 -3.81 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 55 "Net-(U2-Pad15)")) + (pad 14 smd roundrect (at -11.8 -5.08 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 13 smd roundrect (at -11.8 -6.35 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 38 /PDSBuf/IOB_~RESET~)) + (pad 12 smd roundrect (at -11.8 -7.62 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at -11.8 -8.89 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 56 /Control/FPUCLK)) + (pad 10 smd roundrect (at -11.8 -10.16 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 9 smd roundrect (at -10.16 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 8 smd roundrect (at -8.89 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 55 smd roundrect (at 11.8 -3.81 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 469 /CPUBuf/CPU_D14)) + (pad 54 smd roundrect (at 11.8 -2.54 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 470 /CPUBuf/CPU_D15)) + (pad 53 smd roundrect (at 11.8 -1.27 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 52 smd roundrect (at 11.8 0 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 51 smd roundrect (at 11.8 1.27 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 50 smd roundrect (at 11.8 2.54 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 471 /CPUBuf/CPU_D16)) + (pad 49 smd roundrect (at 11.8 3.81 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 472 /CPUBuf/CPU_D17)) + (pad 48 smd roundrect (at 11.8 5.08 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 473 /CPUBuf/CPU_D18)) + (pad 47 smd roundrect (at 11.8 6.35 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 474 /CPUBuf/CPU_D19)) + (pad 46 smd roundrect (at 11.8 7.62 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 475 /CPUBuf/CPU_D20)) + (pad 45 smd roundrect (at 11.8 8.89 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 476 /CPUBuf/CPU_D21)) + (pad 44 smd roundrect (at 11.8 10.16 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 477 /CPUBuf/CPU_D22)) + (pad 43 smd roundrect (at 10.16 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 42 smd roundrect (at 8.89 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 478 /CPUBuf/CPU_D23)) + (pad 41 smd roundrect (at 7.62 11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 59 smd roundrect (at 11.8 -8.89 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 465 /CPUBuf/CPU_D10)) + (pad 58 smd roundrect (at 11.8 -7.62 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 466 /CPUBuf/CPU_D11)) + (pad 57 smd roundrect (at 11.8 -6.35 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 467 /CPUBuf/CPU_D12)) + (pad 56 smd roundrect (at 11.8 -5.08 90) (size 1.7 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 468 /CPUBuf/CPU_D13)) + (pad 67 smd roundrect (at 2.54 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 491 /CPUBuf/CPU_D4)) + (pad 68 smd roundrect (at 1.27 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 490 /CPUBuf/CPU_D3)) + (pad 7 smd roundrect (at -7.62 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 6 smd roundrect (at -6.35 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 5 smd roundrect (at -5.08 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 4 smd roundrect (at -3.81 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 57 "Net-(U2-Pad4)")) + (pad 3 smd roundrect (at -2.54 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 487 /CPUBuf/CPU_D0)) + (pad 2 smd roundrect (at -1.27 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 488 /CPUBuf/CPU_D1)) + (pad 1 smd roundrect (at 0 -11.8 90) (size 0.6 1.7) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 489 /CPUBuf/CPU_D2)) + (model ${KIPRJMOD}/../../stdpads.3dshapes/PLCC-68_PTHSocket.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 0.5)) + (rotate (xyz 0 0 180)) + ) + (model ${KIPRJMOD}/../../stdpads.3dshapes/PLCC-68.wrl + (offset (xyz 0 0 1)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AB4A40) + (at 209.65 38.8) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AB4B1D) + (at 197.35 49 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AB4B0F) + (at 197.35 51.1 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AB4A4E) + (at 207.55 38.8 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_BGA:BGA-256_17.0x17.0mm_Layout16x16_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD (layer F.Cu) (tedit 5A058D74) (tstamp 6178601D) + (at 208.6 50.05 90) + (descr "BGA-256, dimensions: https://www.xilinx.com/support/documentation/package_specs/ft256.pdf, design rules: https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf") + (tags BGA-256) + (path /5F723173/63B6D9FE) + (attr smd) + (fp_text reference U3 (at 0 -9.6 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value XC6SLX9-FTG256 (at 0 9.7 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 9.5 9.5) (end -9.5 9.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.5 9.5) (end 9.5 -9.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -9.5 -9.5) (end -9.5 9.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -9.5 -9.5) (end 9.5 -9.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.5 -8) (end -8.5 8.5) (layer F.Fab) (width 0.1)) + (fp_line (start -8 -8.5) (end -8.5 -8) (layer F.Fab) (width 0.1)) + (fp_line (start 8.5 -8.5) (end -8 -8.5) (layer F.Fab) (width 0.1)) + (fp_line (start 8.5 8.5) (end 8.5 -8.5) (layer F.Fab) (width 0.1)) + (fp_line (start -8.5 8.5) (end 8.5 8.5) (layer F.Fab) (width 0.1)) + (fp_line (start 8.6 8.6) (end 8.6 -8.6) (layer F.SilkS) (width 0.12)) + (fp_line (start -8.6 8.6) (end 8.6 8.6) (layer F.SilkS) (width 0.12)) + (fp_line (start -8.6 -8.6) (end -8.6 8.6) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.6 -8.6) (end -8.6 -8.6) (layer F.SilkS) (width 0.12)) + (fp_line (start -8.8 -8.8) (end -8.8 -8.1) (layer F.SilkS) (width 0.12)) + (fp_line (start -8.1 -8.8) (end -8.8 -8.8) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad A1 smd circle (at -7.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad A2 smd circle (at -6.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 58 "Net-(U3-PadA2)")) + (pad A3 smd circle (at -5.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 59 "Net-(U3-PadA3)")) + (pad A4 smd circle (at -4.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 60 "Net-(U3-PadA4)")) + (pad A5 smd circle (at -3.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 61 "Net-(U3-PadA5)")) + (pad A6 smd circle (at -2.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 62 "Net-(U3-PadA6)")) + (pad A7 smd circle (at -1.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 63 "Net-(U3-PadA7)")) + (pad A8 smd circle (at -0.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 64 "Net-(U3-PadA8)")) + (pad A9 smd circle (at 0.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 65 "Net-(U3-PadA9)")) + (pad A10 smd circle (at 1.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 66 "Net-(U3-PadA10)")) + (pad A11 smd circle (at 2.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 67 "Net-(U3-PadA11)")) + (pad A12 smd circle (at 3.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 68 "Net-(U3-PadA12)")) + (pad A13 smd circle (at 4.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 69 "Net-(U3-PadA13)")) + (pad A14 smd circle (at 5.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 70 "Net-(U3-PadA14)")) + (pad A15 smd circle (at 6.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 71 "Net-(U3-PadA15)")) + (pad A16 smd circle (at 7.5 -7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad B1 smd circle (at -7.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 72 "Net-(U3-PadB1)")) + (pad C1 smd circle (at -7.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 73 "Net-(U3-PadC1)")) + (pad D1 smd circle (at -7.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 74 "Net-(U3-PadD1)")) + (pad E1 smd circle (at -7.5 -3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 75 "Net-(U3-PadE1)")) + (pad F1 smd circle (at -7.5 -2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 76 "Net-(U3-PadF1)")) + (pad G1 smd circle (at -7.5 -1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 77 "Net-(U3-PadG1)")) + (pad H1 smd circle (at -7.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 78 "Net-(U3-PadH1)")) + (pad J1 smd circle (at -7.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 79 "Net-(U3-PadJ1)")) + (pad B16 smd circle (at 7.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 80 "Net-(U3-PadB16)")) + (pad B15 smd circle (at 6.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 81 "Net-(U3-PadB15)")) + (pad B14 smd circle (at 5.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 82 "Net-(U3-PadB14)")) + (pad B13 smd circle (at 4.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad B12 smd circle (at 3.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 83 "Net-(U3-PadB12)")) + (pad B11 smd circle (at 2.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad B10 smd circle (at 1.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 84 "Net-(U3-PadB10)")) + (pad B9 smd circle (at 0.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad B8 smd circle (at -0.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 85 "Net-(U3-PadB8)")) + (pad B7 smd circle (at -1.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad B6 smd circle (at -2.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 86 "Net-(U3-PadB6)")) + (pad B5 smd circle (at -3.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 87 "Net-(U3-PadB5)")) + (pad B2 smd circle (at -6.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 88 "Net-(U3-PadB2)")) + (pad B3 smd circle (at -5.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 89 "Net-(U3-PadB3)")) + (pad B4 smd circle (at -4.5 -6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad C2 smd circle (at -6.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 90 "Net-(U3-PadC2)")) + (pad C3 smd circle (at -5.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 91 "Net-(U3-PadC3)")) + (pad C4 smd circle (at -4.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 455 /Control/HSWAPEN)) + (pad C5 smd circle (at -3.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 92 "Net-(U3-PadC5)")) + (pad C6 smd circle (at -2.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 93 "Net-(U3-PadC6)")) + (pad C7 smd circle (at -1.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 94 "Net-(U3-PadC7)")) + (pad C8 smd circle (at -0.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 95 "Net-(U3-PadC8)")) + (pad C9 smd circle (at 0.5 -5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 96 "Net-(U3-PadC9)")) + (pad D2 smd circle (at -6.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad D3 smd circle (at -5.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 97 "Net-(U3-PadD3)")) + (pad D4 smd circle (at -4.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad D5 smd circle (at -3.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 98 "Net-(U3-PadD5)")) + (pad D6 smd circle (at -2.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 99 "Net-(U3-PadD6)")) + (pad D7 smd circle (at -1.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad D8 smd circle (at -0.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 100 "Net-(U3-PadD8)")) + (pad D9 smd circle (at 0.5 -4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 101 "Net-(U3-PadD9)")) + (pad E2 smd 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(size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 179 "Net-(U3-PadP11)")) + (pad P10 smd circle (at 1.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 510 /Control/MOSI_DIN)) + (pad P9 smd circle (at 0.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 180 "Net-(U3-PadP9)")) + (pad P8 smd circle (at -0.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 181 "Net-(U3-PadP8)")) + (pad P7 smd circle (at -1.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 182 "Net-(U3-PadP7)")) + (pad R7 smd circle (at -1.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 183 "Net-(U3-PadR7)")) + (pad R8 smd circle (at -0.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad R9 smd circle (at 0.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 184 "Net-(U3-PadR9)")) + (pad R10 smd circle (at 1.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad R11 smd circle (at 2.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 511 /Control/CCLK_SCK)) + (pad T7 smd circle (at -1.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 185 "Net-(U3-PadT7)")) + (pad T8 smd circle (at -0.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 186 "Net-(U3-PadT8)")) + (pad T9 smd circle (at 0.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 187 "Net-(U3-PadT9)")) + (pad T10 smd circle (at 1.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 512 "Net-(U3-PadT10)")) + (pad T11 smd circle (at 2.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 458 /Control/M0)) + (pad N8 smd circle (at -0.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 188 "Net-(U3-PadN8)")) + (pad E9 smd circle (at 0.5 -3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad E10 smd circle (at 1.5 -3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 189 "Net-(U3-PadE10)")) + (pad E11 smd circle (at 2.5 -3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 190 "Net-(U3-PadE11)")) + (pad E12 smd circle (at 3.5 -3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 191 "Net-(U3-PadE12)")) + (pad P12 smd circle (at 3.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 513 "Net-(U3-PadP12)")) + (pad F9 smd circle (at 0.5 -2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 192 "Net-(U3-PadF9)")) + (pad F10 smd circle (at 1.5 -2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 193 "Net-(U3-PadF10)")) + (pad F11 smd circle (at 2.5 -2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad F12 smd circle (at 3.5 -2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 194 "Net-(U3-PadF12)")) + (pad J9 smd circle (at 0.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 447 +1V2)) + (pad G12 smd circle (at 3.5 -1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 195 "Net-(U3-PadG12)")) + (pad G11 smd circle (at 2.5 -1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 196 "Net-(U3-PadG11)")) + (pad G10 smd circle (at 1.5 -1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad G9 smd circle (at 0.5 -1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 447 +1V2)) + (pad R12 smd circle (at 3.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 197 "Net-(U3-PadR12)")) + (pad T12 smd circle (at 3.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 198 "Net-(U3-PadT12)")) + (pad H9 smd circle (at 0.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad H10 smd circle (at 1.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 447 +1V2)) + (pad H11 smd circle (at 2.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 199 "Net-(U3-PadH11)")) + (pad H12 smd circle (at 3.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad J10 smd circle (at 1.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad J11 smd circle (at 2.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 200 "Net-(U3-PadJ11)")) + (pad J12 smd circle (at 3.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 201 "Net-(U3-PadJ12)")) + (pad H13 smd circle (at 4.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 202 "Net-(U3-PadH13)")) + (pad J13 smd circle (at 4.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 203 "Net-(U3-PadJ13)")) + (pad K13 smd circle (at 4.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad L13 smd circle (at 4.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 204 "Net-(U3-PadL13)")) + (pad M13 smd circle (at 4.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 205 "Net-(U3-PadM13)")) + (pad N13 smd circle (at 4.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad P13 smd circle (at 4.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 459 /Control/DONE)) + (pad R13 smd circle (at 4.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad T13 smd circle (at 4.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 206 "Net-(U3-PadT13)")) + (pad N9 smd circle (at 0.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 207 "Net-(U3-PadN9)")) + (pad M9 smd circle (at 0.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 208 "Net-(U3-PadM9)")) + (pad L9 smd circle (at 0.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad K9 smd circle (at 0.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad K10 smd circle (at 1.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 447 +1V2)) + (pad L10 smd circle (at 1.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 209 "Net-(U3-PadL10)")) + (pad M10 smd circle (at 1.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 210 "Net-(U3-PadM10)")) + (pad N10 smd circle (at 1.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad T14 smd circle (at 5.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 211 "Net-(U3-PadT14)")) + (pad R14 smd circle (at 5.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 212 "Net-(U3-PadR14)")) + (pad P14 smd circle (at 5.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 213 "Net-(U3-PadP14)")) + (pad N14 smd circle (at 5.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 214 "Net-(U3-PadN14)")) + (pad M14 smd circle (at 5.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 215 "Net-(U3-PadM14)")) + (pad L14 smd circle (at 5.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 216 "Net-(U3-PadL14)")) + (pad K14 smd circle (at 5.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 217 "Net-(U3-PadK14)")) + (pad J14 smd circle (at 5.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 218 "Net-(U3-PadJ14)")) + (pad H14 smd circle (at 5.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 219 "Net-(U3-PadH14)")) + (pad H15 smd circle (at 6.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 220 "Net-(U3-PadH15)")) + (pad J15 smd circle (at 6.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad K15 smd circle (at 6.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 221 "Net-(U3-PadK15)")) + (pad L15 smd circle (at 6.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad M15 smd circle (at 6.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 222 "Net-(U3-PadM15)")) + (pad N15 smd circle (at 6.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 3 +3V3)) + (pad P15 smd circle (at 6.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 223 "Net-(U3-PadP15)")) + (pad R15 smd circle (at 6.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 224 "Net-(U3-PadR15)")) + (pad T15 smd circle (at 6.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 225 "Net-(U3-PadT15)")) + (pad N11 smd circle (at 2.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 460 /Control/M1)) + (pad M11 smd circle (at 2.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 226 "Net-(U3-PadM11)")) + (pad L11 smd circle (at 2.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 227 "Net-(U3-PadL11)")) + (pad K11 smd circle (at 2.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 228 "Net-(U3-PadK11)")) + (pad K12 smd circle (at 3.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(U3-PadK12)")) + (pad L12 smd circle (at 3.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(U3-PadL12)")) + (pad M12 smd circle (at 3.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(U3-PadM12)")) + (pad N12 smd circle (at 3.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 514 "Net-(U3-PadN12)")) + (pad T16 smd circle (at 7.5 7.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 2 GND)) + (pad R16 smd circle (at 7.5 6.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(U3-PadR16)")) + (pad P16 smd circle (at 7.5 5.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(U3-PadP16)")) + (pad N16 smd circle (at 7.5 4.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(U3-PadN16)")) + (pad M16 smd circle (at 7.5 3.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 235 "Net-(U3-PadM16)")) + (pad L16 smd circle (at 7.5 2.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 236 "Net-(U3-PadL16)")) + (pad K16 smd circle (at 7.5 1.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 237 "Net-(U3-PadK16)")) + (pad J16 smd circle (at 7.5 0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 238 "Net-(U3-PadJ16)")) + (pad H16 smd circle (at 7.5 -0.5 90) (size 0.4 0.4) (layers F.Cu F.Paste F.Mask) + (net 239 "Net-(U3-PadH16)")) + (model ${KISYS3DMOD}/Package_BGA.3dshapes/BGA-256_17.0x17.0mm_Layout16x16_P1.0mm_Ball0.5mm_Pad0.4mm_NSMD.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AA5A66) + (at 219.85 51.1 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AA5A58) + (at 219.85 49 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:PQFP-132_24x24mm_P0.635mm_MC68030 (layer F.Cu) (tedit 616BE190) (tstamp 61867E43) + (at 207.5815 145.669 180) + (descr "PQFP, 132 pins, 24mm sq body, 0.635mm pitch (https://www.intel.com/content/dam/www/public/us/en/documents/packaging-databooks/packaging-chapter-02-databook.pdf, http://www.nxp.com/docs/en/application-note/AN4388.pdf)") + (tags "PQFP 132") + (path /5F72F108/627CB7E6) + (autoplace_cost180 5) + (solder_mask_margin 0.03) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U1 (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value MC68030FE (at 0 1.27) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_line (start 12.12 -12.12) (end 12.12 -10.6) (layer F.SilkS) (width 0.12)) + (fp_line (start 10.6 -12.12) (end 12.12 -12.12) (layer F.SilkS) (width 0.12)) + (fp_line (start -11 -12) (end -12 -11) (layer F.Fab) (width 0.1)) + (fp_line (start -14.47 -14.47) (end -14.47 14.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 14.47 -14.47) (end -14.47 -14.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -11 -12) (end 12 -12) (layer F.Fab) (width 0.1)) + (fp_line (start 12 -12) (end 12 12) (layer F.Fab) (width 0.1)) + (fp_line (start 12 12) (end -12 12) (layer F.Fab) (width 0.1)) + (fp_line (start -12 12) (end -12 -11) (layer F.Fab) (width 0.1)) + (fp_line (start 14.47 -14.47) (end 14.47 14.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start 14.47 14.47) (end -14.47 14.47) (layer F.CrtYd) (width 0.05)) + (fp_line (start -10.6 -12.12) (end -12.12 -12.12) (layer F.SilkS) (width 0.12)) + (fp_line (start -12.12 -12.12) (end -12.12 -10.6) (layer F.SilkS) (width 0.12)) + (fp_line (start 10.6 12.12) (end 12.12 12.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 12.12 12.12) (end 12.12 10.6) (layer F.SilkS) (width 0.12)) + (fp_line (start -12.12 12.12) (end -12.12 10.6) (layer F.SilkS) (width 0.12)) + (fp_line (start -10.6 12.12) (end -12.12 12.12) (layer F.SilkS) (width 0.12)) + (fp_line (start -14.1 -10.6) (end -12.12 -10.6) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 18 smd roundrect (at -13.4 -10.16 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 19 smd roundrect (at -13.4 -9.525 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 20 smd roundrect (at -13.4 -8.89 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 21 smd roundrect (at -13.4 -8.255 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 4 /MC68k/A0)) + (pad 22 smd roundrect (at -13.4 -7.62 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 5 /MC68k/A1)) + (pad 23 smd roundrect (at -13.4 -6.985 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 6 /MC68k/A31)) + (pad 24 smd roundrect (at -13.4 -6.35 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 7 /MC68k/A30)) + (pad 25 smd roundrect (at -13.4 -5.715 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 26 smd roundrect (at -13.4 -5.08 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 8 /MC68k/A29)) + (pad 27 smd roundrect (at -13.4 -4.445 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 9 /MC68k/A28)) + (pad 28 smd roundrect (at -13.4 -3.81 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 10 /MC68k/A27)) + (pad 29 smd roundrect (at -13.4 -3.175 180) (size 1.635 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 11 /MC68k/A26)) + (pad 30 smd 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1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 499 /CPUBuf/CPU_~DS~)) + (pad 125 smd roundrect (at 5.08 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 500 /CPUBuf/CPU_~AS~)) + (pad 126 smd roundrect (at 4.445 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 501 /CPUBuf/CPU_~CBREQ~)) + (pad 127 smd roundrect (at 3.81 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 47 /Control/CPU_~CBACK~)) + (pad 128 smd roundrect (at 3.175 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 129 smd roundrect (at 2.54 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 48 /Control/CPU_~HALT~)) + (pad 130 smd roundrect (at 1.905 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 49 /Control/CPU_~BERR~)) + (pad 131 smd roundrect (at 1.27 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 50 /Control/CPU_~STERM~)) + (pad 132 smd roundrect (at 0.635 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 502 /CPUBuf/CPU_~DSACK~1)) + (pad 1 smd roundrect (at 0 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 2 smd roundrect (at -0.635 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 3 smd roundrect (at -1.27 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 503 /CPUBuf/CPU_~DSACK~0)) + (pad 4 smd roundrect (at -1.905 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 5 smd roundrect (at -2.54 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 6 smd roundrect (at -3.175 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 51 /Control/CPUCLK)) + (pad 7 smd roundrect (at -3.81 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 8 smd roundrect (at -4.445 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 9 smd roundrect (at -5.08 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 504 /CPUBuf/CPU_FC2)) + (pad 10 smd roundrect (at -5.715 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 505 /CPUBuf/CPU_FC1)) + (pad 11 smd roundrect (at -6.35 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 12 smd roundrect (at -6.985 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 506 /CPUBuf/CPU_FC0)) + (pad 13 smd roundrect (at -7.62 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 507 /CPUBuf/CPU_~RMC~)) + (pad 14 smd roundrect (at -8.255 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 52 "Net-(U1-Pad14)")) + (pad 15 smd roundrect (at -8.89 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 508 /CPUBuf/CPU_~CIOUT~)) + (pad 16 smd roundrect (at -9.525 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 53 "Net-(U1-Pad16)")) + (pad 17 smd roundrect (at -10.16 -13.4 180) (size 0.4 1.635) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Package_QFP.3dshapes/PQFP-132_24x24mm_P0.635mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm (layer F.Cu) (tedit 616CEBAA) (tstamp 61736EA1) + (at 218.55 74.9 180) + (descr "54-lead TSOP typ II package") + (tags "TSOPII TSOP2") + (path /63261D60/6327223F) + (solder_mask_margin 0.05) + (solder_paste_margin -0.03) + (attr smd) + (fp_text reference U5 (at 0 0) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value W9825G6KH-6 (at 0 0.95) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -4.08 -11.11) (end 5.08 -11.11) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 -11.11) (end 5.08 11.11) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 11.11) (end -5.08 11.11) (layer F.Fab) (width 0.1)) + (fp_line (start -5.08 11.11) (end -5.08 -10.11) (layer F.Fab) (width 0.1)) + (fp_line (start -4.08 -11.11) (end -5.08 -10.11) (layer F.Fab) (width 0.1)) + (fp_line (start -6.5 -10.9) (end -5.3 -10.9) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 -10.9) (end -5.3 -11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 -11.3) (end 5.3 -11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 11.3) (end 5.3 11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.3 -11.3) (end 5.3 -10.9) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.3 10.9) (end 5.3 11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 10.9) (end -5.3 11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -6.76 -11.36) (end 6.76 -11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.76 -11.36) (end 6.76 11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.76 11.36) (end -6.76 11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6.76 -11.36) (end -6.76 11.36) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -5.75 -10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at -5.75 -9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 279 /RAM/D16)) + (pad 3 smd roundrect (at -5.75 -8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 4 smd roundrect (at -5.75 -8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 280 /RAM/D17)) + (pad 5 smd roundrect (at -5.75 -7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 281 /RAM/D18)) + (pad 6 smd roundrect (at -5.75 -6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 7 smd roundrect (at -5.75 -5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 282 /RAM/D19)) + (pad 8 smd roundrect (at -5.75 -4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 283 /RAM/D20)) + (pad 9 smd roundrect (at -5.75 -4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 10 smd roundrect (at -5.75 -3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 284 /RAM/D21)) + (pad 11 smd roundrect (at -5.75 -2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 285 /RAM/D22)) + (pad 12 smd roundrect (at -5.75 -1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 13 smd roundrect (at -5.75 -0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 286 /RAM/D23)) + (pad 14 smd roundrect (at -5.75 0 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 15 smd roundrect (at -5.75 0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 287 /RAM/DQM2)) + (pad 16 smd roundrect (at -5.75 1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 269 /Control/RAM_~WE~)) + (pad 17 smd roundrect (at -5.75 2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 268 /Control/RAM_~CAS~)) + (pad 18 smd roundrect (at -5.75 3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 267 /Control/RAM_~RAS~)) + (pad 19 smd roundrect (at -5.75 4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 266 /Control/RAM_~CS~)) + (pad 20 smd roundrect (at -5.75 4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 265 /RAM/BA0)) + (pad 21 smd roundrect (at -5.75 5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 264 /RAM/BA1)) + (pad 22 smd roundrect (at -5.75 6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 263 /RAM/RA10)) + (pad 23 smd roundrect (at -5.75 7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 262 /RAM/RA0)) + (pad 24 smd roundrect (at -5.75 8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 261 /RAM/RA1)) + (pad 25 smd roundrect (at -5.75 8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 260 /RAM/RA2)) + (pad 26 smd roundrect (at -5.75 9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 259 /RAM/RA3)) + (pad 27 smd roundrect (at -5.75 10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 28 smd roundrect (at 5.75 10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 29 smd roundrect (at 5.75 9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 258 /RAM/RA4)) + (pad 30 smd roundrect (at 5.75 8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 257 /RAM/RA5)) + (pad 31 smd roundrect (at 5.75 8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 256 /RAM/RA6)) + (pad 32 smd roundrect (at 5.75 7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 255 /RAM/RA7)) + (pad 33 smd roundrect (at 5.75 6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 254 /RAM/RA8)) + (pad 34 smd roundrect (at 5.75 5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 253 /RAM/RA9)) + (pad 35 smd roundrect (at 5.75 4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 252 /RAM/RA11)) + (pad 36 smd roundrect (at 5.75 4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 251 /RAM/RA12)) + (pad 37 smd roundrect (at 5.75 3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 250 /RAM/CKE)) + (pad 38 smd roundrect (at 5.75 2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 288 /RAM/CLK23)) + (pad 39 smd roundrect (at 5.75 1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 289 /RAM/DQM3)) + (pad 40 smd roundrect (at 5.75 0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 41 smd roundrect (at 5.75 0 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 42 smd roundrect (at 5.75 -0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 290 /RAM/D24)) + (pad 43 smd roundrect (at 5.75 -1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 44 smd roundrect (at 5.75 -2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 291 /RAM/D25)) + (pad 45 smd roundrect (at 5.75 -3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 292 /RAM/D26)) + (pad 46 smd roundrect (at 5.75 -4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 47 smd roundrect (at 5.75 -4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 293 /RAM/D27)) + (pad 48 smd roundrect (at 5.75 -5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 294 /RAM/D28)) + (pad 49 smd roundrect (at 5.75 -6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 50 smd roundrect (at 5.75 -7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 295 /RAM/D29)) + (pad 51 smd roundrect (at 5.75 -8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 296 /RAM/D30)) + (pad 52 smd roundrect (at 5.75 -8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 53 smd roundrect (at 5.75 -9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 297 /RAM/D31)) + (pad 54 smd roundrect (at 5.75 -10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSOP-II-54_22.2x10.16mm_P0.8mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:R_0603 (layer F.Cu) (tedit 617287CD) (tstamp 619A2E13) + (at 194.05 45 180) + (tags resistor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value R_0603 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 51 /Control/CPUCLK)) + (pad 1 smd roundrect (at -0.8 0 180) (size 0.7 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 51 /Control/CPUCLK)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:R_0603 (layer F.Cu) (tedit 617287D0) (tstamp 619A2E43) + (at 194.05 43.5 180) + (tags resistor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value R_0603 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.8 0 180) (size 0.7 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 56 /Control/FPUCLK)) + (pad 2 smd roundrect (at 0.8 0 180) (size 0.7 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 56 /Control/FPUCLK)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AE5030) + (at 197.35 44.05 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61ABC93F) + (at 231.35 104.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/6372B95C) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U22 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHCT573PW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 502 /CPUBuf/CPU_~DSACK~1)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 503 /CPUBuf/CPU_~DSACK~0)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 374 "Net-(U22-Pad17)")) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 373 "Net-(U22-Pad16)")) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 372 "Net-(U22-Pad15)")) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 371 "Net-(U22-Pad14)")) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 370 "Net-(U22-Pad13)")) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 369 "Net-(U22-Pad12)")) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 368 "Net-(U22-Pad9)")) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 367 "Net-(U22-Pad8)")) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 366 "Net-(U22-Pad7)")) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 365 "Net-(U22-Pad6)")) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 364 "Net-(U22-Pad5)")) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 363 "Net-(U22-Pad4)")) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 362 /Control/CPU_~DSACK~0)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 361 /Control/CPU_~DSACK~1)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 552 /CPUBuf/DSACK~OE~)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61ABC931) + (at 233.8 100 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC31C6) + (at 202.6 38.8) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC321A) + (at 217.85 38.8) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC3244) + (at 199.35 38.8) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC319C) + (at 214.6 38.8) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC30A0) + (at 219.85 40.8 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC2C32) + (at 219.85 59.3 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC32EC) + (at 219.85 56.05 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC2BDE) + (at 219.85 44.05 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC30CA) + (at 217.75 61.3 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 6178EECF) + (at 209.65 61.3) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AC311E) + (at 199.45 61.3 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 6178EEA5) + (at 207.55 61.3 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 447 +1V2)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61795B84) + (at 203.35 61.3 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model 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-0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AE5084) + (at 197.35 40.8 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AE505A) + (at 197.35 59.4 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 61AE4FB2) + (at 197.35 56.05 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:Crystal_SMD_3225-4Pin_3.2x2.5mm (layer F.Cu) (tedit 5F326081) (tstamp 61AC3042) + (at 229.2 54.85 90) + (descr "SMD Crystal SERIES SMD3225/4 http://www.txccrystal.com/images/pdf/7m-accuracy.pdf, 3.2x2.5mm^2 package") + (tags "SMD SMT crystal") + (path /5F723173/63C6B24E) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference U6 (at 0 0 90) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_text value 50M (at 0 0.75 90) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -1.6 -1.25) (end -1.6 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 1.25) (end 1.6 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 1.25) (end 1.6 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -1.25) (end -1.6 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.25) (end -0.6 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -2.15 -0.85) (end -2.15 1.75) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.15 1.75) (end 1.1 1.75) (layer F.SilkS) (width 0.1524)) + (fp_line (start -2.1 -1.7) (end -2.1 1.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.1 1.7) (end 2.1 1.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.1 1.7) (end 2.1 -1.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.1 -1.7) (end -2.1 -1.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -2.25 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 4 smd roundrect (at -1.1 -0.85 90) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 448 "Net-(U6-Pad4)")) + (pad 3 smd roundrect (at 1.1 -0.85 90) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 449 "Net-(U6-Pad3)")) + (pad 2 smd roundrect (at 1.1 0.85 90) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 450 "Net-(U6-Pad2)")) + (pad 1 smd roundrect (at -1.1 0.85 90) (size 1.4 1.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 451 "Net-(U6-Pad1)")) + (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_3225-4Pin_3.2x2.5mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:SOIC-16_3.9mm (layer F.Cu) (tedit 5FDA018C) (tstamp 61AB1A60) + (at 251.3965 55.5625 270) + (descr "SOIC, 16 Pin (JEDEC MS-012AC, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_16.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "SOIC SO") + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference REF** (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value SOIC-16_3.9mm (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -5.2 -3.7) (end -5.2 3.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 5.2 -3.7) (end -5.2 -3.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 5.2 3.7) (end 5.2 -3.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.2 3.7) (end 5.2 3.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.975 1.95) (end -4.95 0.975) (layer F.Fab) (width 0.1)) + (fp_line (start 4.95 1.95) (end -3.975 1.95) (layer F.Fab) (width 0.1)) + (fp_line (start 4.95 -1.95) (end 4.95 1.95) (layer F.Fab) (width 0.1)) + (fp_line (start -4.95 -1.95) (end 4.95 -1.95) (layer F.Fab) (width 0.1)) + (fp_line (start -4.95 0.975) (end -4.95 -1.95) (layer F.Fab) (width 0.1)) + (fp_line (start -5.06 0) (end -5.06 3.45) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.06 0) (end -5.06 -1.95) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.06 0) (end 5.06 1.95) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.06 0) (end 5.06 -1.95) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 0 270) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -4.445 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at -3.175 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 3 smd roundrect (at -1.905 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 4 smd roundrect (at -0.635 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 5 smd roundrect (at 0.635 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 6 smd roundrect (at 1.905 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 7 smd roundrect (at 3.175 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 8 smd roundrect (at 4.445 2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 9 smd roundrect (at 4.445 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 10 smd roundrect (at 3.175 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 11 smd roundrect (at 1.905 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 12 smd roundrect (at 0.635 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 13 smd roundrect (at -0.635 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 14 smd roundrect (at -1.905 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 15 smd roundrect (at -3.175 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 16 smd roundrect (at -4.445 -2.475) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-16_3.9x9.9mm_P1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:USB_Micro-B_ShouHan_MicroXNJ (layer F.Cu) (tedit 602BA043) (tstamp 61AC0867) + (at 232.75 30 90) + (descr http://www.molex.com/pdm_docs/sd/1050170001_sd.pdf) + (tags "Micro-USB SMD Typ-B") + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference REF** (at -0.45 0) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value USB_Micro-B_ShouHan_MicroXNJ (at -4.4 0) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_line (start -2.4225 1.1) (end -2.2125 1.1) (layer F.Fab) (width 0.1)) + (fp_line (start -2.4225 1.5) (end -2.2125 1.5) (layer F.Fab) (width 0.1)) + (fp_line (start -2.4225 1.5) (end -2.4225 1.1) (layer F.Fab) (width 0.1)) + (fp_line (start -2.2125 1.1) (end -2.0125 1.3) (layer F.Fab) (width 0.1)) + (fp_line (start -2.0125 1.3) (end -2.2125 1.5) (layer F.Fab) (width 0.1)) + (fp_line (start -2.6125 1.7) (end -2.1625 1.7) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.6125 1.7) (end -2.6125 1.25) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.6125 -3.9) (end -2.6125 -3.45) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.25 -3.9) (end -2.6125 -3.9) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.35 3.9) (end 1.9875 3.9) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.989204 3.75) (end -2.4625 3.75) (layer F.Fab) (width 0.1)) + (fp_line (start -2.4625 3.75) (end -2.4625 -3.75) (layer F.Fab) (width 0.1)) + (fp_line (start 2.989204 3.75) (end 2.989204 -3.75) (layer F.Fab) (width 0.1)) + (fp_line (start 2.6 3) (end 2.6 -3) (layer F.Fab) (width 0.1)) + (fp_line (start 2.989204 -3.75) (end -2.4625 -3.75) (layer F.Fab) (width 0.1)) + (fp_line (start 2.35 -3.9) (end 1.9875 -3.9) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.25 3.9) (end -2.6125 3.9) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.6125 3.9) (end -2.6125 3.45) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.24 4.4) (end -2.86 4.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.86 4.4) (end -2.86 -4.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.86 -4.4) (end 3.24 -4.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.24 4.4) (end 3.24 -4.4) (layer F.CrtYd) (width 0.05)) + (fp_text user "PCB Edge" (at 2.05 0) (layer Dwgs.User) + (effects (font (size 0.5 0.5) (thickness 0.08))) + ) + (fp_text user %R (at -3.5 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 6 smd roundrect (at 0.875 -0.8 180) (size 0.6 1.35) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 6 thru_hole circle (at -1.8 2.425 180) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask)) + (pad 2 smd roundrect (at -1.775 0.65 180) (size 0.4 1.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (solder_mask_margin 0.04) (solder_paste_margin -0.05)) + (pad 1 smd roundrect (at -1.775 1.3 180) (size 0.4 1.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (solder_mask_margin 0.04) (solder_paste_margin -0.05)) + (pad 5 smd roundrect (at -1.775 -1.3 180) (size 0.4 1.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (solder_mask_margin 0.04) (solder_paste_margin -0.05)) + (pad 4 smd roundrect (at -1.775 -0.65 180) (size 0.4 1.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (solder_mask_margin 0.04) (solder_paste_margin -0.05)) + (pad 3 smd roundrect (at -1.775 0 180) (size 0.4 1.25) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (solder_mask_margin 0.04) (solder_paste_margin -0.05)) + (pad 6 thru_hole circle (at -1.8 -2.425 180) (size 1.3 1.3) (drill 0.7) (layers *.Cu *.Mask)) + (pad 6 smd roundrect (at 0.875 0.8 180) (size 0.6 1.35) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 6 thru_hole oval (at 0.85 3.6) (size 1.07 1.9) (drill oval 0.5 1.3) (layers *.Cu *.Mask)) + (pad 6 thru_hole oval (at 0.85 -3.6 180) (size 1.07 1.9) (drill oval 0.5 1.3) (layers *.Cu *.Mask)) + (model ${KISYS3DMOD}/Connector_USB.3dshapes/USB_Micro-B_Molex_47346-0001.wrl + (offset (xyz -0.6 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:DIN41612_R_3x32_Male_Vertical_THT (layer B.Cu) (tedit 5EAFCB80) (tstamp 61882B84) + (at 268.432 73.872 180) + (descr "DIN41612 connector, type R, Vertical, 3 rows 32 pins wide, https://www.erni-x-press.com/de/downloads/kataloge/englische_kataloge/erni-din41612-iec60603-2-e.pdf") + (tags "DIN 41612 IEC 60603 R") + (fp_text reference REF** (at 2.54 9.13) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value DIN41612_R_3x32_Male_Vertical_THT (at 2.54 -87.87) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -1.81 3.13) (end 4.39 3.13) (layer B.Fab) (width 0.1)) + (fp_line (start 4.39 3.13) (end 4.39 2.13) (layer B.Fab) (width 0.1)) + (fp_line (start 4.39 2.13) (end 6.89 2.13) (layer B.Fab) (width 0.1)) + (fp_line (start 6.89 2.13) (end 6.89 -80.87) (layer B.Fab) (width 0.1)) + (fp_line (start 6.89 -80.87) (end 4.39 -80.87) (layer B.Fab) (width 0.1)) + (fp_line (start 4.39 -80.87) (end 4.39 -81.87) (layer B.Fab) (width 0.1)) + (fp_line (start 4.39 -81.87) (end -1.81 -81.87) (layer B.Fab) (width 0.1)) + (fp_line (start -1.81 -81.87) (end -1.81 3.13) (layer B.Fab) (width 0.1)) + (fp_line (start -3.01 -83.37) (end -0.76 -83.37) (layer B.Fab) (width 0.1)) + (fp_line (start -0.76 -83.37) (end -0.76 -81.87) (layer B.Fab) (width 0.1)) + (fp_line (start 4.39 -81.87) (end 5.24 -81.87) (layer B.Fab) (width 0.1)) + (fp_line (start 5.24 -81.87) (end 5.24 -83.37) (layer B.Fab) (width 0.1)) + (fp_line (start 5.24 -83.37) (end 8.09 -83.37) (layer B.Fab) (width 0.1)) + (fp_line (start -3.01 4.63) (end -0.76 4.63) (layer B.Fab) (width 0.1)) + (fp_line (start -0.76 4.63) (end -0.76 3.13) (layer B.Fab) (width 0.1)) + (fp_line (start 4.39 3.13) (end 5.24 3.13) (layer B.Fab) (width 0.1)) + (fp_line (start 5.24 3.13) (end 5.24 4.63) (layer B.Fab) (width 0.1)) + (fp_line (start 5.24 4.63) (end 8.09 4.63) (layer B.Fab) (width 0.1)) + (fp_line (start -3.01 8.13) (end 8.09 8.13) (layer B.Fab) (width 0.1)) + (fp_line (start 8.09 8.13) (end 8.09 -86.87) (layer B.Fab) (width 0.1)) + (fp_line (start 8.09 -86.87) (end -3.01 -86.87) (layer B.Fab) (width 0.1)) + (fp_line (start -3.01 -86.87) (end -3.01 8.13) (layer B.Fab) (width 0.1)) + (fp_line (start -3.12 8.24) (end 8.2 8.24) (layer B.SilkS) (width 0.12)) + (fp_line (start 8.2 8.24) (end 8.2 -86.98) (layer B.SilkS) (width 0.12)) + (fp_line (start 8.2 -86.98) (end -3.12 -86.98) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.12 -86.98) (end -3.12 8.24) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.5 8.63) (end 8.59 8.63) (layer B.CrtYd) (width 0.05)) + (fp_line (start 8.59 8.63) (end 8.59 -87.37) (layer B.CrtYd) (width 0.05)) + (fp_line (start 8.59 -87.37) (end -3.5 -87.37) (layer B.CrtYd) (width 0.05)) + (fp_line (start -3.5 -87.37) (end -3.5 8.63) (layer B.CrtYd) (width 0.05)) + (fp_line (start -3.31 0) (end -3.99 0.3) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.99 0.3) (end -3.99 -0.3) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.99 -0.3) (end -3.31 0) (layer B.SilkS) (width 0.12)) + (fp_line (start -3.01 0.5) (end -2.31 0) (layer B.Fab) (width 0.1)) + (fp_line (start -2.31 0) (end -3.01 -0.5) (layer B.Fab) (width 0.1)) + (fp_line (start -1.81 3.131) (end 4.39 3.131) (layer B.SilkS) (width 0.12)) + (fp_line (start 4.39 3.131) (end 4.39 2.131) (layer B.SilkS) (width 0.12)) + (fp_line (start 4.39 2.131) (end 6.89 2.131) (layer B.SilkS) (width 0.12)) + (fp_line (start 6.89 2.131) (end 6.89 -80.87) (layer B.SilkS) (width 0.12)) + (fp_line (start 6.89 -80.87) (end 4.39 -80.87) (layer B.SilkS) (width 0.12)) + (fp_line (start 4.39 -80.87) (end 4.39 -81.87) (layer B.SilkS) (width 0.12)) + (fp_line (start 4.39 -81.87) (end -1.81 -81.87) (layer B.SilkS) (width 0.12)) + (fp_line (start -1.81 -81.87) (end -1.81 3.131) (layer B.SilkS) (width 0.12)) + (fp_text user %R (at 2.54 -39.37) (layer B.Fab) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (pad "" np_thru_hole circle (at 2.24 -84.37 180) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 2.24 5.63 180) (size 2.85 2.85) (drill 2.85) (layers *.Cu *.Mask)) + (pad C32 thru_hole circle (at 5.08 -78.74 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C31 thru_hole circle (at 5.08 -76.2 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C30 thru_hole circle (at 5.08 -73.66 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C29 thru_hole circle (at 5.08 -71.12 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C28 thru_hole circle (at 5.08 -68.58 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C27 thru_hole circle (at 5.08 -66.04 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C26 thru_hole circle (at 5.08 -63.5 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C25 thru_hole circle (at 5.08 -60.96 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C24 thru_hole circle (at 5.08 -58.42 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C23 thru_hole circle (at 5.08 -55.88 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C22 thru_hole circle (at 5.08 -53.34 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C21 thru_hole circle (at 5.08 -50.8 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C20 thru_hole circle (at 5.08 -48.26 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C19 thru_hole circle (at 5.08 -45.72 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C18 thru_hole circle (at 5.08 -43.18 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C17 thru_hole circle (at 5.08 -40.64 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C16 thru_hole circle (at 5.08 -38.1 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C15 thru_hole circle (at 5.08 -35.56 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C14 thru_hole circle (at 5.08 -33.02 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C13 thru_hole circle (at 5.08 -30.48 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C12 thru_hole circle (at 5.08 -27.94 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C11 thru_hole circle (at 5.08 -25.4 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C10 thru_hole circle (at 5.08 -22.86 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C9 thru_hole circle (at 5.08 -20.32 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C8 thru_hole circle (at 5.08 -17.78 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C7 thru_hole circle (at 5.08 -15.24 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C6 thru_hole circle (at 5.08 -12.7 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C5 thru_hole circle (at 5.08 -10.16 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C4 thru_hole circle (at 5.08 -7.62 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C3 thru_hole circle (at 5.08 -5.08 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C2 thru_hole circle (at 5.08 -2.54 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad C1 thru_hole circle (at 5.08 0 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B32 thru_hole circle (at 2.54 -78.74 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B31 thru_hole circle (at 2.54 -76.2 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B30 thru_hole circle (at 2.54 -73.66 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B29 thru_hole circle (at 2.54 -71.12 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B28 thru_hole circle (at 2.54 -68.58 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B27 thru_hole circle (at 2.54 -66.04 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B26 thru_hole circle (at 2.54 -63.5 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B25 thru_hole circle (at 2.54 -60.96 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B24 thru_hole circle (at 2.54 -58.42 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B23 thru_hole circle (at 2.54 -55.88 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B22 thru_hole circle (at 2.54 -53.34 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B21 thru_hole circle (at 2.54 -50.8 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B20 thru_hole circle (at 2.54 -48.26 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B19 thru_hole circle (at 2.54 -45.72 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B18 thru_hole circle (at 2.54 -43.18 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B17 thru_hole circle (at 2.54 -40.64 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B16 thru_hole circle (at 2.54 -38.1 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B15 thru_hole circle (at 2.54 -35.56 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B14 thru_hole circle (at 2.54 -33.02 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B13 thru_hole circle (at 2.54 -30.48 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B12 thru_hole circle (at 2.54 -27.94 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B11 thru_hole circle (at 2.54 -25.4 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B10 thru_hole circle (at 2.54 -22.86 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B9 thru_hole circle (at 2.54 -20.32 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B8 thru_hole circle (at 2.54 -17.78 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B7 thru_hole circle (at 2.54 -15.24 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B6 thru_hole circle (at 2.54 -12.7 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B5 thru_hole circle (at 2.54 -10.16 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B4 thru_hole circle (at 2.54 -7.62 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B3 thru_hole circle (at 2.54 -5.08 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B2 thru_hole circle (at 2.54 -2.54 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad B1 thru_hole circle (at 2.54 0 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A32 thru_hole circle (at 0 -78.74 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A31 thru_hole circle (at 0 -76.2 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A30 thru_hole circle (at 0 -73.66 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A29 thru_hole circle (at 0 -71.12 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A28 thru_hole circle (at 0 -68.58 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A27 thru_hole circle (at 0 -66.04 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A26 thru_hole circle (at 0 -63.5 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A25 thru_hole circle (at 0 -60.96 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A24 thru_hole circle (at 0 -58.42 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A23 thru_hole circle (at 0 -55.88 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A22 thru_hole circle (at 0 -53.34 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A21 thru_hole circle (at 0 -50.8 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A20 thru_hole circle (at 0 -48.26 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A19 thru_hole circle (at 0 -45.72 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A18 thru_hole circle (at 0 -43.18 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A17 thru_hole circle (at 0 -40.64 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A16 thru_hole circle (at 0 -38.1 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A15 thru_hole circle (at 0 -35.56 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A14 thru_hole circle (at 0 -33.02 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A13 thru_hole circle (at 0 -30.48 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A12 thru_hole circle (at 0 -27.94 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A11 thru_hole circle (at 0 -25.4 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A10 thru_hole circle (at 0 -22.86 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A9 thru_hole circle (at 0 -20.32 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A8 thru_hole circle (at 0 -17.78 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A7 thru_hole circle (at 0 -15.24 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A6 thru_hole circle (at 0 -12.7 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A5 thru_hole circle (at 0 -10.16 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A4 thru_hole circle (at 0 -7.62 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A3 thru_hole circle (at 0 -5.08 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A2 thru_hole circle (at 0 -2.54 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask)) + (pad A1 thru_hole roundrect (at 0 0 180) (size 1.55 1.55) (drill 1) (layers *.Cu *.Mask) (roundrect_rratio 0.16129)) + (model ${KISYS3DMOD}/Connector_DIN.3dshapes/DIN41612_R_3x32_Male_Vertical_THT.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:Xunpu_TF-115_microSD (layer F.Cu) (tedit 606CA97D) (tstamp 61A9D25C) + (at 265.6 56.55) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at -2.55 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value Xunpu_TF-115_microSD (at -1.65 0 90) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -8.25 7.6) (end 6.15 7.6) (layer F.SilkS) (width 0.127)) + (fp_line (start 5.45 -0.9) (end 5.45 7.4) (layer F.Fab) (width 0.127)) + (fp_line (start 6.45 -4.6) (end 5.45 -0.9) (layer F.Fab) (width 0.127)) + (fp_line (start 6.45 -7.35) (end 6.45 -4.6) (layer F.Fab) (width 0.127)) + (fp_line (start -8.05 -7.35) (end 6.45 -7.35) (layer F.Fab) (width 0.127)) + (fp_line (start -8.05 7.4) (end -8.05 -7.35) (layer F.Fab) (width 0.127)) + (fp_line (start -8.25 7.6) (end -8.25 -7.55) (layer F.SilkS) (width 0.127)) + (fp_line (start -8.25 -7.55) (end 6.15 -7.55) (layer F.SilkS) (width 0.127)) + (fp_line (start -8.05 7.4) (end 5.45 7.4) (layer F.Fab) (width 0.127)) + (fp_line (start -8.85 8.55) (end 6.9 8.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.9 8.55) (end 6.9 -8.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.85 -8.55) (end 6.9 -8.55) (layer F.CrtYd) (width 0.05)) + (fp_line (start -8.85 -8.55) (end -8.85 8.55) (layer F.CrtYd) (width 0.05)) + (pad 10 smd roundrect (at 2.75 7.75 90) (size 1.2 2.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 10 smd roundrect (at -6.85 7.8 90) (size 1.2 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 9 smd roundrect (at -7.85 6.6 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 10 smd roundrect (at -6.85 -6.85 90) (size 1.6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 10 smd roundrect (at 2.75 -7.75 90) (size 1.2 2.2) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -7.85 -2.2 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at -7.85 -1.1 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 3 smd roundrect (at -7.85 0 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 4 smd roundrect (at -7.85 1.1 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 5 smd roundrect (at -7.85 2.2 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 6 smd roundrect (at -7.85 3.3 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 7 smd roundrect (at -7.85 4.4 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 8 smd roundrect (at -7.85 5.5 90) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad "" np_thru_hole circle (at 3.15 4.95 90) (size 1 1) (drill 1) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 3.15 -3.05 90) (size 1 1) (drill 1) (layers *.Cu *.Mask)) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 6182787D) + (at 209.9 88.35 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm (layer F.Cu) (tedit 616CEBAA) (tstamp 61736BBB) + (at 200.85 74.9 180) + (descr "54-lead TSOP typ II package") + (tags "TSOPII TSOP2") + (path /63261D60/6326A531) + (solder_mask_margin 0.05) + (solder_paste_margin -0.03) + (attr smd) + (fp_text reference U4 (at 0 0) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value W9825G6KH-6 (at 0 0.95) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -6.76 -11.36) (end -6.76 11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.76 11.36) (end -6.76 11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.76 -11.36) (end 6.76 11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start -6.76 -11.36) (end 6.76 -11.36) (layer F.CrtYd) (width 0.05)) + (fp_line (start -5.3 10.9) (end -5.3 11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.3 10.9) (end 5.3 11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start 5.3 -11.3) (end 5.3 -10.9) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 11.3) (end 5.3 11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 -11.3) (end 5.3 -11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -5.3 -10.9) (end -5.3 -11.3) (layer F.SilkS) (width 0.12)) + (fp_line (start -6.5 -10.9) (end -5.3 -10.9) (layer F.SilkS) (width 0.12)) + (fp_line (start -4.08 -11.11) (end -5.08 -10.11) (layer F.Fab) (width 0.1)) + (fp_line (start -5.08 11.11) (end -5.08 -10.11) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 11.11) (end -5.08 11.11) (layer F.Fab) (width 0.1)) + (fp_line (start 5.08 -11.11) (end 5.08 11.11) (layer F.Fab) (width 0.1)) + (fp_line (start -4.08 -11.11) (end 5.08 -11.11) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 54 smd roundrect (at 5.75 -10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 53 smd roundrect (at 5.75 -9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 240 /RAM/D15)) + (pad 52 smd roundrect (at 5.75 -8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 51 smd roundrect (at 5.75 -8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 241 /RAM/D14)) + (pad 50 smd roundrect (at 5.75 -7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 242 /RAM/D13)) + (pad 49 smd roundrect (at 5.75 -6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 48 smd roundrect (at 5.75 -5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 243 /RAM/D12)) + (pad 47 smd roundrect (at 5.75 -4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 244 /RAM/D11)) + (pad 46 smd roundrect (at 5.75 -4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 45 smd roundrect (at 5.75 -3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 245 /RAM/D10)) + (pad 44 smd roundrect (at 5.75 -2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 246 /RAM/D9)) + (pad 43 smd roundrect (at 5.75 -1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 42 smd roundrect (at 5.75 -0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 247 /RAM/D8)) + (pad 41 smd roundrect (at 5.75 0 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 40 smd roundrect (at 5.75 0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 39 smd roundrect (at 5.75 1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 248 /RAM/DQM1)) + (pad 38 smd roundrect (at 5.75 2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 249 /RAM/CLK01)) + (pad 37 smd roundrect (at 5.75 3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 250 /RAM/CKE)) + (pad 36 smd roundrect (at 5.75 4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 251 /RAM/RA12)) + (pad 35 smd roundrect (at 5.75 4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 252 /RAM/RA11)) + (pad 34 smd roundrect (at 5.75 5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 253 /RAM/RA9)) + (pad 33 smd roundrect (at 5.75 6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 254 /RAM/RA8)) + (pad 32 smd roundrect (at 5.75 7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 255 /RAM/RA7)) + (pad 31 smd roundrect (at 5.75 8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 256 /RAM/RA6)) + (pad 30 smd roundrect (at 5.75 8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 257 /RAM/RA5)) + (pad 29 smd roundrect (at 5.75 9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 258 /RAM/RA4)) + (pad 28 smd roundrect (at 5.75 10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 27 smd roundrect (at -5.75 10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 26 smd roundrect (at -5.75 9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 259 /RAM/RA3)) + (pad 25 smd roundrect (at -5.75 8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 260 /RAM/RA2)) + (pad 24 smd roundrect (at -5.75 8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 261 /RAM/RA1)) + (pad 23 smd roundrect (at -5.75 7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 262 /RAM/RA0)) + (pad 22 smd roundrect (at -5.75 6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 263 /RAM/RA10)) + (pad 21 smd roundrect (at -5.75 5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 264 /RAM/BA1)) + (pad 20 smd roundrect (at -5.75 4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 265 /RAM/BA0)) + (pad 19 smd roundrect (at -5.75 4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 266 /Control/RAM_~CS~)) + (pad 18 smd roundrect (at -5.75 3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 267 /Control/RAM_~RAS~)) + (pad 17 smd roundrect (at -5.75 2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 268 /Control/RAM_~CAS~)) + (pad 16 smd roundrect (at -5.75 1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 269 /Control/RAM_~WE~)) + (pad 15 smd roundrect (at -5.75 0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 270 /RAM/DQM0)) + (pad 14 smd roundrect (at -5.75 0 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 13 smd roundrect (at -5.75 -0.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 271 /RAM/D7)) + (pad 12 smd roundrect (at -5.75 -1.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at -5.75 -2.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 272 /RAM/D6)) + (pad 10 smd roundrect (at -5.75 -3.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 273 /RAM/D5)) + (pad 9 smd roundrect (at -5.75 -4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 8 smd roundrect (at -5.75 -4.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 274 /RAM/D4)) + (pad 7 smd roundrect (at -5.75 -5.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 275 /RAM/D3)) + (pad 6 smd roundrect (at -5.75 -6.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 5 smd roundrect (at -5.75 -7.2 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 276 /RAM/D2)) + (pad 4 smd roundrect (at -5.75 -8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 277 /RAM/D1)) + (pad 3 smd roundrect (at -5.75 -8.8 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at -5.75 -9.6 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 278 /RAM/D0)) + (pad 1 smd roundrect (at -5.75 -10.4 180) (size 1.51 0.458) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSOP-II-54_22.2x10.16mm_P0.8mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188EED4) + (at 222.975 90.8) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/63262F0F) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U28 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 180) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 445 /Control/CPU_D~OE~)) + (pad 18 smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 290 /RAM/D24)) + (pad 17 smd roundrect (at -0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 291 /RAM/D25)) + (pad 16 smd roundrect (at -0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 292 /RAM/D26)) + (pad 15 smd roundrect (at 0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 293 /RAM/D27)) + (pad 14 smd roundrect (at 0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 294 /RAM/D28)) + (pad 13 smd roundrect (at 1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 295 /RAM/D29)) + (pad 12 smd roundrect (at 2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 296 /RAM/D30)) + (pad 11 smd roundrect (at 2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 297 /RAM/D31)) + (pad 10 smd roundrect (at 2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 486 /CPUBuf/CPU_D31)) + (pad 8 smd roundrect (at 1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 485 /CPUBuf/CPU_D30)) + (pad 7 smd roundrect (at 0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 484 /CPUBuf/CPU_D29)) + (pad 6 smd roundrect (at 0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 483 /CPUBuf/CPU_D28)) + (pad 5 smd roundrect (at -0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 482 /CPUBuf/CPU_D27)) + (pad 4 smd roundrect (at -0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 481 /CPUBuf/CPU_D26)) + (pad 3 smd roundrect (at -1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 480 /CPUBuf/CPU_D25)) + (pad 2 smd roundrect (at -2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 479 /CPUBuf/CPU_D24)) + (pad 1 smd roundrect (at -2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 446 /Control/CPU_DDIR)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618DDCA1) + (at 226.2 85.8 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618DDC93) + (at 226.2 65 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618DDC85) + (at 226.2 75.7 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618DDC77) + (at 226.2 83.2 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618DDC69) + (at 226.2 79.4 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618A2E3B) + (at 193.2 77 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618A2E2D) + (at 193.2 81.8 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618A1429) + (at 210.9 81.8 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618A13E3) + (at 210.9 77 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 618F11FE) + (at 208.5 65 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 6189FEEB) + (at 208.5 75.7 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 6189FEDD) + (at 208.5 85.8 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 6189FE85) + (at 208.5 79.4 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616CEBED) (tstamp 6189FE77) + (at 208.5 83.2 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61891CD1) + (at 206.8115 130.302) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61882E22) + (at 255.2 75.575 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/622CABC7) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U17 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 396 /PDSBuf/D~OE~)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 429 /PDS/D24)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 430 /PDS/D25)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 431 /PDS/D26)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 432 /PDS/D27)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 433 /PDS/D28)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 434 /PDS/D29)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 435 /PDS/D30)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 436 /PDS/D31)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 437 /PDSBuf/IOC_D31)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 438 /PDSBuf/IOC_D30)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 439 /PDSBuf/IOC_D29)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 440 /PDSBuf/IOC_D28)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 441 /PDSBuf/IOC_D27)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 442 /PDSBuf/IOC_D26)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 443 /PDSBuf/IOC_D25)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 444 /PDSBuf/IOC_D24)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 379 /PDSBuf/DDIR)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61882E14) + (at 257.65 71.35 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188172E) + (at 231.35 132.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/629FA6C8) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U21 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244 (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 13 /MC68k/A24)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 550 /CPUBuf/FSB_A28)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 12 /MC68k/A25)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 551 /CPUBuf/FSB_A29)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 11 /MC68k/A26)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 519 /CPUBuf/FSB_A30)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 10 /MC68k/A27)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 520 /CPUBuf/FSB_A31)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 6 /MC68k/A31)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 515 /CPUBuf/FSB_A24)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 7 /MC68k/A30)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 516 /CPUBuf/FSB_A25)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 8 /MC68k/A29)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 517 /CPUBuf/FSB_A26)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 9 /MC68k/A28)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 518 /CPUBuf/FSB_A27)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61881720) + (at 233.8 137 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61881712) + (at 233.8 146 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61881704) + (at 233.8 155 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 618816F6) + (at 233.8 128 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 618816D3) + (at 231.35 141.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/629F220F) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U20 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244 (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 526 /CPUBuf/FSB_A19)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 17 /MC68k/A20)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 527 /CPUBuf/FSB_A18)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 16 /MC68k/A21)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 528 /CPUBuf/FSB_A17)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 15 /MC68k/A22)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 529 /CPUBuf/FSB_A16)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 14 /MC68k/A23)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 522 /CPUBuf/FSB_A23)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 18 /MC68k/A19)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 523 /CPUBuf/FSB_A22)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 19 /MC68k/A18)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 524 /CPUBuf/FSB_A21)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 20 /MC68k/A17)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 525 /CPUBuf/FSB_A20)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 21 /MC68k/A16)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 618816B0) + (at 231.35 150.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/629E6572) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U19 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244 (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 30 /MC68k/A8)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 534 /CPUBuf/FSB_A12)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 29 /MC68k/A9)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 535 /CPUBuf/FSB_A13)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 27 /MC68k/A10)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 536 /CPUBuf/FSB_A14)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 26 /MC68k/A11)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 537 /CPUBuf/FSB_A15)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 22 /MC68k/A15)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 530 /CPUBuf/FSB_A8)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 23 /MC68k/A14)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 531 /CPUBuf/FSB_A9)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 24 /MC68k/A13)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 532 /CPUBuf/FSB_A10)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 25 /MC68k/A12)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 533 /CPUBuf/FSB_A11)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188168D) + (at 231.35 159.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/629FEFBA) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U18 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244 (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 546 /CPUBuf/FSB_A3)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 34 /MC68k/A4)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 547 /CPUBuf/FSB_A2)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 33 /MC68k/A5)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 548 /CPUBuf/FSB_A1)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 32 /MC68k/A6)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 549 /CPUBuf/FSB_A0)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 31 /MC68k/A7)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 544 /CPUBuf/FSB_A7)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 35 /MC68k/A3)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 543 /CPUBuf/FSB_A6)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 36 /MC68k/A2)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 542 /CPUBuf/FSB_A5)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 5 /MC68k/A1)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 541 /CPUBuf/FSB_A4)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 4 /MC68k/A0)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 6188167F) + (at 233.8 119 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61ABC89D) + (at 231.35 114.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/62A2CF45) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U24 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 507 /CPUBuf/CPU_~RMC~)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 538 /CPUBuf/FSB_FC0)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 495 /CPUBuf/CPU_R~W~)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 376 "Net-(U24-Pad5)")) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 504 /CPUBuf/CPU_FC2)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 377 "Net-(U24-Pad7)")) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 505 /CPUBuf/CPU_FC1)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 378 "Net-(U24-Pad9)")) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 560 /CPUBuf/FSB_~RMC~)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 521 /CPUBuf/FSB_R~W~)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 540 /CPUBuf/FSB_FC2)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 506 /CPUBuf/CPU_FC0)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 539 /CPUBuf/FSB_FC1)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 545 /CPUBuf/A~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61ABC8F1) + (at 233.8 110 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61ABC7FA) + (at 231.35 123.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/62A56F1A) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U23 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 500 /CPUBuf/CPU_~AS~)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 553 /CPUBuf/FSB_~CIOUT~)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 501 /CPUBuf/CPU_~CBREQ~)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 554 /CPUBuf/FSB_SIZ0)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 499 /CPUBuf/CPU_~DS~)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 555 /CPUBuf/FSB_SIZ1)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 496 /CPUBuf/CPU_~ECS~)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 375 "Net-(U23-Pad9)")) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 556 /CPUBuf/FSB_~AS~)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 497 /CPUBuf/CPU_SIZ1)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 557 /CPUBuf/FSB_~CBREQ~)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 498 /CPUBuf/CPU_SIZ0)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 558 /CPUBuf/FSB_~DS~)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 508 /CPUBuf/CPU_~CIOUT~)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 559 /CPUBuf/FSB_~ECS~)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61871312) + (at 196.9215 130.302 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 618712BE) + (at 224.2185 123.452 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61871294) + (at 218.8925 97.282 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61871240) + (at 208.0815 97.282) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61871081) + (at 205.8115 97.282 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 617C1B28) + (at 197.731 97.282) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867D0F) + (at 209.804 161.036) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867CE5) + (at 212.5345 161.036) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867CBB) + (at 204.9065 161.036) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867C91) + (at 192.2145 156.0115 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867C67) + (at 210.6215 130.302) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867D8D) + (at 203.9065 130.302 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867D63) + (at 192.2145 149.344 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867D39) + (at 192.2145 135.644 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867C3D) + (at 222.9485 155.5115 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867F85) + (at 222.9485 148.709 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 616BDDCB) (tstamp 61867FAF) + (at 223.012 135.644 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:ESP32-WROOM-32 (layer F.Cu) (tedit 601CCBE5) (tstamp 61ABAACE) + (at 258.953 28.575) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value ESP32-WROOM-32 (at 0 1.5) (layer F.Fab) hide + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_line (start -11.55 20.55) (end -11.55 -10.05) (layer F.CrtYd) (width 0.12)) + (fp_line (start 11.55 20.55) (end -11.55 20.55) (layer F.CrtYd) (width 0.12)) + (fp_line (start 11.55 -10.05) (end 11.55 20.55) (layer F.CrtYd) (width 0.12)) + (fp_line (start -11.55 -10.05) (end 11.55 -10.05) (layer F.CrtYd) (width 0.12)) + (fp_line (start 9.1 18.11) (end 6.4 18.11) (layer F.SilkS) (width 0.2032)) + (fp_line (start 9 -7.49) (end -9 -7.49) (layer F.Fab) (width 0.05)) + (fp_line (start 9 18.01) (end 9 -7.49) (layer F.Fab) (width 0.05)) + (fp_line (start -9 18.01) (end 9 18.01) (layer F.Fab) (width 0.05)) + (fp_line (start -9 -7.49) (end -9 18.01) (layer F.Fab) (width 0.05)) + (fp_line (start -9.1 -1.14) (end 9.1 -1.14) (layer F.SilkS) (width 0.2032)) + (fp_line (start -9.1 18.11) (end -9.1 17.19) (layer F.SilkS) (width 0.2032)) + (fp_line (start -9.1 -0.65) (end -9.1 -7.49) (layer F.SilkS) (width 0.2032)) + (fp_line (start 9.1 -0.65) (end 9.1 -7.49) (layer F.SilkS) (width 0.2032)) + (fp_line (start -9 -1.14) (end 9 -1.14) (layer F.Fab) (width 0.05)) + (fp_line (start 9.1 18.11) (end 9.1 17.19) (layer F.SilkS) (width 0.2032)) + (fp_line (start -6.4 18.11) (end -9.1 18.11) (layer F.SilkS) (width 0.2032)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 39 smd rect (at -1 7.53) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (zone_connect 2)) + (pad 39 smd rect (at 1.159 7.53) (size 0.5 3) (layers F.Cu F.Paste F.Mask) + (zone_connect 2)) + (pad 39 smd rect (at -1 9.562) (size 3 0.5) (layers F.Cu F.Paste F.Mask) + (zone_connect 2)) + (pad 39 smd rect (at -3.032 7.53) (size 0.5 3) (layers F.Cu F.Paste F.Mask) + (zone_connect 2)) + (pad 39 smd rect (at -1 5.498) (size 3 0.5) (layers F.Cu F.Paste F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at -1 6.403) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at -1 8.657) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at 0.127 8.657) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at 0.127 7.53) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at 0.127 6.403) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at -2.127 6.403) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at -2.127 7.53) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 thru_hole circle (at -2.127 8.657) (size 0.8 0.8) (drill 0.3) (layers *.Cu F.Mask) + (zone_connect 2)) + (pad 39 smd rect (at -1 7.53) (size 5 5) (layers F.Cu F.Mask) + (zone_connect 2)) + (pad 1 smd oval (at -8.75 0) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd oval (at -8.75 1.27) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd oval (at -8.75 2.54) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd oval (at -8.75 3.81) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd oval (at -8.75 5.08) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd oval (at -8.75 6.35) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd oval (at -8.75 7.62) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at -8.75 8.89) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd oval (at -8.75 10.16) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd oval (at -8.75 11.43) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd oval (at -8.75 12.7) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd oval (at -8.75 13.97) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at -8.75 15.24) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 14 smd oval (at -8.75 16.51) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd oval (at 8.75 16.51) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd oval (at 8.75 15.24) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd oval (at 8.75 13.97) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd oval (at 8.75 12.7) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at 8.75 11.43) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd oval (at 8.75 10.16) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd oval (at 8.75 8.89) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd oval (at 8.75 7.62) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd oval (at 8.75 6.35) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd oval (at 8.75 5.08) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 35 smd oval (at 8.75 3.81) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 36 smd oval (at 8.75 2.54) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 37 smd oval (at 8.75 1.27) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 38 smd oval (at 8.75 0) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd oval (at -0.635 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd oval (at -1.905 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd oval (at -3.175 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 16 smd oval (at -4.445 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 15 smd oval (at -5.715 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd oval (at 0.635 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd oval (at 1.905 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd oval (at 3.175 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 23 smd oval (at 4.445 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd oval (at 5.715 17.79 90) (size 2.5 0.9) (layers F.Cu F.Paste F.Mask)) + (model ${KISYS3DMOD}/RF_Module.3dshapes/ESP32-WROOM-32.wrl + (offset (xyz 0 -8.210000000000001 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188EF84) + (at 214.125 90.8) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/63262F0C) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U27 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 180) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 446 /Control/CPU_DDIR)) + (pad 2 smd roundrect (at -2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 471 /CPUBuf/CPU_D16)) + (pad 3 smd roundrect (at -1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 472 /CPUBuf/CPU_D17)) + (pad 4 smd roundrect (at -0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 473 /CPUBuf/CPU_D18)) + (pad 5 smd roundrect (at -0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 474 /CPUBuf/CPU_D19)) + (pad 6 smd roundrect (at 0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 475 /CPUBuf/CPU_D20)) + (pad 7 smd roundrect (at 0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 476 /CPUBuf/CPU_D21)) + (pad 8 smd roundrect (at 1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 478 /CPUBuf/CPU_D23)) + (pad 9 smd roundrect (at 2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 477 /CPUBuf/CPU_D22)) + (pad 10 smd roundrect (at 2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 285 /RAM/D22)) + (pad 12 smd roundrect (at 2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 286 /RAM/D23)) + (pad 13 smd roundrect (at 1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 284 /RAM/D21)) + (pad 14 smd roundrect (at 0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 283 /RAM/D20)) + (pad 15 smd roundrect (at 0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 282 /RAM/D19)) + (pad 16 smd roundrect (at -0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 281 /RAM/D18)) + (pad 17 smd roundrect (at -0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 280 /RAM/D17)) + (pad 18 smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 279 /RAM/D16)) + (pad 19 smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 445 /Control/CPU_D~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61827853) + (at 218.75 88.35 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188F23C) + (at 205.275 90.8) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/622AE852) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U26 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 180) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 446 /Control/CPU_DDIR)) + (pad 2 smd roundrect (at -2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 464 /CPUBuf/CPU_D9)) + (pad 3 smd roundrect (at -1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 463 /CPUBuf/CPU_D8)) + (pad 4 smd roundrect (at -0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 465 /CPUBuf/CPU_D10)) + (pad 5 smd roundrect (at -0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 466 /CPUBuf/CPU_D11)) + (pad 6 smd roundrect (at 0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 467 /CPUBuf/CPU_D12)) + (pad 7 smd roundrect (at 0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 468 /CPUBuf/CPU_D13)) + (pad 8 smd roundrect (at 1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 469 /CPUBuf/CPU_D14)) + (pad 9 smd roundrect (at 2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 470 /CPUBuf/CPU_D15)) + (pad 10 smd roundrect (at 2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 240 /RAM/D15)) + (pad 12 smd roundrect (at 2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 241 /RAM/D14)) + (pad 13 smd roundrect (at 1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 242 /RAM/D13)) + (pad 14 smd roundrect (at 0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 243 /RAM/D12)) + (pad 15 smd roundrect (at 0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 244 /RAM/D11)) + (pad 16 smd roundrect (at -0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 245 /RAM/D10)) + (pad 17 smd roundrect (at -0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 247 /RAM/D8)) + (pad 18 smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 246 /RAM/D9)) + (pad 19 smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 445 /Control/CPU_D~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 618279A3) + (at 201.05 88.35 270) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 270) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188F2EC) + (at 196.425 90.8) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /629B918A/6226E539) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U25 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 180) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 445 /Control/CPU_D~OE~)) + (pad 18 smd roundrect (at -1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 274 /RAM/D4)) + (pad 17 smd roundrect (at -0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 273 /RAM/D5)) + (pad 16 smd roundrect (at -0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 275 /RAM/D3)) + (pad 15 smd roundrect (at 0.325 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 272 /RAM/D6)) + (pad 14 smd roundrect (at 0.975 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 276 /RAM/D2)) + (pad 13 smd roundrect (at 1.625 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 271 /RAM/D7)) + (pad 12 smd roundrect (at 2.275 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 277 /RAM/D1)) + (pad 11 smd roundrect (at 2.925 -2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 278 /RAM/D0)) + (pad 10 smd roundrect (at 2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 487 /CPUBuf/CPU_D0)) + (pad 8 smd roundrect (at 1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 488 /CPUBuf/CPU_D1)) + (pad 7 smd roundrect (at 0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 494 /CPUBuf/CPU_D7)) + (pad 6 smd roundrect (at 0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 489 /CPUBuf/CPU_D2)) + (pad 5 smd roundrect (at -0.325 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 493 /CPUBuf/CPU_D6)) + (pad 4 smd roundrect (at -0.975 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 490 /CPUBuf/CPU_D3)) + (pad 3 smd roundrect (at -1.625 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 492 /CPUBuf/CPU_D5)) + (pad 2 smd roundrect (at -2.275 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 491 /CPUBuf/CPU_D4)) + (pad 1 smd roundrect (at -2.925 2.95 90) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 446 /Control/CPU_DDIR)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61A01B2E) + (at 193.2 85.6 90) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4 90) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 90) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61815AF6) + (at 255.2 119.825 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/60941F85) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U12 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHCT573PW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 340 /PDS/A7)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 341 /PDS/A6)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 342 /PDS/A5)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 343 /PDS/A4)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 344 /PDSBuf/IOB_~RMC~)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 345 /PDSBuf/IOB_FC2)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 346 /PDSBuf/IOB_FC1)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 347 /PDSBuf/IOB_FC0)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 315 /PDSBuf/ADoutLE)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 538 /CPUBuf/FSB_FC0)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 539 /CPUBuf/FSB_FC1)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 540 /CPUBuf/FSB_FC2)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 541 /CPUBuf/FSB_A4)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 542 /CPUBuf/FSB_A5)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 543 /CPUBuf/FSB_A6)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 544 /CPUBuf/FSB_A7)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 314 /PDSBuf/A~OE~)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61815AE8) + (at 257.65 115.6 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61815A3F) + (at 255.2 110.975 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/62A8E938) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U13 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74LVC244APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 348 /Control/IOB_~DSACK~0)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 349 /PDSBuf/IOB_~DSACK~1)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 350 /Control/IOB_~HALT~)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 351 /PDS/C16M)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 352 /Control/IOB_~BERR~)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 353 /PDSBuf/FSB_~RESET~)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 354 "Net-(U13-Pad9)")) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 355 /PDSBuf/IOB_~DSACK~0)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 356 "Net-(U13-Pad7)")) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 357 /PDSBuf/IOB_~HALT~)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 358 /Control/IOB_C16M)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 359 /PDSBuf/IOB_~BERR~)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 360 /Control/IOB_~DSACK~1)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 38 /PDSBuf/IOB_~RESET~)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61815A31) + (at 257.65 106.75 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6188298A) + (at 255.2 102.125 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/63262F04) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U14 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 379 /PDSBuf/DDIR)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 380 /PDSBuf/IOC_D0)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 381 /PDSBuf/IOC_D1)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 382 /PDSBuf/IOC_D2)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 383 /PDSBuf/IOC_D3)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 384 /PDSBuf/IOC_D4)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 385 /PDSBuf/IOC_D5)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 386 /PDSBuf/IOC_D6)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 387 /PDSBuf/IOC_D7)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 388 /PDS/D7)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 389 /PDS/D6)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 390 /PDS/D5)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 391 /PDS/D4)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 392 /PDS/D3)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 393 /PDS/D2)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 394 /PDS/D1)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 395 /PDS/D0)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 396 /PDSBuf/D~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61815A00) + (at 257.65 97.9 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 6181596C) + (at 257.65 89.05 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61882870) + (at 255.2 93.275 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/63262F09) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U15 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 379 /PDSBuf/DDIR)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 397 /PDSBuf/IOC_D8)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 398 /PDSBuf/IOC_D9)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 399 /PDSBuf/IOC_D10)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 400 /PDSBuf/IOC_D11)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 401 /PDSBuf/IOC_D12)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 402 /PDSBuf/IOC_D13)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 403 /PDSBuf/IOC_D14)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 404 /PDSBuf/IOC_D15)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 405 /PDS/D15)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 406 /PDS/D14)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 407 /PDS/D13)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 408 /PDS/D12)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 409 /PDS/D11)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 410 /PDS/D10)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 411 /PDS/D9)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 412 /PDS/D8)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 396 /PDSBuf/D~OE~)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 618828FD) + (at 255.2 84.425 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/622CABB5) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U16 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHC245APW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 396 /PDSBuf/D~OE~)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 413 /PDS/D16)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 414 /PDS/D17)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 415 /PDS/D18)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 416 /PDS/D19)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 417 /PDS/D20)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 418 /PDS/D21)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 419 /PDS/D22)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 420 /PDS/D23)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 421 /PDSBuf/IOC_D23)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 422 /PDSBuf/IOC_D22)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 423 /PDSBuf/IOC_D21)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 424 /PDSBuf/IOC_D20)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 425 /PDSBuf/IOC_D19)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 426 /PDSBuf/IOC_D18)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 427 /PDSBuf/IOC_D17)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 428 /PDSBuf/IOC_D16)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 379 /PDSBuf/DDIR)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61815918) + (at 257.65 80.2 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61815884) + (at 257.65 133.3 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61822CBA) + (at 255.2 128.675 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/6094447D) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U11 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHCT573PW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 339 /PDS/A15)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 338 /PDS/A14)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 337 /PDS/A13)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 336 /PDS/A12)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 335 /PDS/A11)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 334 /PDS/A10)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 333 /PDS/A9)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 332 /PDS/A8)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 315 /PDSBuf/ADoutLE)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 530 /CPUBuf/FSB_A8)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 531 /CPUBuf/FSB_A9)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 532 /CPUBuf/FSB_A10)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 533 /CPUBuf/FSB_A11)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 534 /CPUBuf/FSB_A12)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 535 /CPUBuf/FSB_A13)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 536 /CPUBuf/FSB_A14)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 537 /CPUBuf/FSB_A15)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 314 /PDSBuf/A~OE~)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6181583E) + (at 255.2 137.525 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/61398C8D) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U10 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHCT573PW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 314 /PDSBuf/A~OE~)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 522 /CPUBuf/FSB_A23)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 523 /CPUBuf/FSB_A22)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 524 /CPUBuf/FSB_A21)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 525 /CPUBuf/FSB_A20)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 526 /CPUBuf/FSB_A19)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 527 /CPUBuf/FSB_A18)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 528 /CPUBuf/FSB_A17)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 529 /CPUBuf/FSB_A16)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 315 /PDSBuf/ADoutLE)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 324 /PDS/A16)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 325 /PDS/A17)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 326 /PDS/A18)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 327 /PDS/A19)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 328 /PDS/A20)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 329 /PDS/A21)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 330 /PDS/A22)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 331 /PDS/A23)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61815830) + (at 257.65 124.45 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 618157F9) + (at 257.65 151 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0402 (layer F.Cu) (tedit 5EE29C3C) (tstamp 61814E9B) + (at 257.65 142.15 180) + (tags capacitor) + (solder_mask_margin 0.05) + (solder_paste_margin -0.05) + (attr smd) + (fp_text reference REF** (at 0 0) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_text value C_0402 (at 0 0.4) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.05)) + (fp_line (start -1 0.5) (end -1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1 -0.5) (end 1 -0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 -0.5) (end 1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1 0.5) (end -1 0.5) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (pad 1 smd roundrect (at -0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at 0.5 0 180) (size 0.6 0.65) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 6181573F) + (at 255.2 146.375 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/61DF380D) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U9 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHCT573PW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 323 "Net-(U9-Pad19)")) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 322 /PDSBuf/IOB_R~W~)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 321 /PDS/A31)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 320 /PDS/A30)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 319 /PDS/A27)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 318 /PDS/A26)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 317 /PDS/A25)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 316 /PDS/A24)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 315 /PDSBuf/ADoutLE)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 515 /CPUBuf/FSB_A24)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 516 /CPUBuf/FSB_A25)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 517 /CPUBuf/FSB_A26)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 518 /CPUBuf/FSB_A27)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 519 /CPUBuf/FSB_A30)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 520 /CPUBuf/FSB_A31)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 521 /CPUBuf/FSB_R~W~)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 314 /PDSBuf/A~OE~)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5F27C9F6) (tstamp 61724302) + (at 255.2 155.225 270) + (descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.65") + (path /60941922/61ED1513) + (solder_mask_margin 0.024) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U8 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (fp_text value 74AHCT573PW (at 0 1.016 270) (layer F.Fab) + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_line (start -3.45 3.75) (end -3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.45 2.225) (end 3.45 -2.225) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.55 3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end -3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 -3.95) (end 3.55 -3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.55 3.95) (end 3.55 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.25 2.2) (end -3.25 1.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 2.2) (end -2.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start 3.25 -2.2) (end 3.25 2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 -2.2) (end 3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_line (start -3.25 1.2) (end -3.25 -2.2) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 90) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 1 smd roundrect (at -2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 314 /PDSBuf/A~OE~)) + (pad 2 smd roundrect (at -2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 313 /PDSBuf/IOC_SIZ1)) + (pad 3 smd roundrect (at -1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 312 /PDSBuf/IOC_SIZ0)) + (pad 4 smd roundrect (at -0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 311 /PDSBuf/IOC_A3)) + (pad 5 smd roundrect (at -0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 310 /PDSBuf/IOC_A2)) + (pad 6 smd roundrect (at 0.325 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 309 /PDSBuf/IOC_A1)) + (pad 7 smd roundrect (at 0.975 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 308 /PDSBuf/IOC_A0)) + (pad 8 smd roundrect (at 1.625 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 307 /Control/IOC_~AS~)) + (pad 9 smd roundrect (at 2.275 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 306 /Control/IOC_~DS~)) + (pad 10 smd roundrect (at 2.925 2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 11 smd roundrect (at 2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 12 smd roundrect (at 2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 305 /PDSBuf/IOB_~DS~)) + (pad 13 smd roundrect (at 1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 304 /PDSBuf/IOB_~AS~)) + (pad 14 smd roundrect (at 0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 303 /PDS/A0)) + (pad 15 smd roundrect (at 0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 302 /PDS/A1)) + (pad 16 smd roundrect (at -0.325 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 301 /PDS/A2)) + (pad 17 smd roundrect (at -0.975 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 300 /PDS/A3)) + (pad 18 smd roundrect (at -1.625 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 299 /PDSBuf/IOB_SIZ0)) + (pad 19 smd roundrect (at -2.275 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 298 /PDSBuf/IOB_SIZ1)) + (pad 20 smd roundrect (at -2.925 -2.95) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 61B9AEB5) + (at 118.396001 184.020501) + (tags capacitor) + (path /5F6DA71D/616DE7E8) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C4 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 10u (at 0 0.35) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 61B9AE85) + (at 118.396001 187.070501) + (tags capacitor) + (path /5F6DA71D/616DE7D1) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C5 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 10u (at 0 0.35) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module 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(width 0.15)) + (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15)) + (fp_text user %R (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 452 -5V)) + (pad 2 smd roundrect (at 0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 616FF043) + (at 118.396001 190.120501) + (tags capacitor) + (path /5F6DA71D/616DE7F4) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C7 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text 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F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 452 -5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 61B9AE25) + (at 122.846001 187.070501) + (tags capacitor) + (path /5F6DA71D/616DE7DB) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C8 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 10u (at 0 0.35) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 453 +12V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module 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F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 454 -12V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 61B9ADC5) + (at 127.296001 187.070501) + (tags capacitor) + (path /5F6DA71D/616F27A7) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C11 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 10u (at 0 0.35) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 1) 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F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (pad 2 smd roundrect (at 0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 61B9AD35) + (at 161.256001 183.010501) + (tags capacitor) + (path /5F72F108/613F0B6D) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C14 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 10u (at 0 0.35) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 180) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.85 0) (size 1.05 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 +5V)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0805 (layer F.Cu) (tedit 5F02840E) (tstamp 61B9AD05) + (at 161.256001 186.060501) + (tags capacitor) + (path /5F72F108/613F0B66) + (solder_mask_margin 0.05) + (solder_paste_margin -0.025) + (attr smd) + (fp_text reference C15 (at 0 0 180) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 10u (at 0 0.35) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_line (start 1.7 1) (end -1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.7 -1) (end 1.7 1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 -1) (end 1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.7 1) (end -1.7 -1) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.4064 0.8) (end 0.4064 0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start -0.4064 -0.8) (end 0.4064 -0.8) (layer F.SilkS) (width 0.1524)) + (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.15)) + (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.15)) + 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(layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9B4BE) + (at 125.796001 172.870501) + (tags capacitor) + (path /60941922/63262EF8) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C17 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 0.7) (end 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(thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9B45E) + (at 118.096001 176.520501) + (tags capacitor) + (path /60941922/63262F01) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C26 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + 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(roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9B30E) + (at 149.456001 188.620501) + (tags capacitor) + (path /629B918A/61D73210) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C39 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9B2DE) + (at 141.756001 186.170501) + (tags capacitor) + (path /629B918A/61628094) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C40 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9B2AE) + (at 145.606001 183.720501) + (tags capacitor) + (path /629B918A/61D7321A) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C41 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9B27E) + (at 141.756001 188.620501) + (tags capacitor) + (path /629B918A/6162809E) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C42 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9AFDE) + (at 145.606001 186.170501) + (tags capacitor) + (path /629B918A/63262F02) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C43 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9AFAE) + (at 149.456001 183.720501) + (tags capacitor) + (path /629B918A/616280BB) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C44 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9AEE5) + (at 145.606001 188.620501) + (tags capacitor) + (path /629B918A/61D73231) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C45 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:C_0603 (layer F.Cu) (tedit 5EE29C36) (tstamp 61B9AF15) + (at 149.456001 186.170501) + (tags capacitor) + (path /629B918A/616280B5) + (solder_mask_margin 0.05) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference C46 (at 0 0) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 2u2 (at 0 0.25) (layer F.Fab) + (effects (font (size 0.127 0.127) (thickness 0.03175))) + ) + (fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1)) + (fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 0.7) (end -1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.4 -0.7) (end 1.4 -0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 -0.7) (end 1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.4 0.7) (end -1.4 0.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.SilkS) hide + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (pad 2 smd roundrect (at 0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at -0.75 0) (size 0.85 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module stdpads:Fiducial (layer F.Cu) (tedit 5F1BCA76) (tstamp 61B9AF58) + (at 151.431001 170.745501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC47A28) + (attr smd) + (fp_text reference FID1 (at 0 0.05) (layer F.Fab) + (effects (font (size 0.381 0.381) (thickness 0.09525))) + ) + (fp_text value Fiducial (at 0 1.651) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad ~ smd circle (at 0 0) (size 1 1) (layers F.Cu F.Mask) + (solder_mask_margin 0.5) (clearance 0.575)) + ) + + (module stdpads:Fiducial (layer F.Cu) (tedit 5F1BCA76) (tstamp 61B9AF49) + (at 148.331001 173.845501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC4DBD8) + (attr smd) + (fp_text reference FID2 (at 0 0.05) (layer F.Fab) + (effects (font (size 0.381 0.381) (thickness 0.09525))) + ) + (fp_text value Fiducial (at 0 1.651) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad ~ smd circle (at 0 0) (size 1 1) (layers F.Cu F.Mask) + (solder_mask_margin 0.5) (clearance 0.575)) + ) + + (module stdpads:Fiducial (layer F.Cu) (tedit 5F1BCA76) (tstamp 61B9AF3A) + (at 148.331001 170.745501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC4921D) + (attr smd) + (fp_text reference FID3 (at 0 0.05) (layer F.Fab) + (effects (font (size 0.381 0.381) (thickness 0.09525))) + ) + (fp_text value Fiducial (at 0 1.651) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad ~ smd circle (at 0 0) (size 1 1) (layers F.Cu F.Mask) + (solder_mask_margin 0.5) (clearance 0.575)) + ) + + (module stdpads:Fiducial (layer F.Cu) (tedit 5F1BCA76) (tstamp 61B9AF67) + (at 145.231001 173.845501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC4DBDF) + (attr smd) + (fp_text reference FID4 (at 0 0.05) (layer F.Fab) + (effects (font (size 0.381 0.381) (thickness 0.09525))) + ) + (fp_text value Fiducial (at 0 1.651) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad ~ smd circle (at 0 0) (size 1 1) (layers F.Cu F.Mask) + (solder_mask_margin 0.5) (clearance 0.575)) + ) + + (module stdpads:PasteHole_1.1mm_PTH (layer F.Cu) (tedit 5E892B4B) (tstamp 61B9AF76) + (at 145.231001 170.745501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC53461) + (zone_connect 2) + (attr virtual) + (fp_text reference H1 (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_text value " " (at 0 2) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1.1) (layers *.Cu *.Mask) + (net 2 GND) (zone_connect 2)) + ) + + (module stdpads:PasteHole_1.1mm_PTH (layer F.Cu) (tedit 5E892B4B) (tstamp 61B9AF94) + (at 142.131001 173.845501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC795A2) + (zone_connect 2) + (attr virtual) + (fp_text reference H2 (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_text value " " (at 0 2) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1.1) (layers *.Cu *.Mask) + (net 2 GND) (zone_connect 2)) + ) + + (module stdpads:PasteHole_1.1mm_PTH (layer F.Cu) (tedit 5E892B4B) (tstamp 61B9AF85) + (at 142.131001 170.745501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC7E0B9) + (zone_connect 2) + (attr virtual) + (fp_text reference H3 (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_text value " " (at 0 2) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1.1) (layers *.Cu *.Mask) + (net 2 GND) (zone_connect 2)) + ) + + (module stdpads:PasteHole_1.1mm_PTH (layer F.Cu) (tedit 5E892B4B) (tstamp 61B9ACEB) + (at 139.031001 173.845501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5CC7E0C0) + (zone_connect 2) + (attr virtual) + (fp_text reference H4 (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_text value " " (at 0 2) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1.1) (layers *.Cu *.Mask) + (net 2 GND) (zone_connect 2)) + ) + + (module stdpads:PasteHole_1.1mm_PTH (layer F.Cu) (tedit 5E892B4B) (tstamp 61B9ACDC) + (at 139.031001 170.745501) + (descr "Circular Fiducial, 1mm bare copper top; 2mm keepout (Level A)") + (tags marker) + (path /5ED15A93) + (zone_connect 2) + (attr virtual) + (fp_text reference H5 (at 0 0) (layer F.Fab) + (effects (font (size 0.4 0.4) (thickness 0.1))) + ) + (fp_text value " " (at 0 2) (layer F.Fab) hide + (effects (font (size 0.508 0.508) (thickness 0.127))) + ) + (fp_circle (center 0 0) (end 1 0) (layer F.Fab) (width 0.1)) + (pad 1 thru_hole circle (at 0 0) (size 2 2) (drill 1.1) (layers *.Cu *.Mask) + (net 2 GND) (zone_connect 2)) + ) + + (module stdpads:SOT-353 (layer F.Cu) (tedit 5F739FE4) (tstamp 61B9ACAF) + (at 118.296001 171.020501) + (tags "SOT-353 SC-70-5") + (path /60941922/6178B34B) + (solder_mask_margin 0.04) + (solder_paste_margin -0.04) + (attr smd) + (fp_text reference U29 (at 0 0 270) (layer F.Fab) + (effects (font (size 0.254 0.254) (thickness 0.0635))) + ) + (fp_text value 74LVC1G125GW (at -0.35 0 270) (layer F.Fab) + (effects (font (size 0.1905 0.1905) (thickness 0.047625))) + ) + (fp_line (start -1.6 -1.3) (end 1.6 -1.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.6 1.3) (end -1.6 -1.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 1.3) (end -1.6 1.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.6 -1.3) (end 1.6 1.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.73 1.16) (end 1.3 1.16) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.68 -1.16) (end -0.73 -1.16) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.67 1.1) (end 0.18 1.1) (layer F.Fab) (width 0.1)) + (fp_line (start 0.68 0.6) (end 0.68 -1.1) (layer F.Fab) (width 0.1)) + (fp_line (start -0.67 1.1) (end -0.67 -1.1) (layer F.Fab) (width 0.1)) + (fp_line (start -0.67 -1.1) (end 0.68 -1.1) (layer F.Fab) (width 0.1)) + (fp_line (start 0.18 1.1) (end 0.68 0.6) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 1.9) (layer F.SilkS) + (effects (font (size 0.8128 0.8128) (thickness 0.2032))) + ) + (pad 3 smd roundrect (at 0.85 -0.65 180) (size 1 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 1 smd roundrect (at 0.85 0.65 180) (size 1 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 461 /Control/RESET~OE~)) + (pad 2 smd roundrect (at 0.85 0 180) (size 1 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 2 GND)) + (pad 4 smd roundrect (at -0.85 -0.65 180) (size 1 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 462 "Net-(R1-Pad1)")) + (pad 5 smd roundrect (at -0.85 0.65 180) (size 1 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 3 +3V3)) + (model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-353_SC-70-5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (gr_arc (start 191.389 29.464) (end 191.389 27.432) (angle -90) (layer Edge.Cuts) (width 0.15) (tstamp 6185F845)) + (gr_arc (start 270.002 29.464) (end 272.034 29.464) (angle -90) (layer Edge.Cuts) (width 0.15) (tstamp 6185F8D4)) + (gr_arc (start 270.002 161.925) (end 270.002 163.957) (angle -90) (layer Edge.Cuts) (width 0.15) (tstamp 6185F8CD)) + (gr_arc (start 191.389 161.925) (end 189.357 161.925) (angle -90) (layer Edge.Cuts) (width 0.15) (tstamp 61867BD9)) + (gr_line (start 272.034 29.464) (end 272.034 161.925) (layer Edge.Cuts) (width 0.15) (tstamp 618069C5)) + (gr_line (start 191.389 27.432) (end 270.002 27.432) (layer Edge.Cuts) (width 0.15)) + (gr_line (start 189.357 161.925) (end 189.357 29.464) (layer Edge.Cuts) (width 0.15) (tstamp 61887A9B)) + (gr_line (start 270.002 163.957) (end 191.389 163.957) (layer Edge.Cuts) (width 0.15)) + + (segment (start 258.15 143.45) (end 258.15 142.85) (width 0.45) (layer F.Cu) (net 0) (tstamp 61814E93)) + (segment (start 258.15 142.15) (end 258.15 141.45) (width 0.5) (layer F.Cu) (net 0) (tstamp 61814E94)) + (segment (start 257.15 142.15) (end 257.15 142.85) (width 0.5) (layer F.Cu) (net 0) (tstamp 61814E95)) + (segment (start 257.15 142.15) (end 257.15 141.45) (width 0.5) (layer F.Cu) (net 0) (tstamp 61814E96)) + (via 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(thermal_bridge_width 0.3)) + (polygon + (pts + (xy 272.034 163.957) (xy 189.357 163.957) (xy 189.357 26.162) (xy 272.034 26.162) + ) + ) + ) + (zone (net 3) (net_name +3V3) (layer In2.Cu) (tstamp 618A8318) (hatch edge 0.508) + (connect_pads (clearance 0.1524)) + (min_thickness 0.1524) + (fill (arc_segments 32) (thermal_gap 0.1524) (thermal_bridge_width 0.3)) + (polygon + (pts + (xy 272.034 163.957) (xy 189.357 163.957) (xy 189.357 26.162) (xy 272.034 26.162) + ) + ) + ) + (zone (net 2) (net_name GND) (layer In1.Cu) (tstamp 618A8319) (hatch edge 0.508) + (connect_pads (clearance 0.1524)) + (min_thickness 0.1524) + (fill (arc_segments 32) (thermal_gap 0.1524) (thermal_bridge_width 0.3)) + (polygon + (pts + (xy 272.034 163.957) (xy 189.357 163.957) (xy 189.357 26.162) (xy 272.034 26.162) + ) + ) + ) +) diff --git a/SE-030.pro b/SE-030.pro new file mode 100644 index 0000000..415bc0a --- /dev/null +++ b/SE-030.pro @@ -0,0 +1,269 @@ +update=Friday, October 22, 2021 at 05:54:57 AM +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead=SE-030.net +CopperLayerCount=4 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.15 +MinViaDiameter=0.5 +MinViaDrill=0.2 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.15 +TrackWidth2=0.2 +TrackWidth3=0.25 +TrackWidth4=0.3 +TrackWidth5=0.35 +TrackWidth6=0.4 +TrackWidth7=0.45 +TrackWidth8=0.5 +TrackWidth9=0.55 +TrackWidth10=0.6 +TrackWidth11=0.8 +TrackWidth12=1 +TrackWidth13=1.27 +TrackWidth14=1.524 +ViaDiameter1=0.5 +ViaDrill1=0.2 +ViaDiameter2=0.6 +ViaDrill2=0.3 +ViaDiameter3=0.8 +ViaDrill3=0.4 +ViaDiameter4=1 +ViaDrill4=0.5 +ViaDiameter5=1.524 +ViaDrill5=0.762 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.15 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.1524 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.15 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0.07619999999999999 +SolderMaskMinWidth=0.09999999999999999 +SolderPasteClearance=-0.03809999999999999 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=1 +Enabled=1 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=1 +Enabled=1 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.15 +TrackWidth=0.15 +ViaDiameter=0.5 +ViaDrill=0.2 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 diff --git a/SE-030.sch b/SE-030.sch new file mode 100644 index 0000000..cf4d5da --- /dev/null +++ b/SE-030.sch @@ -0,0 +1,529 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr USLetter 11000 8500 +encoding utf-8 +Sheet 1 7 +Title "RAM2E II" +Date "2020-07-25" +Rev "1.0" +Comp "Garrett's Workshop" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Mechanical:MountingHole_Pad H5 +U 1 1 5ED15A93 +P 1950 7250 +F 0 "H5" H 2050 7301 50 0000 L CNN +F 1 " " H 2050 7210 50 0000 L CNN +F 2 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5650 700 50 +F24 "CPU_SIZ[1..0]" I R 5650 1600 50 +F25 "DSACK~OE~" I L 4400 2700 50 +F26 "CPU_~DSACK~1" T R 5650 2500 50 +F27 "CPU_~DSACK~0" T R 5650 2600 50 +F28 "FSB_~DSACK~1" I L 4400 2500 50 +F29 "FSB_~DSACK~0" I L 4400 2600 50 +F30 "CPU_~ECS~" I R 5650 2000 50 +F31 "FSB_~ECS~" O L 4400 2000 50 +$EndSheet +Wire Wire Line + 3900 1500 4400 1500 +$EndSCHEMATC diff --git a/fp-lib-table b/fp-lib-table new file mode 100644 index 0000000..4c34ead --- /dev/null +++ b/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr "")) +) diff --git a/sterminator/STERMINATOR.v b/sterminator/STERMINATOR.v new file mode 100644 index 0000000..e12bb68 --- /dev/null +++ b/sterminator/STERMINATOR.v @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 06:35:56 10/26/2021 +// Design Name: +// Module Name: STERMINATOR +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module STERMINATOR( + input [2:0] FC, + input [31:2] A, + input nWE, + input nAS, + input CLK, + input CLKdat, + input [1:0] CMD, + input STERM, + output nSTERM, + output nFPUCS); + + wire ROMCS = FC[2] && ~FC[0] && A[31:28]==4'b0100; + wire RAMCS = FC[2] && ~FC[0] && A[31:30]==2'b00; + wire RAMROMCS = RAMCS || ROMCS; + + reg NA; + reg [1:0] NB; + reg [12:0] NR; + reg [8:0] NC; + + wire [1:0] AB = A[25:24]; + wire [12:0] AR = A[23:11]; + wire [8:0] AC = A[10:2]; + + always @(posedge CLK) begin + if (CMD==1) begin + NA <= 1; + NB <= AB; + NR <= AR; + NC <= AC+1; + end else if (CMD==2) begin + NA <= 0; + end else if (CMD==3) begin + NA <= 0; + end + end + + wire NSEL = RAMROMCS && NA && AB==NB && AR==NR && AC==NC; + + assign nSTERM = ~(STERM || NSEL); + + wire FPUCS = FC[02:00]==3'h7 && A[19:16]==4'h2 && A[15:13]==3'h1; + assign nFPUCS = ~((FPUCS && ~CLKdat) || (FPUCS && ~nAS)); + + +endmodule diff --git a/sterminator/XC9572XL/STERMINATOR.bld b/sterminator/XC9572XL/STERMINATOR.bld new file mode 100644 index 0000000..fb08610 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.bld @@ -0,0 +1,36 @@ +Release 14.7 ngdbuild P.20131013 (nt) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle +ise -dd _ngo -i -p xc9572xl-VQ64-5 STERMINATOR.ngc STERMINATOR.ngd + +Reading NGO file +"C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.ngc" +... +Gathering constraint information from source properties... +Done. + +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 130104 kilobytes + +Writing NGD file "STERMINATOR.ngd" ... +Total REAL time to NGDBUILD completion: 1 sec +Total CPU time to NGDBUILD completion: 1 sec + +Writing NGDBUILD log file "STERMINATOR.bld"... diff --git a/sterminator/XC9572XL/STERMINATOR.cmd_log b/sterminator/XC9572XL/STERMINATOR.cmd_log new file mode 100644 index 0000000..d4552db --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.cmd_log @@ -0,0 +1,110 @@ +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-10 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-10-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +taengine -intstyle ise -f STERMINATOR -w --format html1 -l STERMINATOR_html/tim/timing_report.htm +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-10 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-10-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +taengine -intstyle ise -f STERMINATOR -w --format html1 -l STERMINATOR_html/tim/timing_report.htm +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-10 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-10-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +hprep6 -s IEEE1149 -n STERMINATOR -i STERMINATOR +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-10 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-10-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +hprep6 -s IEEE1149 -n STERMINATOR -i STERMINATOR +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn 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ise STERMINATOR STERMINATOR.nga +hprep6 -s IEEE1149 -n STERMINATOR -i STERMINATOR +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-10 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-10-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +hprep6 -s IEEE1149 -n STERMINATOR -i STERMINATOR +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-10 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-10-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +hprep6 -s IEEE1149 -n STERMINATOR -i STERMINATOR +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-5 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-5-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +taengine -intstyle ise -f STERMINATOR -w --format html1 -l STERMINATOR_html/tim/timing_report.htm +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +xst -intstyle ise -ifn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.xst" -ofn "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/STERMINATOR.syr" +ngdbuild -intstyle ise -dd _ngo -i -p xc9572xl-VQ64-5 STERMINATOR.ngc STERMINATOR.ngd +cpldfit -intstyle ise -p xc9572xl-5-VQ64 -ofmt vhdl -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper STERMINATOR.ngd +XSLTProcess STERMINATOR_build.xml +tsim -intstyle ise STERMINATOR STERMINATOR.nga +hprep6 -s IEEE1149 -n STERMINATOR -i STERMINATOR +taengine -intstyle ise -f STERMINATOR -w --format html1 -l STERMINATOR_html/tim/timing_report.htm diff --git a/sterminator/XC9572XL/STERMINATOR.gise b/sterminator/XC9572XL/STERMINATOR.gise new file mode 100644 index 0000000..386ed4e --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.gise @@ -0,0 +1,130 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR.gyd b/sterminator/XC9572XL/STERMINATOR.gyd new file mode 100644 index 0000000..0353ee3 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.gyd @@ -0,0 +1,61 @@ +Pin Freeze File: version P.20131013 + +9572XL64 XC9572XL-5-VQ64 +A<10> S:PIN57 +A<11> S:PIN2 +A<12> S:PIN64 +A<13> S:PIN44 +A<14> S:PIN51 +A<15> S:PIN4 +A<16> S:PIN34 +A<17> S:PIN58 +A<18> S:PIN49 +A<19> S:PIN42 +A<20> S:PIN36 +A<21> S:PIN50 +A<22> S:PIN35 +A<23> S:PIN48 +A<24> S:PIN52 +A<25> S:PIN10 +A<28> S:PIN46 +A<29> S:PIN61 +A<2> S:PIN40 +A<30> S:PIN62 +A<31> S:PIN1 +A<3> S:PIN43 +A<4> S:PIN20 +A<5> S:PIN63 +A<6> S:PIN47 +A<7> S:PIN7 +A<8> S:PIN9 +A<9> S:PIN11 +CLK S:PIN15 +CLKdat S:PIN5 +CMD<0> S:PIN39 +CMD<1> S:PIN16 +FC<0> S:PIN31 +FC<1> S:PIN45 +FC<2> S:PIN56 +STERM S:PIN59 +nAS S:PIN6 +nFPUCS S:PIN22 +nSTERM S:PIN60 + + +;The remaining section of the .gyd file is for documentation purposes only. +;It shows where your internal equations were placed in the last successful fit. + +PARTITION FB1_8 EXP6_ EXP7_ EXP8_ EXP9_ + EXP10_ $OpTx$BIN_STEP$409 EXP11_ EXP12_ + EXP13_ EXP14_ EXP15_ +PARTITION FB2_2 nSTERM_OBUF +PARTITION FB2_11 NR<9> NR<1> NR<12> NR<11> + NR<10> NR<0> NB<1> NB<0> + +PARTITION FB3_1 NR<8> nFPUCS_OBUF NR<7> NR<6> + NR<5> NR<4> NR<3> NR<2> + NC<0> NA NC<8> NC<7> + NC<6> NC<5> NC<4> NC<3> + NC<2> NC<1> + + diff --git a/sterminator/XC9572XL/STERMINATOR.jed b/sterminator/XC9572XL/STERMINATOR.jed new file mode 100644 index 0000000..cd59f61 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.jed @@ -0,0 +1,1685 @@ +Programmer Jedec Bit Map +Date Extracted: Tue Oct 26 21:01:57 2021 + +QF46656* +QP64* +QV0* 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+L0046608 000000 000000 000000 000000* +L0046632 000000 000000 000000 000000* +CE6C2* +5534 diff --git a/sterminator/XC9572XL/STERMINATOR.lso b/sterminator/XC9572XL/STERMINATOR.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.lso @@ -0,0 +1 @@ +work diff --git a/sterminator/XC9572XL/STERMINATOR.mfd b/sterminator/XC9572XL/STERMINATOR.mfd new file mode 100644 index 0000000..f725cad --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.mfd @@ -0,0 +1,670 @@ +MDF Database: version 1.0 +MDF_INFO | STERMINATOR | XC9572XL-5-VQ64 +MACROCELL | 1 | 17 | NB<0> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 2 | 0 | 10 | 0 | 13 +INPUTS | 3 | A<24> | CMD<0> | CMD<1> +INPUTP | 3 | 75 | 54 | 21 +EQ | 3 | + NB<0>.D = A<24>; + NB<0>.CLK = CLK; // GCK + NB<0>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 16 | NB<1> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 14 +INPUTS | 3 | A<25> | CMD<0> | CMD<1> +INPUTP | 3 | 13 | 54 | 21 +EQ | 3 | + NB<1>.D = A<25>; + NB<1>.CLK = CLK; // GCK + NB<1>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 8 | NC<0> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 9 +INPUTS | 3 | A<2> | CMD<0> | CMD<1> +INPUTP | 3 | 55 | 54 | 21 +EQ | 3 | + NC<0>.D = !A<2>; + NC<0>.CLK = CLK; // GCK + NC<0>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 17 | NC<1> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 15 +INPUTS | 4 | A<2> | A<3> | CMD<0> | CMD<1> +INPUTP | 4 | 55 | 62 | 54 | 21 +EQ | 4 | + NC<1>.D = A<2> + $ A<3>; + NC<1>.CLK = CLK; // GCK + NC<1>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 16 | NC<2> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 13 +INPUTS | 5 | A<4> | A<2> | A<3> | CMD<0> | CMD<1> +INPUTP | 5 | 27 | 55 | 62 | 54 | 21 +EQ | 4 | + NC<2>.D = A<4> + $ A<2> & A<3>; + NC<2>.CLK = CLK; // GCK + NC<2>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 15 | NC<3> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 11 +INPUTS | 6 | A<5> | A<2> | A<3> | A<4> | CMD<0> | CMD<1> +INPUTP | 6 | 90 | 55 | 62 | 27 | 54 | 21 +EQ | 4 | + NC<3>.D = A<5> + $ A<2> & A<3> & A<4>; + NC<3>.CLK = CLK; // GCK + NC<3>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 14 | NC<4> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 14 +INPUTS | 7 | A<6> | A<2> | A<3> | A<4> | A<5> | CMD<0> | CMD<1> +INPUTP | 7 | 67 | 55 | 62 | 27 | 90 | 54 | 21 +EQ | 4 | + NC<4>.D = A<6> + $ A<2> & A<3> & A<4> & A<5>; + NC<4>.CLK = CLK; // GCK + NC<4>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 13 | NC<5> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 8 +INPUTS | 8 | A<7> | A<2> | A<3> | A<4> | A<5> | A<6> | CMD<0> | CMD<1> +INPUTP | 8 | 10 | 55 | 62 | 27 | 90 | 67 | 54 | 21 +EQ | 4 | + NC<5>.D = A<7> + $ A<2> & A<3> & A<4> & A<5> & A<6>; + NC<5>.CLK = CLK; // GCK + NC<5>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 12 | NC<6> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 13 +INPUTS | 9 | A<8> | A<2> | A<3> | A<4> | A<5> | A<6> | A<7> | CMD<0> | CMD<1> +INPUTP | 9 | 12 | 55 | 62 | 27 | 90 | 67 | 10 | 54 | 21 +EQ | 4 | + NC<6>.D = A<8> + $ A<2> & A<3> & A<4> & A<5> & A<6> & A<7>; + NC<6>.CLK = CLK; // GCK + NC<6>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 11 | NC<7> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 11 +INPUTS | 10 | A<9> | A<2> | A<3> | A<4> | A<5> | A<6> | A<7> | A<8> | CMD<0> | CMD<1> +INPUTP | 10 | 15 | 55 | 62 | 27 | 90 | 67 | 10 | 12 | 54 | 21 +EQ | 5 | + NC<7>.D = A<9> + $ A<2> & A<3> & A<4> & A<5> & A<6> & A<7> & + A<8>; + NC<7>.CLK = CLK; // GCK + NC<7>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 10 | NC<8> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 2 | 0 | 7 | 0 | 16 +INPUTS | 11 | A<10> | A<2> | A<3> | A<4> | A<5> | A<6> | A<7> | A<8> | A<9> | CMD<0> | CMD<1> +INPUTP | 11 | 83 | 55 | 62 | 27 | 90 | 67 | 10 | 12 | 15 | 54 | 21 +EQ | 5 | + NC<8>.D = A<10> + $ A<2> & A<3> & A<4> & A<5> & A<6> & A<7> & + A<8> & A<9>; + NC<8>.CLK = CLK; // GCK + NC<8>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 15 | NR<0> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 8 +INPUTS | 3 | A<11> | CMD<0> | CMD<1> +INPUTP | 3 | 3 | 54 | 21 +EQ | 3 | + NR<0>.D = A<11>; + NR<0>.CLK = CLK; // GCK + NR<0>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 14 | NR<10> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 10 +INPUTS | 3 | A<21> | CMD<0> | CMD<1> +INPUTP | 3 | 72 | 54 | 21 +EQ | 3 | + NR<10>.D = A<21>; + NR<10>.CLK = CLK; // GCK + NR<10>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 13 | NR<11> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 17 +INPUTS | 3 | A<22> | CMD<0> | CMD<1> +INPUTP | 3 | 49 | 54 | 21 +EQ | 3 | + NR<11>.D = A<22>; + NR<11>.CLK = CLK; // GCK + NR<11>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 12 | NR<12> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 10 +INPUTS | 3 | A<23> | CMD<0> | CMD<1> +INPUTP | 3 | 68 | 54 | 21 +EQ | 3 | + NR<12>.D = A<23>; + NR<12>.CLK = CLK; // GCK + NR<12>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 11 | NR<1> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 17 +INPUTS | 3 | A<12> | CMD<0> | CMD<1> +INPUTP | 3 | 92 | 54 | 21 +EQ | 3 | + NR<1>.D = A<12>; + NR<1>.CLK = CLK; // GCK + NR<1>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 7 | NR<2> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 9 +INPUTS | 3 | A<13> | CMD<0> | CMD<1> +INPUTP | 3 | 63 | 54 | 21 +EQ | 3 | + NR<2>.D = A<13>; + NR<2>.CLK = CLK; // GCK + NR<2>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 6 | NR<3> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 16 +INPUTS | 3 | A<14> | CMD<0> | CMD<1> +INPUTP | 3 | 74 | 54 | 21 +EQ | 3 | + NR<3>.D = A<14>; + NR<3>.CLK = CLK; // GCK + NR<3>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 5 | NR<4> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 12 +INPUTS | 3 | A<15> | CMD<0> | CMD<1> +INPUTP | 3 | 5 | 54 | 21 +EQ | 3 | + NR<4>.D = A<15>; + NR<4>.CLK = CLK; // GCK + NR<4>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 4 | NR<5> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 2 | 0 | 9 | 0 | 14 +INPUTS | 3 | A<16> | CMD<0> | CMD<1> +INPUTP | 3 | 47 | 54 | 21 +EQ | 3 | + NR<5>.D = A<16>; + NR<5>.CLK = CLK; // GCK + NR<5>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 3 | NR<6> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 2 | 0 | 7 | 0 | 17 +INPUTS | 3 | A<17> | CMD<0> | CMD<1> +INPUTP | 3 | 84 | 54 | 21 +EQ | 3 | + NR<6>.D = A<17>; + NR<6>.CLK = CLK; // GCK + NR<6>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 2 | NR<7> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 2 | 0 | 8 | 0 | 15 +INPUTS | 3 | A<18> | CMD<0> | CMD<1> +INPUTP | 3 | 70 | 54 | 21 +EQ | 3 | + NR<7>.D = A<18>; + NR<7>.CLK = CLK; // GCK + NR<7>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 0 | NR<8> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 2 | 0 | 12 | 0 | 11 +INPUTS | 3 | A<19> | CMD<0> | CMD<1> +INPUTP | 3 | 59 | 54 | 21 +EQ | 3 | + NR<8>.D = A<19>; + NR<8>.CLK = CLK; // GCK + NR<8>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 1 | 10 | NR<9> +ATTRIBUTES | 8553280 | 0 +OUTPUTMC | 1 | 0 | 16 +INPUTS | 3 | A<20> | CMD<0> | CMD<1> +INPUTP | 3 | 50 | 54 | 21 +EQ | 3 | + NR<9>.D = A<20>; + NR<9>.CLK = CLK; // GCK + NR<9>.CE = CMD<0> & !CMD<1>; +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 9 | NA +ATTRIBUTES | 8553216 | 0 +OUTPUTMC | 2 | 2 | 9 | 1 | 1 +INPUTS | 3 | CMD<0> | CMD<1> | NA +INPUTMC | 1 | 2 | 9 +INPUTP | 2 | 54 | 21 +EQ | 3 | + NA.D = CMD<0> & !CMD<1> + # !CMD<1> & NA; + NA.CLK = CLK; // GCK +GLOBALS | 1 | 2 | CLK + +MACROCELL | 2 | 1 | nFPUCS_OBUF +ATTRIBUTES | 264962 | 0 +INPUTS | 12 | FC<1> | FC<0> | A<17> | A<13> | A<14> | A<15> | A<16> | A<18> | A<19> | FC<2> | nAS | CLKdat +INPUTP | 12 | 65 | 43 | 84 | 63 | 74 | 5 | 47 | 70 | 59 | 82 | 9 | 7 +EQ | 4 | + !nFPUCS = FC<1> & FC<0> & A<17> & A<13> & !A<14> & !A<15> & + !A<16> & !A<18> & !A<19> & FC<2> & !nAS + # FC<1> & FC<0> & A<17> & A<13> & !A<14> & !A<15> & + !A<16> & !A<18> & !A<19> & FC<2> & !CLKdat; + +MACROCELL | 1 | 1 | nSTERM_OBUF +ATTRIBUTES | 264962 | 0 +INPUTS | 4 | STERM | $OpTx$BIN_STEP$409 | FC<0> | NA +INPUTMC | 2 | 0 | 12 | 2 | 9 +INPUTP | 2 | 86 | 43 +EQ | 2 | + !nSTERM = STERM & !$OpTx$BIN_STEP$409 + # !FC<0> & NA & !$OpTx$BIN_STEP$409; + +MACROCELL | 0 | 12 | $OpTx$BIN_STEP$409 +ATTRIBUTES | 133888 | 0 +OUTPUTMC | 1 | 1 | 1 +INPUTS | 9 | A<31> | STERM | FC<2> | A<15> | NR<4> | A<19> | NR<8> | EXP10_.EXP | EXP11_.EXP +INPUTMC | 4 | 2 | 5 | 2 | 0 | 0 | 11 | 0 | 13 +INPUTP | 5 | 1 | 86 | 82 | 5 | 59 +IMPORTS | 2 | 0 | 11 | 0 | 13 +EQ | 62 | + $OpTx$BIN_STEP$409 = !FC<2> & !STERM + # A<31> & !STERM + # A<15> & !NR<4> & !STERM + # !A<15> & NR<4> & !STERM + # !A<19> & NR<8> & !STERM +;Imported pterms FB1_12 + # A<5> & !NC<3> & !STERM + # !A<5> & NC<3> & !STERM + # A<9> & !NC<7> & !STERM + # !A<9> & NC<7> & !STERM + # A<19> & !NR<8> & !STERM +;Imported pterms FB1_11 + # A<24> & !NB<0> & !STERM + # A<21> & !NR<10> & !STERM + # !A<21> & NR<10> & !STERM + # A<23> & !NR<12> & !STERM + # !A<23> & NR<12> & !STERM +;Imported pterms FB1_10 + # A<13> & !NR<2> & !STERM + # !A<13> & NR<2> & !STERM + # A<2> & !NC<0> & !STERM + # !A<2> & NC<0> & !STERM + # A<16> & !NR<5> & !STERM +;Imported pterms FB1_9 + # A<7> & !NC<5> & !STERM + # !A<7> & NC<5> & !STERM + # A<11> & !NR<0> & !STERM + # !A<11> & NR<0> & !STERM + # A<18> & !NR<7> & !STERM +;Imported pterms FB1_8 + # !A<17> & NR<6> & !STERM + # A<10> & !NC<8> & !STERM +;Imported pterms FB1_14 + # !A<24> & NB<0> & !STERM + # A<4> & !NC<2> & !STERM + # !A<4> & NC<2> & !STERM + # A<8> & !NC<6> & !STERM + # !A<8> & NC<6> & !STERM +;Imported pterms FB1_15 + # A<25> & !NB<1> & !STERM + # !A<25> & NB<1> & !STERM + # A<6> & !NC<4> & !STERM + # !A<6> & NC<4> & !STERM + # !A<16> & NR<5> & !STERM +;Imported pterms FB1_16 + # A<3> & !NC<1> & !STERM + # !A<3> & NC<1> & !STERM + # !A<18> & NR<7> & !STERM + # A<30> & A<29> & !STERM + # A<30> & A<28> & !STERM +;Imported pterms FB1_17 + # !A<10> & NC<8> & !STERM + # A<14> & !NR<3> & !STERM + # !A<14> & NR<3> & !STERM + # A<20> & !NR<9> & !STERM + # !A<20> & NR<9> & !STERM +;Imported pterms FB1_18 + # A<17> & !NR<6> & !STERM + # A<22> & !NR<11> & !STERM + # !A<22> & NR<11> & !STERM + # A<12> & !NR<1> & !STERM + # !A<12> & NR<1> & !STERM; + +MACROCELL | 0 | 7 | EXP6_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 8 +INPUTS | 5 | A<17> | NR<6> | STERM | A<10> | NC<8> +INPUTMC | 2 | 2 | 3 | 2 | 10 +INPUTP | 3 | 84 | 86 | 83 +EXPORTS | 1 | 0 | 8 +EQ | 2 | + EXP6_.EXP = !A<17> & NR<6> & !STERM + # A<10> & !NC<8> & !STERM + +MACROCELL | 0 | 8 | EXP7_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 9 +INPUTS | 8 | A<7> | NC<5> | STERM | A<11> | NR<0> | A<18> | NR<7> | EXP6_.EXP +INPUTMC | 4 | 2 | 13 | 1 | 15 | 2 | 2 | 0 | 7 +INPUTP | 4 | 10 | 86 | 3 | 70 +EXPORTS | 1 | 0 | 9 +IMPORTS | 1 | 0 | 7 +EQ | 8 | + EXP7_.EXP = A<7> & !NC<5> & !STERM + # !A<7> & NC<5> & !STERM + # A<11> & !NR<0> & !STERM + # !A<11> & NR<0> & !STERM + # A<18> & !NR<7> & !STERM +;Imported pterms FB1_8 + # !A<17> & NR<6> & !STERM + # A<10> & !NC<8> & !STERM + +MACROCELL | 0 | 9 | EXP8_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 10 +INPUTS | 8 | A<13> | NR<2> | STERM | A<2> | NC<0> | A<16> | NR<5> | EXP7_.EXP +INPUTMC | 4 | 2 | 7 | 2 | 8 | 2 | 4 | 0 | 8 +INPUTP | 4 | 63 | 86 | 55 | 47 +EXPORTS | 1 | 0 | 10 +IMPORTS | 1 | 0 | 8 +EQ | 14 | + EXP8_.EXP = A<13> & !NR<2> & !STERM + # !A<13> & NR<2> & !STERM + # A<2> & !NC<0> & !STERM + # !A<2> & NC<0> & !STERM + # A<16> & !NR<5> & !STERM +;Imported pterms FB1_9 + # A<7> & !NC<5> & !STERM + # !A<7> & NC<5> & !STERM + # A<11> & !NR<0> & !STERM + # !A<11> & NR<0> & !STERM + # A<18> & !NR<7> & !STERM +;Imported pterms FB1_8 + # !A<17> & NR<6> & !STERM + # A<10> & !NC<8> & !STERM + +MACROCELL | 0 | 10 | EXP9_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 11 +INPUTS | 8 | A<24> | NB<0> | STERM | A<21> | NR<10> | A<23> | NR<12> | EXP8_.EXP +INPUTMC | 4 | 1 | 17 | 1 | 14 | 1 | 12 | 0 | 9 +INPUTP | 4 | 75 | 86 | 72 | 68 +EXPORTS | 1 | 0 | 11 +IMPORTS | 1 | 0 | 9 +EQ | 20 | + EXP9_.EXP = A<24> & !NB<0> & !STERM + # A<21> & !NR<10> & !STERM + # !A<21> & NR<10> & !STERM + # A<23> & !NR<12> & !STERM + # !A<23> & NR<12> & !STERM +;Imported pterms FB1_10 + # A<13> & !NR<2> & !STERM + # !A<13> & NR<2> & !STERM + # A<2> & !NC<0> & !STERM + # !A<2> & NC<0> & !STERM + # A<16> & !NR<5> & !STERM +;Imported pterms FB1_9 + # A<7> & !NC<5> & !STERM + # !A<7> & NC<5> & !STERM + # A<11> & !NR<0> & !STERM + # !A<11> & NR<0> & !STERM + # A<18> & !NR<7> & !STERM +;Imported pterms FB1_8 + # !A<17> & NR<6> & !STERM + # A<10> & !NC<8> & !STERM + +MACROCELL | 0 | 11 | EXP10_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 12 +INPUTS | 8 | A<5> | NC<3> | STERM | A<9> | NC<7> | A<19> | NR<8> | EXP9_.EXP +INPUTMC | 4 | 2 | 15 | 2 | 11 | 2 | 0 | 0 | 10 +INPUTP | 4 | 90 | 86 | 15 | 59 +EXPORTS | 1 | 0 | 12 +IMPORTS | 1 | 0 | 10 +EQ | 26 | + EXP10_.EXP = A<5> & !NC<3> & !STERM + # !A<5> & NC<3> & !STERM + # A<9> & !NC<7> & !STERM + # !A<9> & NC<7> & !STERM + # A<19> & !NR<8> & !STERM +;Imported pterms FB1_11 + # A<24> & !NB<0> & !STERM + # A<21> & !NR<10> & !STERM + # !A<21> & NR<10> & !STERM + # A<23> & !NR<12> & !STERM + # !A<23> & NR<12> & !STERM +;Imported pterms FB1_10 + # A<13> & !NR<2> & !STERM + # !A<13> & NR<2> & !STERM + # A<2> & !NC<0> & !STERM + # !A<2> & NC<0> & !STERM + # A<16> & !NR<5> & !STERM +;Imported pterms FB1_9 + # A<7> & !NC<5> & !STERM + # !A<7> & NC<5> & !STERM + # A<11> & !NR<0> & !STERM + # !A<11> & NR<0> & !STERM + # A<18> & !NR<7> & !STERM +;Imported pterms FB1_8 + # !A<17> & NR<6> & !STERM + # A<10> & !NC<8> & !STERM + +MACROCELL | 0 | 13 | EXP11_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 12 +INPUTS | 8 | A<24> | NB<0> | STERM | A<4> | NC<2> | A<8> | NC<6> | EXP12_.EXP +INPUTMC | 4 | 1 | 17 | 2 | 16 | 2 | 12 | 0 | 14 +INPUTP | 4 | 75 | 86 | 27 | 12 +EXPORTS | 1 | 0 | 12 +IMPORTS | 1 | 0 | 14 +EQ | 29 | + EXP11_.EXP = !A<24> & NB<0> & !STERM + # A<4> & !NC<2> & !STERM + # !A<4> & NC<2> & !STERM + # A<8> & !NC<6> & !STERM + # !A<8> & NC<6> & !STERM +;Imported pterms FB1_15 + # A<25> & !NB<1> & !STERM + # !A<25> & NB<1> & !STERM + # A<6> & !NC<4> & !STERM + # !A<6> & NC<4> & !STERM + # !A<16> & NR<5> & !STERM +;Imported pterms FB1_16 + # A<3> & !NC<1> & !STERM + # !A<3> & NC<1> & !STERM + # !A<18> & NR<7> & !STERM + # A<30> & A<29> & !STERM + # A<30> & A<28> & !STERM +;Imported pterms FB1_17 + # !A<10> & NC<8> & !STERM + # A<14> & !NR<3> & !STERM + # !A<14> & NR<3> & !STERM + # A<20> & !NR<9> & !STERM + # !A<20> & NR<9> & !STERM +;Imported pterms FB1_18 + # A<17> & !NR<6> & !STERM + # A<22> & !NR<11> & !STERM + # !A<22> & NR<11> & !STERM + # A<12> & !NR<1> & !STERM + # !A<12> & NR<1> & !STERM + +MACROCELL | 0 | 14 | EXP12_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 13 +INPUTS | 8 | A<25> | NB<1> | STERM | A<6> | NC<4> | A<16> | NR<5> | EXP13_.EXP +INPUTMC | 4 | 1 | 16 | 2 | 14 | 2 | 4 | 0 | 15 +INPUTP | 4 | 13 | 86 | 67 | 47 +EXPORTS | 1 | 0 | 13 +IMPORTS | 1 | 0 | 15 +EQ | 23 | + EXP12_.EXP = A<25> & !NB<1> & !STERM + # !A<25> & NB<1> & !STERM + # A<6> & !NC<4> & !STERM + # !A<6> & NC<4> & !STERM + # !A<16> & NR<5> & !STERM +;Imported pterms FB1_16 + # A<3> & !NC<1> & !STERM + # !A<3> & NC<1> & !STERM + # !A<18> & NR<7> & !STERM + # A<30> & A<29> & !STERM + # A<30> & A<28> & !STERM +;Imported pterms FB1_17 + # !A<10> & NC<8> & !STERM + # A<14> & !NR<3> & !STERM + # !A<14> & NR<3> & !STERM + # A<20> & !NR<9> & !STERM + # !A<20> & NR<9> & !STERM +;Imported pterms FB1_18 + # A<17> & !NR<6> & !STERM + # A<22> & !NR<11> & !STERM + # !A<22> & NR<11> & !STERM + # A<12> & !NR<1> & !STERM + # !A<12> & NR<1> & !STERM + +MACROCELL | 0 | 15 | EXP13_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 14 +INPUTS | 9 | A<3> | NC<1> | STERM | A<18> | NR<7> | A<30> | A<29> | A<28> | EXP14_.EXP +INPUTMC | 3 | 2 | 17 | 2 | 2 | 0 | 16 +INPUTP | 6 | 62 | 86 | 70 | 89 | 88 | 66 +EXPORTS | 1 | 0 | 14 +IMPORTS | 1 | 0 | 16 +EQ | 17 | + EXP13_.EXP = A<3> & !NC<1> & !STERM + # !A<3> & NC<1> & !STERM + # !A<18> & NR<7> & !STERM + # A<30> & A<29> & !STERM + # A<30> & A<28> & !STERM +;Imported pterms FB1_17 + # !A<10> & NC<8> & !STERM + # A<14> & !NR<3> & !STERM + # !A<14> & NR<3> & !STERM + # A<20> & !NR<9> & !STERM + # !A<20> & NR<9> & !STERM +;Imported pterms FB1_18 + # A<17> & !NR<6> & !STERM + # A<22> & !NR<11> & !STERM + # !A<22> & NR<11> & !STERM + # A<12> & !NR<1> & !STERM + # !A<12> & NR<1> & !STERM + +MACROCELL | 0 | 16 | EXP14_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 15 +INPUTS | 8 | A<10> | NC<8> | STERM | A<14> | NR<3> | A<20> | NR<9> | EXP15_.EXP +INPUTMC | 4 | 2 | 10 | 2 | 6 | 1 | 10 | 0 | 17 +INPUTP | 4 | 83 | 86 | 74 | 50 +EXPORTS | 1 | 0 | 15 +IMPORTS | 1 | 0 | 17 +EQ | 11 | + EXP14_.EXP = !A<10> & NC<8> & !STERM + # A<14> & !NR<3> & !STERM + # !A<14> & NR<3> & !STERM + # A<20> & !NR<9> & !STERM + # !A<20> & NR<9> & !STERM +;Imported pterms FB1_18 + # A<17> & !NR<6> & !STERM + # A<22> & !NR<11> & !STERM + # !A<22> & NR<11> & !STERM + # A<12> & !NR<1> & !STERM + # !A<12> & NR<1> & !STERM + +MACROCELL | 0 | 17 | EXP15_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 0 | 16 +INPUTS | 7 | A<17> | NR<6> | STERM | A<22> | NR<11> | A<12> | NR<1> +INPUTMC | 3 | 2 | 3 | 1 | 13 | 1 | 11 +INPUTP | 4 | 84 | 86 | 49 | 92 +EXPORTS | 1 | 0 | 16 +EQ | 5 | + EXP15_.EXP = A<17> & !NR<6> & !STERM + # A<22> & !NR<11> & !STERM + # !A<22> & NR<11> & !STERM + # A<12> & !NR<1> & !STERM + # !A<12> & NR<1> & !STERM + +PIN | FC<1> | 64 | 0 | N/A | 65 | 1 | 2 | 1 +PIN | FC<0> | 64 | 0 | N/A | 43 | 2 | 2 | 1 | 1 | 1 +PIN | A<17> | 64 | 0 | N/A | 84 | 4 | 2 | 3 | 2 | 1 | 0 | 7 | 0 | 17 +PIN | A<13> | 64 | 0 | N/A | 63 | 3 | 2 | 7 | 2 | 1 | 0 | 9 +PIN | A<24> | 64 | 0 | N/A | 75 | 3 | 1 | 17 | 0 | 10 | 0 | 13 +PIN | CLK | 4096 | 0 | N/A | 20 | 25 | 1 | 17 | 1 | 16 | 2 | 8 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 2 | 7 | 2 | 6 | 2 | 5 | 2 | 4 | 2 | 3 | 2 | 2 | 2 | 0 | 1 | 10 | 2 | 9 +PIN | CMD<0> | 64 | 0 | N/A | 54 | 25 | 1 | 17 | 1 | 16 | 2 | 8 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 2 | 7 | 2 | 6 | 2 | 5 | 2 | 4 | 2 | 3 | 2 | 2 | 2 | 0 | 1 | 10 | 2 | 9 +PIN | CMD<1> | 64 | 0 | N/A | 21 | 25 | 1 | 17 | 1 | 16 | 2 | 8 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 2 | 7 | 2 | 6 | 2 | 5 | 2 | 4 | 2 | 3 | 2 | 2 | 2 | 0 | 1 | 10 | 2 | 9 +PIN | A<25> | 64 | 0 | N/A | 13 | 2 | 1 | 16 | 0 | 14 +PIN | A<2> | 64 | 0 | N/A | 55 | 10 | 2 | 8 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 9 +PIN | A<3> | 64 | 0 | N/A | 62 | 9 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 15 +PIN | A<4> | 64 | 0 | N/A | 27 | 8 | 2 | 16 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 13 +PIN | A<5> | 64 | 0 | N/A | 90 | 7 | 2 | 15 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 11 +PIN | A<6> | 64 | 0 | N/A | 67 | 6 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 14 +PIN | A<7> | 64 | 0 | N/A | 10 | 5 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 8 +PIN | A<8> | 64 | 0 | N/A | 12 | 4 | 2 | 12 | 2 | 11 | 2 | 10 | 0 | 13 +PIN | A<9> | 64 | 0 | N/A | 15 | 3 | 2 | 11 | 2 | 10 | 0 | 11 +PIN | A<10> | 64 | 0 | N/A | 83 | 3 | 2 | 10 | 0 | 7 | 0 | 16 +PIN | A<11> | 64 | 0 | N/A | 3 | 2 | 1 | 15 | 0 | 8 +PIN | A<21> | 64 | 0 | N/A | 72 | 2 | 1 | 14 | 0 | 10 +PIN | A<22> | 64 | 0 | N/A | 49 | 2 | 1 | 13 | 0 | 17 +PIN | A<23> | 64 | 0 | N/A | 68 | 2 | 1 | 12 | 0 | 10 +PIN | A<12> | 64 | 0 | N/A | 92 | 2 | 1 | 11 | 0 | 17 +PIN | A<14> | 64 | 0 | N/A | 74 | 3 | 2 | 6 | 2 | 1 | 0 | 16 +PIN | A<15> | 64 | 0 | N/A | 5 | 3 | 2 | 5 | 2 | 1 | 0 | 12 +PIN | A<16> | 64 | 0 | N/A | 47 | 4 | 2 | 4 | 2 | 1 | 0 | 9 | 0 | 14 +PIN | A<18> | 64 | 0 | N/A | 70 | 4 | 2 | 2 | 2 | 1 | 0 | 8 | 0 | 15 +PIN | A<19> | 64 | 0 | N/A | 59 | 4 | 2 | 0 | 2 | 1 | 0 | 12 | 0 | 11 +PIN | A<20> | 64 | 0 | N/A | 50 | 2 | 1 | 10 | 0 | 16 +PIN | FC<2> | 64 | 0 | N/A | 82 | 2 | 2 | 1 | 0 | 12 +PIN | nAS | 64 | 0 | N/A | 9 | 1 | 2 | 1 +PIN | CLKdat | 64 | 0 | N/A | 7 | 1 | 2 | 1 +PIN | A<30> | 64 | 0 | N/A | 89 | 1 | 0 | 15 +PIN | A<29> | 64 | 0 | N/A | 88 | 1 | 0 | 15 +PIN | A<28> | 64 | 0 | N/A | 66 | 1 | 0 | 15 +PIN | A<31> | 64 | 0 | N/A | 1 | 1 | 0 | 12 +PIN | STERM | 64 | 0 | N/A | 86 | 12 | 1 | 1 | 0 | 12 | 0 | 7 | 0 | 8 | 0 | 9 | 0 | 10 | 0 | 11 | 0 | 13 | 0 | 14 | 0 | 15 | 0 | 16 | 0 | 17 +PIN | nFPUCS | 536871040 | 0 | N/A | 29 +PIN | nSTERM | 536871040 | 0 | N/A | 87 diff --git a/sterminator/XC9572XL/STERMINATOR.nga b/sterminator/XC9572XL/STERMINATOR.nga new file mode 100644 index 0000000..d91728c --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.nga @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$33042<,Fz_t)LFN^QWAU"380$O=85+OqV{ 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42>28:87c?;8;28yv77:3:1>v3i0;5:?8e328>87)?;9;337>h6<10:7p}>0083>7}:n90<463l4;376>"6<00:<>5a15:96>{t99:1<736>5rsgd94?4|5o:1;;52c58205=#9=31===4n06;>1=z{oo1<73685rsgf94?4|5o:1;952c5827`=#9=31===4n06;>3=z{oi1<736:5rsg`94?4|5o:1:i52c5827f=#9=31===4n06;>==z{ok1<77}:n90:>n52c68:`>"6<00m56`>4982?xua?3:1>v3i0;31f>;d?33h7)?;9;d:?k730380q~h9:1818`7288j70m8:8`8 42>2o30b<:7:29~wc3=838p1k>513;89f1=1h1/=975f89m51>=<2wxj94?:3y>b5<6:116o:469:&20<44134i<6494$06:>c?36:5rsg394?4|5o:1=?>4=b59=4=#9=31j45a15:9<>{zutwKLNu73e85==`d0:lvLMLt0|BCT~{GH \ No newline at end of file diff --git a/sterminator/XC9572XL/STERMINATOR.pad b/sterminator/XC9572XL/STERMINATOR.pad new file mode 100644 index 0000000..cfc0293 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.pad @@ -0,0 +1,93 @@ +Release 8.1i - Fit P.20131013 +Copyright(c) 1995-2003 Xilinx Inc. All rights reserved + +10-26-2021 9:01PM + +NOTE: This file is designed to be imported into a spreadsheet program +such as Microsoft Excel for viewing, printing and sorting. The pipe '|' +character is used as the data field separator. +This file is also designed to support parsing. + +Input file: STERMINATOR.ngd +output file: STERMINATOR.pad +Part type: xc9572xl +Speed grade: -5 +Package: vq64 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|{blank}|Slew Rate|Termination|{blank}|Voltage|Constraint| +P1|A<31>|I|I/O|INPUT||||||||| +P2|A<11>|I|I/O/GTS2|INPUT||||||||| +P3|VCC||VCCINT|||||||||| +P4|A<15>|I|I/O|INPUT||||||||| +P5|CLKdat|I|I/O/GTS1|INPUT||||||||| +P6|nAS|I|I/O|INPUT||||||||| +P7|A<7>|I|I/O|INPUT||||||||| +P8|TIE||I/O|||||||||| +P9|A<8>|I|I/O|INPUT||||||||| +P10|A<25>|I|I/O|INPUT||||||||| +P11|A<9>|I|I/O|INPUT||||||||| +P12|TIE||I/O|||||||||| +P13|TIE||I/O|||||||||| +P14|GND||GND|||||||||| +P15|CLK|GCK|I/O/GCK1|||||||||| +P16|CMD<1>|I|I/O/GCK2|INPUT||||||||| +P17|TIE||I/O/GCK3|||||||||| +P18|TIE||I/O|||||||||| +P19|TIE||I/O|||||||||| +P20|A<4>|I|I/O|INPUT||||||||| +P21|GND||GND|||||||||| +P22|nFPUCS|O|I/O|OUTPUT||||||||| +P23|TIE||I/O|||||||||| +P24|TIE||I/O|||||||||| +P25|TIE||I/O|||||||||| +P26|VCC||VCCIO|||||||||| +P27|TIE||I/O|||||||||| +P28|TDI||TDI|||||||||| +P29|TMS||TMS|||||||||| +P30|TCK||TCK|||||||||| +P31|FC<0>|I|I/O|INPUT||||||||| +P32|TIE||I/O|||||||||| +P33|TIE||I/O|||||||||| +P34|A<16>|I|I/O|INPUT||||||||| +P35|A<22>|I|I/O|INPUT||||||||| +P36|A<20>|I|I/O|INPUT||||||||| +P37|VCC||VCCINT|||||||||| +P38|TIE||I/O|||||||||| +P39|CMD<0>|I|I/O|INPUT||||||||| +P40|A<2>|I|I/O|INPUT||||||||| +P41|GND||GND|||||||||| +P42|A<19>|I|I/O|INPUT||||||||| +P43|A<3>|I|I/O|INPUT||||||||| +P44|A<13>|I|I/O|INPUT||||||||| +P45|FC<1>|I|I/O|INPUT||||||||| +P46|A<28>|I|I/O|INPUT||||||||| +P47|A<6>|I|I/O|INPUT||||||||| +P48|A<23>|I|I/O|INPUT||||||||| +P49|A<18>|I|I/O|INPUT||||||||| +P50|A<21>|I|I/O|INPUT||||||||| +P51|A<14>|I|I/O|INPUT||||||||| +P52|A<24>|I|I/O|INPUT||||||||| +P53|TDO||TDO|||||||||| +P54|GND||GND|||||||||| +P55|VCC||VCCIO|||||||||| +P56|FC<2>|I|I/O|INPUT||||||||| +P57|A<10>|I|I/O|INPUT||||||||| +P58|A<17>|I|I/O|INPUT||||||||| +P59|STERM|I|I/O|INPUT||||||||| +P60|nSTERM|O|I/O|OUTPUT||||||||| +P61|A<29>|I|I/O|INPUT||||||||| +P62|A<30>|I|I/O|INPUT||||||||| +P63|A<5>|I|I/O|INPUT||||||||| +P64|A<12>|I|I/O/GSR|INPUT||||||||| + +To preserve the pinout above for future design iterations in +Project Navigator simply execute the (Lock Pins) process +located under the (Implement Design) process in a toolbox named +(Optional Implementation Tools) or invoke PIN2UCF from the +command line. The location constraints will be written into your +specified UCF file + + diff --git a/sterminator/XC9572XL/STERMINATOR.pnx b/sterminator/XC9572XL/STERMINATOR.pnx new file mode 100644 index 0000000..7f1e976 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.pnx @@ -0,0 +1,18 @@ + + + + + + +]> + diff --git a/sterminator/XC9572XL/STERMINATOR.prj b/sterminator/XC9572XL/STERMINATOR.prj new file mode 100644 index 0000000..b7ca504 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.prj @@ -0,0 +1 @@ +verilog work "../STERMINATOR.v" diff --git a/sterminator/XC9572XL/STERMINATOR.rpt b/sterminator/XC9572XL/STERMINATOR.rpt new file mode 100644 index 0000000..5ad36fa --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.rpt @@ -0,0 +1,579 @@ + +cpldfit: version P.20131013 Xilinx Inc. + Fitter Report +Design Name: STERMINATOR Date: 10-26-2021, 9:01PM +Device Used: XC9572XL-5-VQ64 +Fitting Status: Successful + +************************* Mapped Resource Summary ************************** + +Macrocells Product Terms Function Block Registers Pins +Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot +28 /72 ( 39%) 114 /360 ( 32%) 92 /216 ( 43%) 25 /72 ( 35%) 39 /52 ( 75%) + +** Function Block Resources ** + +Function Mcells FB Inps Pterms IO +Block Used/Tot Used/Tot Used/Tot Used/Tot +FB1 1/18 54/54* 52/90 6/13 +FB2 9/18 14/54 18/90 13/13* +FB3 18/18* 24/54 44/90 8/14 +FB4 0/18 0/54 0/90 12/12* + ----- ----- ----- ----- + 28/72 92/216 114/360 39/52 + +* - Resource is exhausted + +** Global Control Resources ** + +Signal 'CLK' mapped onto global clock net GCK1. +Global output enable net(s) unused. +Global set/reset net(s) unused. + +** Pin Resources ** + +Signal Type Required Mapped | Pin Type Used Total +------------------------------------|------------------------------------ +Input : 36 36 | I/O : 34 46 +Output : 2 2 | GCK/IO : 2 3 +Bidirectional : 0 0 | GTS/IO : 2 2 +GCK : 1 1 | GSR/IO : 1 1 +GTS : 0 0 | +GSR : 0 0 | + ---- ---- + Total 39 39 + +** Power Data ** + +There are 28 macrocells in high performance mode (MCHP). +There are 0 macrocells in low power mode (MCLP). +End of Mapped Resource Summary + ************************** Errors and Warnings *************************** + +WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will + use the default filename of 'STERMINATOR.ise'. + ************************* Summary of Mapped Logic ************************ + +** 2 Outputs ** + +Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init +Name Pts Inps No. Type Use Mode Rate State +nSTERM 2 4 FB2_2 60 I/O O STD FAST +nFPUCS 2 12 FB3_2 22 I/O O STD FAST + +** 26 Buried Nodes ** + +Signal Total Total Loc Pwr Reg Init +Name Pts Inps Mode State +$OpTx$BIN_STEP$409 52 54 FB1_13 STD +NR<9> 2 3 FB2_11 STD RESET +NR<1> 2 3 FB2_12 STD RESET +NR<12> 2 3 FB2_13 STD RESET +NR<11> 2 3 FB2_14 STD RESET +NR<10> 2 3 FB2_15 STD RESET +NR<0> 2 3 FB2_16 STD RESET +NB<1> 2 3 FB2_17 STD RESET +NB<0> 2 3 FB2_18 STD RESET +NR<8> 2 3 FB3_1 STD RESET +NR<7> 2 3 FB3_3 STD RESET +NR<6> 2 3 FB3_4 STD RESET +NR<5> 2 3 FB3_5 STD RESET +NR<4> 2 3 FB3_6 STD RESET +NR<3> 2 3 FB3_7 STD RESET +NR<2> 2 3 FB3_8 STD RESET +NC<0> 2 3 FB3_9 STD RESET +NA 2 3 FB3_10 STD RESET +NC<8> 3 11 FB3_11 STD RESET +NC<7> 3 10 FB3_12 STD RESET +NC<6> 3 9 FB3_13 STD RESET +NC<5> 3 8 FB3_14 STD RESET +NC<4> 3 7 FB3_15 STD RESET +NC<3> 3 6 FB3_16 STD RESET +NC<2> 3 5 FB3_17 STD RESET +NC<1> 3 4 FB3_18 STD RESET + +** 37 Inputs ** + +Signal Loc Pin Pin Pin +Name No. Type Use +A<8> FB1_5 9 I/O I +A<25> FB1_6 10 I/O I +A<9> FB1_8 11 I/O I +CLK FB1_9 15~ GCK/I/O GCK +CMD<1> FB1_11 16 GCK/I/O I +A<4> FB1_17 20 I/O I +A<17> FB2_3 58 I/O I +STERM FB2_4 59 I/O I +A<29> FB2_5 61 I/O I +A<30> FB2_6 62 I/O I +A<5> FB2_8 63 I/O I +A<12> FB2_9 64 GSR/I/O I +A<31> FB2_10 1 I/O I +A<11> FB2_11 2 GTS/I/O I +A<15> FB2_12 4 I/O I +CLKdat FB2_14 5 GTS/I/O I +nAS FB2_15 6 I/O I +A<7> FB2_17 7 I/O I +FC<0> FB3_3 31 I/O I +A<16> FB3_6 34 I/O I +CMD<0> FB3_10 39 I/O I +A<2> FB3_12 40 I/O I +A<22> FB3_14 35 I/O I +A<20> FB3_15 36 I/O I +A<19> FB3_16 42 I/O I +A<3> FB4_2 43 I/O I +A<28> FB4_3 46 I/O I +A<6> FB4_4 47 I/O I +A<13> FB4_5 44 I/O I +A<18> FB4_6 49 I/O I +FC<1> FB4_8 45 I/O I +A<14> FB4_10 51 I/O I +A<23> FB4_11 48 I/O I +A<24> FB4_12 52 I/O I +A<21> FB4_14 50 I/O I +FC<2> FB4_15 56 I/O I +A<10> FB4_17 57 I/O I + +Legend: +Pin No. - ~ - User Assigned + ************************** Function Block Details ************************ +Legend: +Total Pt - Total product terms used by the macrocell signal +Imp Pt - Product terms imported from other macrocells +Exp Pt - Product terms exported to other macrocells + in direction shown +Unused Pt - Unused local product terms remaining in macrocell +Loc - Location where logic was mapped in device +Pin Type/Use - I - Input GCK - Global Clock + O - Output GTS - Global Output Enable + (b) - Buried macrocell GSR - Global Set/Reset +X - Signal used as input to the macrocell logic. +Pin No. - ~ - User Assigned + *********************************** FB1 *********************************** +Number of function block inputs used/remaining: 54/0 +Number of signals used by logic mapping into function block: 54 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB1_1 (b) +(unused) 0 0 0 5 FB1_2 8 I/O +(unused) 0 0 0 5 FB1_3 12 I/O +(unused) 0 0 0 5 FB1_4 13 I/O +(unused) 0 0 0 5 FB1_5 9 I/O I +(unused) 0 0 0 5 FB1_6 10 I/O I +(unused) 0 0 0 5 FB1_7 (b) +(unused) 0 0 \/2 3 FB1_8 11 I/O I +(unused) 0 0 \/5 0 FB1_9 15 GCK/I/O GCK +(unused) 0 0 \/5 0 FB1_10 18 I/O (b) +(unused) 0 0 \/5 0 FB1_11 16 GCK/I/O I +(unused) 0 0 \/5 0 FB1_12 23 I/O (b) +$OpTx$BIN_STEP$409 52 47<- 0 0 FB1_13 (b) (b) +(unused) 0 0 /\5 0 FB1_14 17 GCK/I/O (b) +(unused) 0 0 /\5 0 FB1_15 19 I/O (b) +(unused) 0 0 /\5 0 FB1_16 (b) (b) +(unused) 0 0 /\5 0 FB1_17 20 I/O I +(unused) 0 0 /\5 0 FB1_18 (b) (b) + +Signals Used by Logic in Function Block + 1: A<10> 19: A<2> 37: NC<5> + 2: A<11> 20: A<30> 38: NC<6> + 3: A<12> 21: A<31> 39: NC<7> + 4: A<13> 22: A<3> 40: NC<8> + 5: A<14> 23: A<4> 41: NR<0> + 6: A<15> 24: A<5> 42: NR<10> + 7: A<16> 25: A<6> 43: NR<11> + 8: A<17> 26: A<7> 44: NR<12> + 9: A<18> 27: A<8> 45: NR<1> + 10: A<19> 28: A<9> 46: NR<2> + 11: A<20> 29: FC<2> 47: NR<3> + 12: A<21> 30: NB<0> 48: NR<4> + 13: A<22> 31: NB<1> 49: NR<5> + 14: A<23> 32: NC<0> 50: NR<6> + 15: A<24> 33: NC<1> 51: NR<7> + 16: A<25> 34: NC<2> 52: NR<8> + 17: A<28> 35: NC<3> 53: NR<9> + 18: A<29> 36: NC<4> 54: STERM + +Signal 1 2 3 4 5 6 FB +Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs +$OpTx$BIN_STEP$409 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX...... 54 + 0----+----1----+----2----+----3----+----4----+----5----+----6 + 0 0 0 0 0 0 + *********************************** FB2 *********************************** +Number of function block inputs used/remaining: 14/40 +Number of signals used by logic mapping into function block: 14 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB2_1 (b) +nSTERM 2 0 0 3 FB2_2 60 I/O O +(unused) 0 0 0 5 FB2_3 58 I/O I +(unused) 0 0 0 5 FB2_4 59 I/O I +(unused) 0 0 0 5 FB2_5 61 I/O I +(unused) 0 0 0 5 FB2_6 62 I/O I +(unused) 0 0 0 5 FB2_7 (b) +(unused) 0 0 0 5 FB2_8 63 I/O I +(unused) 0 0 0 5 FB2_9 64 GSR/I/O I +(unused) 0 0 0 5 FB2_10 1 I/O I +NR<9> 2 0 0 3 FB2_11 2 GTS/I/O I +NR<1> 2 0 0 3 FB2_12 4 I/O I +NR<12> 2 0 0 3 FB2_13 (b) (b) +NR<11> 2 0 0 3 FB2_14 5 GTS/I/O I +NR<10> 2 0 0 3 FB2_15 6 I/O I +NR<0> 2 0 0 3 FB2_16 (b) (b) +NB<1> 2 0 0 3 FB2_17 7 I/O I +NB<0> 2 0 0 3 FB2_18 (b) (b) + +Signals Used by Logic in Function Block + 1: $OpTx$BIN_STEP$409 6: A<22> 11: CMD<1> + 2: A<11> 7: A<23> 12: FC<0> + 3: A<12> 8: A<24> 13: NA + 4: A<20> 9: A<25> 14: STERM + 5: A<21> 10: CMD<0> + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +nSTERM X..........XXX.......................... 4 +NR<9> ...X.....XX............................. 3 +NR<1> ..X......XX............................. 3 +NR<12> ......X..XX............................. 3 +NR<11> .....X...XX............................. 3 +NR<10> ....X....XX............................. 3 +NR<0> .X.......XX............................. 3 +NB<1> ........XXX............................. 3 +NB<0> .......X.XX............................. 3 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB3 *********************************** +Number of function block inputs used/remaining: 24/30 +Number of signals used by logic mapping into function block: 24 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +NR<8> 2 0 0 3 FB3_1 (b) (b) +nFPUCS 2 0 0 3 FB3_2 22 I/O O +NR<7> 2 0 0 3 FB3_3 31 I/O I +NR<6> 2 0 0 3 FB3_4 32 I/O (b) +NR<5> 2 0 0 3 FB3_5 24 I/O (b) +NR<4> 2 0 0 3 FB3_6 34 I/O I +NR<3> 2 0 0 3 FB3_7 (b) (b) +NR<2> 2 0 0 3 FB3_8 25 I/O (b) +NC<0> 2 0 0 3 FB3_9 27 I/O (b) +NA 2 0 0 3 FB3_10 39 I/O I +NC<8> 3 0 0 2 FB3_11 33 I/O (b) +NC<7> 3 0 0 2 FB3_12 40 I/O I +NC<6> 3 0 0 2 FB3_13 (b) (b) +NC<5> 3 0 0 2 FB3_14 35 I/O I +NC<4> 3 0 0 2 FB3_15 36 I/O I +NC<3> 3 0 0 2 FB3_16 42 I/O I +NC<2> 3 0 0 2 FB3_17 38 I/O (b) +NC<1> 3 0 0 2 FB3_18 (b) (b) + +Signals Used by Logic in Function Block + 1: A<10> 9: A<2> 17: CLKdat + 2: A<13> 10: A<3> 18: CMD<0> + 3: A<14> 11: A<4> 19: CMD<1> + 4: A<15> 12: A<5> 20: FC<0> + 5: A<16> 13: A<6> 21: FC<1> + 6: A<17> 14: A<7> 22: FC<2> + 7: A<18> 15: A<8> 23: NA + 8: A<19> 16: A<9> 24: nAS + +Signal 1 2 3 4 FB +Name 0----+----0----+----0----+----0----+----0 Inputs +NR<8> .......X.........XX..................... 3 +nFPUCS .XXXXXXX........X..XXX.X................ 12 +NR<7> ......X..........XX..................... 3 +NR<6> .....X...........XX..................... 3 +NR<5> ....X............XX..................... 3 +NR<4> ...X.............XX..................... 3 +NR<3> ..X..............XX..................... 3 +NR<2> .X...............XX..................... 3 +NC<0> ........X........XX..................... 3 +NA .................XX...X................. 3 +NC<8> X.......XXXXXXXX.XX..................... 11 +NC<7> ........XXXXXXXX.XX..................... 10 +NC<6> ........XXXXXXX..XX..................... 9 +NC<5> ........XXXXXX...XX..................... 8 +NC<4> ........XXXXX....XX..................... 7 +NC<3> ........XXXX.....XX..................... 6 +NC<2> ........XXX......XX..................... 5 +NC<1> ........XX.......XX..................... 4 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 + *********************************** FB4 *********************************** +Number of function block inputs used/remaining: 0/54 +Number of signals used by logic mapping into function block: 0 +Signal Total Imp Exp Unused Loc Pin Pin Pin +Name Pt Pt Pt Pt # Type Use +(unused) 0 0 0 5 FB4_1 (b) +(unused) 0 0 0 5 FB4_2 43 I/O I +(unused) 0 0 0 5 FB4_3 46 I/O I +(unused) 0 0 0 5 FB4_4 47 I/O I +(unused) 0 0 0 5 FB4_5 44 I/O I +(unused) 0 0 0 5 FB4_6 49 I/O I +(unused) 0 0 0 5 FB4_7 (b) +(unused) 0 0 0 5 FB4_8 45 I/O I +(unused) 0 0 0 5 FB4_9 (b) +(unused) 0 0 0 5 FB4_10 51 I/O I +(unused) 0 0 0 5 FB4_11 48 I/O I +(unused) 0 0 0 5 FB4_12 52 I/O I +(unused) 0 0 0 5 FB4_13 (b) +(unused) 0 0 0 5 FB4_14 50 I/O I +(unused) 0 0 0 5 FB4_15 56 I/O I +(unused) 0 0 0 5 FB4_16 (b) +(unused) 0 0 0 5 FB4_17 57 I/O I +(unused) 0 0 0 5 FB4_18 (b) + ******************************* Equations ******************************** + +********** Mapped Logic ********** + + +$OpTx$BIN_STEP$409 <= ((EXP9_.EXP) + OR (A(5) AND NOT NC(3) AND NOT STERM) + OR (NOT A(5) AND NC(3) AND NOT STERM) + OR (A(9) AND NOT NC(7) AND NOT STERM) + OR (NOT A(9) AND NC(7) AND NOT STERM) + OR (A(19) AND NOT NR(8) AND NOT STERM) + OR (EXP12_.EXP) + OR (NOT A(24) AND NB(0) AND NOT STERM) + OR (A(4) AND NOT NC(2) AND NOT STERM) + OR (NOT A(4) AND NC(2) AND NOT STERM) + OR (A(8) AND NOT NC(6) AND NOT STERM) + OR (NOT A(8) AND NC(6) AND NOT STERM) + OR (NOT FC(2) AND NOT STERM) + OR (A(31) AND NOT STERM) + OR (A(15) AND NOT NR(4) AND NOT STERM) + OR (NOT A(15) AND NR(4) AND NOT STERM) + OR (NOT A(19) AND NR(8) AND NOT STERM)); + + + + + + + + + + + + + + + + + + + + + +FDCPE_NA: FDCPE port map (NA,NA_D,CLK,'0','0'); +NA_D <= ((CMD(0) AND NOT CMD(1)) + OR (NOT CMD(1) AND NA)); + +FDCPE_NB0: FDCPE port map (NB(0),A(24),CLK,'0','0',NB_CE(0)); +NB_CE(0) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NB1: FDCPE port map (NB(1),A(25),CLK,'0','0',NB_CE(1)); +NB_CE(1) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC0: FDCPE port map (NC(0),NOT A(2),CLK,'0','0',NC_CE(0)); +NC_CE(0) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC1: FDCPE port map (NC(1),NC_D(1),CLK,'0','0',NC_CE(1)); +NC_D(1) <= A(2) + XOR +NC_D(1) <= A(3); +NC_CE(1) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC2: FDCPE port map (NC(2),NC_D(2),CLK,'0','0',NC_CE(2)); +NC_D(2) <= A(4) + XOR +NC_D(2) <= (A(2) AND A(3)); +NC_CE(2) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC3: FDCPE port map (NC(3),NC_D(3),CLK,'0','0',NC_CE(3)); +NC_D(3) <= A(5) + XOR +NC_D(3) <= (A(2) AND A(3) AND A(4)); +NC_CE(3) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC4: FDCPE port map (NC(4),NC_D(4),CLK,'0','0',NC_CE(4)); +NC_D(4) <= A(6) + XOR +NC_D(4) <= (A(2) AND A(3) AND A(4) AND A(5)); +NC_CE(4) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC5: FDCPE port map (NC(5),NC_D(5),CLK,'0','0',NC_CE(5)); +NC_D(5) <= A(7) + XOR +NC_D(5) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6)); +NC_CE(5) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC6: FDCPE port map (NC(6),NC_D(6),CLK,'0','0',NC_CE(6)); +NC_D(6) <= A(8) + XOR +NC_D(6) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7)); +NC_CE(6) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC7: FDCPE port map (NC(7),NC_D(7),CLK,'0','0',NC_CE(7)); +NC_D(7) <= A(9) + XOR +NC_D(7) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND + A(8)); +NC_CE(7) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NC8: FDCPE port map (NC(8),NC_D(8),CLK,'0','0',NC_CE(8)); +NC_D(8) <= A(10) + XOR +NC_D(8) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND + A(8) AND A(9)); +NC_CE(8) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR0: FDCPE port map (NR(0),A(11),CLK,'0','0',NR_CE(0)); +NR_CE(0) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR1: FDCPE port map (NR(1),A(12),CLK,'0','0',NR_CE(1)); +NR_CE(1) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR2: FDCPE port map (NR(2),A(13),CLK,'0','0',NR_CE(2)); +NR_CE(2) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR3: FDCPE port map (NR(3),A(14),CLK,'0','0',NR_CE(3)); +NR_CE(3) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR4: FDCPE port map (NR(4),A(15),CLK,'0','0',NR_CE(4)); +NR_CE(4) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR5: FDCPE port map (NR(5),A(16),CLK,'0','0',NR_CE(5)); +NR_CE(5) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR6: FDCPE port map (NR(6),A(17),CLK,'0','0',NR_CE(6)); +NR_CE(6) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR7: FDCPE port map (NR(7),A(18),CLK,'0','0',NR_CE(7)); +NR_CE(7) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR8: FDCPE port map (NR(8),A(19),CLK,'0','0',NR_CE(8)); +NR_CE(8) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR9: FDCPE port map (NR(9),A(20),CLK,'0','0',NR_CE(9)); +NR_CE(9) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR10: FDCPE port map (NR(10),A(21),CLK,'0','0',NR_CE(10)); +NR_CE(10) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR11: FDCPE port map (NR(11),A(22),CLK,'0','0',NR_CE(11)); +NR_CE(11) <= (CMD(0) AND NOT CMD(1)); + +FDCPE_NR12: FDCPE port map (NR(12),A(23),CLK,'0','0',NR_CE(12)); +NR_CE(12) <= (CMD(0) AND NOT CMD(1)); + + +nFPUCS <= NOT (((FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND + NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT nAS) + OR (FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND + NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT CLKdat))); + + +nSTERM <= NOT (((STERM AND NOT $OpTx$BIN_STEP$409) + OR (NOT FC(0) AND NA AND NOT $OpTx$BIN_STEP$409))); + +Register Legend: + FDCPE (Q,D,C,CLR,PRE,CE); + FTCPE (Q,D,C,CLR,PRE,CE); + LDCP (Q,D,G,CLR,PRE); + + ****************************** Device Pin Out ***************************** + +Device : XC9572XL-5-VQ64 + + + ----------------------------------------------- + /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \ + | 49 32 | + | 50 31 | + | 51 30 | + | 52 29 | + | 53 28 | + | 54 27 | + | 55 26 | + | 56 XC9572XL-5-VQ64 25 | + | 57 24 | + | 58 23 | + | 59 22 | + | 60 21 | + | 61 20 | + | 62 19 | + | 63 18 | + | 64 17 | + \ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 / + ----------------------------------------------- + + +Pin Signal Pin Signal +No. Name No. Name + 1 A<31> 33 KPR + 2 A<11> 34 A<16> + 3 VCC 35 A<22> + 4 A<15> 36 A<20> + 5 CLKdat 37 VCC + 6 nAS 38 KPR + 7 A<7> 39 CMD<0> + 8 KPR 40 A<2> + 9 A<8> 41 GND + 10 A<25> 42 A<19> + 11 A<9> 43 A<3> + 12 KPR 44 A<13> + 13 KPR 45 FC<1> + 14 GND 46 A<28> + 15 CLK 47 A<6> + 16 CMD<1> 48 A<23> + 17 KPR 49 A<18> + 18 KPR 50 A<21> + 19 KPR 51 A<14> + 20 A<4> 52 A<24> + 21 GND 53 TDO + 22 nFPUCS 54 GND + 23 KPR 55 VCC + 24 KPR 56 FC<2> + 25 KPR 57 A<10> + 26 VCC 58 A<17> + 27 KPR 59 STERM + 28 TDI 60 nSTERM + 29 TMS 61 A<29> + 30 TCK 62 A<30> + 31 FC<0> 63 A<5> + 32 KPR 64 A<12> + + +Legend : NC = Not Connected, unbonded pin + PGND = Unused I/O configured as additional Ground pin + TIE = Unused I/O floating -- must tie to VCC, GND or other signal + KPR = Unused I/O with weak keeper (leave unconnected) + VCC = Dedicated Power Pin + GND = Dedicated Ground Pin + TDI = Test Data In, JTAG pin + TDO = Test Data Out, JTAG pin + TCK = Test Clock, JTAG pin + TMS = Test Mode Select, JTAG pin + PROHIBITED = User reserved pin + **************************** Compiler Options **************************** + +Following is a list of all global compiler options used by the fitter run. + +Device(s) Specified : xc9572xl-5-VQ64 +Optimization Method : SPEED +Multi-Level Logic Optimization : ON +Ignore Timing Specifications : OFF +Default Register Power Up Value : LOW +Keep User Location Constraints : ON +What-You-See-Is-What-You-Get : OFF +Exhaustive Fitting : OFF +Keep Unused Inputs : OFF +Slew Rate : FAST +Power Mode : STD +Ground on Unused IOs : OFF +Set I/O Pin Termination : KEEPER +Global Clock Optimization : ON +Global Set/Reset Optimization : ON +Global Ouput Enable Optimization : ON +Input Limit : 54 +Pterm Limit : 25 diff --git a/sterminator/XC9572XL/STERMINATOR.stx b/sterminator/XC9572XL/STERMINATOR.stx new file mode 100644 index 0000000..e69de29 diff --git a/sterminator/XC9572XL/STERMINATOR.syr b/sterminator/XC9572XL/STERMINATOR.syr new file mode 100644 index 0000000..2a64981 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.syr @@ -0,0 +1,225 @@ +Release 14.7 - xst P.20131013 (nt) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.08 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.08 secs + +--> Reading design: STERMINATOR.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "STERMINATOR.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "STERMINATOR" +Output Format : NGC +Target Device : XC9500XL CPLDs + +---- Source Options +Top Module Name : STERMINATOR +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +Mux Extraction : Yes +Resource Sharing : YES + +---- Target Options +Add IO Buffers : YES +MACRO Preserve : YES +XOR Preserve : YES +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : Yes +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Verilog 2001 : YES + +---- Other Options +Clock Enable : YES +wysiwyg : NO + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../STERMINATOR.v" in library work +Module compiled +No errors in compilation +Analysis of file <"STERMINATOR.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "../STERMINATOR.v". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 9-bit register for signal . + Found 9-bit adder for signal created at line 51. + Found 13-bit register for signal . + Found 2-bit comparator equal for signal created at line 59. + Found 13-bit comparator equal for signal created at line 59. + Found 9-bit comparator equal for signal created at line 59. + Summary: + inferred 1 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). + inferred 3 Comparator(s). +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 1 + 9-bit adder : 1 +# Registers : 4 + 1-bit register : 1 + 13-bit register : 1 + 2-bit register : 1 + 9-bit register : 1 +# Comparators : 3 + 13-bit comparator equal : 1 + 2-bit comparator equal : 1 + 9-bit comparator equal : 1 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 1 + 9-bit adder : 1 +# Registers : 1 + Flip-Flops : 1 +# Comparators : 3 + 13-bit comparator equal : 1 + 2-bit comparator equal : 1 + 9-bit comparator equal : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : STERMINATOR.ngr +Top Level Output File Name : STERMINATOR +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : Yes +Target Technology : XC9500XL CPLDs +Macro Preserve : YES +XOR Preserve : YES +Clock Enable : YES +wysiwyg : NO + +Design Statistics +# IOs : 42 + +Cell Usage : +# BELS : 102 +# AND2 : 14 +# AND3 : 5 +# AND4 : 2 +# AND5 : 1 +# AND8 : 2 +# GND : 1 +# INV : 41 +# OR2 : 4 +# XOR2 : 32 +# FlipFlops/Latches : 25 +# FD : 1 +# FDCE : 24 +# IO Buffers : 39 +# IBUF : 37 +# OBUF : 2 +========================================================================= + + +Total REAL time to Xst completion: 2.00 secs +Total CPU time to Xst completion: 2.08 secs + +--> + +Total memory usage is 225560 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 2 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/sterminator/XC9572XL/STERMINATOR.tim b/sterminator/XC9572XL/STERMINATOR.tim new file mode 100644 index 0000000..e69de29 diff --git a/sterminator/XC9572XL/STERMINATOR.tspec b/sterminator/XC9572XL/STERMINATOR.tspec new file mode 100644 index 0000000..ddcf210 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.tspec @@ -0,0 +1,182 @@ +AUTO_TS_P2P:FROM:FC<1>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:FC<0>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<17>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<13>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<14>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<15>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<16>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<18>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:A<19>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:FC<2>:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:nAS:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:CLKdat:TO:nFPUCS:1 +AUTO_TS_P2P:FROM:STERM:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<17>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:CLK:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<10>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<7>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<11>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<18>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<13>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<2>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<16>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<24>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<21>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<23>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<5>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<9>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<19>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<22>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<12>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<14>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<20>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<3>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<30>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<29>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<28>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<25>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<6>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<4>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<8>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:FC<2>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<31>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:A<15>:TO:nSTERM:1 +AUTO_TS_P2P:FROM:FC<0>:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<6>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<8>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<5>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<0>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<7>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<2>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<0>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<5>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NB<0>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<10>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<12>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<3>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<7>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<8>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<11>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<1>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<3>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<9>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<1>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NB<1>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<4>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<2>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NC<6>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NR<4>.Q:TO:nSTERM:1 +AUTO_TS_F2P:FROM:NA.Q:TO:nSTERM:1 +AUTO_TS_F2F:FROM:NA.Q:TO:NA.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NA.D:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NA.D:1 +AUTO_TS_P2F:FROM:CLK:TO:NA.D:1 +AUTO_TS_P2F:FROM:A<24>:TO:NB<0>.D:1 +AUTO_TS_P2F:FROM:CLK:TO:FCLKIO_0:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NB<0>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NB<0>.CE:1 +AUTO_TS_P2F:FROM:A<25>:TO:NB<1>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NB<1>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NB<1>.CE:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<0>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<0>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<0>.CE:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<1>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<1>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<1>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<1>.CE:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<2>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<2>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<2>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<2>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<2>.CE:1 +AUTO_TS_P2F:FROM:A<5>:TO:NC<3>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<3>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<3>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<3>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<3>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<3>.CE:1 +AUTO_TS_P2F:FROM:A<6>:TO:NC<4>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<4>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<4>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<4>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:NC<4>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<4>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<4>.CE:1 +AUTO_TS_P2F:FROM:A<7>:TO:NC<5>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<5>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<5>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<5>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:NC<5>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:NC<5>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<5>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<5>.CE:1 +AUTO_TS_P2F:FROM:A<8>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:A<7>:TO:NC<6>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<6>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<6>.CE:1 +AUTO_TS_P2F:FROM:A<9>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<7>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:A<8>:TO:NC<7>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<7>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<7>.CE:1 +AUTO_TS_P2F:FROM:A<10>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<2>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<3>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<4>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<5>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<6>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<7>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<8>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:A<9>:TO:NC<8>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NC<8>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NC<8>.CE:1 +AUTO_TS_P2F:FROM:A<11>:TO:NR<0>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<0>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<0>.CE:1 +AUTO_TS_P2F:FROM:A<21>:TO:NR<10>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<10>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<10>.CE:1 +AUTO_TS_P2F:FROM:A<22>:TO:NR<11>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<11>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<11>.CE:1 +AUTO_TS_P2F:FROM:A<23>:TO:NR<12>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<12>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<12>.CE:1 +AUTO_TS_P2F:FROM:A<12>:TO:NR<1>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<1>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<1>.CE:1 +AUTO_TS_P2F:FROM:A<13>:TO:NR<2>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<2>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<2>.CE:1 +AUTO_TS_P2F:FROM:A<14>:TO:NR<3>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<3>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<3>.CE:1 +AUTO_TS_P2F:FROM:A<15>:TO:NR<4>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<4>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<4>.CE:1 +AUTO_TS_P2F:FROM:A<16>:TO:NR<5>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<5>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<5>.CE:1 +AUTO_TS_P2F:FROM:A<17>:TO:NR<6>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<6>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<6>.CE:1 +AUTO_TS_P2F:FROM:A<18>:TO:NR<7>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<7>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<7>.CE:1 +AUTO_TS_P2F:FROM:A<19>:TO:NR<8>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<8>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<8>.CE:1 +AUTO_TS_P2F:FROM:A<20>:TO:NR<9>.D:1 +AUTO_TS_P2F:FROM:CMD<0>:TO:NR<9>.CE:1 +AUTO_TS_P2F:FROM:CMD<1>:TO:NR<9>.CE:1 diff --git a/sterminator/XC9572XL/STERMINATOR.vm6 b/sterminator/XC9572XL/STERMINATOR.vm6 new file mode 100644 index 0000000..98589df --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.vm6 @@ -0,0 +1,2091 @@ +NDS Database: version P.20131013 + +NDS_INFO | xc9500xl | 9572XL64 | XC9572XL-5-VQ64 + +DEVICE | 9572XL | 9572XL64 | + +NETWORK | STERMINATOR | 0 | 0 | 16391 + +INPUT_INSTANCE | 0 | 0 | NULL | FC_1_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | FC<1> | 1978 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | FC_1_IBUF | 1911 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_1_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | FC_0_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | FC<0> | 1979 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | FC_0_IBUF | 1912 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_0_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_17_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<17> | 1980 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_13_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<13> | 1981 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_24_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<24> | 1982 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | CLK_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | CLK | 1983 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 3 | 5 | II_FCLK +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK + +INPUT_INSTANCE | 0 | 0 | NULL | CMD_0_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | CMD<0> | 2006 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | CMD_1_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | CMD<1> | 2007 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NB<0> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NB<0> | 1917 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<0>.Q | NB<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NB<0>.SI | NB<0> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NB<0>.D1 | 2016 | ? | 0 | 4096 | NB<0> | NULL | NULL | NB<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NB<0>.D2 | 2017 | ? | 0 | 4096 | NB<0> | NULL | NULL | NB<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_24_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NB<0>.CE | 2018 | ? | 0 | 4096 | NB<0> | NULL | NULL | NB<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NB<0>.REG | NB<0> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NB<0>.D | 2015 | ? | 0 | 0 | NB<0> | NULL | NULL | NB<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NB<0>.CE | 2018 | ? | 0 | 4096 | NB<0> | NULL | NULL | NB<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NB<0>.Q | 2019 | ? | 0 | 0 | NB<0> | NULL | NULL | NB<0>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_25_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<25> | 1984 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_25_IBUF | 1918 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_25_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NB<1> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_25_IBUF | 1918 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_25_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NB<1> | 1919 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<1>.Q | NB<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NB<1>.SI | NB<1> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_25_IBUF | 1918 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_25_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NB<1>.D1 | 2021 | ? | 0 | 4096 | NB<1> | NULL | NULL | NB<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NB<1>.D2 | 2022 | ? | 0 | 4096 | NB<1> | NULL | NULL | NB<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_25_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NB<1>.CE | 2023 | ? | 0 | 4096 | NB<1> | NULL | NULL | NB<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NB<1>.REG | NB<1> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NB<1>.D | 2020 | ? | 0 | 0 | NB<1> | NULL | NULL | NB<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NB<1>.CE | 2023 | ? | 0 | 4096 | NB<1> | NULL | NULL | NB<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NB<1>.Q | 2024 | ? | 0 | 0 | NB<1> | NULL | NULL | NB<1>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_2_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<2> | 1985 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<0> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<0> | 1921 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<0>.Q | NC<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<0>.SI | NC<0> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<0>.D1 | 2026 | ? | 0 | 4096 | NC<0> | NULL | NULL | NC<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<0>.D2 | 2027 | ? | 0 | 4096 | NC<0> | NULL | NULL | NC<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_FALSE | A_2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<0>.CE | 2028 | ? | 0 | 4096 | NC<0> | NULL | NULL | NC<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<0>.REG | NC<0> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<0>.D | 2025 | ? | 0 | 0 | NC<0> | NULL | NULL | NC<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<0>.CE | 2028 | ? | 0 | 4096 | NC<0> | NULL | NULL | NC<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<0>.Q | 2029 | ? | 0 | 0 | NC<0> | NULL | NULL | NC<0>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_3_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<3> | 1986 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<1> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<1> | 1923 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<1>.Q | NC<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<1>.SI | NC<1> | 0 | 4 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<1>.D1 | 2031 | ? | 0 | 4096 | NC<1> | NULL | NULL | NC<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_2_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<1>.D2 | 2032 | ? | 0 | 4096 | NC<1> | NULL | NULL | NC<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_3_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<1>.CE | 2033 | ? | 0 | 4096 | NC<1> | NULL | NULL | NC<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<1>.REG | NC<1> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<1>.D | 2030 | ? | 0 | 0 | NC<1> | NULL | NULL | NC<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<1>.CE | 2033 | ? | 0 | 4096 | NC<1> | NULL | NULL | NC<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<1>.Q | 2034 | ? | 0 | 0 | NC<1> | NULL | NULL | NC<1>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_4_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<4> | 1987 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<2> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 6 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<2> | 1925 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<2>.Q | NC<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<2>.SI | NC<2> | 0 | 5 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<2>.D1 | 2036 | ? | 0 | 4096 | NC<2> | NULL | NULL | NC<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_4_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<2>.D2 | 2037 | ? | 0 | 4096 | NC<2> | NULL | NULL | NC<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<2>.CE | 2038 | ? | 0 | 4096 | NC<2> | NULL | NULL | NC<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<2>.REG | NC<2> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<2>.D | 2035 | ? | 0 | 0 | NC<2> | NULL | NULL | NC<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<2>.CE | 2038 | ? | 0 | 4096 | NC<2> | NULL | NULL | NC<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<2>.Q | 2039 | ? | 0 | 0 | NC<2> | NULL | NULL | NC<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_5_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<5> | 1988 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<3> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<3> | 1927 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<3>.Q | NC<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<3>.SI | NC<3> | 0 | 6 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<3>.D1 | 2041 | ? | 0 | 4096 | NC<3> | NULL | NULL | NC<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_5_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<3>.D2 | 2042 | ? | 0 | 4096 | NC<3> | NULL | NULL | NC<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 3 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_4_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<3>.CE | 2043 | ? | 0 | 4096 | NC<3> | NULL | NULL | NC<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<3>.REG | NC<3> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<3>.D | 2040 | ? | 0 | 0 | NC<3> | NULL | NULL | NC<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<3>.CE | 2043 | ? | 0 | 4096 | NC<3> | NULL | NULL | NC<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<3>.Q | 2044 | ? | 0 | 0 | NC<3> | NULL | NULL | NC<3>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_6_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<6> | 1989 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<4> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<4> | 1929 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<4>.Q | NC<4> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<4>.SI | NC<4> | 0 | 7 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<4>.D1 | 2046 | ? | 0 | 4096 | NC<4> | NULL | NULL | NC<4>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_6_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<4>.D2 | 2047 | ? | 0 | 4096 | NC<4> | NULL | NULL | NC<4>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_5_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<4>.CE | 2048 | ? | 0 | 4096 | NC<4> | NULL | NULL | NC<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<4>.REG | NC<4> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<4>.D | 2045 | ? | 0 | 0 | NC<4> | NULL | NULL | NC<4>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<4>.CE | 2048 | ? | 0 | 4096 | NC<4> | NULL | NULL | NC<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<4>.Q | 2049 | ? | 0 | 0 | NC<4> | NULL | NULL | NC<4>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_7_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<7> | 1990 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<5> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<5> | 1931 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<5>.Q | NC<5> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<5>.SI | NC<5> | 0 | 8 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<5>.D1 | 2051 | ? | 0 | 4096 | NC<5> | NULL | NULL | NC<5>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_7_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<5>.D2 | 2052 | ? | 0 | 4096 | NC<5> | NULL | NULL | NC<5>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 5 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_5_IBUF | IV_TRUE | A_6_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<5>.CE | 2053 | ? | 0 | 4096 | NC<5> | NULL | NULL | NC<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<5>.REG | NC<5> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<5>.D | 2050 | ? | 0 | 0 | NC<5> | NULL | NULL | NC<5>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<5>.CE | 2053 | ? | 0 | 4096 | NC<5> | NULL | NULL | NC<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<5>.Q | 2054 | ? | 0 | 0 | NC<5> | NULL | NULL | NC<5>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_8_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<8> | 1991 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<6> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 10 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<6> | 1933 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<6>.Q | NC<6> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<6>.SI | NC<6> | 0 | 9 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<6>.D1 | 2056 | ? | 0 | 4096 | NC<6> | NULL | NULL | NC<6>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_8_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<6>.D2 | 2057 | ? | 0 | 4096 | NC<6> | NULL | NULL | NC<6>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 6 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_5_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_7_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<6>.CE | 2058 | ? | 0 | 4096 | NC<6> | NULL | NULL | NC<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<6>.REG | NC<6> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<6>.D | 2055 | ? | 0 | 0 | NC<6> | NULL | NULL | NC<6>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<6>.CE | 2058 | ? | 0 | 4096 | NC<6> | NULL | NULL | NC<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<6>.Q | 2059 | ? | 0 | 0 | NC<6> | NULL | NULL | NC<6>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_9_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<9> | 1992 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<7> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 11 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<7> | 1935 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<7>.Q | NC<7> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<7>.SI | NC<7> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<7>.D1 | 2061 | ? | 0 | 4096 | NC<7> | NULL | NULL | NC<7>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_9_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<7>.D2 | 2062 | ? | 0 | 4096 | NC<7> | NULL | NULL | NC<7>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_5_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_7_IBUF | IV_TRUE | A_8_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<7>.CE | 2063 | ? | 0 | 4096 | NC<7> | NULL | NULL | NC<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<7>.REG | NC<7> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<7>.D | 2060 | ? | 0 | 0 | NC<7> | NULL | NULL | NC<7>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<7>.CE | 2063 | ? | 0 | 4096 | NC<7> | NULL | NULL | NC<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<7>.Q | 2064 | ? | 0 | 0 | NC<7> | NULL | NULL | NC<7>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_10_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<10> | 1993 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NC<8> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 12 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NC<8> | 1937 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<8>.Q | NC<8> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NC<8>.SI | NC<8> | 0 | 11 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NC<8>.D1 | 2066 | ? | 0 | 4096 | NC<8> | NULL | NULL | NC<8>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | A_10_IBUF +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NC<8>.D2 | 2067 | ? | 0 | 4096 | NC<8> | NULL | NULL | NC<8>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 8 | IV_TRUE | A_2_IBUF | IV_TRUE | A_3_IBUF | IV_TRUE | A_4_IBUF | IV_TRUE | A_5_IBUF | IV_TRUE | A_6_IBUF | IV_TRUE | A_7_IBUF | IV_TRUE | A_8_IBUF | IV_TRUE | A_9_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NC<8>.CE | 2068 | ? | 0 | 4096 | NC<8> | NULL | NULL | NC<8>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NC<8>.REG | NC<8> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NC<8>.D | 2065 | ? | 0 | 0 | NC<8> | NULL | NULL | NC<8>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NC<8>.CE | 2068 | ? | 0 | 4096 | NC<8> | NULL | NULL | NC<8>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NC<8>.Q | 2069 | ? | 0 | 0 | NC<8> | NULL | NULL | NC<8>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_11_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<11> | 1994 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_11_IBUF | 1938 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_11_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<0> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_11_IBUF | 1938 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_11_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<0> | 1939 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<0>.Q | NR<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<0>.SI | NR<0> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_11_IBUF | 1938 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_11_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<0>.D1 | 2071 | ? | 0 | 4096 | NR<0> | NULL | NULL | NR<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<0>.D2 | 2072 | ? | 0 | 4096 | NR<0> | NULL | NULL | NR<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_11_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<0>.CE | 2073 | ? | 0 | 4096 | NR<0> | NULL | NULL | NR<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<0>.REG | NR<0> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<0>.D | 2070 | ? | 0 | 0 | NR<0> | NULL | NULL | NR<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<0>.CE | 2073 | ? | 0 | 4096 | NR<0> | NULL | NULL | NR<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<0>.Q | 2074 | ? | 0 | 0 | NR<0> | NULL | NULL | NR<0>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_21_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<21> | 1995 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_21_IBUF | 1940 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<10> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 1940 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<10> | 1941 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<10>.Q | NR<10> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<10>.SI | NR<10> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 1940 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<10>.D1 | 2076 | ? | 0 | 4096 | NR<10> | NULL | NULL | NR<10>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<10>.D2 | 2077 | ? | 0 | 4096 | NR<10> | NULL | NULL | NR<10>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_21_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<10>.CE | 2078 | ? | 0 | 4096 | NR<10> | NULL | NULL | NR<10>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<10>.REG | NR<10> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<10>.D | 2075 | ? | 0 | 0 | NR<10> | NULL | NULL | NR<10>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<10>.CE | 2078 | ? | 0 | 4096 | NR<10> | NULL | NULL | NR<10>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<10>.Q | 2079 | ? | 0 | 0 | NR<10> | NULL | NULL | NR<10>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_22_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<22> | 1996 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_22_IBUF | 1942 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<11> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 1942 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<11> | 1943 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<11>.Q | NR<11> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<11>.SI | NR<11> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 1942 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<11>.D1 | 2081 | ? | 0 | 4096 | NR<11> | NULL | NULL | NR<11>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<11>.D2 | 2082 | ? | 0 | 4096 | NR<11> | NULL | NULL | NR<11>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_22_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<11>.CE | 2083 | ? | 0 | 4096 | NR<11> | NULL | NULL | NR<11>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<11>.REG | NR<11> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<11>.D | 2080 | ? | 0 | 0 | NR<11> | NULL | NULL | NR<11>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<11>.CE | 2083 | ? | 0 | 4096 | NR<11> | NULL | NULL | NR<11>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<11>.Q | 2084 | ? | 0 | 0 | NR<11> | NULL | NULL | NR<11>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_23_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<23> | 1997 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_23_IBUF | 1944 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<12> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 1944 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<12> | 1945 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<12>.Q | NR<12> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<12>.SI | NR<12> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 1944 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<12>.D1 | 2086 | ? | 0 | 4096 | NR<12> | NULL | NULL | NR<12>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<12>.D2 | 2087 | ? | 0 | 4096 | NR<12> | NULL | NULL | NR<12>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_23_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<12>.CE | 2088 | ? | 0 | 4096 | NR<12> | NULL | NULL | NR<12>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<12>.REG | NR<12> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<12>.D | 2085 | ? | 0 | 0 | NR<12> | NULL | NULL | NR<12>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<12>.CE | 2088 | ? | 0 | 4096 | NR<12> | NULL | NULL | NR<12>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<12>.Q | 2089 | ? | 0 | 0 | NR<12> | NULL | NULL | NR<12>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_12_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<12> | 1998 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_12_IBUF | 1946 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<1> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_12_IBUF | 1946 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<1> | 1947 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<1>.Q | NR<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<1>.SI | NR<1> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_12_IBUF | 1946 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<1>.D1 | 2091 | ? | 0 | 4096 | NR<1> | NULL | NULL | NR<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<1>.D2 | 2092 | ? | 0 | 4096 | NR<1> | NULL | NULL | NR<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_12_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<1>.CE | 2093 | ? | 0 | 4096 | NR<1> | NULL | NULL | NR<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<1>.REG | NR<1> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<1>.D | 2090 | ? | 0 | 0 | NR<1> | NULL | NULL | NR<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<1>.CE | 2093 | ? | 0 | 4096 | NR<1> | NULL | NULL | NR<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<1>.Q | 2094 | ? | 0 | 0 | NR<1> | NULL | NULL | NR<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<2> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<2> | 1948 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<2>.Q | NR<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<2>.SI | NR<2> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<2>.D1 | 2096 | ? | 0 | 4096 | NR<2> | NULL | NULL | NR<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<2>.D2 | 2097 | ? | 0 | 4096 | NR<2> | NULL | NULL | NR<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_13_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<2>.CE | 2098 | ? | 0 | 4096 | NR<2> | NULL | NULL | NR<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<2>.REG | NR<2> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<2>.D | 2095 | ? | 0 | 0 | NR<2> | NULL | NULL | NR<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<2>.CE | 2098 | ? | 0 | 4096 | NR<2> | NULL | NULL | NR<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<2>.Q | 2099 | ? | 0 | 0 | NR<2> | NULL | NULL | NR<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_14_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<14> | 1999 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<3> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<3> | 1950 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<3>.Q | NR<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<3>.SI | NR<3> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<3>.D1 | 2101 | ? | 0 | 4096 | NR<3> | NULL | NULL | NR<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<3>.D2 | 2102 | ? | 0 | 4096 | NR<3> | NULL | NULL | NR<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_14_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<3>.CE | 2103 | ? | 0 | 4096 | NR<3> | NULL | NULL | NR<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<3>.REG | NR<3> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<3>.D | 2100 | ? | 0 | 0 | NR<3> | NULL | NULL | NR<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<3>.CE | 2103 | ? | 0 | 4096 | NR<3> | NULL | NULL | NR<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<3>.Q | 2104 | ? | 0 | 0 | NR<3> | NULL | NULL | NR<3>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_15_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<15> | 2000 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<4> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<4> | 1952 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<4>.Q | NR<4> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<4>.SI | NR<4> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<4>.D1 | 2106 | ? | 0 | 4096 | NR<4> | NULL | NULL | NR<4>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<4>.D2 | 2107 | ? | 0 | 4096 | NR<4> | NULL | NULL | NR<4>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_15_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<4>.CE | 2108 | ? | 0 | 4096 | NR<4> | NULL | NULL | NR<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<4>.REG | NR<4> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<4>.D | 2105 | ? | 0 | 0 | NR<4> | NULL | NULL | NR<4>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<4>.CE | 2108 | ? | 0 | 4096 | NR<4> | NULL | NULL | NR<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<4>.Q | 2109 | ? | 0 | 0 | NR<4> | NULL | NULL | NR<4>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_16_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<16> | 2001 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<5> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<5> | 1954 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<5>.Q | NR<5> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<5>.SI | NR<5> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<5>.D1 | 2111 | ? | 0 | 4096 | NR<5> | NULL | NULL | NR<5>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<5>.D2 | 2112 | ? | 0 | 4096 | NR<5> | NULL | NULL | NR<5>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_16_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<5>.CE | 2113 | ? | 0 | 4096 | NR<5> | NULL | NULL | NR<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<5>.REG | NR<5> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<5>.D | 2110 | ? | 0 | 0 | NR<5> | NULL | NULL | NR<5>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<5>.CE | 2113 | ? | 0 | 4096 | NR<5> | NULL | NULL | NR<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<5>.Q | 2114 | ? | 0 | 0 | NR<5> | NULL | NULL | NR<5>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<6> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<6> | 1955 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<6>.Q | NR<6> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<6>.SI | NR<6> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<6>.D1 | 2116 | ? | 0 | 4096 | NR<6> | NULL | NULL | NR<6>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<6>.D2 | 2117 | ? | 0 | 4096 | NR<6> | NULL | NULL | NR<6>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_17_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<6>.CE | 2118 | ? | 0 | 4096 | NR<6> | NULL | NULL | NR<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<6>.REG | NR<6> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<6>.D | 2115 | ? | 0 | 0 | NR<6> | NULL | NULL | NR<6>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<6>.CE | 2118 | ? | 0 | 4096 | NR<6> | NULL | NULL | NR<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<6>.Q | 2119 | ? | 0 | 0 | NR<6> | NULL | NULL | NR<6>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_18_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<18> | 2002 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<7> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<7> | 1957 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<7>.Q | NR<7> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<7>.SI | NR<7> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<7>.D1 | 2121 | ? | 0 | 4096 | NR<7> | NULL | NULL | NR<7>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<7>.D2 | 2122 | ? | 0 | 4096 | NR<7> | NULL | NULL | NR<7>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_18_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<7>.CE | 2123 | ? | 0 | 4096 | NR<7> | NULL | NULL | NR<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<7>.REG | NR<7> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<7>.D | 2120 | ? | 0 | 0 | NR<7> | NULL | NULL | NR<7>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<7>.CE | 2123 | ? | 0 | 4096 | NR<7> | NULL | NULL | NR<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<7>.Q | 2124 | ? | 0 | 0 | NR<7> | NULL | NULL | NR<7>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_19_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<19> | 2003 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<8> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<8> | 1959 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<8>.Q | NR<8> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<8>.SI | NR<8> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<8>.D1 | 2126 | ? | 0 | 4096 | NR<8> | NULL | NULL | NR<8>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<8>.D2 | 2127 | ? | 0 | 4096 | NR<8> | NULL | NULL | NR<8>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_19_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<8>.CE | 2128 | ? | 0 | 4096 | NR<8> | NULL | NULL | NR<8>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<8>.REG | NR<8> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<8>.D | 2125 | ? | 0 | 0 | NR<8> | NULL | NULL | NR<8>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<8>.CE | 2128 | ? | 0 | 4096 | NR<8> | NULL | NULL | NR<8>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<8>.Q | 2129 | ? | 0 | 0 | NR<8> | NULL | NULL | NR<8>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | A_20_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<20> | 2004 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_20_IBUF | 1960 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NR<9> | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 1960 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NR<9> | 1961 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<9>.Q | NR<9> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NR<9>.SI | NR<9> | 0 | 3 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 1960 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NR<9>.D1 | 2131 | ? | 0 | 4096 | NR<9> | NULL | NULL | NR<9>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NR<9>.D2 | 2132 | ? | 0 | 4096 | NR<9> | NULL | NULL | NR<9>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | A_20_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | NR<9>.CE | 2133 | ? | 0 | 4096 | NR<9> | NULL | NULL | NR<9>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF + +SRFF_INSTANCE | NR<9>.REG | NR<9> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NR<9>.D | 2130 | ? | 0 | 0 | NR<9> | NULL | NULL | NR<9>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | NR<9>.CE | 2133 | ? | 0 | 4096 | NR<9> | NULL | NULL | NR<9>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NR<9>.Q | 2134 | ? | 0 | 0 | NR<9> | NULL | NULL | NR<9>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | FC_2_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | FC<2> | 2005 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | FC_2_IBUF | 1962 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_2_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | NA | STERMINATOR_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NA | 1965 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NA.Q | NA | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | NA | 1965 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NA.Q | NA | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | NA.SI | NA | 0 | 3 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_0_IBUF | 1963 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CMD_1_IBUF | 1964 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CMD_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NA | 1965 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NA.Q | NA | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | NA.D1 | 2136 | ? | 0 | 4096 | NA | NULL | NULL | NA.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | NA.D2 | 2137 | ? | 0 | 4096 | NA | NULL | NULL | NA.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | CMD_0_IBUF | IV_FALSE | CMD_1_IBUF +SPPTERM | 2 | IV_FALSE | CMD_1_IBUF | IV_TRUE | NA + +SRFF_INSTANCE | NA.REG | NA | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | NA.D | 2135 | ? | 0 | 0 | NA | NULL | NULL | NA.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +NODE | FCLKIO_0 | 1916 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLK_IBUF | 3 | 5 | II_FCLK +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | NA.Q | 2138 | ? | 0 | 0 | NA | NULL | NULL | NA.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | nAS_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | nAS | 2008 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | nAS_IBUF | 1966 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | nAS_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | CLKdat_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | CLKdat | 2009 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | CLKdat_IBUF | 1967 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLKdat_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_30_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<30> | 2010 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_30_IBUF | 1968 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_30_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_29_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<29> | 2011 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_29_IBUF | 1969 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_29_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_28_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<28> | 2012 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_28_IBUF | 1970 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_28_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | A_31_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | A<31> | 2013 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | A_31_IBUF | 1971 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_31_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | Inv+OptxMapped | nFPUCS_OBUF | STERMINATOR_COPY_0_COPY_0 | 2155872512 | 12 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_1_IBUF | 1911 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_0_IBUF | 1912 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_2_IBUF | 1962 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | nAS_IBUF | 1966 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | nAS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CLKdat_IBUF | 1967 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLKdat_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | nFPUCS_OBUF | 1972 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | nFPUCS_OBUF.Q | nFPUCS_OBUF | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | nFPUCS_OBUF.SI | nFPUCS_OBUF | 0 | 12 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_1_IBUF | 1911 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_0_IBUF | 1912 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_2_IBUF | 1962 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | nAS_IBUF | 1966 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | nAS_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | CLKdat_IBUF | 1967 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | CLKdat_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | nFPUCS_OBUF.D1 | 2140 | ? | 0 | 4096 | nFPUCS_OBUF | NULL | NULL | nFPUCS_OBUF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | nFPUCS_OBUF.D2 | 2141 | ? | 0 | 4096 | nFPUCS_OBUF | NULL | NULL | nFPUCS_OBUF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 11 | IV_TRUE | FC_1_IBUF | IV_TRUE | FC_0_IBUF | IV_TRUE | A_17_IBUF | IV_TRUE | A_13_IBUF | IV_FALSE | A_14_IBUF | IV_FALSE | A_15_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_18_IBUF | IV_FALSE | A_19_IBUF | IV_TRUE | FC_2_IBUF | IV_FALSE | nAS_IBUF +SPPTERM | 11 | IV_TRUE | FC_1_IBUF | IV_TRUE | FC_0_IBUF | IV_TRUE | A_17_IBUF | IV_TRUE | A_13_IBUF | IV_FALSE | A_14_IBUF | IV_FALSE | A_15_IBUF | IV_FALSE | A_16_IBUF | IV_FALSE | A_18_IBUF | IV_FALSE | A_19_IBUF | IV_TRUE | FC_2_IBUF | IV_FALSE | CLKdat_IBUF + +SRFF_INSTANCE | nFPUCS_OBUF.REG | nFPUCS_OBUF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | nFPUCS_OBUF.D | 2139 | ? | 0 | 0 | nFPUCS_OBUF | NULL | NULL | nFPUCS_OBUF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | nFPUCS_OBUF.Q | 2142 | ? | 0 | 0 | nFPUCS_OBUF | NULL | NULL | nFPUCS_OBUF.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | STERM_IBUF | STERMINATOR_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | STERM | 2014 | PI | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | Inv+OptxMapped | nSTERM_OBUF | STERMINATOR_COPY_0_COPY_0 | 2155872512 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$BIN_STEP$409.UIM | 1977 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | $OpTx$BIN_STEP$409.Q | $OpTx$BIN_STEP$409 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_0_IBUF | 1912 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NA | 1965 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NA.Q | NA | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | nSTERM_OBUF | 1974 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | nSTERM_OBUF.Q | nSTERM_OBUF | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | nSTERM_OBUF.SI | nSTERM_OBUF | 0 | 4 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$BIN_STEP$409.UIM | 1977 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | $OpTx$BIN_STEP$409.Q | $OpTx$BIN_STEP$409 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_0_IBUF | 1912 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NA | 1965 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NA.Q | NA | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | nSTERM_OBUF.D1 | 2144 | ? | 0 | 4096 | nSTERM_OBUF | NULL | NULL | nSTERM_OBUF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | nSTERM_OBUF.D2 | 2145 | ? | 0 | 4096 | nSTERM_OBUF | NULL | NULL | nSTERM_OBUF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | STERM_IBUF | IV_FALSE | $OpTx$BIN_STEP$409.UIM +SPPTERM | 3 | IV_FALSE | FC_0_IBUF | IV_TRUE | NA | IV_FALSE | $OpTx$BIN_STEP$409.UIM + +SRFF_INSTANCE | nSTERM_OBUF.REG | nSTERM_OBUF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | nSTERM_OBUF.D | 2143 | ? | 0 | 0 | nSTERM_OBUF | NULL | NULL | nSTERM_OBUF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | nSTERM_OBUF.Q | 2146 | ? | 0 | 0 | nSTERM_OBUF | NULL | NULL | nSTERM_OBUF.REG | 0 | 8 | SRFF_Q + +OUTPUT_INSTANCE | 0 | nFPUCS | STERMINATOR_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | nFPUCS_OBUF | 1972 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | nFPUCS_OBUF.Q | nFPUCS_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | nFPUCS | 1975 | PO | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | nFPUCS | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | nSTERM | STERMINATOR_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | nSTERM_OBUF | 1974 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | nSTERM_OBUF.Q | nSTERM_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | nSTERM | 1976 | PO | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | nSTERM | 0 | 6 | OI_OUT + +MACROCELL_INSTANCE | SoftPfbk | $OpTx$BIN_STEP$409 | STERMINATOR_COPY_0_COPY_0 | 2181038080 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_31_IBUF | 1971 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_31_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_2_IBUF | 1962 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<4> | 1952 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<4>.Q | NR<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<8> | 1959 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<8>.Q | NR<8> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP10_.EXP | 2165 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP10_.EXP | EXP10_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP11_.EXP | 2166 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP11_.EXP | EXP11_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | $OpTx$BIN_STEP$409.UIM | 1977 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | $OpTx$BIN_STEP$409.Q | $OpTx$BIN_STEP$409 | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | $OpTx$BIN_STEP$409.SI | $OpTx$BIN_STEP$409 | 0 | 9 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_31_IBUF | 1971 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_31_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | FC_2_IBUF | 1962 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | FC_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_15_IBUF | 1951 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_15_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<4> | 1952 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<4>.Q | NR<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<8> | 1959 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<8>.Q | NR<8> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP10_.EXP | 2165 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP10_.EXP | EXP10_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP11_.EXP | 2166 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP11_.EXP | EXP11_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | $OpTx$BIN_STEP$409.D1 | 2148 | ? | 0 | 4096 | $OpTx$BIN_STEP$409 | NULL | NULL | $OpTx$BIN_STEP$409.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | $OpTx$BIN_STEP$409.D2 | 2149 | ? | 0 | 4096 | $OpTx$BIN_STEP$409 | NULL | NULL | $OpTx$BIN_STEP$409.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | EXP10_.EXP +SPPTERM | 1 | IV_TRUE | EXP11_.EXP +SPPTERM | 2 | IV_FALSE | FC_2_IBUF | IV_FALSE | STERM_IBUF +SPPTERM | 2 | IV_TRUE | A_31_IBUF | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_15_IBUF | IV_FALSE | NR<4> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_15_IBUF | IV_TRUE | NR<4> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_19_IBUF | IV_TRUE | NR<8> | IV_FALSE | STERM_IBUF + +SRFF_INSTANCE | $OpTx$BIN_STEP$409.REG | $OpTx$BIN_STEP$409 | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | $OpTx$BIN_STEP$409.D | 2147 | ? | 0 | 0 | $OpTx$BIN_STEP$409 | NULL | NULL | $OpTx$BIN_STEP$409.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | $OpTx$BIN_STEP$409.Q | 2150 | ? | 0 | 0 | $OpTx$BIN_STEP$409 | NULL | NULL | $OpTx$BIN_STEP$409.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | NULL | EXP6_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<6> | 1955 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<6>.Q | NR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<8> | 1937 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<8>.Q | NC<8> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP6_.EXP | 2161 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP6_.SI | EXP6_ | 0 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<6> | 1955 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<6>.Q | NR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<8> | 1937 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<8>.Q | NC<8> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP6_.EXP | 2151 | ? | 0 | 0 | EXP6_ | NULL | NULL | EXP6_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 3 | IV_FALSE | A_17_IBUF | IV_TRUE | NR<6> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_10_IBUF | IV_FALSE | NC<8> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP7_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<5> | 1931 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<5>.Q | NC<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_11_IBUF | 1938 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_11_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<0> | 1939 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<0>.Q | NR<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<7> | 1957 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<7>.Q | NR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP6_.EXP | 2161 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP7_.EXP | 2162 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP7_.EXP | EXP7_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP7_.SI | EXP7_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_7_IBUF | 1930 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_7_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<5> | 1931 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<5>.Q | NC<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_11_IBUF | 1938 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_11_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<0> | 1939 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<0>.Q | NR<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<7> | 1957 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<7>.Q | NR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP6_.EXP | 2161 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP7_.EXP | 2152 | ? | 0 | 0 | EXP7_ | NULL | NULL | EXP7_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP6_.EXP +SPPTERM | 3 | IV_TRUE | A_7_IBUF | IV_FALSE | NC<5> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_7_IBUF | IV_TRUE | NC<5> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_11_IBUF | IV_FALSE | NR<0> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_11_IBUF | IV_TRUE | NR<0> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_18_IBUF | IV_FALSE | NR<7> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP8_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<2> | 1948 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<2>.Q | NR<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<0> | 1921 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<0>.Q | NC<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<5> | 1954 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<5>.Q | NR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP7_.EXP | 2162 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP7_.EXP | EXP7_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP8_.EXP | 2163 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP8_.EXP | EXP8_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP8_.SI | EXP8_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_13_IBUF | 1914 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_13_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<2> | 1948 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<2>.Q | NR<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_2_IBUF | 1920 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<0> | 1921 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<0>.Q | NC<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<5> | 1954 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<5>.Q | NR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP7_.EXP | 2162 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP7_.EXP | EXP7_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP8_.EXP | 2153 | ? | 0 | 0 | EXP8_ | NULL | NULL | EXP8_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP7_.EXP +SPPTERM | 3 | IV_TRUE | A_13_IBUF | IV_FALSE | NR<2> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_13_IBUF | IV_TRUE | NR<2> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_2_IBUF | IV_FALSE | NC<0> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_2_IBUF | IV_TRUE | NC<0> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_16_IBUF | IV_FALSE | NR<5> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP9_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NB<0> | 1917 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<0>.Q | NB<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 1940 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<10> | 1941 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<10>.Q | NR<10> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 1944 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<12> | 1945 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<12>.Q | NR<12> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP8_.EXP | 2163 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP8_.EXP | EXP8_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP9_.EXP | 2164 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP9_.EXP | EXP9_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP9_.SI | EXP9_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NB<0> | 1917 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<0>.Q | NB<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_21_IBUF | 1940 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_21_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<10> | 1941 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<10>.Q | NR<10> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_23_IBUF | 1944 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_23_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<12> | 1945 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<12>.Q | NR<12> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP8_.EXP | 2163 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP8_.EXP | EXP8_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP9_.EXP | 2154 | ? | 0 | 0 | EXP9_ | NULL | NULL | EXP9_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP8_.EXP +SPPTERM | 3 | IV_TRUE | A_24_IBUF | IV_FALSE | NB<0> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_21_IBUF | IV_FALSE | NR<10> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_21_IBUF | IV_TRUE | NR<10> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_23_IBUF | IV_FALSE | NR<12> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_23_IBUF | IV_TRUE | NR<12> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP10_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<3> | 1927 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<3>.Q | NC<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<7> | 1935 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<7>.Q | NC<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<8> | 1959 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<8>.Q | NR<8> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP9_.EXP | 2164 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP9_.EXP | EXP9_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP10_.EXP | 2165 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP10_.EXP | EXP10_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP10_.SI | EXP10_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_5_IBUF | 1926 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_5_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<3> | 1927 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<3>.Q | NC<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_9_IBUF | 1934 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_9_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<7> | 1935 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<7>.Q | NC<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_19_IBUF | 1958 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_19_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<8> | 1959 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<8>.Q | NR<8> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP9_.EXP | 2164 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP9_.EXP | EXP9_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP10_.EXP | 2155 | ? | 0 | 0 | EXP10_ | NULL | NULL | EXP10_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP9_.EXP +SPPTERM | 3 | IV_TRUE | A_5_IBUF | IV_FALSE | NC<3> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_5_IBUF | IV_TRUE | NC<3> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_9_IBUF | IV_FALSE | NC<7> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_9_IBUF | IV_TRUE | NC<7> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_19_IBUF | IV_FALSE | NR<8> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP11_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NB<0> | 1917 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<0>.Q | NB<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<2> | 1925 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<2>.Q | NC<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<6> | 1933 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<6>.Q | NC<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP12_.EXP | 2167 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP12_.EXP | EXP12_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP11_.EXP | 2166 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP11_.EXP | EXP11_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP11_.SI | EXP11_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_24_IBUF | 1915 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_24_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NB<0> | 1917 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<0>.Q | NB<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_4_IBUF | 1924 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_4_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<2> | 1925 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<2>.Q | NC<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_8_IBUF | 1932 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_8_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<6> | 1933 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<6>.Q | NC<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP12_.EXP | 2167 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP12_.EXP | EXP12_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP11_.EXP | 2156 | ? | 0 | 0 | EXP11_ | NULL | NULL | EXP11_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP12_.EXP +SPPTERM | 3 | IV_FALSE | A_24_IBUF | IV_TRUE | NB<0> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_4_IBUF | IV_FALSE | NC<2> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_4_IBUF | IV_TRUE | NC<2> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_8_IBUF | IV_FALSE | NC<6> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_8_IBUF | IV_TRUE | NC<6> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP12_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_25_IBUF | 1918 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_25_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NB<1> | 1919 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<1>.Q | NB<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<4> | 1929 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<4>.Q | NC<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<5> | 1954 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<5>.Q | NR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP13_.EXP | 2168 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP13_.EXP | EXP13_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP12_.EXP | 2167 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP12_.EXP | EXP12_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP12_.SI | EXP12_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_25_IBUF | 1918 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_25_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NB<1> | 1919 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NB<1>.Q | NB<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_6_IBUF | 1928 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_6_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<4> | 1929 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<4>.Q | NC<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_16_IBUF | 1953 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_16_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<5> | 1954 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<5>.Q | NR<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP13_.EXP | 2168 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP13_.EXP | EXP13_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP12_.EXP | 2157 | ? | 0 | 0 | EXP12_ | NULL | NULL | EXP12_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP13_.EXP +SPPTERM | 3 | IV_TRUE | A_25_IBUF | IV_FALSE | NB<1> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_25_IBUF | IV_TRUE | NB<1> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_6_IBUF | IV_FALSE | NC<4> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_6_IBUF | IV_TRUE | NC<4> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_16_IBUF | IV_TRUE | NR<5> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP13_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<1> | 1923 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<1>.Q | NC<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<7> | 1957 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<7>.Q | NR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_30_IBUF | 1968 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_30_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_29_IBUF | 1969 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_29_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_28_IBUF | 1970 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_28_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP14_.EXP | 2169 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP13_.EXP | 2168 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP13_.EXP | EXP13_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP13_.SI | EXP13_ | 0 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_3_IBUF | 1922 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<1> | 1923 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<1>.Q | NC<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_18_IBUF | 1956 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_18_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<7> | 1957 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<7>.Q | NR<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_30_IBUF | 1968 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_30_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_29_IBUF | 1969 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_29_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_28_IBUF | 1970 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_28_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP14_.EXP | 2169 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP13_.EXP | 2158 | ? | 0 | 0 | EXP13_ | NULL | NULL | EXP13_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP14_.EXP +SPPTERM | 3 | IV_TRUE | A_3_IBUF | IV_FALSE | NC<1> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_3_IBUF | IV_TRUE | NC<1> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_18_IBUF | IV_TRUE | NR<7> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_30_IBUF | IV_TRUE | A_29_IBUF | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_30_IBUF | IV_TRUE | A_28_IBUF | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP14_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<8> | 1937 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<8>.Q | NC<8> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<3> | 1950 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<3>.Q | NR<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 1960 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<9> | 1961 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<9>.Q | NR<9> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP15_.EXP | 2170 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP14_.EXP | 2169 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP14_.EXP | EXP14_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP14_.SI | EXP14_ | 0 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_10_IBUF | 1936 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_10_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NC<8> | 1937 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NC<8>.Q | NC<8> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_14_IBUF | 1949 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_14_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<3> | 1950 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<3>.Q | NR<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_20_IBUF | 1960 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_20_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<9> | 1961 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<9>.Q | NR<9> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP15_.EXP | 2170 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP14_.EXP | 2159 | ? | 0 | 0 | EXP14_ | NULL | NULL | EXP14_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 1 | IV_TRUE | EXP15_.EXP +SPPTERM | 3 | IV_FALSE | A_10_IBUF | IV_TRUE | NC<8> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_14_IBUF | IV_FALSE | NR<3> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_14_IBUF | IV_TRUE | NR<3> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_20_IBUF | IV_FALSE | NR<9> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_20_IBUF | IV_TRUE | NR<9> | IV_FALSE | STERM_IBUF + +MACROCELL_INSTANCE | NULL | EXP15_ | STERMINATOR_COPY_0_COPY_0 | 2147483648 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<6> | 1955 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<6>.Q | NR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 1942 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<11> | 1943 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<11>.Q | NR<11> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_12_IBUF | 1946 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<1> | 1947 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<1>.Q | NR<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP15_.EXP | 2170 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | EXP15_.EXP | EXP15_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP15_.SI | EXP15_ | 0 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_17_IBUF | 1913 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_17_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<6> | 1955 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<6>.Q | NR<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | STERM_IBUF | 1973 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | STERM_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_22_IBUF | 1942 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_22_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<11> | 1943 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<11>.Q | NR<11> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | A_12_IBUF | 1946 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NULL | A_12_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | NR<1> | 1947 | ? | 0 | 0 | STERMINATOR_COPY_0_COPY_0 | NULL | NR<1>.Q | NR<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP15_.EXP | 2160 | ? | 0 | 0 | EXP15_ | NULL | NULL | EXP15_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 3 | IV_TRUE | A_17_IBUF | IV_FALSE | NR<6> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_22_IBUF | IV_FALSE | NR<11> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_22_IBUF | IV_TRUE | NR<11> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_TRUE | A_12_IBUF | IV_FALSE | NR<1> | IV_FALSE | STERM_IBUF +SPPTERM | 3 | IV_FALSE | A_12_IBUF | IV_TRUE | NR<1> | IV_FALSE | STERM_IBUF + +FB_INSTANCE | FOOBAR1_ | STERMINATOR_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 5 | NULL | 0 | A_8_IBUF | 1 | NULL | 0 | 9 | 49152 +FBPIN | 6 | NULL | 0 | A_25_IBUF | 1 | NULL | 0 | 10 | 49152 +FBPIN | 8 | EXP6_ | 1 | A_9_IBUF | 1 | NULL | 0 | 11 | 49152 +FBPIN | 9 | EXP7_ | 1 | CLK_IBUF | 1 | NULL | 0 | 15 | 57344 +FBPIN | 10 | EXP8_ | 1 | NULL | 0 | NULL | 0 | 18 | 49152 +FBPIN | 11 | EXP9_ | 1 | CMD_1_IBUF | 1 | NULL | 0 | 16 | 57344 +FBPIN | 12 | EXP10_ | 1 | NULL | 0 | NULL | 0 | 23 | 49152 +FBPIN | 13 | $OpTx$BIN_STEP$409 | 1 | NULL | 0 | NULL | 0 +FBPIN | 14 | EXP11_ | 1 | NULL | 0 | NULL | 0 | 17 | 57344 +FBPIN | 15 | EXP12_ | 1 | NULL | 0 | NULL | 0 | 19 | 49152 +FBPIN | 16 | EXP13_ | 1 | NULL | 0 | NULL | 0 +FBPIN | 17 | EXP14_ | 1 | A_4_IBUF | 1 | NULL | 0 | 20 | 49152 +FBPIN | 18 | EXP15_ | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR2_ | STERMINATOR_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 2 | nSTERM_OBUF | 1 | NULL | 0 | nSTERM | 1 | 60 | 49152 +FBPIN | 3 | NULL | 0 | A_17_IBUF | 1 | NULL | 0 | 58 | 49152 +FBPIN | 4 | NULL | 0 | STERM_IBUF | 1 | NULL | 0 | 59 | 49152 +FBPIN | 5 | NULL | 0 | A_29_IBUF | 1 | NULL | 0 | 61 | 49152 +FBPIN | 6 | NULL | 0 | A_30_IBUF | 1 | NULL | 0 | 62 | 49152 +FBPIN | 8 | NULL | 0 | A_5_IBUF | 1 | NULL | 0 | 63 | 49152 +FBPIN | 9 | NULL | 0 | A_12_IBUF | 1 | NULL | 0 | 64 | 51200 +FBPIN | 10 | NULL | 0 | A_31_IBUF | 1 | NULL | 0 | 1 | 49152 +FBPIN | 11 | NR<9> | 1 | A_11_IBUF | 1 | NULL | 0 | 2 | 53248 +FBPIN | 12 | NR<1> | 1 | A_15_IBUF | 1 | NULL | 0 | 4 | 49152 +FBPIN | 13 | NR<12> | 1 | NULL | 0 | NULL | 0 +FBPIN | 14 | NR<11> | 1 | CLKdat_IBUF | 1 | NULL | 0 | 5 | 53248 +FBPIN | 15 | NR<10> | 1 | nAS_IBUF | 1 | NULL | 0 | 6 | 49152 +FBPIN | 16 | NR<0> | 1 | NULL | 0 | NULL | 0 +FBPIN | 17 | NB<1> | 1 | A_7_IBUF | 1 | NULL | 0 | 7 | 49152 +FBPIN | 18 | NB<0> | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR3_ | STERMINATOR_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | NR<8> | 1 | NULL | 0 | NULL | 0 +FBPIN | 2 | nFPUCS_OBUF | 1 | NULL | 0 | nFPUCS | 1 | 22 | 49152 +FBPIN | 3 | NR<7> | 1 | FC_0_IBUF | 1 | NULL | 0 | 31 | 49152 +FBPIN | 4 | NR<6> | 1 | NULL | 0 | NULL | 0 | 32 | 49152 +FBPIN | 5 | NR<5> | 1 | NULL | 0 | NULL | 0 | 24 | 49152 +FBPIN | 6 | NR<4> | 1 | A_16_IBUF | 1 | NULL | 0 | 34 | 49152 +FBPIN | 7 | NR<3> | 1 | NULL | 0 | NULL | 0 +FBPIN | 8 | NR<2> | 1 | NULL | 0 | NULL | 0 | 25 | 49152 +FBPIN | 9 | NC<0> | 1 | NULL | 0 | NULL | 0 | 27 | 49152 +FBPIN | 10 | NA | 1 | CMD_0_IBUF | 1 | NULL | 0 | 39 | 49152 +FBPIN | 11 | NC<8> | 1 | NULL | 0 | NULL | 0 | 33 | 49152 +FBPIN | 12 | NC<7> | 1 | A_2_IBUF | 1 | NULL | 0 | 40 | 49152 +FBPIN | 13 | NC<6> | 1 | NULL | 0 | NULL | 0 +FBPIN | 14 | NC<5> | 1 | A_22_IBUF | 1 | NULL | 0 | 35 | 49152 +FBPIN | 15 | NC<4> | 1 | A_20_IBUF | 1 | NULL | 0 | 36 | 49152 +FBPIN | 16 | NC<3> | 1 | A_19_IBUF | 1 | NULL | 0 | 42 | 49152 +FBPIN | 17 | NC<2> | 1 | NULL | 0 | NULL | 0 | 38 | 49152 +FBPIN | 18 | NC<1> | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR4_ | STERMINATOR_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 2 | NULL | 0 | A_3_IBUF | 1 | NULL | 0 | 43 | 49152 +FBPIN | 3 | NULL | 0 | A_28_IBUF | 1 | NULL | 0 | 46 | 49152 +FBPIN | 4 | NULL | 0 | A_6_IBUF | 1 | NULL | 0 | 47 | 49152 +FBPIN | 5 | NULL | 0 | A_13_IBUF | 1 | NULL | 0 | 44 | 49152 +FBPIN | 6 | NULL | 0 | A_18_IBUF | 1 | NULL | 0 | 49 | 49152 +FBPIN | 8 | NULL | 0 | FC_1_IBUF | 1 | NULL | 0 | 45 | 49152 +FBPIN | 10 | NULL | 0 | A_14_IBUF | 1 | NULL | 0 | 51 | 49152 +FBPIN | 11 | NULL | 0 | A_23_IBUF | 1 | NULL | 0 | 48 | 49152 +FBPIN | 12 | NULL | 0 | A_24_IBUF | 1 | NULL | 0 | 52 | 49152 +FBPIN | 14 | NULL | 0 | A_21_IBUF | 1 | NULL | 0 | 50 | 49152 +FBPIN | 15 | NULL | 0 | FC_2_IBUF | 1 | NULL | 0 | 56 | 49152 +FBPIN | 17 | NULL | 0 | A_10_IBUF | 1 | NULL | 0 | 57 | 49152 + +FB_INSTANCE | INPUTPINS_FOOBAR5_ | STERMINATOR_COPY_0_COPY_0 | 0 | 0 | 0 + +BUSINFO | A<31:2> | 30 | 0 | 0 | A<10> | 21 | A<11> | 20 | A<12> | 19 | A<13> | 18 | A<14> | 17 | A<15> | 16 | A<16> | 15 | A<17> | 14 | A<18> | 13 | A<19> | 12 | A<20> | 11 | A<21> | 10 | A<22> | 9 | A<23> | 8 | A<24> | 7 | A<25> | 6 | A<28> | 3 | A<29> | 2 | A<2> | 29 | A<30> | 1 | A<31> | 0 | A<3> | 28 | A<4> | 27 | A<5> | 26 | A<6> | 25 | A<7> | 24 | A<8> | 23 | A<9> | 22 +BUSINFO | CMD<1:0> | 2 | 0 | 0 | CMD<0> | 1 | CMD<1> | 0 +BUSINFO | FC<2:0> | 3 | 0 | 0 | FC<0> | 2 | FC<1> | 1 | FC<2> | 0 + +FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | NR<8> | NULL | 1 | A<10> | 57 | 2 | A<25> | 10 | 3 | NR<6> | NULL | 4 | NR<5> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 5 | A<23> | 48 | 6 | NR<3> | NULL | 7 | A<2> | 40 | 8 | A<29> | 61 | 9 | A<28> | 46 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 10 | A<30> | 62 | 11 | A<24> | 52 | 12 | A<5> | 63 | 13 | A<14> | 51 | 14 | NR<10> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 15 | NR<0> | NULL | 16 | A<31> | 1 | 17 | NC<1> | NULL | 18 | STERM | 59 | 19 | NR<11> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 20 | A<18> | 49 | 21 | NR<9> | NULL | 22 | NR<4> | NULL | 23 | NC<3> | NULL | 24 | A<20> | 36 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 25 | NC<5> | NULL | 26 | NC<7> | NULL | 27 | FC<2> | 56 | 28 | NC<0> | NULL | 29 | A<8> | 9 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 30 | A<21> | 50 | 31 | NR<2> | NULL | 32 | A<4> | 20 | 33 | A<16> | 34 | 34 | NC<6> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 35 | A<3> | 43 | 36 | A<13> | 44 | 37 | NC<8> | NULL | 38 | NB<1> | NULL | 39 | A<19> | 42 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 40 | A<9> | 11 | 41 | NR<12> | NULL | 42 | NR<1> | NULL | 43 | A<6> | 47 | 44 | NC<2> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 45 | NR<7> | NULL | 46 | A<22> | 35 | 47 | A<7> | 7 | 48 | A<15> | 4 | 49 | A<11> | 2 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 50 | A<17> | 58 | 51 | NC<4> | NULL | 52 | A<12> | 64 | 53 | NB<0> | NULL + +FB_IMUX_INDEX | FOOBAR1_ | 36 | 73 | 110 | 39 | 40 | 95 | 42 | 115 | 80 | 99 | 82 | 83 | 84 | 85 | 32 | 33 | 88 | 53 | 76 | 31 | 93 | 28 | 41 | 51 | 123 | 49 | 47 | 75 | 44 | 108 | 89 | 43 | 132 | 129 | 48 | 105 | 103 | 46 | 34 | 111 | 114 | 30 | 29 | 97 | 52 | 38 | 125 | 104 | 94 | 92 | 72 | 50 | 86 | 35 + + +FB_ORDER_OF_INPUTS | FOOBAR2_ | 4 | STERM | 59 | 9 | NA | NULL | 14 | A<12> | 64 | 15 | A<20> | 36 | 17 | A<21> | 50 +FB_ORDER_OF_INPUTS | FOOBAR2_ | 21 | A<24> | 52 | 23 | A<23> | 48 | 26 | $OpTx$BIN_STEP$409.UIM | NULL | 28 | A<22> | 35 | 33 | A<25> | 10 +FB_ORDER_OF_INPUTS | FOOBAR2_ | 34 | FC<0> | 31 | 38 | CMD<0> | 39 | 49 | A<11> | 2 | 50 | CMD<1> | 16 + +FB_IMUX_INDEX | FOOBAR2_ | -1 | -1 | -1 | -1 | 76 | -1 | -1 | -1 | -1 | 45 | -1 | -1 | -1 | -1 | 86 | 123 | -1 | 89 | -1 | -1 | -1 | 83 | -1 | 95 | -1 | -1 | 12 | -1 | 125 | -1 | -1 | -1 | -1 | 110 | 135 | -1 | -1 | -1 | 117 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 92 | 122 | -1 | -1 | -1 + + +FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | A<17> | 58 | 1 | A<10> | 57 | 3 | A<18> | 49 | 4 | A<15> | 4 | 6 | A<4> | 20 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 9 | NA | NULL | 13 | A<14> | 51 | 14 | A<7> | 7 | 15 | A<3> | 43 | 19 | A<9> | 11 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 20 | A<8> | 9 | 22 | CLKdat | 5 | 27 | FC<2> | 56 | 28 | A<6> | 47 | 31 | A<13> | 44 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 32 | A<5> | 63 | 33 | A<16> | 34 | 34 | FC<0> | 31 | 38 | CMD<0> | 39 | 39 | A<19> | 42 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 41 | FC<1> | 45 | 42 | A<2> | 40 | 45 | nAS | 6 | 50 | CMD<1> | 16 + +FB_IMUX_INDEX | FOOBAR3_ | 72 | 73 | -1 | 93 | 94 | -1 | 132 | -1 | -1 | 45 | -1 | -1 | -1 | 85 | 104 | 105 | -1 | -1 | -1 | 114 | 108 | -1 | 98 | -1 | -1 | -1 | -1 | 75 | 97 | -1 | -1 | 103 | 84 | 129 | 135 | -1 | -1 | -1 | 117 | 111 | -1 | 101 | 115 | -1 | -1 | 102 | -1 | -1 | -1 | -1 | 122 | -1 | -1 | -1 + + +GLOBAL_FCLK | CLK | 0 | 0 diff --git a/sterminator/XC9572XL/STERMINATOR.xise b/sterminator/XC9572XL/STERMINATOR.xise new file mode 100644 index 0000000..e7dc592 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.xise @@ -0,0 +1,234 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR.xst b/sterminator/XC9572XL/STERMINATOR.xst new file mode 100644 index 0000000..ddb25de --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR.xst @@ -0,0 +1,29 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn STERMINATOR.prj +-ifmt mixed +-ofn STERMINATOR +-ofmt NGC +-p xc9500xl +-top STERMINATOR +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy Yes +-netlist_hierarchy As_Optimized +-rtlview Yes +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-mux_extract Yes +-resource_sharing YES +-iobuf YES +-pld_mp YES +-pld_xp YES +-pld_ce YES +-wysiwyg NO +-equivalent_register_removal YES diff --git a/sterminator/XC9572XL/STERMINATOR_envsettings.html b/sterminator/XC9572XL/STERMINATOR_envsettings.html new file mode 100644 index 0000000..0d562cb --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_envsettings.html @@ -0,0 +1,238 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuild
PATHEXT.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
PathC:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files\Microchip\xc8\v2.31\bin;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files\PuTTY\;
C:\Program Files\WinMerge;
C:\Program Files\dotnet\;
C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;
C:\Users\zanek\AppData\Local\GitHubDesktop\bin;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\Users\zanek\.dotnet\tools;
C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin		C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;
C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;
C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;
C:\Xilinx\14.7\ISE_DS\common\bin\nt64;
C:\Xilinx\14.7\ISE_DS\common\lib\nt64;
C:\ispLEVER_Classic2_0\ispcpld\bin;
C:\ispLEVER_Classic2_0\ispFPGA\bin\nt;
C:\ispLEVER_Classic2_0\active-hdl\BIN;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Program Files\Microchip\xc8\v2.31\bin;
C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;
C:\Program Files\PuTTY\;
C:\Program Files\WinMerge;
C:\Program Files\dotnet\;
C:\Users\zanek\AppData\Local\Microsoft\WindowsApps;
C:\Users\zanek\AppData\Local\GitHubDesktop\bin;
C:\altera\13.0sp1\modelsim_ase\win32aloem;
C:\Users\zanek\.dotnet\tools;
C:\Program Files (x86)\Skyworks\ClockBuilder Pro\Bin
XILINXC:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\
XILINX_DSPC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISE
XILINX_EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDK
XILINX_PLANAHEADC:\Xilinx\14.7\ISE_DS\PlanAheadC:\Xilinx\14.7\ISE_DS\PlanAhead
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn STERMINATOR.prj 
-ifmt mixedMIXED
-ofn STERMINATOR 
-ofmt NGCNGC
-p xc9500xl 
-top STERMINATOR 
-opt_modeOptimization GoalSpeedSPEED
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyYesYES
-netlist_hierarchyNetlist HierarchyAs_Optimizedas_optimized
-rtlviewGenerate RTL SchematicYesNO
-bus_delimiterBus Delimiter<><>
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-resource_sharing YESYES
-iobuf YESYES
-equivalent_register_removal YESYES
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc9572xl-VQ64-5None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuild
CPU Architecture/SpeedIntel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHzIntel(R) Core(TM) i7-4770K CPU @ 3.50GHz/3500 MHz
HostZanePCZanePC
OS NameMicrosoft , 64-bitMicrosoft , 64-bit
OS Releasemajor release (build 9200)major release (build 9200)
+ \ No newline at end of file diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/applet.js b/sterminator/XC9572XL/STERMINATOR_html/fit/applet.js new file mode 100644 index 0000000..d255dd2 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/applet.js @@ -0,0 +1,128 @@ + var tmpStr = ""; + var waitWin; + + function openWait() { + waitWin = window.open("wait.htm", "wait", + "toolbar=no,location=no,"+ + "directories=no,status=no,menubar=no,scrollbars=no,"+ + "resizable=no,width=300,height=50" ); + } + + function closeWait() { if (waitWin) waitWin.close(); } + + function setMsg(msg){ + + parent.leftnav.setAppletMsg( msg ); + // now send it reload forces + // call to applet paint + location.reload(); + } + + function getMsg(){ + + return( parent.leftnav.getAppletMsg() ); + } + + function resetMsg(){ parent.leftnav.setAppletMsg(""); } + + function printAppletPkg() { + if( isNS() ){ + setMsg("cmd printPkg "); + } + else{ + document.ChipViewerApplet.PrintPkg(); + } + } + + function showAppletGraphicMC(mc) { + if( isNS() ){ + setMsg("cmd showMac " + mc); + } + else{ + document.ChipViewerApplet.ShowMac(mc); + } + } + + function ShowMC() { showAppletGraphicMC(tmpStr); } + + function showAppletGraphicFB(fb) { + if( isNS() ){ + setMsg("cmd showFB " + fb); + } + else{ + document.ChipViewerApplet.ShowFB(fb); + } + } + + function showAppletGraphicPin(pin) { + if( isNS() ){ + setMsg("cmd showPin " + pin); + } + else{ + document.ChipViewerApplet.ShowPin(pin); + } + } + + function ShowFB() { showAppletGraphicFB(tmpStr); } + + function isNS() { + return ((navigator.appName.indexOf("Netscape") >= 0) && (parseFloat(navigator.appVersion) < 5) ) ? true : false; + } + + function isIE(){ + var agt=navigator.userAgent.toLowerCase(); + return( ( (agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1) ) ? true: false ); + } + + function waitUntilOK() { + if (!waitWin) openWait(); + if (isNS()) { + if (document.ChipViewerApplet.isActive()) closeWait(); + else settimeout("waitUntilOK()",100); + } + else { + if (document.ChipViewerApplet.readyState == 4) closeWait(); + else settimeout("waitUntilOK()",100); + } + } + + + // check that the applet if file has been generated + // this can only be done if the applets been loaded. + function fileExists(fileName){ + + if( document.ChipViewerApplet.readyState != 4 ) { + window.alert("Navigation disabled until the applet is loaded." ); + } + if( isIE() ){ + if( parent.leftnav.getAppletPermission() == 1 ){ + if( document.ChipViewerApplet.TestFileExists(fileName) == 1 ){ + window.alert("file exist tests true" ); + return( true ); + } + } + else{ + window.alert("file exist returns true no permission" ); + return( true ); + } + } + else{ + return( true ); + } + window.alert("file exist returns false" ); + return( false ); + } + + + + function setPermission(){ + + if( isIE() ){ + if( document.ChipViewerApplet.granted() ){ + parent.leftnav.setAppletPermission(); + } + } + else{ + return( true ); + } + } diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/appletref.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/appletref.htm new file mode 100644 index 0000000..2182301 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/appletref.htm @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/ascii.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/ascii.htm new file mode 100644 index 0000000..d0a6314 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/ascii.htm @@ -0,0 +1,587 @@ + +
+ 
+cpldfit:  version P.20131013                        Xilinx Inc.
+                                  Fitter Report
+Design Name: STERMINATOR                         Date: 10-26-2021,  9:01PM
+Device Used: XC9572XL-5-VQ64
+Fitting Status: Successful
+
+*************************  Mapped Resource Summary  **************************
+
+Macrocells     Product Terms    Function Block   Registers      Pins           
+Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
+28 /72  ( 39%) 114 /360  ( 32%) 92 /216 ( 43%)   25 /72  ( 35%) 39 /52  ( 75%)
+
+** Function Block Resources **
+
+Function    Mcells      FB Inps     Pterms      IO          
+Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
+FB1           1/18       54/54*      52/90       6/13
+FB2           9/18       14/54       18/90      13/13*
+FB3          18/18*      24/54       44/90       8/14
+FB4           0/18        0/54        0/90      12/12*
+             -----       -----       -----      -----    
+             28/72       92/216     114/360     39/52 
+
+* - Resource is exhausted
+
+** Global Control Resources **
+
+Signal 'CLK' mapped onto global clock net GCK1.
+Global output enable net(s) unused.
+Global set/reset net(s) unused.
+
+** Pin Resources **
+
+Signal Type    Required     Mapped  |  Pin Type            Used    Total 
+------------------------------------|------------------------------------
+Input         :   36          36    |  I/O              :    34      46
+Output        :    2           2    |  GCK/IO           :     2       3
+Bidirectional :    0           0    |  GTS/IO           :     2       2
+GCK           :    1           1    |  GSR/IO           :     1       1
+GTS           :    0           0    |
+GSR           :    0           0    |
+                 ----        ----
+        Total     39          39
+
+** Power Data **
+
+There are 28 macrocells in high performance mode (MCHP).
+There are 0 macrocells in low power mode (MCLP).
+End of Mapped Resource Summary
+**************************  Errors and Warnings  ***************************
+
+WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
+   use the default filename of 'STERMINATOR.ise'.
+*************************  Summary of Mapped Logic  ************************
+
+** 2 Outputs **
+
+Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
+Name                Pts   Inps          No.  Type    Use     Mode Rate State
+nSTERM              2     4     FB2_2   60   I/O     O       STD  FAST 
+nFPUCS              2     12    FB3_2   22   I/O     O       STD  FAST 
+
+** 26 Buried Nodes **
+
+Signal              Total Total Loc     Pwr  Reg Init
+Name                Pts   Inps          Mode State
+$OpTx$BIN_STEP$409  52    54    FB1_13  STD  
+NR<9>               2     3     FB2_11  STD  RESET
+NR<1>               2     3     FB2_12  STD  RESET
+NR<12>              2     3     FB2_13  STD  RESET
+NR<11>              2     3     FB2_14  STD  RESET
+NR<10>              2     3     FB2_15  STD  RESET
+NR<0>               2     3     FB2_16  STD  RESET
+NB<1>               2     3     FB2_17  STD  RESET
+NB<0>               2     3     FB2_18  STD  RESET
+NR<8>               2     3     FB3_1   STD  RESET
+NR<7>               2     3     FB3_3   STD  RESET
+NR<6>               2     3     FB3_4   STD  RESET
+NR<5>               2     3     FB3_5   STD  RESET
+NR<4>               2     3     FB3_6   STD  RESET
+NR<3>               2     3     FB3_7   STD  RESET
+NR<2>               2     3     FB3_8   STD  RESET
+NC<0>               2     3     FB3_9   STD  RESET
+NA                  2     3     FB3_10  STD  RESET
+NC<8>               3     11    FB3_11  STD  RESET
+NC<7>               3     10    FB3_12  STD  RESET
+NC<6>               3     9     FB3_13  STD  RESET
+NC<5>               3     8     FB3_14  STD  RESET
+NC<4>               3     7     FB3_15  STD  RESET
+NC<3>               3     6     FB3_16  STD  RESET
+NC<2>               3     5     FB3_17  STD  RESET
+NC<1>               3     4     FB3_18  STD  RESET
+
+** 37 Inputs **
+
+Signal              Loc     Pin  Pin     Pin     
+Name                        No.  Type    Use     
+A<8>                FB1_5   9    I/O     I
+A<25>               FB1_6   10   I/O     I
+A<9>                FB1_8   11   I/O     I
+CLK                 FB1_9   15~  GCK/I/O GCK
+CMD<1>              FB1_11  16   GCK/I/O I
+A<4>                FB1_17  20   I/O     I
+A<17>               FB2_3   58   I/O     I
+STERM               FB2_4   59   I/O     I
+A<29>               FB2_5   61   I/O     I
+A<30>               FB2_6   62   I/O     I
+A<5>                FB2_8   63   I/O     I
+A<12>               FB2_9   64   GSR/I/O I
+A<31>               FB2_10  1    I/O     I
+A<11>               FB2_11  2    GTS/I/O I
+A<15>               FB2_12  4    I/O     I
+CLKdat              FB2_14  5    GTS/I/O I
+nAS                 FB2_15  6    I/O     I
+A<7>                FB2_17  7    I/O     I
+FC<0>               FB3_3   31   I/O     I
+A<16>               FB3_6   34   I/O     I
+CMD<0>              FB3_10  39   I/O     I
+A<2>                FB3_12  40   I/O     I
+A<22>               FB3_14  35   I/O     I
+A<20>               FB3_15  36   I/O     I
+A<19>               FB3_16  42   I/O     I
+A<3>                FB4_2   43   I/O     I
+A<28>               FB4_3   46   I/O     I
+A<6>                FB4_4   47   I/O     I
+A<13>               FB4_5   44   I/O     I
+A<18>               FB4_6   49   I/O     I
+FC<1>               FB4_8   45   I/O     I
+A<14>               FB4_10  51   I/O     I
+A<23>               FB4_11  48   I/O     I
+A<24>               FB4_12  52   I/O     I
+A<21>               FB4_14  50   I/O     I
+FC<2>               FB4_15  56   I/O     I
+A<10>               FB4_17  57   I/O     I
+
+Legend:
+Pin No. - ~ - User Assigned
+**************************  Function Block Details  ************************
+Legend:
+Total Pt     - Total product terms used by the macrocell signal
+Imp Pt       - Product terms imported from other macrocells
+Exp Pt       - Product terms exported to other macrocells
+               in direction shown
+Unused Pt    - Unused local product terms remaining in macrocell
+Loc          - Location where logic was mapped in device
+Pin Type/Use - I  - Input             GCK - Global Clock
+               O  - Output            GTS - Global Output Enable
+              (b) - Buried macrocell  GSR - Global Set/Reset
+X            - Signal used as input to the macrocell logic.
+Pin No.      - ~  - User Assigned
+*********************************** FB1  ***********************************
+Number of function block inputs used/remaining:               54/0
+Number of signals used by logic mapping into function block:  54
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB1_1         (b)     
+(unused)              0       0     0   5     FB1_2   8     I/O     
+(unused)              0       0     0   5     FB1_3   12    I/O     
+(unused)              0       0     0   5     FB1_4   13    I/O     
+(unused)              0       0     0   5     FB1_5   9     I/O     I
+(unused)              0       0     0   5     FB1_6   10    I/O     I
+(unused)              0       0     0   5     FB1_7         (b)     
+(unused)              0       0   \/2   3     FB1_8   11    I/O     I
+(unused)              0       0   \/5   0     FB1_9   15    GCK/I/O GCK
+(unused)              0       0   \/5   0     FB1_10  18    I/O     (b)
+(unused)              0       0   \/5   0     FB1_11  16    GCK/I/O I
+(unused)              0       0   \/5   0     FB1_12  23    I/O     (b)
+$OpTx$BIN_STEP$409   52      47<-   0   0     FB1_13        (b)     (b)
+(unused)              0       0   /\5   0     FB1_14  17    GCK/I/O (b)
+(unused)              0       0   /\5   0     FB1_15  19    I/O     (b)
+(unused)              0       0   /\5   0     FB1_16        (b)     (b)
+(unused)              0       0   /\5   0     FB1_17  20    I/O     I
+(unused)              0       0   /\5   0     FB1_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: A<10>             19: A<2>              37: NC<5> 
+  2: A<11>             20: A<30>             38: NC<6> 
+  3: A<12>             21: A<31>             39: NC<7> 
+  4: A<13>             22: A<3>              40: NC<8> 
+  5: A<14>             23: A<4>              41: NR<0> 
+  6: A<15>             24: A<5>              42: NR<10> 
+  7: A<16>             25: A<6>              43: NR<11> 
+  8: A<17>             26: A<7>              44: NR<12> 
+  9: A<18>             27: A<8>              45: NR<1> 
+ 10: A<19>             28: A<9>              46: NR<2> 
+ 11: A<20>             29: FC<2>             47: NR<3> 
+ 12: A<21>             30: NB<0>             48: NR<4> 
+ 13: A<22>             31: NB<1>             49: NR<5> 
+ 14: A<23>             32: NC<0>             50: NR<6> 
+ 15: A<24>             33: NC<1>             51: NR<7> 
+ 16: A<25>             34: NC<2>             52: NR<8> 
+ 17: A<28>             35: NC<3>             53: NR<9> 
+ 18: A<29>             36: NC<4>             54: STERM 
+
+Signal                        1         2         3         4         5         6 FB
+Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
+$OpTx$BIN_STEP$409   XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX...... 54
+                    0----+----1----+----2----+----3----+----4----+----5----+----6
+                              0         0         0         0         0         0
+*********************************** FB2  ***********************************
+Number of function block inputs used/remaining:               14/40
+Number of signals used by logic mapping into function block:  14
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB2_1         (b)     
+nSTERM                2       0     0   3     FB2_2   60    I/O     O
+(unused)              0       0     0   5     FB2_3   58    I/O     I
+(unused)              0       0     0   5     FB2_4   59    I/O     I
+(unused)              0       0     0   5     FB2_5   61    I/O     I
+(unused)              0       0     0   5     FB2_6   62    I/O     I
+(unused)              0       0     0   5     FB2_7         (b)     
+(unused)              0       0     0   5     FB2_8   63    I/O     I
+(unused)              0       0     0   5     FB2_9   64    GSR/I/O I
+(unused)              0       0     0   5     FB2_10  1     I/O     I
+NR<9>                 2       0     0   3     FB2_11  2     GTS/I/O I
+NR<1>                 2       0     0   3     FB2_12  4     I/O     I
+NR<12>                2       0     0   3     FB2_13        (b)     (b)
+NR<11>                2       0     0   3     FB2_14  5     GTS/I/O I
+NR<10>                2       0     0   3     FB2_15  6     I/O     I
+NR<0>                 2       0     0   3     FB2_16        (b)     (b)
+NB<1>                 2       0     0   3     FB2_17  7     I/O     I
+NB<0>                 2       0     0   3     FB2_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: $OpTx$BIN_STEP$409   6: A<22>             11: CMD<1> 
+  2: A<11>                7: A<23>             12: FC<0> 
+  3: A<12>                8: A<24>             13: NA 
+  4: A<20>                9: A<25>             14: STERM 
+  5: A<21>               10: CMD<0>           
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+nSTERM               X..........XXX.......................... 4
+NR<9>                ...X.....XX............................. 3
+NR<1>                ..X......XX............................. 3
+NR<12>               ......X..XX............................. 3
+NR<11>               .....X...XX............................. 3
+NR<10>               ....X....XX............................. 3
+NR<0>                .X.......XX............................. 3
+NB<1>                ........XXX............................. 3
+NB<0>                .......X.XX............................. 3
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB3  ***********************************
+Number of function block inputs used/remaining:               24/30
+Number of signals used by logic mapping into function block:  24
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+NR<8>                 2       0     0   3     FB3_1         (b)     (b)
+nFPUCS                2       0     0   3     FB3_2   22    I/O     O
+NR<7>                 2       0     0   3     FB3_3   31    I/O     I
+NR<6>                 2       0     0   3     FB3_4   32    I/O     (b)
+NR<5>                 2       0     0   3     FB3_5   24    I/O     (b)
+NR<4>                 2       0     0   3     FB3_6   34    I/O     I
+NR<3>                 2       0     0   3     FB3_7         (b)     (b)
+NR<2>                 2       0     0   3     FB3_8   25    I/O     (b)
+NC<0>                 2       0     0   3     FB3_9   27    I/O     (b)
+NA                    2       0     0   3     FB3_10  39    I/O     I
+NC<8>                 3       0     0   2     FB3_11  33    I/O     (b)
+NC<7>                 3       0     0   2     FB3_12  40    I/O     I
+NC<6>                 3       0     0   2     FB3_13        (b)     (b)
+NC<5>                 3       0     0   2     FB3_14  35    I/O     I
+NC<4>                 3       0     0   2     FB3_15  36    I/O     I
+NC<3>                 3       0     0   2     FB3_16  42    I/O     I
+NC<2>                 3       0     0   2     FB3_17  38    I/O     (b)
+NC<1>                 3       0     0   2     FB3_18        (b)     (b)
+
+Signals Used by Logic in Function Block
+  1: A<10>              9: A<2>              17: CLKdat 
+  2: A<13>             10: A<3>              18: CMD<0> 
+  3: A<14>             11: A<4>              19: CMD<1> 
+  4: A<15>             12: A<5>              20: FC<0> 
+  5: A<16>             13: A<6>              21: FC<1> 
+  6: A<17>             14: A<7>              22: FC<2> 
+  7: A<18>             15: A<8>              23: NA 
+  8: A<19>             16: A<9>              24: nAS 
+
+Signal                        1         2         3         4 FB
+Name                0----+----0----+----0----+----0----+----0 Inputs
+NR<8>                .......X.........XX..................... 3
+nFPUCS               .XXXXXXX........X..XXX.X................ 12
+NR<7>                ......X..........XX..................... 3
+NR<6>                .....X...........XX..................... 3
+NR<5>                ....X............XX..................... 3
+NR<4>                ...X.............XX..................... 3
+NR<3>                ..X..............XX..................... 3
+NR<2>                .X...............XX..................... 3
+NC<0>                ........X........XX..................... 3
+NA                   .................XX...X................. 3
+NC<8>                X.......XXXXXXXX.XX..................... 11
+NC<7>                ........XXXXXXXX.XX..................... 10
+NC<6>                ........XXXXXXX..XX..................... 9
+NC<5>                ........XXXXXX...XX..................... 8
+NC<4>                ........XXXXX....XX..................... 7
+NC<3>                ........XXXX.....XX..................... 6
+NC<2>                ........XXX......XX..................... 5
+NC<1>                ........XX.......XX..................... 4
+                    0----+----1----+----2----+----3----+----4
+                              0         0         0         0
+*********************************** FB4  ***********************************
+Number of function block inputs used/remaining:               0/54
+Number of signals used by logic mapping into function block:  0
+Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
+Name                Pt      Pt    Pt  Pt               #    Type    Use
+(unused)              0       0     0   5     FB4_1         (b)     
+(unused)              0       0     0   5     FB4_2   43    I/O     I
+(unused)              0       0     0   5     FB4_3   46    I/O     I
+(unused)              0       0     0   5     FB4_4   47    I/O     I
+(unused)              0       0     0   5     FB4_5   44    I/O     I
+(unused)              0       0     0   5     FB4_6   49    I/O     I
+(unused)              0       0     0   5     FB4_7         (b)     
+(unused)              0       0     0   5     FB4_8   45    I/O     I
+(unused)              0       0     0   5     FB4_9         (b)     
+(unused)              0       0     0   5     FB4_10  51    I/O     I
+(unused)              0       0     0   5     FB4_11  48    I/O     I
+(unused)              0       0     0   5     FB4_12  52    I/O     I
+(unused)              0       0     0   5     FB4_13        (b)     
+(unused)              0       0     0   5     FB4_14  50    I/O     I
+(unused)              0       0     0   5     FB4_15  56    I/O     I
+(unused)              0       0     0   5     FB4_16        (b)     
+(unused)              0       0     0   5     FB4_17  57    I/O     I
+(unused)              0       0     0   5     FB4_18        (b)     
+*******************************  Equations  ********************************
+
+********** Mapped Logic **********
+
+
+$OpTx$BIN_STEP$409 <= ((EXP9_.EXP)
+	OR (A(5) AND NOT NC(3) AND NOT STERM)
+	OR (NOT A(5) AND NC(3) AND NOT STERM)
+	OR (A(9) AND NOT NC(7) AND NOT STERM)
+	OR (NOT A(9) AND NC(7) AND NOT STERM)
+	OR (A(19) AND NOT NR(8) AND NOT STERM)
+	OR (EXP12_.EXP)
+	OR (NOT A(24) AND NB(0) AND NOT STERM)
+	OR (A(4) AND NOT NC(2) AND NOT STERM)
+	OR (NOT A(4) AND NC(2) AND NOT STERM)
+	OR (A(8) AND NOT NC(6) AND NOT STERM)
+	OR (NOT A(8) AND NC(6) AND NOT STERM)
+	OR (NOT FC(2) AND NOT STERM)
+	OR (A(31) AND NOT STERM)
+	OR (A(15) AND NOT NR(4) AND NOT STERM)
+	OR (NOT A(15) AND NR(4) AND NOT STERM)
+	OR (NOT A(19) AND NR(8) AND NOT STERM));
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+FDCPE_NA: FDCPE port map (NA,NA_D,CLK,'0','0');
+NA_D <= ((CMD(0) AND NOT CMD(1))
+	OR (NOT CMD(1) AND NA));
+
+FDCPE_NB0: FDCPE port map (NB(0),A(24),CLK,'0','0',NB_CE(0));
+NB_CE(0) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NB1: FDCPE port map (NB(1),A(25),CLK,'0','0',NB_CE(1));
+NB_CE(1) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC0: FDCPE port map (NC(0),NOT A(2),CLK,'0','0',NC_CE(0));
+NC_CE(0) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC1: FDCPE port map (NC(1),NC_D(1),CLK,'0','0',NC_CE(1));
+NC_D(1) <= A(2)
+	 XOR 
+NC_D(1) <= A(3);
+NC_CE(1) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC2: FDCPE port map (NC(2),NC_D(2),CLK,'0','0',NC_CE(2));
+NC_D(2) <= A(4)
+	 XOR 
+NC_D(2) <= (A(2) AND A(3));
+NC_CE(2) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC3: FDCPE port map (NC(3),NC_D(3),CLK,'0','0',NC_CE(3));
+NC_D(3) <= A(5)
+	 XOR 
+NC_D(3) <= (A(2) AND A(3) AND A(4));
+NC_CE(3) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC4: FDCPE port map (NC(4),NC_D(4),CLK,'0','0',NC_CE(4));
+NC_D(4) <= A(6)
+	 XOR 
+NC_D(4) <= (A(2) AND A(3) AND A(4) AND A(5));
+NC_CE(4) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC5: FDCPE port map (NC(5),NC_D(5),CLK,'0','0',NC_CE(5));
+NC_D(5) <= A(7)
+	 XOR 
+NC_D(5) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6));
+NC_CE(5) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC6: FDCPE port map (NC(6),NC_D(6),CLK,'0','0',NC_CE(6));
+NC_D(6) <= A(8)
+	 XOR 
+NC_D(6) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7));
+NC_CE(6) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC7: FDCPE port map (NC(7),NC_D(7),CLK,'0','0',NC_CE(7));
+NC_D(7) <= A(9)
+	 XOR 
+NC_D(7) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND 
+	A(8));
+NC_CE(7) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NC8: FDCPE port map (NC(8),NC_D(8),CLK,'0','0',NC_CE(8));
+NC_D(8) <= A(10)
+	 XOR 
+NC_D(8) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND 
+	A(8) AND A(9));
+NC_CE(8) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR0: FDCPE port map (NR(0),A(11),CLK,'0','0',NR_CE(0));
+NR_CE(0) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR1: FDCPE port map (NR(1),A(12),CLK,'0','0',NR_CE(1));
+NR_CE(1) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR2: FDCPE port map (NR(2),A(13),CLK,'0','0',NR_CE(2));
+NR_CE(2) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR3: FDCPE port map (NR(3),A(14),CLK,'0','0',NR_CE(3));
+NR_CE(3) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR4: FDCPE port map (NR(4),A(15),CLK,'0','0',NR_CE(4));
+NR_CE(4) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR5: FDCPE port map (NR(5),A(16),CLK,'0','0',NR_CE(5));
+NR_CE(5) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR6: FDCPE port map (NR(6),A(17),CLK,'0','0',NR_CE(6));
+NR_CE(6) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR7: FDCPE port map (NR(7),A(18),CLK,'0','0',NR_CE(7));
+NR_CE(7) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR8: FDCPE port map (NR(8),A(19),CLK,'0','0',NR_CE(8));
+NR_CE(8) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR9: FDCPE port map (NR(9),A(20),CLK,'0','0',NR_CE(9));
+NR_CE(9) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR10: FDCPE port map (NR(10),A(21),CLK,'0','0',NR_CE(10));
+NR_CE(10) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR11: FDCPE port map (NR(11),A(22),CLK,'0','0',NR_CE(11));
+NR_CE(11) <= (CMD(0) AND NOT CMD(1));
+
+FDCPE_NR12: FDCPE port map (NR(12),A(23),CLK,'0','0',NR_CE(12));
+NR_CE(12) <= (CMD(0) AND NOT CMD(1));
+
+
+nFPUCS <= NOT (((FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND 
+	NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT nAS)
+	OR (FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND 
+	NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT CLKdat)));
+
+
+nSTERM <= NOT (((STERM AND NOT $OpTx$BIN_STEP$409)
+	OR (NOT FC(0) AND NA AND NOT $OpTx$BIN_STEP$409)));
+
+Register Legend:
+ FDCPE (Q,D,C,CLR,PRE,CE); 
+ FTCPE (Q,D,C,CLR,PRE,CE); 
+ LDCP  (Q,D,G,CLR,PRE); 
+
+******************************  Device Pin Out *****************************
+
+Device : XC9572XL-5-VQ64
+
+
+   -----------------------------------------------  
+  /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
+ | 49                                           32 | 
+ | 50                                           31 | 
+ | 51                                           30 | 
+ | 52                                           29 | 
+ | 53                                           28 | 
+ | 54                                           27 | 
+ | 55                                           26 | 
+ | 56               XC9572XL-5-VQ64             25 | 
+ | 57                                           24 | 
+ | 58                                           23 | 
+ | 59                                           22 | 
+ | 60                                           21 | 
+ | 61                                           20 | 
+ | 62                                           19 | 
+ | 63                                           18 | 
+ | 64                                           17 | 
+ \ 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16 /
+   -----------------------------------------------  
+
+
+Pin Signal                         Pin Signal                        
+No. Name                           No. Name                          
+  1 A<31>                            33 KPR                           
+  2 A<11>                            34 A<16>                         
+  3 VCC                              35 A<22>                         
+  4 A<15>                            36 A<20>                         
+  5 CLKdat                           37 VCC                           
+  6 nAS                              38 KPR                           
+  7 A<7>                             39 CMD<0>                        
+  8 KPR                              40 A<2>                          
+  9 A<8>                             41 GND                           
+ 10 A<25>                            42 A<19>                         
+ 11 A<9>                             43 A<3>                          
+ 12 KPR                              44 A<13>                         
+ 13 KPR                              45 FC<1>                         
+ 14 GND                              46 A<28>                         
+ 15 CLK                              47 A<6>                          
+ 16 CMD<1>                           48 A<23>                         
+ 17 KPR                              49 A<18>                         
+ 18 KPR                              50 A<21>                         
+ 19 KPR                              51 A<14>                         
+ 20 A<4>                             52 A<24>                         
+ 21 GND                              53 TDO                           
+ 22 nFPUCS                           54 GND                           
+ 23 KPR                              55 VCC                           
+ 24 KPR                              56 FC<2>                         
+ 25 KPR                              57 A<10>                         
+ 26 VCC                              58 A<17>                         
+ 27 KPR                              59 STERM                         
+ 28 TDI                              60 nSTERM                        
+ 29 TMS                              61 A<29>                         
+ 30 TCK                              62 A<30>                         
+ 31 FC<0>                            63 A<5>                          
+ 32 KPR                              64 A<12>                         
+
+
+Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+****************************  Compiler Options  ****************************
+
+Following is a list of all global compiler options used by the fitter run.
+
+Device(s) Specified                         : xc9572xl-5-VQ64
+Optimization Method                         : SPEED
+Multi-Level Logic Optimization              : ON
+Ignore Timing Specifications                : OFF
+Default Register Power Up Value             : LOW
+Keep User Location Constraints              : ON
+What-You-See-Is-What-You-Get                : OFF
+Exhaustive Fitting                          : OFF
+Keep Unused Inputs                          : OFF
+Slew Rate                                   : FAST
+Power Mode                                  : STD
+Ground on Unused IOs                        : OFF
+Set I/O Pin Termination                     : KEEPER
+Global Clock Optimization                   : ON
+Global Set/Reset Optimization               : ON
+Global Ouput Enable Optimization            : ON
+Input Limit                                 : 54
+Pterm Limit                                 : 25
+
+
+ + +
+ diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/asciidoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/asciidoc.htm new file mode 100644 index 0000000..3455598 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/asciidoc.htm @@ -0,0 +1,71 @@ + + + + + + + + + + +Text Report + + + + + + + + + + + + + + + + + + + + + + + + +

Text Report

+ +

Selecting Text + Report from the left-hand frame will give you a printable text version + of the fitter report.  It + contains sections similar to those of the XML report (a summary section, + errors and warnings, mapped logic, function blocks, function block details, + a text-graphical display of the pinout, and a summary of compiler options), + but it is not easily navigable.  It + is best to use the text report only when you need to print out a hard + copy of the fitter results.

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Equations

+ + +
+
+********** Mapped Logic ********** +
+
+$OpTx$BIN_STEP$409 <= ((EXP9_.EXP) +
      OR (A(5) AND NOT NC(3) AND NOT STERM) +
      OR (NOT A(5) AND NC(3) AND NOT STERM) +
      OR (A(9) AND NOT NC(7) AND NOT STERM) +
      OR (NOT A(9) AND NC(7) AND NOT STERM) +
      OR (A(19) AND NOT NR(8) AND NOT STERM) +
      OR (EXP12_.EXP) +
      OR (NOT A(24) AND NB(0) AND NOT STERM) +
      OR (A(4) AND NOT NC(2) AND NOT STERM) +
      OR (NOT A(4) AND NC(2) AND NOT STERM) +
      OR (A(8) AND NOT NC(6) AND NOT STERM) +
      OR (NOT A(8) AND NC(6) AND NOT STERM) +
      OR (NOT FC(2) AND NOT STERM) +
      OR (A(31) AND NOT STERM) +
      OR (A(15) AND NOT NR(4) AND NOT STERM) +
      OR (NOT A(15) AND NR(4) AND NOT STERM) +
      OR (NOT A(19) AND NR(8) AND NOT STERM)); +
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+FDCPE_NA: FDCPE port map (NA,NA_D,CLK,'0','0'); +
     NA_D <= ((CMD(0) AND NOT CMD(1)) +
      OR (NOT CMD(1) AND NA)); +
+FDCPE_NB0: FDCPE port map (NB(0),A(24),CLK,'0','0',NB_CE(0)); +
     NB_CE(0) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NB1: FDCPE port map (NB(1),A(25),CLK,'0','0',NB_CE(1)); +
     NB_CE(1) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC0: FDCPE port map (NC(0),NOT A(2),CLK,'0','0',NC_CE(0)); +
     NC_CE(0) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC1: FDCPE port map (NC(1),NC_D(1),CLK,'0','0',NC_CE(1)); +
     NC_D(1) <= A(2) +
      XOR +
     NC_D(1) <= A(3); +
     NC_CE(1) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC2: FDCPE port map (NC(2),NC_D(2),CLK,'0','0',NC_CE(2)); +
     NC_D(2) <= A(4) +
      XOR +
     NC_D(2) <= (A(2) AND A(3)); +
     NC_CE(2) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC3: FDCPE port map (NC(3),NC_D(3),CLK,'0','0',NC_CE(3)); +
     NC_D(3) <= A(5) +
      XOR +
     NC_D(3) <= (A(2) AND A(3) AND A(4)); +
     NC_CE(3) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC4: FDCPE port map (NC(4),NC_D(4),CLK,'0','0',NC_CE(4)); +
     NC_D(4) <= A(6) +
      XOR +
     NC_D(4) <= (A(2) AND A(3) AND A(4) AND A(5)); +
     NC_CE(4) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC5: FDCPE port map (NC(5),NC_D(5),CLK,'0','0',NC_CE(5)); +
     NC_D(5) <= A(7) +
      XOR +
     NC_D(5) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6)); +
     NC_CE(5) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC6: FDCPE port map (NC(6),NC_D(6),CLK,'0','0',NC_CE(6)); +
     NC_D(6) <= A(8) +
      XOR +
     NC_D(6) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7)); +
     NC_CE(6) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC7: FDCPE port map (NC(7),NC_D(7),CLK,'0','0',NC_CE(7)); +
     NC_D(7) <= A(9) +
      XOR +
     NC_D(7) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND +
      A(8)); +
     NC_CE(7) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NC8: FDCPE port map (NC(8),NC_D(8),CLK,'0','0',NC_CE(8)); +
     NC_D(8) <= A(10) +
      XOR +
     NC_D(8) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND +
      A(8) AND A(9)); +
     NC_CE(8) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR0: FDCPE port map (NR(0),A(11),CLK,'0','0',NR_CE(0)); +
     NR_CE(0) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR1: FDCPE port map (NR(1),A(12),CLK,'0','0',NR_CE(1)); +
     NR_CE(1) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR2: FDCPE port map (NR(2),A(13),CLK,'0','0',NR_CE(2)); +
     NR_CE(2) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR3: FDCPE port map (NR(3),A(14),CLK,'0','0',NR_CE(3)); +
     NR_CE(3) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR4: FDCPE port map (NR(4),A(15),CLK,'0','0',NR_CE(4)); +
     NR_CE(4) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR5: FDCPE port map (NR(5),A(16),CLK,'0','0',NR_CE(5)); +
     NR_CE(5) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR6: FDCPE port map (NR(6),A(17),CLK,'0','0',NR_CE(6)); +
     NR_CE(6) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR7: FDCPE port map (NR(7),A(18),CLK,'0','0',NR_CE(7)); +
     NR_CE(7) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR8: FDCPE port map (NR(8),A(19),CLK,'0','0',NR_CE(8)); +
     NR_CE(8) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR9: FDCPE port map (NR(9),A(20),CLK,'0','0',NR_CE(9)); +
     NR_CE(9) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR10: FDCPE port map (NR(10),A(21),CLK,'0','0',NR_CE(10)); +
     NR_CE(10) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR11: FDCPE port map (NR(11),A(22),CLK,'0','0',NR_CE(11)); +
     NR_CE(11) <= (CMD(0) AND NOT CMD(1)); +
+FDCPE_NR12: FDCPE port map (NR(12),A(23),CLK,'0','0',NR_CE(12)); +
     NR_CE(12) <= (CMD(0) AND NOT CMD(1)); +
+
+nFPUCS <= NOT (((FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND +
      NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT nAS) +
      OR (FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND +
      NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT CLKdat))); +
+
+nSTERM <= NOT (((STERM AND NOT $OpTx$BIN_STEP$409) +
      OR (NOT FC(0) AND NA AND NOT $OpTx$BIN_STEP$409))); +
+Register Legend: +
      FDCPE (Q,D,C,CLR,PRE,CE); +
      FTCPE (Q,D,C,CLR,PRE,CE); +
      LDCP (Q,D,G,CLR,PRE); +
+
+
+ + +
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"; +var tabStr = spcStr + spcStr + spcStr + spcStr + spcStr; +var nlTabStr = nlStr + tabStr; +var rClrS = ""; +var rClrE = ""; +var cClrS = ""; +var cClrE = ""; + +var abelOper = new Array(); +abelOper["GND"] = new Array("Gnd"); +abelOper["VCC"] = new Array("Vcc"); +abelOper["NOT"] = new Array(rClrS + "!" + rClrE); +abelOper["AND"] = new Array(rClrS + "&" + rClrE); +abelOper["OR"] = new Array(rClrS + "#" + rClrE); +abelOper["XOR"] = new Array(rClrS + "$" + rClrE); +abelOper["EQUAL_COLON"] = new Array(":= "); +abelOper["EQUAL"] = new Array("= "); +abelOper["ASSIGN"] = new Array(""); +abelOper["OPEN_NEGATE"] = new Array("("); +abelOper["CLOSE_NEGATE"] = new Array(")"); +abelOper["OPEN_PTERM"] = new Array(""); +abelOper["CLOSE_PTERM"] = new Array(""); +abelOper["OPEN_BRACE"] = new Array("<"); +abelOper["CLOSE_BRACE"] = new Array(">"); +abelOper["INVALID_OPEN_BRACE"] = new Array("<"); +abelOper["INVALID_CLOSE_BRACE"] = new Array(">"); + +abelOper["ENDLN"] = new Array(";"); +abelOper["COMMENT"] = new Array("//"); +abelOper["IMPORT"] = new Array(";Imported pterms "); +abelOper["GCK_COM"] = new Array("GCK"); +abelOper["GTS_COM"] = new Array("GTS"); +abelOper["GSR_COM"] = new Array("GSR"); +abelOper["OD_COM"] = new Array("Open Drain"); +abelOper["START_EQN"] = new Array(""); +abelOper["END_EQN"] = new Array(""); + +abelOper["_I"] = new Array(".I"); +abelOper["_T"] = new Array(".T"); +abelOper["_D"] = new Array(".D"); +abelOper["_C"] = new Array(".CLK"); +abelOper["_DEC"] = new Array(".DEC"); +abelOper["_LH"] = new Array(".LH"); +abelOper["_CLR"] = new Array(".AR"); +abelOper["_PRE"] = new Array(".AP"); +abelOper["_CE"] = new Array(".CE"); +abelOper["_OE"] = new Array(".OE"); + +abelOper["OE_START"] = new Array(" <= "); +abelOper["OE_WHEN"] = new Array(" when "); +abelOper["OE_EQUAL"] = new Array(" = "); +abelOper["OE_ELSE"] = new Array(" else "); +abelOper["B0"] = new Array("'0'"); +abelOper["B1"] = new Array("'1'"); +abelOper["BZ"] = new Array("'Z'"); + +abelOper["FD"] = new Array(".D"); +abelOper["FT"] = new Array(".T"); +abelOper["FDD"] = new Array(".DEC"); +abelOper["FTD"] = new Array(".T"); +abelOper["LD"] = new Array(".LH"); +abelOper["Q"] = new Array(".Q"); + +var vhdlOper = new Array(); +vhdlOper["GND"] = new Array("'0'"); +vhdlOper["VCC"] = new Array("'1'"); +vhdlOper["NOT"] = new Array(rClrS + "NOT " + rClrE); +vhdlOper["AND"] = new Array(rClrS + "AND" + rClrE); +vhdlOper["OR"] = new Array(rClrS + "OR" + rClrE); +vhdlOper["XOR"] = new Array(rClrS + "XOR" + rClrE); +vhdlOper["EQUAL_COLON"] = new Array("<= "); +vhdlOper["EQUAL"] = new Array("<= "); +vhdlOper["ASSIGN"] = new Array(""); +vhdlOper["OPEN_NEGATE"] = new Array("("); +vhdlOper["CLOSE_NEGATE"] = new Array(")"); +vhdlOper["OPEN_PTERM"] = new Array("("); +vhdlOper["CLOSE_PTERM"] = new Array(")"); +vhdlOper["OPEN_BRACE"] = new Array("("); +vhdlOper["CLOSE_BRACE"] = new Array(")"); +vhdlOper["INVALID_OPEN_BRACE"] = new Array("<"); +vhdlOper["INVALID_CLOSE_BRACE"] = new Array(">"); + +vhdlOper["ENDLN"] = new Array(";"); +vhdlOper["COMMENT"] = new Array("--"); +vhdlOper["IMPORT"] = new Array(""); +vhdlOper["GCK_COM"] = new Array("GCK"); +vhdlOper["GTS_COM"] = new Array("GTS"); +vhdlOper["GSR_COM"] = new Array("GSR"); +vhdlOper["OD_COM"] = new Array("Open Drain"); +vhdlOper["START_EQN"] = new Array(rClrS + "port map" + rClrE + " ("); +vhdlOper["END_EQN"] = new Array(")"); + +vhdlOper["_I"] = new Array("_I"); +vhdlOper["_T"] = new Array("_T"); +vhdlOper["_D"] = new Array("_D"); +vhdlOper["_C"] = new Array("_C"); +vhdlOper["_DEC"] = new Array("_C"); +vhdlOper["_LH"] = new Array("_C"); +vhdlOper["_CLR"] = new Array("_CLR"); +vhdlOper["_PRE"] = new Array("_PRE"); +vhdlOper["_CE"] = new Array("_CE"); +vhdlOper["_OE"] = new Array("_OE"); + +vhdlOper["OE_START"] = new Array(" <= "); +vhdlOper["OE_WHEN"] = new Array(" when "); +vhdlOper["OE_EQUAL"] = new Array(" = "); +vhdlOper["OE_ELSE"] = new Array(" else "); +vhdlOper["B0"] = new Array("'0'"); +vhdlOper["B1"] = new Array("'1'"); +vhdlOper["BZ"] = new Array("'Z'"); + +vhdlOper["FD"] = new Array("FDCPE"); +vhdlOper["FT"] = new Array("FTCPE"); +vhdlOper["FDD"] = new Array("FDDCPE"); +vhdlOper["FTD"] = new Array("FTDCPE"); +vhdlOper["LD"] = new Array("LDCP"); +vhdlOper["Q"] = new Array(""); + +var verOper = new Array(); +verOper["GND"] = new Array("1'b0"); +verOper["VCC"] = new Array("1'b1"); +verOper["NOT"] = new Array(rClrS + "!" + rClrE); +verOper["AND"] = new Array(rClrS + "&&" + rClrE); +verOper["OR"] = new Array(rClrS + "||" + rClrE); +verOper["XOR"] = new Array(rClrS + "XOR" + rClrE); +verOper["EQUAL_COLON"] = new Array("= "); +verOper["EQUAL"] = new Array("= "); +verOper["ASSIGN"] = new Array("assign "); +verOper["OPEN_NEGATE"] = new Array("("); +verOper["CLOSE_NEGATE"] = new Array(")"); +verOper["OPEN_PTERM"] = new Array("("); +verOper["CLOSE_PTERM"] = new Array(")"); +verOper["OPEN_BRACE"] = new Array("["); +verOper["CLOSE_BRACE"] = new Array("]"); +verOper["INVALID_OPEN_BRACE"] = new Array("<"); +verOper["INVALID_CLOSE_BRACE"] = new Array(">"); + +verOper["ENDLN"] = new Array(";"); +verOper["COMMENT"] = new Array("//"); +verOper["IMPORT"] = new Array(""); +verOper["GCK_COM"] = new Array("GCK"); +verOper["GTS_COM"] = new Array("GTS"); +verOper["GSR_COM"] = new Array("GSR"); +verOper["OD_COM"] = new Array("Open Drain"); +verOper["START_EQN"] = new Array(" ("); +verOper["END_EQN"] = new Array(")"); + +verOper["_I"] = new Array("_I"); +verOper["_T"] = new Array("_T"); +verOper["_D"] = new Array("_D"); +verOper["_C"] = new Array("_C"); +verOper["_DEC"] = new Array("_C"); +verOper["_LH"] = new Array("_C"); +verOper["_CLR"] = new Array("_CLR"); +verOper["_PRE"] = new Array("_PRE"); +verOper["_CE"] = new Array("_CE"); +verOper["_OE"] = new Array("_OE"); + +verOper["OE_START"] = new Array(" = "); +verOper["OE_WHEN"] = new Array(" ? "); +verOper["OE_EQUAL"] = new Array(""); +verOper["OE_ELSE"] = new Array(" : "); +verOper["B0"] = new Array("1'b0"); +verOper["B1"] = new Array("1'b1"); +verOper["BZ"] = new Array("1'bz"); + +verOper["FD"] = new Array("FDCPE"); +verOper["FT"] = new Array("FTCPE"); +verOper["FDD"] = new Array("FDDCPE"); +verOper["FTD"] = new Array("FTDCPE"); +verOper["LD"] = new Array("LDCP"); +verOper["Q"] = new Array(""); + +var operator = abelOper; + +var pterms = new Array(); +var d1 = new Array(); +var d2 = new Array(); +var clk = new Array(); +var set = new Array(); +var rst = new Array(); +var trst = new Array(); +var d1imp = new Array(); +var d2imp = new Array(); +var clkimp = new Array(); +var setimp = new Array(); +var rstimp = new Array(); +var trstimp = new Array(); +var gblclk = new Array(); +var gblset = new Array(); +var gblrst = new Array(); +var gbltrst = new Array(); +var ce = new Array(); +var ceimp = new Array(); +var prld = new Array(); +var specSig = new Array(); +var clkNegs = new Array(); +var setNegs = new Array(); +var rstNegs = new Array(); +var trstNegs = new Array(); +var ceNegs = new Array(); +var fbnand = new Array(); +var inreg = new Array(); +var iostyle = new Array(); + +var dOneLit = true; + +function setOper(type) { + if (type == "1") { operator = vhdlOper; eqnType = 1; } + else if (type == "2") { operator = verOper; eqnType = 2; } + else { operator = abelOper; eqnType = 0; } +} + +function isXC95() { + if (device.indexOf("95") != -1) return true; + return false; +} + +function is9500() { + if ((device.indexOf("95") != -1) && + (device.indexOf("XL") == -1) && + (device.indexOf("XV") == -1)) return true; + return false; +} + +function retSigType(s) { + var sigType = sigTypes[s]; + var str = operator["Q"]; + if (sigType == "D") str = operator["FD"]; + else if (sigType == "T") str = operator["FT"]; + else if (sigType.indexOf("LATCH") != -1) str = operator["LD"]; + else if (sigType.indexOf("DDEFF") != -1) str = operator["FDD"]; + else if (sigType.indexOf("DEFF") != -1) str = operator["FD"]; + else if (sigType.indexOf("DDFF") != -1) str = operator["FDD"]; + else if (sigType.indexOf("TDFF") != -1) str = operator["FTD"]; + else if (sigType.indexOf("DFF") != -1) str = operator["FD"]; + else if (sigType.indexOf("TFF") != -1) str = operator["FT"]; + return str; +} + +function retSigIndex(signal) { + for (s=0; s 1) str += operator["OPEN_PTERM"]; + for (p=0; p0) str += " " + operator["AND"] + " "; + var neg = 0; + if (sig.indexOf("/") != -1) { + sig = sig.substring(1, sig.length); + str += operator["NOT"]; + neg = 1; + } + + str += retSigName(sig); + } + if (pterms[pt].length > 1) str += operator["CLOSE_PTERM"]; + + return str; +} + +function retFBMC(str) { + return str.substring(0,str.length-2) + nlStr + tabStr; +} + +function retD1D2(signal) { + var str = ""; + + dOneLit = true; + if (d1[signal]) { + var currImp = ""; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(d1[signal][i]); + } + + if (d2[signal]) str += nlTabStr + operator["XOR"]+ spcStr; + } + + if (d2[signal]) { + var currImp = ""; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(d2[signal][i]); + } + } + + if (str == "GND") str = operator["GND"]; + else if (str == "VCC") str = operator["VCC"]; + else if (!isOneLiteral(str)) { + dOneLit = false; + + var type = retSigType(retSigIndex(signal)); + if ((type == operator["FD"]) || + (type == operator["FDD"])) type = operator["_D"]; + else if ((type == operator["FT"]) || + (type == operator["FTD"])) type = operator["_T"]; + else if (type == operator["LD"] && eqnType) type = "_D"; + + var tmpStr = updateName(retSigName(signal), type); + tmpStr += spcStr + operator["EQUAL_COLON"]; + var idx = retSigIndex(signal); + if (eqnType && sigNegs[idx] == "ON") tmpStr += operator["NOT"] + operator["OPEN_NEGATE"]; + str = tmpStr + str; + if (eqnType && sigNegs[idx] == "ON") str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + + return str; +} + +function retClk(signal) { + var str = ""; + + if (clk[signal]) { + if (clk[signal].length == 1) { + var pterm = retPterm(clk[signal][0]); + if (clkNegs[signal]) { + str += operator["NOT"]; + if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"]; + } + str += pterm; + if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"]; + } + else { + if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + var currImp = ""; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(clk[signal][i]); + } + if (clkNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (gblclk[signal]) { + if (gblclk[signal].length == 1) { + var pterm = retPterm(gblclk[signal][0]); + if (clkNegs[signal]) { + str += operator["NOT"]; + if (!isOneLiteral(pterm)) str += operator["OPEN_NEGATE"]; + } + str += pterm; + if (clkNegs[signal] && !isOneLiteral(pterm)) str += operator["CLOSE_NEGATE"]; + } + else { + if (clkNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gblclk[signal][i]); + } + if (clkNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"] + tabStr + cClrS + + operator["COMMENT"] + spcStr + operator["GCK_COM"] + cClrE; + } + } + else if (eqnType) str += operator["B0"]; + + return str; +} + +function retRst(signal) { + var str = ""; + + if (rst[signal]) { + if (rst[signal].length == 1) { + var currImp; + if (!eqnType && rstimp[signal] && (rstimp[signal][0] == "1")) { + if ((currImp != retFBMC(rst[signal][i])) && + (rst[signal][i].indexOf("FB") == 0)) { + currImp = retFBMC(rst[signal][0]); + str += nlStr + operator["IMPORT"] + currImp; + } + } + if (rstNegs[signal]) str += operator["NOT"]; + str += retPterm(rst[signal][0]); + } + else { + var currImp = ""; + if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(rst[signal][i]); + } + if (rstNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (gblrst[signal]) { + if (gblrst[signal].length == 1) { + if (rstNegs[signal]) str += operator["NOT"]; + str += retPterm(gblrst[signal][0]); + } + else { + if (rstNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gblrst[signal][i]); + } + if (rstNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"] + tabStr + cClrS + + operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE; + } + } + else if (eqnType) str += operator["B0"]; + + return str; +} + +function retSet(signal) { + var str = ""; + + if (set[signal]) { + if (set[signal].length == 1) { + var currImp = ""; + if (!eqnType && setimp[signal] && (setimp[signal][0] == "1")) { + if ((currImp != retFBMC(set[signal][i])) && + (set[signal][i].indexOf("FB") == 0)) { + currImp = retFBMC(set[signal][0]); + str += nlStr + operator["IMPORT"] + currImp; + } + } + if (setNegs[signal]) str += operator["NOT"]; + str += retPterm(set[signal][0]); + } + else { + var currImp = ""; + if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(set[signal][i]); + } + if (setNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (gblset[signal]) { + if (gblset[signal].length == 1) { + if (setNegs[signal]) str += operator["NOT"]; + str += retPterm(gblset[signal][0]); + } + else { + if (setNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gblset[signal][i]); + } + if (setNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"] + tabStr + cClrS + + operator["COMMENT"] + spcStr + operator["GSR_COM"] + cClrE; + } + } + else if (eqnType) str += operator["B0"]; + + return str; +} + +function retCE(signal) { + var str = ""; + + if (ce[signal]) { + if (ce[signal].length == 1) { + var currImp = ""; + if (!eqnType && ceimp[signal] && (ceimp[signal][0] == "1")) { + if ((currImp != retFBMC(ce[signal][i])) && + (ce[signal][i].indexOf("FB") == 0)) { + currImp = retFBMC(ce[signal][0]); + str += nlStr + operator["IMPORT"] + currImp; + } + } + if (ceNegs[signal]) str += operator["NOT"]; + str += retPterm(ce[signal][0]); + } + else { + var currImp = ""; + if (ceNegs[signal]) str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(ce[signal][i]); + } + if (ceNegs[signal]) str += operator["CLOSE_NEGATE"]; + str += operator["ENDLN"]; + } + } + else if (eqnType) str += operator["B1"]; + + return str; +} + +function retTrst(signal) { + var str = ""; + if (trst[signal]) { + if (trstNegs[signal]) + str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(trst[signal][i]); + } + if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; + } + else if (gbltrst[signal]) { + if (trstNegs[signal]) + str += operator["NOT"] + operator["OPEN_NEGATE"]; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(gbltrst[signal][i]); + } + if (trstNegs[signal]) str += operator["CLOSE_NEGATE"]; + } + + str += operator["ENDLN"]; + return str; +} + +function retEqn(signal) { + var str = inregStr = ""; + var iStr = qStr = ""; + var dStr = dEqn = ""; + var cStr = cEqn = ""; + var clrStr = clrEqn = ""; + var preStr = preEqn = ""; + var ceStr = ceEqn = ""; + var oeStr = oeEqn = ""; + var sigName = retSigName(signal); + + var type = retSigType(retSigIndex(signal)); + + if (gbltrst[signal] || trst[signal]) iStr = operator["_I"]; + if (eqnType) qStr = updateName(sigName, iStr); + + if (inreg[signal]) { + if (!eqnType) + inregStr = operator["COMMENT"] + " Direct Input Register" + nlStr; + dStr = retSigName(inreg[signal][0]); + } + else dStr = retD1D2(signal); + if (eqnType && !dOneLit) { + dEqn = dStr; + dStr = dStr.substring(0,dStr.indexOf(operator["EQUAL_COLON"])); + } + else if (!eqnType) { + if (!dOneLit) dStr = dStr.substring(dStr.indexOf(operator["EQUAL_COLON"])+2); + if (sigNegs[retSigIndex(signal)] == "ON") dEqn += operator["NOT"]; + dEqn += sigName; + if ((type == operator["FT"]) || + (type == operator["FTD"])) dEqn += operator["_T"]; + else if ((type == operator["FD"]) || + (type == operator["FTD"])|| + (type == operator["LD"])) dEqn += operator["_D"]; + dEqn += " "; + if ((type != operator["Q"]) && (type != operator["LD"])) + dEqn += operator["EQUAL_COLON"]; + else dEqn += operator["EQUAL"]; + dEqn += dStr; + if (dOneLit) { + dEqn += operator["ENDLN"]; + if (iostyle[signal] && iostyle[signal].indexOf("OD")) + dEqn += tabStr + operator["COMMENT"] + " " + operator["OD_COM"]; + } + } + + cStr = retClk(signal); + if (eqnType && !isOneLiteral(cStr)){ + cEqn = cStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + cEqn += operator["ENDLN"]; + cStr = updateName(sigName, operator["_C"]); + } + else if (!eqnType && cStr) { + cEqn += cStr; + cStr = tabStr + sigName; + if (type == operator["LD"]) cStr += operator["_LH"]; + else if (type == operator["FDD"]) cStr += operator["_DEC"]; + else cStr += operator["_C"]; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + cEqn += operator["ENDLN"]; + if (gblclk[signal]) cEqn += tabStr + operator["COMMENT"] + " " + operator["GCK_COM"]; + } + + clrStr = retRst(signal); + if (eqnType && !isOneLiteral(clrStr)){ + clrEqn = clrStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + clrEqn += operator["ENDLN"]; + clrStr = updateName(sigName, operator["_CLR"]); + } + else if (!eqnType && clrStr) { + clrEqn += clrStr; + clrStr = tabStr + sigName + operator["_CLR"]; + if (clrEqn.indexOf(operator["ENDLN"]) == -1) + clrEqn += operator["ENDLN"]; + if (gblrst[signal]) clrEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"]; + } + + preStr = retSet(signal); + if (eqnType && !isOneLiteral(preStr)){ + preEqn = preStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + preEqn += operator["ENDLN"]; + preStr = updateName(sigName, operator["_PRE"]); + } + else if (!eqnType && preStr) { + preEqn += preStr; + preStr = tabStr + sigName + operator["_PRE"]; + if (preEqn.indexOf(operator["ENDLN"]) == -1) + preEqn += operator["ENDLN"]; + if (gblset[signal]) preEqn += tabStr + operator["COMMENT"] + " " + operator["GSR_COM"]; + } + + if (!is9500()) { + ceStr = retCE(signal); + if (eqnType && !isOneLiteral(ceStr)){ + ceEqn = ceStr; + if (cEqn.indexOf(operator["ENDLN"]) == -1) + ceEqn += operator["ENDLN"]; + ceStr = updateName(sigName, operator["_CE"]); + } + else if (!eqnType && ceStr) { + ceEqn += ceStr; + ceStr = tabStr + sigName + operator["_CE"]; + if (ceEqn.indexOf(operator["ENDLN"]) == -1) + ceEqn += operator["ENDLN"]; + } + } + + if (eqnType && gbltrst[signal]) oeEqn = retTrst(signal); + else if (!eqnType && (trst[signal] || gbltrst[signal])) oeEqn = retTrst(signal); + + var newline = false; + if ((type == "") && (clrStr == "")) { + str += operator["ASSIGN"] + qStr + " " + operator["EQUAL"]; + if (dOneLit) str += dStr; + else str += dEqn.substring(dEqn.indexOf(operator["EQUAL"])+2); + if (oeEqn != "") { + var oeStr = updateName(sigName, operator["_OE"]); + if (eqnType == 1) { + str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr + + operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] + + operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"]; + } + else if (eqnType == 2) { + str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + + oeStr + operator["OE_WHEN"] + qStr + + operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"]; + } + str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + } + else { + if (eqnType == 1) { + str += type + "_" + removePar(retSigName(signal)) + + ": " + type + " " + operator["START_EQN"] + + qStr + ", " + dStr + ", " + cStr + ", " + + clrStr + ", " + preStr; + if (!is9500() && (type != operator["LD"])) str += ", " + ceStr; + str += operator["END_EQN"] + operator["ENDLN"]; + newline = true; + } + else if (eqnType == 2) { + str += type + " " + + type + "_" + removePar(retSigName(signal)) + + operator["START_EQN"] + + qStr + ", " + dStr + ", " + cStr + ", " + + clrStr + ", " + preStr; + if (!is9500() && (type != operator["LD"])) str += ", " + ceStr; + str += operator["END_EQN"] + operator["ENDLN"]; + newline = true; + } + + if (dEqn != "") { + if (newline) str += nlStr; + if (inregStr) str += inregStr; + str += operator["ASSIGN"] + dEqn; + } + + if (cEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + cStr + " " + operator["EQUAL"] + " " + cEqn; + } + + if (clrEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + clrStr + " " + operator["EQUAL"] + " " + clrEqn; + } + + + if (preEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + preStr + " " + operator["EQUAL"] + " " + preEqn; + } + + if (ceEqn != "") { + if (newline || !eqnType) str += nlStr; + str += operator["ASSIGN"] + ceStr + " " + operator["EQUAL"] + " " + ceEqn; + } + + if (oeEqn != "") { + if (eqnType == 1) { + // var oeStr = updateName(sigName, operator["_OE"]); + var oeStr = sigName; + str += nlStr + sigName + operator["OE_START"] + qStr + operator["OE_WHEN"] + oeStr + + operator["OE_EQUAL"] + operator["B1"] + operator["OE_ELSE"] + + operator["OE_EQUAL"] + operator["BZ"] + operator["ENDLN"]; + // str += nlStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + else if (eqnType == 2) { + // var oeStr = updateName(sigName, operator["_OE"]); + var oeStr = sigName; + str += nlStr + operator["ASSIGN"] + sigName + operator["OE_START"] + oeStr + operator["OE_WHEN"] + qStr + + operator["OE_ELSE"] + operator["BZ"] + operator["ENDLN"]; + // str += nlStr + operator["ASSIGN"] + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + else { + var oeStr = sigName + operator["_OE"]; + if (gbltrst[signal]) + oeEqn += tabStr + operator["COMMENT"] + " " + operator["GTS_COM"]; + str += nlStr + tabStr + oeStr + " " + operator["EQUAL"] + " " + oeEqn; + } + } + } + + if (iostyle[signal] && iostyle[signal].indexOf("OD")) { + if (str.indexOf("//") == -1) + str += tabStr + operator["COMMENT"] + " " + operator["OD_COM"]; + } + + return str; +} + +function retFamily() { + var family = "xc9500"; + if (device.indexOf("XC2C") != -1) { + if (device.indexOf("S") != -1) family = "cr2s"; + else family = "xbr"; + } + else if (device.indexOf("XCR3") != -1) family = "xpla3"; + else { + if (device.indexOf("XL") != -1) family = "xc9500xl"; + if (device.indexOf("XV") != -1) family = "xc9500xv"; + } + + return family; +} + +function retDesign() { return design; } + +function getPterm(pt, type) { + if (type) return type + " = " + retPterm(pt); + return "PT" + pt.substring(pt.indexOf('_')+1,pt.length) + " = " + retPterm(pt); +} + +function getPRLDName(prld) { + if (eqnType != 0) return prld; + else if (prld == "VCC") return "S"; + return "R"; +} + +function retFbnand(signal) { + var str = operator["COMMENT"] + spcStr + "Foldback NAND"; + str += nlStr + retSigName(signal) + spcStr + operator["EQUAL"] + spcStr; + for (i=0; i0) str += nlTabStr + operator["OR"] + spcStr; + str += retPterm(fbnand[signal][i]); + } + + return str; +} + +function getEqn(signal) { return retEqn(signal); } + +function retUimPterm(pt) { + var str = ""; + if (!uimPterms[pt]) return pt; + for (p=0; p0) str += spcStr + operator["AND"] + spcStr; + var sig = uimPterms[pt][p]; + if (sig.indexOf("/") != -1) sig = sig.substring(1, sig.length); + + str += retSigName(sig); + } + return str; +} + +function retUimEqn(signal) { + var str = operator["COMMENT"] + spcStr + "FC Node" + nlStr; + var neg = 0; + if (uimSigNegs[s] == "ON") str += operator["NOT"]; + str += retSigName(signal) + spcStr + operator["EQUAL"]; + str += retUimPterm(signal) + ";"; + + return str; +} + +function retLegend(url) { + var str = ""; + if (!eqnType && !isXC95()) { + str = "Legend: " + "<" + "signame" + ">" + ".COMB = combinational node mapped to "; + str += "the same physical macrocell as the FastInput \"signal\" (not logically related)"; + } + else if (eqnType) { + str = "Register Legend:"; + if (is9500()) { + str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE);"; + str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE);"; + str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; + } + else if (retFamily() == "xbr") { + str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FDDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FTDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; + } + else { + str += nlTabStr + "FDCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "FTCPE (Q,D,C,CLR,PRE,CE);"; + str += nlTabStr + "LDCP (Q,D,G,CLR,PRE);"; + } + } + return str; +} + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/equations.gif b/sterminator/XC9572XL/STERMINATOR_html/fit/equations.gif new file mode 100644 index 0000000000000000000000000000000000000000..d81602dcda8c50e3a304aa4aa7320bba1e499b88 GIT binary patch literal 20290 zcmX7OWl$T=*L8{&cef(J-Mz&jxCM775Q-OXakn7FT>}&kQlPlILvSlzC@lpld4B)* z-48oEvomMzJ?Gq+y*pP8q$(+4*9jIxa5hx%M07Qa;NH`FQ`Y$>l3JgTSfhg4f!UTXp05}MM0s#RaAQ%LM zgMcUy2mk_sK_EB?gaSbUASf6Fg@d3d5DWlRQb zL!l@r3;>0Jp)fcUhJqphPy`r?fI|@|C=vigf}uz_6p8weMJNgkMZuvc)c@!NfMEbQ z41j_G0WcsK286?aC>RI;1A$>6I1Ge>K>;u*7zTyIpePs&0E2;HFgOf`f*}Af1Q>>Z z!w@JK5&%PjVMsU(iTY0&7zzwS!C@%W|0Du{5db&>fI0`1PFitfe|1$ z0)#?90SG7<0fi%=CI1-8a&p}8O7>R--QK?a`;QzVmKQp0#U=$Gk zp9B6A9t8rUK=A+6`cEVj6pVtx|6}$)LQya<3I_j=h5wRAA;2gE{J)6*3lxO}qmc0b z(EkHPp};5<{J#_P6UP6m0p9=Z|Emdk?Eh|Y=+&D`2cxjbxGg7|%ZB5KSv4Fv>$FFc zC`IhIYg<^y(-@T^>A6~glbP&><(74=PAb^|ezaV!%wsJ8^V=S+x=d%aBI>YKj09iT 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+ + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/equationsdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/equationsdoc.htm new file mode 100644 index 0000000..e335b77 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/equationsdoc.htm @@ -0,0 +1,53 @@ + + + + + + + + + + +Equations + + + + + + + + + + + + + + + + + + + + + + +

Equations

+ +

The Equations + page provides a list of equations organized by signal name.  You + can use the pulldown menu in the left-hand frame of the page to select + ABEL, VHDL, or Verilog as your language of display.

+ +

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Errors/Warnings

+ +

The Errors/Warnings + section of the report lists all of the error, warning, and information + messages generated by the fitter. By default, this section will display + the number of each kind of message you have and the full text of the messages, + but checkboxes at the top of the screen allow you to filter message details + as you choose.

+ +

Checking all + the boxes will give you a display like this:

+ +

+ +

Deselecting + the Warning box in this particular example would result in this less detailed + display:

+ +

+ + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/errs.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/errs.htm new file mode 100644 index 0000000..b0a7a8c --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/errs.htm @@ -0,0 +1,13 @@ + + + + + + +

Errors and Warnings

+There are 0 error(s), 1 warning(s), and 0 information.

[Warning]:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'STERMINATOR.ise'.
+ + +
+ + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/failtable.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/failtable.htm new file mode 100644 index 0000000..0d33122 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/failtable.htm @@ -0,0 +1,33 @@ + + + + + + +

Failure Table

+ + + + + + +
Signal NameFB1FB2FB3FB4
+
+ + + + + + + + + + + +
Legend:
ce - signal clock enable cannot be placed
clk - signal clock cannot be placed
fbi - insufficient function block inputs available to place signal
io - insufficient I/O pins available to place output
loc - signal cannot be placed in this FB because it is assigned to a different FB
mc - insufficient macrocells available to place signal
oe - signal output enable cannot be placed
pt - insufficient product terms available to place signal
sr - signal set/reset cannot be placed
unk - unknown reason for failure - Please contact Xilinx Support
+ +
+ + +
+ diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/failtable.js b/sterminator/XC9572XL/STERMINATOR_html/fit/failtable.js new file mode 100644 index 0000000..045081f --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/failtable.js @@ -0,0 +1 @@ +function showFailTable() { parent.leftnav.showFailTable(); } diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/failtabledoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/failtabledoc.htm new file mode 100644 index 0000000..c95037a --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/failtabledoc.htm @@ -0,0 +1,95 @@ + + + + + + + + + + + + + + + + Failure Table + + + + + + + + + + + +

+Failure Table

+The +Failure Table section provides a table listing all logic failing to be +placed as well as the cause for failure to fit for each individual Function +Block. The user can use this table to determine primary cause of +failure and try to correct it. +
+
The +Failure Table contains the following:  +
    +
  • +The +signal name 
    • +
+ +
Note: +Clicking on the signal name will open a new window with the equations for +that signal. 
+ +
    +
  • +A +column for each Function Block in device, with reason for failure to fit +for each FB
    • + +
  • +A +legend at the bottom listing all possible reasons for failure
    • +
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Function Blocks

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function BlockMacrocells Used/TotalFunction Block Inputs Used/TotalProduct Terms Used/TotalPins Used/Total
FB11 / 1854 / 5452 / 905 / 13
FB29 / 1814 / 5418 / 9013 / 13
FB318 / 1824 / 5444 / 908 / 14
FB40 / 180 / 540 / 9012 / 12
+ + +
+ + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbs.js b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs.js new file mode 100644 index 0000000..8e97ea6 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs.js @@ -0,0 +1,9 @@ +function showFBApplet(fb) { parent.leftnav.showAppletFB(fb); } +function showFB(fb) { parent.leftnav.showFB(fb); } +function showMC(mc) { parent.leftnav.showAppletMC(mc); } +function showPT(pterm, type) { parent.leftnav.showPterm(pterm, type); } +function showPin(pin) { parent.leftnav.showAppletPin(pin); } +function showEqn(sig) { parent.leftnav.showEqn(sig); } +function showFBDetail(fb) { parent.leftnav.showFB(fb); } +function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } +function showTop() { parent.leftnav.showTop(); } diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB1.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB1.htm new file mode 100644 index 0000000..dcc2872 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB1.htm @@ -0,0 +1,271 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
(unused)0 MC1  (b) 
(unused)0 MC2 8I/O 
(unused)0 MC3 12I/O 
(unused)0 MC4 13I/O 
(unused)0 MC5 9I/OI
(unused)0 MC6 10I/OI
(unused)0 MC7  (b) 
(unused)0 MC8 11I/OI
(unused)0 MC9 15I/O/GCK1GCK
(unused)0 MC10 18I/O(b)
(unused)0 MC11 16I/O/GCK2I
(unused)0 MC12 23I/O(b)
$OpTx$BIN_STEP$40952 10_1 10_2 10_3 10_4 10_5 11_1 11_2 11_3 11_4 11_5 12_1 12_2 12_3 12_4 12_5 13_1 13_2 13_3 13_4 13_5 14_1 14_2 14_3 14_4 14_5 15_1 15_2 15_3 15_4 15_5 16_1 16_2 16_3 16_4 16_5 17_1 17_2 17_3 17_4 17_5 18_1 18_2 18_3 18_4 18_5 8_1 8_2 9_1 9_2 9_3 9_4 9_5 +MC13STD (b)(b)
(unused)0 MC14 17I/O/GCK3(b)
(unused)0 MC15 19I/O(b)
(unused)0 MC16  (b)(b)
(unused)0 MC17 20I/OI
(unused)0 MC18  (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. A<10>
    2. +
  2. A<11>
    3. +
  3. A<12>
    4. +
  4. A<13>
    5. +
  5. A<14>
    6. +
  6. A<15>
    7. +
  7. A<16>
    8. +
  8. A<17>
    9. +
  9. A<18>
    10. +
  10. A<19>
    11. +
  11. A<20>
    12. +
  12. A<21>
    13. +
  13. A<22>
    14. +
  14. A<23>
    15. +
  15. A<24>
    16. +
  16. A<25>
    17. +
  17. A<28>
    18. +
  18. A<29>
    19. +
  19. A<2>
    20. +
  20. A<30>
    21. +
  21. A<31>
    22. +
  22. A<3>
    23. +
  23. A<4>
    24. +
  24. A<5>
    25. +
  25. A<6>
    26. +
  26. A<7>
    27. +
  27. A<8>
    28. +
  28. A<9>
    29. +
  29. FC<2>
    30. +
  30. NB<0>
    31. +
  31. NB<1>
    32. +
  32. NC<0>
    33. +
  33. NC<1>
    34. +
  34. NC<2>
    35. +
  35. NC<3>
    36. +
  36. NC<4>
    37. +
  37. NC<5>
    38. +
  38. NC<6>
    39. +
  39. NC<7>
    40. +
  40. NC<8>
    41. +
  41. NR<0>
    42. +
  42. NR<10>
    43. +
  43. NR<11>
    44. +
  44. NR<12>
    45. +
  45. NR<1>
    46. +
  46. NR<2>
    47. +
  47. NR<3>
    48. +
  48. NR<4>
    49. +
  49. NR<5>
    50. +
  50. NR<6>
    51. +
  51. NR<7>
    52. +
  52. NR<8>
    53. +
  53. NR<9>
    54. +
  54. STERM
    55. +
+ + + +
 + +
+ + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB2.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB2.htm new file mode 100644 index 0000000..311c5a4 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB2.htm @@ -0,0 +1,243 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
(unused)0 MC1  (b) 
nSTERM2 2_1 2_2 +MC2STD60I/OO
(unused)0 MC3 58I/OI
(unused)0 MC4 59I/OI
(unused)0 MC5 61I/OI
(unused)0 MC6 62I/OI
(unused)0 MC7  (b) 
(unused)0 MC8 63I/OI
(unused)0 MC9 64I/O/GSRI
(unused)0 MC10 1I/OI
NR<9>2 11_1 11_2 +MC11STD2I/O/GTS2I
NR<1>2 12_1 12_2 +MC12STD4I/OI
NR<12>2 13_1 13_2 +MC13STD (b)(b)
NR<11>2 14_1 14_2 +MC14STD5I/O/GTS1I
NR<10>2 15_1 15_2 +MC15STD6I/OI
NR<0>2 16_1 16_2 +MC16STD (b)(b)
NB<1>2 17_1 17_2 +MC17STD7I/OI
NB<0>2 18_1 18_2 +MC18STD (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. $OpTx$BIN_STEP$409
    2. +
  2. A<11>
    3. +
  3. A<12>
    4. +
  4. A<20>
    5. +
  5. A<21>
    6. +
  6. A<22>
    7. +
  7. A<23>
    8. +
  8. A<24>
    9. +
  9. A<25>
    10. +
  10. CMD<0>
    11. +
  11. CMD<1>
    12. +
  12. FC<0>
    13. +
  13. NA
    14. +
  14. STERM
    15. +
+ + + +
+ +    + +
 + +
+ + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB3.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB3.htm new file mode 100644 index 0000000..f7f6ccd --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB3.htm @@ -0,0 +1,262 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
NR<8>2 1_1 1_2 +MC1STD (b)(b)
nFPUCS2 2_1 2_2 +MC2STD22I/OO
NR<7>2 3_1 3_2 +MC3STD31I/OI
NR<6>2 4_1 4_2 +MC4STD32I/O(b)
NR<5>2 5_1 5_2 +MC5STD24I/O(b)
NR<4>2 6_1 6_2 +MC6STD34I/OI
NR<3>2 7_1 7_2 +MC7STD (b)(b)
NR<2>2 8_1 8_2 +MC8STD25I/O(b)
NC<0>2 9_1 9_2 +MC9STD27I/O(b)
NA2 10_1 10_2 +MC10STD39I/OI
NC<8>3 11_1 11_2 11_3 +MC11STD33I/O(b)
NC<7>3 12_1 12_2 12_3 +MC12STD40I/OI
NC<6>3 13_1 13_2 13_3 +MC13STD (b)(b)
NC<5>3 14_1 14_2 14_3 +MC14STD35I/OI
NC<4>3 15_1 15_2 15_3 +MC15STD36I/OI
NC<3>3 16_1 16_2 16_3 +MC16STD42I/OI
NC<2>3 17_1 17_2 17_3 +MC17STD38I/O(b)
NC<1>3 18_1 18_2 18_3 +MC18STD (b)(b)
+
+
Signals Used By Logic in Function Block
    +
  1. A<10>
    2. +
  2. A<13>
    3. +
  3. A<14>
    4. +
  4. A<15>
    5. +
  5. A<16>
    6. +
  6. A<17>
    7. +
  7. A<18>
    8. +
  8. A<19>
    9. +
  9. A<2>
    10. +
  10. A<3>
    11. +
  11. A<4>
    12. +
  12. A<5>
    13. +
  13. A<6>
    14. +
  14. A<7>
    15. +
  15. A<8>
    16. +
  16. A<9>
    17. +
  17. CLKdat
    18. +
  18. CMD<0>
    19. +
  19. CMD<1>
    20. +
  20. FC<0>
    21. +
  21. FC<1>
    22. +
  22. FC<2>
    23. +
  23. NA
    24. +
  24. nAS
    25. +
+ + + +
+ +    + +
 + +
+ + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB4.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB4.htm new file mode 100644 index 0000000..4a9b2b6 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FB4.htm @@ -0,0 +1,215 @@ + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal NameTotal Product TermsProduct TermsLocationPower ModePin NumberPinTypePin Use
(unused)0 MC1  (b) 
(unused)0 MC2 43I/OI
(unused)0 MC3 46I/OI
(unused)0 MC4 47I/OI
(unused)0 MC5 44I/OI
(unused)0 MC6 49I/OI
(unused)0 MC7  (b) 
(unused)0 MC8 45I/OI
(unused)0 MC9  (b) 
(unused)0 MC10 51I/OI
(unused)0 MC11 48I/OI
(unused)0 MC12 52I/OI
(unused)0 MC13  (b) 
(unused)0 MC14 50I/OI
(unused)0 MC15 56I/OI
(unused)0 MC16  (b) 
(unused)0 MC17 57I/OI
(unused)0 MC18  (b) 
+
+
Signals Used By Logic in Function Block
    + + + +
    		 + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FBdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FBdoc.htm new file mode 100644 index 0000000..36e7c96 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbs_FBdoc.htm @@ -0,0 +1,310 @@ + + + + + + + + + + + + + + + Function Block Specifics + + + + + + + + + + + +

    +Function Block Specifics

    + +
    To access specific details for a particular function +block, click on that function block in either the Mapped +Logic, Mapped Inputs, or Function +Blocks sections of the fitter report. The +function block details page displays a table of details about the particular +function block you selected, a view button you can click to show a graphical +display of the function block, and a pulldown menu you can use to select +other function blocks to see.
    + + +

    The Table + +

    The View +

    + +

    +The Table

    +The +table at the top of the function block details page provides the following +information about the function block: +
      +
    • +The +signal name 
      • +
    + +
    Note: +Clicking on a signal name will open a new window with the equations for +that signal. 
    + +
      +
    • +The +total product terms used 
      • + +
    • + A +list of product terms
      • +
    + +
    Note: +Clicking on a product +term will open a new window with the equations for that term. 
    + +
      +
    • +The +macrocell number in which the function block is located
      • +
    + +
    Note: +Clicking on the underscored macrocell number will provide a graphical display +of the macrocell that looks like this:
    + + +

    +. +

      +
    • +The +power mode
      • + +
    • +The +pin number - an asterisk "*" indicates a user assignment
      • +
    + +
      +
      Note: +Clicking on the underscored pin number will provide the pin layout diagram +for the highlighted pin. Rolling +your mouse over the colored pin will pop up a tooltip with the signal name +assigned to the pin, the I/O standard, the +I/O style, the slew rate, and/or any constraints assigned to the pin:
      +
    + +
    +
    + +
      +
    • +The +pin type
      • + +
    • +The +pin use 
      • + +
    • +XPLA3 +only - The GCK (Global Clock Signal) mapping 
      • +
    + +
    Note: +Moving your mouse cursor over an "I" in the Pin Use column will display +that input signal as a tooltip.
    + +
    +
    XBR +only - Below the resource table there is another table listing the +Function Block Control Term usage, the product term mapped to the +control term is listed. Clicking on the product term will bring up a pop-up +window displaying that product term. +
    +
  1. +CTC - control term clock
    2. + +
  2. +CTR - control term reset
    3. + +
  3. +CTS - control term set
    4. + +
  4. +CTE - control term output enable
    5. +
    + +


    Below +this table you will find a list of signals used by logic in the function +block you are viewing. The +list displays output signals as links. Clicking +on an output signal link will open a new window showing the equations for +that signal. +
    + +

    Note:There +is also a  +button +below the table. Click +this button to open a new window describing all of the acronyms used in +the function block table. You +can select either brief descriptions or more detailed descriptions by clicking +the "Verbose" button at the top of the window. +

    +The View

    + +
    When you click on the  +button +above the table, a new window will open with a graphical display of the +function block you are examining. The +pins are all color-coded: input pins are green, output pins are blue, and +clocks are magenta:
    + + +

    + + +

    Right-click anywhere within the window to pull up a menu +that allows you to zoom in or out for easier viewing.  + +

    This menu also allows you choose to see all of the input +connections, all of the output connections, or both at once. Like +the pins, the signals are color-coded: inputs are red, outputs are yellow, +and macrocell connections are aqua: + +

    + + +

    To examine the signals of single pins, simply click the +pin whose signals you wish to see. To +examine multiple pins without having to see everything at once, hold down +the control key while you click the pins you want to view. + +

    To view the signals for individual macrocells: +

      +
      Click the inside edge of the macrocell to display its +macrocell connections and inputs.
      + + +

      Click the outer edge to display its output signals + +

      Click in the center to display everything + +

      Double click in the center to open a new window with a +detailed macrocell diagram

    + +
    + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/fbsdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/fbsdoc.htm new file mode 100644 index 0000000..04a25ff --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/fbsdoc.htm @@ -0,0 +1,103 @@ + + + + + + + + + + +Function Blocks + + + + + + + + + + + + + + + + + + + + + + + + +

    Function Blocks

    + +The Function + Blocks page provides a summary of all function blocks' resources. Clicking + on one of the function blocks in the summary table will display the specific details for that function block.   + +
      + + +
    The summary table + contains the following:   + +
      + +
    • The + function block
      • + +
    • The + number of macrocell used
      • + +
    • The + number of function block inputs used
      • + +
    • The + number of product terms used
      • + +
    • The + pins used
      • + +
    • The + local control terms used
      • + +
    • The + number of foldback NANDs used (CoolRunner only)
      • +
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    +This file is currently being generated. Please recheck the link after some +time for this report data.
    +
    + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/header.gif b/sterminator/XC9572XL/STERMINATOR_html/fit/header.gif new file mode 100644 index 0000000000000000000000000000000000000000..526171bdf217d82a99bbd6cfacec0fb44ffd7582 GIT binary patch literal 7878 zcmd6o_d6Tj`~U6PS8G#3?UAaQwUyYhWACl@CQ_?L5Mn0w9DG z2_1a;{{9u;bDis4_x;0pJn#E?&bf}Zu9lp<^Cqzn5rOD`LSi zR#sPVb2#h-c3^OztGlbYr5RI;DJetV-V#=3d~g%U6FjE55lJ}5ZOpk2wA-9~3Bir} z5RQ<9BQ)Wt=Y2XD+k@JluuGd3q5T~|hJ z@Jp_^!GEz2VJ8H?8nQCsbMhr}V=jb%PsFcAo_t9p;E}f{=#3@hK=(i0E?m3BO20g= zTYh5{v@!_7b%UCVp&W5RV~!sqs1wM&sJqyHrS1&JpgksEW!lP@JF zJI#cnF2V_Jpoj-sD>6_ff@_h$)=I2&%i~()HwHo2f1b31SNb6vqc$6(uGp4;*nbf8 z$rlU(-#pO%&(Z;G84tEf1lK5mt&+es{@Vyz=?1TKLkRdT!V&hCuz~%Dt^Ie(CnZH_ z0)F83pZV>s_!(qZ4)~UU#}Y=a1S8vYEvj5l4?*4_5akzS6w$(E?GADg5)bTzpxGp2tTVrEY%rts)Yf~ zf#%v)9p0Z0C#fxjoCcD<0rL=y9foWY*01xjKlTLfOo#nOe6M>Q%=9%EC41s9@Iv|P zg@zUV)@ZVch}IsWt`faTvWo9PHzGh5ooRGM44M89XYb};B;K|gDgS} z{J5ZYd_lZ#SqT3xiOr>RcK?G*vw_ySM~F>0yEkU9j~!U>?W>UAi;->}KOe3n4*z~~ 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b/sterminator/XC9572XL/STERMINATOR_html/fit/index.htm @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/inputleft.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/inputleft.htm new file mode 100644 index 0000000..83dc5e0 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/inputleft.htm @@ -0,0 +1,14 @@ + + + + + +

    Unmapped Inputs

    + + + +
    Signal NameUser Assignment
    + + +
    + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/inputleft.js b/sterminator/XC9572XL/STERMINATOR_html/fit/inputleft.js new file mode 100644 index 0000000..63fe42f --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/inputleft.js @@ -0,0 +1 @@ +function showInputLeft() { parent.leftnav.showInputLeft(); } diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/inputleftdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/inputleftdoc.htm new file mode 100644 index 0000000..0cb5adb --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/inputleftdoc.htm @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + Mapped Logic + + + + + + + + + + + +

    +Unmapped Inputs

    +The +Unmapped Inputs section provides a table listing all inputs that failed +to fit into the specified device. The page will appear in your browser +sorted by Signal Name.  +
    +
    The +Unmapped Inputs table contains the following:  +
      +
    • +The +input signal name 
      • +
    + +
      +
    • +The +Pin/FB Assignment specified by the user.
      • +
    + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/leftnav.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/leftnav.htm new file mode 100644 index 0000000..99d935f --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/leftnav.htm @@ -0,0 +1,63 @@ + + + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Fitter Report
     Summary
     Errors/Warnings
     Logic
     Inputs
     Function Blocks
     Equations
     Pin List
     Compiler Options
     Text Report
     Help
    +


    + + + + + +
    Equation Display Style
     
    +
      +
    + +
    + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/leftnav.js b/sterminator/XC9572XL/STERMINATOR_html/fit/leftnav.js new file mode 100644 index 0000000..bbc0028 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/leftnav.js @@ -0,0 +1,180 @@ +var noAppletOnClicked = 1; +var appletMsg = ""; +var waitWin; +var oldIn = oldOut = oldGbl = oldIsp = oldVcc = oldGnd = oldProhibit = oldUnuse = oldNc = 1; +var oldInfo = oldWarn = oldError = 1; +var verbose = 0; +var dispPage, mapLogPage, mapInPage, unLogPage, unInPage; +var javaPermission = 0; +var abelEqn = vhdlEqn = verEqn = ""; + +function IsNS() { + return ((navigator.appName.indexOf("Netscape") >= 0) && + (parseFloat(navigator.appVersion) >= 4)) ? true : false; +} + +function openWait() { + waitWin = window.open("wait.htm", "wait", + "toolbar=no,location=no,"+ + "directories=no,status=no,menubar=no,scrollbars=no,"+ + "resizable=no,width=300,height=50" ); +} + +function closeWait() { if (waitWin) waitWin.close(); } + +function popHTML(name, str) { + document.options.htmlStr.value = str; + if (name.indexOf(":") > -1) + name = name.substring(0,name.indexOf(":")) + "_COLON_" + + name.substring(name.indexOf(":")+1,name.length); + if (name.indexOf(".") > -1) + name = name.substring(0,name.indexOf(".")) + "_DOT_" + + name.substring(name.indexOf(".")+1,name.length); + var win = window.open("result.htm", "win_"+name, + "toolbar=no,location=no,"+ + "directories=no,status=no,menubar=no,scrollbars=yes,"+ + "resizable=yes,width=300,height=200" ); + win.focus(); +} + +function setAppletPermission() { appletPermission = 1; } +function getAppletPermission() { return( appletPermission); } +function getAppletMsg() { return(appletMsg); } +function setAppletMsg(msg) { appletMsg = msg; } + + +function showHTML(page, html) { + + dispPage = html; + document.options.currPage.value = page; + parent.content.location.href = html; +} + +function showTop() { showHTML(document.options.currPage.value, dispPage); } + +function setVerbose(value) { verbose = value; } + +function showLegend(url, w, h) { + if (verbose == 1) { + url = url.substring(0,name.indexOf(".htm")) + "V.htm"; + } + var win = window.open(url, 'win', + 'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h); + win.focus(); +} + +function showSummary() { showHTML("summary", "summary.htm"); } +function showOptions() { showHTML("options", "options.htm"); } +function showFBSum() { showHTML("fbs", "fbs.htm"); } +function showFB(fb) { showHTML("fbs_FB", "fbs_"+fb+".htm"); } +function showPinOut() { showHTML("pins", "pins.htm"); } +function showError() { showHTML("errors", "errs.htm"); } +function showFailTable() { showHTML("failtable", "failtable.htm"); } + +function showEqnAll() { + openWait(); + parent.eqns.setOper(currEqnType); + if (currEqnType == defEqnType) showHTML("equations", "defeqns.htm"); + else if (currEqnType == 0) { + if (abelEqn == "") abelEqn = parent.eqns.getEqnList(); + document.options.htmlStr.value = abelEqn; + showHTML("equations", "equations.htm"); + } + else if (currEqnType == 1) { + if (vhdlEqn == "") vhdlEqn = parent.eqns.getEqnList(); + document.options.htmlStr.value = vhdlEqn; + showHTML("equations", "equations.htm"); + } + else { + if (verEqn == "") verEqn = parent.eqns.getEqnList(); + document.options.htmlStr.value = verEqn; + showHTML("equations", "equations.htm"); + } + closeWait(); +} + +function showEqn(sig) { + popHTML(sig, parent.eqns.getEqn(sig)); +} + +function showPterm(pterm, type) { + popHTML(pterm, parent.eqns.getPterm(pterm, type)); +} + +function showAscii() { showHTML("ascii", "ascii.htm"); } + +function showHelp() { + var helpDoc = document.options.currPage.value + "doc.htm"; + popWin(helpDoc); +} + +function getMapParam(type) { + var paramStr = ""; + switch(type) { + case 1: paramStr += "10"; break; + case 2: paramStr += "01"; break; + case 3: paramStr += "11"; break; + case 4: paramStr += "02"; break; + case 5: paramStr += "12"; break; + default: paramStr += "00"; + } + + return paramStr; +} + +function showMappedLogics(type) { + showHTML("maplogic", "maplogic_" + getMapParam(type) + ".htm"); +} + +function showMappedInputs(type) { + showHTML("mapinput", "mapinput_" + getMapParam(type) + ".htm"); +} + +function showUnMappedLogics(type) { + showHTML("unmaplogic", "unmaplogic_" + getMapParam(type) + ".htm"); +} + +function showLogicLeft() { showHTML("logicleft", "logicleft.htm"); } + +function showUnMappedInputs(type) { + showHTML("unmapinput", "unmapinput_" + getMapParam(type) + ".htm"); +} + +function showInputLeft() { showHTML("inputleft", "inputleft.htm"); } + +function doEqnFormat() { + var type = document.options.eqnType.options[document.options.eqnType.options.selectedIndex].value; + currEqnType = type; + parent.eqns.setOper(currEqnType); + if (document.options.currPage.value == "equations") showEqnAll(); +} + +function showNoAppletAlert() { + window.alert("No Applet supported for this session!!!"); +} + +function showAppletMC(mc) { + if (parent.applets) parent.applets.showAppletGraphicMC(mc); + else showNoAppletAlert(); +} + +function showAppletFB(fb) { + if (parent.applets) parent.applets.showAppletGraphicFB(fb); + else showNoAppletAlert(); +} + +function showAppletPin(pin) { + if (parent.applets) parent.applets.showAppletGraphicPin(pin); + else showNoAppletAlert(); +} + +function printAppletPkg() { + if (parent.applets) parent.applets.printAppletPkg(); + else showNoAppletAlert(); +} + +function popWin(url) { + var win = window.open(url, 'win', + 'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600'); + win.focus(); +} diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/legend.gif b/sterminator/XC9572XL/STERMINATOR_html/fit/legend.gif new file mode 100644 index 0000000000000000000000000000000000000000..0aad0ebb2b70d602a5de51f334db320963aecd00 GIT binary patch literal 1213 zcmZ?wbhEHbbYYNT_|5t{|x`Z6p#k8fItW26Hs1o;P}rV&LQKmVZp&>4q>gB2!Vr4tUMwf zN5lgenL0(4!=`X-R6f=(Z(g>hLQvVYk6pkb#GqiQN1v*Xk(@mQx>{oX4}SYL3(-ZLg{PbIW?Vg46wGYMq|u zn=Q81XAM_fo9K>9t7CUNzkhZ2b*P^AE-z+oIhh>~gZomd%jWJ1On$UhL9zRb_P11* znKj1MwUvgepRad#DVKI<+KOA3ob}7Mbbc=OKeb3PJ*+0m`2O{T|9S-(SBu}@-`C76 zueZmd@CMIh?f7$hc7A?-Qr2nyI~g73jf(3Zb>I2=Ic;6U$-YHbW*xBl_EBGT_4HM7 zDan_3PFe4ftKN9-%a)sy@0}OjT>g{$!uH$FYPnCuqK#L!oNvsCY?&F5Cd$5`p|sNF zl26#yuYo?2o7^t9mit!7<*xboB_TI!YD7?2OlO3A=&D$@L|^f>Gs1hmTShF-5!z|7 zAf$k`Q@qE8OH;+&?%ejdxjtq)r^krs6&#on5|;UNYDC(~r_(~8iHRg8w0TODrc9C) HV6X-NY{uvO literal 0 HcmV?d00001 diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/legend.jpg b/sterminator/XC9572XL/STERMINATOR_html/fit/legend.jpg new file mode 100644 index 0000000000000000000000000000000000000000..1d04af024b10f70a03faa699fb2da92df25a3ced GIT binary patch literal 1256 zcmex=9X@jO*zpr5PhGlvPb?HxGHT=yahkYr<3UbkKb$@|Xn~>>0l3-%LJOC;5^8;98;2VV88*>51JHKa(Qear>Bm)mQ%? zq4QY(Gb~_T|M!Fap&jRMT>j@#*886!M)*I2TJL*7|q# z`G4m&UWt-e_v}+j#r>Sb*=1b9pC%uaJeqZQQH{W?XP<7#x*yu)pUi!}QY!vH)IF8l zb)OiDy4HT0RKWP)`rJRpf9KiwK3wa6ApF*{g^TX}XGpkVyY!3Uy}L^?4hL7?c-o=h zZ}G5c%5)A1ZGqnocF7+;KRDj|$5(9k!^$mlogLcjInFORydtZt==RL?f49sFJNY<@ zPV7kQII+;{lV1o!t*Tz<2Pe(9x=*jvXvOi`|`FD6KAU@8ln+!F=gI!^5x&@qZ0s`@bLf&%pKJ z{w-sNi+`-wWp0~g+9Ed5MDLt(0JqHgs9*E;<@{a!pW#UcP|NG){|s-oFn*qX`2MZr zBlkEzOl@yBnX7dB&9{j<)whawo{%{Cv)=3ee}=XrAFuyqT3i4A=YNJr8H*bDf8_Yf z)?d)N{_j7-{C{fwsN60M26Qdxd<-LY)=T}nD0RGho$fo+UM}%ztf_8&PgW{CUVr+n Js|e%&n*i?m6>0zg literal 0 HcmV?d00001 diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXC95.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXC95.htm new file mode 100644 index 0000000..e253a0b --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXC95.htm @@ -0,0 +1,2 @@ +
    +
    diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXbr.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXbr.htm new file mode 100644 index 0000000..d256e25 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXbr.htm @@ -0,0 +1,16 @@ +
    +I/O Style - OD    - OpenDrain
+          - PU    - Pullup
+          - PN    - Pulldown
+          - KPR   - Keeper
+          - S     - SchmittTrigger
+          - DG    - DataGate
+Reg Use   - LATCH - Transparent latch
+          - DFF   - D-flip-flop
+          - DEFF  - D-flip-flop with clock enable
+          - TFF   - T-flip-flop
+          - TDFF  - Dual-edge-triggered T-flip-flop
+          - DDFF  - Dual-edge-triggered flip-flop
+          - DDEFF - Dual-edge-triggered flip-flop with clock enable
+          /S (after any above flop/latch type) indicates initial state is Set
+
    diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXpla3.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXpla3.htm new file mode 100644 index 0000000..c0e6f4a --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logic_legXpla3.htm @@ -0,0 +1,3 @@ +
    +Legend: PU  - Pull Up
+
    diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logicleft.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logicleft.htm new file mode 100644 index 0000000..5da8011 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logicleft.htm @@ -0,0 +1,16 @@ + + + + + +

    Unmapped Logic

    + + + + + +
    Signal NameTotal PtermsTotal InputsUser Assignment
    + + +
    + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logicleft.js b/sterminator/XC9572XL/STERMINATOR_html/fit/logicleft.js new file mode 100644 index 0000000..2fa4142 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logicleft.js @@ -0,0 +1 @@ +function showLogicLeft() { parent.leftnav.showLogicLeft(); } diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logicleftdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logicleftdoc.htm new file mode 100644 index 0000000..3537167 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logicleftdoc.htm @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + Mapped Logic + + + + + + + + + + + +

    +Unmapped Logic

    +The +Unmapped Logic section provides a table listing all logic that failed to +fit into the specified device. The page will appear in your browser sorted +by Signal Name.  +
    +
    The +Mapped Logic table contains the following:  +
      +
    • +The +signal name 
      • +
    + +
    Note: +Clicking on the signal name will open a new window with the equations for +that signal. 
    + +
      +
    • +The +total number of product terms 
      • + +
    • +The +total number of inputs 
      • + +
    • +The +I/O standard where appropriate
      • + +
    • +The +Pin/FB Assignment specified by the user.
      • +
    + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logiclegend.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logiclegend.htm new file mode 100644 index 0000000..7033b9e --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logiclegend.htm @@ -0,0 +1,106 @@ + + + + + + + +

    Legends

    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    AcronymBrief Description
     * User Assigned
     (b) Buried macrocell
     FB# Function Block number
     GCK# Global Clock number
     GTS# Global Output Enable number
     GSR Global Set/Reset
     I Input
     I/O Input/Output
     Latch Transparent latch
     LOW Low Power Mode
     MC# Macrocell number
     O Output
     OD Open Drain
     PU Pullup
     /S After any flop/latch type indicates initial state is Set
     STD Standard Power Mode
     TCK Test clock
     TDI Test data input
     TDO Test data output
     TFF Toggle Flip-Flop
     TMS Test mode select
    + + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/logiclegendV.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/logiclegendV.htm new file mode 100644 index 0000000..e1813d1 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/logiclegendV.htm @@ -0,0 +1,106 @@ + + + + + + + +

    Legends

    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    AcronymVerbose Description
     * User Assigned
     (b) Buried macrocell
     FB# Function Block number
     GCK# Global Clock number
     GTS# Global Output Enable number
     GSR Global Set/Reset
     I Input
     I/O Input/Output
     Latch Transparent latch
     LOW Low Power Mode
     MC# Macrocell number
     O Output
     OD Open Drain
     PU Pullup
     /S After any flop/latch type indicates initial state is Set
     STD Standard Power Mode
     TCK One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.
     TDI One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.
     TDO One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.
     TFF Toggle Flip-Flop
     TMS One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.
    + + +
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zfCP2qY*bu`1w4#1?~M&qRKc697>Yi2MOcU{!AF9xgQ pHu?wNT8*0;r9K-rhWEExe{eL*LO$C5B=XVjV9+eL#m9Xl^ncXyUyA?$ literal 0 HcmV?d00001 diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_00.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_00.htm new file mode 100644 index 0000000..6b61238 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_00.htm @@ -0,0 +1,320 @@ + + + + + + +

    Inputs

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameFunction BlockMacrocellPin NumberPin TypePin Use
    A<10>FB4MC1757I/OI
    A<11>FB2MC112I/O/GTS2I
    A<12>FB2MC964I/O/GSRI
    A<13>FB4MC544I/OI
    A<14>FB4MC1051I/OI
    A<15>FB2MC124I/OI
    A<16>FB3MC634I/OI
    A<17>FB2MC358I/OI
    A<18>FB4MC649I/OI
    A<19>FB3MC1642I/OI
    A<20>FB3MC1536I/OI
    A<21>FB4MC1450I/OI
    A<22>FB3MC1435I/OI
    A<23>FB4MC1148I/OI
    A<24>FB4MC1252I/OI
    A<25>FB1MC610I/OI
    A<28>FB4MC346I/OI
    A<29>FB2MC561I/OI
    A<2>FB3MC1240I/OI
    A<30>FB2MC662I/OI
    A<31>FB2MC101I/OI
    A<3>FB4MC243I/OI
    A<4>FB1MC1720I/OI
    A<5>FB2MC863I/OI
    A<6>FB4MC447I/OI
    A<7>FB2MC177I/OI
    A<8>FB1MC59I/OI
    A<9>FB1MC811I/OI
    CLKFB1MC915I/O/GCK1GCK
    CLKdatFB2MC145I/O/GTS1I
    CMD<0>FB3MC1039I/OI
    CMD<1>FB1MC1116I/O/GCK2I
    FC<0>FB3MC331I/OI
    FC<1>FB4MC845I/OI
    FC<2>FB4MC1556I/OI
    STERMFB2MC459I/OI
    nASFB2MC156I/OI
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_01.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_01.htm new file mode 100644 index 0000000..e659eee --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_01.htm @@ -0,0 +1,320 @@ + + + + + + +

    Inputs

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameFunction BlockMacrocellPin NumberPin TypePin Use
    A<8>FB1MC59I/OI
    A<25>FB1MC610I/OI
    A<9>FB1MC811I/OI
    CLKFB1MC915I/O/GCK1GCK
    CMD<1>FB1MC1116I/O/GCK2I
    A<4>FB1MC1720I/OI
    A<17>FB2MC358I/OI
    STERMFB2MC459I/OI
    A<29>FB2MC561I/OI
    A<30>FB2MC662I/OI
    A<5>FB2MC863I/OI
    A<12>FB2MC964I/O/GSRI
    A<31>FB2MC101I/OI
    A<11>FB2MC112I/O/GTS2I
    A<15>FB2MC124I/OI
    CLKdatFB2MC145I/O/GTS1I
    nASFB2MC156I/OI
    A<7>FB2MC177I/OI
    FC<0>FB3MC331I/OI
    A<16>FB3MC634I/OI
    CMD<0>FB3MC1039I/OI
    A<2>FB3MC1240I/OI
    A<22>FB3MC1435I/OI
    A<20>FB3MC1536I/OI
    A<19>FB3MC1642I/OI
    A<3>FB4MC243I/OI
    A<28>FB4MC346I/OI
    A<6>FB4MC447I/OI
    A<13>FB4MC544I/OI
    A<18>FB4MC649I/OI
    FC<1>FB4MC845I/OI
    A<14>FB4MC1051I/OI
    A<23>FB4MC1148I/OI
    A<24>FB4MC1252I/OI
    A<21>FB4MC1450I/OI
    FC<2>FB4MC1556I/OI
    A<10>FB4MC1757I/OI
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_02.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_02.htm new file mode 100644 index 0000000..445bfd6 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinput_02.htm @@ -0,0 +1,320 @@ + + + + + + +

    Inputs

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameFunction BlockMacrocellPin NumberPin TypePin Use
    A<31>FB2MC101I/OI
    A<11>FB2MC112I/O/GTS2I
    A<15>FB2MC124I/OI
    CLKdatFB2MC145I/O/GTS1I
    nASFB2MC156I/OI
    A<7>FB2MC177I/OI
    A<8>FB1MC59I/OI
    A<25>FB1MC610I/OI
    A<9>FB1MC811I/OI
    CLKFB1MC915I/O/GCK1GCK
    CMD<1>FB1MC1116I/O/GCK2I
    A<4>FB1MC1720I/OI
    FC<0>FB3MC331I/OI
    A<16>FB3MC634I/OI
    A<22>FB3MC1435I/OI
    A<20>FB3MC1536I/OI
    CMD<0>FB3MC1039I/OI
    A<2>FB3MC1240I/OI
    A<19>FB3MC1642I/OI
    A<3>FB4MC243I/OI
    A<13>FB4MC544I/OI
    FC<1>FB4MC845I/OI
    A<28>FB4MC346I/OI
    A<6>FB4MC447I/OI
    A<23>FB4MC1148I/OI
    A<18>FB4MC649I/OI
    A<21>FB4MC1450I/OI
    A<14>FB4MC1051I/OI
    A<24>FB4MC1252I/OI
    FC<2>FB4MC1556I/OI
    A<10>FB4MC1757I/OI
    A<17>FB2MC358I/OI
    STERMFB2MC459I/OI
    A<29>FB2MC561I/OI
    A<30>FB2MC662I/OI
    A<5>FB2MC863I/OI
    A<12>FB2MC964I/O/GSRI
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/mapinputdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinputdoc.htm new file mode 100644 index 0000000..3ac20d8 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/mapinputdoc.htm @@ -0,0 +1,147 @@ + + + + + + + + + + + + + + + Mapped Inputs + + + + + + + + + + + +

    +Mapped Inputs

    +Like +the Mapped Logic section, the Mapped Inputs +section of the report displays a table detailing the resources allocated +by the fitter to mapped inputs. Again, +the table can be sorted by Signal Name, Function Block, or Pin Number by +clicking on the appropriate table headings.  +
    +
    The +inputs table contains the following:  +
      +
    • +The +input signal name 
      • + +
    • +The +function block number - an asterisk "*" indicates a user assignment
      • +
    + +
    Note: +Clicking on the function block will provide a detailed table of all the +block's resources and a graphical display of the function block diagram +(see Function Block Specifics for more details).
    + +
      +
    • +The +macrocell number
      • +
    + +
      +
      Note: +Clicking on the underscored macrocell number will provide a graphical display +of the macrocell that looks like this:
      + +
      +
      + +
        + +
    • +The +pin number - an asterisk "*" indicates a user assignment
      • +
    + +
    Note: +Clicking on the underscored pin number will provide the pin layout diagram +for the highlighted pin. Rolling +your mouse over the colored pin will pop up a tooltip with the signal name +assigned to the pin, the I/O standard, the +I/O style, the slew rate, and/or any constraints assigned to the pin:
    + + +

    + +

      + +
      +
    • +The +pin type
      • + +
    • +The +pin use 
      • + +
    • +The +I/O standard
      • + +
    • +The +I/O style
      • +
    + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic.js b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic.js new file mode 100644 index 0000000..e40c8f2 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic.js @@ -0,0 +1,23 @@ +function showFB(fb) { parent.leftnav.showFB(fb); } +function showMC(mc) { parent.leftnav.showAppletMC(mc); } +function showEqn(sig) { parent.leftnav.showEqn(sig); } +function showPin(pin) { parent.leftnav.showAppletPin(pin); } +function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } +function showTop() { parent.leftnav.showTop(); } + +function Sort(x) { + switch (x) { + case 0: parent.leftnav.showMappedLogics(0); break; + case 1: parent.leftnav.showMappedLogics(2); break; + case 2: parent.leftnav.showMappedLogics(4); break; + case 10: parent.leftnav.showMappedInputs(0); break; + case 11: parent.leftnav.showMappedInputs(2); break; + case 12: parent.leftnav.showMappedInputs(4); break; + case 20: parent.leftnav.showUnMappedLogics(0); break; + case 21: parent.leftnav.showUnMappedLogics(2); break; + case 22: parent.leftnav.showUnMappedLogics(4); break; + case 30: parent.leftnav.showUnMappedInputs(0); break; + case 31: parent.leftnav.showUnMappedInputs(2); break; + case 32: parent.leftnav.showUnMappedInputs(4); break; + } +} diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_00.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_00.htm new file mode 100644 index 0000000..d4a63bb --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_00.htm @@ -0,0 +1,393 @@ + + + + + + +

    Logic

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameTotal PtermsTotal InputsFunction BlockMacrocellPower ModeSlew RatePin NumberPin TypePin UseReg Init State
    NA23FB3MC10STD 39I/OIRESET
    NB<0>23FB2MC18STD  (b)(b)RESET
    NB<1>23FB2MC17STD 7I/OIRESET
    NC<0>23FB3MC9STD 27I/O(b)RESET
    NC<1>34FB3MC18STD  (b)(b)RESET
    NC<2>35FB3MC17STD 38I/O(b)RESET
    NC<3>36FB3MC16STD 42I/OIRESET
    NC<4>37FB3MC15STD 36I/OIRESET
    NC<5>38FB3MC14STD 35I/OIRESET
    NC<6>39FB3MC13STD  (b)(b)RESET
    NC<7>310FB3MC12STD 40I/OIRESET
    NC<8>311FB3MC11STD 33I/O(b)RESET
    NR<0>23FB2MC16STD  (b)(b)RESET
    NR<10>23FB2MC15STD 6I/OIRESET
    NR<11>23FB2MC14STD 5I/O/GTS1IRESET
    NR<12>23FB2MC13STD  (b)(b)RESET
    NR<1>23FB2MC12STD 4I/OIRESET
    NR<2>23FB3MC8STD 25I/O(b)RESET
    NR<3>23FB3MC7STD  (b)(b)RESET
    NR<4>23FB3MC6STD 34I/OIRESET
    NR<5>23FB3MC5STD 24I/O(b)RESET
    NR<6>23FB3MC4STD 32I/O(b)RESET
    NR<7>23FB3MC3STD 31I/OIRESET
    NR<8>23FB3MC1STD  (b)(b)RESET
    NR<9>23FB2MC11STD 2I/O/GTS2IRESET
    $OpTx$BIN_STEP$4095254FB1MC13STD  (b)(b) 
    nFPUCS212FB3MC2STDFAST22I/OO 
    nSTERM24FB2MC2STDFAST60I/OO 
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_01.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_01.htm new file mode 100644 index 0000000..993c483 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_01.htm @@ -0,0 +1,393 @@ + + + + + + +

    Logic

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameTotal PtermsTotal InputsFunction BlockMacrocellPower ModeSlew RatePin NumberPin TypePin UseReg Init State
    $OpTx$BIN_STEP$4095254FB1MC13STD  (b)(b) 
    nSTERM24FB2MC2STDFAST60I/OO 
    NR<9>23FB2MC11STD 2I/O/GTS2IRESET
    NR<1>23FB2MC12STD 4I/OIRESET
    NR<12>23FB2MC13STD  (b)(b)RESET
    NR<11>23FB2MC14STD 5I/O/GTS1IRESET
    NR<10>23FB2MC15STD 6I/OIRESET
    NR<0>23FB2MC16STD  (b)(b)RESET
    NB<1>23FB2MC17STD 7I/OIRESET
    NB<0>23FB2MC18STD  (b)(b)RESET
    NR<8>23FB3MC1STD  (b)(b)RESET
    nFPUCS212FB3MC2STDFAST22I/OO 
    NR<7>23FB3MC3STD 31I/OIRESET
    NR<6>23FB3MC4STD 32I/O(b)RESET
    NR<5>23FB3MC5STD 24I/O(b)RESET
    NR<4>23FB3MC6STD 34I/OIRESET
    NR<3>23FB3MC7STD  (b)(b)RESET
    NR<2>23FB3MC8STD 25I/O(b)RESET
    NC<0>23FB3MC9STD 27I/O(b)RESET
    NA23FB3MC10STD 39I/OIRESET
    NC<8>311FB3MC11STD 33I/O(b)RESET
    NC<7>310FB3MC12STD 40I/OIRESET
    NC<6>39FB3MC13STD  (b)(b)RESET
    NC<5>38FB3MC14STD 35I/OIRESET
    NC<4>37FB3MC15STD 36I/OIRESET
    NC<3>36FB3MC16STD 42I/OIRESET
    NC<2>35FB3MC17STD 38I/O(b)RESET
    NC<1>34FB3MC18STD  (b)(b)RESET
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_02.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_02.htm new file mode 100644 index 0000000..21d37bf --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogic_02.htm @@ -0,0 +1,417 @@ + + + + + + +

    Logic

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal NameTotal PtermsTotal InputsFunction BlockMacrocellPower ModeSlew RatePin NumberPin TypePin UseReg Init State
    NR<9>23FB2MC11STD 2I/O/GTS2IRESET
    NR<1>23FB2MC12STD 4I/OIRESET
    NR<11>23FB2MC14STD 5I/O/GTS1IRESET
    NR<10>23FB2MC15STD 6I/OIRESET
    NB<1>23FB2MC17STD 7I/OIRESET
    nFPUCS212FB3MC2STDFAST22I/OO 
    NR<5>23FB3MC5STD 24I/O(b)RESET
    NR<2>23FB3MC8STD 25I/O(b)RESET
    NC<0>23FB3MC9STD 27I/O(b)RESET
    NR<7>23FB3MC3STD 31I/OIRESET
    NR<6>23FB3MC4STD 32I/O(b)RESET
    NC<8>311FB3MC11STD 33I/O(b)RESET
    NR<4>23FB3MC6STD 34I/OIRESET
    NC<5>38FB3MC14STD 35I/OIRESET
    NC<4>37FB3MC15STD 36I/OIRESET
    NC<2>35FB3MC17STD 38I/O(b)RESET
    NA23FB3MC10STD 39I/OIRESET
    NC<7>310FB3MC12STD 40I/OIRESET
    NC<3>36FB3MC16STD 42I/OIRESET
    nSTERM24FB2MC2STDFAST60I/OO 
    $OpTx$BIN_STEP$4095254FB1MC13STD  (b)(b)    
    NR<12>23FB2MC13STD  (b)(b)D  RESET
    NR<0>23FB2MC16STD  (b)(b)D  RESET
    NB<0>23FB2MC18STD  (b)(b)D  RESET
    NR<8>23FB3MC1STD  (b)(b)D  RESET
    NR<3>23FB3MC7STD  (b)(b)D  RESET
    NC<6>39FB3MC13STD  (b)(b)D  RESET
    NC<1>34FB3MC18STD  (b)(b)D  RESET
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/maplogicdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogicdoc.htm new file mode 100644 index 0000000..75e0468 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/maplogicdoc.htm @@ -0,0 +1,167 @@ + + + + + + + + + + + + + + + Mapped Logic + + + + + + + + + + + +

    +Mapped Logic

    +The +Mapped Logic section provides a table listing resources allocated by the +fitter to mapped logic. The page will appear in your browser sorted by +Signal Name, but you can choose to sort it by Signal Name, Function Block, +and Pin Number by clicking on the appropriate table headers.  +
    +
    The +Mapped Logic table contains the following:  +
      +
    • +The +output signal name 
      • +
    + +
    Note: +Clicking on the signal name will open a new window with the equations for +that signal. 
    + +
      +
    • +The +total number of product terms 
      • + +
    • +The +number of signals used 
      • + +
    • +The +function block number - an asterisk "*" indicates a user assignment 
      • +
    + +
    Note: +Clicking on the function block will provide a detailed table of all the +block's resources and a graphical display of the function block diagram +(see Function Block Specifics for more details).
    + +
      +
    • +The +macrocell number
      • +
    + +
    Note: +Clicking on the underscored macrocell number will provide a graphical display +of the macrocell that looks like this:
    + + +

    +. +

      +
    • +The +slew rate
      • + +
    • +The +pin number - an asterisk "*" indicates a user assignment 
      • +
    + +
    Note: +Clicking on the underscored pin number will provide the pin layout diagram +for the highlighted pin. Rolling +your mouse over the colored pin will pop up a tooltip with the signal name +assigned to the pin, the I/O standard, the +I/O style, the slew rate, and/or any constraints assigned to the pin:
    + + +

    + +

      +
    • +The +pin type
      • + +
    • +The +pin use
      • + +
    • +The +input register use
      • + +
    • +The +I/O standard
      • + +
    • +The +I/O style
      • +
    + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/newappletref.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/newappletref.htm new file mode 100644 index 0000000..37f3d7f --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/newappletref.htm @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/next.jpg b/sterminator/XC9572XL/STERMINATOR_html/fit/next.jpg new file mode 100644 index 0000000000000000000000000000000000000000..b8bbb999ee5f7042c9dcbad4dacf3659aa2ee7a8 GIT binary patch literal 1079 zcmex=9X@jO*zpr5PhGlvPb?HxGHT=yahkYr<3UbkKb$@|Xn~>>0k;H_C~9n78`F`QPzJCPur8PO(e59<=M&#AB!andt81j&-><& zq0R)8)>*%}S1eCIc5p`YX|0I4_YHq$Fz?;;;rYSt*U{0tb<-VpZr`&@tnAX^l};~h z4@wFuvh)0Bc+*$ATG}JO(dzgS4jcZ(uV&>fUG1N$daHKQE6pTDX*Pvd9!8IgE0a~U zjAeMzr9*y*KC+EJcQ} z_Q%h2XUvoA_V4%D9AWcJ^)|EmddV+~w(ZY~|Jm}-{= 4)); + +var pluginDetected = false; + +// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up' +if(is_nav4up) { + + // Refresh 'navigator.plugins' to get newly installed plugins. + // Use 'navigator.plugins.refresh(false)' to refresh plugins + // without refreshing open documents (browser windows) + if(navigator.plugins) { + navigator.plugins.refresh(false); + } + + // check for Java plugin in installed plugins + if(navigator.mimeTypes) { + // window.alert( navigator.mimeTypes.length); + for (i=0; i < navigator.mimeTypes.length; i++) { + // window.alert( navigator.mimeTypes[i].type); + if( (navigator.mimeTypes[ i].type != null) + &&(navigator.mimeTypes[ i].type.indexOf( + "application/x-java-applet;jpi-version=1.4") != -1) ) { + //window.alert("Found"); + pluginDetected = true; + break; + } + + } + } + +} + +if (pluginDetected) { + // show applet page + document.location.href="appletref.htm"; + +} else if (confirm("Java Plugin 1.4+ not found, Do you want to download it?\n" + + "if you choose not to install the plugin the reports graphical applets will not be available.")) { + document.location.href=XilinxD; +} else { + document.location.href="appletref.htm"; +} + +} + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/options.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/options.htm new file mode 100644 index 0000000..22128da --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/options.htm @@ -0,0 +1,106 @@ + + + + + + +

    Compiler Options

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    OptionValue
     Device(s) Specified + xc9572xl-5-VQ64
     Optimization Method + SPEED
     Multi-Level Logic Optimization + ON
     Ignore Timing Specifications + OFF
     Default Register Power Up Value + LOW
     Slew Rate + FAST
     Keep User Location Constraints + ON
     What-You-See-Is-What-You-Get + OFF
     Exhaustive Fitting + OFF
     Keep Unused Inputs + OFF
     Power Mode + STD
     Ground on Unused IOs + OFF
     Global Clock Optimization + ON
     Global Set/Reset Optimization + ON
     Global Ouput Enable Optimization + ON
     Set I/O Pin Termination + KEEPER
     Input Limit (2-54) 54
     Pterm Limit (1-90) 25
    + + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/optionsdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/optionsdoc.htm new file mode 100644 index 0000000..f1ee543 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/optionsdoc.htm @@ -0,0 +1,760 @@ + + + + + + + + + + +Compiler Options + + + + + + + + + + + + + + + + + + + + + + + + +

    Compiler Options

    + +

    The Compiler + Options page provides all the fitter options settings for the device family + the fitter has selected.

    + +

    Fitter Options

    + +

    Basic Tab

    + +

    XPLA3 Advanced + Options

    + +

    CoolRunner-II + Advanced Options

    + +

    XC9500/XL/XV + Advanced Options

    + +

    Basic + Tab

    + +

    The CPLD devices + have the following fitter Implementation + Options available in + the Basic tab:

    + +
      + +

    • Use + Multi-Level Logic Optimization

      • +
    + +

    This option simplifies the total number + of logic expressions in a design, and then collapses the logic in order + to meet user objectives such as density, speed and timing constraints. + This optimization targets CPLD architecture, making it possible to collapse + to the macrocell limits, reduce levels of logic, and minimize the total + number of p-terms.

    + +

    Multi-level Logic Optimization optimizes + all combinatorial logic arcs spanning from an input pad or register output + to an output pad or register input.

    + +

    Multi-level Logic Optimization operates + on combinatorial logic according to the following rules.

    + +

    If timing constraints are set, the program + optimizes for speed to meet timing constraints.

    + +

    If timing constraints are not set, the + program optimizes either for speed or density, depending on the user setting + for the Use Timing Optimization + option.

    + +
      + +
        + +
          + +

        • If + Use Timing Optimization is turned + on, the combinatorial logic will be mapped for speed.

          • + +

        • If + Use Timing Optimization is turned + off, the combinatorial logic will be mapped for density. The goal of optimization + will then be to reduce the total number of p-terms.

          • +
        +
      +
    + +

    Logic + marked with the NOREDUCE property will not be extracted or optimized.

    + +

    By + default, this option is on.

    + +
      + +

    • Use Timing Constraints -- This + option instructs the fitter use Timing Constraints when fitting the design. +  If this + box is not checked, the fitter will ignore timing constraints, if necessary.

      • + +

    • Enable WYSIWYG + Mode -- (CoolRunner only) The + goal of the WYSIWYG options is to have a netlist reflect the user's specifications, + as much as possible. All the nodes declared in the HDL design are preserved. + By default, this property is set to Off (Checkbox is not checked) When + this property is On (checkbox is checked), XST:

      • + +
        + +

      • Preserves + all the user internal signals (nodes)

        • + +

      • Creates + source_node constraints in NGC file for all these nodes.

        • + +

      • Skips + the design optimization (collapse, factorization). Only the Boolean equation + minimization is performed.

        • +
      + +

    • Optimization Style-- The Optimization + Method allows you to select from one of two basic optimization strategies: + Density or Speed. + Density focuses on solely + on density, and Speed focuses + solely on speed.

      • + +

    • Location Constraints -- The Try selection + will attempt to fit the design with the pin assignments specified in the + design source. If the design cannot be fit with these pin assignments, + the fitter will remove the location constraints and attempt to fit the + design with no location constraints. A warning message will tell the user + if the location constraints have been removed.

      • + +
        + +

      • The + Try selection will attempt + to fit the design with the pin assignments specified in the design source. + If the design cannot be fit with these pin assignments, the fitter will + ignore the pin assignments.

        • +
      + +

    • The + On selection will attempt to fit + the design with the pin assignments specified in the design source. If + the design cannot be fit with these pin assignments, the fitter will notify + the user that the device could not fit. It will not unlock the pins under + this option.

      • + +

    • The + Off selection will attempt to + fit the design and will ignore the pin assignments specified in the design + source. If the design can be fit with no pre-assigned pins, the fitter + will assign pins, which can be viewed in the fitter report (filename.fit). + The user should take these pin assignments and incorporate them back into + the design source file. The user will be notified whether the fitting + operation was successful.

      • + +

    • Output + Slew Rate -- Use this option + to control the default output slew rate. You can control the transition + time of device output pins by setting the slew rate to Slow or Fast. Limiting + the slew rate (Slow) reduces output switching surges in the device. The + default is Fast.

      • +
    + +

    Note: + Any explicit slew rate control properties in the design or constraints + file take precedence over this Output Slew Rate setting.

    + +
      + +

    • FF Initial State -- Sets + the initial state for all Flip-Flops.  The + options are Low, High and FPGA.

      • + +

    • Collapsing + P-Term Limit -- This option + controls the degree to which the fitter flattens a design netlist. A logic + gate can collapse forward into a subsequent gate only if the number of + product terms in the resulting logic function does not exceed the p-term + limit. If the path delay of a logic function is not acceptable, increase + the p-term limit to allow the larger functions to be further flattened. + Choose a number from 3 to 48.

      • + +

    • Collapsing + Input Limit -- This is a + secondary option for controlling the degree to which the fitter flattens + a design netlist. A logic gate can collapse forward into a subsequent + gate only if the number of inputs in the resulting logic function does + not exceed the input limit. If the design fails to fit the target device + because flattening uses up too many of the function block inputs, decrease + the input limit to prevent flattening of certain high fan-in functions. +  

      • +
    + +

    XPLA Advanced + Options

    + +

    The + following options are available under XPLA Implementation + Options, Advanced tab.

    + +
      + +

    • Enable Fast + Input Registers -- Enables the use + of the Fast Input path in XPLA3 devices.

      • + +

    • Enable Use + of Foldback NANDs -- When selected, + the software will use foldback NANDs. This increases the capability to + fit a design, sometimes at the expense of speed.

      • + +

    • Reserve JTAG Pins for ISP -- Checking + this box will instruct the fitter to reserve JTAG pins.

      • +
    + +

    CoolRunner-II + Advanced Options

    + +

    The following + options are found under the Advanced tab for CoolRunner-II devices.

    + +
      + +

    • Use + Global Clock(s) -- Select this option + to allow the fitter to assign input pins used as clocks to dedicated global + clock (GCK) pins of the device. If this option is disabled, only pins + identified with the BUFG=CLK property in the design (or UCF file) will + be assigned to GCK device pins. By default, this option is on. +

      • + +

    • Use Global Output Enable(s) -- Select + this option to allow the fitter to assign input pins used as output enable + control to dedicated global OE (GTS) pins of the device. If this option + is disabled, only pins identified with the BUFG=OE property in the design + (or UCF file) will be assigned to GTS device pins. By default, this option + is on.

      • + +

    • Use Global Set/Reset -- Select this + option to allow the fitter to assign input pins used as register asynchronous + reset or preset control to the dedicated global set/reset (GSR) pin of + the device. If this option is disabled, only a pin identified with the + BUFG=SR property in the design (or UCF file) will be assigned to the GSR + device pin. By default, this option is on.

      • + +

    • Enable Fast Input Registers -- Enables + fast input registers.

      • + +

    • Ignore DATA_GATE Attributes -- Data + Gate is a power saving property that can be used in CoolRunner-II designs. +  This option + allows you to turn Data Gate off in case you want the fitter to ignore + data gate.

      • + +

    • Tristate Outputs Termination Node -- + The Tristate Output Termination Mode globally sets all tristate outputs + to the specified termination mode. By default, this field is set to Pullup.. +  The options + are Pullup, Keeper and Float.

      • + +

    • Create Programmable Ground Pins on Unused I/O + -- The Create Programmable GND Pins on Unused I/O property controls the + option to indicate that you want all unused I/O pads to be configured + as ground pins. This can reduce ground bounce. By default, this option + is set to ground.  The + options are Ground, Pullup, Keeper and Float.

      • + +
    • +

      Default + Output Voltage Standard -- set a default voltage standard for CoolRunner-II + device pins.

      + +

      IOSTANDARD + names supported by CoolRunner-II are:

      + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
      +

      I/O Standard

      		 +

      VCCIO

      		 +

      Input VREF

      		 +

      Board Termination Voltage (VTT)

      +

      LVTTL

      		+

      3.3V

      		 +

      N/A

      		 +

      N/A

      +

      LVCMOS33

      		 +

      3.3V

      		 +

      N/A

      		 +

      N/A

      +

      LVCMOS25

      		 +

      2.5V

      		 +

      N/A

      		 +

      N/A

      +

      LVCMOS18

      		 +

      1.8V

      		 +

      N/A

      		 +

      N/A

      +

      LVCMOS15

      		 +

      1.5V

      		 +

      N/A

      		 +

      N/A

      +

      HSTL_I

      		 +

      1.5V

      		 +

      0.75V

      		 +

      0.75V

      +

      SSTL2_I

      		 +

      2.5V

      		 +

      1.25V

      		 +

      1.25V

      +

      SSTL3_I

      		 +

      3.3V

      		 +

      1.5V

      		 +

      1.5V

      + +

      The software + automatically groups outputs with similar IOSTANDARD settings into the + same bank when no location constraints are specified.

      +
      • +
    + +

    XC9500/XL/XV + Advanced Options

    + +

    The following + options are found under the Advanced tab for XC9500/XL/XV.  Note + that additional options for XC9500 only are also described below.

    + +
      + +

    • Use + Global Clock(s) -- Select this option + to allow the fitter to assign input pins used as clocks to dedicated global + clock (GCK) pins of the device. If this option is disabled, only pins + identified with the BUFG=CLK property in the design (or UCF file) will + be assigned to GCK device pins. By default, this option is on. +

      • + +

    • Use Global Output Enable(s) -- Select + this option to allow the fitter to assign input pins used as output enable + control to dedicated global OE (GTS) pins of the device. If this option + is disabled, only pins identified with the BUFG=OE property in the design + (or UCF file) will be assigned to GTS device pins. By default, this option + is on.

      • + +

    • Use Global Set/Reset -- Select this + option to allow the fitter to assign input pins used as register asynchronous + reset or preset control to the dedicated global set/reset (GSR) pin of + the device. If this option is disabled, only a pin identified with the + BUFG=SR property in the design (or UCF file) will be assigned to the GSR + device pin. By default, this option is on.

      • + +

    • Create Programmable Ground Pins on Unused I/O + -- Select this option to indicate that you want all unused I/O pads to + be configured as ground pins. This can reduce ground bounce. By default, + this option is off.

      • + +

    • Macrocell Power Setting -- Use this + option to control device power consumption. Select Low or Standard to + set the default power mode for the macrocells used to implement the design. + Select Timing Driven to automatically reduce power on paths covered by + timing specifications that can meet speed requirements while operating + in low power. The default is Standard, which results in highest speed.

      • +
    + +

    Note: Any explicit power control (PWR_MODE) + properties in the design or constraints file take precedence over this + Macrocell Power Setting.

    + +
      + +

    • Enable FASTConnect/UIM Optimization (XC9500 + only) -- Enables optimization of the FASTConnect/UIM for XC9500 + devices.

      • + +

    • Use + Local Feedback (XC9500 only)

      • +
    + +

    Select this option to enable the software + to use local macrocell feedback whenever possible. The local feedback + path, running from each macrocell output to an input of the same function + block, has shorter propagation delay than the global feedback path. The + fitter always tries to use local macrocell feedback (if possible) to satisfy + timing constraints. This option allows the fitter to use local feedback + to generally improve timing on remaining paths. Using local feedback can + speed up your design but could also make it difficult to maintain the + same timing after a design change. By default, this option is on.

    + + + +
    + + +

    Note: + To force the fitter to use local feedback, manually map both + the source and load functions into the same function block using the property + LOC=FBnn, + then apply a timespec across the path. 

    + + + +
    + + +

    Note: + The XC9536 device does not have local feedback.

    + + + +
    + + +
      + +

    • Use + Pin Feedback (XC9500 only)

      • +
    + +

    Select this option to enable the software + to use I/O pin feedback whenever possible. The pin feedback path has slightly + shorter propagation delay than the global feedback path. If this option + is enabled, the software uses the pin feedback path instead of the global + feedback path for macrocell signals that do not drive 3-state outputs + or slew-rate-limited outputs, and where the associated I/O pin is not + used as input-only. By default, this option is on.

    + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/paths.js b/sterminator/XC9572XL/STERMINATOR_html/fit/paths.js new file mode 100644 index 0000000..ff4aa89 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/paths.js @@ -0,0 +1,39 @@ +rootURL = "http://www.xilinx.com/"; +prodURL = "xlnx/xil_prodcat_product.jsp?title="; +cpldURL = "CPLD+Products"; +acr2URL = "coolrunner2_page"; +xbrURL = "coolrunner2_page"; +xpla3URL = "xpla3_page"; +xc9500URL = "xc9500_page"; +xc9500xlURL = "xc9500xl_page"; +xa9500xlURL = "xc9500xl_page"; +xc9500xvURL = "xc9500xv_page"; +marketURL= "esp"; +supportURL = "http://www.support.xilinx.com/"; +educationURL = "support/education-home.htm"; +buyURL = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront"; +contactURL = "company/contact.htm"; +searchURL = "company/search.htm"; + +docURL = rootURL + "support/documentation/"; +doc95URL = docURL + "xc9500.htm"; +doc95xlURL = docURL + "xc9500xl.htm"; +docA95xlURL = docURL + "xc9500xl.htm"; +doc95xvURL = docURL + "xc9500xv.htm"; +docXpla3URL = docURL + "coolrunner_xpla3.htm"; +docAcr2URL = docURL + "coolrunner-ii.htm"; +docXbrURL = docURL + "coolrunner-ii.htm"; +docCr2sURL = docURL + "coolrunner-ii.htm"; + +var messages = new Array(); +messages["fastinreg"] = "Direct Input Register"; +messages["inreg"] = "Direct Input Register"; +messages["fbnand"] = "Foldback NAND"; +messages["fcnode"] = "FC node"; +messages["LATCH"] = "Transparent latch"; +messages["DFF"] = "D-flip-flop"; +messages["DEFF"] = "D-flip-flop with clock enable"; +messages["TFF"] = "T-flip-flop"; +messages["TDFF"] = "Dual-edge-triggered T-flip-flop"; +messages["DDFF"] = "Dual-edge-triggered flip-flop"; +messages["DDEFF"] = "Dual-edge-triggered flip-flop with clock enable"; diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pin.gif b/sterminator/XC9572XL/STERMINATOR_html/fit/pin.gif new file mode 100644 index 0000000000000000000000000000000000000000..f110f3df4f08db5e7b03c33b102290f713d6f6ce GIT binary patch literal 3093 zcmeH`_d6R37spFmSG8tUjiM+uiz3#g)2Q96R;#UEGh$WM2p7HfjoBfjMi4|otV-(#5vjTT!J0J1sW-ZcLRDEFM{t8p5~a8`#) zYYCK+s_h7e57Aai(>OoV`XmS(Gt=<;=Z0tqZs%K>50flvCiv%E8;DooMWdCK*|&TSLph+NEZ!Xat_6O-sRziqcYMWT?%mOG_e5lT$kkj|YOnjtXj*36T+FbX z?1)bZwM#7adaOM>R^oiTK+wgzn%OZ6b@XfqH9=M^;d&kt8gzRFDHWg|-tp?G7){nC z>0VCHT&giP0O9=zP%@mNp1HR4k?#>OJ?V)XY4ZIHaJ}$>)qu+~)Wz0~qQyTz&(Q_g=@durMF&SyY5Yq0ptxOp}G2FB?FG+?oY22-8T0O?r9h zOcj9*IMDMM&tLVXzU%_@EWc<4YnNMSHzJjvHCddAK^3g`EM}vYx$V|&2Z)rY+VX*Jmc6w$NZ9nJf%1tD( zXlJ}&)P8x>4i{xNKo!IO~-%Md||UI>wIx%^ta+y>G?KjLFI1Ze|B=x@ki`crKcuQ#&6sNTM$!YLfRCQ;lvN zEPb@|Iatnc#~iF=1(6R{;pN%;Yw^(V{dGh^@@i#KF&VsBfxZ}C%PS2`2$tNM>#xU zg~54pppSW}%uq~A(WmWx$kz8JPcU6hfScta!!P!}GuMJ7PcB%2+015HSkB$8QuNcM zhxUSGWbtS3D~EBr!1q`)S~um&Bl|buMz`40IXH%*r4r%noCR%jF{vPx{(&(*L1|XK zekU#h_uCs3b!26HoLs0?JCi^4%Pn53>lYV=cwPtR9#eP>Ed&1Kkpgr`a-ECe=e56t z3(gUW-8BR(Q(NyO&BR3sXP}|u3D5l?erd6&V0D`+$fvTUr!tI@ zmMiiX((wL8a?gwb!X|1GH^RPaQe!nV{u z$utOAu4|~lsEP5qWA4m>u-NlC;XjM@#vDv&+trb*&uzE=q}P*FDS2E;9@h3ZAIAeI z`2s}bT=KG<{o5zDl^p9v1~B>e7*B+(641mFHIkkqpQn;kV&-l#3Y(%7X%R~-g8D{t z4k^WVIZ;+|CSUV~sYqjU)E`iJ9S2ov$#k2CL9zT8$}=GUV&R4j4mE~(`ZjxRVZ*Ll ze!R*@9qmFzIgIw%BK@9d_$8qoS4}4Br>K}9ieF&eb&}bKky+DQ{*J-CyBPWstfPXzhH&;lyLd96McOmF_O{ioGZP10B&>&o2ybADVTKQH!iGY$ zrC}s{H*ueX{%iyy_fg#ft;zmly1roH8(CMmsSu-o0xRy*V}KmI4%*V7YM6Uwm-Q-= z;51rUpz3DEsaD<9K!YYm5Z9c33Xf=WeW^Sc18HAo^b!OBa;97NJe&`wfMOch;zk3< z>Hh9}v65|F<^=t=S`y;mi!e?PRN~F(QO&`EReM%F2tCv7XM+m1l_UcQ^wA@($EeRj zyP;Ckgv7F-R^_FgW7e#%p*Of2jfmcE+zq{vv9yemB3Fy%o*8U2we?NemLjNOk^k^& zO`q$y--A1jMAb`mUwGdxuq%YktBD-o7O%NvNg-=fW z$`y@z4^ghA934>wjsdN~ve|WBj=$d7-AO>{YSOR)f5j*XFea301I1mB*A4?qM+&|M zGGnsath#+;7Rf(QB3QCUNGM|PR@)b4==$xZhB!KTsf-}HzD{L$u?!L$)#`^H#f8Q3 zh+B6;vNyj8`)%)=9FBZGp&%`rHVFE7EQ(6Sr0A`5V#lZ2XK7WrSI9vTjM;{q{5o#^ totOw)q%d>8$Flhcbns|Jmw7Oh(o89~Jl=T5Je(YCrs42)k!Q~6{ts)#@;m?l literal 0 HcmV?d00001 diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXC95.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXC95.htm new file mode 100644 index 0000000..db88bcb --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXC95.htm @@ -0,0 +1,13 @@ +
    +Legend :  NC  = Not Connected, unbonded pin
+         PGND = Unused I/O configured as additional Ground pin
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+         PE   = Port Enable pin
+  PROHIBITED  = User reserved pin
+
    diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXbr.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXbr.htm new file mode 100644 index 0000000..00a6d2c --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXbr.htm @@ -0,0 +1,21 @@ +
    +Legend :  NC  = Not Connected, unbonded pin
+        PGND  = Unused I/O configured as additional Ground pin
+         KPR  = Unused I/O with weak keeper (leave unconnected)
+         WPU  = Unused I/O with weak pull up (leave unconnected)
+         WPD  = Unused I/O with weak pull down (leave unconnected)
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+      VCCAUX  = Power supply for JTAG pins
+   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
+   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
+   VCCIO-1.8  = I/O supply voltage for LVCMOS18
+   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
+        VREF  = Reference voltage for indicated input standard
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+
    diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXpla3.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXpla3.htm new file mode 100644 index 0000000..8dad55d --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pin_legXpla3.htm @@ -0,0 +1,13 @@ +
    +Legend :  NC  = Not Connected, unbonded pin
+          PE  = Port Enable pin
+         WPU  = Unused with Internal Weak Pull Up
+         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
+         VCC  = Dedicated Power Pin
+         GND  = Dedicated Ground Pin
+         TDI  = Test Data In, JTAG pin
+         TDO  = Test Data Out, JTAG pin
+         TCK  = Test Clock, JTAG pin
+         TMS  = Test Mode Select, JTAG pin
+  PROHIBITED  = User reserved pin
+
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    Legends

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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    AcronymBrief Description
     CLK Clock
     GCK0 Global Clock 0
     GCK1 Global Clock 1
     GCK2 Global Clock 2
     GND Ground
     GSR Global Set/Reset
     GTS0 Global Output Enable 0
     GTS1 Global Output Enable 1
     GTS2 Global Output Enable 2
     GTS3 Global Output Enable 3
     I/O Input/Output
     INIT Initial state
     ISP In system programmable
     JTAG Joint Test Action Group
     KPR Unused I/O with weak keeper
     NC No Connects
     PGND Programmable ground pin
     PROHIBITED User reserved pin
     R Reset
     S Set
     TCK Test clock
     TDI Test data input
     TDO Test data output
     TIE Unused I/O floating
     TMS Test mode select
     LVCMOS Low Voltage CMOS 3.3 Volts
     LVCMOS25 Low Voltage CMOS 2.5 Volts
     LVCMOS33 Low Voltage CMOS 2.5 to 3.3 Volts
     LVTTL Low Voltage TTL 3.3 Volts
     VCCIO Input/Output Supply Voltage
     VCC Power internal
     WPU Weak Pull Up
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    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pinlegendV.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/pinlegendV.htm new file mode 100644 index 0000000..577547a --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pinlegendV.htm @@ -0,0 +1,150 @@ + + + + + + + +

    Legends

    +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    AcronymVerbose Description
     CLK Global Clock
     GCK0 Global clock zero
     GCK1 Global clock one
     GCK2 Global clock two
     GND Dedicated Ground Pin
     GSR Global set-reset
     GTS0 Global tristate zero (output enable)
     GTS1 Global tristate one (output enable)
     GTS2 Global tristate two (output enable)
     GTS3 Global tristate three (output enable)
     I/O Input/Output
     INIT Initial state
     ISP The use of the JTAG port to program the chip while it is powered in a system.
     JTAG IEEE Standard 1149 (JTAG) boundary-scan test standard.
     KPR Unused I/O with weak keeper (leave unconnected)
     NC Not Connected, unbonded pin
     PGND Programmable ground pin
     PROHIBITED User reserved pin
     R Reset
     S Set
     TCK One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pull-up forces TCK to a high level if left unconnected.
     TDI One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial input for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level if left unconnected.
     TDO One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It is the serial output for shifting data through the instruction register or selected data register. An internal pull-up forces TDI to a high level when it is not driven from an external source.
     TIE Unused I/O floating -- must tie to VCC, GND or other signal
     TMS One of four terminals required by (JTAG) IEEE Std 1149 or IEEE Std 1532. It directs the device through its Test Access Port controller states. An internal pull-up forces TDI to a high level when it is not driven from an external source. TMS also provides the optional test reset signal of IEEE Std 1149 or IEEE Std 1532.
     LVCMOS Low Voltage Complementary Metal Oxide Semiconductor 3.3 Volts
     LVCMOS25 External I/O supply voltage for LVCMOS25
     LVCMOS33 External I/O supply voltage for LVCMOS33
     LVTTL Low Voltage Transistor Transistor Logic 3.3Volts
     VCCIO External power for Inputs/Outputs
     VCC Dedicated Power Pin, Internal supply voltage for the device
     WPU Unused I/O with Internal Weak Pull Up (leave unconnected)
    + + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pins.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/pins.htm new file mode 100644 index 0000000..218fb43 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pins.htm @@ -0,0 +1,341 @@ + + + + + + +

    Pin List

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Pin NumPin TypeAssigned Signal
    1I/OA<31>
    2I/O/GTS2A<11>
    3VCCINTVCC
    4I/OA<15>
    5I/O/GTS1CLKdat
    6I/OnAS
    7I/OA<7>
    8I/OKPR
    9I/OA<8>
    10I/OA<25>
    11I/OA<9>
    12I/OKPR
    13I/OKPR
    14GNDGND
    15I/O/GCK1CLK
    16I/O/GCK2CMD<1>
    17I/O/GCK3KPR
    18I/OKPR
    19I/OKPR
    20I/OA<4>
    21GNDGND
    22I/OnFPUCS
    23I/OKPR
    24I/OKPR
    25I/OKPR
    26VCCIOVCC
    27I/OKPR
    28TDITDI
    29TMSTMS
    30TCKTCK
    31I/OFC<0>
    32I/OKPR
    33I/OKPR
    34I/OA<16>
    35I/OA<22>
    36I/OA<20>
    37VCCINTVCC
    38I/OKPR
    39I/OCMD<0>
    40I/OA<2>
    41GNDGND
    42I/OA<19>
    43I/OA<3>
    44I/OA<13>
    45I/OFC<1>
    46I/OA<28>
    47I/OA<6>
    48I/OA<23>
    49I/OA<18>
    50I/OA<21>
    51I/OA<14>
    52I/OA<24>
    53TDOTDO
    54GNDGND
    55VCCIOVCC
    56I/OFC<2>
    57I/OA<10>
    58I/OA<17>
    59I/OSTERM
    60I/OnSTERM
    61I/OA<29>
    62I/OA<30>
    63I/OA<5>
    64I/O/GSRA<12>
    + + +
    + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pins.js b/sterminator/XC9572XL/STERMINATOR_html/fit/pins.js new file mode 100644 index 0000000..591e563 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pins.js @@ -0,0 +1,62 @@ +var specSig = new Array(); +var pins = new Array(); +var pinsAssign = new Array(); +var prohibit = new Array(); +var unusedStr = "WPU"; +var gndStr = "GND"; +var vccStr = "VCC"; +var tdiStr = "TDI"; +var tdoStr = "TDO"; +var tmsStr = "TMS"; +var tckStr = "TCK"; + +function showPin(pin) { parent.leftnav.showAppletPin(pin); } + +function printPage() { window.print(); parent.leftnav.printAppletPkg(); } + +function showEqn(signal) { parent.leftnav.showEqn(signal); } + +function updatePin(type) { + with (document.options) { + switch (type) { + case 0: + if (inp.checked) parent.leftnav.document.options.inOn.value = 1; + else parent.leftnav.document.options.inOn.value = 0; + break; + + case 1: + if (out.checked) parent.leftnav.document.options.outOn.value = 1; + else parent.leftnav.document.options.outOn.value = 0; + break; + + case 2: + if (glb.checked) parent.leftnav.document.options.glbOn.value = 1; + else parent.leftnav.document.options.glbOn.value = 0; + break; + + case 3: + if (isp.checked) parent.leftnav.document.options.ispOn.value = 1; + else parent.leftnav.document.options.ispOn.value = 0; + break; + + case 4: + if (vcc.checked) parent.leftnav.document.options.vccOn.value = 1; + else parent.leftnav.document.options.vccOn.value = 0; + break; + + case 5: + if (gnd.checked) parent.leftnav.document.options.gndOn.value = 1; + else parent.leftnav.document.options.gndOn.value = 0; + break; + + case 6: + if (unuse.checked) parent.leftnav.document.options.unuseOn.value = 1; + else parent.leftnav.document.options.unuseOn.value = 0; + break; + } + } + + parent.leftnav.showPinOut(); +} + +function showLegend(url) { parent.leftnav.showLegend(url, 650, 350); } diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pinsdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/pinsdoc.htm new file mode 100644 index 0000000..9da2708 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/pinsdoc.htm @@ -0,0 +1,265 @@ + + + + + + + + + + +Pin List + + + + + + + + + + + + + + + + + + + + + + + + +

    Pin List

    + +

    The Pin List + page lists each pin of your design with its pin type and associated signal. +  Check boxes + at the top of the table allow you to select and deselect which pin types + you want displayed in the table (the default view will display all of + them).

    + +

    Note: +  There is + a button below the table.  Click + this button to open a new window describing all of the acronyms used in + the function block table.  You + can select either brief descriptions or more detailed descriptions by + clicking the "Verbose" button at the top of the window.

    + +Clicking + on the underscored pin numbers in the first column of the table will open + a new window displaying the pin layout diagram for the selected pin.  Rolling + your mouse over the colored pin will pop up a tooltip with the signal + name assigned to the pin, the I/O standard,  the + I/O style, the slew rate, and/or any constraints assigned to the pin: + + +

    + +

    Clicking any underscored signal in the + third column of the table will open a new window displaying the equations + for that particular signal.

    + +

    Clicking on the button + at the top of the screen will open a new window with a graphical, top + view of all of the pins:  

    + +

    + +

    They are color-coded as follows:

    + + + +++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +

    Color

    		 +

    Signal

    +

    Green

    		 +

    Input

    +

    Aqua

    		 +

    Bidirectional

    +

    Blue

    		 +

    Output

    +

    Magenta

    		 +

    Clock

    +

    Red

    		 +

    VCC

    +

    Black

    		 +

    GND

    +

    Yellow

    		 +

    TDO

    +

    Gray

    		 +

    TDI

    +

    White

    		 +

    Unused Pin

    +

    Black Outline

    		 +

    No available + Pad

    + +

    As with the single pin display, rolling + your mouse over any colored pin will pop up a tooltip with the signal + name assigned to the pin, the I/O standard,  the + I/O style, the slew rate, and/or any constraints assigned to the pin.

    + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/pinview.jpg b/sterminator/XC9572XL/STERMINATOR_html/fit/pinview.jpg new file mode 100644 index 0000000000000000000000000000000000000000..c3a27ca5c3e1ff7ae45eafedc7f9c40ec212299e GIT binary patch literal 1868 zcmbW!doQXf>O=;b# zml(RHBH~iiy)@RfMOBNDifvJY(lMJ*t&%nqyL)EO*}r!8dC&X)^FHr;zMu2RU&v!WtZ>>V6w zPTzj#dBV$^?h_bvI{3_4=DFyY*tmEW`@#=t=^2@qIal%vt{2|8dFwX!r@Ljma(;!N z@_s{OQ*%pe+k@_&-oE}vj|T=v$Hsr25WScb&%U1fWqx7t&C;@Tb?x2y`wtr*H@967 z0QOJTAF}^&feIH?F%~#-+XaEfD>e*-BX*i8VQk%zj7Uw={!7Z(BYCCuT`Gp=9ulp9 zsOPFUvc)V#x=s6s?7xGh{$H{`VE=ZB0W=Jv7#<7+4g)_+5EI|t_Te)MgV8aqayC{*8bzy$NGB4*&!*%FG=ecG%YliwDrYHhrnf5ol^=CG&*$fDJ z>&hzMl%ArdWBUhrx1iZHSPHwknAnAR+l*PJ7EIcryAvYAhhmGY3e!9o!qL7GD^lX= zUtAi%HYd>-QQbb7$U1xGGlSZ>NeLNvhnEB0(NZ*;xFLv?1Nqbx)j{`0uC>6KyVo`D znwe1V9Hlfci4VOuLN#n7u$Z`Sst?M6T!4qXS+^3H|7RW6;tHyK+1lokU}*#&5`mVO z521w9(=;P8i>-SZYIv=~l>DRSIxq3zmS0lQ3b#b|scNWxb!~nwICxsL_%tr&hZG&S7x~bR2uU;oFaTucWUE1L;PEE0tVgdBfD&;M5^$Rrx&p>bR;%+kc}nMh;|X@Vn)J+S^x@k}(%f z*qI{Ne6dB&kiUsv!)5Wz^`W$M-#8_wa1VA)rVVM-*RG*`Y@Hq(hV*RDTWLCw^3!Xh zA&w7yU#%AKU13>Xc6h1#S_|a;?Wm3~rAD^TWROzvvN)b&JU`kvbbP;LsPu1XR~ArM zw&A`8UGOgLTDwj7k0SlK9m$V+gl6NiW3ykte7UsOxf`85UYlPG`cC^)_OA|;8WRFz z>38FU0gzNb-^rS4Z?)g6LV31{5e9s^M{pB29$C=hWRwg;&XeN^$s$w>dAG3&`cEf= z@K=S!yhN8Vi=~=sev|aj#GQoBEfZRdZ*$w#iJ%N;D^89k4L@oeU}xf;Tg$O3=)cHx z1(`yFEN^bNev{b%6Ww{1{ymF)wcLwSdfq0qZobX0b=fC(#9I>cp!jBwW7F`S-?+#1 zSP|vTKagKeRX!NTJ^wIrW!l=EZya->@zkc zuU+3Gc4;um9d2_8z=?HjiMu-cTy~bx7^Nhu7RQ&fu{rHTA`fTXhq^^*UJ0duqem znwlj|E9?n(?|Ka2*R|NmMyvsopf=xknjPnA4UV>5 zhYpr4lA%w&S!vyThJ1N{!>}uAm~A1{kZcVk-DzrP*4=0w%Cuojt;v>ap0a^;t(l9> zCdK?E8%%xO=&xa+p|b|ZBEm3_^iHpyuLSV= 4)); + +var is_ie = ((agt.indexOf("msie") != -1) && (agt.indexOf("opera") == -1)); +var is_ie5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.0")!= -1) ); +var is_ie5_5 = (is_ie && (is_major == 4) && (agt.indexOf("msie 5.5") != -1)); +var is_ie6 = (is_ie && (is_major == 4) && (agt.indexOf("msie 6.0") != -1)); + +var is_ie5up = (is_ie && (is_major == 4) && ( (agt.indexOf("msie 5.0")!=-1) || (agt.indexOf("msie 5.5")!=-1) || (agt.indexOf("msie 6.0")!=-1) ) ); + +var pluginDetected = false; +var activeXDisabled = false; + +// we can check for plugin existence only when browser is 'is_ie5up' or 'is_nav4up' +if(is_nav4up) { + + // Refresh 'navigator.mimeTypes' to get newly installed mimeTypes. + // Use 'navigator.mimeTypes.refresh(false)' to refresh mimeTypes + // without refreshing open documents (browser windows) + + // check for Java plugin in installed mimeTypes + if(navigator.mimeTypes ) { + //window.alert( "length"); + //window.alert( navigator.mimeTypes.length); + for (i=0; i < navigator.mimeTypes.length; i++) { + //window.alert(navigator.mimeTypes[i].type); + if( (navigator.mimeTypes[ i].type != null) + &&(navigator.mimeTypes[ i].type.indexOf( + "application/x-java-applet;jpi-version=1.4") != -1) ) { + + pluginDetected = true; + break; + } + + } + } + +} else if (is_ie5up) { + var javaVersion; + var shell; + try { + // Create WSH(WindowsScriptHost) shell, available on Windows only + shell = new ActiveXObject("WScript.Shell"); + + if (shell != null) { + // Read JRE version from Window Registry + try { + javaVersion = shell.regRead + ("HKEY_LOCAL_MACHINE\\Software\\JavaSoft\\Java Runtime Environment\\CurrentVersion"); + } catch(e) { + // handle exceptions raised by 'shell.regRead(...)' here + // so that the outer try-catch block would receive only + // exceptions raised by 'shell = new ActiveXObject(...)' + } + } + } catch(e) { + window.alert(" Creating ActiveX controls thru script is disabled \n in InternetExplorer security options \n To enable it: \n a. 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    Summary

    + + + + + + + + + + + + + + + + + + + + + +
     Design Name + STERMINATOR
     Fitting Status + Successful
     Software Version + P.20131013
     Device Used + XC9572XL-5-VQ64 +
     Date + 10-26-2021, 9:01PM

    RESOURCES SUMMARY
    + + + + + + + + + + + + + + + +
    Macrocells UsedPterms UsedRegisters UsedPins UsedFunction Block Inputs Used
    28/72  (39%)114/360  (32%)25/72  (35%)39/52  (75%)92/216  (43%)

    PIN RESOURCES
    + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Signal TypeRequiredMapped
     Input 36 36
     Output 2 2
     Bidirectional 0 0
     GCK 1 1
     GTS 0 0
     GSR 0 0
    		 + + + + + + + + + + + + + + + + + + + + + + + + + +
    Pin TypeUsedTotal
     I/O  + 34 47
     GCK/IO 2 3
     GTS/IO 2 2
     GSR/IO 1 1

    GLOBAL RESOURCES
    + + + +
     Signal mapped onto global clock net (GCK1) CLK

    POWER DATA
    + + + + + + + + + + + + + +
     Macrocells in high performance mode (MCHP) 28
     Macrocells in low power mode (MCLP) 0
     Total macrocells used (MC) 28
    + + +
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/summary.js b/sterminator/XC9572XL/STERMINATOR_html/fit/summary.js new file mode 100644 index 0000000..8702822 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/summary.js @@ -0,0 +1,28 @@ +function popWin(url, w, h) { + var win = window.open(url, 'win', + 'toolbar=no,location=no,directories=no,status=no,menubar=no,scrollbars=yes,resizable=yes,width='+w+',height='+h); + win.focus(); +} + +function showTop() { parent.leftnav.showTop(); } + +function showDoc(device) { + var url = docURL; + + if ((device.indexOf("XC2") != -1) && (device.indexOf("S") != -1)) + url = docCr2sURL; + else if (device.indexOf("XC2") != -1) url = docXbrURL; + else if (device.indexOf("XA2") != -1) url = docAcr2URL; + else if (device.indexOf("XCR3") != -1) url = docXpla3URL; + else if (device.indexOf("XV") != -1) url = doc95xvURL; + else if (device.indexOf("XL") != -1) url = doc95xlURL; + else if (device.indexOf("XA") != -1) url = doc95xaURL; + else url = doc95URL; + + popWin(url); +} + +function priceDev(device) { + var url = "http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1816638537/Catalog"; + popWin(url); +} diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/summarydoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/summarydoc.htm new file mode 100644 index 0000000..607f637 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/summarydoc.htm @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + Summary + + + + + + + + +

    +Summary

    + +
    The +Summary section of the HTML report contains several tables summarizing +the fitting results for your design. +
     
    +The Header +table contains the following:  +
      +
    • +The Design +Name
      • + +
    • +The Fitting +Status, which is one of  the following:
      • + +
        +
      • +Successful
        • + +
      • +Design Rule Checking Failed
        • + +
      • +Placement Failed
        • + +
      • +Routing Failed
        • +
      + +
    • +The Software +Version 
      • + +
    • +The Device +Used, with a link to a PDF version of the device documentation
      • + +
    • +The Date +and time of completion
      • +
    +The Resources +Summary table includes: +
      +
    • +The number +and percentage of macrocells used vs total in device 
      • + +
    • +The number +and percentage of product terms used vs total in device 
      • + +
    • +The number +and percentage of registers used vs total in device 
      • + +
    • +The number +and percentage of pins used vs total in device 
      • + +
    • +The number +and percentage of function block inputs used vs total in device 
      • +
    +The Pin +Resources table includes two tables: +
      +
    • +The first +table indicates the requirements of the design, broken up by Signal Type. +The number required and the number mapped onto the device are indicated +for each signal type.
      • + +
    • +The second +table gives the total number of each pin type available in the device, +alongwith the number used.
      • +
    +XPLA3 +only - The Local Control Term Resources table lists the local +control term mapping for each function block: +
      +
    • +Each row +lists the local control term mapping for each of the eight control terms, +LCT0-LCT7, in a function block.
      • + +
    • +The control +term mapping can be:
      • + +
        +
      • +ce - clock +enable
        • + +
      • +clk - clock
        • + +
      • +ee - output +enable
        • + +
      • +sr - set/reset
        • + +
      • +uct1 - universal +control term clock
        • + +
      • +uct2 - universal +control term output enable
        • + +
      • +uct3 - universal +control term set
        • + +
      • +uct4 - universal +control term reset
        • +
      + +
    • +Each LCT +can have some subset of the signals above mapped onto them:
      • + +
        +
      • +LCT0 - sr, +oe
        • + +
      • +LCT1 - sr, +oe
        • + +
      • +LCT2 - sr, +oe
        • + +
      • +LCT3 - sr
        • + +
      • +LCT4 - ce, +clk, sr
        • + +
      • +LCT5 - clk, +sr
        • + +
      • +LCT6 - clk, +oe
        • + +
      • +LCT7 - clk, +uct1/uct2/uct3/uct4
        • +
      +
    +The Global +Resources table indicates the signals used as global signals in the +device. +

    XC9500/XL/XV +only - The Power Data table indicates the number of macrocells +in standard and low power mode. +

    XPLA3 +only - The Block Resources table indicates the number of function +block control terms used vs available and the number of foldback NANDs +used vs available. + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/support.gif b/sterminator/XC9572XL/STERMINATOR_html/fit/support.gif new file mode 100644 index 0000000000000000000000000000000000000000..a154620eb23ea85665f2a9d925132d1cb474dbdb GIT binary patch literal 760 zcmVr;Hg@0hXyRRA=8o0Qvv9YC1O-({V zLLeX@C@3g2G&ECFQ&?D7P*6~4W?$66WbxT$te;|XZeJxOC46^akB4EQp_JXoWHB)@ zz_4SJlY_mzvK}5DiHUimm|~faVWgy&oSck$dTi&>Wy-i?si~VwOG`aHJvur%v$LnP zw5df!MM+6XFE1~yuA#Q4Vn9GZR#sM8T2Q&UtzltTXlPrxxvqbIaZyo7baZDJu-SE}PHjv>IXKwhTUld`_?1@A$mF&RTpHfPsR8goTEOh=VK^j1~-!kdcy;l$Dm3 zkSs8p8ygLuprN9pq@|{(4I42ltSTxq3bC@Yw6(UkxVSSaF)j)&E-xtw#Kp$P$jQpf z%PB7?&M7?*4g=QL*xB0K+}+&{5GW7{)HDwP=;`X~?CtLF?+-L6;ML~<`1$(#{Qds_ z{{lQ1QE$LKfCv*R>?bfo!Gi!U5XcvSKm>dQDpVwp5#Pp+`Yu$U$dTj4k|p&CB=Il+ zfCv%<2$+BY0099L0SKUQQ>Fm_4mN%M#3y2cOcNJ^`kZh|RJ3!SrCR ze>qSHaq{Qxi;9UNz8QkRVG(fUzJ3t9vP%jRL=fO`6~F`u1Z;~%4Va<{4H$~P-M%xq zWF2-Ra4-rUABLD3LiEMhJ>P{BGtc&&pc%4qs3q97(0~N`BT#_O6{z5X0`VZ=f)Fay q;DZrXXy5}sP-x+X`3Qs+gN7V#D9{ZchFGCMHI!%~gaYjl1OPiZ2uK$I literal 0 HcmV?d00001 diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/time.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/time.htm new file mode 100644 index 0000000..2856558 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/time.htm @@ -0,0 +1,4 @@ + +

    +
    + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/tooltips.js b/sterminator/XC9572XL/STERMINATOR_html/fit/tooltips.js new file mode 100644 index 0000000..790ce27 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/tooltips.js @@ -0,0 +1,143 @@ +/* Your are permitted to reuse this code as long as the following copyright + notice is not removed: + + This HTML tip handling is copyright 1998 by insideDHTML.com, LLC. More information about this + code can be found at Inside Dynamic HTML: HTTP://www.insideDHTML.com +*/ + + +// Support for all collection +var allSupport = document.all!=null; + +function setupEventObject(e) { + // Map NS event object to IEs + if (e==null) return; // IE returns + window.event = e; + window.event.fromElement = e.target; + window.event.toElement = e.target; + window.event.srcElement = e.target; + window.event.x = e.x; + window.event.y = e.y; + // Route the event to the original element + // Necessary to make sure _tip is set. + window.event.srcElement.handleEvent(e); +} + +function checkName(src) { + // Look for tooltip in IE + while ((src!=null) && (src._tip==null)) + src = src.parentElement; + return src; +} + +function getElement(elName) { + // Get an element from its ID + if (allSupport) return document.all[elName]; + else return document.layers[elName]; +} + +function writeContents(el, tip) { + // Replace the contents of the tooltip + if (allSupport) + el.innerHTML = tip; + else { + // In NS, insert a table to work around + // stylesheet rendering bug. + // NS fails to apply style sheets when writing + // contents into a positioned element. + el.document.open(); + el.document.write("
    "); + el.document.write(tip); + el.document.write("
    "); + el.document.close(); + } +} + +function getOffset(el, which) { + // Function for IE to calculate position + // of an element. + var amount = el["offset"+which]; + if (which=="Top") amount+=el.offsetHeight; + el = el.offsetParent; + while (el!=null) { + amount+=el["offset"+which]; + el = el.offsetParent; + } + return amount; +} + + +function setPosition(el) { + // Set the position of an element + + src = window.event.srcElement + if (allSupport) { + el.style.pixelTop = getOffset(src, "Top"); + el.style.pixelLeft = getOffset(src, "Left"); + } + else { + el.top = src.y + 20; //window.event.y + 15 + el.left = src.x; //window.event.x + } +} + +function setVisibility(el, bDisplay) { + // Hide or show to tip + if (bDisplay) { + if (allSupport) el.style.visibility = "visible"; + else el.visibility = "show"; + } + else { + if (allSupport) el.style.visibility = "hidden"; + else el.visibility = "hidden"; + } +} + + +function displayContents(tip) { + // Display the tooltip. + var el = getElement("tipBox"); + writeContents(el, tip); + setPosition(el); + setVisibility(el, true); +} + + +function doMouseOver(e) { + // Mouse moves over an element + setupEventObject(e); + var el, tip; + if ((el = checkName(window.event.srcElement))!=null) { + if (!el._display) { + displayContents(el._tip); + el._display = true; + } + } +} + +function doMouseOut(e) { + // Mouse leaves an element + setupEventObject(e); + el = checkName(window.event.srcElement); + var el, tip; + if ((el = checkName(window.event.srcElement))!=null) { + if (el._display) { + if ((el.contains==null) || (!el.contains(window.event.toElement))) { + setVisibility(getElement("tipBox"), false); + el._display = false; + } + } + } +} + +function doLoad() { + // Do Loading + if ((window.document.captureEvents==null) && (!allSupport)) + return; // Not IE4 or NS4 + if (window.document.captureEvents!=null) // NS - capture events + window.document.captureEvents(Event.MOUSEOVER | Event.MOUSEOUT) + window.document.onmouseover = doMouseOver; + window.document.onmouseout = doMouseOut; +} + +window.onload = doLoad; diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/topnav.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/topnav.htm new file mode 100644 index 0000000..ac2b452 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/topnav.htm @@ -0,0 +1,10 @@ + + + + + + + + +
    + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/topnav.js b/sterminator/XC9572XL/STERMINATOR_html/fit/topnav.js new file mode 100644 index 0000000..9e3bb9a --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/topnav.js @@ -0,0 +1,30 @@ +function popWin(url) { + var win = window.open(url, 'win', + 'location=yes,directories=yes,menubar=yes,toolbar=yes,status=yes,scrollbars=yes,resizable=yes,width=800,height=600'); + win.focus(); +} + +function openTab(type, device) { + var url = rootURL; + switch (type) { + case 0: url = rootURL; break; + case 1: + if (device.indexOf('XC2') != -1) url += prodURL + xbrURL; + else if (device.indexOf('XA2') != -1) url += prodURL + acr2URL; + else if (device.indexOf('XCR3') != -1) url += prodURL + xpla3URL; + else if (device.indexOf('XV') != -1) url += prodURL + xc9500xvURL; + else if (device.indexOf('XL') != -1) url += prodURL + xc9500xlURL; + else if (device.indexOf('XA') != -1) url += prodURL + xa9500xlURL; + else url += prodURL + xc9500URL; + break; + case 2: url += marketURL; break; + case 3: url = supportURL; break; + case 4: url += educationURL; break; + case 5: url = buyURL; break; + case 6: url += contactURL; break; + case 7: url += searchURL; break; + default: url = rootURL; + } + + popWin(url); +} diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/unmapinputdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/unmapinputdoc.htm new file mode 100644 index 0000000..fe242d6 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/unmapinputdoc.htm @@ -0,0 +1,65 @@ + + + + + + + + + + +unmapinputdoc + + + + + + + + + + + + + + + + + + + + + + + + +

    Unmapped Inputs

    + +

    This page shows + input signals which were either not mapped or not + routed.

    + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/fit/unmaplogicdoc.htm b/sterminator/XC9572XL/STERMINATOR_html/fit/unmaplogicdoc.htm new file mode 100644 index 0000000..6371313 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/fit/unmaplogicdoc.htm @@ -0,0 +1,68 @@ + + + + + + + + + + +unmaplogicdoc + + + + + + + + + + + + + + + + + + + + + + + + +

    Unmapped Logic

    + +

    This page shows those equations whose + logic was either not placed or not completely + placed in the specified device.

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    Processing...

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    Introduction

    + +

    This report is the result of a static timing analysis of your design + after it has been fit in the device that you selected. The timing values + given represent the worst-case values over the recommended operating conditions + for the part.

    + +

    Overview

    + +

    The timing report consists of a series of sections:

    + +

    Summary

    + +

    This table summarizes the external timing parameters for your device, + including tPD, + tCO, + tSU, + tCYC, + and fSYSTEM. +  For a more + detailed description of the timing model for your device, please refer + to the application notes linked below.

    + +

    Timing Constraints

    + +

    This section reports on any timing constraints that you created for + your design. Timing constraints can be entered using the Constraints Editor + tool, or by editing an Implementation Constraints File directly. For more + information on creating timing constraints, see the Constraints Guide. +

    + +

    Note that if you + did not define any constraints for your design, then the timing analysis + software will automatically create a default set of constraints for you. + These include pad-to-pad, register-to-register, pad-to-register, and period + constraints. A constraint value of 0 ns + will be used for all of these automatically generated constraints. As + a result, all paths listed under each constraint will violate the constraint, + and will have a negative value for slack.

    + +

    Note also that to + limit the size of the report, each path endpoint involved in a timing + path will only be listed once, under a single constraint.  

    + +

    For each timing path listed under a constraint, there is a hyperlink + that can be used to open a window listing the individual internal delay + elements traversed in the path. To understand these delay elements, consult + the Definitions section below, or the following + application notes and white papers:

    + +

    XAPP375: Understanding + the CoolRunner-II + Timing Model

    + +

    WP122: + Using the CoolRunner + XPLA3 Timing Model

    + +

    XAPP071: Using + the XC9500 Timing Model

    + +

    XAPP111: Using + the XC9500XL Timing Model

    + +

    XAPP + 362: Using the XC9500XV Timing Model

    + +

    available in the literature section of www.xilinx.com. +

    + +

    Data Sheet Report

    + +

    This section of the report lists the external timing parameters for + your design. This includes; maximum external clock speed for each clock, + setup and hold times for each registered input, clock-to-output pad timing + for each registered output, clock to setup time for each register-to-register + timing path, and pad-to-pad time for each combinatorial path through your + design.

    + +

    Going Further

    + +

    To do more advanced timing analysis of your design, select the process + Analyze Post-Fit Static Timing + in iSE. This + will run Xilinx's + Timing Analyzer tool interactively.  The + Timing Analyzer provides a powerful, flexible, and easy way to perform + static timing analysis on FPGA + and CPLD designs. + With Timing Analyzer, analysis can be performed immediately after mapping, + placing or routing an FPGA + design, and after fitting and routing a CPLD + design.

    + +

    Timing Analyzer verifies that the delay along a given path or paths + meets specified timing requirements. It organizes and displays data that + allows you to analyze critical paths in a circuit, the cycle time of the + circuit, the delay along any specified path(s), + and the path with the greatest delay. It also provides a quick analysis + of the effect different speed grades have on the same design.  

    + +

    Timing Analyzer performs setup and hold checks (skew analysis). It works + with synchronous systems composed of synchronous elements and combinatorial + logic. In synchronous design, Timing Analyzer takes into account all path + delays, including clock-to-out and setup requirements, while calculating + the worst-case timing of the design.

    + +

    Timing Analyzer creates timing analysis reports based on existing timing + constraints or user specified paths within the program. Timing reports + have a hierarchical browser to quickly jump to different sections of the + reports. Timing paths in reports can be cross probed to synthesis tools + (Exemplar and Synplicity) + and Floorplanner. +

    + +

    There are several ways to issue commands in Timing Analyzer. Timing + Analyzer can be controlled through GUI + features (menu commands) or its comprehensive macro command language facility. + You can select from menus, click toolbar buttons, type keyboard commands + in the console window, and run macros.

    + +

    Definitions

    + +

    Pad to Pad (tPD) +

    + +

    Reports pad to pad paths that start at input pads and end at output + pads. The maximum external pad to pad delay.  Combinatorial + pad-to-pad paths begin at input pads, propagate through one or more levels + of combinatorial logic and end at output pads. Combinatorial paths also + trace through the enable inputs of 3-state controlled pads. Combinatorial + paths are not traced through clock, and asynchronous set and reset inputs + of registers. These paths are also broken at bidirectional pins

    + +

    Clock Pad to Output Pad (tCO) +

    + +

    The maximum external clock pad to output pad delay.  Reports + paths that start at input  pads + trace through clock inputs of  registers + and end at output pads. Paths are not traced through PRE/CLR +  inputs + of registers.  You + can directly specify tCO + for all registered output paths in your design using the Pad-to-Pad timespec. + Clock-Pad-to-Pad paths for global clocks begin at global clock pads, propagate + through global clock buffers, and propagate through the flip-flop Q + output and any number of levels of combinatorial logic and end at the + output pad. Clock-Pad-to-Pad paths for product term clock paths begin + at input pads, propagate through any number of logic levels feeding into + a clock product term, propagate through the flip-flop Q + output and any number of levels of combinatorial logic and end at the + output pad. Clock-Pad-to-Pad paths also trace through the enable inputs + of 3-state controlled pads.

    + +

    Setup to Clock at Pad (tSU + or tSUF)

    + +

    Reports external setup time of data  to + clock at pad. Data path starts at an input pad and ends at register  (Fast + Input Register for tSUF) + D/T  input. + Clock path starts at input pad and ends at the register clock input.  Paths + are not traced through registers. Pin-to-pin setup requirement is not + reported or guaranteed for product-term clocks derived from macrocell + feedback signals.

    + +

    The minimum required setup time for flip-flops.  You + can specify the tSU + (setup-to-clock) for all inputs in your design relative to a global clock + or product term clock. Each tSU + OFFSET timespec involves an input path and a clock path. Input paths start + at input pads, propagate through input buffers and any number of combinatorial + logic levels before ending at a flip-flop D/T input, including the receiving + flip-flop's tSU.  Input + paths are not traced through flip-flop clock pins, asynchronous set/reset + inputs or bidirectional I/O pins. Global clock paths start at global clock + pads, propagate through global clock buffers and end at the flip-flop + clock pin. Product term clock paths start at input pads, propagate through + a single level of logic implemented in a clock product term and end at + the flip-flop clock pin.

    + +

    Clock to Setup (tCYC)

    + +

    Register to register cycle time. Includes source register tCO and destination + register tSU.

    + +

    Note that when the + computed Maximum Clock Speed is limited by tCYC, it is computed assuming + that all registers are rising-edge sensitive.

    + +

    fSYSTEM

    + +

    Maximum clock operating frequency.  You + can specify the fSYSTEM (clock frequency or period) for all registered + paths in your design using a Register-to-Register timespec. Register-to-Register + paths begin at flip-flop clock inputs, propagate through the flip-flop + Q output and any number of levels of combinatorial logic and end at the + receiving flip-flop D/T input, including the receiving flip-flop's tSU. + When these flip-flops are clocked by the same clock, the delay on this + path is equivalent to the cycle time of the clock. Registered paths do + not propagate through clock, and asynchronous set and reset inputs of + registers as shown below. These paths are also broken at bidirectional + pins.

    + +

     

    + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/cpldta_style.css b/sterminator/XC9572XL/STERMINATOR_html/tim/cpldta_style.css new file mode 100644 index 0000000..4b82019 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/cpldta_style.css @@ -0,0 +1,144 @@ + + + + +.cpldta_text_report_header { + font-style: normal; + font-weight: bold; + font-size: 25pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + +.cpldta_text_section_header { + font-style: normal; + font-weight: bold; + font-size: 15pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + +.cpldta_text_subsection_header { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_warnings_header { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFFFCC; } + + +.cpldta_text_normal { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_text_normal_bold { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_constraint_description_normal { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} +.cpldta_constraint_description_bold { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_constraint_name { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} + + +.cpldta_constraint_name_error { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left; + background-color: #FFCCCC; } + + +.cpldta_time_value { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + + +.cpldta_time_value_error { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFCCCC; } + + +.cpldta_delaytable_header { + font-style: normal; + font-weight: bold; + font-size: 12pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFFFCC; } +.cpldta_constraint_header { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left; + background-color: #FFFFCC; } +.cpldta_time_header { + font-style: normal; + font-weight: bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center; + background-color: #FFFFCC; } +.cpldta_text_caption { + font-style: normal; + font-weight: Bold; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + + +.cpldta_datasheet_pathname { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: left;} +.cpldta_datasheet_time_value { + font-style: normal; + font-weight: normal; + font-size: 10pt; + font-family: Arial, Helvetica, sans-serif; + text-align: center;} + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/genreport.htm b/sterminator/XC9572XL/STERMINATOR_html/tim/genreport.htm new file mode 100644 index 0000000..43aca47 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/genreport.htm @@ -0,0 +1,17 @@ + + +Reports + + +; + + + + + + + +<body bgcolor="#FFFFFF" text="#000000"> +</body> + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/leftnav.htm b/sterminator/XC9572XL/STERMINATOR_html/tim/leftnav.htm new file mode 100644 index 0000000..e72761d --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/leftnav.htm @@ -0,0 +1,37 @@ + + +Timing Navigation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    +
    Timing Report
    +
     Description
     Summary
     Constraints
     Definitions
      
    + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/report.htm b/sterminator/XC9572XL/STERMINATOR_html/tim/report.htm new file mode 100644 index 0000000..43aca47 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/report.htm @@ -0,0 +1,17 @@ + + +Reports + + +; + + + + + + + +<body bgcolor="#FFFFFF" text="#000000"> +</body> + + diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/timing_report.htm b/sterminator/XC9572XL/STERMINATOR_html/tim/timing_report.htm new file mode 100644 index 0000000..9dbf72d --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/timing_report.htm @@ -0,0 +1,1036 @@ + + + + + + + +Timing report for STERMINATOR + + + +

    Timing Report

    +
    Need help reading this report?

    + + + + + + + + + + + + + + + + + + +
    Design NameSTERMINATOR
    Device, Speed (SpeedFile Version)XC9572XL, -5 (3.0)
    Date Created Tue Oct 26 21:02:01 2021 +
    Created By Timing Report Generator: version P.20131013
    Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
    +

    Summary

    + + + + + + + + + + +
    Notes and Warnings
    Note: This design contains no timing constraints.
    Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Performance Summary
    Min. Clock Period5.600 ns.
    Max. Clock Frequency (fSYSTEM)178.571 MHz.
    Limited by Clock Pulse Width for CLK
    Clock to Setup (tCYC)5.600 ns.
    Pad to Pad Delay (tPD)10.300 ns.
    Setup to Clock at the Pad (tSU)3.700 ns.
    Clock Pad to Output Pad Delay (tCO)12.200 ns.
    +
    +

    Timing Constraints

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Constraint NameRequirement (ns)Delay (ns)PathsPaths Failing
    TS10000.00.000
    AUTO_TS_F2F0.05.611
    AUTO_TS_P2P0.012.24444
    AUTO_TS_P2F0.04.8111111
    AUTO_TS_F2P0.011.12525
    +
    +
    + +

    Constraint: TS1000

    + + + + + + + + +
    Description: PERIOD:PERIOD_CLK:0.000 nS
    PathRequirement (ns)Delay (ns)Slack (ns)
    +
    +
    +     +

    Constraint: AUTO_TS_F2F

    + + + + + + + + + + + + + + + + +
    Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
    PathRequirement (ns)Delay (ns)Slack (ns)
    NA.Q to NA.D0.0005.600-5.600
     +
    +
    + +

    Constraint: AUTO_TS_P2P

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
    PathRequirement (ns)Delay (ns)Slack (ns)
    CLK to nSTERM0.00012.200-12.200
    A<10> to nSTERM0.00010.300-10.300
    A<12> to nSTERM0.00010.300-10.300
     +
    +
    + +

    Constraint: AUTO_TS_P2F

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
    PathRequirement (ns)Delay (ns)Slack (ns)
    A<10> to NC<8>.D0.0004.800-4.800
    A<11> to NR<0>.D0.0004.800-4.800
    A<12> to NR<1>.D0.0004.800-4.800
     +
    +
    + +

    Constraint: AUTO_TS_F2P

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
    PathRequirement (ns)Delay (ns)Slack (ns)
    NC<8>.Q to nSTERM0.00011.100-11.100
    NR<11>.Q to nSTERM0.00011.100-11.100
    NR<1>.Q to nSTERM0.00011.100-11.100
     +
    +
    +
    Number of constraints not met: 4
    +
    + +

    Data Sheet Report

    + +

    Maximum External Clock Speeds

    + + + + + + + + + + + +
    ClockfEXT (MHz)Reason
    CLK178.571Limited by Clock Pulse Width for CLK
    +
    + +

    Setup/Hold Times for Clocks

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Setup/Hold Times for Clock CLK
    Source PadSetup to clk (edge) Hold to clk (edge)
    A<10>3.7000.000
    A<11>3.7000.000
    A<12>3.7000.000
    A<13>3.7000.000
    A<14>3.7000.000
    A<15>3.7000.000
    A<16>3.7000.000
    A<17>3.7000.000
    A<18>3.7000.000
    A<19>3.7000.000
    A<20>3.7000.000
    A<21>3.7000.000
    A<22>3.7000.000
    A<23>3.7000.000
    A<24>3.7000.000
    A<25>3.7000.000
    A<2>3.7000.000
    A<3>3.7000.000
    A<4>3.7000.000
    A<5>3.7000.000
    A<6>3.7000.000
    A<7>3.7000.000
    A<8>3.7000.000
    A<9>3.7000.000
    CMD<0>3.7000.000
    CMD<1>3.7000.000

    +
    + +

    Clock to Pad Timing

    + + + + + + + + + + +
    Clock CLK to Pad
    Destination PadClock (edge) to Pad
    nSTERM12.200

    +
    + +

    Clock to Setup Times for Clocks

    + + + + + + + + + + + + +
    Clock to Setup for clock CLK
    SourceDestinationDelay
    NA.QNA.D5.600

    +
    + +

    Pad to Pad List

    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Source PadDestination PadDelay
    A<10>nSTERM10.300
    A<12>nSTERM10.300
    A<17>nSTERM10.300
    A<22>nSTERM10.300
    STERMnSTERM10.300
    A<11>nSTERM10.000
    A<14>nSTERM10.000
    A<18>nSTERM10.000
    A<20>nSTERM10.000
    A<7>nSTERM10.000
    A<13>nSTERM9.700
    A<16>nSTERM9.700
    A<28>nSTERM9.700
    A<29>nSTERM9.700
    A<2>nSTERM9.700
    A<30>nSTERM9.700
    A<3>nSTERM9.700
    A<21>nSTERM9.400
    A<23>nSTERM9.400
    A<24>nSTERM9.400
    A<25>nSTERM9.400
    A<6>nSTERM9.400
    A<19>nSTERM9.100
    A<4>nSTERM9.100
    A<5>nSTERM9.100
    A<8>nSTERM9.100
    A<9>nSTERM9.100
    A<15>nSTERM8.400
    A<31>nSTERM8.400
    FC<2>nSTERM8.400
    A<13>nFPUCS5.000
    A<14>nFPUCS5.000
    A<15>nFPUCS5.000
    A<16>nFPUCS5.000
    A<17>nFPUCS5.000
    A<18>nFPUCS5.000
    A<19>nFPUCS5.000
    CLKdatnFPUCS5.000
    FC<0>nFPUCS5.000
    FC<0>nSTERM5.000
    FC<1>nFPUCS5.000
    FC<2>nFPUCS5.000
    nASnFPUCS5.000
    +
    +
    +
    Number of paths analyzed: +181 +
    Number of Timing errors: +181 +
    Analysis Completed: Tue Oct 26 21:02:01 2021 + +
    + diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/toc.css b/sterminator/XC9572XL/STERMINATOR_html/tim/toc.css new file mode 100644 index 0000000..29af0e1 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/toc.css @@ -0,0 +1,36 @@ +.HEADING { + font-size: 15px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #000000; + text-align: normal; + margin-left: 0px; } +.Fitting { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #000000; + text-align: normal; + margin-left: 0px; } +.SECONDARY-NAV { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #FFFFFF; + margin-left: 0px; + text-decoration: none; ; + list-style-type: disc ; + list-style-position: inside } +.Timing { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #333333; + margin-left: 0px; + text-decoration: none; ; + list-style-type: disc ; + list-style-position: inside } +.Timing-Error { + font-size: 11px; + font-family: Arial, Geneva, Verdana, Helvetica; + font-weight: bold; color: #990000; + margin-left: 0px; + text-decoration: none; ; + list-style-type: disc ; + list-style-position: inside } diff --git a/sterminator/XC9572XL/STERMINATOR_html/tim/topnav.htm b/sterminator/XC9572XL/STERMINATOR_html/tim/topnav.htm new file mode 100644 index 0000000..00e11b8 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_html/tim/topnav.htm @@ -0,0 +1,31 @@ + + +CPLD Reports Banner + + + + + + + + + + + + + + +
     
    + + + + +   
    + + + + + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_ngdbuild.xrpt b/sterminator/XC9572XL/STERMINATOR_ngdbuild.xrpt new file mode 100644 index 0000000..fd9ad59 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_ngdbuild.xrpt @@ -0,0 +1,99 @@ + + + + + + +
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    + + + + diff --git a/sterminator/XC9572XL/STERMINATOR_summary.html b/sterminator/XC9572XL/STERMINATOR_summary.html new file mode 100644 index 0000000..ea3153d --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_summary.html @@ -0,0 +1,81 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    STERMINATOR Project Status (10/26/2021 - 21:02:02)
    Project File:STERMINATOR.xiseParser Errors: No Errors
    Module Name:STERMINATORImplementation State:Fitted
    Target Device:xc9572xl-5VQ64
    • Errors:
    		 +No Errors
    Product Version:ISE 14.7
    • Warnings:
    		2 Warnings (2 new)
    Design Goal:Balanced
    • Routing Results:
    		 + 
    Design Strategy:Xilinx Default (unlocked)
    • Timing Constraints:
    		 
    Environment: + +System Settings +
    • Final Timing Score:
    		  
    + + + + + + + + + + + + 
    + + + + + + + +
    Detailed Reports [-]
    Report NameStatusGeneratedErrorsWarningsInfos
    Synthesis ReportCurrentTue Oct 26 21:01:44 202102 Warnings (2 new)0
    Translation ReportCurrentTue Oct 26 21:01:47 2021000
    CPLD Fitter Report (Text)CurrentTue Oct 26 21:01:52 202101 Warning (1 new)0
    Power Report     
    + 
    + + + +
    Secondary Reports [-]
    Report NameStatusGenerated
    Post-Fit Simulation Model Report  
    + + +
    Date Generated: 10/26/2021 - 21:02:02
    + \ No newline at end of file diff --git a/sterminator/XC9572XL/STERMINATOR_xst.xrpt b/sterminator/XC9572XL/STERMINATOR_xst.xrpt new file mode 100644 index 0000000..76204c2 --- /dev/null +++ b/sterminator/XC9572XL/STERMINATOR_xst.xrpt @@ -0,0 +1,140 @@ + + + + + + +
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    +
    + + + +
    + + + diff --git a/sterminator/XC9572XL/_ngo/netlist.lst b/sterminator/XC9572XL/_ngo/netlist.lst new file mode 100644 index 0000000..5e67cdd --- /dev/null +++ b/sterminator/XC9572XL/_ngo/netlist.lst @@ -0,0 +1,2 @@ +C:\Users\zanek\Documents\GitHub\SE-030\sterminator\XC9572XL\STERMINATOR.ngc 1635296504 +OK diff --git a/sterminator/XC9572XL/_xmsgs/cpldfit.xmsgs b/sterminator/XC9572XL/_xmsgs/cpldfit.xmsgs new file mode 100644 index 0000000..02f75b0 --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/cpldfit.xmsgs @@ -0,0 +1,12 @@ + + + +Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'STERMINATOR.ise'. + + + + diff --git a/sterminator/XC9572XL/_xmsgs/hprep6.xmsgs b/sterminator/XC9572XL/_xmsgs/hprep6.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/hprep6.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/sterminator/XC9572XL/_xmsgs/ngdbuild.xmsgs b/sterminator/XC9572XL/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/sterminator/XC9572XL/_xmsgs/pn_parser.xmsgs b/sterminator/XC9572XL/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..dfaaaa5 --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "C:/Users/zanek/Documents/GitHub/SE-030/sterminator/STERMINATOR.v" into library work + + + + diff --git a/sterminator/XC9572XL/_xmsgs/taengine.xmsgs b/sterminator/XC9572XL/_xmsgs/taengine.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/taengine.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/sterminator/XC9572XL/_xmsgs/tsim.xmsgs b/sterminator/XC9572XL/_xmsgs/tsim.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/tsim.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/sterminator/XC9572XL/_xmsgs/xst.xmsgs b/sterminator/XC9572XL/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..c3182cd --- /dev/null +++ b/sterminator/XC9572XL/_xmsgs/xst.xmsgs @@ -0,0 +1,15 @@ + + + +Input <A<27:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + +Input <nWE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + + + diff --git a/sterminator/XC9572XL/iseconfig/STERMINATOR.projectmgr b/sterminator/XC9572XL/iseconfig/STERMINATOR.projectmgr new file mode 100644 index 0000000..357f7a8 --- /dev/null +++ b/sterminator/XC9572XL/iseconfig/STERMINATOR.projectmgr @@ -0,0 +1,76 @@ + + + + + + + + + 2 + + + STERMINATOR (C:/Users/zanek/Documents/GitHub/SE-030/sterminator/STERMINATOR.v) + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010f0000000100000003000000000000000100000003 + true + STERMINATOR (C:/Users/zanek/Documents/GitHub/SE-030/sterminator/STERMINATOR.v) + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002d70000000100000000 + false + ..\STERMINATOR.v + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + false + work + + 000000ff00000000000000020000011b0000011b01000000050100000002 + Implementation + + + 1 + Design Utilities + Implement Design/Configure Target Device + Implement Design/Optional Implementation Tools/Generate Timing + Implement Design/Synthesize - XST + User Constraints + + + Generate Timing + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000fb000000010000000100000000000000000000000064ffffffff000000810000000000000001000000fb0000000100000000 + false + Generate Timing + + diff --git a/sterminator/XC9572XL/iseconfig/STERMINATOR.xreport b/sterminator/XC9572XL/iseconfig/STERMINATOR.xreport new file mode 100644 index 0000000..b924c07 --- /dev/null +++ b/sterminator/XC9572XL/iseconfig/STERMINATOR.xreport @@ -0,0 +1,215 @@ + + +
    + 2021-10-26T21:00:45 + STERMINATOR + Unknown + C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL/iseconfig/STERMINATOR.xreport + C:/Users/zanek/Documents/GitHub/SE-030/sterminator/XC9572XL\ + 2021-10-26T06:35:56 + false +
    + + + + + + + + + + + + + + + + + + + + + + + +     diff --git a/sterminator/XC9572XL/tmperr.err b/sterminator/XC9572XL/tmperr.err new file mode 100644 index 0000000..e69de29 diff --git a/sterminator/XC9572XL/xlnx_auto_0_xdb/cst.xbcd b/sterminator/XC9572XL/xlnx_auto_0_xdb/cst.xbcd new file mode 100644 index 0000000000000000000000000000000000000000..c832410665bef281e05a042fc852acf41574eaab GIT binary patch literal 233 zcmV(;5Tf$ z6Iys-G|(rh5b`Yyg1)VvYgTu|w;DJzvuDm6W_`w(c&vGMy|vHAp_fls5Hd_Nz@n-X z9>bD|BS2P%5g3M!?x+p^sSegya~$CWbToD})O=2G&4%&x*njZ>@Aor|D%EIM literal 0 HcmV?d00001 diff --git a/sterminator/XC9572XL/xst/work/hdllib.ref b/sterminator/XC9572XL/xst/work/hdllib.ref new file mode 100644 index 0000000..c39399a --- /dev/null +++ b/sterminator/XC9572XL/xst/work/hdllib.ref @@ -0,0 +1 @@ +MO STERMINATOR NULL ../STERMINATOR.v vlg7C/_s_t_e_r_m_i_n_a_t_o_r.bin 1635296502 diff --git a/sterminator/XC9572XL/xst/work/vlg7C/_s_t_e_r_m_i_n_a_t_o_r.bin b/sterminator/XC9572XL/xst/work/vlg7C/_s_t_e_r_m_i_n_a_t_o_r.bin new file mode 100644 index 0000000000000000000000000000000000000000..ae95212080f3e62cb5d83509800d680ed510548d GIT binary patch literal 8372 zcmcIo2bdmJ6`k45rfmWtA-(*`E=eE>OF&437&c2t5J+Pah;$=h0gR%CCdvX9kZz+Y zRq0K7QB+W=BA|kzf`Ud9x7dv1Gg-kUcw`|!&v9>}t+ z5y*i7EiIcYUNWbB{`L#nmMm;4~s0CC=|FK~=euBDSFbWIh*o;>%QY_S%{NFVmxhuniH$M{;jZ0rfui1k^UHgVF) z*|^rCK_2XVV>rN^>I-vkx&Whqu>hA;!`>3|On~Lth5+@m=kw}L2kP3k!SDA?nvLHZ zfcn|~9&AWZ@qY-$iV_lCKPcAkxlc|DY#%Vlac&21U8H?+6Sr(?Fq2Ivi^b~hajJ@ZRP@!d3D;sbyqfv*D>0#^gK0sp}u(dEMdUN9KDyaa|-IO6Sq?Ex;qd|)B46Tn&S3@imo8#QVBL*Q~h#ILb~t zlkqzDVnA%*=-g8_>a?Tp40gRUxyQc>AGRL$+u&ZzX7j97suA{na`yh+mg?iBIlQ4B zTk&4Hat(#gI>5TJL(T>OWdo!0AYgqtdtXWP&gA6L)*yy$J^LL<3KFx~PpwkJU>`1L z?<M|M?nq&q(EHSvP^UPCtufukrRrJWn-rE4fW{3iob z+>d&;F;KStG)@IJmGe6#rycDL#IUv4?ulb=u&2EKm9cos(s#$Tzr@iK^Ld|Z4 zZWC(i?69MoJkpC>$x@(ntZR7NO0WYK4tC~wus8+N#s`mL=1M3WMjk9q!91wyLhy$b zTsT!cSe$}+;_wNlm>nb(jt37Gr(hl(_84>fJOvl-b2o}pFwcO7P&|rBctCB?_)E0L}Iu1vpjMqbZoS zJ|TD)1&<>c4C7=dyPI{yuR;LZuGJz|v0x()yK(3>WckGHET28$$DO!G607la75h<- z-8+fp{#urBm8e6GcZbHJV_f>a$g>ZyUySvdd!heW32*ze$J9-yPECy5Js$@?ned$a zCxA~S{6}2h9k%^lZh{Gwn7CPdDx9ZUl(=Aan~an&>yyI~M3{ZPn<0Efj`=&boU;NTLzdR05u zOsTkLhXY5HgnSYFmlFO!*FOW>mtAg#9M`N_*QjjGni+(~Z!)%{s;aF|!A2f-akj<@ zXLoDlEMt~^1^rhOzQgrnVEdZO<87c)*rUDTNsg_mHi!w7!ROvf*F-14_6^{8*_q=6 zDeTes*~NBZRkef@DTC8zh;${M2;0fPDegx-J5>sMv=>RDeY2`s!VM{d>+QXCCFTeF zw}J1-4mta-6!vKUCW&@hRkehZpvT3YL>o9=8tE!T|1*KJ+>d&8Hc+-XEEtaer4!os z7{ms-V2d1V_6QC>@g~xM>=`c~^ydNR0_P{W&T#!4*e-CHZ@O{PlbzSHN!O(5|3l!S z5T9KPqHNL@3`cz2Tf2loY|sj}$ib%1O!>q~Ye0=j%oT{c9Jn&!f8hFMuwCWy6v%PX zQ=He9lCDY9|3|>JAwIhfMA@V*7>=*Q&UQV6*dP~dk%O&o)FH=7Ye03;2QfDTHvzXK z{57uM2-~eLx3EXEPdEy&8Hb+j#|g(H_a_N=JGh@E9AoMGl=Jp613A8t=>tc%l60QY zKL_rJvC!H0u6P%4FYs&NVfV3TGh{o>A_pJk*Yo?A;C@9PHpupw2GI_zgtI#{a`3+! zxQ84YaKjgW2)pzT#}ZL=OI%kNH3!2>b?kF!6f;+(V(x z<}SxIFb;m&L(;hhzXg8hImLsrb^W9BTX@cR-HoGT^nv;)@CWzjyr;Pw$7399^&Tso z<9Q7DQ^JF?@%+{K>7Fx=$2dAhAE=K5Pq=^Qc)ExFR#x_k%t^_pqPXFE78|; z@XK{g!vDi{eiFax@=VBa0cVm&v;Rv_fL$ENtMwIUYZ?9MgT}RZBjNeZ{AR+v<~pwt zMb>Kt;+R@hv}{wgTGZOL&mssdx4T`5qAhZ8)Tz+wKJn$>IA$xx3KFV_&2h8&0 z#O(hBx$Z|<2E`1J<1hqzjTs=9Rqr2t zkYhby05Gt~TlN0n3prU7fB27hzJB8W_BF9*P#6{GF$frvL@?7}U}%xg{h5$sin-qW zW+7kPBC{BS##>dZCeC&SjWCJhzgG%=P%+|sbo2wqF^vMoL>_WkPTq25Img9V&p8%3 bn-ZR;3ecSJ9M=X#F1P