]> Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf PLL.ucf WarpLC.ncdWarpLC.ncdWarpLC.pcfWarpLC.pcfxc6slx9C-2PRODUCTION 1.23 2013-10-1313INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;220000108.586Paths for end point CPU_nSTERM (E11.PAD), 22 paths 6.414l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPCPU_nSTERM8.5860.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPCPU_nSTERM4SLICE_X16Y51.CLKFSBCLKSLICE_X16Y51.AMUXTshcko1.081l2pre/n0023<14>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DPSLICE_X20Y50.D3net11.014l2pre/n0023<11>SLICE_X20Y50.COUTTopcyd0.312l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CMUXTcinc0.302l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.640l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.254CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet12.998CPU_nSTERM_OBUFE11.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.9314.6558.58645.854.26.422l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPCPU_nSTERM8.5780.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPCPU_nSTERM3SLICE_X16Y51.CLKFSBCLKSLICE_X16Y51.BTshcko1.106l2pre/n0023<14>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DPSLICE_X20Y51.A4net10.968l2pre/n0023<14>SLICE_X20Y51.CMUXTopac0.630l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.640l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.254CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet12.998CPU_nSTERM_OBUFE11.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM3.9724.6068.57846.353.76.445l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPCPU_nSTERM8.5550.00015.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPCPU_nSTERM4SLICE_X20Y55.CLKFSBCLKSLICE_X20Y55.AMUXTshcko1.081l2pre/n0023<21>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DPSLICE_X20Y50.A3net10.821l2pre/n0023<2>SLICE_X20Y50.COUTTopcya0.474l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CINnet10.003l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>SLICE_X20Y51.CMUXTcinc0.302l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.640l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.254CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet12.998CPU_nSTERM_OBUFE11.PADTioop1.982CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM4.0934.4628.55547.852.2Fastest Paths: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns; Paths for end point CPU_nSTERM (E11.PAD), 22 paths 3.066l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPCPU_nSTERM2SLICE_X20Y55.CLKFSBCLKSLICE_X20Y55.BTshcko0.449l2pre/n0023<21>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DPSLICE_X20Y56.A5net10.194l2pre/n0023<21>SLICE_X20Y56.ATilo0.156CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet11.568CPU_nSTERM_OBUFE11.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.3041.7623.06642.557.53.557l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPCPU_nSTERM3SLICE_X20Y52.CLKFSBCLKSLICE_X20Y52.BTshcko0.449l2pre/n0023<18>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DPSLICE_X20Y51.C5net10.150l2pre/n0023<18>SLICE_X20Y51.CMUXTopcc0.250l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.285l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.156CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet11.568CPU_nSTERM_OBUFE11.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.5542.0033.55743.756.33.629l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPCPU_nSTERM0.0000.0000.000l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPCPU_nSTERM3SLICE_X20Y52.CLKFSBCLKSLICE_X20Y52.ATshcko0.441l2pre/n0023<18>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DPSLICE_X20Y51.C4net10.230l2pre/n0023<19>SLICE_X20Y51.CMUXTopcc0.250l2pre/RDTag[20]_RDATag[20]_equal_5_ol2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6>SLICE_X20Y56.A6net10.285l2pre/RDTag[20]_RDATag[20]_equal_5_oSLICE_X20Y56.ATilo0.156CPU_nSTERM_OBUFCPU_nSTERM1E11.Onet11.568CPU_nSTERM_OBUFE11.PADTioop0.699CPU_nSTERMCPU_nSTERM_OBUFCPU_nSTERM1.5462.0833.62942.657.40CLKIN0000220398.586Sun Oct 31 15:23:24 2021 TraceTrace Settings Peak Memory Usage: 214 MB