cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: STERMINATOR Date: 10-26-2021, 9:01PM Device Used: XC9572XL-5-VQ64 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 28 /72 ( 39%) 114 /360 ( 32%) 92 /216 ( 43%) 25 /72 ( 35%) 39 /52 ( 75%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 1/18 54/54* 52/90 6/13 FB2 9/18 14/54 18/90 13/13* FB3 18/18* 24/54 44/90 8/14 FB4 0/18 0/54 0/90 12/12* ----- ----- ----- ----- 28/72 92/216 114/360 39/52 * - Resource is exhausted ** Global Control Resources ** Signal 'CLK' mapped onto global clock net GCK1. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 36 36 | I/O : 34 46 Output : 2 2 | GCK/IO : 2 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 39 39 ** Power Data ** There are 28 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'STERMINATOR.ise'. ************************* Summary of Mapped Logic ************************ ** 2 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State nSTERM 2 4 FB2_2 60 I/O O STD FAST nFPUCS 2 12 FB3_2 22 I/O O STD FAST ** 26 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$BIN_STEP$409 52 54 FB1_13 STD NR<9> 2 3 FB2_11 STD RESET NR<1> 2 3 FB2_12 STD RESET NR<12> 2 3 FB2_13 STD RESET NR<11> 2 3 FB2_14 STD RESET NR<10> 2 3 FB2_15 STD RESET NR<0> 2 3 FB2_16 STD RESET NB<1> 2 3 FB2_17 STD RESET NB<0> 2 3 FB2_18 STD RESET NR<8> 2 3 FB3_1 STD RESET NR<7> 2 3 FB3_3 STD RESET NR<6> 2 3 FB3_4 STD RESET NR<5> 2 3 FB3_5 STD RESET NR<4> 2 3 FB3_6 STD RESET NR<3> 2 3 FB3_7 STD RESET NR<2> 2 3 FB3_8 STD RESET NC<0> 2 3 FB3_9 STD RESET NA 2 3 FB3_10 STD RESET NC<8> 3 11 FB3_11 STD RESET NC<7> 3 10 FB3_12 STD RESET NC<6> 3 9 FB3_13 STD RESET NC<5> 3 8 FB3_14 STD RESET NC<4> 3 7 FB3_15 STD RESET NC<3> 3 6 FB3_16 STD RESET NC<2> 3 5 FB3_17 STD RESET NC<1> 3 4 FB3_18 STD RESET ** 37 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use A<8> FB1_5 9 I/O I A<25> FB1_6 10 I/O I A<9> FB1_8 11 I/O I CLK FB1_9 15~ GCK/I/O GCK CMD<1> FB1_11 16 GCK/I/O I A<4> FB1_17 20 I/O I A<17> FB2_3 58 I/O I STERM FB2_4 59 I/O I A<29> FB2_5 61 I/O I A<30> FB2_6 62 I/O I A<5> FB2_8 63 I/O I A<12> FB2_9 64 GSR/I/O I A<31> FB2_10 1 I/O I A<11> FB2_11 2 GTS/I/O I A<15> FB2_12 4 I/O I CLKdat FB2_14 5 GTS/I/O I nAS FB2_15 6 I/O I A<7> FB2_17 7 I/O I FC<0> FB3_3 31 I/O I A<16> FB3_6 34 I/O I CMD<0> FB3_10 39 I/O I A<2> FB3_12 40 I/O I A<22> FB3_14 35 I/O I A<20> FB3_15 36 I/O I A<19> FB3_16 42 I/O I A<3> FB4_2 43 I/O I A<28> FB4_3 46 I/O I A<6> FB4_4 47 I/O I A<13> FB4_5 44 I/O I A<18> FB4_6 49 I/O I FC<1> FB4_8 45 I/O I A<14> FB4_10 51 I/O I A<23> FB4_11 48 I/O I A<24> FB4_12 52 I/O I A<21> FB4_14 50 I/O I FC<2> FB4_15 56 I/O I A<10> FB4_17 57 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 54/0 Number of signals used by logic mapping into function block: 54 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 8 I/O (unused) 0 0 0 5 FB1_3 12 I/O (unused) 0 0 0 5 FB1_4 13 I/O (unused) 0 0 0 5 FB1_5 9 I/O I (unused) 0 0 0 5 FB1_6 10 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 \/2 3 FB1_8 11 I/O I (unused) 0 0 \/5 0 FB1_9 15 GCK/I/O GCK (unused) 0 0 \/5 0 FB1_10 18 I/O (b) (unused) 0 0 \/5 0 FB1_11 16 GCK/I/O I (unused) 0 0 \/5 0 FB1_12 23 I/O (b) $OpTx$BIN_STEP$409 52 47<- 0 0 FB1_13 (b) (b) (unused) 0 0 /\5 0 FB1_14 17 GCK/I/O (b) (unused) 0 0 /\5 0 FB1_15 19 I/O (b) (unused) 0 0 /\5 0 FB1_16 (b) (b) (unused) 0 0 /\5 0 FB1_17 20 I/O I (unused) 0 0 /\5 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: A<10> 19: A<2> 37: NC<5> 2: A<11> 20: A<30> 38: NC<6> 3: A<12> 21: A<31> 39: NC<7> 4: A<13> 22: A<3> 40: NC<8> 5: A<14> 23: A<4> 41: NR<0> 6: A<15> 24: A<5> 42: NR<10> 7: A<16> 25: A<6> 43: NR<11> 8: A<17> 26: A<7> 44: NR<12> 9: A<18> 27: A<8> 45: NR<1> 10: A<19> 28: A<9> 46: NR<2> 11: A<20> 29: FC<2> 47: NR<3> 12: A<21> 30: NB<0> 48: NR<4> 13: A<22> 31: NB<1> 49: NR<5> 14: A<23> 32: NC<0> 50: NR<6> 15: A<24> 33: NC<1> 51: NR<7> 16: A<25> 34: NC<2> 52: NR<8> 17: A<28> 35: NC<3> 53: NR<9> 18: A<29> 36: NC<4> 54: STERM Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs $OpTx$BIN_STEP$409 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX...... 54 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 14/40 Number of signals used by logic mapping into function block: 14 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) nSTERM 2 0 0 3 FB2_2 60 I/O O (unused) 0 0 0 5 FB2_3 58 I/O I (unused) 0 0 0 5 FB2_4 59 I/O I (unused) 0 0 0 5 FB2_5 61 I/O I (unused) 0 0 0 5 FB2_6 62 I/O I (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 63 I/O I (unused) 0 0 0 5 FB2_9 64 GSR/I/O I (unused) 0 0 0 5 FB2_10 1 I/O I NR<9> 2 0 0 3 FB2_11 2 GTS/I/O I NR<1> 2 0 0 3 FB2_12 4 I/O I NR<12> 2 0 0 3 FB2_13 (b) (b) NR<11> 2 0 0 3 FB2_14 5 GTS/I/O I NR<10> 2 0 0 3 FB2_15 6 I/O I NR<0> 2 0 0 3 FB2_16 (b) (b) NB<1> 2 0 0 3 FB2_17 7 I/O I NB<0> 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$BIN_STEP$409 6: A<22> 11: CMD<1> 2: A<11> 7: A<23> 12: FC<0> 3: A<12> 8: A<24> 13: NA 4: A<20> 9: A<25> 14: STERM 5: A<21> 10: CMD<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs nSTERM X..........XXX.......................... 4 NR<9> ...X.....XX............................. 3 NR<1> ..X......XX............................. 3 NR<12> ......X..XX............................. 3 NR<11> .....X...XX............................. 3 NR<10> ....X....XX............................. 3 NR<0> .X.......XX............................. 3 NB<1> ........XXX............................. 3 NB<0> .......X.XX............................. 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 24/30 Number of signals used by logic mapping into function block: 24 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use NR<8> 2 0 0 3 FB3_1 (b) (b) nFPUCS 2 0 0 3 FB3_2 22 I/O O NR<7> 2 0 0 3 FB3_3 31 I/O I NR<6> 2 0 0 3 FB3_4 32 I/O (b) NR<5> 2 0 0 3 FB3_5 24 I/O (b) NR<4> 2 0 0 3 FB3_6 34 I/O I NR<3> 2 0 0 3 FB3_7 (b) (b) NR<2> 2 0 0 3 FB3_8 25 I/O (b) NC<0> 2 0 0 3 FB3_9 27 I/O (b) NA 2 0 0 3 FB3_10 39 I/O I NC<8> 3 0 0 2 FB3_11 33 I/O (b) NC<7> 3 0 0 2 FB3_12 40 I/O I NC<6> 3 0 0 2 FB3_13 (b) (b) NC<5> 3 0 0 2 FB3_14 35 I/O I NC<4> 3 0 0 2 FB3_15 36 I/O I NC<3> 3 0 0 2 FB3_16 42 I/O I NC<2> 3 0 0 2 FB3_17 38 I/O (b) NC<1> 3 0 0 2 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: A<10> 9: A<2> 17: CLKdat 2: A<13> 10: A<3> 18: CMD<0> 3: A<14> 11: A<4> 19: CMD<1> 4: A<15> 12: A<5> 20: FC<0> 5: A<16> 13: A<6> 21: FC<1> 6: A<17> 14: A<7> 22: FC<2> 7: A<18> 15: A<8> 23: NA 8: A<19> 16: A<9> 24: nAS Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs NR<8> .......X.........XX..................... 3 nFPUCS .XXXXXXX........X..XXX.X................ 12 NR<7> ......X..........XX..................... 3 NR<6> .....X...........XX..................... 3 NR<5> ....X............XX..................... 3 NR<4> ...X.............XX..................... 3 NR<3> ..X..............XX..................... 3 NR<2> .X...............XX..................... 3 NC<0> ........X........XX..................... 3 NA .................XX...X................. 3 NC<8> X.......XXXXXXXX.XX..................... 11 NC<7> ........XXXXXXXX.XX..................... 10 NC<6> ........XXXXXXX..XX..................... 9 NC<5> ........XXXXXX...XX..................... 8 NC<4> ........XXXXX....XX..................... 7 NC<3> ........XXXX.....XX..................... 6 NC<2> ........XXX......XX..................... 5 NC<1> ........XX.......XX..................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 43 I/O I (unused) 0 0 0 5 FB4_3 46 I/O I (unused) 0 0 0 5 FB4_4 47 I/O I (unused) 0 0 0 5 FB4_5 44 I/O I (unused) 0 0 0 5 FB4_6 49 I/O I (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 45 I/O I (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 51 I/O I (unused) 0 0 0 5 FB4_11 48 I/O I (unused) 0 0 0 5 FB4_12 52 I/O I (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 50 I/O I (unused) 0 0 0 5 FB4_15 56 I/O I (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 57 I/O I (unused) 0 0 0 5 FB4_18 (b) ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$BIN_STEP$409 <= ((EXP9_.EXP) OR (A(5) AND NOT NC(3) AND NOT STERM) OR (NOT A(5) AND NC(3) AND NOT STERM) OR (A(9) AND NOT NC(7) AND NOT STERM) OR (NOT A(9) AND NC(7) AND NOT STERM) OR (A(19) AND NOT NR(8) AND NOT STERM) OR (EXP12_.EXP) OR (NOT A(24) AND NB(0) AND NOT STERM) OR (A(4) AND NOT NC(2) AND NOT STERM) OR (NOT A(4) AND NC(2) AND NOT STERM) OR (A(8) AND NOT NC(6) AND NOT STERM) OR (NOT A(8) AND NC(6) AND NOT STERM) OR (NOT FC(2) AND NOT STERM) OR (A(31) AND NOT STERM) OR (A(15) AND NOT NR(4) AND NOT STERM) OR (NOT A(15) AND NR(4) AND NOT STERM) OR (NOT A(19) AND NR(8) AND NOT STERM)); FDCPE_NA: FDCPE port map (NA,NA_D,CLK,'0','0'); NA_D <= ((CMD(0) AND NOT CMD(1)) OR (NOT CMD(1) AND NA)); FDCPE_NB0: FDCPE port map (NB(0),A(24),CLK,'0','0',NB_CE(0)); NB_CE(0) <= (CMD(0) AND NOT CMD(1)); FDCPE_NB1: FDCPE port map (NB(1),A(25),CLK,'0','0',NB_CE(1)); NB_CE(1) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC0: FDCPE port map (NC(0),NOT A(2),CLK,'0','0',NC_CE(0)); NC_CE(0) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC1: FDCPE port map (NC(1),NC_D(1),CLK,'0','0',NC_CE(1)); NC_D(1) <= A(2) XOR NC_D(1) <= A(3); NC_CE(1) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC2: FDCPE port map (NC(2),NC_D(2),CLK,'0','0',NC_CE(2)); NC_D(2) <= A(4) XOR NC_D(2) <= (A(2) AND A(3)); NC_CE(2) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC3: FDCPE port map (NC(3),NC_D(3),CLK,'0','0',NC_CE(3)); NC_D(3) <= A(5) XOR NC_D(3) <= (A(2) AND A(3) AND A(4)); NC_CE(3) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC4: FDCPE port map (NC(4),NC_D(4),CLK,'0','0',NC_CE(4)); NC_D(4) <= A(6) XOR NC_D(4) <= (A(2) AND A(3) AND A(4) AND A(5)); NC_CE(4) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC5: FDCPE port map (NC(5),NC_D(5),CLK,'0','0',NC_CE(5)); NC_D(5) <= A(7) XOR NC_D(5) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6)); NC_CE(5) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC6: FDCPE port map (NC(6),NC_D(6),CLK,'0','0',NC_CE(6)); NC_D(6) <= A(8) XOR NC_D(6) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7)); NC_CE(6) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC7: FDCPE port map (NC(7),NC_D(7),CLK,'0','0',NC_CE(7)); NC_D(7) <= A(9) XOR NC_D(7) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND A(8)); NC_CE(7) <= (CMD(0) AND NOT CMD(1)); FDCPE_NC8: FDCPE port map (NC(8),NC_D(8),CLK,'0','0',NC_CE(8)); NC_D(8) <= A(10) XOR NC_D(8) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND A(8) AND A(9)); NC_CE(8) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR0: FDCPE port map (NR(0),A(11),CLK,'0','0',NR_CE(0)); NR_CE(0) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR1: FDCPE port map (NR(1),A(12),CLK,'0','0',NR_CE(1)); NR_CE(1) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR2: FDCPE port map (NR(2),A(13),CLK,'0','0',NR_CE(2)); NR_CE(2) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR3: FDCPE port map (NR(3),A(14),CLK,'0','0',NR_CE(3)); NR_CE(3) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR4: FDCPE port map (NR(4),A(15),CLK,'0','0',NR_CE(4)); NR_CE(4) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR5: FDCPE port map (NR(5),A(16),CLK,'0','0',NR_CE(5)); NR_CE(5) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR6: FDCPE port map (NR(6),A(17),CLK,'0','0',NR_CE(6)); NR_CE(6) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR7: FDCPE port map (NR(7),A(18),CLK,'0','0',NR_CE(7)); NR_CE(7) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR8: FDCPE port map (NR(8),A(19),CLK,'0','0',NR_CE(8)); NR_CE(8) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR9: FDCPE port map (NR(9),A(20),CLK,'0','0',NR_CE(9)); NR_CE(9) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR10: FDCPE port map (NR(10),A(21),CLK,'0','0',NR_CE(10)); NR_CE(10) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR11: FDCPE port map (NR(11),A(22),CLK,'0','0',NR_CE(11)); NR_CE(11) <= (CMD(0) AND NOT CMD(1)); FDCPE_NR12: FDCPE port map (NR(12),A(23),CLK,'0','0',NR_CE(12)); NR_CE(12) <= (CMD(0) AND NOT CMD(1)); nFPUCS <= NOT (((FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT nAS) OR (FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT CLKdat))); nSTERM <= NOT (((STERM AND NOT $OpTx$BIN_STEP$409) OR (NOT FC(0) AND NA AND NOT $OpTx$BIN_STEP$409))); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572XL-5-VQ64 ----------------------------------------------- /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \ | 49 32 | | 50 31 | | 51 30 | | 52 29 | | 53 28 | | 54 27 | | 55 26 | | 56 XC9572XL-5-VQ64 25 | | 57 24 | | 58 23 | | 59 22 | | 60 21 | | 61 20 | | 62 19 | | 63 18 | | 64 17 | \ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 / ----------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 A<31> 33 KPR 2 A<11> 34 A<16> 3 VCC 35 A<22> 4 A<15> 36 A<20> 5 CLKdat 37 VCC 6 nAS 38 KPR 7 A<7> 39 CMD<0> 8 KPR 40 A<2> 9 A<8> 41 GND 10 A<25> 42 A<19> 11 A<9> 43 A<3> 12 KPR 44 A<13> 13 KPR 45 FC<1> 14 GND 46 A<28> 15 CLK 47 A<6> 16 CMD<1> 48 A<23> 17 KPR 49 A<18> 18 KPR 50 A<21> 19 KPR 51 A<14> 20 A<4> 52 A<24> 21 GND 53 TDO 22 nFPUCS 54 GND 23 KPR 55 VCC 24 KPR 56 FC<2> 25 KPR 57 A<10> 26 VCC 58 A<17> 27 KPR 59 STERM 28 TDI 60 nSTERM 29 TMS 61 A<29> 30 TCK 62 A<30> 31 FC<0> 63 A<5> 32 KPR 64 A<12> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-5-VQ64 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25