Equations

********** Mapped Logic **********

$OpTx$BIN_STEP$409 <= ((EXP9_.EXP)
      OR (A(5) AND NOT NC(3) AND NOT STERM)
      OR (NOT A(5) AND NC(3) AND NOT STERM)
      OR (A(9) AND NOT NC(7) AND NOT STERM)
      OR (NOT A(9) AND NC(7) AND NOT STERM)
      OR (A(19) AND NOT NR(8) AND NOT STERM)
      OR (EXP12_.EXP)
      OR (NOT A(24) AND NB(0) AND NOT STERM)
      OR (A(4) AND NOT NC(2) AND NOT STERM)
      OR (NOT A(4) AND NC(2) AND NOT STERM)
      OR (A(8) AND NOT NC(6) AND NOT STERM)
      OR (NOT A(8) AND NC(6) AND NOT STERM)
      OR (NOT FC(2) AND NOT STERM)
      OR (A(31) AND NOT STERM)
      OR (A(15) AND NOT NR(4) AND NOT STERM)
      OR (NOT A(15) AND NR(4) AND NOT STERM)
      OR (NOT A(19) AND NR(8) AND NOT STERM));

FDCPE_NA: FDCPE port map (NA,NA_D,CLK,'0','0');
NA_D <= ((CMD(0) AND NOT CMD(1))
OR (NOT CMD(1) AND NA));

FDCPE_NB0: FDCPE port map (NB(0),A(24),CLK,'0','0',NB_CE(0));
NB_CE(0) <= (CMD(0) AND NOT CMD(1));

FDCPE_NB1: FDCPE port map (NB(1),A(25),CLK,'0','0',NB_CE(1));
NB_CE(1) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC0: FDCPE port map (NC(0),NOT A(2),CLK,'0','0',NC_CE(0));
NC_CE(0) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC1: FDCPE port map (NC(1),NC_D(1),CLK,'0','0',NC_CE(1));
     NC_D(1) <= A(2)
      XOR
     NC_D(1) <= A(3);
     NC_CE(1) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC2: FDCPE port map (NC(2),NC_D(2),CLK,'0','0',NC_CE(2));
     NC_D(2) <= A(4)
      XOR
     NC_D(2) <= (A(2) AND A(3));
     NC_CE(2) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC3: FDCPE port map (NC(3),NC_D(3),CLK,'0','0',NC_CE(3));
     NC_D(3) <= A(5)
      XOR
     NC_D(3) <= (A(2) AND A(3) AND A(4));
     NC_CE(3) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC4: FDCPE port map (NC(4),NC_D(4),CLK,'0','0',NC_CE(4));
     NC_D(4) <= A(6)
      XOR
     NC_D(4) <= (A(2) AND A(3) AND A(4) AND A(5));
     NC_CE(4) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC5: FDCPE port map (NC(5),NC_D(5),CLK,'0','0',NC_CE(5));
     NC_D(5) <= A(7)
      XOR
     NC_D(5) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6));
     NC_CE(5) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC6: FDCPE port map (NC(6),NC_D(6),CLK,'0','0',NC_CE(6));
     NC_D(6) <= A(8)
      XOR
     NC_D(6) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7));
     NC_CE(6) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC7: FDCPE port map (NC(7),NC_D(7),CLK,'0','0',NC_CE(7));
     NC_D(7) <= A(9)
      XOR
     NC_D(7) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND
      A(8));
     NC_CE(7) <= (CMD(0) AND NOT CMD(1));

FDCPE_NC8: FDCPE port map (NC(8),NC_D(8),CLK,'0','0',NC_CE(8));
     NC_D(8) <= A(10)
      XOR
     NC_D(8) <= (A(2) AND A(3) AND A(4) AND A(5) AND A(6) AND A(7) AND
      A(8) AND A(9));
     NC_CE(8) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR0: FDCPE port map (NR(0),A(11),CLK,'0','0',NR_CE(0));
NR_CE(0) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR1: FDCPE port map (NR(1),A(12),CLK,'0','0',NR_CE(1));
NR_CE(1) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR2: FDCPE port map (NR(2),A(13),CLK,'0','0',NR_CE(2));
NR_CE(2) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR3: FDCPE port map (NR(3),A(14),CLK,'0','0',NR_CE(3));
NR_CE(3) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR4: FDCPE port map (NR(4),A(15),CLK,'0','0',NR_CE(4));
NR_CE(4) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR5: FDCPE port map (NR(5),A(16),CLK,'0','0',NR_CE(5));
NR_CE(5) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR6: FDCPE port map (NR(6),A(17),CLK,'0','0',NR_CE(6));
NR_CE(6) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR7: FDCPE port map (NR(7),A(18),CLK,'0','0',NR_CE(7));
NR_CE(7) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR8: FDCPE port map (NR(8),A(19),CLK,'0','0',NR_CE(8));
NR_CE(8) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR9: FDCPE port map (NR(9),A(20),CLK,'0','0',NR_CE(9));
NR_CE(9) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR10: FDCPE port map (NR(10),A(21),CLK,'0','0',NR_CE(10));
NR_CE(10) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR11: FDCPE port map (NR(11),A(22),CLK,'0','0',NR_CE(11));
NR_CE(11) <= (CMD(0) AND NOT CMD(1));

FDCPE_NR12: FDCPE port map (NR(12),A(23),CLK,'0','0',NR_CE(12));
NR_CE(12) <= (CMD(0) AND NOT CMD(1));

nFPUCS <= NOT (((FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND
      NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT nAS)
      OR (FC(1) AND FC(0) AND A(17) AND A(13) AND NOT A(14) AND NOT A(15) AND
      NOT A(16) AND NOT A(18) AND NOT A(19) AND FC(2) AND NOT CLKdat)));

nSTERM <= NOT (((STERM AND NOT $OpTx$BIN_STEP$409)
OR (NOT FC(0) AND NA AND NOT $OpTx$BIN_STEP$409)));