65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:47:14 10/29/2021
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// Design Name:
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// Module Name: CLKGEN
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ClkGen(
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input CLKIN,
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input CLKFB_IN,
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output CLKFB_OUT,
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output FSBCLK,
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output reg CPUCLKr,
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output CPUCLK,
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output FPUCLK,
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output RAMCLK0,
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output RAMCLK1);
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PLL pll (
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.CLKIN(CLKIN),
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.CLKFB_IN(CLKFB_IN),
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.CLKFB_OUT(CLKFB_OUT),
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.FSBCLK(FSBCLK));
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always @(posedge FSBCLK) CPUCLKr <= ~CPUCLKr;
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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CPUCLK_inst (.Q(CPUCLK), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(~CPUCLKr), .D1(~CPUCLKr),
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.R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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FPUCLK_inst (.Q(FPUCLK), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(CPUCLKr), .D1(CPUCLKr),
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.R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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RAMCLK0_inst (.Q(RAMCLK0), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(1'b0), .D1(1'b1),
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.R(1'b0), .S(1'b0));
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ODDR2 #(.DDR_ALIGNMENT("C0"), .INIT(1'b0), .SRTYPE("ASYNC"))
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RAMCLK1_inst (.Q(RAMCLK1), .CE(1'b1),
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.C0(FSBCLK), .C1(~FSBCLK),
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.D0(1'b0), .D1(1'b1),
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.R(1'b0), .S(1'b0));
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endmodule
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