54 lines
971 B
Verilog
54 lines
971 B
Verilog
/* L2 Cache Way
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* 1024 x 47 bits
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* (1) Valid
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* (14) Tag - {A[30], A[28], A[25:2]}
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* (32) Data
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*/
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module L2CacheWay(
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input CLK,
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input CPUCLKr,
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input [27:2] RDA,
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output [31:0] RDD,
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output RDMatch,
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input [27:2] WRA,
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input [31:0] WRD,
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input [3:0] WRM,
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input TS,
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input WR,
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input CLR,
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input ALL);
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/* Read address */
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wire [15:0] RDATag = RDA[27:12];
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wire [11:0] RDAIndex = RDA[11:2];
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/* Write address */
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wire [15:0] WRATag = WRA[27:12];
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wire [11:0] WRAIndex = WRA[11:2];
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/* Cache way RAM */
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wire [31:0] TSD;
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wire [15:0] RDTag;
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wire [15:0] TSTag;
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wire RDValid;
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wire TSValid;
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assign RDMatch = RDValid && RDTag==RDATag;
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wire TSMatch = TSValid && TSTag==WRATag;
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L2WayRAM way (
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.clka(CLK),
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.ena(~CPUCLKr),
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.wea(1'b0),
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.addra(RDAIndex),
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.dina(50'b0),
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.douta({RDValid, RDTag, RDD}),
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.clkb(CLK),
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.enb(1'b0),
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.web(1'b0),
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.addrb(WRAIndex),
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.dinb({~CLR, WRATag, WRD}),
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.doutb({TSValid, TSTag, TSD}));
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endmodule
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