Warp-LC/fpga/PLL.ucf

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NET "CLKIN" TNM_NET = CLKIN;
#NET "FSB_A[31]" TNM_NET = FSB_A;
#NET "FSB_A[30]" TNM_NET = FSB_A;
#NET "FSB_A[29]" TNM_NET = FSB_A;
#NET "FSB_A[28]" TNM_NET = FSB_A;
NET "FSB_A[27]" TNM_NET = FSB_A;
NET "FSB_A[26]" TNM_NET = FSB_A;
NET "FSB_A[25]" TNM_NET = FSB_A;
NET "FSB_A[24]" TNM_NET = FSB_A;
NET "FSB_A[23]" TNM_NET = FSB_A;
NET "FSB_A[22]" TNM_NET = FSB_A;
NET "FSB_A[21]" TNM_NET = FSB_A;
NET "FSB_A[20]" TNM_NET = FSB_A;
NET "FSB_A[19]" TNM_NET = FSB_A;
NET "FSB_A[18]" TNM_NET = FSB_A;
NET "FSB_A[17]" TNM_NET = FSB_A;
NET "FSB_A[16]" TNM_NET = FSB_A;
NET "FSB_A[15]" TNM_NET = FSB_A;
NET "FSB_A[14]" TNM_NET = FSB_A;
NET "FSB_A[13]" TNM_NET = FSB_A;
NET "FSB_A[12]" TNM_NET = FSB_A;
NET "FSB_A[11]" TNM_NET = FSB_A;
NET "FSB_A[10]" TNM_NET = FSB_A;
NET "FSB_A[9]" TNM_NET = FSB_A;
NET "FSB_A[8]" TNM_NET = FSB_A;
NET "FSB_A[7]" TNM_NET = FSB_A;
NET "FSB_A[6]" TNM_NET = FSB_A;
NET "FSB_A[5]" TNM_NET = FSB_A;
NET "FSB_A[4]" TNM_NET = FSB_A;
NET "FSB_A[3]" TNM_NET = FSB_A;
NET "FSB_A[2]" TNM_NET = FSB_A;
#NET "FSB_A[1]" TNM_NET = FSB_A;
#NET "FSB_A[0]" TNM_NET = FSB_A;
NET "CPU_nSTERM" TNM_NET = CPU_nSTERM;
NET CLKFB_OUT FEEDBACK = 160ps NET CLKFB_IN;
#TIMESPEC TS_CLKIN = PERIOD "CLKIN" 30 ns HIGH 50%;
#NET "FSB_A[*]" OFFSET = IN 12ns VALID 12ns BEFORE CLKIN;
#NET "CPU_nAS" OFFSET = IN 15ns VALID 15ns BEFORE CLKIN;
#TIMESPEC TS_CPU_nSTERM_A = FROM "FSB_A" TO "CPU_nSTERM" 15ns;
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2021/10/31