225 lines
14 KiB
XML
225 lines
14 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="WarpLC.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_VERILOG_INSTTEMPLATE" xil_pn:name="L2Cache.tfi"/>
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<file xil_pn:fileType="FILE_VERILOG_INSTTEMPLATE" xil_pn:name="L2CacheWay.tfi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="WarpLC.bld"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="WarpLC.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="WarpLC.lso"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC.ncd" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="WarpLC.ngc"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="WarpLC.ngd"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="WarpLC.ngr"/>
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<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="WarpLC.pad"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="WarpLC.par" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="WarpLC.pcf" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="WarpLC.prj"/>
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<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="WarpLC.ptwx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="WarpLC.stx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="WarpLC.syr"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="WarpLC.twr" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="WarpLC.twx" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="WarpLC.unroutes" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_XPI" xil_pn:name="WarpLC.xpi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="WarpLC.xst"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="WarpLC_envsettings.html"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="WarpLC_fpga_editor.log"/>
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<file xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC_guide.ncd" xil_pn:origination="imported"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="WarpLC_map.map" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="WarpLC_map.mrp" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="WarpLC_map.ncd" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="WarpLC_map.ngm" xil_pn:subbranch="Map"/>
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<file xil_pn:fileType="FILE_PSR" xil_pn:name="WarpLC_map.psr"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_map.xrpt"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_ngdbuild.xrpt"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="WarpLC_pad.csv" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="WarpLC_pad.txt" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_par.xrpt"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="WarpLC_preroute.twr" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="WarpLC_preroute.twx" xil_pn:subbranch="Map"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="WarpLC_summary.html"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="WarpLC_summary.xml"/>
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<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="WarpLC_usage.xml"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="WarpLC_xst.xrpt"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3515295135630071778" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="InputAdded"/>
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<status xil_pn:value="InputRemoved"/>
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</transform>
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<transform xil_pn:end_ts="1635827575" xil_pn:in_ck="792064813085319307" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4864019295268560826" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ipcore_dir/L2WayRAM.ngc"/>
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<outfile xil_pn:name="ipcore_dir/L2WayRAM.v"/>
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<outfile xil_pn:name="ipcore_dir/PLL.v"/>
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<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.ngc"/>
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<outfile xil_pn:name="ipcore_dir/PrefetchDataRAM.v"/>
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<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.ngc"/>
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<outfile xil_pn:name="ipcore_dir/PrefetchTagRAM.v"/>
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</transform>
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<transform xil_pn:end_ts="1635827575" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6691162141195559328" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1635827575" xil_pn:in_ck="8930453670915267207" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745411629038" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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</transform>
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<transform xil_pn:end_ts="1635827575" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="5917552782042024336" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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</transform>
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<transform xil_pn:end_ts="1635827583" xil_pn:in_ck="6037603080330662639" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1250938673410109993" xil_pn:start_ts="1635827575">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="InputAdded"/>
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<status xil_pn:value="InputChanged"/>
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<outfile xil_pn:name="WarpLC.lso"/>
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<outfile xil_pn:name="WarpLC.ngc"/>
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<outfile xil_pn:name="WarpLC.ngr"/>
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<outfile xil_pn:name="WarpLC.prj"/>
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<outfile xil_pn:name="WarpLC.stx"/>
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<outfile xil_pn:name="WarpLC.syr"/>
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<outfile xil_pn:name="WarpLC.xst"/>
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<outfile xil_pn:name="WarpLC_xst.xrpt"/>
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<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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</transform>
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<transform xil_pn:end_ts="1635827583" xil_pn:in_ck="-7789573437496007849" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5069202360897704523" xil_pn:start_ts="1635827583">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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</transform>
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<transform xil_pn:end_ts="1635827589" xil_pn:in_ck="1514068505672127241" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2511870374322119143" xil_pn:start_ts="1635827583">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<outfile xil_pn:name="WarpLC.bld"/>
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<outfile xil_pn:name="WarpLC.ngd"/>
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<outfile xil_pn:name="WarpLC_ngdbuild.xrpt"/>
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<outfile xil_pn:name="_ngo"/>
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<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1635827613" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-5057403149233638808" xil_pn:start_ts="1635827589">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<outfile xil_pn:name="WarpLC.pcf"/>
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<outfile xil_pn:name="WarpLC_map.map"/>
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<outfile xil_pn:name="WarpLC_map.mrp"/>
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<outfile xil_pn:name="WarpLC_map.ncd"/>
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<outfile xil_pn:name="WarpLC_map.ngm"/>
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<outfile xil_pn:name="WarpLC_map.psr"/>
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<outfile xil_pn:name="WarpLC_map.xrpt"/>
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<outfile xil_pn:name="WarpLC_summary.xml"/>
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<outfile xil_pn:name="WarpLC_usage.xml"/>
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<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1635827357" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3071725558691267845" xil_pn:start_ts="1635827347">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="InputChanged"/>
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<outfile xil_pn:name="WarpLC.ncd"/>
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<outfile xil_pn:name="WarpLC.pad"/>
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<outfile xil_pn:name="WarpLC.par"/>
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<outfile xil_pn:name="WarpLC.ptwx"/>
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<outfile xil_pn:name="WarpLC.unroutes"/>
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<outfile xil_pn:name="WarpLC.xpi"/>
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<outfile xil_pn:name="WarpLC_pad.csv"/>
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<outfile xil_pn:name="WarpLC_pad.txt"/>
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<outfile xil_pn:name="WarpLC_par.xrpt"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1635505623" xil_pn:in_ck="4179226981374028" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1635505621">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="InputAdded"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="InputRemoved"/>
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</transform>
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<transform xil_pn:end_ts="1635827362" xil_pn:in_ck="5584679923051828224" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="-4489077157552092322" xil_pn:start_ts="1635827357">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="WarpLC.twr"/>
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<outfile xil_pn:name="WarpLC.twx"/>
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1635827618" xil_pn:in_ck="-665988527316138595" xil_pn:name="TRAN_preRouteTrce" xil_pn:prop_ck="722859607460791352" xil_pn:start_ts="1635827613">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="WarpLC_preroute.twr"/>
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<outfile xil_pn:name="WarpLC_preroute.twx"/>
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1635705810" xil_pn:in_ck="5584679923051828356" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1635705810">
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<status xil_pn:value="InputAdded"/>
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<status xil_pn:value="InputRemoved"/>
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</transform>
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</transforms>
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</generated_project>
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