184 lines
8.1 KiB
Plaintext
184 lines
8.1 KiB
Plaintext
Release 14.7 par P.20131013 (nt)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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DOG-PC:: Tue Nov 02 00:29:08 2021
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par -w -intstyle ise -ol high -xe c -mt 4 WarpLC_map.ncd WarpLC.ncd WarpLC.pcf
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Constraints file: WarpLC.pcf.
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Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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"WarpLC" is an NCD, version 3.2, device xc6slx9, package ftg256, speed -2
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INFO:Par:338 -
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Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
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not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
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speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
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design even if the time specs can not be met. If you are looking for the best possible design speed available from a
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long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
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speed improvements have shrunk to the point that the time specs are not expected to be met.
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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Device speed data version: "PRODUCTION 1.23 2013-10-13".
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Device Utilization Summary:
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Slice Logic Utilization:
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Number of Slice Registers: 1 out of 11,440 1%
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Number used as Flip Flops: 1
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 294 out of 5,720 5%
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Number used as logic: 214 out of 5,720 3%
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Number using O6 output only: 183
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Number using O5 output only: 5
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Number using O5 and O6: 26
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Number used as ROM: 0
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Number used as Memory: 80 out of 1,440 5%
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Number used as Dual Port RAM: 80
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Number using O6 output only: 80
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Number using O5 output only: 0
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Number using O5 and O6: 0
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Number used as Single Port RAM: 0
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Number used as Shift Register: 0
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Slice Logic Distribution:
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Number of occupied Slices: 113 out of 1,430 7%
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Number of MUXCYs used: 72 out of 2,860 2%
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Number of LUT Flip Flop pairs used: 295
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Number with an unused Flip Flop: 294 out of 295 99%
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Number with an unused LUT: 1 out of 295 1%
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Number of fully used LUT-FF pairs: 0 out of 295 0%
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Number of slice register sites lost
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to control set restrictions: 0 out of 11,440 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 66 out of 186 35%
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IOB Flip Flops: 5
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Specific Feature Utilization:
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Number of RAMB16BWERs: 28 out of 32 87%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
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Number used as BUFIO2s: 1
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Number used as BUFIO2_2CLKs: 0
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
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Number used as BUFIO2FBs: 1
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Number used as BUFIO2FB_2CLKs: 0
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Number of BUFG/BUFGMUXs: 2 out of 16 12%
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Number used as BUFGs: 2
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
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Number used as OLOGIC2s: 5
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Number used as OSERDES2s: 0
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 16 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 1 out of 2 50%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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PAR will use up to 4 processors
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Starting Multi-threaded Router
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Phase 1 : 5140 unrouted; REAL time: 3 secs
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Phase 2 : 1769 unrouted; REAL time: 3 secs
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Phase 3 : 1550 unrouted; REAL time: 4 secs
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Phase 4 : 1550 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 secs
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Updating file: WarpLC.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 secs
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Total REAL time to Router completion: 6 secs
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Total CPU time to Router completion (all processors): 7 secs
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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|cg/pll/clkfb_bufg_ou | | | | | |
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| t | BUFGMUX_X2Y3| No | 2 | 0.062 | 2.139 |
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+---------------------+--------------+------+------+------------+-------------+
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| FSBCLK | BUFGMUX_X3Y13| No | 37 | 0.652 | 2.088 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 7 secs
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Total CPU time to PAR completion (all processors): 8 secs
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Peak Memory Usage: 258 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Timing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 1
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Writing design to file WarpLC.ncd
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PAR done!
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