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Warp-LC
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Warp-LC/fpga/WarpLC.pcf

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//! **************************************************************************
// Written by: Map P.20131013 on Tue Nov 02 00:33:32 2021
//! **************************************************************************
SCHEMATIC START;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKA;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKB;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKA;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKB;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKA;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKB;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKA;
PIN
prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>
= BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
PINNAME CLKB;
PIN cg/CPUCLK_inst_pins<1> = BEL "cg/CPUCLK_inst" PINNAME CK0;
PIN cg/CPUCLK_inst_pins<2> = BEL "cg/CPUCLK_inst" PINNAME CK1;
PIN cg/FPUCLK_inst_pins<1> = BEL "cg/FPUCLK_inst" PINNAME CK0;
PIN cg/FPUCLK_inst_pins<2> = BEL "cg/FPUCLK_inst" PINNAME CK1;
PIN cg/RAMCLK0_inst_pins<1> = BEL "cg/RAMCLK0_inst" PINNAME CK0;
PIN cg/RAMCLK0_inst_pins<2> = BEL "cg/RAMCLK0_inst" PINNAME CK1;
PIN cg/RAMCLK1_inst_pins<1> = BEL "cg/RAMCLK1_inst" PINNAME CK0;
PIN cg/RAMCLK1_inst_pins<2> = BEL "cg/RAMCLK1_inst" PINNAME CK1;
TIMEGRP cg_pll_clkout0 = BEL "cg/CPUCLKr" BEL "cg/pll/clkout1_buf" PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<28>"
PIN
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram_pins<29>"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW"
PIN "cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
"cg/CPUCLK_inst_pins<1>" PIN "cg/CPUCLK_inst_pins<2>" PIN
"cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN
"cg/FPUCLK_inst_pins<1>" PIN "cg/FPUCLK_inst_pins<2>" PIN
"cg/RAMCLK0_inst_pins<1>" PIN "cg/RAMCLK0_inst_pins<2>" PIN
"cg/RAMCLK0_inst_pins<1>" PIN "cg/RAMCLK0_inst_pins<2>" PIN
"cg/RAMCLK1_inst_pins<1>" PIN "cg/RAMCLK1_inst_pins<2>" PIN
"cg/RAMCLK1_inst_pins<1>" PIN "cg/RAMCLK1_inst_pins<2>";
PIN cg/pll/clkfbout_oddr_pins<1> = BEL "cg/pll/clkfbout_oddr" PINNAME CK0;
PIN cg/pll/clkfbout_oddr_pins<2> = BEL "cg/pll/clkfbout_oddr" PINNAME CK1;
TIMEGRP cg_pll_clkfbout = BEL "cg/pll/clkfbout_bufg" PIN
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>" PIN
"cg/pll/clkfbout_oddr_pins<1>" PIN "cg/pll/clkfbout_oddr_pins<2>";
TIMEGRP FSB_A = BEL "FSB_D<31>" BEL "FSB_D<30>" BEL "FSB_D<29>" BEL
"FSB_D<28>" BEL "FSB_D<27>" BEL "FSB_D<26>" BEL "FSB_D<25>" BEL
"FSB_D<24>" BEL "FSB_D<23>" BEL "FSB_D<22>" BEL "FSB_D<21>" BEL
"FSB_D<20>" BEL "FSB_D<19>" BEL "FSB_D<18>" BEL "FSB_D<17>" BEL
"FSB_D<16>" BEL "FSB_D<15>" BEL "FSB_D<14>" BEL "FSB_D<13>" BEL
"FSB_D<12>" BEL "FSB_D<11>" BEL "FSB_D<10>" BEL "FSB_D<9>" BEL
"FSB_D<8>" BEL "FSB_D<7>" BEL "FSB_D<6>" BEL "FSB_D<5>" BEL "FSB_D<4>"
BEL "FSB_D<3>" BEL "FSB_D<2>" BEL "FSB_D<1>" BEL "FSB_D<0>" BEL
"CPU_nSTERM" BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
BEL
"prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH"
BEL
"prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW";
TIMEGRP CPU_nSTERM = BEL "CPU_nSTERM";
PIN SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0> = BEL
"SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0" PINNAME DIVCLK;
PIN cg/pll/pll_base_inst/PLL_ADV_pins<2> = BEL "cg/pll/pll_base_inst/PLL_ADV"
PINNAME CLKIN1;
TIMEGRP CLKIN = PIN "SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0_pins<0>" PIN
"cg/pll/pll_base_inst/PLL_ADV_pins<2>";
BEL "CLKFB_OUT" FEEDBACK = 0.16 ns BEL "CLKFB_IN";
SCHEMATIC END;
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