340 lines
141 KiB
XML
340 lines
141 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE twReport [
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<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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twDebug*, twFoot?, twClientInfo?)>
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<!ATTLIST twReport version CDATA "10,4">
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<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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<!ELEMENT twExecVer (#PCDATA)>
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<!ELEMENT twCopyright (#PCDATA)>
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<!ELEMENT twCmdLine (#PCDATA)>
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<!ELEMENT twDesign (#PCDATA)>
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<!ELEMENT twPCF (#PCDATA)>
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<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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<!ELEMENT twDevName (#PCDATA)>
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<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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<!ELEMENT twSpeedGrade (#PCDATA)>
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<!ELEMENT twSpeedVer (#PCDATA)>
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<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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<!ELEMENT twItemLimit (#PCDATA)>
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<!ELEMENT twUnconst EMPTY>
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<!ELEMENT twUnconstLimit (#PCDATA)>
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<!ELEMENT twEnvVar EMPTY>
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<!ATTLIST twEnvVar name CDATA #REQUIRED>
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<!ATTLIST twEnvVar description CDATA #REQUIRED>
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<!ELEMENT twWarn (#PCDATA)>
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<!ELEMENT twInfo (#PCDATA)>
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<!ELEMENT twDebug (#PCDATA)>
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<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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<!ELEMENT twProc (#PCDATA)>
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<!ELEMENT twTemp (#PCDATA)>
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<!ELEMENT twVolt (#PCDATA)>
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<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
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<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twCycles (twSigConn+)>
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<!ATTLIST twCycles twNum CDATA #REQUIRED>
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<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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<!ELEMENT twSig (#PCDATA)>
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<!ELEMENT twDriver (#PCDATA)>
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<!ELEMENT twLoad (#PCDATA)>
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<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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<!ATTLIST twConst twConstType (NET |
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NETDELAY |
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NETSKEW |
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PATH |
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DEFPERIOD |
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UNCONSTPATH |
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DEFPATH |
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PATH2SETUP |
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UNCONSTPATH2SETUP |
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PATHCLASS |
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PATHDELAY |
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PERIOD |
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FREQUENCY |
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PATHBLOCK |
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OFFSET |
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OFFSETIN |
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OFFSETINCLOCK |
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UNCONSTOFFSETINCLOCK |
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OFFSETINDELAY |
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OFFSETINMOD |
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OFFSETOUT |
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OFFSETOUTCLOCK |
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UNCONSTOFFSETOUTCLOCK |
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OFFSETOUTDELAY |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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twEndPtCnt?,
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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<!ELEMENT twConstName (#PCDATA)>
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<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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<!ATTLIST twConstHead uID CDATA #IMPLIED>
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<!ELEMENT twItemCnt (#PCDATA)>
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<!ELEMENT twErrCnt (#PCDATA)>
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<!ELEMENT twErrCntEndPt (#PCDATA)>
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<!ELEMENT twErrCntSetup (#PCDATA)>
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<!ELEMENT twErrCntHold (#PCDATA)>
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<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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<!ELEMENT twEndPtCnt (#PCDATA)>
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<!ELEMENT twPathErrCnt (#PCDATA)>
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<!ELEMENT twMinPer (#PCDATA) >
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<!ELEMENT twFootnote EMPTY>
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<!ATTLIST twFootnote number CDATA #REQUIRED>
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<!ELEMENT twMaxDel (#PCDATA)>
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<!ELEMENT twMaxFreq (#PCDATA)>
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<!ELEMENT twMinOff (#PCDATA)>
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<!ELEMENT twMaxOff (#PCDATA)>
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<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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<!ELEMENT twTIGName (#PCDATA)>
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<!ELEMENT twInstantiated (#PCDATA)>
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<!ELEMENT twBlocked (#PCDATA)>
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<!ELEMENT twRacePathRpt (twRacePath+)>
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<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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twSimpleMinPath CDATA #IMPLIED>
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<!ELEMENT twTotDel (#PCDATA)>
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<!ELEMENT twSrc (#PCDATA)>
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<!ATTLIST twSrc BELType CDATA #IMPLIED>
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<!ELEMENT twDest (#PCDATA)>
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<!ATTLIST twDest BELType CDATA #IMPLIED>
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<!ELEMENT twDel (#PCDATA)>
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<!ELEMENT twSUTime (#PCDATA)>
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<!ELEMENT twTotPathDel (#PCDATA)>
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<!ELEMENT twClkSkew (#PCDATA)>
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<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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<!ELEMENT twSlack (#PCDATA)>
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<!ELEMENT twDelConst (#PCDATA)>
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<!ELEMENT tw2Phase EMPTY>
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<!ELEMENT twClkUncert (#PCDATA)>
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<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
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<!ELEMENT twPathRptBanner (#PCDATA)>
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<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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<!ELEMENT twOff (#PCDATA)>
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<!ELEMENT twGuaranteed EMPTY>
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<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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<!ELEMENT twClkDel (#PCDATA)>
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<!ELEMENT twClkSrc (#PCDATA)>
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<!ELEMENT twClkDest (#PCDATA)>
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<!ELEMENT twGuarInSetup (#PCDATA)>
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<!ELEMENT twOffSrc (#PCDATA)>
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<!ELEMENT twOffDest (#PCDATA)>
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<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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<!ELEMENT twDataDel (#PCDATA)>
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<!ELEMENT twDataSrc (#PCDATA)>
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<!ELEMENT twDataDest (#PCDATA)>
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<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
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<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twLogLvls (#PCDATA)>
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<!ELEMENT twSrcSite (#PCDATA)>
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<!ELEMENT twSrcClk (#PCDATA)>
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<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
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<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
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<!ELEMENT twDelInfo (#PCDATA)>
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<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twSite (#PCDATA)>
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<!ELEMENT twDelType (#PCDATA)>
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<!ELEMENT twFanCnt (#PCDATA)>
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<!ELEMENT twComp (#PCDATA)>
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<!ELEMENT twNet (#PCDATA)>
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<!ELEMENT twBEL (#PCDATA)>
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<!ELEMENT twLogDel (#PCDATA)>
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<!ELEMENT twRouteDel (#PCDATA)>
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<!ELEMENT twDestClk (#PCDATA)>
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<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPctLog (#PCDATA)>
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<!ELEMENT twPctRoute (#PCDATA)>
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<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
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<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
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<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
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<!ELEMENT twTimeConst (#PCDATA)>
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<!ELEMENT twAbsSlack (#PCDATA)>
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<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
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<!ELEMENT twSkew (#PCDATA)>
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<!ELEMENT twDetNet (twNetDel*)>
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<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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<!ELEMENT twNetDelInfo (#PCDATA)>
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<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twDetSkewNet (twNetSkew*)>
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<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
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<!ELEMENT twClkSkewLimit EMPTY>
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<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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<!ELEMENT twConstRollupTable (twConstRollup*)>
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<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
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<!ELEMENT twConstRollup EMPTY>
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<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
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<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
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<!ELEMENT twConstList (twConstListItem)*>
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<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
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<!ELEMENT twNotMet EMPTY>
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<!ELEMENT twReqVal (#PCDATA)>
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<!ELEMENT twActVal (#PCDATA)>
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<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
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<!ELEMENT twConstStats (twConstName)>
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<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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<!ATTLIST twConstStats twActual CDATA #IMPLIED>
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<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
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<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
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<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
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<!ELEMENT twConstData EMPTY>
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<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
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best CDATA #IMPLIED requested CDATA #IMPLIED
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errors CDATA #IMPLIED
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score CDATA #IMPLIED>
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<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
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<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
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<!ELEMENT twTimeGrpName (#PCDATA)>
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<!ELEMENT twCompList (twCompName+)>
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<!ELEMENT twCompName (#PCDATA)>
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<!ELEMENT twSigList (twSigName+)>
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<!ELEMENT twSigName (#PCDATA)>
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<!ELEMENT twBELList (twBELName+)>
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<!ELEMENT twBELName (#PCDATA)>
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<!ELEMENT twBlockList (twBlockName+)>
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<!ELEMENT twBlockName (#PCDATA)>
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<!ELEMENT twMacList (twMacName+)>
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<!ELEMENT twMacName (#PCDATA)>
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<!ELEMENT twPinList (twPinName+)>
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<!ELEMENT twPinName (#PCDATA)>
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<!ELEMENT twUnmetConstCnt (#PCDATA)>
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<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
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<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
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<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
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<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
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<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
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<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
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<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
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<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
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<!ELEMENT twSU2ClkTime (#PCDATA)>
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<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twH2ClkTime (#PCDATA)>
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<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
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<!ELEMENT twClk2Pad (twDest, twTime)>
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<!ELEMENT twTime (#PCDATA)>
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<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
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<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
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<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
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<!ELEMENT twClk2Out EMPTY>
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<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
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<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
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<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
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<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
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<!ELEMENT twRiseRise (#PCDATA)>
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<!ELEMENT twFallRise (#PCDATA)>
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<!ELEMENT twRiseFall (#PCDATA)>
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<!ELEMENT twFallFall (#PCDATA)>
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<!ELEMENT twPad2PadList (twPad2Pad+)>
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<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
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<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
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<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
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<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
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<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
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<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
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<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
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<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffOutTblRow EMPTY>
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<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
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<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
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<!ELEMENT twNonDedClk (#PCDATA)>
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<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
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<!ELEMENT twScore (#PCDATA)>
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<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
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<!ELEMENT twPathCnt (#PCDATA)>
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<!ELEMENT twNetCnt (#PCDATA)>
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<!ELEMENT twConnCnt (#PCDATA)>
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<!ELEMENT twPct (#PCDATA)>
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<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
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<!ELEMENT twMaxCombDel (#PCDATA)>
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<!ELEMENT twMaxFromToDel (#PCDATA)>
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<!ELEMENT twMaxNetDel (#PCDATA)>
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<!ELEMENT twMaxNetSkew (#PCDATA)>
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<!ELEMENT twMaxInAfterClk (#PCDATA)>
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<!ELEMENT twMinInBeforeClk (#PCDATA)>
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<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
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<!ELEMENT twMinOutAfterClk (#PCDATA)>
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<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3
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-timegroups -s 2 -u 10000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o
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WarpLC.twr WarpLC.pcf -ucf PLL.ucf
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</twCmdLine><twDesign>WarpLC.ncd</twDesign><twDesignPath>WarpLC.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twUnconst></twUnconst><twUnconstLimit>10000</twUnconstLimit><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="5" twNameLen="15"><twSUH2ClkList anchorID="6" twDestWidth="8" twPhaseWidth="6"><twDest>CLKIN</twDest><twSUH2Clk ><twSrc>FSB_A<2></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.357</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.792</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A<3></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.113</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-5.235</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A<4></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.801</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.763</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A<5></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.561</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.981</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A<6></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.522</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.617</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A<7></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">12.787</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.498</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>FSB_A<8></twSrc><twSUHTime twInternalClk ="FSBCLK" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.770</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.347</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="7" twDestWidth="10" twPhaseWidth="21"><twSrc>CLKIN</twSrc><twClk2Out twOutPad = "CLKFB_OUT" twMinTime = "-0.091" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.068" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="cg/pll/clkfb_bufg_out" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "CLKFB_OUT" twMinTime = "-0.151" twMinCrnr="f" twMinEdge ="twFalling" twMaxTime = "-0.137" twMaxCrnr="t" twMaxEdge ="twFalling" twInternalClk="cg/pll/clkfb_bufg_out" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "CPUCLK" twMinTime = "-0.184" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.176" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "CPU_nSTERM" twMinTime = "2.525" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "6.973" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FPUCLK" twMinTime = "-0.090" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.082" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<0>" twMinTime = "4.515" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.716" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<1>" twMinTime = "4.793" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.617" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<2>" twMinTime = "4.489" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.803" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<3>" twMinTime = "4.307" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.655" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<4>" twMinTime = "4.818" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "11.229" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<5>" twMinTime = "5.205" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "11.167" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<6>" twMinTime = "4.335" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.791" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<7>" twMinTime = "4.415" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.656" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<8>" twMinTime = "4.544" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.494" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<9>" twMinTime = "3.128" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.245" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<10>" twMinTime = "4.295" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.530" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<11>" twMinTime = "3.901" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.150" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<12>" twMinTime = "4.192" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.166" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<13>" twMinTime = "3.636" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.710" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<14>" twMinTime = "4.134" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.683" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<15>" twMinTime = "4.222" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.040" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<16>" twMinTime = "4.099" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.111" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<17>" twMinTime = "3.734" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.393" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<18>" twMinTime = "3.924" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.323" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<19>" twMinTime = "4.516" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.459" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<20>" twMinTime = "4.373" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.580" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<21>" twMinTime = "4.830" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.834" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<22>" twMinTime = "4.226" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.370" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<23>" twMinTime = "4.299" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.133" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<24>" twMinTime = "4.491" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.129" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<25>" twMinTime = "4.463" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.251" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<26>" twMinTime = "4.439" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.102" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<27>" twMinTime = "4.410" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.337" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<28>" twMinTime = "4.107" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.065" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<29>" twMinTime = "4.734" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.537" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<30>" twMinTime = "4.654" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.639" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "FSB_D<31>" twMinTime = "4.185" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.533" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RAMCLK0" twMinTime = "-0.140" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "-0.132" twMaxCrnr="t" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RAMCLK1" twMinTime = "-0.179" twMinCrnr="f" twMinEdge ="twRising" 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>FSB_A<30></twSrc><twDest>FSB_D<30></twDest><twDel>20.893</twDel></twPad2Pad><twPad2Pad><twSrc>FSB_A<30></twSrc><twDest>FSB_D<31></twDest><twDel>20.435</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet><twTimeGrp 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\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKA</twPinName><twPinName>prefetch\/data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/TRUE_DP.PRIM18.ram.CLKB</twPinName><twPinName>cg\/RAMCLK0_inst.CK0</twPinName><twPinName>cg\/RAMCLK0_inst.CK1</twPinName><twPinName>cg\/RAMCLK1_inst.CK0</twPinName><twPinName>cg\/RAMCLK1_inst.CK1</twPinName></twPinList></twTimeGrp><twTimeGrp anchorID="11"><twTimeGrpName>cg_pll_clkfbout</twTimeGrpName><twBlockList><twBlockName>cg/pll/clkfbout_bufg</twBlockName></twBlockList><twPinList><twPinName>cg\/pll\/clkfbout_oddr.CK0</twPinName><twPinName>cg\/pll\/clkfbout_oddr.CK1</twPinName></twPinList></twTimeGrp><twTimeGrp anchorID="12"><twTimeGrpName>FSB_A</twTimeGrpName><twBlockList><twBlockName>prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>prefetch/data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<0>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<1>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<1>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<1>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<2>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<2>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<2>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<3>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<3>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<3>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<4>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<4>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<4>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<5>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<5>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<5>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<6>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<6>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<6>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<7>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<7>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>cache/Way<7>/way/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram</twBlockName><twBlockName>CPU_nSTERM</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/x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_inst/Mram_ram12/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP.LOW</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.HIGH</twBlockName><twBlockName>prefetch/tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP.LOW</twBlockName><twBlockName>FSB_D<10></twBlockName><twBlockName>FSB_D<11></twBlockName><twBlockName>FSB_D<0></twBlockName><twBlockName>FSB_D<12></twBlockName><twBlockName>FSB_D<20></twBlockName><twBlockName>FSB_D<1></twBlockName><twBlockName>FSB_D<13></twBlockName><twBlockName>FSB_D<21></twBlockName><twBlockName>FSB_D<2></twBlockName><twBlockName>FSB_D<14></twBlockName><twBlockName>FSB_D<22></twBlockName><twBlockName>FSB_D<30></twBlockName><twBlockName>FSB_D<3></twBlockName><twBlockName>FSB_D<15></twBlockName><twBlockName>FSB_D<23></twBlockName><twBlockName>FSB_D<31></twBlockName><twBlockName>FSB_D<4></twBlockName><twBlockName>FSB_D<16></twBlockName><twBlockName>FSB_D<24></twBlockName><twBlockName>FSB_D<5></twBlockName><twBlockName>FSB_D<17></twBlockName><twBlockName>FSB_D<25></twBlockName><twBlockName>FSB_D<6></twBlockName><twBlockName>FSB_D<18></twBlockName><twBlockName>FSB_D<26></twBlockName><twBlockName>FSB_D<7></twBlockName><twBlockName>FSB_D<19></twBlockName><twBlockName>FSB_D<27></twBlockName><twBlockName>FSB_D<8></twBlockName><twBlockName>FSB_D<28></twBlockName><twBlockName>FSB_D<9></twBlockName><twBlockName>FSB_D<29></twBlockName></twBlockList></twTimeGrp><twTimeGrp anchorID="13"><twTimeGrpName>CPU_nSTERM</twTimeGrpName><twBlockList><twBlockName>CPU_nSTERM</twBlockName></twBlockList></twTimeGrp><twTimeGrp anchorID="14"><twTimeGrpName>CLKIN</twTimeGrpName><twPinList><twPinName>cg\/pll\/pll_base_inst\/PLL_ADV.CLKIN1</twPinName><twPinName>SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0.DIVCLK</twPinName></twPinList></twTimeGrp></twVerboseRpt></twBody><twFoot><twTimestamp>Tue Nov 02 00:29:20 2021 </twTimestamp></twFoot><twClientInfo anchorID="15"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
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Peak Memory Usage: 167 MB
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</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
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