343 lines
34 KiB
XML
343 lines
34 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE twReport [
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<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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twDebug*, twFoot?, twClientInfo?)>
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<!ATTLIST twReport version CDATA "10,4">
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<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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<!ELEMENT twExecVer (#PCDATA)>
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<!ELEMENT twCopyright (#PCDATA)>
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<!ELEMENT twCmdLine (#PCDATA)>
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<!ELEMENT twDesign (#PCDATA)>
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<!ELEMENT twPCF (#PCDATA)>
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<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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<!ELEMENT twDevName (#PCDATA)>
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<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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<!ELEMENT twSpeedGrade (#PCDATA)>
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<!ELEMENT twSpeedVer (#PCDATA)>
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<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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<!ELEMENT twItemLimit (#PCDATA)>
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<!ELEMENT twUnconst EMPTY>
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<!ELEMENT twUnconstLimit (#PCDATA)>
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<!ELEMENT twEnvVar EMPTY>
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<!ATTLIST twEnvVar name CDATA #REQUIRED>
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<!ATTLIST twEnvVar description CDATA #REQUIRED>
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<!ELEMENT twWarn (#PCDATA)>
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<!ELEMENT twInfo (#PCDATA)>
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<!ELEMENT twDebug (#PCDATA)>
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<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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<!ELEMENT twProc (#PCDATA)>
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<!ELEMENT twTemp (#PCDATA)>
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<!ELEMENT twVolt (#PCDATA)>
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<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
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<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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<!ELEMENT twCycles (twSigConn+)>
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<!ATTLIST twCycles twNum CDATA #REQUIRED>
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<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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<!ELEMENT twSig (#PCDATA)>
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<!ELEMENT twDriver (#PCDATA)>
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<!ELEMENT twLoad (#PCDATA)>
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<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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<!ATTLIST twConst twConstType (NET |
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NETDELAY |
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NETSKEW |
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PATH |
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DEFPERIOD |
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UNCONSTPATH |
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DEFPATH |
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PATH2SETUP |
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UNCONSTPATH2SETUP |
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PATHCLASS |
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PATHDELAY |
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PERIOD |
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FREQUENCY |
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PATHBLOCK |
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OFFSET |
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OFFSETIN |
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OFFSETINCLOCK |
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UNCONSTOFFSETINCLOCK |
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OFFSETINDELAY |
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OFFSETINMOD |
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OFFSETOUT |
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OFFSETOUTCLOCK |
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UNCONSTOFFSETOUTCLOCK |
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OFFSETOUTDELAY |
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OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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twEndPtCnt?,
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twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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<!ELEMENT twConstName (#PCDATA)>
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<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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<!ATTLIST twConstHead uID CDATA #IMPLIED>
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<!ELEMENT twItemCnt (#PCDATA)>
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<!ELEMENT twErrCnt (#PCDATA)>
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<!ELEMENT twErrCntEndPt (#PCDATA)>
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<!ELEMENT twErrCntSetup (#PCDATA)>
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<!ELEMENT twErrCntHold (#PCDATA)>
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<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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<!ELEMENT twEndPtCnt (#PCDATA)>
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<!ELEMENT twPathErrCnt (#PCDATA)>
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<!ELEMENT twMinPer (#PCDATA) >
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<!ELEMENT twFootnote EMPTY>
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<!ATTLIST twFootnote number CDATA #REQUIRED>
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<!ELEMENT twMaxDel (#PCDATA)>
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<!ELEMENT twMaxFreq (#PCDATA)>
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<!ELEMENT twMinOff (#PCDATA)>
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<!ELEMENT twMaxOff (#PCDATA)>
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<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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<!ELEMENT twTIGName (#PCDATA)>
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<!ELEMENT twInstantiated (#PCDATA)>
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<!ELEMENT twBlocked (#PCDATA)>
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<!ELEMENT twRacePathRpt (twRacePath+)>
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<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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twSimpleMinPath CDATA #IMPLIED>
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<!ELEMENT twTotDel (#PCDATA)>
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<!ELEMENT twSrc (#PCDATA)>
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<!ATTLIST twSrc BELType CDATA #IMPLIED>
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<!ELEMENT twDest (#PCDATA)>
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<!ATTLIST twDest BELType CDATA #IMPLIED>
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<!ELEMENT twDel (#PCDATA)>
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<!ELEMENT twSUTime (#PCDATA)>
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<!ELEMENT twTotPathDel (#PCDATA)>
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<!ELEMENT twClkSkew (#PCDATA)>
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<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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<!ELEMENT twSlack (#PCDATA)>
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<!ELEMENT twDelConst (#PCDATA)>
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<!ELEMENT tw2Phase EMPTY>
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<!ELEMENT twClkUncert (#PCDATA)>
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<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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fDCMJit CDATA #IMPLIED
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fPhaseErr CDATA #IMPLIED
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sEqu CDATA #IMPLIED>
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<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
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<!ELEMENT twPathRptBanner (#PCDATA)>
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<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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<!ELEMENT twOff (#PCDATA)>
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<!ELEMENT twGuaranteed EMPTY>
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<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
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<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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<!ELEMENT twClkDel (#PCDATA)>
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<!ELEMENT twClkSrc (#PCDATA)>
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<!ELEMENT twClkDest (#PCDATA)>
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<!ELEMENT twGuarInSetup (#PCDATA)>
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<!ELEMENT twOffSrc (#PCDATA)>
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<!ELEMENT twOffDest (#PCDATA)>
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<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
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<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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<!ELEMENT twDataDel (#PCDATA)>
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<!ELEMENT twDataSrc (#PCDATA)>
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<!ELEMENT twDataDest (#PCDATA)>
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<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
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<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
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<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
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<!ELEMENT twLogLvls (#PCDATA)>
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<!ELEMENT twSrcSite (#PCDATA)>
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<!ELEMENT twSrcClk (#PCDATA)>
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<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
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<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
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<!ELEMENT twDelInfo (#PCDATA)>
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<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twSite (#PCDATA)>
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<!ELEMENT twDelType (#PCDATA)>
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<!ELEMENT twFanCnt (#PCDATA)>
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<!ELEMENT twComp (#PCDATA)>
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<!ELEMENT twNet (#PCDATA)>
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<!ELEMENT twBEL (#PCDATA)>
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<!ELEMENT twLogDel (#PCDATA)>
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<!ELEMENT twRouteDel (#PCDATA)>
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<!ELEMENT twDestClk (#PCDATA)>
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<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
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<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
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<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
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<!ELEMENT twPctLog (#PCDATA)>
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<!ELEMENT twPctRoute (#PCDATA)>
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<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
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<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
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<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
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<!ELEMENT twTimeConst (#PCDATA)>
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<!ELEMENT twAbsSlack (#PCDATA)>
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<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
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<!ELEMENT twSkew (#PCDATA)>
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<!ELEMENT twDetNet (twNetDel*)>
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<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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<!ELEMENT twNetDelInfo (#PCDATA)>
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<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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<!ELEMENT twDetSkewNet (twNetSkew*)>
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<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
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<!ELEMENT twClkSkewLimit EMPTY>
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<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
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arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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<!ELEMENT twConstRollupTable (twConstRollup*)>
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<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
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<!ELEMENT twConstRollup EMPTY>
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<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
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<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
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<!ELEMENT twConstList (twConstListItem)*>
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<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
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<!ELEMENT twNotMet EMPTY>
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<!ELEMENT twReqVal (#PCDATA)>
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<!ELEMENT twActVal (#PCDATA)>
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<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
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<!ELEMENT twConstStats (twConstName)>
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<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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<!ATTLIST twConstStats twActual CDATA #IMPLIED>
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<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
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<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
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<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
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<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
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<!ELEMENT twConstData EMPTY>
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<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
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best CDATA #IMPLIED requested CDATA #IMPLIED
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errors CDATA #IMPLIED
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score CDATA #IMPLIED>
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<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
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<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
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<!ELEMENT twTimeGrpName (#PCDATA)>
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<!ELEMENT twCompList (twCompName+)>
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<!ELEMENT twCompName (#PCDATA)>
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<!ELEMENT twSigList (twSigName+)>
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<!ELEMENT twSigName (#PCDATA)>
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<!ELEMENT twBELList (twBELName+)>
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<!ELEMENT twBELName (#PCDATA)>
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<!ELEMENT twBlockList (twBlockName+)>
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<!ELEMENT twBlockName (#PCDATA)>
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<!ELEMENT twMacList (twMacName+)>
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<!ELEMENT twMacName (#PCDATA)>
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<!ELEMENT twPinList (twPinName+)>
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<!ELEMENT twPinName (#PCDATA)>
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<!ELEMENT twUnmetConstCnt (#PCDATA)>
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<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
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<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
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<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
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<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
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<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
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<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
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<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
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<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
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<!ELEMENT twSU2ClkTime (#PCDATA)>
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<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twH2ClkTime (#PCDATA)>
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<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
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<!ELEMENT twClk2Pad (twDest, twTime)>
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<!ELEMENT twTime (#PCDATA)>
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<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
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<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
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<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
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<!ELEMENT twClk2Out EMPTY>
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<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
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<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
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<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
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<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
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<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
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<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
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<!ELEMENT twRiseRise (#PCDATA)>
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<!ELEMENT twFallRise (#PCDATA)>
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<!ELEMENT twRiseFall (#PCDATA)>
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<!ELEMENT twFallFall (#PCDATA)>
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<!ELEMENT twPad2PadList (twPad2Pad+)>
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<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
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<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
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<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
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<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
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<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
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<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
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<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
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<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
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<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
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<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
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<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
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<!ELEMENT twOffOutTblRow EMPTY>
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<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
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<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
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<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
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<!ELEMENT twNonDedClk (#PCDATA)>
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<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
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<!ELEMENT twScore (#PCDATA)>
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<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
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<!ELEMENT twPathCnt (#PCDATA)>
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<!ELEMENT twNetCnt (#PCDATA)>
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<!ELEMENT twConnCnt (#PCDATA)>
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<!ELEMENT twPct (#PCDATA)>
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<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
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<!ELEMENT twMaxCombDel (#PCDATA)>
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<!ELEMENT twMaxFromToDel (#PCDATA)>
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<!ELEMENT twMaxNetDel (#PCDATA)>
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<!ELEMENT twMaxNetSkew (#PCDATA)>
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<!ELEMENT twMaxInAfterClk (#PCDATA)>
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<!ELEMENT twMinInBeforeClk (#PCDATA)>
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<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
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<!ELEMENT twMinOutAfterClk (#PCDATA)>
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<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
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-n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o WarpLC.twr WarpLC.pcf -ucf
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PLL.ucf
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</twCmdLine><twDesign>WarpLC.ncd</twDesign><twDesignPath>WarpLC.ncd</twDesignPath><twPCF>WarpLC.pcf</twPCF><twPcfPath>WarpLC.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="ftg256"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PATHDELAY" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_CPU_nSTERM_A = FROM "FSB_A" TO "CPU_nSTERM" 15ns;" ScopeName="">TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;</twConstName><twItemCnt>22</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMaxDel>8.586</twMaxDel></twConstHead><twPathRptBanner iPaths="22" iCriticalPaths="0" sType="EndPoint">Paths for end point CPU_nSTERM (E11.PAD), 22 paths
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</twPathRptBanner><twPathRpt anchorID="6"><twConstPath anchorID="7" twDataPathType="twDataPathFromToDelay"><twSlack>6.414</twSlack><twSrc BELType="RAM">l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP</twSrc><twDest BELType="PAD">CPU_nSTERM</twDest><twTotPathDel>8.586</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>15.000</twDelConst><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP</twSrc><twDest BELType='PAD'>CPU_nSTERM</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X16Y51.CLK</twSrcSite><twSrcClk twEdge ="twRising">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X16Y51.AMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">1.081</twDelInfo><twComp>l2pre/n0023<14></twComp><twBEL>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y50.D3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.014</twDelInfo><twComp>l2pre/n0023<11></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y50.COUT</twSite><twDelType>Topcyd</twDelType><twDelInfo twEdge="twRising">0.312</twDelInfo><twComp>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3></twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3></twBEL><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y51.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y51.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.302</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y56.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.640</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM1</twBEL></twPathDel><twPathDel><twSite>E11.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.998</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp></twPathDel><twPathDel><twSite>E11.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twRising">1.982</twDelInfo><twComp>CPU_nSTERM</twComp><twBEL>CPU_nSTERM_OBUF</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>3.931</twLogDel><twRouteDel>4.655</twRouteDel><twTotDel>8.586</twTotDel><twPctLog>45.8</twPctLog><twPctRoute>54.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="8"><twConstPath anchorID="9" twDataPathType="twDataPathFromToDelay"><twSlack>6.422</twSlack><twSrc BELType="RAM">l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP</twSrc><twDest BELType="PAD">CPU_nSTERM</twDest><twTotPathDel>8.578</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>15.000</twDelConst><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP</twSrc><twDest BELType='PAD'>CPU_nSTERM</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X16Y51.CLK</twSrcSite><twSrcClk twEdge ="twRising">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X16Y51.B</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">1.106</twDelInfo><twComp>l2pre/n0023<14></twComp><twBEL>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y51.A4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.968</twDelInfo><twComp>l2pre/n0023<14></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y51.CMUX</twSite><twDelType>Topac</twDelType><twDelInfo twEdge="twRising">0.630</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4></twBEL><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y56.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.640</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM1</twBEL></twPathDel><twPathDel><twSite>E11.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.998</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp></twPathDel><twPathDel><twSite>E11.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twRising">1.982</twDelInfo><twComp>CPU_nSTERM</twComp><twBEL>CPU_nSTERM_OBUF</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>3.972</twLogDel><twRouteDel>4.606</twRouteDel><twTotDel>8.578</twTotDel><twPctLog>46.3</twPctLog><twPctRoute>53.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathFromToDelay"><twSlack>6.445</twSlack><twSrc BELType="RAM">l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP</twSrc><twDest BELType="PAD">CPU_nSTERM</twDest><twTotPathDel>8.555</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>15.000</twDelConst><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='RAM'>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP</twSrc><twDest BELType='PAD'>CPU_nSTERM</twDest><twLogLvls>4</twLogLvls><twSrcSite>SLICE_X20Y55.CLK</twSrcSite><twSrcClk twEdge ="twRising">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X20Y55.AMUX</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">1.081</twDelInfo><twComp>l2pre/n0023<21></twComp><twBEL>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y50.A3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.821</twDelInfo><twComp>l2pre/n0023<2></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y50.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.474</twDelInfo><twComp>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3></twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0></twBEL><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y51.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y51.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.302</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y56.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.640</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.254</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM1</twBEL></twPathDel><twPathDel><twSite>E11.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">2.998</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp></twPathDel><twPathDel><twSite>E11.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twRising">1.982</twDelInfo><twComp>CPU_nSTERM</twComp><twBEL>CPU_nSTERM_OBUF</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>4.093</twLogDel><twRouteDel>4.462</twRouteDel><twTotDel>8.555</twTotDel><twPctLog>47.8</twPctLog><twPctRoute>52.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Fastest Paths: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;
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</twPathRptBanner><twPathRptBanner iPaths="22" iCriticalPaths="0" sType="EndPoint">Paths for end point CPU_nSTERM (E11.PAD), 22 paths
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</twPathRptBanner><twRacePathRpt><twRacePath anchorID="12"><twSlack>3.066</twSlack><twSrc BELType="RAM">l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP</twSrc><twDest BELType="PAD">CPU_nSTERM</twDest><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='RAM'>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP</twSrc><twDest BELType='PAD'>CPU_nSTERM</twDest><twLogLvls>2</twLogLvls><twSrcSite>SLICE_X20Y55.CLK</twSrcSite><twSrcClk twEdge ="twRising">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X20Y55.B</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.449</twDelInfo><twComp>l2pre/n0023<21></twComp><twBEL>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y56.A5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.194</twDelInfo><twComp>l2pre/n0023<21></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.156</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM1</twBEL></twPathDel><twPathDel><twSite>E11.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.568</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp></twPathDel><twPathDel><twSite>E11.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twFalling">0.699</twDelInfo><twComp>CPU_nSTERM</twComp><twBEL>CPU_nSTERM_OBUF</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>1.304</twLogDel><twRouteDel>1.762</twRouteDel><twTotDel>3.066</twTotDel><twPctLog>42.5</twPctLog><twPctRoute>57.5</twPctRoute></twDetPath></twRacePath><twRacePath anchorID="13"><twSlack>3.557</twSlack><twSrc BELType="RAM">l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP</twSrc><twDest BELType="PAD">CPU_nSTERM</twDest><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='RAM'>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP</twSrc><twDest BELType='PAD'>CPU_nSTERM</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X20Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X20Y52.B</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.449</twDelInfo><twComp>l2pre/n0023<18></twComp><twBEL>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y51.C5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.150</twDelInfo><twComp>l2pre/n0023<18></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y51.CMUX</twSite><twDelType>Topcc</twDelType><twDelInfo twEdge="twRising">0.250</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6></twBEL><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y56.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.285</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.156</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM1</twBEL></twPathDel><twPathDel><twSite>E11.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.568</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp></twPathDel><twPathDel><twSite>E11.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twFalling">0.699</twDelInfo><twComp>CPU_nSTERM</twComp><twBEL>CPU_nSTERM_OBUF</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>1.554</twLogDel><twRouteDel>2.003</twRouteDel><twTotDel>3.557</twTotDel><twPctLog>43.7</twPctLog><twPctRoute>56.3</twPctRoute></twDetPath></twRacePath><twRacePath anchorID="14"><twSlack>3.629</twSlack><twSrc BELType="RAM">l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP</twSrc><twDest BELType="PAD">CPU_nSTERM</twDest><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='RAM'>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP</twSrc><twDest BELType='PAD'>CPU_nSTERM</twDest><twLogLvls>3</twLogLvls><twSrcSite>SLICE_X20Y52.CLK</twSrcSite><twSrcClk twEdge ="twRising">FSBCLK</twSrcClk><twPathDel><twSite>SLICE_X20Y52.A</twSite><twDelType>Tshcko</twDelType><twDelInfo twEdge="twRising">0.441</twDelInfo><twComp>l2pre/n0023<18></twComp><twBEL>l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP</twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y51.C4</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.230</twDelInfo><twComp>l2pre/n0023<19></twComp></twPathDel><twPathDel><twSite>SLICE_X20Y51.CMUX</twSite><twDelType>Topcc</twDelType><twDelInfo twEdge="twRising">0.250</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6></twBEL><twBEL>l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<6></twBEL></twPathDel><twPathDel><twSite>SLICE_X20Y56.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.285</twDelInfo><twComp>l2pre/RDTag[20]_RDATag[20]_equal_5_o</twComp></twPathDel><twPathDel><twSite>SLICE_X20Y56.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.156</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp><twBEL>CPU_nSTERM1</twBEL></twPathDel><twPathDel><twSite>E11.O</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">1.568</twDelInfo><twComp>CPU_nSTERM_OBUF</twComp></twPathDel><twPathDel><twSite>E11.PAD</twSite><twDelType>Tioop</twDelType><twDelInfo twEdge="twFalling">0.699</twDelInfo><twComp>CPU_nSTERM</twComp><twBEL>CPU_nSTERM_OBUF</twBEL><twBEL>CPU_nSTERM</twBEL></twPathDel><twLogDel>1.546</twLogDel><twRouteDel>2.083</twRouteDel><twTotDel>3.629</twTotDel><twPctLog>42.6</twPctLog><twPctRoute>57.4</twPctRoute></twDetPath></twRacePath></twRacePathRpt></twConst><twUnmetConstCnt anchorID="15">0</twUnmetConstCnt><twDataSheet anchorID="16" twNameLen="15"><twClk2OutList anchorID="17" twDestWidth="10" twPhaseWidth="6"><twSrc>CLKIN</twSrc><twClk2Out twOutPad = "CPU_nSTERM" twMinTime = "1.330" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "4.305" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="FSBCLK" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="18"><twErrCnt>0</twErrCnt><twScore>0</twScore><twSetupScore>0</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>22</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>39</twConnCnt></twConstCov><twStats anchorID="19"><twMaxFromToDel>8.586</twMaxFromToDel></twStats></twSum><twFoot><twTimestamp>Sun Oct 31 15:23:24 2021 </twTimestamp></twFoot><twClientInfo anchorID="20"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
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Peak Memory Usage: 214 MB
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