166 lines
7.0 KiB
Plaintext
166 lines
7.0 KiB
Plaintext
Release 14.7 Map P.20131013 (nt)
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Xilinx Map Application Log File for Design 'WarpLC'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc6slx9-ftg256-2 -w -logic_opt on -ol high
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-xe c -t 1 -xt 0 -r 4 -global_opt speed -equivalent_register_removal on -mt 2
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-ir off -pr off -lc off -power off -o WarpLC_map.ncd WarpLC.ngd WarpLC.pcf
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Target Device : xc6slx9
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Target Package : ftg256
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Target Speed : -2
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Mapper Version : spartan6 -- $Revision: 1.55 $
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Mapped Date : Tue Nov 02 00:33:09 2021
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Running global optimization...
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Updating timing models...
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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Running timing-driven placement...
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Total REAL time at the beginning of Placer: 9 secs
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Total CPU time at the beginning of Placer: 9 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:a4d8) REAL time: 10 secs
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Phase 2.7 Design Feasibility Check
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Phase 2.7 Design Feasibility Check (Checksum:a4d8) REAL time: 10 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:a4d8) REAL time: 10 secs
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Phase 4.2 Initial Placement for Architecture Specific Features
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...
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....
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Phase 4.2 Initial Placement for Architecture Specific Features
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(Checksum:2d53f6ff) REAL time: 14 secs
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Phase 5.36 Local Placement Optimization
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Phase 5.36 Local Placement Optimization (Checksum:2d53f6ff) REAL time: 14 secs
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Phase 6.30 Global Clock Region Assignment
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Phase 6.30 Global Clock Region Assignment (Checksum:2d53f6ff) REAL time: 14 secs
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Phase 7.3 Local Placement Optimization
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...
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....
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Phase 7.3 Local Placement Optimization (Checksum:615a33f3) REAL time: 19 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:615a33f3) REAL time: 19 secs
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Phase 9.8 Global Placement
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...................................................
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.......................
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Phase 9.8 Global Placement (Checksum:b18754dd) REAL time: 19 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:b18754dd) REAL time: 19 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:58c2ff74) REAL time: 20 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:58c2ff74) REAL time: 20 secs
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Phase 13.34 Placement Validation
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Phase 13.34 Placement Validation (Checksum:58c2ff74) REAL time: 20 secs
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Total REAL time to Placer completion: 20 secs
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Total CPU time to Placer completion: 20 secs
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Running physical synthesis...
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Physical synthesis completed.
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Running post-placement packing...
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Writing output files...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 0
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Slice Logic Utilization:
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Number of Slice Registers: 1 out of 11,440 1%
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Number used as Flip Flops: 1
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 105 out of 5,720 1%
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Number used as logic: 25 out of 5,720 1%
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Number using O6 output only: 7
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Number using O5 output only: 1
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Number using O5 and O6: 17
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Number used as ROM: 0
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Number used as Memory: 80 out of 1,440 5%
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Number used as Dual Port RAM: 80
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Number using O6 output only: 80
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Number using O5 output only: 0
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Number using O5 and O6: 0
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Number used as Single Port RAM: 0
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Number used as Shift Register: 0
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Slice Logic Distribution:
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Number of occupied Slices: 35 out of 1,430 2%
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Number of MUXCYs used: 8 out of 2,860 1%
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Number of LUT Flip Flop pairs used: 106
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Number with an unused Flip Flop: 105 out of 106 99%
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Number with an unused LUT: 1 out of 106 1%
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Number of fully used LUT-FF pairs: 0 out of 106 0%
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Number of unique control sets: 2
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Number of slice register sites lost
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to control set restrictions: 7 out of 11,440 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 66 out of 186 35%
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IOB Flip Flops: 5
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Specific Feature Utilization:
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Number of RAMB16BWERs: 4 out of 32 12%
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Number of RAMB8BWERs: 0 out of 64 0%
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Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
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Number used as BUFIO2s: 1
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Number used as BUFIO2_2CLKs: 0
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
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Number used as BUFIO2FBs: 1
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Number used as BUFIO2FB_2CLKs: 0
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Number of BUFG/BUFGMUXs: 2 out of 16 12%
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Number used as BUFGs: 2
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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Number of OLOGIC2/OSERDES2s: 5 out of 200 2%
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Number used as OLOGIC2s: 5
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Number used as OSERDES2s: 0
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 16 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 1 out of 2 50%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 3.54
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Peak Memory Usage: 283 MB
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Total REAL time to MAP completion: 22 secs
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Total CPU time to MAP completion (all processors): 22 secs
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Mapping completed.
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See MAP report file "WarpLC_map.mrp" for details.
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