Warp-LC/fpga/ipcore_dir/edit_CLK.tcl
2021-10-29 10:04:15 -04:00

38 lines
1.1 KiB
Tcl

##
## Core Generator Run Script, generator for Project Navigator edit command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_edit "CLK" xc6slx9-2ftg256 Verilog ]
if { $result == 0 } {
puts "Core Generator edit command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator edit command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator edit cancelled."
}
exit $result