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49 lines
998 B
Verilog
49 lines
998 B
Verilog
module L2Cache(
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input CLK,
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input CPUCLKr,
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input [27:2] RDA,
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output [31:0] RDD,
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output Match,
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input [27:2] WRA,
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input [31:0] WRD,
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input [3:0] WRM,
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input TS,
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input WR,
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input CLR,
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input ALL);
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/* Cache ways */
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wire [31:0] WayRDD[7:0];
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wire WayRDMatch[7:0];
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L2CacheWay Way[7:0] (
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.CLK(CLK),
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.CPUCLKr(CPUCLKr),
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.RDA(RDA),
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.RDD(WayRDD),
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.RDMatch(WayRDMatch),
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.WRA(WRA),
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.WRD(WRD),
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.WRM(WRM),
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.TS(TS),
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.WR(WR),
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.CLR(CLR),
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.ALL(ALL));
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assign Match == WayRDMatch[0] || WayRDMatch[1] ||
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WayRDMatch[2] || WayRDMatch[3] ||
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WayRDMatch[4] || WayRDMatch[5] ||
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WayRDMatch[6] || WayRDMatch[7];
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assign RDD[31:0] = WayRDMatch[0] ? WayRDD[0] :
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WayRDMatch[1] ? WayRDD[1] :
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WayRDMatch[2] ? WayRDD[2] :
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WayRDMatch[3] ? WayRDD[3] :
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WayRDMatch[4] ? WayRDD[4] :
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WayRDMatch[5] ? WayRDD[5] :
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WayRDMatch[6] ? WayRDD[6] :
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WayRDMatch[7] ? WayRDD[7] : 0;
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endmodule
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