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118 lines
4.3 KiB
VHDL
118 lines
4.3 KiB
VHDL
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--------------------------------------------------------------------------------
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--
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-- BLK MEM GEN v7_3 Core - Address Generator
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: addr_gen.vhd
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--
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-- Description:
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-- Address Generator
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--
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--------------------------------------------------------------------------------
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-- Author: IP Solutions Division
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--
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-- History: Sep 12, 2011 - First Release
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--------------------------------------------------------------------------------
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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LIBRARY work;
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USE work.ALL;
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ENTITY ADDR_GEN IS
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GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
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RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
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RST_INC : INTEGER := 0);
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PORT (
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CLK : IN STD_LOGIC;
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RST : IN STD_LOGIC;
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EN : IN STD_LOGIC;
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LOAD :IN STD_LOGIC;
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LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
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ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
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);
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END ADDR_GEN;
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ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
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SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
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BEGIN
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ADDR_OUT <= ADDR_TEMP;
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PROCESS(CLK)
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BEGIN
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IF(RISING_EDGE(CLK)) THEN
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IF(RST='1') THEN
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ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
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ELSE
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IF(EN='1') THEN
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IF(LOAD='1') THEN
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ADDR_TEMP <=LOAD_VALUE;
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ELSE
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IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
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ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
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ELSE
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ADDR_TEMP <= ADDR_TEMP + '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END ARCHITECTURE;
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