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536 lines
16 KiB
VHDL
536 lines
16 KiB
VHDL
--------------------------------------------------------------------------------
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--
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-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
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--
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--------------------------------------------------------------------------------
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--
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-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--------------------------------------------------------------------------------
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--
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-- Filename: bmg_stim_gen.vhd
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--
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-- Description:
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-- Stimulus Generation For TDP
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-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
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-- simulation ends
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--
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--------------------------------------------------------------------------------
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-- Author: IP Solutions Division
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--
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-- History: Sep 12, 2011 - First Release
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--------------------------------------------------------------------------------
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--
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--------------------------------------------------------------------------------
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-- Library Declarations
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE IEEE.STD_LOGIC_MISC.ALL;
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LIBRARY work;
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USE work.ALL;
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USE work.BMG_TB_PKG.ALL;
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ENTITY REGISTER_LOGIC_TDP IS
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PORT(
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Q : OUT STD_LOGIC;
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CLK : IN STD_LOGIC;
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RST : IN STD_LOGIC;
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D : IN STD_LOGIC
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);
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END REGISTER_LOGIC_TDP;
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ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
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SIGNAL Q_O : STD_LOGIC :='0';
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BEGIN
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Q <= Q_O;
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FF_BEH: PROCESS(CLK)
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BEGIN
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IF(RISING_EDGE(CLK)) THEN
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IF(RST ='1') THEN
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Q_O <= '0';
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ELSE
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Q_O <= D;
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END IF;
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END IF;
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END PROCESS;
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END REGISTER_ARCH;
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_ARITH.ALL;
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--USE IEEE.NUMERIC_STD.ALL;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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USE IEEE.STD_LOGIC_MISC.ALL;
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LIBRARY work;
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USE work.ALL;
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USE work.BMG_TB_PKG.ALL;
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ENTITY BMG_STIM_GEN IS
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PORT (
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CLKA : IN STD_LOGIC;
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CLKB : IN STD_LOGIC;
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TB_RST : IN STD_LOGIC;
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ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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DINA : OUT STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
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ENA : OUT STD_LOGIC :='0';
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WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
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WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
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ADDRB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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DINB : OUT STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
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ENB : OUT STD_LOGIC :='0';
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CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
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);
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END BMG_STIM_GEN;
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ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
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CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(47,47);
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CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(47,47);
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SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
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SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
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SIGNAL DINA_INT : STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
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SIGNAL DINB_INT : STD_LOGIC_VECTOR(46 DOWNTO 0) := (OTHERS => '0');
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SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
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SIGNAL DO_WRITE_A : STD_LOGIC := '0';
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SIGNAL DO_READ_A : STD_LOGIC := '0';
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SIGNAL DO_WRITE_B : STD_LOGIC := '0';
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SIGNAL DO_READ_B : STD_LOGIC := '0';
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SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
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SIGNAL DO_READ_RA : STD_LOGIC := '0';
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SIGNAL DO_READ_RB : STD_LOGIC := '0';
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SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
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SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
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SIGNAL COUNT : integer := 0;
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SIGNAL COUNT_B : integer := 0;
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CONSTANT WRITE_CNT_A : integer := 6;
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CONSTANT READ_CNT_A : integer := 6;
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CONSTANT WRITE_CNT_B : integer := 4;
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CONSTANT READ_CNT_B : integer := 4;
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signal porta_wr_rd : std_logic:='0';
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signal portb_wr_rd : std_logic:='0';
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signal porta_wr_rd_complete: std_logic:='0';
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signal portb_wr_rd_complete: std_logic:='0';
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signal incr_cnt : std_logic :='0';
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signal incr_cnt_b : std_logic :='0';
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SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
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SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
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SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
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SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
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SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
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SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
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SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
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SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
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SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
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SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
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SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
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SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
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BEGIN
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WRITE_ADDR_INT_A(9 DOWNTO 0) <= WRITE_ADDR_A(9 DOWNTO 0);
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READ_ADDR_INT_A(9 DOWNTO 0) <= READ_ADDR_A(9 DOWNTO 0);
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ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
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WRITE_ADDR_INT_B(9 DOWNTO 0) <= WRITE_ADDR_B(9 DOWNTO 0);
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--To avoid collision during idle period, negating the read_addr of port A
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READ_ADDR_INT_B(9 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(9 DOWNTO 0));
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ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
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DINA <= DINA_INT ;
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DINB <= DINB_INT ;
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CHECK_DATA(0) <= DO_READ_A;
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CHECK_DATA(1) <= DO_READ_B;
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RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
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GENERIC MAP( C_MAX_DEPTH => 1024,
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RST_INC => 1 )
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PORT MAP(
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CLK => CLKA,
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RST => TB_RST,
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EN => DO_READ_A,
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LOAD => '0',
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LOAD_VALUE => ZERO,
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ADDR_OUT => READ_ADDR_A
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);
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WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
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GENERIC MAP( C_MAX_DEPTH =>1024 ,
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RST_INC => 1 )
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PORT MAP(
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CLK => CLKA,
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RST => TB_RST,
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EN => DO_WRITE_A,
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LOAD => '0',
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LOAD_VALUE => ZERO,
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ADDR_OUT => WRITE_ADDR_A
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);
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RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
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GENERIC MAP( C_MAX_DEPTH => 1024 ,
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RST_INC => 1 )
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PORT MAP(
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CLK => CLKB,
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RST => TB_RST,
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EN => DO_READ_B,
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LOAD => '0',
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LOAD_VALUE => ZERO,
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ADDR_OUT => READ_ADDR_B
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);
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WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
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GENERIC MAP( C_MAX_DEPTH => 1024 ,
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RST_INC => 1 )
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PORT MAP(
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CLK => CLKB,
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RST => TB_RST,
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EN => DO_WRITE_B,
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LOAD => '0',
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LOAD_VALUE => ZERO,
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ADDR_OUT => WRITE_ADDR_B
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);
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WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
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GENERIC MAP ( DATA_GEN_WIDTH =>47,
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DOUT_WIDTH => 47,
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DATA_PART_CNT => 1,
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SEED => 2)
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PORT MAP (
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CLK =>CLKA,
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RST => TB_RST,
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EN => DO_WRITE_A,
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DATA_OUT => DINA_INT
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);
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WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
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GENERIC MAP ( DATA_GEN_WIDTH =>47,
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DOUT_WIDTH =>47 ,
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DATA_PART_CNT =>1,
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SEED => 2)
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PORT MAP (
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CLK =>CLKB,
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RST => TB_RST,
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EN => DO_WRITE_B,
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DATA_OUT => DINB_INT
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);
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PROCESS(CLKB)
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BEGIN
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IF(RISING_EDGE(CLKB)) THEN
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IF(TB_RST='1') THEN
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LATCH_PORTB_WR_RD_COMPLETE<='0';
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ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
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LATCH_PORTB_WR_RD_COMPLETE <='1';
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ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
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LATCH_PORTB_WR_RD_COMPLETE<='0';
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END IF;
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END IF;
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END PROCESS;
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PROCESS(CLKA)
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BEGIN
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IF(RISING_EDGE(CLKA)) THEN
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IF(TB_RST='1') THEN
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PORTB_WR_RD_L1 <='0';
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PORTB_WR_RD_L2 <='0';
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ELSE
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PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
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PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
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END IF;
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END IF;
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END PROCESS;
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PORTA_WR_RD_EN: PROCESS(CLKA)
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BEGIN
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IF(RISING_EDGE(CLKA)) THEN
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IF(TB_RST='1') THEN
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PORTA_WR_RD <='1';
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ELSE
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PORTA_WR_RD <= PORTB_WR_RD_L2;
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END IF;
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END IF;
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END PROCESS;
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PROCESS(CLKB)
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BEGIN
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IF(RISING_EDGE(CLKB)) THEN
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IF(TB_RST='1') THEN
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PORTA_WR_RD_R1 <='0';
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PORTA_WR_RD_R2 <='0';
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ELSE
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PORTA_WR_RD_R1 <=PORTA_WR_RD;
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PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
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END IF;
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END IF;
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END PROCESS;
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PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
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PROCESS(CLKA)
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BEGIN
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IF(RISING_EDGE(CLKA)) THEN
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IF(TB_RST='1') THEN
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LATCH_PORTA_WR_RD_COMPLETE<='0';
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ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
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LATCH_PORTA_WR_RD_COMPLETE <='1';
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ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
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LATCH_PORTA_WR_RD_COMPLETE<='0';
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END IF;
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END IF;
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END PROCESS;
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PROCESS(CLKB)
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BEGIN
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IF(RISING_EDGE(CLKB)) THEN
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IF(TB_RST='1') THEN
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PORTA_WR_RD_L1 <='0';
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PORTA_WR_RD_L2 <='0';
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ELSE
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PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
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PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
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END IF;
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END IF;
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END PROCESS;
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PORTB_EN: PROCESS(CLKB)
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BEGIN
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IF(RISING_EDGE(CLKB)) THEN
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IF(TB_RST='1') THEN
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PORTB_WR_RD <='0';
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ELSE
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PORTB_WR_RD <= PORTA_WR_RD_L2;
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END IF;
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END IF;
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END PROCESS;
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PROCESS(CLKA)
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BEGIN
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IF(RISING_EDGE(CLKA)) THEN
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IF(TB_RST='1') THEN
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PORTB_WR_RD_R1 <='0';
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PORTB_WR_RD_R2 <='0';
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ELSE
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PORTB_WR_RD_R1 <=PORTB_WR_RD;
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PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
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END IF;
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END IF;
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END PROCESS;
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---double registered of porta complete on portb clk
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PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
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PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
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start_counter: process(clka)
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begin
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if(rising_edge(clka)) then
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if(TB_RST='1') then
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incr_cnt <= '0';
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elsif(porta_wr_rd ='1') then
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incr_cnt <='1';
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elsif(porta_wr_rd_complete='1') then
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incr_cnt <='0';
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end if;
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end if;
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end process;
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COUNTER: process(clka)
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begin
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if(rising_edge(clka)) then
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if(TB_RST='1') then
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count <= 0;
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elsif(incr_cnt='1') then
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count<=count+1;
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end if;
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if(count=(WRITE_CNT_A+READ_CNT_A)) then
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count<=0;
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end if;
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end if;
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end process;
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DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
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DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
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PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
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startb_counter: process(clkb)
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begin
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if(rising_edge(clkb)) then
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if(TB_RST='1') then
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incr_cnt_b <= '0';
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elsif(portb_wr_rd ='1') then
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incr_cnt_b <='1';
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elsif(portb_wr_rd_complete='1') then
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incr_cnt_b <='0';
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end if;
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end if;
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end process;
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COUNTER_B: process(clkb)
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begin
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if(rising_edge(clkb)) then
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if(TB_RST='1') then
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count_b <= 0;
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elsif(incr_cnt_b='1') then
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count_b<=count_b+1;
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end if;
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if(count_b=WRITE_CNT_B+READ_CNT_B) then
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count_b<=0;
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end if;
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end if;
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end process;
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DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
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DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
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BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
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BEGIN
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DFF_RIGHT: IF I=0 GENERATE
|
|
BEGIN
|
|
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
|
|
PORT MAP(
|
|
Q => DO_READ_REG_A(0),
|
|
CLK =>CLKA,
|
|
RST=>TB_RST,
|
|
D =>DO_READ_A
|
|
);
|
|
END GENERATE DFF_RIGHT;
|
|
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
|
|
BEGIN
|
|
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
|
|
PORT MAP(
|
|
Q => DO_READ_REG_A(I),
|
|
CLK =>CLKA,
|
|
RST=>TB_RST,
|
|
D =>DO_READ_REG_A(I-1)
|
|
);
|
|
END GENERATE DFF_OTHERS;
|
|
END GENERATE BEGIN_SHIFT_REG_A;
|
|
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
|
|
BEGIN
|
|
DFF_RIGHT: IF I=0 GENERATE
|
|
BEGIN
|
|
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
|
|
PORT MAP(
|
|
Q => DO_READ_REG_B(0),
|
|
CLK =>CLKB,
|
|
RST=>TB_RST,
|
|
D =>DO_READ_B
|
|
);
|
|
END GENERATE DFF_RIGHT;
|
|
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
|
|
BEGIN
|
|
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
|
|
PORT MAP(
|
|
Q => DO_READ_REG_B(I),
|
|
CLK =>CLKB,
|
|
RST=>TB_RST,
|
|
D =>DO_READ_REG_B(I-1)
|
|
);
|
|
END GENERATE DFF_OTHERS;
|
|
END GENERATE BEGIN_SHIFT_REG_B;
|
|
|
|
|
|
|
|
REGCEA_PROCESS: PROCESS(CLKA)
|
|
BEGIN
|
|
IF(RISING_EDGE(CLKA)) THEN
|
|
IF(TB_RST='1') THEN
|
|
DO_READ_RA <= '0';
|
|
ELSE
|
|
DO_READ_RA <= DO_READ_A;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
|
|
REGCEB_PROCESS: PROCESS(CLKB)
|
|
BEGIN
|
|
IF(RISING_EDGE(CLKB)) THEN
|
|
IF(TB_RST='1') THEN
|
|
DO_READ_RB <= '0';
|
|
ELSE
|
|
DO_READ_RB <= DO_READ_B;
|
|
END IF;
|
|
END IF;
|
|
END PROCESS;
|
|
|
|
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
|
|
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
|
|
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
|
|
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
|
|
|
|
ENA <= DO_READ_A OR DO_WRITE_A ;
|
|
ENB <= DO_READ_B OR DO_WRITE_B ;
|
|
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
|
|
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
|
|
|
|
END ARCHITECTURE;
|