mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-06-02 16:41:28 +00:00
31 lines
1.4 KiB
XML
31 lines
1.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="sim" num="172" delta="old" >Generating IP...
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'PrefetchTagRAM' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named 'PrefetchTagRAM' already exists in the project. Output products for this core may be overwritten.</arg>
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</msg>
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<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for 'PrefetchTagRAM'...</arg>
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</msg>
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<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file C:/Users/Dog/Documents/GitHub/Warp-LC/fpga/ipcore_dir/tmp/_cg/PrefetchTagRAM/doc/dist_mem_gen_v7_2_vinfo.html with file from view xilinx_documentation</arg>
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</msg>
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<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
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</msg>
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<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
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</msg>
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</messages>
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