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374d7663d3
Warp-LC/fpga/WarpLC.twr
Zane Kaminski 374d7663d3 idk
2021-10-31 15:39:28 -04:00

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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3
-timegroups -s 2 -u 1000 -n 3 -fastpaths -xml WarpLC.twx WarpLC.ncd -o
WarpLC.twr WarpLC.pcf -ucf PLL.ucf
Design file: WarpLC.ncd
Physical constraint file: WarpLC.pcf
Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report
unconstrained path report, limited to 1000 items per endpoint, 3 endpoints per path report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
information, see the TSI report. Please consult the Xilinx Command Line
Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 10.000ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 13.948ns (period - min period limit)
Period: 15.000ns
Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax))
Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0
Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0
Location pin: PLL_ADV_X0Y1.CLKOUT0
Clock network: cg/pll/clkout0
--------------------------------------------------------------------------------
Slack: 20.000ns (period - (min low pulse limit / (low pulse / period)))
Period: 30.000ns
Low pulse: 15.000ns
Low pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50)
Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
Location pin: PLL_ADV_X0Y1.CLKIN2
Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 20.000ns (period - (min high pulse limit / (high pulse / period)))
Period: 30.000ns
High pulse: 15.000ns
High pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50)
Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
Location pin: PLL_ADV_X0Y1.CLKIN2
Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP
"CPU_nSTERM" 15 ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
22 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 7.879ns.
--------------------------------------------------------------------------------
Paths for end point CPU_nSTERM (D12.PAD), 22 paths
--------------------------------------------------------------------------------
Slack (slowest paths): 7.121ns (requirement - data path)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (RAM)
Destination: CPU_nSTERM (PAD)
Requirement: 15.000ns
Data Path Delay: 7.879ns (Levels of Logic = 2)
Source Clock: FSBCLK rising at 0.000ns
Maximum Data Path at Slow Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X16Y51.AMUX Tshcko 1.081 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 7.879ns (3.711ns logic, 4.168ns route)
(47.1% logic, 52.9% route)
--------------------------------------------------------------------------------
Slack (slowest paths): 7.227ns (requirement - data path)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (RAM)
Destination: CPU_nSTERM (PAD)
Requirement: 15.000ns
Data Path Delay: 7.773ns (Levels of Logic = 2)
Source Clock: FSBCLK rising at 0.000ns
Maximum Data Path at Slow Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X16Y51.A Tshcko 1.012 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 7.773ns (3.618ns logic, 4.155ns route)
(46.5% logic, 53.5% route)
--------------------------------------------------------------------------------
Slack (slowest paths): 7.243ns (requirement - data path)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP (RAM)
Destination: CPU_nSTERM (PAD)
Requirement: 15.000ns
Data Path Delay: 7.757ns (Levels of Logic = 3)
Source Clock: FSBCLK rising at 0.000ns
Maximum Data Path at Slow Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y50.BMUX Tshcko 1.131 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 7.757ns (3.828ns logic, 3.929ns route)
(49.3% logic, 50.7% route)
--------------------------------------------------------------------------------
Hold Paths: TS_CPU_nSTERM_A = MAXDELAY FROM TIMEGRP "FSB_A" TO TIMEGRP "CPU_nSTERM" 15 ns;
--------------------------------------------------------------------------------
Paths for end point CPU_nSTERM (D12.PAD), 22 paths
--------------------------------------------------------------------------------
Delay (fastest path): 3.026ns (data path)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP (RAM)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 3.026ns (Levels of Logic = 2)
Source Clock: FSBCLK rising at 0.000ns
Minimum Data Path at Fast Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y51.AMUX Tshcko 0.490 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
SLICE_X22Y51.C6 net (fanout=1) 0.129 l2pre/n0023<18>
SLICE_X22Y51.DMUX Topcd 0.307 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 1.401 CPU_nSTERM_OBUF
D12.PAD Tioop 0.699 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 3.026ns (1.496ns logic, 1.530ns route)
(49.4% logic, 50.6% route)
--------------------------------------------------------------------------------
Delay (fastest path): 3.039ns (data path)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP (RAM)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 3.039ns (Levels of Logic = 2)
Source Clock: FSBCLK rising at 0.000ns
Minimum Data Path at Fast Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y51.B Tshcko 0.449 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
SLICE_X22Y51.B6 net (fanout=1) 0.119 l2pre/n0023<15>
SLICE_X22Y51.DMUX Topbd 0.371 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 1.401 CPU_nSTERM_OBUF
D12.PAD Tioop 0.699 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 3.039ns (1.519ns logic, 1.520ns route)
(50.0% logic, 50.0% route)
--------------------------------------------------------------------------------
Delay (fastest path): 3.074ns (data path)
Source: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP (RAM)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 3.074ns (Levels of Logic = 2)
Source Clock: FSBCLK rising at 0.000ns
Minimum Data Path at Fast Process Corner: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y51.BMUX Tshcko 0.495 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
SLICE_X22Y51.C5 net (fanout=1) 0.172 l2pre/n0023<19>
SLICE_X22Y51.DMUX Topcd 0.307 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 1.401 CPU_nSTERM_OBUF
D12.PAD Tioop 0.699 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 3.074ns (1.501ns logic, 1.573ns route)
(48.8% logic, 51.2% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout"
TS_CLKIN HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 component switching limit errors)
Minimum period is 2.666ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;
--------------------------------------------------------------------------------
Slack: 27.334ns (period - min period limit)
Period: 30.000ns
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
Physical resource: cg/pll/clkfbout_bufg/I0
Logical resource: cg/pll/clkfbout_bufg/I0
Location pin: BUFGMUX_X2Y3.I0
Clock network: cg/pll/clkfbout
--------------------------------------------------------------------------------
Slack: 27.751ns (period - min period limit)
Period: 30.000ns
Min period limit: 2.249ns (444.642MHz) (Tockper)
Physical resource: CLKFB_OUT_OBUF/CLK0
Logical resource: cg/pll/clkfbout_oddr/CK0
Location pin: OLOGIC_X1Y62.CLK0
Clock network: cg/pll/clkfb_bufg_out
--------------------------------------------------------------------------------
Slack: 27.960ns (period - min period limit)
Period: 30.000ns
Min period limit: 2.040ns (490.196MHz) (Tockper)
Physical resource: CLKFB_OUT_OBUF/CLK1
Logical resource: cg/pll/clkfbout_oddr/CK1
Location pin: OLOGIC_X1Y62.CLK1
Clock network: cg/pll/clkfb_bufg_out
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN
/ 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 3.689ns.
--------------------------------------------------------------------------------
Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y61.D1), 1 path
--------------------------------------------------------------------------------
Slack (setup path): 11.311ns (requirement - (data path - clock path skew + uncertainty))
Source: cg/CPUCLKr (FF)
Destination: cg/CPUCLK_inst (FF)
Requirement: 15.000ns
Data Path Delay: 4.087ns (Levels of Logic = 1)
Clock Path Skew: 0.514ns (1.205 - 0.691)
Source Clock: FSBCLK rising at 0.000ns
Destination Clock: FSBCLK rising at 15.000ns
Clock Uncertainty: 0.116ns
Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y61.DQ Tcko 0.525 cg/CPUCLKr
cg/CPUCLKr
SLICE_X20Y61.D6 net (fanout=3) 0.156 cg/CPUCLKr
SLICE_X20Y61.D Tilo 0.254 cg/CPUCLKr
][292_3_INV_0
OLOGIC_X1Y61.D1 net (fanout=3) 2.186 ][292_3
OLOGIC_X1Y61.CLK0 Todck 0.966 CPUCLK_OBUF
cg/CPUCLK_inst
------------------------------------------------- ---------------------------
Total 4.087ns (1.745ns logic, 2.342ns route)
(42.7% logic, 57.3% route)
--------------------------------------------------------------------------------
Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y61.D2), 1 path
--------------------------------------------------------------------------------
Slack (setup path): 11.624ns (requirement - (data path - clock path skew + uncertainty))
Source: cg/CPUCLKr (FF)
Destination: cg/CPUCLK_inst (FF)
Requirement: 15.000ns
Data Path Delay: 3.774ns (Levels of Logic = 1)
Clock Path Skew: 0.514ns (1.205 - 0.691)
Source Clock: FSBCLK rising at 0.000ns
Destination Clock: FSBCLK rising at 15.000ns
Clock Uncertainty: 0.116ns
Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y61.DQ Tcko 0.525 cg/CPUCLKr
cg/CPUCLKr
SLICE_X20Y61.D6 net (fanout=3) 0.156 cg/CPUCLKr
SLICE_X20Y61.D Tilo 0.254 cg/CPUCLKr
][292_3_INV_0
OLOGIC_X1Y61.D2 net (fanout=3) 2.008 ][292_3
OLOGIC_X1Y61.CLK0 Todck 0.831 CPUCLK_OBUF
cg/CPUCLK_inst
------------------------------------------------- ---------------------------
Total 3.774ns (1.610ns logic, 2.164ns route)
(42.7% logic, 57.3% route)
--------------------------------------------------------------------------------
Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y61.D2), 1 path
--------------------------------------------------------------------------------
Slack (setup path): 12.401ns (requirement - (data path - clock path skew + uncertainty))
Source: cg/CPUCLKr (FF)
Destination: cg/FPUCLK_inst (FF)
Requirement: 15.000ns
Data Path Delay: 2.966ns (Levels of Logic = 0)
Clock Path Skew: 0.483ns (0.800 - 0.317)
Source Clock: FSBCLK rising at 0.000ns
Destination Clock: FSBCLK rising at 15.000ns
Clock Uncertainty: 0.116ns
Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/FPUCLK_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y61.DQ Tcko 0.525 cg/CPUCLKr
cg/CPUCLKr
OLOGIC_X11Y61.D2 net (fanout=3) 1.610 cg/CPUCLKr
OLOGIC_X11Y61.CLK0 Todck 0.831 FPUCLK_OBUF
cg/FPUCLK_inst
------------------------------------------------- ---------------------------
Total 2.966ns (1.356ns logic, 1.610ns route)
(45.7% logic, 54.3% route)
--------------------------------------------------------------------------------
Hold Paths: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point cg/CPUCLKr (SLICE_X20Y61.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.458ns (requirement - (clock path skew + uncertainty - data path))
Source: cg/CPUCLKr (FF)
Destination: cg/CPUCLKr (FF)
Requirement: 0.000ns
Data Path Delay: 0.458ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: FSBCLK rising at 15.000ns
Destination Clock: FSBCLK rising at 15.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/CPUCLKr
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y61.DQ Tcko 0.234 cg/CPUCLKr
cg/CPUCLKr
SLICE_X20Y61.D6 net (fanout=3) 0.027 cg/CPUCLKr
SLICE_X20Y61.CLK Tah (-Th) -0.197 cg/CPUCLKr
][292_3_INV_0
cg/CPUCLKr
------------------------------------------------- ---------------------------
Total 0.458ns (0.431ns logic, 0.027ns route)
(94.1% logic, 5.9% route)
--------------------------------------------------------------------------------
Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y61.D1), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.665ns (requirement - (clock path skew + uncertainty - data path))
Source: cg/CPUCLKr (FF)
Destination: cg/FPUCLK_inst (FF)
Requirement: 0.000ns
Data Path Delay: 0.857ns (Levels of Logic = 0)
Clock Path Skew: 0.192ns (0.269 - 0.077)
Source Clock: FSBCLK rising at 15.000ns
Destination Clock: FSBCLK rising at 15.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/FPUCLK_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y61.DQ Tcko 0.234 cg/CPUCLKr
cg/CPUCLKr
OLOGIC_X11Y61.D1 net (fanout=3) 0.293 cg/CPUCLKr
OLOGIC_X11Y61.CLK0 Tockd (-Th) -0.330 FPUCLK_OBUF
cg/FPUCLK_inst
------------------------------------------------- ---------------------------
Total 0.857ns (0.564ns logic, 0.293ns route)
(65.8% logic, 34.2% route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ENBRDEN), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.736ns (requirement - (clock path skew + uncertainty - data path))
Source: cg/CPUCLKr (FF)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Requirement: 0.000ns
Data Path Delay: 0.736ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: FSBCLK rising at 15.000ns
Destination Clock: FSBCLK rising at 15.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: cg/CPUCLKr to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X20Y61.DQ Tcko 0.234 cg/CPUCLKr
cg/CPUCLKr
SLICE_X20Y61.D6 net (fanout=3) 0.027 cg/CPUCLKr
SLICE_X20Y61.D Tilo 0.156 cg/CPUCLKr
][292_3_INV_0
RAMB8_X1Y31.ENBRDEN net (fanout=3) 0.363 ][292_3
RAMB8_X1Y31.CLKBRDCLKTrckc_ENB (-Th) 0.044 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
------------------------------------------------- ---------------------------
Total 0.736ns (0.346ns logic, 0.390ns route)
(47.0% logic, 53.0% route)
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 11.430ns (period - min period limit)
Period: 15.000ns
Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
Location pin: RAMB8_X1Y31.CLKAWRCLK
Clock network: FSBCLK
--------------------------------------------------------------------------------
Slack: 11.430ns (period - min period limit)
Period: 15.000ns
Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK
Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK
Location pin: RAMB8_X1Y31.CLKBRDCLK
Clock network: FSBCLK
--------------------------------------------------------------------------------
Slack: 12.334ns (period - min period limit)
Period: 15.000ns
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
Physical resource: cg/pll/clkout1_buf/I0
Logical resource: cg/pll/clkout1_buf/I0
Location pin: BUFGMUX_X3Y13.I0
Clock network: cg/pll/clkout0
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Unconstrained OFFSET IN BEFORE analysis for clock "FSBCLK"
5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
Minimum allowable offset is 8.910ns.
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path
--------------------------------------------------------------------------------
Offset (setup paths): 8.910ns (data path - clock path + uncertainty)
Source: FSB_A<6> (PAD)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination Clock: FSBCLK rising at 0.000ns
Data Path Delay: 4.600ns (Levels of Logic = 1)
Clock Path Delay: -4.014ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Maximum Data Path at Slow Process Corner: FSB_A<6> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
RAMB8_X1Y31.ADDRBRDADDR9 net (fanout=13) 2.643 FSB_A_6_IBUF
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
----------------------------------------------------- ---------------------------
Total 4.600ns (1.957ns logic, 2.643ns route)
(42.5% logic, 57.5% route)
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.882 FSBCLK
------------------------------------------------- ---------------------------
Total -4.014ns (-6.437ns logic, 2.423ns route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path
--------------------------------------------------------------------------------
Offset (setup paths): 8.905ns (data path - clock path + uncertainty)
Source: FSB_A<4> (PAD)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination Clock: FSBCLK rising at 0.000ns
Data Path Delay: 4.595ns (Levels of Logic = 1)
Clock Path Delay: -4.014ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Maximum Data Path at Slow Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) 2.638 FSB_A_4_IBUF
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
----------------------------------------------------- ---------------------------
Total 4.595ns (1.957ns logic, 2.638ns route)
(42.6% logic, 57.4% route)
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.882 FSBCLK
------------------------------------------------- ---------------------------
Total -4.014ns (-6.437ns logic, 2.423ns route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path
--------------------------------------------------------------------------------
Offset (setup paths): 8.878ns (data path - clock path + uncertainty)
Source: FSB_A<5> (PAD)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination Clock: FSBCLK rising at 0.000ns
Data Path Delay: 4.568ns (Levels of Logic = 1)
Clock Path Delay: -4.014ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Maximum Data Path at Slow Process Corner: FSB_A<5> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
RAMB8_X1Y31.ADDRBRDADDR8 net (fanout=13) 2.611 FSB_A_5_IBUF
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
----------------------------------------------------- ---------------------------
Total 4.568ns (1.957ns logic, 2.611ns route)
(42.8% logic, 57.2% route)
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.882 FSBCLK
------------------------------------------------- ---------------------------
Total -4.014ns (-6.437ns logic, 2.423ns route)
--------------------------------------------------------------------------------
Hold Paths: Unconstrained OFFSET IN BEFORE analysis for clock "FSBCLK"
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path
--------------------------------------------------------------------------------
Offset (hold paths): 4.005ns (data path - clock path + uncertainty)
Source: FSB_A<4> (PAD)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination Clock: FSBCLK rising at 0.000ns
Data Path Delay: 1.886ns (Levels of Logic = 1)
Clock Path Delay: -1.823ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Minimum Data Path at Fast Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
E13.I Tiopi 0.763 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) 1.189 FSB_A_4_IBUF
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
----------------------------------------------------- ---------------------------
Total 1.886ns (0.697ns logic, 1.189ns route)
(37.0% logic, 63.0% route)
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.824 FSBCLK
------------------------------------------------- ---------------------------
Total -1.823ns (-3.351ns logic, 1.528ns route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path
--------------------------------------------------------------------------------
Offset (hold paths): 4.007ns (data path - clock path + uncertainty)
Source: FSB_A<3> (PAD)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination Clock: FSBCLK rising at 0.000ns
Data Path Delay: 1.888ns (Levels of Logic = 1)
Clock Path Delay: -1.823ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Minimum Data Path at Fast Process Corner: FSB_A<3> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
E11.I Tiopi 0.763 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
RAMB8_X1Y31.ADDRBRDADDR6 net (fanout=13) 1.191 FSB_A_3_IBUF
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
----------------------------------------------------- ---------------------------
Total 1.888ns (0.697ns logic, 1.191ns route)
(36.9% logic, 63.1% route)
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.824 FSBCLK
------------------------------------------------- ---------------------------
Total -1.823ns (-3.351ns logic, 1.528ns route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path
--------------------------------------------------------------------------------
Offset (hold paths): 4.008ns (data path - clock path + uncertainty)
Source: FSB_A<2> (PAD)
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination Clock: FSBCLK rising at 0.000ns
Data Path Delay: 1.889ns (Levels of Logic = 1)
Clock Path Delay: -1.823ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Minimum Data Path at Fast Process Corner: FSB_A<2> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
----------------------------------------------------- -------------------
B14.I Tiopi 0.763 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
RAMB8_X1Y31.ADDRBRDADDR5 net (fanout=13) 1.192 FSB_A_2_IBUF
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
----------------------------------------------------- ---------------------------
Total 1.889ns (0.697ns logic, 1.192ns route)
(36.9% logic, 63.1% route)
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 0.824 FSBCLK
------------------------------------------------- ---------------------------
Total -1.823ns (-3.351ns logic, 1.528ns route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Unconstrained OFFSET OUT AFTER analysis for clock "FSBCLK"
36 paths analyzed, 36 endpoints analyzed, 0 failing endpoints
0 timing errors detected.
Maximum allowable offset is 5.139ns.
--------------------------------------------------------------------------------
Paths for end point FSB_D<2> (C5.PAD), 1 path
--------------------------------------------------------------------------------
Offset (slowest paths): 5.139ns (clock path + data path + uncertainty)
Source: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination: FSB_D<2> (PAD)
Source Clock: FSBCLK rising at 0.000ns
Data Path Delay: 9.129ns (Levels of Logic = 1)
Clock Path Delay: -4.286ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Maximum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 1.037 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.643 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.178 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.505 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.209 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 1.466 FSBCLK
------------------------------------------------- ---------------------------
Total -4.286ns (-7.742ns logic, 3.456ns route)
Maximum Data Path at Slow Process Corner: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram to FSB_D<2>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB8_X1Y31.DOADO2 Trcko_DOA 2.100 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
C5.O net (fanout=1) 4.047 FSB_D_2_OBUF
C5.PAD Tioop 2.982 FSB_D<2>
FSB_D_2_OBUF
FSB_D<2>
------------------------------------------------- ---------------------------
Total 9.129ns (5.082ns logic, 4.047ns route)
(55.7% logic, 44.3% route)
--------------------------------------------------------------------------------
Paths for end point FSB_D<4> (A6.PAD), 1 path
--------------------------------------------------------------------------------
Offset (slowest paths): 5.039ns (clock path + data path + uncertainty)
Source: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination: FSB_D<4> (PAD)
Source Clock: FSBCLK rising at 0.000ns
Data Path Delay: 9.029ns (Levels of Logic = 1)
Clock Path Delay: -4.286ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Maximum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 1.037 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.643 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.178 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.505 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.209 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 1.466 FSBCLK
------------------------------------------------- ---------------------------
Total -4.286ns (-7.742ns logic, 3.456ns route)
Maximum Data Path at Slow Process Corner: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram to FSB_D<4>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB8_X1Y31.DOADO4 Trcko_DOA 2.100 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
A6.O net (fanout=1) 3.947 FSB_D_4_OBUF
A6.PAD Tioop 2.982 FSB_D<4>
FSB_D_4_OBUF
FSB_D<4>
------------------------------------------------- ---------------------------
Total 9.029ns (5.082ns logic, 3.947ns route)
(56.3% logic, 43.7% route)
--------------------------------------------------------------------------------
Paths for end point FSB_D<0> (A5.PAD), 1 path
--------------------------------------------------------------------------------
Offset (slowest paths): 4.996ns (clock path + data path + uncertainty)
Source: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
Destination: FSB_D<0> (PAD)
Source Clock: FSBCLK rising at 0.000ns
Data Path Delay: 8.986ns (Levels of Logic = 1)
Clock Path Delay: -4.286ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Maximum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 1.037 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.643 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.190 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.842 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -9.178 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.505 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.209 cg/pll/clkout1_buf
cg/pll/clkout1_buf
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) 1.466 FSBCLK
------------------------------------------------- ---------------------------
Total -4.286ns (-7.742ns logic, 3.456ns route)
Maximum Data Path at Slow Process Corner: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram to FSB_D<0>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB8_X1Y31.DOADO0 Trcko_DOA 2.100 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
A5.O net (fanout=1) 3.904 FSB_D_0_OBUF
A5.PAD Tioop 2.982 FSB_D<0>
FSB_D_0_OBUF
FSB_D<0>
------------------------------------------------- ---------------------------
Total 8.986ns (5.082ns logic, 3.904ns route)
(56.6% logic, 43.4% route)
--------------------------------------------------------------------------------
Fastest Paths: Unconstrained OFFSET OUT AFTER analysis for clock "FSBCLK"
--------------------------------------------------------------------------------
Paths for end point RAMCLK0 (A14.PAD), 1 path
--------------------------------------------------------------------------------
Offset (fastest paths): -0.475ns (clock path + data path - uncertainty)
Source: cg/RAMCLK0_inst (FF)
Destination: RAMCLK0 (PAD)
Source Clock: FSBCLK rising at 0.000ns
Data Path Delay: 3.331ns (Levels of Logic = 1)
Clock Path Delay: -3.510ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Minimum Clock Path at Slow Process Corner: CLKIN to cg/RAMCLK0_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
OLOGIC_X11Y62.CLK0 net (fanout=17) 1.386 FSBCLK
------------------------------------------------- ---------------------------
Total -3.510ns (-6.437ns logic, 2.927ns route)
Minimum Data Path at Slow Process Corner: cg/RAMCLK0_inst to RAMCLK0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X11Y62.OQ Tockq 1.090 RAMCLK0_OBUF
cg/RAMCLK0_inst
A14.O net (fanout=1) 0.375 RAMCLK0_OBUF
A14.PAD Tioop 1.866 RAMCLK0
RAMCLK0_OBUF
RAMCLK0
------------------------------------------------- ---------------------------
Total 3.331ns (2.956ns logic, 0.375ns route)
(88.7% logic, 11.3% route)
--------------------------------------------------------------------------------
Paths for end point RAMCLK1 (C4.PAD), 1 path
--------------------------------------------------------------------------------
Offset (fastest paths): -0.436ns (clock path + data path - uncertainty)
Source: cg/RAMCLK1_inst (FF)
Destination: RAMCLK1 (PAD)
Source Clock: FSBCLK rising at 0.000ns
Data Path Delay: 3.331ns (Levels of Logic = 1)
Clock Path Delay: -3.471ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Minimum Clock Path at Slow Process Corner: CLKIN to cg/RAMCLK1_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
OLOGIC_X1Y63.CLK0 net (fanout=17) 1.425 FSBCLK
------------------------------------------------- ---------------------------
Total -3.471ns (-6.437ns logic, 2.966ns route)
Minimum Data Path at Slow Process Corner: cg/RAMCLK1_inst to RAMCLK1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X1Y63.OQ Tockq 1.090 RAMCLK1_OBUF
cg/RAMCLK1_inst
C4.O net (fanout=1) 0.375 RAMCLK1_OBUF
C4.PAD Tioop 1.866 RAMCLK1
RAMCLK1_OBUF
RAMCLK1
------------------------------------------------- ---------------------------
Total 3.331ns (2.956ns logic, 0.375ns route)
(88.7% logic, 11.3% route)
--------------------------------------------------------------------------------
Paths for end point FPUCLK (D11.PAD), 1 path
--------------------------------------------------------------------------------
Offset (fastest paths): -0.424ns (clock path + data path - uncertainty)
Source: cg/FPUCLK_inst (FF)
Destination: FPUCLK (PAD)
Source Clock: FSBCLK rising at 0.000ns
Data Path Delay: 3.382ns (Levels of Logic = 1)
Clock Path Delay: -3.510ns (Levels of Logic = 4)
Clock Uncertainty: 0.296ns
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.221ns
Phase Error (PE): 0.182ns
Minimum Clock Path at Slow Process Corner: CLKIN to cg/FPUCLK_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
OLOGIC_X11Y61.CLK0 net (fanout=17) 1.386 FSBCLK
------------------------------------------------- ---------------------------
Total -3.510ns (-6.437ns logic, 2.927ns route)
Minimum Data Path at Slow Process Corner: cg/FPUCLK_inst to FPUCLK
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X11Y61.OQ Tockq 1.090 FPUCLK_OBUF
cg/FPUCLK_inst
D11.O net (fanout=1) 0.426 FPUCLK_OBUF
D11.PAD Tioop 1.866 FPUCLK
FPUCLK_OBUF
FPUCLK
------------------------------------------------- ---------------------------
Total 3.382ns (2.956ns logic, 0.426ns route)
(87.4% logic, 12.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Unconstrained OFFSET OUT AFTER analysis for clock
"cg/pll/clkfb_bufg_out"
2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints
0 timing errors detected.
Maximum allowable offset is 15.120ns.
--------------------------------------------------------------------------------
Paths for end point CLKFB_OUT (A4.PAD), 2 paths
--------------------------------------------------------------------------------
Offset (slowest paths): 15.120ns (clock path + data path + uncertainty)
Source: cg/pll/clkfbout_oddr (FF)
Destination: CLKFB_OUT (PAD)
Source Clock: cg/pll/clkfb_bufg_out falling at 15.000ns
Data Path Delay: 1.466ns (Levels of Logic = 1)
Clock Path Delay: -1.603ns (Levels of Logic = 4)
Clock Uncertainty: 0.257ns
Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.141ns
Phase Error (PE): 0.182ns
Maximum Clock Path at Fast Process Corner: CLKIN to cg/pll/clkfbout_oddr
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 cg/pll/clkfbout
BUFGMUX_X2Y3.O Tgi0o 0.063 cg/pll/clkfbout_bufg
cg/pll/clkfbout_bufg
OLOGIC_X1Y62.CLK1 net (fanout=2) 1.044 cg/pll/clkfb_bufg_out
------------------------------------------------- ---------------------------
Total -1.603ns (-3.351ns logic, 1.748ns route)
Maximum Data Path at Fast Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X1Y62.OQ Tockq 0.451 CLKFB_OUT_OBUF
cg/pll/clkfbout_oddr
A4.O net (fanout=1) 0.273 CLKFB_OUT_OBUF
A4.PAD Tioop 0.742 CLKFB_OUT
CLKFB_OUT_OBUF
CLKFB_OUT
------------------------------------------------- ---------------------------
Total 1.466ns (1.193ns logic, 0.273ns route)
(81.4% logic, 18.6% route)
--------------------------------------------------------------------------------
Offset (slowest paths): 0.189ns (clock path + data path + uncertainty)
Source: cg/pll/clkfbout_oddr (FF)
Destination: CLKFB_OUT (PAD)
Source Clock: cg/pll/clkfb_bufg_out rising at 0.000ns
Data Path Delay: 1.460ns (Levels of Logic = 1)
Clock Path Delay: -1.528ns (Levels of Logic = 4)
Clock Uncertainty: 0.257ns
Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.141ns
Phase Error (PE): 0.182ns
Maximum Clock Path at Fast Process Corner: CLKIN to cg/pll/clkfbout_oddr
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 cg/pll/clkfbout
BUFGMUX_X2Y3.O Tgi0o 0.063 cg/pll/clkfbout_bufg
cg/pll/clkfbout_bufg
OLOGIC_X1Y62.CLK0 net (fanout=2) 1.119 cg/pll/clkfb_bufg_out
------------------------------------------------- ---------------------------
Total -1.528ns (-3.351ns logic, 1.823ns route)
Maximum Data Path at Fast Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X1Y62.OQ Tockq 0.445 CLKFB_OUT_OBUF
cg/pll/clkfbout_oddr
A4.O net (fanout=1) 0.273 CLKFB_OUT_OBUF
A4.PAD Tioop 0.742 CLKFB_OUT
CLKFB_OUT_OBUF
CLKFB_OUT
------------------------------------------------- ---------------------------
Total 1.460ns (1.187ns logic, 0.273ns route)
(81.3% logic, 18.7% route)
--------------------------------------------------------------------------------
Fastest Paths: Unconstrained OFFSET OUT AFTER analysis for clock "cg/pll/clkfb_bufg_out"
--------------------------------------------------------------------------------
Paths for end point CLKFB_OUT (A4.PAD), 2 paths
--------------------------------------------------------------------------------
Offset (fastest paths): -0.348ns (clock path + data path - uncertainty)
Source: cg/pll/clkfbout_oddr (FF)
Destination: CLKFB_OUT (PAD)
Source Clock: cg/pll/clkfb_bufg_out rising at 0.000ns
Data Path Delay: 3.331ns (Levels of Logic = 1)
Clock Path Delay: -3.422ns (Levels of Logic = 4)
Clock Uncertainty: 0.257ns
Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.141ns
Phase Error (PE): 0.182ns
Minimum Clock Path at Slow Process Corner: CLKIN to cg/pll/clkfbout_oddr
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 cg/pll/clkfbout
BUFGMUX_X2Y3.O Tgi0o 0.197 cg/pll/clkfbout_bufg
cg/pll/clkfbout_bufg
OLOGIC_X1Y62.CLK0 net (fanout=2) 1.474 cg/pll/clkfb_bufg_out
------------------------------------------------- ---------------------------
Total -3.422ns (-6.437ns logic, 3.015ns route)
Minimum Data Path at Slow Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X1Y62.OQ Tockq 1.090 CLKFB_OUT_OBUF
cg/pll/clkfbout_oddr
A4.O net (fanout=1) 0.375 CLKFB_OUT_OBUF
A4.PAD Tioop 1.866 CLKFB_OUT
CLKFB_OUT_OBUF
CLKFB_OUT
------------------------------------------------- ---------------------------
Total 3.331ns (2.956ns logic, 0.375ns route)
(88.7% logic, 11.3% route)
--------------------------------------------------------------------------------
Offset (fastest paths): 14.592ns (clock path + data path - uncertainty)
Source: cg/pll/clkfbout_oddr (FF)
Destination: CLKFB_OUT (PAD)
Source Clock: cg/pll/clkfb_bufg_out falling at 15.000ns
Data Path Delay: 3.331ns (Levels of Logic = 1)
Clock Path Delay: -3.482ns (Levels of Logic = 4)
Clock Uncertainty: 0.257ns
Clock Uncertainty: 0.257ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.050ns
Discrete Jitter (DJ): 0.141ns
Phase Error (PE): 0.182ns
Minimum Clock Path at Slow Process Corner: CLKIN to cg/pll/clkfbout_oddr
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X2Y3.I0 net (fanout=1) 0.440 cg/pll/clkfbout
BUFGMUX_X2Y3.O Tgi0o 0.197 cg/pll/clkfbout_bufg
cg/pll/clkfbout_bufg
OLOGIC_X1Y62.CLK1 net (fanout=2) 1.414 cg/pll/clkfb_bufg_out
------------------------------------------------- ---------------------------
Total -3.482ns (-6.437ns logic, 2.955ns route)
Minimum Data Path at Slow Process Corner: cg/pll/clkfbout_oddr to CLKFB_OUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X1Y62.OQ Tockq 1.090 CLKFB_OUT_OBUF
cg/pll/clkfbout_oddr
A4.O net (fanout=1) 0.375 CLKFB_OUT_OBUF
A4.PAD Tioop 1.866 CLKFB_OUT
CLKFB_OUT_OBUF
CLKFB_OUT
------------------------------------------------- ---------------------------
Total 3.331ns (2.956ns logic, 0.375ns route)
(88.7% logic, 11.3% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: Unconstrained path analysis
188 paths analyzed, 58 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is 12.945ns.
--------------------------------------------------------------------------------
Paths for end point CPU_nSTERM (D12.PAD), 131 paths
--------------------------------------------------------------------------------
Delay (setup path): 12.945ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.945ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X16Y51.A3 net (fanout=13) 4.264 FSB_A_4_IBUF
SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.945ns (4.513ns logic, 8.432ns route)
(34.9% logic, 65.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.836ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.836ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X16Y51.A3 net (fanout=13) 4.264 FSB_A_4_IBUF
SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.836ns (4.417ns logic, 8.419ns route)
(34.4% logic, 65.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.820ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.820ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X16Y51.A1 net (fanout=13) 4.139 FSB_A_2_IBUF
SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.820ns (4.513ns logic, 8.307ns route)
(35.2% logic, 64.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.811ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.811ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X16Y51.B1 net (fanout=13) 4.312 FSB_A_2_IBUF
SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.811ns (4.513ns logic, 8.298ns route)
(35.2% logic, 64.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.711ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.711ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X16Y51.A1 net (fanout=13) 4.139 FSB_A_2_IBUF
SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.711ns (4.417ns logic, 8.294ns route)
(34.7% logic, 65.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.708ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.708ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X16Y51.A2 net (fanout=13) 4.027 FSB_A_3_IBUF
SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.708ns (4.513ns logic, 8.195ns route)
(35.5% logic, 64.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.691ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.691ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X16Y51.B1 net (fanout=13) 4.312 FSB_A_2_IBUF
SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.691ns (4.350ns logic, 8.341ns route)
(34.3% logic, 65.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.659ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.659ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X16Y51.B3 net (fanout=13) 4.160 FSB_A_4_IBUF
SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.659ns (4.513ns logic, 8.146ns route)
(35.7% logic, 64.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.599ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.599ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X16Y51.A2 net (fanout=13) 4.027 FSB_A_3_IBUF
SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.599ns (4.417ns logic, 8.182ns route)
(35.1% logic, 64.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.539ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.539ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X16Y51.B3 net (fanout=13) 4.160 FSB_A_4_IBUF
SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.539ns (4.350ns logic, 8.189ns route)
(34.7% logic, 65.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.537ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.537ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X16Y51.B2 net (fanout=13) 4.038 FSB_A_3_IBUF
SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.537ns (4.513ns logic, 8.024ns route)
(36.0% logic, 64.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.517ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.517ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y50.B1 net (fanout=13) 4.008 FSB_A_2_IBUF
SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.517ns (4.580ns logic, 7.937ns route)
(36.6% logic, 63.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.435ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.435ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X16Y51.A4 net (fanout=13) 3.754 FSB_A_5_IBUF
SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.435ns (4.513ns logic, 7.922ns route)
(36.3% logic, 63.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.417ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.417ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X16Y51.B2 net (fanout=13) 4.038 FSB_A_3_IBUF
SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.417ns (4.350ns logic, 8.067ns route)
(35.0% logic, 65.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.398ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.398ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y50.B3 net (fanout=13) 3.889 FSB_A_4_IBUF
SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.398ns (4.580ns logic, 7.818ns route)
(36.9% logic, 63.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.356ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.356ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X16Y51.A5 net (fanout=13) 3.675 FSB_A_6_IBUF
SLICE_X16Y51.AMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
SLICE_X22Y51.A1 net (fanout=1) 1.261 l2pre/n0023<14>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.356ns (4.513ns logic, 7.843ns route)
(36.5% logic, 63.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.345ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.345ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y49.A3 net (fanout=13) 4.019 FSB_A_4_IBUF
SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.345ns (4.532ns logic, 7.813ns route)
(36.7% logic, 63.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.326ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.326ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X16Y51.A4 net (fanout=13) 3.754 FSB_A_5_IBUF
SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.326ns (4.417ns logic, 7.909ns route)
(35.8% logic, 64.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.323ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.323ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X16Y51.B5 net (fanout=13) 3.824 FSB_A_6_IBUF
SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.323ns (4.513ns logic, 7.810ns route)
(36.6% logic, 63.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.274ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.274ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X16Y51.B4 net (fanout=13) 3.775 FSB_A_5_IBUF
SLICE_X16Y51.BMUX Tilo 0.326 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
SLICE_X22Y51.A3 net (fanout=1) 1.079 l2pre/n0023<12>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.274ns (4.513ns logic, 7.761ns route)
(36.8% logic, 63.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.247ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.247ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X16Y51.A5 net (fanout=13) 3.675 FSB_A_6_IBUF
SLICE_X16Y51.A Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
SLICE_X22Y51.B2 net (fanout=1) 1.248 l2pre/n0023<16>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.247ns (4.417ns logic, 7.830ns route)
(36.1% logic, 63.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.205ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.205ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y49.A1 net (fanout=13) 3.879 FSB_A_2_IBUF
SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.205ns (4.532ns logic, 7.673ns route)
(37.1% logic, 62.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.203ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.203ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X16Y51.B5 net (fanout=13) 3.824 FSB_A_6_IBUF
SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.203ns (4.350ns logic, 7.853ns route)
(35.6% logic, 64.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.173ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.173ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y50.B1 net (fanout=13) 4.008 FSB_A_2_IBUF
SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.173ns (4.508ns logic, 7.665ns route)
(37.0% logic, 63.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.154ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.154ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X16Y51.B4 net (fanout=13) 3.775 FSB_A_5_IBUF
SLICE_X16Y51.B Tilo 0.254 l2pre/n0023<11>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
SLICE_X22Y50.D1 net (fanout=1) 1.119 l2pre/n0023<11>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.154ns (4.350ns logic, 7.804ns route)
(35.8% logic, 64.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.141ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.141ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y49.B3 net (fanout=13) 4.080 FSB_A_4_IBUF
SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.141ns (4.604ns logic, 7.537ns route)
(37.9% logic, 62.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.113ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.113ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y49.B1 net (fanout=13) 4.052 FSB_A_2_IBUF
SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.113ns (4.604ns logic, 7.509ns route)
(38.0% logic, 62.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.072ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.072ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y49.A3 net (fanout=13) 4.019 FSB_A_4_IBUF
SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.072ns (4.580ns logic, 7.492ns route)
(37.9% logic, 62.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.054ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.054ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y50.B3 net (fanout=13) 3.889 FSB_A_4_IBUF
SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.054ns (4.508ns logic, 7.546ns route)
(37.4% logic, 62.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.014ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.014ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y49.A4 net (fanout=13) 3.688 FSB_A_5_IBUF
SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.014ns (4.532ns logic, 7.482ns route)
(37.7% logic, 62.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 12.007ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 12.007ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y50.B4 net (fanout=13) 3.498 FSB_A_5_IBUF
SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 12.007ns (4.580ns logic, 7.427ns route)
(38.1% logic, 61.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.943ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.943ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y49.A5 net (fanout=13) 3.617 FSB_A_6_IBUF
SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.943ns (4.532ns logic, 7.411ns route)
(37.9% logic, 62.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.932ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.932ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y49.A1 net (fanout=13) 3.879 FSB_A_2_IBUF
SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.932ns (4.580ns logic, 7.352ns route)
(38.4% logic, 61.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.927ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.927ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y49.A2 net (fanout=13) 3.601 FSB_A_3_IBUF
SLICE_X20Y49.A Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
SLICE_X22Y50.A2 net (fanout=1) 0.884 l2pre/n0023<1>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.927ns (4.532ns logic, 7.395ns route)
(38.0% logic, 62.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.926ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.926ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y50.A1 net (fanout=13) 3.835 FSB_A_2_IBUF
SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.926ns (4.457ns logic, 7.469ns route)
(37.4% logic, 62.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.919ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.919ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y50.A3 net (fanout=13) 3.828 FSB_A_4_IBUF
SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.919ns (4.457ns logic, 7.462ns route)
(37.4% logic, 62.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.901ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.901ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y50.B2 net (fanout=13) 3.392 FSB_A_3_IBUF
SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.901ns (4.580ns logic, 7.321ns route)
(38.5% logic, 61.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.900ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.900ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y50.B5 net (fanout=13) 3.391 FSB_A_6_IBUF
SLICE_X20Y50.BMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
SLICE_X22Y50.B1 net (fanout=1) 1.019 l2pre/n0023<4>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.900ns (4.580ns logic, 7.320ns route)
(38.5% logic, 61.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.900ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.900ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y49.B3 net (fanout=13) 4.080 FSB_A_4_IBUF
SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.900ns (4.532ns logic, 7.368ns route)
(38.1% logic, 61.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.872ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.872ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y49.B1 net (fanout=13) 4.052 FSB_A_2_IBUF
SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.872ns (4.532ns logic, 7.340ns route)
(38.2% logic, 61.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.749ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.749ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y49.B4 net (fanout=13) 3.688 FSB_A_5_IBUF
SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.749ns (4.604ns logic, 7.145ns route)
(39.2% logic, 60.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.741ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.741ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y49.A4 net (fanout=13) 3.688 FSB_A_5_IBUF
SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.741ns (4.580ns logic, 7.161ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.720ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.720ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y52.A1 net (fanout=13) 3.666 FSB_A_2_IBUF
SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.720ns (4.350ns logic, 7.370ns route)
(37.1% logic, 62.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.705ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.705ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y50.A1 net (fanout=13) 3.835 FSB_A_2_IBUF
SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.705ns (4.385ns logic, 7.320ns route)
(37.5% logic, 62.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.698ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.698ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y50.A3 net (fanout=13) 3.828 FSB_A_4_IBUF
SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.698ns (4.385ns logic, 7.313ns route)
(37.5% logic, 62.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.696ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.696ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y51.A1 net (fanout=13) 3.660 FSB_A_2_IBUF
SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.696ns (4.417ns logic, 7.279ns route)
(37.8% logic, 62.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.673ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.673ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y49.B2 net (fanout=13) 3.612 FSB_A_3_IBUF
SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.673ns (4.604ns logic, 7.069ns route)
(39.4% logic, 60.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.670ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.670ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y52.A3 net (fanout=13) 3.616 FSB_A_4_IBUF
SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.670ns (4.350ns logic, 7.320ns route)
(37.3% logic, 62.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.670ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.670ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y49.A5 net (fanout=13) 3.617 FSB_A_6_IBUF
SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.670ns (4.580ns logic, 7.090ns route)
(39.2% logic, 60.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.668ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.668ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y51.A3 net (fanout=13) 3.632 FSB_A_4_IBUF
SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.668ns (4.417ns logic, 7.251ns route)
(37.9% logic, 62.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.663ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.663ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y50.B4 net (fanout=13) 3.498 FSB_A_5_IBUF
SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.663ns (4.508ns logic, 7.155ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.654ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.654ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y49.A2 net (fanout=13) 3.601 FSB_A_3_IBUF
SLICE_X20Y49.AMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
SLICE_X22Y50.B4 net (fanout=1) 0.563 l2pre/n0023<5>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.654ns (4.580ns logic, 7.074ns route)
(39.3% logic, 60.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.642ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.642ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y49.B5 net (fanout=13) 3.581 FSB_A_6_IBUF
SLICE_X20Y49.BMUX Tilo 0.326 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
SLICE_X22Y50.A4 net (fanout=1) 0.547 l2pre/n0023<0>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.642ns (4.604ns logic, 7.038ns route)
(39.5% logic, 60.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.633ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.633ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y52.A1 net (fanout=13) 3.666 FSB_A_2_IBUF
SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.633ns (4.513ns logic, 7.120ns route)
(38.8% logic, 61.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.589ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.589ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y50.A4 net (fanout=13) 3.498 FSB_A_5_IBUF
SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.589ns (4.457ns logic, 7.132ns route)
(38.5% logic, 61.5% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.583ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.583ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y52.A3 net (fanout=13) 3.616 FSB_A_4_IBUF
SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.583ns (4.513ns logic, 7.070ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.560ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.560ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y51.B1 net (fanout=13) 3.833 FSB_A_2_IBUF
SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.560ns (4.366ns logic, 7.194ns route)
(37.8% logic, 62.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.557ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.557ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y50.B2 net (fanout=13) 3.392 FSB_A_3_IBUF
SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.557ns (4.508ns logic, 7.049ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.556ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.556ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y50.B5 net (fanout=13) 3.391 FSB_A_6_IBUF
SLICE_X20Y50.B Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
SLICE_X22Y50.B2 net (fanout=1) 0.747 l2pre/n0023<3>
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.556ns (4.508ns logic, 7.048ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.553ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.553ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y52.B3 net (fanout=13) 3.496 FSB_A_4_IBUF
SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.553ns (4.422ns logic, 7.131ns route)
(38.3% logic, 61.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.518ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.518ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y50.A5 net (fanout=13) 3.427 FSB_A_6_IBUF
SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.518ns (4.457ns logic, 7.061ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.508ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.508ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y49.B4 net (fanout=13) 3.688 FSB_A_5_IBUF
SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.508ns (4.532ns logic, 6.976ns route)
(39.4% logic, 60.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.504ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.504ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y51.B1 net (fanout=13) 3.833 FSB_A_2_IBUF
SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.504ns (4.417ns logic, 7.087ns route)
(38.4% logic, 61.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.472ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.472ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y50.A2 net (fanout=13) 3.381 FSB_A_3_IBUF
SLICE_X20Y50.AMUX Tilo 0.326 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
SLICE_X22Y50.C2 net (fanout=1) 0.724 l2pre/n0023<6>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.472ns (4.457ns logic, 7.015ns route)
(38.9% logic, 61.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.454ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.454ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y52.B1 net (fanout=13) 3.397 FSB_A_2_IBUF
SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.454ns (4.422ns logic, 7.032ns route)
(38.6% logic, 61.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.435ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.435ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y52.B3 net (fanout=13) 3.496 FSB_A_4_IBUF
SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.435ns (4.385ns logic, 7.050ns route)
(38.3% logic, 61.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.432ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.432ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y49.B2 net (fanout=13) 3.612 FSB_A_3_IBUF
SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.432ns (4.532ns logic, 6.900ns route)
(39.6% logic, 60.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.424ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.424ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y52.B2 net (fanout=13) 3.367 FSB_A_3_IBUF
SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.424ns (4.422ns logic, 7.002ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.420ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.420ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y51.B3 net (fanout=13) 3.693 FSB_A_4_IBUF
SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.420ns (4.366ns logic, 7.054ns route)
(38.2% logic, 61.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.418ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.418ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y51.A2 net (fanout=13) 3.382 FSB_A_3_IBUF
SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.418ns (4.417ns logic, 7.001ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.410ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.410ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y52.A2 net (fanout=13) 3.356 FSB_A_3_IBUF
SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.410ns (4.350ns logic, 7.060ns route)
(38.1% logic, 61.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.401ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.401ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y49.B5 net (fanout=13) 3.581 FSB_A_6_IBUF
SLICE_X20Y49.B Tilo 0.254 l2pre/n0023<2>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
SLICE_X22Y50.A6 net (fanout=1) 0.378 l2pre/n0023<2>
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.401ns (4.532ns logic, 6.869ns route)
(39.8% logic, 60.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.398ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.398ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y53.B4 net (fanout=13) 3.374 FSB_A_4_IBUF
SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.398ns (4.294ns logic, 7.104ns route)
(37.7% logic, 62.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.368ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.368ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y50.A4 net (fanout=13) 3.498 FSB_A_5_IBUF
SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.368ns (4.385ns logic, 6.983ns route)
(38.6% logic, 61.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.364ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.364ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y51.B3 net (fanout=13) 3.693 FSB_A_4_IBUF
SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.364ns (4.417ns logic, 6.947ns route)
(38.9% logic, 61.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.337ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.337ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y51.A4 net (fanout=13) 3.301 FSB_A_5_IBUF
SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.337ns (4.417ns logic, 6.920ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.336ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.336ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y52.B1 net (fanout=13) 3.397 FSB_A_2_IBUF
SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.336ns (4.385ns logic, 6.951ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.323ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.323ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y52.A2 net (fanout=13) 3.356 FSB_A_3_IBUF
SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.323ns (4.513ns logic, 6.810ns route)
(39.9% logic, 60.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.306ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.306ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y52.B2 net (fanout=13) 3.367 FSB_A_3_IBUF
SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.306ns (4.385ns logic, 6.921ns route)
(38.8% logic, 61.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.304ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.304ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y51.A1 net (fanout=13) 3.660 FSB_A_2_IBUF
SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.304ns (4.366ns logic, 6.938ns route)
(38.6% logic, 61.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.297ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.297ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y50.A5 net (fanout=13) 3.427 FSB_A_6_IBUF
SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.297ns (4.385ns logic, 6.912ns route)
(38.8% logic, 61.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.276ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.276ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y51.A3 net (fanout=13) 3.632 FSB_A_4_IBUF
SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.276ns (4.366ns logic, 6.910ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.266ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.266ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y51.A5 net (fanout=13) 3.230 FSB_A_6_IBUF
SLICE_X20Y51.A Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
SLICE_X22Y51.B4 net (fanout=1) 0.712 l2pre/n0023<17>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.266ns (4.417ns logic, 6.849ns route)
(39.2% logic, 60.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.251ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.251ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y50.A2 net (fanout=13) 3.381 FSB_A_3_IBUF
SLICE_X20Y50.A Tilo 0.254 l2pre/n0023<3>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
SLICE_X22Y50.C4 net (fanout=1) 0.575 l2pre/n0023<8>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.251ns (4.385ns logic, 6.866ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.245ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.245ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y53.B2 net (fanout=13) 3.221 FSB_A_2_IBUF
SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.245ns (4.294ns logic, 6.951ns route)
(38.2% logic, 61.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.209ns (data path)
Source: FSB_A<4> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.209ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<4> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E13.I Tiopi 1.557 FSB_A<4>
FSB_A<4>
FSB_A_4_IBUF
ProtoComp0.IMUX.22
SLICE_X20Y53.A4 net (fanout=13) 3.374 FSB_A_4_IBUF
SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21>
SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF
l2pre/n0023<21>_rt
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.209ns (4.259ns logic, 6.950ns route)
(38.0% logic, 62.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.159ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.159ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y52.A4 net (fanout=13) 3.105 FSB_A_5_IBUF
SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.159ns (4.350ns logic, 6.809ns route)
(39.0% logic, 61.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.128ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.128ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y52.B4 net (fanout=13) 3.071 FSB_A_5_IBUF
SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.128ns (4.422ns logic, 6.706ns route)
(39.7% logic, 60.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.120ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.120ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y51.B2 net (fanout=13) 3.393 FSB_A_3_IBUF
SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.120ns (4.366ns logic, 6.754ns route)
(39.3% logic, 60.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.092ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.092ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y53.B3 net (fanout=13) 3.068 FSB_A_3_IBUF
SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.092ns (4.294ns logic, 6.798ns route)
(38.7% logic, 61.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.081ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.081ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y52.A5 net (fanout=13) 3.027 FSB_A_6_IBUF
SLICE_X20Y52.A Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
SLICE_X22Y50.D3 net (fanout=1) 0.794 l2pre/n0023<10>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.081ns (4.350ns logic, 6.731ns route)
(39.3% logic, 60.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.072ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.072ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y52.A4 net (fanout=13) 3.105 FSB_A_5_IBUF
SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.072ns (4.513ns logic, 6.559ns route)
(40.8% logic, 59.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.064ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.064ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y51.B2 net (fanout=13) 3.393 FSB_A_3_IBUF
SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.064ns (4.417ns logic, 6.647ns route)
(39.9% logic, 60.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.045ns (data path)
Source: FSB_A<2> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.045ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<2> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B14.I Tiopi 1.557 FSB_A<2>
FSB_A<2>
FSB_A_2_IBUF
ProtoComp0.IMUX.20
SLICE_X20Y53.A2 net (fanout=13) 3.210 FSB_A_2_IBUF
SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21>
SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF
l2pre/n0023<21>_rt
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.045ns (4.259ns logic, 6.786ns route)
(38.6% logic, 61.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.028ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.028ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y51.B4 net (fanout=13) 3.301 FSB_A_5_IBUF
SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.028ns (4.366ns logic, 6.662ns route)
(39.6% logic, 60.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.026ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.026ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y51.A2 net (fanout=13) 3.382 FSB_A_3_IBUF
SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.026ns (4.366ns logic, 6.660ns route)
(39.6% logic, 60.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.019ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.019ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y52.B5 net (fanout=13) 2.962 FSB_A_6_IBUF
SLICE_X20Y52.BMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
SLICE_X22Y50.D4 net (fanout=1) 0.725 l2pre/n0023<9>
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.019ns (4.422ns logic, 6.597ns route)
(40.1% logic, 59.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 11.010ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 11.010ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y52.B4 net (fanout=13) 3.071 FSB_A_5_IBUF
SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 11.010ns (4.385ns logic, 6.625ns route)
(39.8% logic, 60.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.994ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.994ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y52.A5 net (fanout=13) 3.027 FSB_A_6_IBUF
SLICE_X20Y52.AMUX Tilo 0.326 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
SLICE_X22Y51.A4 net (fanout=1) 0.547 l2pre/n0023<13>
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.994ns (4.513ns logic, 6.481ns route)
(41.0% logic, 59.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.972ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.972ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y51.B4 net (fanout=13) 3.301 FSB_A_5_IBUF
SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.972ns (4.417ns logic, 6.555ns route)
(40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.945ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.945ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y51.A4 net (fanout=13) 3.301 FSB_A_5_IBUF
SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.945ns (4.366ns logic, 6.579ns route)
(39.9% logic, 60.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.921ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.921ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y51.B5 net (fanout=13) 3.194 FSB_A_6_IBUF
SLICE_X20Y51.BMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
SLICE_X22Y51.C5 net (fanout=1) 0.454 l2pre/n0023<19>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.921ns (4.366ns logic, 6.555ns route)
(40.0% logic, 60.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.901ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.901ns (Levels of Logic = 5)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y52.B5 net (fanout=13) 2.962 FSB_A_6_IBUF
SLICE_X20Y52.B Tilo 0.254 l2pre/n0023<7>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
SLICE_X22Y50.C5 net (fanout=1) 0.644 l2pre/n0023<7>
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.901ns (4.385ns logic, 6.516ns route)
(40.2% logic, 59.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.874ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.874ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y51.A5 net (fanout=13) 3.230 FSB_A_6_IBUF
SLICE_X20Y51.AMUX Tilo 0.326 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
SLICE_X22Y51.C6 net (fanout=1) 0.371 l2pre/n0023<18>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.874ns (4.366ns logic, 6.508ns route)
(40.2% logic, 59.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.865ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.865ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y51.B5 net (fanout=13) 3.194 FSB_A_6_IBUF
SLICE_X20Y51.B Tilo 0.254 l2pre/n0023<15>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
SLICE_X22Y51.B6 net (fanout=1) 0.347 l2pre/n0023<15>
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.865ns (4.417ns logic, 6.448ns route)
(40.7% logic, 59.3% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.842ns (data path)
Source: FSB_A<3> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.842ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<3> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E11.I Tiopi 1.557 FSB_A<3>
FSB_A<3>
FSB_A_3_IBUF
ProtoComp0.IMUX.21
SLICE_X20Y53.A3 net (fanout=13) 3.007 FSB_A_3_IBUF
SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21>
SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF
l2pre/n0023<21>_rt
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.842ns (4.259ns logic, 6.583ns route)
(39.3% logic, 60.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.832ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.832ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y53.B5 net (fanout=13) 2.808 FSB_A_5_IBUF
SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.832ns (4.294ns logic, 6.538ns route)
(39.6% logic, 60.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.748ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.748ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y53.B6 net (fanout=13) 2.724 FSB_A_6_IBUF
SLICE_X20Y53.B Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
SLICE_X22Y51.C4 net (fanout=1) 0.823 l2pre/n0023<20>
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.748ns (4.294ns logic, 6.454ns route)
(40.0% logic, 60.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.679ns (data path)
Source: FSB_A<5> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.679ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<5> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E12.I Tiopi 1.557 FSB_A<5>
FSB_A<5>
FSB_A_5_IBUF
ProtoComp0.IMUX.23
SLICE_X20Y53.A5 net (fanout=13) 2.844 FSB_A_5_IBUF
SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21>
SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF
l2pre/n0023<21>_rt
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.679ns (4.259ns logic, 6.420ns route)
(39.9% logic, 60.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.629ns (data path)
Source: FSB_A<24> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.629ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<24> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
G12.I Tiopi 1.557 FSB_A<24>
FSB_A<24>
FSB_A_24_IBUF
ProtoComp0.IMUX.13
SLICE_X22Y51.B1 net (fanout=1) 3.559 FSB_A_24_IBUF
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.629ns (4.163ns logic, 6.466ns route)
(39.2% logic, 60.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.559ns (data path)
Source: FSB_A<6> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.559ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<6> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B15.I Tiopi 1.557 FSB_A<6>
FSB_A<6>
FSB_A_6_IBUF
ProtoComp0.IMUX.24
SLICE_X20Y53.A6 net (fanout=13) 2.724 FSB_A_6_IBUF
SLICE_X20Y53.A Tilo 0.254 l2pre/n0023<20>
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
SLICE_X22Y51.D5 net (fanout=1) 0.669 l2pre/n0023<21>
SLICE_X22Y51.DMUX Topdd 0.466 CPU_nSTERM_OBUF
l2pre/n0023<21>_rt
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.559ns (4.259ns logic, 6.300ns route)
(40.3% logic, 59.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.397ns (data path)
Source: FSB_A<26> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.397ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<26> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
H13.I Tiopi 1.557 FSB_A<26>
FSB_A<26>
FSB_A_26_IBUF
ProtoComp0.IMUX.17
SLICE_X22Y51.C3 net (fanout=1) 3.450 FSB_A_26_IBUF
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.397ns (4.040ns logic, 6.357ns route)
(38.9% logic, 61.1% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.386ns (data path)
Source: FSB_A<15> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.386ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<15> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
G14.I Tiopi 1.557 FSB_A<15>
FSB_A<15>
FSB_A_15_IBUF
ProtoComp0.IMUX.10
SLICE_X22Y50.C1 net (fanout=1) 3.345 FSB_A_15_IBUF
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.386ns (4.131ns logic, 6.255ns route)
(39.8% logic, 60.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.342ns (data path)
Source: FSB_A<18> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.342ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<18> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
H16.I Tiopi 1.557 FSB_A<18>
FSB_A<18>
FSB_A_18_IBUF
ProtoComp0.IMUX.16
SLICE_X22Y50.D2 net (fanout=1) 3.336 FSB_A_18_IBUF
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.342ns (4.096ns logic, 6.246ns route)
(39.6% logic, 60.4% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.341ns (data path)
Source: FSB_A<7> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.341ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<7> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
B16.I Tiopi 1.557 FSB_A<7>
FSB_A<7>
FSB_A_7_IBUF
ProtoComp0.IMUX.25
SLICE_X22Y50.A1 net (fanout=1) 3.153 FSB_A_7_IBUF
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.341ns (4.278ns logic, 6.063ns route)
(41.4% logic, 58.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.331ns (data path)
Source: FSB_A<27> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.331ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<27> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
H14.I Tiopi 1.557 FSB_A<27>
FSB_A<27>
FSB_A_27_IBUF
ProtoComp0.IMUX.19
SLICE_X22Y51.C1 net (fanout=1) 3.384 FSB_A_27_IBUF
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.331ns (4.040ns logic, 6.291ns route)
(39.1% logic, 60.9% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.285ns (data path)
Source: FSB_A<25> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.285ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<25> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
H11.I Tiopi 1.557 FSB_A<25>
FSB_A<25>
FSB_A_25_IBUF
ProtoComp0.IMUX.15
SLICE_X22Y51.C2 net (fanout=1) 3.338 FSB_A_25_IBUF
SLICE_X22Y51.DMUX Topcd 0.501 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<6>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.285ns (4.040ns logic, 6.245ns route)
(39.3% logic, 60.7% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.186ns (data path)
Source: FSB_A<17> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.186ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<17> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
H15.I Tiopi 1.557 FSB_A<17>
FSB_A<17>
FSB_A_17_IBUF
ProtoComp0.IMUX.14
SLICE_X22Y50.D6 net (fanout=1) 3.180 FSB_A_17_IBUF
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.186ns (4.096ns logic, 6.090ns route)
(40.2% logic, 59.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.091ns (data path)
Source: FSB_A<8> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.091ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<8> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
F12.I Tiopi 1.557 FSB_A<8>
FSB_A<8>
FSB_A_8_IBUF
ProtoComp0.IMUX.26
SLICE_X22Y50.A3 net (fanout=1) 2.903 FSB_A_8_IBUF
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.091ns (4.278ns logic, 5.813ns route)
(42.4% logic, 57.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 10.036ns (data path)
Source: FSB_A<16> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 10.036ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<16> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
G16.I Tiopi 1.557 FSB_A<16>
FSB_A<16>
FSB_A_16_IBUF
ProtoComp0.IMUX.12
SLICE_X22Y50.D5 net (fanout=1) 3.030 FSB_A_16_IBUF
SLICE_X22Y50.COUT Topcyd 0.290 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 10.036ns (4.096ns logic, 5.940ns route)
(40.8% logic, 59.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.996ns (data path)
Source: FSB_A<9> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.996ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<9> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
G11.I Tiopi 1.557 FSB_A<9>
FSB_A<9>
FSB_A_9_IBUF
ProtoComp0.IMUX.27
SLICE_X22Y50.A5 net (fanout=1) 2.808 FSB_A_9_IBUF
SLICE_X22Y50.COUT Topcya 0.472 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<0>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.996ns (4.278ns logic, 5.718ns route)
(42.8% logic, 57.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.938ns (data path)
Source: FSB_A<11> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.938ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<11> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D16.I Tiopi 1.557 FSB_A<11>
FSB_A<11>
FSB_A_11_IBUF
ProtoComp0.IMUX.2
SLICE_X22Y50.B3 net (fanout=1) 2.774 FSB_A_11_IBUF
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.938ns (4.254ns logic, 5.684ns route)
(42.8% logic, 57.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.929ns (data path)
Source: FSB_A<10> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.929ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<10> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
D14.I Tiopi 1.557 FSB_A<10>
FSB_A<10>
FSB_A_10_IBUF
ProtoComp0.IMUX.1
SLICE_X22Y50.B5 net (fanout=1) 2.765 FSB_A_10_IBUF
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.929ns (4.254ns logic, 5.675ns route)
(42.8% logic, 57.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.879ns (data path)
Source: FSB_A<20> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.879ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<20> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C16.I Tiopi 1.557 FSB_A<20>
FSB_A<20>
FSB_A_20_IBUF
ProtoComp0.IMUX.4
SLICE_X22Y51.A2 net (fanout=1) 2.785 FSB_A_20_IBUF
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.879ns (4.187ns logic, 5.692ns route)
(42.4% logic, 57.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.750ns (data path)
Source: FSB_A<14> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.750ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<14> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
C15.I Tiopi 1.557 FSB_A<14>
FSB_A<14>
FSB_A_14_IBUF
ProtoComp0.IMUX.8
SLICE_X22Y50.C3 net (fanout=1) 2.709 FSB_A_14_IBUF
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.750ns (4.131ns logic, 5.619ns route)
(42.4% logic, 57.6% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.717ns (data path)
Source: FSB_A<23> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.717ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<23> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
F15.I Tiopi 1.557 FSB_A<23>
FSB_A<23>
FSB_A_23_IBUF
ProtoComp0.IMUX.11
SLICE_X22Y51.B3 net (fanout=1) 2.647 FSB_A_23_IBUF
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.717ns (4.163ns logic, 5.554ns route)
(42.8% logic, 57.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.634ns (data path)
Source: FSB_A<12> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.634ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<12> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
F13.I Tiopi 1.557 FSB_A<12>
FSB_A<12>
FSB_A_12_IBUF
ProtoComp0.IMUX.3
SLICE_X22Y50.B6 net (fanout=1) 2.470 FSB_A_12_IBUF
SLICE_X22Y50.COUT Topcyb 0.448 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<1>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.634ns (4.254ns logic, 5.380ns route)
(44.2% logic, 55.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.596ns (data path)
Source: FSB_A<13> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.596ns (Levels of Logic = 4)
Maximum Data Path at Slow Process Corner: FSB_A<13> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
F14.I Tiopi 1.557 FSB_A<13>
FSB_A<13>
FSB_A_13_IBUF
ProtoComp0.IMUX.6
SLICE_X22Y50.C6 net (fanout=1) 2.555 FSB_A_13_IBUF
SLICE_X22Y50.COUT Topcyc 0.325 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<2>
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.CIN net (fanout=1) 0.003 l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_cy<3>
SLICE_X22Y51.DMUX Tcind 0.267 CPU_nSTERM_OBUF
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.596ns (4.131ns logic, 5.465ns route)
(43.0% logic, 57.0% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.567ns (data path)
Source: FSB_A<21> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.567ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<21> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E15.I Tiopi 1.557 FSB_A<21>
FSB_A<21>
FSB_A_21_IBUF
ProtoComp0.IMUX.7
SLICE_X22Y51.A5 net (fanout=1) 2.473 FSB_A_21_IBUF
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.567ns (4.187ns logic, 5.380ns route)
(43.8% logic, 56.2% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.409ns (data path)
Source: FSB_A<22> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.409ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<22> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
E16.I Tiopi 1.557 FSB_A<22>
FSB_A<22>
FSB_A_22_IBUF
ProtoComp0.IMUX.9
SLICE_X22Y51.B5 net (fanout=1) 2.339 FSB_A_22_IBUF
SLICE_X22Y51.DMUX Topbd 0.624 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<5>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.409ns (4.163ns logic, 5.246ns route)
(44.2% logic, 55.8% route)
--------------------------------------------------------------------------------
Delay (setup path): 9.160ns (data path)
Source: FSB_A<19> (PAD)
Destination: CPU_nSTERM (PAD)
Data Path Delay: 9.160ns (Levels of Logic = 3)
Maximum Data Path at Slow Process Corner: FSB_A<19> to CPU_nSTERM
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
F16.I Tiopi 1.557 FSB_A<19>
FSB_A<19>
FSB_A_19_IBUF
ProtoComp0.IMUX.18
SLICE_X22Y51.A6 net (fanout=1) 2.066 FSB_A_19_IBUF
SLICE_X22Y51.DMUX Topad 0.648 CPU_nSTERM_OBUF
l2pre/Mcompar_RDTag[20]_RDATag[20]_equal_5_o_lut<4>
CPU_nSTERM1_cy
D12.O net (fanout=1) 2.907 CPU_nSTERM_OBUF
D12.PAD Tioop 1.982 CPU_nSTERM
CPU_nSTERM_OBUF
CPU_nSTERM
------------------------------------------------- ---------------------------
Total 9.160ns (4.187ns logic, 4.973ns route)
(45.7% logic, 54.3% route)
--------------------------------------------------------------------------------
Paths for end point cg/pll/clkfbout_oddr (OLOGIC_X1Y62.CLK0), 1 path
--------------------------------------------------------------------------------
Delay (setup path): -1.528ns (data path)
Source: CLKIN (PAD)
Destination: cg/pll/clkfbout_oddr (FF)
Data Path Delay: -1.528ns (Levels of Logic = 4)
Maximum Data Path at Fast Process Corner: CLKIN to cg/pll/clkfbout_oddr
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKFBOUTTpllcko_CLKFBOUT -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X2Y3.I0 net (fanout=1) 0.178 cg/pll/clkfbout
BUFGMUX_X2Y3.O Tgi0o 0.063 cg/pll/clkfbout_bufg
cg/pll/clkfbout_bufg
OLOGIC_X1Y62.CLK0 net (fanout=2) 1.119 cg/pll/clkfb_bufg_out
------------------------------------------------- ---------------------------
Total -1.528ns (-3.351ns logic, 1.823ns route)
--------------------------------------------------------------------------------
Paths for end point cg/RAMCLK1_inst (OLOGIC_X1Y63.CLK0), 1 path
--------------------------------------------------------------------------------
Delay (setup path): -1.592ns (data path)
Source: CLKIN (PAD)
Destination: cg/RAMCLK1_inst (FF)
Data Path Delay: -1.592ns (Levels of Logic = 4)
Maximum Data Path at Fast Process Corner: CLKIN to cg/RAMCLK1_inst
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.367 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.230 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.296 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -3.911 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.178 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
cg/pll/clkout1_buf
OLOGIC_X1Y63.CLK0 net (fanout=17) 1.055 FSBCLK
------------------------------------------------- ---------------------------
Total -1.592ns (-3.351ns logic, 1.759ns route)
--------------------------------------------------------------------------------
Hold Paths: Unconstrained path analysis
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (SLICE_X16Y51.CLK), 1 path
--------------------------------------------------------------------------------
Delay (hold path): -4.017ns (data path)
Source: CLKIN (PAD)
Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP (RAM)
Requirement: 0.000ns
Data Path Delay: -4.017ns (Levels of Logic = 4)
Minimum Data Path at Slow Process Corner: CLKIN to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
SLICE_X16Y51.CLK net (fanout=17) 0.879 FSBCLK
------------------------------------------------- ---------------------------
Total -4.017ns (-6.437ns logic, 2.420ns route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (SLICE_X16Y51.CLK), 1 path
--------------------------------------------------------------------------------
Delay (hold path): -4.017ns (data path)
Source: CLKIN (PAD)
Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP (RAM)
Requirement: 0.000ns
Data Path Delay: -4.017ns (Levels of Logic = 4)
Minimum Data Path at Slow Process Corner: CLKIN to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
SLICE_X16Y51.CLK net (fanout=17) 0.879 FSBCLK
------------------------------------------------- ---------------------------
Total -4.017ns (-6.437ns logic, 2.420ns route)
--------------------------------------------------------------------------------
Paths for end point l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP (SLICE_X16Y51.CLK), 1 path
--------------------------------------------------------------------------------
Delay (hold path): -4.017ns (data path)
Source: CLKIN (PAD)
Destination: l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP (RAM)
Requirement: 0.000ns
Data Path Delay: -4.017ns (Levels of Logic = 4)
Minimum Data Path at Slow Process Corner: CLKIN to l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
J4.I Tiopi 0.902 CLKIN
CLKIN
cg/pll/clkin1_buf
ProtoComp0.IMUX
BUFIO2_X0Y23.I net (fanout=1) 0.368 cg/pll/clkin1
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
PLL_ADV_X0Y1.CLKIN2 net (fanout=1) 0.733 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -7.715 cg/pll/pll_base_inst/PLL_ADV
cg/pll/pll_base_inst/PLL_ADV
BUFGMUX_X3Y13.I0 net (fanout=1) 0.440 cg/pll/clkout0
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
cg/pll/clkout1_buf
SLICE_X16Y51.CLK net (fanout=17) 0.879 FSBCLK
------------------------------------------------- ---------------------------
Total -4.017ns (-6.437ns logic, 2.420ns route)
--------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_CLKIN
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_CLKIN | 30.000ns| 10.000ns| 7.378ns| 0| 0| 0| 6|
| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
| TS_cg_pll_clkout0 | 15.000ns| 3.689ns| N/A| 0| 0| 6| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock CLKIN
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
FSB_A<2> | 8.756(R)| SLOW | -3.416(R)| FAST |FSBCLK | 0.000|
FSB_A<3> | 8.745(R)| SLOW | -3.415(R)| FAST |FSBCLK | 0.000|
FSB_A<4> | 8.905(R)| SLOW | -3.413(R)| FAST |FSBCLK | 0.000|
FSB_A<5> | 8.878(R)| SLOW | -3.447(R)| FAST |FSBCLK | 0.000|
FSB_A<6> | 8.910(R)| SLOW | -3.417(R)| FAST |FSBCLK | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
Clock CLKIN to Pad
------------+-----------------+------------+-----------------+------------+---------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+---------------------+--------+
CLKFB_OUT | 0.189(R)| FAST | -0.348(R)| SLOW |cg/pll/clkfb_bufg_out| 0.000|
| 15.120(F)| FAST | 14.592(F)| SLOW |cg/pll/clkfb_bufg_out| 15.000|
CPUCLK | 0.214(R)| FAST | -0.386(R)| SLOW |FSBCLK | 0.000|
CPU_nSTERM | 3.599(R)| SLOW | 1.294(R)| FAST |FSBCLK | 0.000|
FPUCLK | 0.176(R)| FAST | -0.424(R)| SLOW |FSBCLK | 0.000|
FSB_D<0> | 4.996(R)| SLOW | 2.943(R)| FAST |FSBCLK | 0.000|
FSB_D<1> | 4.679(R)| SLOW | 2.722(R)| FAST |FSBCLK | 0.000|
FSB_D<2> | 5.139(R)| SLOW | 2.993(R)| FAST |FSBCLK | 0.000|
FSB_D<3> | 4.796(R)| SLOW | 2.838(R)| FAST |FSBCLK | 0.000|
FSB_D<4> | 5.039(R)| SLOW | 2.943(R)| FAST |FSBCLK | 0.000|
FSB_D<5> | 4.575(R)| SLOW | 2.599(R)| FAST |FSBCLK | 0.000|
FSB_D<6> | 4.192(R)| SLOW | 2.432(R)| FAST |FSBCLK | 0.000|
FSB_D<7> | 4.413(R)| SLOW | 2.551(R)| FAST |FSBCLK | 0.000|
FSB_D<8> | 4.142(R)| SLOW | 2.382(R)| FAST |FSBCLK | 0.000|
FSB_D<9> | 4.553(R)| SLOW | 2.601(R)| FAST |FSBCLK | 0.000|
FSB_D<10> | 4.549(R)| SLOW | 2.620(R)| FAST |FSBCLK | 0.000|
FSB_D<11> | 4.191(R)| SLOW | 2.462(R)| FAST |FSBCLK | 0.000|
FSB_D<12> | 4.180(R)| SLOW | 2.447(R)| FAST |FSBCLK | 0.000|
FSB_D<13> | 4.313(R)| SLOW | 2.482(R)| FAST |FSBCLK | 0.000|
FSB_D<14> | 4.442(R)| SLOW | 2.602(R)| FAST |FSBCLK | 0.000|
FSB_D<15> | 3.945(R)| SLOW | 2.313(R)| FAST |FSBCLK | 0.000|
FSB_D<16> | 3.945(R)| SLOW | 2.313(R)| FAST |FSBCLK | 0.000|
FSB_D<17> | 3.939(R)| SLOW | 2.192(R)| FAST |FSBCLK | 0.000|
FSB_D<18> | 3.964(R)| SLOW | 2.177(R)| FAST |FSBCLK | 0.000|
FSB_D<19> | 3.713(R)| SLOW | 2.080(R)| FAST |FSBCLK | 0.000|
FSB_D<20> | 4.145(R)| SLOW | 2.333(R)| FAST |FSBCLK | 0.000|
FSB_D<21> | 3.789(R)| SLOW | 2.149(R)| FAST |FSBCLK | 0.000|
FSB_D<22> | 3.647(R)| SLOW | 2.048(R)| FAST |FSBCLK | 0.000|
FSB_D<23> | 3.508(R)| SLOW | 1.976(R)| FAST |FSBCLK | 0.000|
FSB_D<24> | 3.458(R)| SLOW | 1.926(R)| FAST |FSBCLK | 0.000|
FSB_D<25> | 3.598(R)| SLOW | 2.019(R)| FAST |FSBCLK | 0.000|
FSB_D<26> | 3.393(R)| SLOW | 1.890(R)| FAST |FSBCLK | 0.000|
FSB_D<27> | 3.678(R)| SLOW | 2.094(R)| FAST |FSBCLK | 0.000|
FSB_D<28> | 3.678(R)| SLOW | 2.094(R)| FAST |FSBCLK | 0.000|
FSB_D<29> | 3.552(R)| SLOW | 2.049(R)| FAST |FSBCLK | 0.000|
FSB_D<30> | 3.552(R)| SLOW | 2.049(R)| FAST |FSBCLK | 0.000|
FSB_D<31> | 3.621(R)| SLOW | 2.113(R)| FAST |FSBCLK | 0.000|
RAMCLK0 | 0.125(R)| FAST | -0.475(R)| SLOW |FSBCLK | 0.000|
RAMCLK1 | 0.164(R)| FAST | -0.436(R)| SLOW |FSBCLK | 0.000|
------------+-----------------+------------+-----------------+------------+---------------------+--------+
Clock to Setup on destination clock CLKIN
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLKIN | 3.689| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
FSB_A<2> |CPU_nSTERM | 12.820|
FSB_A<3> |CPU_nSTERM | 12.708|
FSB_A<4> |CPU_nSTERM | 12.945|
FSB_A<5> |CPU_nSTERM | 12.435|
FSB_A<6> |CPU_nSTERM | 12.356|
FSB_A<7> |CPU_nSTERM | 10.341|
FSB_A<8> |CPU_nSTERM | 10.091|
FSB_A<9> |CPU_nSTERM | 9.996|
FSB_A<10> |CPU_nSTERM | 9.929|
FSB_A<11> |CPU_nSTERM | 9.938|
FSB_A<12> |CPU_nSTERM | 9.634|
FSB_A<13> |CPU_nSTERM | 9.596|
FSB_A<14> |CPU_nSTERM | 9.750|
FSB_A<15> |CPU_nSTERM | 10.386|
FSB_A<16> |CPU_nSTERM | 10.036|
FSB_A<17> |CPU_nSTERM | 10.186|
FSB_A<18> |CPU_nSTERM | 10.342|
FSB_A<19> |CPU_nSTERM | 9.160|
FSB_A<20> |CPU_nSTERM | 9.879|
FSB_A<21> |CPU_nSTERM | 9.567|
FSB_A<22> |CPU_nSTERM | 9.409|
FSB_A<23> |CPU_nSTERM | 9.717|
FSB_A<24> |CPU_nSTERM | 10.629|
FSB_A<25> |CPU_nSTERM | 10.285|
FSB_A<26> |CPU_nSTERM | 10.397|
FSB_A<27> |CPU_nSTERM | 10.331|
---------------+---------------+---------+
Table of Timegroups:
-------------------
TimeGroup cg_pll_clkout0:
Blocks
cg/pll/clkout1_buf
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP
cg/CPUCLKr
Pins
cg\/RAMCLK0_inst.CK0
cg\/RAMCLK0_inst.CK1
cg\/RAMCLK1_inst.CK0
cg\/RAMCLK1_inst.CK1
cg\/FPUCLK_inst.CK0
cg\/FPUCLK_inst.CK1
cg\/CPUCLK_inst.CK0
cg\/CPUCLK_inst.CK1
l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKAWRCLK
l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKBRDCLK
TimeGroup cg_pll_clkfbout:
Blocks
cg/pll/clkfbout_bufg
Pins
cg\/pll\/clkfbout_oddr.CK0 cg\/pll\/clkfbout_oddr.CK1
TimeGroup CPU_nSTERM:
Blocks
CPU_nSTERM
TimeGroup FSB_A:
Blocks
CPU_nSTERM
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram15/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram17/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram13/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram12/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram6/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram2/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram1/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram3/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram7/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram9/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram5/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram4/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram19/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram18/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram20/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram16/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram14/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram11/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram10/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram8/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/DP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram22/SP
l2pre/Way0Tag/U0/xst_options.dist_mem_inst/gen_dp_ram.dpram_inst/Mram_ram21/SP
Pins
l2pre\/Way0Data\/U0\/xst_blk_mem_generator\/gnativebmg.native_blk_mem_gen\/valid.cstr\/ramloop[0].ram.r\/s6_noinit.ram\/SDP.WIDE_PRIM9.ram.CLKBRDCLK
TimeGroup CLKIN:
Pins
cg\/pll\/pll_base_inst\/PLL_ADV.CLKIN1 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0.DIVCLK
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 259 paths, 0 nets, and 178 connections
Design statistics:
Minimum period: 10.000ns{1} (Maximum frequency: 100.000MHz)
Maximum combinational path delay: 12.945ns
Maximum path delay from/to any node: 7.879ns
Minimum input required time before clock: 8.910ns
Maximum output delay after clock: 15.120ns
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Sun Oct 31 15:38:38 2021
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 214 MB
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