mirror of
https://github.com/garrettsworkshop/Warp-LC.git
synced 2024-06-02 16:41:28 +00:00
114 lines
2.1 KiB
Verilog
114 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06:27:24 10/29/2021
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// Design Name:
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// Module Name: WarpLC
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module WarpLC(
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CPU_nAS,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input [31:0] FSB_A,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input [1:0] FSB_SIZ,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "8" *)
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(* SLEW = "SLOW" *)
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output [31:0] FSB_D,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CPU_nSTERM,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CPUCLK,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output FPUCLK,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output RAMCLK0,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output RAMCLK1,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CLKIN,
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(* IOSTANDARD = "LVCMOS33" *)
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(* IOBDELAY = "NONE" *)
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input CLKFB_IN,
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(* IOSTANDARD = "LVCMOS33" *)
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(* DRIVE = "24" *)
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(* SLEW = "FAST" *)
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output CLKFB_OUT);
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wire FSBCLK;
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wire CPUCLKr;
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ClkGen cg (
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.CLKIN(CLKIN),
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.CLKFB_IN(CLKFB_IN),
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.CLKFB_OUT(CLKFB_OUT),
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.FSBCLK(FSBCLK),
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.CPUCLKr(CPUCLKr),
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.CPUCLK(CPUCLK),
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.FPUCLK(FPUCLK),
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.RAMCLK0(RAMCLK0),
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.RAMCLK1(RAMCLK1));
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wire [3:0] FSB_B;
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SizeDecode sd (
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.A(FSB_A[1:0]),
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.SIZ(FSB_SIZ[1:0]),
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.B(FSB_B[3:0]));
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wire L2PrefetchMatch;
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L2Prefetch l2pre (
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.CLK(FSBCLK),
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.CPUCLKr(CPUCLKr),
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.RDA(FSB_A[28:2]),
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.RDD(FSB_D[31:0]),
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.Match(L2PrefetchMatch),
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.WRA(27'b0),
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.WRD(32'b0),
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.WR(1'b0),
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.WRM(4'b0),
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.CLR(1'b0));
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assign CPU_nSTERM = ~(L2PrefetchMatch);
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endmodule
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