mirror of
https://github.com/garrettsworkshop/Warp-LC.git
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1308 lines
82 KiB
Plaintext
1308 lines
82 KiB
Plaintext
--------------------------------------------------------------------------------
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Release 14.7 Trace (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
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-n 3 -fastpaths -xml WarpLC_preroute.twx WarpLC_map.ncd -o WarpLC_preroute.twr
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WarpLC.pcf -ucf PLL.ucf
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Design file: WarpLC_map.ncd
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Physical constraint file: WarpLC.pcf
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Device,package,speed: xc6slx9,ftg256,C,-2 (PRODUCTION 1.23 2013-10-13)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<27>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<27>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<26>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<26>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<25>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<25>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<24>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<24>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<23>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<23>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<22>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<22>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<21>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<21>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<20>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<20>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<19>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<19>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<18>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<18>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<17>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<17>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<16>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<16>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<15>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<15>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<14>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<14>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<13>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<13>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<12>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<12>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<11>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<11>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<10>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<10>" OFFSET = IN 12 ns
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VALID 12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<9>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<9>" OFFSET = IN 12 ns VALID
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12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<8>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<8>" OFFSET = IN 12 ns VALID
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12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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WARNING:Timing:3175 - CLKIN does not clock data from FSB_A<7>
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WARNING:Timing:3225 - Timing constraint COMP "FSB_A<7>" OFFSET = IN 12 ns VALID
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12 ns BEFORE COMP "CLKIN"; ignored during timing analysis
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3284 - This timing report was generated using estimated delay
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information. For accurate numbers, please refer to the post Place and Route
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timing report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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================================================================================
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Timing constraint: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 component switching limit errors)
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Minimum period is 10.000ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_CLKIN = PERIOD TIMEGRP "CLKIN" 30 ns HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 13.948ns (period - min period limit)
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Period: 15.000ns
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Min period limit: 1.052ns (950.570MHz) (Tpllper_CLKOUT(Foutmax))
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Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0
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Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKOUT0
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Location pin: PLL_ADV_X0Y1.CLKOUT0
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Clock network: cg/pll/clkout0
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--------------------------------------------------------------------------------
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Slack: 20.000ns (period - (min low pulse limit / (low pulse / period)))
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Period: 30.000ns
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Low pulse: 15.000ns
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Low pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50)
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Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
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Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
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Location pin: PLL_ADV_X0Y1.CLKIN1
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Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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--------------------------------------------------------------------------------
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Slack: 20.000ns (period - (min high pulse limit / (high pulse / period)))
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Period: 30.000ns
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High pulse: 15.000ns
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High pulse limit: 5.000ns (Tdcmpw_CLKIN_25_50)
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Physical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
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Logical resource: cg/pll/pll_base_inst/PLL_ADV/CLKIN1
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Location pin: PLL_ADV_X0Y1.CLKIN1
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Clock network: cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout"
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TS_CLKIN HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 component switching limit errors)
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Minimum period is 2.666ns.
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_cg_pll_clkfbout = PERIOD TIMEGRP "cg_pll_clkfbout" TS_CLKIN HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 27.334ns (period - min period limit)
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Period: 30.000ns
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Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
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Physical resource: cg/pll/clkfbout_bufg/I0
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Logical resource: cg/pll/clkfbout_bufg/I0
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Location pin: BUFGMUX_X2Y3.I0
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Clock network: cg/pll/clkfbout
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--------------------------------------------------------------------------------
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Slack: 27.751ns (period - min period limit)
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Period: 30.000ns
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Min period limit: 2.249ns (444.642MHz) (Tockper)
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Physical resource: CLKFB_OUT_OBUF/CLK0
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Logical resource: cg/pll/clkfbout_oddr/CK0
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Location pin: OLOGIC_X1Y63.CLK0
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Clock network: cg/pll/clkfb_bufg_out
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--------------------------------------------------------------------------------
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Slack: 27.960ns (period - min period limit)
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Period: 30.000ns
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Min period limit: 2.040ns (490.196MHz) (Tockper)
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Physical resource: CLKFB_OUT_OBUF/CLK1
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Logical resource: cg/pll/clkfbout_oddr/CK1
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Location pin: OLOGIC_X1Y63.CLK1
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Clock network: cg/pll/clkfb_bufg_out
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--------------------------------------------------------------------------------
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================================================================================
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Timing constraint: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN
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/ 2 HIGH 50%;
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For more information, see Period Analysis in the Timing Closure User Guide (UG612).
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6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints
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0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
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Minimum period is 3.649ns.
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--------------------------------------------------------------------------------
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Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y62.D1), 1 path
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--------------------------------------------------------------------------------
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Slack (setup path): 11.351ns (requirement - (data path - clock path skew + uncertainty))
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Source: cg/CPUCLKr (FF)
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Destination: cg/CPUCLK_inst (FF)
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Requirement: 15.000ns
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Data Path Delay: 3.533ns (Levels of Logic = 1)
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Clock Path Skew: 0.000ns
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Source Clock: FSBCLK rising at 0.000ns
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Destination Clock: FSBCLK rising at 15.000ns
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Clock Uncertainty: 0.116ns
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Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.070ns
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Discrete Jitter (DJ): 0.221ns
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Phase Error (PE): 0.000ns
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Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X14Y63.DQ Tcko 0.476 cg/CPUCLKr
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cg/CPUCLKr
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SLICE_X14Y63.D4 net (fanout=4) e 0.491 cg/CPUCLKr
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SLICE_X14Y63.D Tilo 0.235 cg/CPUCLKr
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l2pre/CPUCLKr_INV_15_o1_INV_0
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OLOGIC_X1Y62.D1 net (fanout=3) e 1.365 l2pre/CPUCLKr_INV_15_o
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OLOGIC_X1Y62.CLK0 Todck 0.966 CPUCLK_OBUF
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cg/CPUCLK_inst
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------------------------------------------------- ---------------------------
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Total 3.533ns (1.677ns logic, 1.856ns route)
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(47.5% logic, 52.5% route)
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--------------------------------------------------------------------------------
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Paths for end point cg/CPUCLK_inst (OLOGIC_X1Y62.D2), 1 path
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--------------------------------------------------------------------------------
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Slack (setup path): 11.751ns (requirement - (data path - clock path skew + uncertainty))
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Source: cg/CPUCLKr (FF)
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Destination: cg/CPUCLK_inst (FF)
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Requirement: 15.000ns
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Data Path Delay: 3.133ns (Levels of Logic = 1)
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Clock Path Skew: 0.000ns
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Source Clock: FSBCLK rising at 0.000ns
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Destination Clock: FSBCLK rising at 15.000ns
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Clock Uncertainty: 0.116ns
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Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.070ns
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Discrete Jitter (DJ): 0.221ns
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Phase Error (PE): 0.000ns
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Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/CPUCLK_inst
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X14Y63.DQ Tcko 0.476 cg/CPUCLKr
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cg/CPUCLKr
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SLICE_X14Y63.D4 net (fanout=4) e 0.491 cg/CPUCLKr
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SLICE_X14Y63.D Tilo 0.235 cg/CPUCLKr
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l2pre/CPUCLKr_INV_15_o1_INV_0
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OLOGIC_X1Y62.D2 net (fanout=3) e 1.100 l2pre/CPUCLKr_INV_15_o
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OLOGIC_X1Y62.CLK0 Todck 0.831 CPUCLK_OBUF
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cg/CPUCLK_inst
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------------------------------------------------- ---------------------------
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Total 3.133ns (1.542ns logic, 1.591ns route)
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(49.2% logic, 50.8% route)
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--------------------------------------------------------------------------------
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Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D1), 1 path
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--------------------------------------------------------------------------------
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Slack (setup path): 12.451ns (requirement - (data path - clock path skew + uncertainty))
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Source: cg/CPUCLKr (FF)
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Destination: cg/FPUCLK_inst (FF)
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Requirement: 15.000ns
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Data Path Delay: 2.433ns (Levels of Logic = 0)
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Clock Path Skew: 0.000ns
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Source Clock: FSBCLK rising at 0.000ns
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Destination Clock: FSBCLK rising at 15.000ns
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Clock Uncertainty: 0.116ns
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Clock Uncertainty: 0.116ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.070ns
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Discrete Jitter (DJ): 0.221ns
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Phase Error (PE): 0.000ns
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Maximum Data Path at Slow Process Corner: cg/CPUCLKr to cg/FPUCLK_inst
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X14Y63.DQ Tcko 0.476 cg/CPUCLKr
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cg/CPUCLKr
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OLOGIC_X11Y63.D1 net (fanout=4) e 0.991 cg/CPUCLKr
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OLOGIC_X11Y63.CLK0 Todck 0.966 FPUCLK_OBUF
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cg/FPUCLK_inst
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------------------------------------------------- ---------------------------
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Total 2.433ns (1.442ns logic, 0.991ns route)
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(59.3% logic, 40.7% route)
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--------------------------------------------------------------------------------
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Hold Paths: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;
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--------------------------------------------------------------------------------
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Paths for end point cg/CPUCLKr (SLICE_X14Y63.SR), 1 path
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--------------------------------------------------------------------------------
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Slack (hold path): 0.577ns (requirement - (clock path skew + uncertainty - data path))
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Source: cg/CPUCLKr (FF)
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Destination: cg/CPUCLKr (FF)
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Requirement: 0.000ns
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Data Path Delay: 0.577ns (Levels of Logic = 0)
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Clock Path Skew: 0.000ns
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Source Clock: FSBCLK rising at 15.000ns
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Destination Clock: FSBCLK rising at 15.000ns
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Clock Uncertainty: 0.000ns
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Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/CPUCLKr
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X14Y63.DQ Tcko 0.200 cg/CPUCLKr
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cg/CPUCLKr
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SLICE_X14Y63.SR net (fanout=4) e 0.376 cg/CPUCLKr
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SLICE_X14Y63.CLK Tcksr (-Th) -0.001 cg/CPUCLKr
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cg/CPUCLKr
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------------------------------------------------- ---------------------------
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Total 0.577ns (0.201ns logic, 0.376ns route)
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(34.8% logic, 65.2% route)
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--------------------------------------------------------------------------------
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Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D2), 1 path
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--------------------------------------------------------------------------------
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Slack (hold path): 1.346ns (requirement - (clock path skew + uncertainty - data path))
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Source: cg/CPUCLKr (FF)
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Destination: cg/FPUCLK_inst (FF)
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Requirement: 0.000ns
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Data Path Delay: 1.346ns (Levels of Logic = 0)
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Clock Path Skew: 0.000ns
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Source Clock: FSBCLK rising at 15.000ns
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Destination Clock: FSBCLK rising at 15.000ns
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Clock Uncertainty: 0.000ns
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Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/FPUCLK_inst
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X14Y63.DQ Tcko 0.200 cg/CPUCLKr
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cg/CPUCLKr
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OLOGIC_X11Y63.D2 net (fanout=4) e 0.991 cg/CPUCLKr
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OLOGIC_X11Y63.CLK0 Tockd (-Th) -0.155 FPUCLK_OBUF
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cg/FPUCLK_inst
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------------------------------------------------- ---------------------------
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Total 1.346ns (0.355ns logic, 0.991ns route)
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(26.4% logic, 73.6% route)
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--------------------------------------------------------------------------------
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Paths for end point cg/FPUCLK_inst (OLOGIC_X11Y63.D1), 1 path
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--------------------------------------------------------------------------------
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Slack (hold path): 1.521ns (requirement - (clock path skew + uncertainty - data path))
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Source: cg/CPUCLKr (FF)
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Destination: cg/FPUCLK_inst (FF)
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Requirement: 0.000ns
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Data Path Delay: 1.521ns (Levels of Logic = 0)
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Clock Path Skew: 0.000ns
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Source Clock: FSBCLK rising at 15.000ns
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Destination Clock: FSBCLK rising at 15.000ns
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Clock Uncertainty: 0.000ns
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Minimum Data Path at Fast Process Corner: cg/CPUCLKr to cg/FPUCLK_inst
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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------------------------------------------------- -------------------
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SLICE_X14Y63.DQ Tcko 0.200 cg/CPUCLKr
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cg/CPUCLKr
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OLOGIC_X11Y63.D1 net (fanout=4) e 0.991 cg/CPUCLKr
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OLOGIC_X11Y63.CLK0 Tockd (-Th) -0.330 FPUCLK_OBUF
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cg/FPUCLK_inst
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------------------------------------------------- ---------------------------
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Total 1.521ns (0.530ns logic, 0.991ns route)
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(34.8% logic, 65.2% route)
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--------------------------------------------------------------------------------
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Component Switching Limit Checks: TS_cg_pll_clkout0 = PERIOD TIMEGRP "cg_pll_clkout0" TS_CLKIN / 2 HIGH 50%;
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--------------------------------------------------------------------------------
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Slack: 11.430ns (period - min period limit)
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Period: 15.000ns
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Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
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Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
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Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKAWRCLK
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Location pin: RAMB8_X1Y31.CLKAWRCLK
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Clock network: FSBCLK
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--------------------------------------------------------------------------------
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Slack: 11.430ns (period - min period limit)
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Period: 15.000ns
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Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
|
|
Physical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK
|
|
Logical resource: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram/CLKBRDCLK
|
|
Location pin: RAMB8_X1Y31.CLKBRDCLK
|
|
Clock network: FSBCLK
|
|
--------------------------------------------------------------------------------
|
|
Slack: 12.334ns (period - min period limit)
|
|
Period: 15.000ns
|
|
Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
|
|
Physical resource: cg/pll/clkout1_buf/I0
|
|
Logical resource: cg/pll/clkout1_buf/I0
|
|
Location pin: BUFGMUX_X3Y13.I0
|
|
Clock network: cg/pll/clkout0
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<27>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<26>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<25>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<24>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<23>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<22>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<21>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<20>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<19>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<18>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<17>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<16>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<15>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<14>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<13>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<12>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<11>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<10>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<9>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<8>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<7>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
|
|
0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 setup errors, 0 hold errors)
|
|
Minimum allowable offset is 9.606ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 2.394ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
|
Source: FSB_A<6> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 12.000ns
|
|
Data Path Delay: 4.419ns (Levels of Logic = 1)
|
|
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Maximum Data Path at Slow Process Corner: FSB_A<6> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
B15.I Tiopi 1.557 FSB_A<6>
|
|
FSB_A<6>
|
|
FSB_A_6_IBUF
|
|
ProtoComp0.IMUX.24
|
|
RAMB8_X1Y31.ADDRBRDADDR9 net (fanout=13) e 2.462 FSB_A_6_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 4.419ns (1.957ns logic, 2.462ns route)
|
|
(44.3% logic, 55.7% route)
|
|
|
|
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.902 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR9), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 5.962ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
|
Source: FSB_A<6> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 3.159ns (Levels of Logic = 1)
|
|
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Minimum Data Path at Fast Process Corner: FSB_A<6> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
B15.I Tiopi 0.763 FSB_A<6>
|
|
FSB_A<6>
|
|
FSB_A_6_IBUF
|
|
ProtoComp0.IMUX.24
|
|
RAMB8_X1Y31.ADDRBRDADDR9 net (fanout=13) e 2.462 FSB_A_6_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 3.159ns (0.697ns logic, 2.462ns route)
|
|
(22.1% logic, 77.9% route)
|
|
|
|
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.367 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 setup errors, 0 hold errors)
|
|
Minimum allowable offset is 9.777ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 2.223ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
|
Source: FSB_A<5> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 12.000ns
|
|
Data Path Delay: 4.590ns (Levels of Logic = 1)
|
|
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Maximum Data Path at Slow Process Corner: FSB_A<5> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
E12.I Tiopi 1.557 FSB_A<5>
|
|
FSB_A<5>
|
|
FSB_A_5_IBUF
|
|
ProtoComp0.IMUX.23
|
|
RAMB8_X1Y31.ADDRBRDADDR8 net (fanout=13) e 2.633 FSB_A_5_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 4.590ns (1.957ns logic, 2.633ns route)
|
|
(42.6% logic, 57.4% route)
|
|
|
|
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.902 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR8), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 6.133ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
|
Source: FSB_A<5> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 3.330ns (Levels of Logic = 1)
|
|
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Minimum Data Path at Fast Process Corner: FSB_A<5> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
E12.I Tiopi 0.763 FSB_A<5>
|
|
FSB_A<5>
|
|
FSB_A_5_IBUF
|
|
ProtoComp0.IMUX.23
|
|
RAMB8_X1Y31.ADDRBRDADDR8 net (fanout=13) e 2.633 FSB_A_5_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 3.330ns (0.697ns logic, 2.633ns route)
|
|
(20.9% logic, 79.1% route)
|
|
|
|
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.367 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 setup errors, 0 hold errors)
|
|
Minimum allowable offset is 9.445ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 2.555ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
|
Source: FSB_A<4> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 12.000ns
|
|
Data Path Delay: 4.258ns (Levels of Logic = 1)
|
|
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Maximum Data Path at Slow Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
E13.I Tiopi 1.557 FSB_A<4>
|
|
FSB_A<4>
|
|
FSB_A_4_IBUF
|
|
ProtoComp0.IMUX.22
|
|
RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) e 2.301 FSB_A_4_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 4.258ns (1.957ns logic, 2.301ns route)
|
|
(46.0% logic, 54.0% route)
|
|
|
|
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.902 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR7), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 5.801ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
|
Source: FSB_A<4> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 2.998ns (Levels of Logic = 1)
|
|
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Minimum Data Path at Fast Process Corner: FSB_A<4> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
E13.I Tiopi 0.763 FSB_A<4>
|
|
FSB_A<4>
|
|
FSB_A_4_IBUF
|
|
ProtoComp0.IMUX.22
|
|
RAMB8_X1Y31.ADDRBRDADDR7 net (fanout=13) e 2.301 FSB_A_4_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 2.998ns (0.697ns logic, 2.301ns route)
|
|
(23.2% logic, 76.8% route)
|
|
|
|
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.367 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 setup errors, 0 hold errors)
|
|
Minimum allowable offset is 9.381ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 2.619ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
|
Source: FSB_A<3> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 12.000ns
|
|
Data Path Delay: 4.194ns (Levels of Logic = 1)
|
|
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Maximum Data Path at Slow Process Corner: FSB_A<3> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
D12.I Tiopi 1.557 FSB_A<3>
|
|
FSB_A<3>
|
|
FSB_A_3_IBUF
|
|
ProtoComp0.IMUX.21
|
|
RAMB8_X1Y31.ADDRBRDADDR6 net (fanout=13) e 2.237 FSB_A_3_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 4.194ns (1.957ns logic, 2.237ns route)
|
|
(46.7% logic, 53.3% route)
|
|
|
|
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.902 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR6), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 5.737ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
|
Source: FSB_A<3> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 2.934ns (Levels of Logic = 1)
|
|
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Minimum Data Path at Fast Process Corner: FSB_A<3> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
D12.I Tiopi 0.763 FSB_A<3>
|
|
FSB_A<3>
|
|
FSB_A_3_IBUF
|
|
ProtoComp0.IMUX.21
|
|
RAMB8_X1Y31.ADDRBRDADDR6 net (fanout=13) e 2.237 FSB_A_3_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 2.934ns (0.697ns logic, 2.237ns route)
|
|
(23.8% logic, 76.2% route)
|
|
|
|
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.367 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
================================================================================
|
|
Timing constraint: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP
|
|
"CLKIN";
|
|
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).
|
|
|
|
1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
|
|
0 timing errors detected. (0 setup errors, 0 hold errors)
|
|
Minimum allowable offset is 9.717ns.
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (setup path): 2.283ns (requirement - (data path - clock path - clock arrival + uncertainty))
|
|
Source: FSB_A<2> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 12.000ns
|
|
Data Path Delay: 4.530ns (Levels of Logic = 1)
|
|
Clock Path Delay: -4.891ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Maximum Data Path at Slow Process Corner: FSB_A<2> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
D11.I Tiopi 1.557 FSB_A<2>
|
|
FSB_A<2>
|
|
FSB_A_2_IBUF
|
|
ProtoComp0.IMUX.20
|
|
RAMB8_X1Y31.ADDRBRDADDR5 net (fanout=13) e 2.573 FSB_A_2_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trcck_ADDRB 0.400 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 4.530ns (1.957ns logic, 2.573ns route)
|
|
(43.2% logic, 56.8% route)
|
|
|
|
Minimum Clock Path at Slow Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.902 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.179 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -8.248 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.197 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -4.891ns (-6.970ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
Hold Paths: COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
--------------------------------------------------------------------------------
|
|
|
|
Paths for end point l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAMB8_X1Y31.ADDRBRDADDR5), 1 path
|
|
--------------------------------------------------------------------------------
|
|
Slack (hold path): 6.073ns (requirement - (clock path + clock arrival + uncertainty - data path))
|
|
Source: FSB_A<2> (PAD)
|
|
Destination: l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram (RAM)
|
|
Destination Clock: FSBCLK rising at 0.000ns
|
|
Requirement: 0.000ns
|
|
Data Path Delay: 3.270ns (Levels of Logic = 1)
|
|
Clock Path Delay: -3.099ns (Levels of Logic = 4)
|
|
Clock Uncertainty: 0.296ns
|
|
|
|
Clock Uncertainty: 0.296ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.221ns
|
|
Phase Error (PE): 0.182ns
|
|
|
|
Minimum Data Path at Fast Process Corner: FSB_A<2> to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
----------------------------------------------------- -------------------
|
|
D11.I Tiopi 0.763 FSB_A<2>
|
|
FSB_A<2>
|
|
FSB_A_2_IBUF
|
|
ProtoComp0.IMUX.20
|
|
RAMB8_X1Y31.ADDRBRDADDR5 net (fanout=13) e 2.573 FSB_A_2_IBUF
|
|
RAMB8_X1Y31.CLKBRDCLK Trckc_ADDRB (-Th) 0.066 l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
----------------------------------------------------- ---------------------------
|
|
Total 3.270ns (0.697ns logic, 2.573ns route)
|
|
(21.3% logic, 78.7% route)
|
|
|
|
Maximum Clock Path at Fast Process Corner: CLKIN to l2pre/Way0Data/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.WIDE_PRIM9.ram
|
|
Location Delay type Delay(ns) Physical Resource
|
|
Logical Resource(s)
|
|
------------------------------------------------- -------------------
|
|
J4.I Tiopi 0.367 CLKIN
|
|
CLKIN
|
|
cg/pll/clkin1_buf
|
|
ProtoComp0.IMUX
|
|
BUFIO2_X0Y23.I net (fanout=1) e 0.000 cg/pll/clkin1
|
|
BUFIO2_X0Y23.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
|
|
PLL_ADV_X0Y1.CLKIN1 net (fanout=1) e 0.000 cg/pll/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
|
|
PLL_ADV_X0Y1.CLKOUT0 Tpllcko_CLK -5.738 cg/pll/pll_base_inst/PLL_ADV
|
|
cg/pll/pll_base_inst/PLL_ADV
|
|
BUFGMUX_X3Y13.I0 net (fanout=1) e 0.505 cg/pll/clkout0
|
|
BUFGMUX_X3Y13.O Tgi0o 0.063 cg/pll/clkout1_buf
|
|
cg/pll/clkout1_buf
|
|
RAMB8_X1Y31.CLKBRDCLKnet (fanout=17) e 1.574 FSBCLK
|
|
------------------------------------------------- ---------------------------
|
|
Total -3.099ns (-5.178ns logic, 2.079ns route)
|
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Derived Constraint Report
|
|
Derived Constraints for TS_CLKIN
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
| | Period | Actual Period | Timing Errors | Paths Analyzed |
|
|
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|
|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
|TS_CLKIN | 30.000ns| 10.000ns| 7.298ns| 0| 0| 0| 6|
|
|
| TS_cg_pll_clkfbout | 30.000ns| 2.666ns| N/A| 0| 0| 0| 0|
|
|
| TS_cg_pll_clkout0 | 15.000ns| 3.649ns| N/A| 0| 0| 6| 0|
|
|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|
|
|
|
All constraints were met.
|
|
|
|
|
|
Data Sheet report:
|
|
-----------------
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
Setup/Hold to clock CLKIN
|
|
------------+------------+------------+------------+------------+------------------+--------+
|
|
|Max Setup to| Process |Max Hold to | Process | | Clock |
|
|
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
|
|
------------+------------+------------+------------+------------+------------------+--------+
|
|
FSB_A<2> | 9.717(R)| SLOW | -6.073(R)| FAST |FSBCLK | 0.000|
|
|
FSB_A<3> | 9.381(R)| SLOW | -5.737(R)| FAST |FSBCLK | 0.000|
|
|
FSB_A<4> | 9.445(R)| SLOW | -5.801(R)| FAST |FSBCLK | 0.000|
|
|
FSB_A<5> | 9.777(R)| SLOW | -6.133(R)| FAST |FSBCLK | 0.000|
|
|
FSB_A<6> | 9.606(R)| SLOW | -5.962(R)| FAST |FSBCLK | 0.000|
|
|
------------+------------+------------+------------+------------+------------------+--------+
|
|
|
|
Clock to Setup on destination clock CLKIN
|
|
---------------+---------+---------+---------+---------+
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
|
---------------+---------+---------+---------+---------+
|
|
CLKIN | 3.649| | | |
|
|
---------------+---------+---------+---------+---------+
|
|
|
|
COMP "FSB_A<6>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.784;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
FSB_A<6> | 9.606(R)| SLOW | -5.962(R)| FAST | 2.394| 5.962| -1.784|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 9.606| - | -5.962| - | 2.394| 5.962| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
COMP "FSB_A<5>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.955;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
FSB_A<5> | 9.777(R)| SLOW | -6.133(R)| FAST | 2.223| 6.133| -1.955|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 9.777| - | -6.133| - | 2.223| 6.133| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
COMP "FSB_A<4>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.623;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
FSB_A<4> | 9.445(R)| SLOW | -5.801(R)| FAST | 2.555| 5.801| -1.623|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 9.445| - | -5.801| - | 2.555| 5.801| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
COMP "FSB_A<3>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.559;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
FSB_A<3> | 9.381(R)| SLOW | -5.737(R)| FAST | 2.619| 5.737| -1.559|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 9.381| - | -5.737| - | 2.619| 5.737| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
COMP "FSB_A<2>" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "CLKIN";
|
|
Worst Case Data Window 3.644; Ideal Clock Offset To Actual Clock 1.895;
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
| | Process | | Process | Setup | Hold |Source Offset|
|
|
Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
FSB_A<2> | 9.717(R)| SLOW | -6.073(R)| FAST | 2.283| 6.073| -1.895|
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
Worst Case Summary| 9.717| - | -6.073| - | 2.283| 6.073| |
|
|
------------------+------------+------------+------------+------------+---------+---------+-------------+
|
|
|
|
|
|
Timing summary:
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
|
|
|
|
Constraints cover 11 paths, 0 nets, and 24 connections
|
|
|
|
Design statistics:
|
|
Minimum period: 10.000ns{1} (Maximum frequency: 100.000MHz)
|
|
Minimum input required time before clock: 9.777ns
|
|
|
|
|
|
------------------------------------Footnotes-----------------------------------
|
|
1) The minimum period statistic assumes all single cycle delays.
|
|
|
|
Analysis completed Sun Oct 31 14:40:54 2021
|
|
--------------------------------------------------------------------------------
|
|
|
|
Trace Settings:
|
|
-------------------------
|
|
Trace Settings
|
|
|
|
Peak Memory Usage: 213 MB
|
|
|
|
|
|
|